P3C1256 HIGH SPEED 32K x 8 3.3V STATIC CMOS RAM FEATURES 3.3V Power Supply Common Data I/O High Speed (Equal Access and Cycle Times) — 12/15/20/25 ns (Commercial) — 15/20/25 ns (Industrial) Three-State Outputs Low Power Advanced CMOS Technology Single 3.3 Volts ±0.3Volts Power Supply Automatic Power Down Easy Memory Expansion Using CE and OE Inputs Packages —28-Pin TSOP and SOJ Fully TTL Compatible Inputs and Outputs DESCRIPTION The P3C1256 is a 262,144-bit high-speed CMOS static RAM organized as 32Kx8. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times. Inputs are fully TTL-compatible. The RAM operates from a single 3.3V± 0.3V tolerance power supply. The P3C1256 device provides asynchronous operation with matching access and cycle times. Memory locations are specified on address pins A0 to A14. Reading is accomplished by device selection (CE and output enabling (OE) while write enable (WE) remains HIGH. By presenting the address under these conditions, the data in the addressed memory location is presented on the data input/output pins. The input/output pins stay in the HIGH Z state when either CE or OE is HIGH or WE is LOW. Access times as fast as 12 nanoseconds permit greatly enhanced system operating speeds. CMOS is utilized to reduce power consumption to a low level. The P3C1256 is a member of a family of PACE RAM™ products offering fast access times. Package options for the P3C1256 include 28-pin TSOP and SOJ packages. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATIONS SOJ (J5) 1519B TOP VIEW See end of datasheet for TSOP pin configuration Document # SRAM122 REV B 1 Revised August 2006 P3C1256 RECOMMENDED OPERATING TEMPERATURE & SUPPLY VOLTAGE Temperature Range (Ambient) Supply Voltage Commercial (0°C to 70°C) 3.0V ≤ VCC ≤ 3.6V Industrial (-40°C to 85°C) 3.0 ≤ VCC ≤ 3.6V MAXIMUM RATINGS(1) Stresses greater than those listed can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of this data sheet. Exposure to Maximum Ratings for extended periods can adversely affect device reliability. Symbol Min Max Unit Supply Voltage with Respect to GND -0.5 7.0 V Terminal Voltage with Respect to GND (up to 7.0V) -0.5 VCC + 0.5 V TA Operating Ambient Temperature -40 85 °C STG Storage Temperature -55 125 °C IOUT Output Current into Low Outputs 25 mA ILAT Latch-up Current VCC VTERM Parameter >200 mA DC ELECTRICAL CHARACTERISTICS (Over Recommended Operating Temperature & Supply Voltage)(2) Symbol Parameter Test Conditions Min 2.4 VOH Output High Voltage (I/O0 - I/O7) IOH = –4mA, VCC = 3.0V VOL Output Low Voltage (I/O0 - I/O8) IOL = 8 mA IOL = 10 mA VIH Input High Voltage VIL Input Low Voltage ILI Input Leakage Current ILO Max Unit V 0.4 0.5 V V 2.2 VCC + 0.3 V -0.5(3) 0.8 V GND ≤ VIN ≤ VCC -5 +5 µA Output Leakage Current GND ≤ VOUT ≤ VCC CE = VCC -5 +5 µA ISB VCC Current TTL Standby Current VCC = 3.6V, IOUT = 0 mA CE = VCC 20 mA ISB1 VCC Current CMOS Standby Current VCC = 3.6V, IOUT = 0 mA CE = VCC 3 mA Document # SRAM122 REV B Page 2 of 10 P3C1256 CAPACITANCES(4) (VCC = 5.0V, TA = 25°C, f = 1.0 MHz) Symbol Parameter Test Conditions Max Unit CIN Input Capacitance VIN = 0V 10 pF COUT Output Capacitance VOUT = 0V 10 pF POWER DISSIPATION CHARACTERISTICS VS. SPEED Symbol Parameter ICC Dynamic Operating Current Temperature Test Range Conditions -12 -15 -20 -25 Unit Commercial * 110 100 95 90 mA Industrial * N/A 115 110 105 mA *Tested with outputs open and all address and data inputs changing at the maximum write-cycle rate. The device is continuously enabled for writing, i.e., CE, and WE ≤ VIL (max), OE is high. Switching inputs are 0V and 3V. AC ELECTRICAL CHARACTERISTICS - READ CYCLE (Over Recommended Operating Temperature & Supply Voltage) Symbol Parameter tRC Read Cycle Time tAA Address Access Time tAC Chip Enable Access Time Output Hold from Address Change tOH -12 Min -15 Max Min Max Min Max Min Max 25 20 15 12 -25 -20 Unit ns 12 15 20 25 ns 12 15 20 25 ns 2 2 2 2 ns 2 2 2 2 ns tLZ Chip Enable to Output in Low Z tHZ Chip Disable to Output in High Z 7 8 9 10 ns tOE Output Enable Low to Data Valid 7 9 11 12 ns tOLZ Output Enable Low to Low Z tOHZ Output Enable High to High Z tPU Chip Enable to Power Up Time tPD Chip Disable to Power Down Time Document # SRAM122 REV B 0 0 0 6 0 7 0 12 10 9 0 0 15 ns 0 20 ns ns 20 ns Page 3 of 10 P3C1256 OE CONTROLLED)(5) TIMING WAVEFORM OF READ CYCLE NO. 1 (OE TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6) TIMING WAVEFORM OF READ CYCLE NO. 3 (CE CONTROLLED)(5,7) Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability. 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with VIL and IIL not more negative than –3.0V and –100mA, respectively, are permissible for pulse widths up to 20 ns. Document # SRAM122 REV B 4. This parameter is sampled and not 100% tested. 5. WE is HIGH for READ cycle. 6. CE is LOW and OE is LOW for READ cycle. 7. ADDRESS must be valid prior to, or coincident with CE transition LOW. 8. Transition is measured ± 200 mV from steady state voltage prior to change, with loading as specified in Figure 1. This parameter is sampled and not 100% tested. 9. Read Cycle Time is measured from the last valid address to the first transitioning address. Page 4 of 10 P3C1256 AC CHARACTERISTICS—WRITE CYCLE (Over Recommended Operating Temperature & Supply Voltage) Symbol Parameter -12 Min -20 -15 Max Min Max Min -25 Max Min Max Unit tWC Write Cycle Time 12 15 20 25 ns tCW Chip Enable Time to End of Write 10 12 15 18 ns tAW Address Valid to End of Write Address Set-up Time 10 12 15 18 ns 0 0 0 0 ns tWP Write Pulse Width 9 11 15 18 ns tAH Address Hold Time 0 0 0 0 ns tDW Data Valid to End of Write 8 10 12 15 ns tDH Data Hold Time 0 0 0 0 ns tWZ Write Enable to Output in High Z tOW Output Active from End of Write tAS 7 3 8 3 10 3 11 3 ns ns WE CONTROLLED)(10,11) TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE Notes: 10. CE and WE must be LOW for WRITE cycle. 11. OE is LOW for this WRITE cycle to show tWZ and tOW. 12. If CE goes HIGH simultaneously with WE HIGH, the output remains Document # SRAM122 REV B in a high impedance state 13. Write Cycle Time is measured from the last valid address to the first transitioning address. Page 5 of 10 P3C1256 CE CONTROLLED)(10) TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE AC TEST CONDITIONS Input Pulse Levels TRUTH TABLE GND to 3.0V Mode CE OE WE I/O Power Input Rise and Fall Times 3ns Standby H X X High Z Standby Input Timing Reference Level 1.5V Standby X X High Z Standby Output Timing Reference Level 1.5V DOUT Disabled L H X H High Z Active Read L L H DOUT Active Write L X L High Z Active Output Load See Figures 1 and 2 Figure 1. Output Load Figure 2. Thevenin Equivalent * including scope and test fixture. Note: Because of the ultra-high speed of the P3C1256, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 µF high frequency capacitor is also required between VCC and ground. To avoid signal Document # SRAM122 REV B reflections, proper termination must be used; for example, a 50Ω test environment should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at the comparator input, and a 116Ω resistor must be used in series with DOUT to match 166Ω (Thevenin Resistance). Page 6 of 10 P3C1256 DATA RETENTION CHARACTERISTICS Symbol Parameter VDR VCC for Data Retention ICCDR Data Retention Current tCDR Chip Deselect to Data Retention Time tR† Operation Recovery Time Test Conditons Min Typ.* VCC = 2.0V 3.0V Max VCC = 2.0V 3.0V V 2.0 10 CE ≥ VCC –0.2V, VIN ≥ VCC –0.2V or VIN ≤ 0.2V Unit 15 600 900 µA 0 ns tRC§ ns *TA = +25°C §tRC = Read Cycle Time † This parameter is guaranteed but not tested. DATA RETENTION WAVEFORM TSOP PIN CONFIGURATION Document # SRAM122 REV B Page 7 of 10 P3C1256 ORDERING INFORMATION SELECTION GUIDE The P3C1256 is available in the following temperature, speed and package options. Speed Temperature Package Range 12 15 20 25 Commercial TSOP -12TC -15TC -20TC -25TC Plastic SOJ Industrial -12JC -15JC -20JC -25JC TSOP N/A -15TI -20TI -25TI Plastic SOJ N/A -15JI -20JI -25JI N/A = Not Available Document # SRAM122 REV B Page 8 of 10 P3C1256 Pkg # # Pins Symbol A A1 b C D e E E1 E2 Q Pkg # # Pins Symbol A A2 b D E e HD J5 SOJ SMALL OUTLINE IC PACKAGE 28 (300 mil) Min Max 0.120 0.148 0.078 0.014 0.020 0.007 0.011 0.700 0.730 0.050 BSC 0.335 BSC 0.292 0.300 0.267 BSC 0.025 - T1 TSOP THIN SMALL OUTLINE PACKAGE 28 Min Max 0.039 0.047 0.036 0.040 0.007 0.011 0.461 0.469 0.311 0.319 0.022 BSC 0.520 0.535 Document # SRAM122 REV B Page 9 of 10 P3C1256 REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: SRAM122 P3C1256 HIGH SPEED 32K x 8 3.3V STATIC CMOS RAM REV. ISSUE DATE ORIG. OF CHANGE OR 1997 DAB New Data Sheet A Oct-05 JDB Change logo to Pyramid B Aug-06 JDB Updated SOJ package information Document # SRAM122 REV B DESCRIPTION OF CHANGE Page 10 of 10