P4C1024L LOW POWER 128K x 8 CMOS STATIC RAM FEATURES VCC Current (Commercial/Industrial) – Operating: 70mA/85mA – CMOS Standby: 150µA/150µA Three-State Outputs Fully TTL Compatible Inputs and Outputs Advanced CMOS Technology Access Times – 55/70/100 ns (Commercial or Industrial) Automatic Power Down Single 5V±10% Power Supply Easy Memory Expansion Using CE1, CE2, and OE Common Data I/O Packages – 32-Pin 600 mil Plastic and Ceramic DIP – 32-Pin 445 mil SOP – 32-Pin TSOP – 32-Pin LCC (400x820 mil) [Two-Sided] DESCRIPTION The P4C1024L is a 1,048,576-bit low power CMOS static RAM organized as 128Kx8. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times. Inputs are fully TTL-compatible. The RAM operates from a single 5V±10% tolerance power supply. Access times of 55 ns, 70 ns, and 100 ns are available. CMOS is utilized to reduce power consumption to a low level. The P4C1024L device provides asynchronous operation with matching access and cycle times. Memory locations Functional Block Diagram are specified on address pins A0 to A16. Reading is accomplished by device selection (CE1 low and CE2 high) and output enabling (OE) while write enable (WE) remains HIGH. By presenting the address under these conditions, the data in the addressed memory location is presented on the data input/output pins. The input/output pins stay in the HIGH Z state when either CE1 or OE is HIGH or WE or CE2 is LOW. The P4C1024L is packaged in a 32-pin TSOP, 445 mil SOP, 600 mil PDIP, or 32-pin LCC package. Pin ConfigurationS DIP(P600, C10), SOP (S12), LCC (L1) TOP VIEW TSOP configuration at end of datasheet Document # SRAM125 REV H Revised May 2011 P4C1024L - LOW POWER 128K x 8 CMOS STATIC RAM Maximum Ratings(1) Sym Parameter RECOMMENDED OPERATING CONDITIONS Value Unit V Grade(2) Ambient Temp GND VCC 0°C to 70°C 0V 5.0V ± 10% Industrial -40°C to +85°C 0V 5.0V ± 10% Military -55°C to +125°C 0V 5.0V ± 10% VCC Power Supply Pin with Respect to GND -0.5 to +7 VTERM Terminal Voltage with Respect to GND (up to 7.0V) -0.5 to VCC + 0.5 V TA Operating Temperature -55 to +125 °C TBIAS Temperature Under Bias -55 to +125 °C TSTG Storage Temperature -65 to +150 °C Sym Parameter IOUT Output Current into Low Outputs mA CIN Input Capacitance ILAT Latch-up Current mA COUT Output Capacitance Commercial CAPACITANCES(4) (VCC = 5.0V, TA = 25°C, f = 1.0MHz) Conditions Max Unit VIN=0V 7 pF VOUT=0V 9 pF DC ELECTRICAL CHARACTERISTICS (Over Recommended Operating Temperature & Supply Voltage)(2) Sym Parameter Test Conditions Min 2.4 VOH Output High Voltage (I/O0 - I/O7) IOH=-1mA, VCC=4.5V VOL Output Low Voltage (I/O0 - I/O7) IOL=2.1mA VIH Input High Voltage VIL Input Low Voltage ILI ILO Input Leakage Current Output Leakage Current GND ≤ VIN ≤ VCC GND ≤ VOUT ≤ VCC, CE1 ≥ VIH or CE2 ≤ VIL ISB VCC Current TTL Standby Current (TTL Input Levels) VCC=5.5V, IOUT=0mA ISB1 VCC Current CMOS Standby Current (CMOS Input Levels) VCC=5.5V, IOUT=0mA Document # SRAM125 REV H CE1=VIH or CE2=VIL CE1 ≥ VCC-0.2V, CE2 ≤ 0.2V Max Unit V 0.4 V 2.2 VCC + 0.3 V -0.5 0.8 V MIL -10 +10 IND -5 +5 COM -2 +2 MIL -10 +10 IND -5 +5 COM -2 +2 µA µA 3 mA 50 µA Page 2 P4C1024L - LOW POWER 128K x 8 CMOS STATIC RAM POWER DISSIPATION CHARACTERISTICS Sym ICC Parameter Dynamic Operating Current Temperature Range * ** Unit -55 -70 -100 -55 -70 -100 Commercial 70 70 70 15 15 15 mA Industrial/Military 85 85 85 25 25 25 mA * Tested with outputs open and all address and data inputs changing at the maximum write-cycle rate. The device is continuously enabled for writing, i.e., CE2 ≥ VIH (min), CE1 and WE ≤ VIL (max), OE is high. Switching inputs are 0V and 3V. ** As above but @ f=1 MHz and VIL / VIH = 0V/VCC AC ELECTRICAL CHARACTERISTICS—READ CYCLE (Over Recommended Operating Temperature & Supply Voltage) Sym Parameter -55 Min -70 Max 55 Min -100 Max 70 Min Max tRC Read Cycle Time tAA Address Access Time 55 70 100 ns tAC Chip Enable Access Time 55 70 100 ns tOH Output Hold from Address Change 5 5 5 ns tLZ Chip Enable to Output in Low Z 10 10 10 ns tHZ Chip Disable to Output in High Z 20 25 30 ns tOE Output Enable Low to Data Valid 30 35 40 ns tOLZ Output Enable Low to Low Z tOHZ Output Enable High to High Z tPU Chip Enable to Power Up Time tPD Chip Disable to Power Down 5 100 Unit 5 20 0 5 25 0 55 ns ns 30 0 70 ns ns 100 ns TIMING WAVEFORM OF READ CYCLE NO. 1 (OE CONTROLLED)(1) Document # SRAM125 REV H Page 3 P4C1024L - LOW POWER 128K x 8 CMOS STATIC RAM TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED) TIMING WAVEFORM OF READ CYCLE NO. 3 (CE CONTROLLED) Notes: 1.WE is HIGH for READ cycle. 2.CE1 and OE are LOW, and CE2 is HIGH for READ cycle. 3.ADDRESS must be valid prior to, or coincident with later of CE1 transition LOW or CE2 transition HIGH. 4.Transition is measured ± 200 mV from steady state voltage prior to Document # SRAM125 REV H change, with loading as specified in Figure 1. This parameter is sampled and not 100% tested. 5.READ Cycle Time is measured from the last valid address to the first transitioning address. Page 4 P4C1024L - LOW POWER 128K x 8 CMOS STATIC RAM AC CHARACTERISTICS—WRITE CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Sym Parameter -55 Min -70 Max Min -100 Max Min Max Unit tWC Write Cycle Time 55 70 100 ns tCW Chip Enable Time to End of Write 50 60 75 ns tAW Address Valid to End of Write 50 60 75 ns tAS Address Setup Time 0 0 0 ns tWP Write Pulse Width 40 50 60 ns tAH Address Hold Time 0 0 0 ns tDW Data Valid to End of Write 25 30 35 ns tDH Data Hold Time 0 0 0 ns tWZ Write Enable to Output in High Z tOW Output Active from End of Write 25 5 30 5 35 5 ns ns TIMING WAVEFORM OF WRITE Cycle No. 1 (WE Controlled)(6) Notes: 6. CE1 and WE are LOW and CE2 is HIGH for WRITE cycle. 7. OE is LOW for this WRITE cycle to show tWZ and tOW. 8. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high impedance state Document # SRAM125 REV H 9. Write Cycle Time is measured from the last valid address to the first transitioning address. Page 5 P4C1024L - LOW POWER 128K x 8 CMOS STATIC RAM Timing Waveform of Write Cycle No. 2 (CE Controlled)(6) AC TEST CONDITIONS TRUTH TABLE Input Pulse Levels GND to 3.0V Input Rise and Fall Times 3ns Input Timing Reference Level 1.5V Output Timing Reference Level 1.5V Output Load See Figures 1 and 2 Mode CE1 CE2 OE WE I/O Power Standby H H X X High Z Standby Standby X L X X High Z Standby DOUT Disabled L H H H High Z Active Read L H L H DOUT Active Write L H X L High Z Active Figure 1. Output Load Figure 2. Thevenin Equivalent Note: Because of the ultra-high speed of the P4C1024L, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 µF high frequency capacitor is also required between VCC and ground. To avoid signal reflections, proper termination must be used; for example, a 50Ω test environment should be terminated into a 50Ω load with 1.77V (Thevenin Voltage) at the comparator input, and a 589Ω resistor must be used in series with DOUT to match 639Ω (Thevenin Resistance). * including scope and test fixture. Document # SRAM125 REV H Page 6 P4C1024L - LOW POWER 128K x 8 CMOS STATIC RAM DATA RETENTION CHARACTERISTICS Sym Parameter VDR VCC for Data Retention ICCDR(1) Data Retention Current tCDR Chip Deselect to Data Retention Time Test Conditions Min Max Unit 2.0 5.5 V VDR=2.0V 75 µA VDR=3.0V 100 µA CE1 ≥ VCC -0.2V, CE2 ≤ 0.2V, VIN ≥ VCC -0.2V or VIN ≤ 0.2V See Retention Waveform 0 ns 1. CE1 ≤ 0.2V, CE2 ≤ 0.2V or CE1 ≥ VDR -0.2V, CE2 ≤ 0.2V or CE1 ≥ VDR -0.2V, CE2 ≥ VDR -0.2V AND VIN ≥ VDR -0.2V or VIN ≤ 0.2V LOW VCC DATA RETENTION WAVEFORM 1 (CE1 CONTROLLED) LOW VCC DATA RETENTION WAVEFORM 2 (CE2 CONTROLLED) Document # SRAM125 REV H Page 7 P4C1024L - LOW POWER 128K x 8 CMOS STATIC RAM ORDERING INFORMATION TSOP PIN CONFIGURATION Document # SRAM125 REV H Page 8 P4C1024L - LOW POWER 128K x 8 CMOS STATIC RAM RECTANGULAR LEADLESS CHIP CARRIER [TWO-SIDED] L1 Pkg # # Pins 32 Symbol Min Max A 0.080 0.100 b 0.022 0.028 b1 0.006 0.022 b2 0.040 - D 0.800 0.840 E 0.392 0.400 e 0.050 BSC h 0.012 REF L 0.070 0.080 L1 0.090 0.110 L2 0.003 0.015 N 32 Pkg # P600 # Pins 32 (600 mil) Symbol Min Max A 0.160 0.200 A1 0.015 - b 0.014 0.023 b2 0.045 0.070 C 0.006 0.014 D 1.600 1.700 E1 0.526 0.548 E 0.590 0.610 PLASTIC DUAL IN-LINE PACKAGE e 0.100 BSC eB 0.600 BSC L 0.120 0.150 α 0° 15° Document # SRAM125 REV H Page 9 P4C1024L - LOW POWER 128K x 8 CMOS STATIC RAM SOIC/SOP SMALL OUTLINE IC PACKAGE S12 Pkg # # Pins 32 (445 Mil) Symbol Min Max A - 0.118 A1 0.004 - A2 0.101 0.111 B 0.014 0.020 C 0.006 0.012 D 0.793 0.817 e 0.050 BSC E 0.440 0.450 H 0.546 0.566 L 0.023 0.039 L1 0.047 0.063 α 0° 4° Pkg # T3 # Pins 32 TSOP THIN SMALL OUTLINE PACKAGE (8 x 20 mm) Symbol Min Max A - 0.048 A2 0.037 0.042 b 0.006 0.011 D 0.720 0.729 E 0.307 0.323 e 0.50 mm BSC HD 0.779 0.796 Document # SRAM125 REV H Page 10 P4C1024L - LOW POWER 128K x 8 CMOS STATIC RAM SIDEBRAZED DUAL IN-LINE PACKAGE C10 Pkg # # Pins 32 (600 mil) Symbol Min Max A - 0.225 b 0.014 0.026 b2 0.045 0.065 C 0.008 0.018 D - 1.680 E 0.510 0.620 eA 0.600 BSC e 0.100 BSC L 0.125 0.200 Q 0.015 0.070 S1 0.005 - S2 0.005 - Document # SRAM125 REV H Page 11 P4C1024L - LOW POWER 128K x 8 CMOS STATIC RAM REVISIONS DOCUMENT NUMBER SRAM 125 DOCUMENT TITLE P4C1024L - LOW POWER 128K x 8 CMOS STATIC RAM REV ISSUE DATE ORIGINATOR OR 1997 DAB New Data Sheet A Oct-2005 JDB Changed logo to Pyramid B Feb-2006 JDB Added TSOP package C Sep-2006 JDB Added Ceramic DIP package D May-2007 JDB Corrected errors in P600 package dimensions E Nov-2008 JDB Added L1 package, lead-free option F Nov-2008 JDB Changed layout and formatting, no significant changes to content G Sep-2010 JDB Corrected error in DC Electrical Characteristics table H May-2011 JDB Added 100 ns speed Document # SRAM125 REV H DESCRIPTION OF CHANGE Page 12