PI90LV14/PI90LVT14 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 1:5 Clock Distribution Features Description • Meets and Exceeds the Requirements of ANSI TIA/EIA-644-1995 • Designed for clocking rates up to 320MHz • Operates from a single 3.3V Supply • Low Voltage Differential Signaling (LVDS) with Output Voltages of ±350mV into a 100-ohm load • Choice between LVDS or TTL clock input • Synchronous Enable/Disable • Clock outputs default LOW when inputs open • Multiplexed clock input – Internal 300kohms pullup resistor on input pins – CLK & CLK have 110-ohm internal termination (PI90LVT14) • 50ps Output-to-Output Skew • 475ps typical propagation delay • ±22ps Period Jitter • Bus Pins are high impedance when disabled or with VCC less than 1.5V • TTL inputs are 5V Tolerant • Power Dissipation at 400Mbits/s of 150mW • Function compatible to Motorola (PECL) – MC100EL14 and Micrel/Synergy (PECL) – SY100EL14V • >9kV ESD Protection • 20-pin TSSOP (L) (Pb-free available) The PI90LV14 implements low voltage differential signaling (LVDS) to achieve clocking rates as high as 320MHz with low skew. The PI90LV14 is a low-skew 1:5 clock distribution chip which incorporates multiplexed clock inputs to allow for distribution of a lower-speed, single-ended clock or a high-speed system clock. When LOWthe SEL pin will select the differential clock input. The common enable (EN) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. Because the internal flip-flop is clocked on the falling edge of the input clock, all associated specification limits are referenced to the negative edge of the clock input. The intended application of these devices and signaling technique is for high-speed clock distribution between boards. PI90LV14 Block Diagram CLK1OUT+ CLK1OUT– Pin Descriptions 1 20 2 VCC 19 Pin EN Function CLK, CLK CLK2OUT+ Differential Clock Inputs SCLK LVTTL Clock Input EN Synchronous Enable SEL Clock Select Input CLK3OUT+ CLK1- 5OUT± Differential Clock Outputs CLK3OUT– Function Table CLK SCLK SEL EN* CLKOUT+ L X L L L H X L L H X L H L L X H H L H ↓ ↓ X H Z* CLK4OUT+ CLK4OUT– CLK5OUT+ CLK5OUT– 4 D Q V CLK2OUT– 3 5 1 8 9 VCC 17 GND 16 15 6 7 18 0 SCLK CLK 1107 PI90LVT14 Only 14 CLK 13 GND 12 SEL 11 GND 10 * On next negative transition of CLK, or SCLK 08-0295 1 PS8538D 10/27/09 PI90LV14/PI90LVT14 1:5 Clock Distribution 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Electrical Characteristics over Recommended Operating Conditions (unless otherwise noted). Symbol Parame te r ⎪VOD ⎪ Differential output voltage magnitude Δ⎪VOD ⎪ Change in differential output voltage magnitude between logic states VOC(SS) Steady- state common- mode output voltage ΔVOC(SS) VOC(PP) Change in steady- state common- mode output voltage between logic states Te s t Conditions RL = 100Ω See Figures 1 and 2 M in. Typ.(1) M ax. 247 3 40 454 –50 1.125 See Figure 3 50 1.40 –5 0 1.7 V mV Peak- to- peak common- mode output voltage Enabled, RL = 100Ω VIN = VCC or GND 60 10 0 21 35 2 .5 4.0 Supply Current IIH High- level input current VIH = 2V 3.0 20 IIL Low- level input current VIL = 0.8V 5.0 20 IOS Short- circuit output current IOZ High- impedance output current VO = 0V or VCC 1 Power- off output current VCC = 1.1V, VO = 2.4V 1 CIN Input capacitance, VI = 0.4 sin (4E6πt) +0.5V 9 CO Output capacitance VI = 0.4 sin (4E6πt) +0.5V, Disabled 10 RTERM Termination Resistor PI90LVT14 08-0295 mV 50 ICC IO(OFF) Units Disabled, VIN = VCC or GND 0.5 VODOUT+ or VODOUT– = 0V ±7.4 VOD = 0V ±4.7 2 90 110 mA μA mA μA pF 13 2 PS8538D Ω 10/27/09 PI90LV14/PI90LVT14 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 1:5 Clock Distribution 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Switching Characteristics over Recommended Operating Conditions (unless otherwise noted)(8,9). Characte ris tic Propagation De lay to Output CLK to CLKOUT ± SCLK to CLKOUT ± SEL to CLKOUT ± Dis able Time CLK or SCLK to CLKOUT ± Symbol M in. Typ. M ax. tPLH tPHL 3.0 2.5 2.6 4.0 3.5 3.6 tPHZ tPLZ tPZH tPZL 2.7 2.7 4.7 3.7 3.5 3.5 6.0 6.0 Part-to-Part Ske w CLK (Diff) to Q CLK (SE), SCLK to Q With Device Skew tskew tskew tskew Cycle -to-Cycle Jitte r tjit(cc) –50 +50 Pe riod Jitte r tjit(per) –22 +22 Se tup Time ENx to CLK CEN to CLK ts ts 100 100 Hold Time ENx, CEN to SCLK ENx, CEN to CLKx th th M inimum Input Swing (CLK) Com. M ode Range (CLK) Ris e /Fall Time s (20 – 80%) SCLK to CLKOUT± SCLK to CLKOUT± Units Condition ns ns 2 TBD TBD TBD 0.20 VCMR 0.125 tr tf 150 150 Figure 6 ps Figure 7 –100 –100 550 500 VPP 1 2 720 720 0.800 1.5 VCC - 0.20 1200 1200 2 3 V 4 ps Duty Cycle Dis tortion Puls e Ske w ( tPLH - tPHL) tSK1R 200 3 00 5 Channe l-to-Channe l Ske w, s ame e dge tSK2R 70 190 6 250 M aximum Ope rating Fre que ncy MHz 7 Notes: 1. Within-Device skew is defined for identical transitions on similar paths through a device. 2. Setup, Hold, and Disable times are all relative to a falling edge on CLK or SCLK. 3. Minimum input swing for which AC parameters are guaranteed. Full DC LVDS output swings will be generated with only 50mV input swings. 4. The range in which the high level of the input swing must fall while meeting the VPP spec. 5. tSKIR is the difference in receiver propagation delay (tPLH-tPHL) of one device, and is the duty cycle distortion of the output at any given temperature and VCC. The propagation delay specification is a device-to-device worst case over process, voltage, and temperature. 6. tSK2R is the difference in receiver propagation delay between channels in the same device of any outputs switching in the same direction. This parameter is guaranteed by design and characterization. 7. Generator input conditions: trtf < 1ns, 50% duty cycle, differential (1.10V to 1.35V peak-peak). Output Criteria: 60%/40% duty cycle, VOL (max) 0-4V, VOH (min) 2.7V, Load - 7pF (stray plus probes). 8. CL includes probe and fixture capacitance. 9. Generator waveform for all tests unless otherwise specified: f = 25 MHz, ZO = 50 ohms, tr = 1ns, tf = 1ns (35%-65%). To ensure fastest propagation delay & minimum skew, clock input edge rates should not be slower than 1ns/V; control signals not slower than 3ns/V. 08-0295 3 PS8538D 10/27/09 PI90LV14/PI90LVT14 1:5 Clock Distribution 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Parameter Measurement Information II DIN VI IOY DOUT+ IOZ VOD VODOUT+ VOC VODOUT– DOUT– GND (VODOUT++VODOUT–)/2 Figure 1. Voltage and Current Definitions 3.75k7 DOUT+ VOD Input DOUT– 1007 3.75k7 ± 0V £ VTEST £ 2.4V Figure 2. VOD Test Circuit 3V DOUT+ 49.97 ±1% (2 places) VI Input DOUT– VOC(PP) 0V VOC(SS) VOC Note: 1. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1ns, Pulse Repetition Rate (PRR) = 50 Mpps, Pulse width = 10 ±0.2ns. CL includes instrumentation and fixture capacitance within 0.06m of the D.U.T. The measurement of VOC(PP) is made on test equipment with a –3dB bandwidth of at least 300MHz. Figure 3. Test Circuit & Definitions for the Driver Common-Mode Output Voltage 08-0295 4 PS8538D 10/27/09 PI90LV14/PI90LVT14 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 1:5 Clock Distribution 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Parameter Measurement Information (continued) 32V 1.4V Input 0.8V DOUT+ Input tPLH VOD DOUT– tPHL 1007 ±1% Output CL= 10pF (2 places) 0V 100% 80% VOD(H) VOD(L) tf 20% 0% tr Note: 1. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1ns, Pulse Repetition Rate (PRR) = 15 Mpps, Pulse width = 10 ±0.2ns. CL includes instrumentation and fixture capacitance within 0.06m of the D.U.T. Figure 4. Test Circuit, Timing, & Voltage Definitions for the Differential Output Signal 49.97 ±1% (2 places) DOUT+ 0.8V or 2V DOUT– VODOUT+ VODOUT– + 1.2V – Input 2V 1.4V 0.8V Input tPZH tPHZ @1.4V VODOUT+ or VODOUT– 1.3V 1.2V tPZL tPLZ 1.2V VODOUT– 1.1V or VODOUT+ @1V Note: 1. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1ns, Pulse Repetition Rate (PRR) = 0.5 Mpps, Pulse width = 500 ±10ns. CL includes instrumentation and fixture capacitance within 0.06m of the D.U.T. Figure 5. Enable & Disable Time Circuit & Definitions 08-0295 5 PS8538D 10/27/09 PI90LV14/PI90LVT14 1:5 Clock Distribution 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 CLKOUT– CLKOUT+ t cycle n t cycle n+1 t jit(cc) = t cycle n - t cycle n+1 Figure 6. Cycle-to-Cycle Jitter CLKOUT– CLKOUT+ t cycle n CLKOUT– CLKOUT+ 1 fO t jit(per) = t cycle n 1 fO Figure 7. Period Jitter 08-0295 6 PS8538D 10/27/09 PI90LV14/PI90LVT14 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 1:5 Clock Distribution 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 DOCUMENT CONTROL NO. PD - 1311 20 REVISION: E DATE: 03/09/05 .169 .177 1 .252 .260 6.4 6.6 4.3 4.5 .004 0.09 .008 0.20 1 .047 1.20 Max .007 .012 0.19 0.30 .0256 BSC 0.65 0.45 0.75 SEATING PLANE .018 .030 .238 .269 6.1 6.7 .002 0.05 .006 0.15 Pericom Semiconductor Corporation 3545 N. 1st Street, San Jose, CA 95134 1-800-435-2335 • www.pericom.com Note: 1. Package Outline Exclusive of Mold Flash and Metal Burr 2. Controlling dimentions in millimeters 3. Ref: JEDEC MO-153F/AC DESCRIPTION: 20-Pin, 173-Mil Wide, TSSOP PACKAGE CODE: L Notes: 1. For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php Ordering Information Orde ring Code Packaging Code Package Type PI90LV14LE L Pb- free, 20- Pin 173- mil TSSO P PI90LVT14LE L Pb- free, 20- Pin 173- mil TSSO P Notes: 1. Thermal characteristics can be found on the company web site at http://www.pericom.com/packaging/mechanicals.php 2. E = Pb-free and Green 3. Adding X suffix = Tape/Reel Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com 08-0295 7 PS8538D 10/27/09