DS92CK16 3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver General Description Features The DS92CK16 1 to 6 Clock Buffer/Bus Transceiver is a one to six CMOS differential clock distribution device utilizing Bus Low Voltage Differential Signaling (BLVDS) technology. This clock distribution device is designed for applications requiring ultra low power dissipation, low noise, and high data rates. The BLVDS side is a transceiver with a separate channel acting as a return/source clock. Master/Slave clock selection in a backplane application 125 MHz operation (typical) 100 ps duty cycle distortion (typical) 50 ps channel to channel skew (typical) 3.3V power supply design Glitch-free power on at CLKI/O pins Low Power design (20 mA @ 3.3V static) Accepts small swing (300 mV typical) differential signal levels n Industrial temperature operating range (-40˚C to +85˚C) n Available in 24-pin TSSOP Packaging The DS92CK16 accepts LVDS (300 mV typical) differential input levels, and translates them to 3V CMOS output levels. An output enable pin OE , when high, forces all CLKOUT pins high. The device can be used as a source synchronous driver. The selection of the source driving is controlled by the CrdCLKIN and DE pins. This device can be the master clock, driving the inputs of other clock I/O pins in a multipoint environment. Easy master/slave clock selection is achieved along a backplane. n n n n n n n n Function Diagram and Truth Table 10108201 Receive Mode Truth Table INPUT OE DE Driver Mode Truth Table OUTPUT INPUT OUTPUT CrdCLKIN (CLKI/O+)–(CLKI/O−) CLKOUT OE DE X H L L L L CrdCLKIN CLK/I/O+ CLKI/O− CLKOUT H L H H X L H X VID≥ 0.07V H L L H H L H L H X VID≤ −0.07V L H L L L H H H L H H L H H H X Z Z H L = Low Logic State H = High Logic State X = Irrelevant Z = TRI-STATE TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 2006 National Semiconductor Corporation DS101082 www.national.com DS92CK16 3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver April 2006 DS92CK16 Connection Diagram 10108202 Order Number DS92CK16TMTC See NS Package Number MTC24 TSSOP Package Pin Descriptions Pin Name Pin # Type CLKI/O+ 6 I/O True (Positive) side of the differential clock input. CLKI/O− 7 I/O Complementary (Negative) side of the differential clock input. OE 2 I OE; this pin is active Low. When High, this pin forces all CLKOUT pins High. When Low, CLKOUT pins logic state is determined by either the CrdCLKIN or the VID at the CLK/I/O pins with respect to the logic level at the DE pin. This pin has a weak pullup device to VCC. If OE is floating, then all CLKOUT pins will be High. DE 11 I DE; this pin is active LOW. When Low, this pin enables the CardCLKIN signal to the CLKI/O pins and CLKOUT pins. When High, the Driver is TRI-STATE ® , the CLKI/O pins are inputs and determine the state of the CLKOUT pins. This pin has a weak pullup device to VCC. If DE is floating, then CLKI/O pins are TRI-STATE. 13, 15, 17, 19, 21, 23 O 6 Buffered clock (CMOS) outputs. 9 I VCC 16, 20, 24 Power VCC; Analog VCCA (Internally separate from VCC, connect externally or use separate power supplies). No special power sequencing required. Either VCCA or VCC can be applied first, or simultaneously apply both power supplies. GND 1, 12, 14, 18, 22 Ground GND VCCA 4 Power Analog VCCA (Internally separate from VCC, connect externally or use separate power supplies). No special power sequencing required. Either VCCA or VCC can be applied first, or simultaneously apply both power supplies. GNDA 5, 8 Ground Analog Ground (Internally separate from Ground must be connected externally). NC 3, 10 CLKOUT CrdCLKIN www.national.com Description Input clock from Card (CMOS level or TTL level). No Connects 2 Storage Temperature Range If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Lead Temperature Range Supply Voltage (VCC) −0.3V to +4V Enable Input Voltage (DE, OE, CrdCLKIN) −0.3V to +4V Voltage (CLKOUT) Voltage (CLKI/O ± ) (Soldering, 4 sec.) 260˚C > 3000V > 1000V > 200V ESD Ratings: HBM (Note 2) CDM (Note 2) Machine Model (Note 2) −0.3V to (VCC + 0.3V) Recommended Operating Conditions −0.3V to +4V Driver Short Circuit Current momentary Receiver Short Circuit Current momentary Min Supply Voltage (VCC) Maximum Package Power Dissipation at +25˚C TSSOP Package Derate TSSOP Package −65˚C to +150˚C CrdCLKIN, DE, OE Input Voltage 1500 mW 8.2 mW/˚C above +25˚C θJA 95˚C/W θJC 30˚C/W Typ +3.0 +3.3 0 Operating Free Air Temperature (TA) −40 25 Max Units +3.6 V VCC V +85 ˚C DC Electrical Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Notes 3, 4). Symbol VTH Parameter Conditions Pin Input Threshold High CLKI/O+, CLKI/O− Min VTL Input Threshold Low VCMR Common Mode Voltage Range (Note 5) VID = 250 mV pk to pk IIN Input Current VIN = 0V to VCC, DE = VCC, OE = VCC, Other Input = 1.2V ± 50 mV VOH1R Output High Voltage VID = 250 mV, IOH = −1.0 mA VOH2R Output High Voltage VID = 250 mV, IOH = −6 mA VOL1R Output Low Voltage IOL = 1.0 mA, VID = −250 mV VOL2R Output Low Voltage IOL = 6 mA, VID = −250 mV IODHR CLKOUT Dynamic Output Current (Note 6) VID = +250 mV, VOUT = VCC−1V IODLR CLKOUT Dynamic Output Current (Note 6) VID = −250 mV, VOUT = 1V VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current VIN = GND or 0.4V IINCRD Input Current VIN = 0V to VCC, OE = VCC CrdCLKIN −5 VCL Input Voltage Clamp IOUT = −1.5 mA OE, DE, CrdCLKIN −0.8 −70 Typ Max Units 25 +70 mV -35 |VID|/2 CLKOUT −20 ±5 VCC−0.4 2.9 VCC−0.8 2.5 0.06 0 VIN = VCC or 2.4V 3 mV 2.4 |VID|/2 V +20 µA V V 0.3 V 0.4 V −8 -16 -30 mA 10 21 35 mA VCC V DE, OE, CrdCLKIN 2.0 GND 0.8 V OE, DE −10 −2 +10 µA −20 −5 +20 µA +5 µA V www.national.com DS92CK16 Absolute Maximum Ratings (Note 1) DS92CK16 DC Electrical Characteristics (Continued) Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Notes 3, 4). Symbol ICC ICC1 ICCD Parameter Conditions Pin No Load Supply Current OE = DE = 0V, Outputs Enabled, No VID CrdCLKIN = VCC or GND, CLKI/O ( ± ) = Open Applied CLKOUT (0:5) = Open Circuit No Load Supply Current Outputs Enabled, VID over Common Mode Voltage Range OE = GND DE = VCC CrdCLKIN = VCC or GND, VID = 250 mV (0.125V VCM 2.275V), CLKOUT (0:5) = Open Circuit Driver Loaded Supply Current DE = OE = 0V, CrdCLKIN = VCC or GND, RL = 37.5Ω between CLKI/O+ and CLKI/O−, CLKOUT (0:5) = Open Circuit VOD Driver Output Differential Voltage ∆VOD Driver VOD Magnitude Change VOS Driver Offset Voltage ∆VOS Driver Offset Voltage Magnitude Change RL = 37.5Ω, Figure 5 DE = 0V CLKI/O+, CLKI/O− VOHD Driver Output High Driver Output Low IOS1D Driver Differential Short Circuit Current (Note 6) CrdCLKIN = VCC or GND, VOD = 0V, (outputs shorted together) DE = 0V Driver Output Short Circuit Current to VCC (Note 6) IOS3D IOS4D IOS5D IOFF 250 1.1 VOLD IOS2D Min Typ Max Units 13 mA 10 mA 20 25 mA 350 450 mV 10 20 mV 1.29 1.5 V 5 20 mV 1.35 1.8 VCC 0.80 1.05 V V |30| |50| mA CrdCLKIN = GND, DE = 0V, CLKI/O+ = VCC 36 70 mA Driver Output Short Circuit Current to VCC (Note 6) CrdCLKIN = VCC, DE = 0V, CLKI/O− = VCC 34 70 mA Driver Output Short Circuit Current to GND (Note 6) CrdCLKIN = VCC, DE = 0V, CLKI/O+ = 0V −47 −70 mA Driver Output Short Circuit Current to GND (Note 6) CrdCLKIN = GND, DE = 0V, CLKI/O− = 0V −50 −70 mA Power Off Leakage Current VCC = 0V or Open, VAPPLIED = 3.6V ± 20 µA www.national.com 4 Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Notes 7, 8). Symbol Parameter Conditions Min Typ Max Units 1.3 2.8 3.8 ns 1.3 2.9 3.8 ns DIFFERENTIAL RECEIVER CHARACTERISTICS tPHLDR Differential Propagation Delay High to Low. CLKI/O to CLKOUT tPLHDR Differential Propagation Delay Low to High. CLKI/O to CLKOUT tSK1R Duty Cycle Distortion(Note 10) (pulse skew) |tPLH–tPHL| 100 400 ps tSK2R Channel to Channel Skew; Same Edge (Note 11) 30 80 ps 2.5 ns CL = 15 pF VID = 250 mV Figures 1, 2 tSK3R Part to Part Skew (Note 12) tTLHR Transition Time Low to High (Note 9) (20% to 80% ) 0.4 1.4 2.4 ns tTHLR Transition Time High to Low(Note 9) (80% to 20% ) 0.4 1.3 2.2 ns tPLHOER Propagation Delay Low to High ( OEto CLKOUT) 1.0 3 4.5 ns tPHLOER Propagation Delay High to Low (OE to CLKOUT) 1.0 3 4.5 ns fMAX Maximum Operating Frequency (Note 15) 100 125 0.5 1.8 2.5 ns 0.5 1.8 2.5 ns 2.0 4.5 6.0 ns 2.0 4.5 CL = 15 pF Figures 3, 4 MHz DIFFERENTIAL DRIVER TIMING REQUIREMENTS tPHLDD tPLHDD Differential Propagation Delay High to Low. CrdCLKIN to CL = 15 pF CLKI/O RL = 37.5Ω Differential Propagation Delay Low to High. CrdCLKIN to Figures 6, 7 CLKI/O tPHLCrd CrdCLKIN to CLKOUT Propagation Delay High to Low CL = 15 pF Figures 8, 9 tPLHCrd CrdCLKIN to CLKOUT Propagation Delay Low to High 6.0 ns tSK1D Duty Cycle Distortion (pulse skew) |tPLH–tPHL| (Note 13) 600 ps 2.0 ns tSK2D Differential Part-to-Part Skew (Note 14) tTLHD Differential Transition Time (Note 9) (20% to 80% ) 0.4 0.75 1.4 ns tTHLD Differential Transition Time (Note 9) (80% to 20% ) 0.4 0.75 1.4 ns 10 ns 10 ns 32 ns 32 ns tPHZD Transition Time High to TRI-STATE. DE to CLKI/O tPLZD Transition Time Low to TRI-STATE. DE to CLKI/O tPZHD Transition Time TRI-STATE to High. DE to CLKI/O tPZLD Transition Time TRI-STATE to Low. DE to CLKI/O fMAX Maximum Operating Frequency (Note 15) VIN = 0V to VCC CL = 15 pF, RL = 37.5Ω Figures 10, 11 100 125 MHz Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. These ratings are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Note 2: ESD Rating: ESD qualification is performed per the following: HBM (1.5 kΩ, 100 pF), Machine Model (250V, 0Ω), IEC 1000-4-2. All VCC pins connected together, all ground pins connected together. Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VID, VOD, VTH, and VTL. Note 4: All typicals are given for: VCC = +3.3V and TA = +25˚C. Note 5: The VCMR range is reduced for larger VID. Example: If VID=400 mV, then VCMR is 0.2V to 2.2V A VID up to |VCC–0V| may be applied between the CLKI/O+ and CLKI/O− inputs, with the Common Mode set to VCC/2. Note 6: Only one output should be momentarily shorted at a time. Do not exceed package power dissipation rating. Note 7: CL includes probe and fixture capacitance. Note 8: Generator waveform for all tests unless otherwise specified: f = 25 MHz, Zo = 50Ω, tr = 1 ns, tf = 1 ns (10%–90%). To ensure fastest propagation delay and minimum skew, clock input edge rates should not be slower than 1 ns/V; control signals not slower than 3 ns/V. In general, the faster the input edge rate, the better the AC performance. Note 9: All device output transition times are based on characterization measurements and are guaranteed by design. 5 www.national.com DS92CK16 Switching Characteristics DS92CK16 Switching Characteristics (Continued) Note 10: tSK1R is the difference in receiver propagation delay (|tPLH–tPHL|) of one device, and is the duty cycle distortion of the output at any given temperature and VCC. The propagation delay specification is a device to device worst case over process, voltage and temperature. Note 11: tSK2R is the difference in receiver propagation delay between channels in the same device of any outputs switching in the same direction. This parameter is guaranteed by design and characterization. Note 12: tSK3R, part-to-part skew, is the difference in receiver propagation delay between devices of any outputs switching in the same direction. This specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. TSK3R is defined as Max–Min differential propagation delay.This parameter is guaranteed by design and characterization. Note 13: tSK1D is the difference in driver propagation delay (|tPLH–tPHL|) and is the duty cycle distortion of the CLKI/O outputs. Note 14: tSK2D part-to-part skew, is the difference in driver propagation delay between devices of any outputs switching in the same direction. This specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. tSK2D is defined as Max–Min differential propagation delay. Note 15: Generator input conditions: tr/tf < 1 ns, 50% duty cycle, differential (1.10V to 1.35V pk-pk). Output Criteria: 60%/40% duty cycle, VOL(max) 0.4V, VOH(min) 2.7V, Load = 7 pF (stray plus probes). Parameter Measurement Information 10108203 FIGURE 1. Receiver Propagation Delay and Transition Time Test Circuit 10108204 Generator waveform for all test unless otherwise specified: f = 25 MHz, 50% Duty Cycle, Zo = 50Ω, tTLH = 1 ns, tTHL = 1 ns. FIGURE 2. Receiver Propagation Delay and Transition Time Waveforms 10108205 FIGURE 3. Output Enable (OE) Delay Test Circuit www.national.com 6 DS92CK16 Parameter Measurement Information (Continued) 10108206 FIGURE 4. Output Enable (OE) Delay Waveforms 10108207 FIGURE 5. Differential Driver DC Test 10108208 FIGURE 6. Driver Propagation Delay Test Circuit 7 www.national.com DS92CK16 Parameter Measurement Information (Continued) 10108209 FIGURE 7. Driver Propagation Delay and Transition Time Waveforms 10108210 FIGURE 8. CrdCLKIN Propagation Delay Time Test Circuit 10108211 FIGURE 9. CrdCLKIN Propagation Delay Time Waveforms www.national.com 8 DS92CK16 Parameter Measurement Information (Continued) 10108212 FIGURE 10. Driver TRI-STATE Test Circuit 10108213 FIGURE 11. Driver TRI-STATE Waveforms 9 www.national.com DS92CK16 decoupling capacitors to the power planes. A 4.7µF (35V) or greater solid tantalum capacitor should be connected at the power entry point on the printed circuit board. Applications Information General application guidelines and hints for BLVDS/LVDS transceivers, drivers and receivers may be found in the following application notes: LVDS Owner’s Manual (lit #550062-001), AN805, AN807, AN808, AN903, AN905, AN916, AN971, AN977 . BLVDS drivers and receivers are intended to be used in a differential backplane configuration. Transceivers or receivers are connected to the driver through a balanced media such as differential PCB traces. Typically, the characteristic differential impedance of the media (Zo) is in the range of 50Ω to100Ω. Two termination resistors of ZoΩ each are placed at the ends of the transmission line backplane. The termination resistor converts the current sourced by the driver into a voltage that is detected by the receiver. The effects of mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as ground shifting, noise margin limits, and total termination loading must be taken into account. The DS92CK16 differential line driver is a balanced current source design. A current mode driver, generally speaking has a high output impedance (100 ohms) and supplies a constant current for a range of loads (a voltage mode driver on the other hand supplies a constant voltage for a range of loads). Current is switched through the load in one direction to produce a logic state and in the other direction to produce the other logic state. The output current is typically 9.330 mA. The current changes as a function of load resistor. The current mode requires (as discussed above) that a resistive termination be employed to terminate the signal and to complete the loop. Unterminated configurations are not allowed. The 9.33 mA loop current will develop a differential voltage of about 350mV across 37.5Ω (double terminated 75Ω differential transmission backplane) effective resistance, which the receiver detects with a 280 mV minimum differential noise margin neglecting resistive line losses (driven signal minus receiver threshold (350 mV – 70 mV = 280 mV)). The signal is centered around +1.2V (Driver Offset, VOS) with respect to ground. Note that the steady-state voltage (VSS) peak-to-peak swing is twice the differential voltage (VOD) and is typically 700 mV. The current mode driver provides substantial benefits over voltage mode drivers, such as an RS-422 driver. Its quiescent current remains relatively flat versus switching frequency. Whereas the RS-422 voltage mode driver increases exponentially in most case between 20 MHz–50 MHz. This is due to the overlap current that flows between the rails of the device when the internal gates switch. Whereas the current mode driver switches a fixed current between its output without any substantial overlap current. This is similar to some ECL and PECL devices, but without the heavy static ICC requirements of the ECL/PECL designs. LVDS requires > 80% less current than similar PECL devices. AC specifications for the driver are a tenfold improvement over other existing RS-422 drivers. The TRI-STATE function allows the driver outputs to be disabled, thus obtaining an even lower power state when the transmission of data is not required. PC BOARD CONSIDERATIONS Use at least 4 PCB layers (top to bottom); BLVDS signals, ground, power, TTL signals. Isolate TTL signals from BLVDS signals, otherwise the TTL may couple onto the BLVDS lines. It is best to put TTL and BLVDS signals on different layers which are isolated by a power/ground plane(s). Keep drivers and receivers as close to the (BLVDS port side) connectors as possible to create short stub lengths. DIFFERENTIAL TRACES Use controlled impedance traces which match the differential impedance of your transmission medium (ie. backplane or cable) and termination resistor(s). Run the differential pair trace lines as close together as possible as soon as they leave the IC . This will help eliminate reflections and ensure noise is coupled as common-mode. In fact, we have seen that differential signals which are 1mm apart radiate far less noise than traces 3mm apart since magnetic field cancellation is much better with the closer traces. Plus, noise induced on the differential lines is much more likely to appear as common-mode which is rejected by the receiver. Match electrical lengths between traces to reduce skew. Skew between the signals of a pair means a phase difference between signals which destroys the magnetic field cancellation benefits of differential signals and EMI will result. (Note the velocity of propagation, v = c/Er where c (the speed of light) = 0.2997mm/ps or 0.0118 in/ps). Do not rely solely on the autoroute function for differential traces. Carefully review dimensions to match differential impedance and provide isolation for the differential lines. Minimize the number or vias and other discontinuities on the line. Avoid 90˚ turns (these cause impedance discontinuities). Use arcs or 45˚ bevels. Within a pair of traces, the distance between the two traces should be minimized to maintain common-mode rejection of the receivers. On the printed circuit board, this distance should remain constant to avoid discontinuities in differential impedance. Minor violations at connection points are allowable. STUB LENGTH Stub lengths should be kept to a minimum. The typical transition time of the DS92CK16 BLVDS output is 0.75ns (20% to 80%). The 100 percent time is 0.75/0.6 or 1.25ns. For a general approximation, if the electrical length of a trace is greater than 1/5 of the transition edge, then the trace is considered a transmission line. For example, 1.25ns/5 is 250 picoseconds. Let velocity equal 160ps per inch for a typical loaded backplane. Then maximum stub length is 250ps/ 160ps/in or 1.56 inches. To determine the maximum stub for your backplane, you need to know the propagation velocity for the actual conditions (refer to application notes AN– 905 and AN–808). POWER DECOUPLING RECOMMENDATIONS Bypass capacitors must be used on power pins. High frequency ceramic (surface mount is recommended) 0.1µF in parallel with 0.01µF, in parallel with 0.001µF at the power supply pin as well as scattered capacitors over the printed circuit board. Multiple vias should be used to connect the www.national.com TERMINATION Use a resistor which best matches the differential impedance of your loaded transmission line. Remember that the current mode outputs need the termination resistor to generate the differential voltage. BLVDS will not work without resistor termination. 10 Balanced cables (e.g. twisted pair) are usually better than unbalanced cables (ribbon cable, simple coax.) for noise reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling effects and also tend to pick up electromagnetic radiation a common-mode (not differential mode) noise which is rejected by the receiver. For cable distances < 0.5M, most cables can be made to work effectively. For distances 0.5M ≤ d ≤ 10M, CAT 3 (category 3) twisted pair cable works well, is readily available and relatively inexpensive. (Continued) Surface mount 1% to 2% resistors are best. PROBING BLVDS TRANSMISSION LINES Always use high impedance ( > 100kΩ), low capacitance ( < 2pF) scope probes with a wide bandwidth (1GHz) scope. Improper probing will give deceiving results. CABLES AND CONNECTORS, GENERAL COMMENTS Use controlled impedance media. The connectors you use should have a matched differential impedance of about Zo Ω. They should not introduce major impedance discontinuities. 11 www.national.com DS92CK16 Applications Information DS92CK16 3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver Physical Dimensions inches (millimeters) unless otherwise noted 24-Pin TSSOP Package Drawing Dimensions shown in millimeters Order Number DS92CK16TMTC NS Package Number MTC24 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. 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