PI6C49014 Networking Clock Generator Description Features • 3.3V ±10% Supply Voltage • Uses 25MHz Crystal or 25MHz reference input • One 200MHz selectable HCSL output with spread – default is spread off • Two 25MHz LVCMOS outputs • One 32.256MHz LVCMOS output • Industrial temperature -40°C to 85°C • Package: 28pin TSSOP (L) The PI6C49014 is a high performance networking clock generator which generates 200MHz HCSL clock signal along with two LVCMOS 25MHz and 32.256MHz clocks from either 25MHz crystal or reference input. This integrated solution is ideal for Networking and Embedded systems that require multiple frequencies yet small foot print. Applications • Networking systems • Embedded systems Pin Configuration Block Diagram 25 MHz crystal or clock input GNDO_200M IREF NC Clock Buffer/ Crystal Oscillator PLL, Dividers, Buffers, and Logic SCLK SDATA NC SCLK 200M_OUT 2 25M_OUT(1-2) 32.256M_OUT PD_RESET 1 200M_Q+ 200M_QNC NC VDDO_200M SDATA GND_25M 25M_Out1 25M_Out2 VDD_200M GND_200M NC VDD_D VDDO_25M GND_32M VDDO_32M GND_D VDD_XTAL X2 32.256M_Out GND_XTAL 11-0146 O X1 PDRESET 02/16/2012 PI6C49014 Networking Clock Generator Pin Description Pin # 1 2 3 4 5 6 7 Pin Name GNDO_200M IREF NC NC SCLK SDATA GND_25M Pin Type Power Output Input I/O Power 8 25M_Out1 Output 9 25M_Out2 Output 10 VDDO_25M Power 3.3V supply for 25MHz output 11 12 GND_32M VDDO_32M Power Power 13 32.256M_Out Output 14 GND_XTAL Power 15 PD_RESET Input 16 17 X1 X2 Input Output Ground for 32M output and related PLL 3.3V supply for 32M output and related PLL 32.256MHz LVCMOS output. When disabled, output is trisated and has a normal 110kOhm pull-down Ground for XTAL Power on reset, when low all PLLs are powered down and output trisated. SMBus registers are reset to default values Crystal input. Integrated 6pf capacitance Crystal output. Integrated 6pf capacitance 18 VDD_XTAL Power 3.3V supply for XTAL 19 20 21 22 23 24 25 GND_D VDD_D NC GND_200M VDD_200M VDDO_200M NC Power Power Power Power Power - Ground for all input and feedback divider of PLL 3.3V supply for all input and feedback divider of PLL No Connect, leave open Ground for 200MHz related PLL and I2C interface 3.3V supply for 200MHz related PLL and I2C interface 3.3V supply for 200MHz output buffer No Connect, leave open 26 NC - No Connect, leave open 27 28 200M_Q200M_Q+ Output Output 200MHz HCSL output 200MHz HCSL output 11-0146 Pin Description Ground for 200MHz output Connect 475-Ohm resistor to set HCSL output drive current No Connect, leave open No Connect, leave open SMBus compatible input clock. Supports fast mode 400 kHz input clock SMBus compatible data line Ground for 25MHz output 25MHz LVCMOS output. When disabled, output is trisated and has a normal 110kOhm pull-down 25MHz LVCMOS output. When disabled, output is trisated and has a normal 110kOhm pull-down 2 02/16/2012 PI6C49014 Networking Clock Generator Serial Data Interface (SMBus) PI6C49014 is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7-bit address and read/write bit as shown below. Address Assignment A6 A5 A4 A3 A2 A1 A0 R/W 1 1 0 1 0 0 1 0/1 How to Write 1 bit 8 bits 1 8 bits 1 8 bits 1 8 bits 1 Start bit d2H Ack Register offset Ack Byte Count = N Ack Data Byte 0 Ack … 8 bits 1 1 bit Data Byte N-1 Ack Stop bit Note: 1. Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0. How to Read (M: abbreviation for Master or Controller; S: abbreviation for slave/clock) 1 bit M: Start bit 8 bits M: Send "D2h" 1 bit 8 bits S: sends Ack M: send starting databyte location: N 1 bit S: sends Ack 1 bit M: Start bit 8 bits M: Send "D3h" 1 bit 8 bits S: sends Ack S: sends # of data bytes that will be sent: X 1 bit 8 bits M: sends Ack S: sends starting data byte N 1 bit M: sends Ack … 8 bits 1 bit 1 bit … S: sends data byte N+X1 M: Not Acknowledge M: Stop bit Byte 0: Spread Spectrum Control Register Bit Description Type Power Up Condition Output(s) Affected 7 Spread Spectrum Selection for 200 MHz HCSL PCI-Express clocks RW 0 200MHz HCSL PCI Express output RW 0 PD_RESET pin, bit 5 RW 1 All outputs 6 5 Enables hardware or software control of OE bits (see Byte 0–Bit 6 and Bit 5 Functionality table) Software PD_RESET bit. Enables or disables all outputs (see Byte 0–Bit 6 and Bit 5 Functionality table) 4 to 1 Reserved RW Undefined Not Applicable 0 OE for single-ended 25MHz output 25M_Out2 RW 1 Single-ended 25MHz output 25M_Out2 11-0146 3 Notes 0=spread off 1 = -0.5% down spread 0 = hardware cntl 1 = software ctrl 0 = disabled 1 = enabled 0 = disabled 1 = enabled 02/16/2012 PI6C49014 Networking Clock Generator Byte 0 - Bit 6 and Bit 5 Functionality Bit 6 0 1 1 Bit 5 X 0 1 Description PD_RESET HW pin/signal = enabled Disables all outputs and tri-states the outputs, PD_RESET HW pin/signal = DO NOT CARE Enable all outputs, PD_RESET HW pin/signal = DON'T CARE Byte 1: Control Register Bit Description Type Power Up CondiOutput(s) Affected tion 7 OE for 32.256M_Out1 RW 1 32.256M_Out 6 OE for 25M_Out1 RW 1 25M_Out1 5 to 0 Reserved RW Undefined Not Applicable Notes 0 = disabled 1 = enabled 0 = disabled 1 = enabled Byte 2: Control Register Bit Description Type Power Up CondiOutput(s) Affected tion 7 to 5 4 to 0 Reserved Reserved RW R Undefined Undefined Notes Not Applicable Not Applicable Byte 3: Control Register Bit Description Type Power Up Condition Output(s) Affected 7 to 3 Reserved RW Undefined Not Applicable 2 OE for 200M HCSL Output RW 1 200M 1 to 0 Reserved RW Undefined Not Applicable 11-0146 4 Notes 0 = disabled 1 = enabled 02/16/2012 PI6C49014 Networking Clock Generator Byte 4: Control Register Bit Description Type Power Up CondiOutput(s) Affected tion 7 to 0 Reserved R Undefined Notes Not Applicable Byte 5: Control Register Bit Description Type Power Up CondiOutput(s) Affected tion 7 Revision ID bit 3 R 0 Not Applicable 6 Revision ID bit 2 R 0 Not Applicable 5 4 3 2 1 0 Revision ID bit 1 Revision ID bit 0 Vendor ID bit 3 Vendor ID bit 2 Vendor ID bit 1 Vendor ID bit 0 R R R R R R 0 0 0 0 1 1 Not Applicable Not Applicable Not Applicable Not Applicable Not Applicable Not Applicable Notes Byte 6: Control Register Bit Description Type Power Up CondiOutput(s) Affected tion 7 to 0 Reserved R Undefined 11-0146 5 Notes Not Applicable 02/16/2012 PI6C49014 Networking Clock Generator Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.) Symbol Parameters Test Condition Min. Max. Units 3.0 3.6 V VDD 3.3V I/O Supply Voltage IDD Total Power Supply Current All outputs unloaded - 64 mA IDD_Output tristated Total power supply current with Outputs are tri-stated OE is “0”, no load - 54 mA Idd power down Total power supply current in power down mode PD_RESET = “0”, no load 4 mA TA Operating temperature - +85 ºC -40 Note: 1. Stress beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Absolute Maximum Ratings1 (Over operating free-air temperature range) Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. STORAGE TEMPERATURE…………………………………………..- 65°C TO +155°C AMBIENT TEMPERATURE WITH POWER APPLIED……………………-40°C TO +85°C 3.3V ANALOG SUPPLY VOLTAGE ……………………………………...- 0.5 TO +4.6V ESD PROTECTION(HBM)…………………………………….. …………… 2000V LVCMOS DC Electrical Characteristics Unless otherwise specified, VDD=3.3V±10%, Ambient Temperature –40°C to +85°C Symbol Parameter Operating Supply Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage VDD VIH VIL VIH VIL VOH VOL Conditions Min. Typ. 3.0 Max. 3.6 SDATA, SCLK SDATA, SCLK 2 -0.3 0.7VDD - VDD+0.3 0.8 VDD 0.3VDD IOH = -8mA VDD-0.4 - - IOL = 8mA - - 0.4 IIH Input High Current VIN = VDD-0.1V - - 45 IIL Input Low Current Internal pull up resistance Internal pull down resistance VIN = 0V -45 - - PD_RESET - 216 - 25M_Out1, 25M_Out2, 32.256M_Out - 110 - RPU RDN CIN Input Capacitance 11-0146 All input pins V µA kOhm 6 6 Unit pF 02/16/2012 PI6C49014 Networking Clock Generator LVCMOS AC Electrical Characteristics Unless otherwise specified, VDD=3.3V±10%, Ambient Temperature –40°C to +85°C Symbol Parameter Fin Input Frequency FOUT Output Frequency FOUTE Conditions Min. Typ. Max. Unit 25 MHz CLOAD = 15pF, 25MHz 25 MHz Output Frequency Error Xtal Frequency = 25MHz, CL = 18pF, +/-20ppm, output -20 = 25MHz 0 FOUT Output Frequency CLOAD = 15pF, 32.256MHz 32.256 FOUTE Output Frequency Error Xtal Frequency = 25MHz, CL = 18pF, +/-20ppm, Output = 32.256MHz FSC SCLK Frequency Min. pulse width of PD_RESET Input Output Rise/Fall time Output Duty Cycle Cycle –to- cycle Jitter Period Jitter Clock Stabilization Time from Power up Tr /Tf TDC TCj TPj TS -20 20 MHz 0 20 PPM 100 400 kHz 100 20% of VDD to 80% of VDD 32.256MHz 25 MHz clock output 45 - PPM ns - 3 1.2 55 150 40 ns % 10 ms ps HCSL DC Electrical Characteristics Unless otherwise specified, VDD=3.3V±10%, Ambient Temperature –40°C to +85°C Symbol Parameter Conditions Min. VOH Output High Voltage VOL Output Low Voltage Absolute Crossing Point Voltages Total variation of VCROSS overall edges VCROSS ΔVCROSS IOH Output High Current 11-0146 - With 475-Ohm resistor connected between IREF pin and GND 7 Typ. Max. Unit 660 - 950 mV - - 150 250 - 550 - - 140 mV - 14 - mA mV 02/16/2012 PI6C49014 Networking Clock Generator HCSL AC Electrical Characteristics Unless otherwise specified, VDD=3.3V±10%, Ambient Temperature –40°C to +85°C Symbol Parameter Conditions FOUT Output Frequency HCSL termination FOUTE Output Frequency Error Tr /Tf ΔTr /ΔTf TDC Output Rise/Fall time Rise and Fall Time Variation*2 Output Duty Cycle*3 Xtal Frequency = 25MHz, CL = 18pF, +/-20ppm, output = 200 MHz, 0% Spread. Between 0.175V and 0.525V *2 - TCj Cycle to cycle jitter *3 Differential waveform Min. Typ. Max. Unit 200 200 MHz -20 0 20 PPM 175 47 - 700 125 53 Spread Modulation Percentage -0.5 Spread Modulation Frequency 32 ps % 70 ps 0 % kHz Notes: *1. Test configuration is Rs=33Ω, Rp=49.9Ω, and 2pF *2. Measurement is taken from Single Ended waveform. *3. Measurement is taken from Differential waveform. *4. Measured from -150 mV to +150 mV on the differential waveform. The signal is monotonic through the measurement region for rise and fall time. The 300 mV measurement window is centered on the differential zero crossing. 11-0146 8 02/16/2012 PI6C49014 Networking Clock Generator HCSL output buffer characteristics VDD Slope ~ 1/Rs RO IOUT ROS Iout 0V VOUT = 0.90V max 0.90V Figure 9. Simplified diagram of current-mode output buffer HCSL Buffer characteristics Symbol Minimum Maximum RO 3000Ω N/A ROS unspecified unspecified VOUT N/A 950mV Application Notes Crystal circuit connection The following diagram shows PI6C49014 crystal circuit connection with a parallel crystal. For the CL=18pF crystal, it is suggested to use C1= 18pF, C2= 18pF. C1 and C2 can be adjusted to fine tune to the target ppm of crystal oscillator according to different board layouts. Crystal Oscillator Circuit XTAL_IN C1 18pF Crystal�(CL�=�18pF) XTAL_OUT C2 18pF 11-0146 9 02/16/2012 PI6C49014 Networking Clock Generator Recommended Crystal Specification Pericom recommends: a) GC2500003 XTAL 49S/SMD(4.0 mm), 25M, CL=18pF, +/-30ppm, http://www.pericom.com/pdf/datasheets/se/GC_GF.pdf b) FY2500081, SMD 5x3.2(4P), 25M, CL=18pF, +/-30ppm, http://www.pericom.com/pdf/datasheets/se/FY_F9.pdf c) FL2500047, SMD 3.2x2.5(4P), 25M, CL=18pF, +/-20ppm, http://www.pericom.com/pdf/datasheets/se/FL.pdf Configuration test load board termination for HCSL Outputs Rs 33Ω 5% PI6C49014 Clock TLA Rs 33Ω 5% Clock# TLB 475Ω 1% Rp 49.9Ω 1% Rp 49.9Ω 1% 2pF 5% 2pF 5% Figure 4. Configuration Test Load Board Termination 11-0146 10 02/16/2012 PI6C49014 Networking Clock Generator Configuration test load board termination for LVCMOS Outputs 3.3V ±10% 3.3V ±10% VDD 10Ω VDDO 15pF GND Figure 5. LVCMOS Test Load Board Termination 11-0146 11 02/16/2012 PI6C49014 Networking Clock Generator Packaging Mechanical: 28-Contact TSSOP (L) DOCUMENT CONTROL NO. PD - 1313 REVISION: D 28 DATE: 03/09/05 .169 .177 4.3 4.5 .004 .008 1 .378 .386 9.6 9.8 0.45 0.75 0.09 0.20 .018 .030 .252 BSC 6.4 1 .047 1.20 Max SEATING PLANE .0256 BSC 0.65 .007 .012 0.19 0.30 .002 .006 0.05 0.15 Pericom Semiconductor Corporation 3545 N. 1st Street, San Jose, CA 95134 1-800-435-2335 • www.pericom.com Note: 1. Package Outline Exclusive of Mold Flash and Metal Burr 2. Controlling dimentions in millimeters 3. Ref: JEDEC MO-153F/AE DESCRIPTION: 28-Pin, 173-Mil Wide, TSSOP PACKAGE CODE: L Ordering Information(1-3) Ordering Code Package Code PI6C49014LIE L Package Description 28pin TSSOP Notes: 1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ 2. E = Pb-free and Green 3. Adding an X suffix = Tape/Reel 11-0146 12 02/16/2012