PI6C49004A

PI6C49004A
PCIe® Gen 2 Networking Clock Generator
Description
Features
The PI6C49004A is a clock generator device intended for PCIe®
Gen2 networking applications. The device includes twelve
100MHz differential Host Clock Signal Level (HCSL) outputs
for PCIe Gen 2, two single-ended 50MHz outputs, one singleended 32.256MHz output, and one selectable single-ended
33/66/133MHz output.
• 3.3V +/-10% Supply Voltage
• Uses 25MHz xtal such as Saronix-eCera™ SRX7278
• Twelve PCIe® Gen. 2 100MHz HCSL outputs with optional
-0.5% spread spectrum support
• Two LVCMOS 50MHz outputs that support +/- 10%
frequency margining
• One frequency selectable 33/66/133MHz LVCMOS output
• One 32.256MHz LVCMOS output
• Industrial temperature -40°C to 85°C
• Package: 56-pin TSSOP package
Using a serially programmable SMBUS interface, the PI6C49004A
incorporates spread spectrum modulation on the twelve 100MHz
HCSL PCIe Gen 2 outputs, and independent frequency margining
on the 50MHz output, 33.3333MHz and 66.6666MHz clock
outputs.
Pin Configuration
Block Diagram
VDD
12
25 MHz
crystal or
clock input
Clock Buffer/
Crystal
Oscillator
12
2
PLL, Dividers,
Buffers, and
Logic
100M_OUT(0-11)
50M_OUT(1-2)
33/66/133M_OUT1
SCLK
32.256M_OUT1
SDATA
PD_RESET
8
GND
11-0104
ISET
475 Ohms
1%
1
VDD
1
56
GND
IREF
2
55
VDD
NC
3
54
100M_Q0-
100M_Q11-
4
53
100M_Q0+
100M_Q11+
5
52
100M_Q1+
100M_Q10-
6
51
100M_Q1-
100M_Q10+
7
50
VDD
VDD
8
49
GND
VDD
9
48
VDD
GND
10
47
100M_Q2+
100M_Q9-
11
46
100M_Q2-
100M_Q9+
12
45
100M_Q3+
100M_Q8-
13
44
100M_Q3-
100M_Q8+
14
43
100M_Q4+
100M_Q7-
15
42
100M_Q4-
100M_Q7+
16
41
100M_Q5+
SCLK
17
40
100M_Q5-
SDATA
18
39
VDD
GND
19
38
GND
50M_OUT1
20
37
VDD
50M_OUT2
21
36
100M_Q6+
VDD
22
35
100M_Q6-
GND
23
34
33/66/133M_OUT1
VDD
24
33
VDD
32.256M_OUT1
25
32
GND
GND
26
31
VDD
NC
27
30
X2
PD_RESET
28
29
X1
PS-01
04/19/11
PI6C49004A
PCIe® Gen 2 Networking Clock Generator
Pin Description
Pin # Pin Name
Pin Type
Pin Description
1
VDD
Power
3.3V Supply Pin
2
IREF
Output
Connect to 475-Ohm resistor to set HCSL output drive current
3
NC
4
100M_Q11-
Output
100MHz HCSL output
5
100M_Q11+
Output
100MHz HCSL output
6
100M_Q10-
Output
100MHz HCSL output
7
100M_Q10+
Output
100MHz HCSL output
8
VDD
Power
3.3V Supply Pin
9
VDD
Power
3.3V Supply Pin
10
GND
Power
Ground
11
100M_Q9-
Output
100MHz HCSL output
12
100M_Q9+
Output
100MHz HCSL output
13
100M_Q8-
Output
100MHz HCSL output
14
100M_Q8+
Output
100MHz HCSL output
15
100M_Q7-
Output
100MHz HCSL output
16
100M_Q7+
Output
100MHz HCSL output
17
SCLK
Input
SMBus compatible input clock. Supports fast mode 400kHz input clock.
18
SDATA
I/O
SMBus compatible data line
19
GND
Power
Ground
20
50M_Out1
Output
50MHz LVCMOS output. When disabled, output is trisated and has a nominal 110kOhm pull-down.
21
50M_Out2
Output
50MHz LVCMOS output. When disabled, output is trisated and has a nominal
110kOhm pull-down.
22
VDD
Power
3.3V Supply Pin
23
GND
Power
Ground
24
VDD
Power
3.3V Supply Pin
25
32.256M_Out1
Output
32.256MHz LVCMOS output. When disabled, output is trisated and has a nominal
110k-Ohm pull-down.
26
GND
Power
GND
27
NC
28
PD_RESET
Input
Power down reset - when low all PLL's are powered down and outputs tristated.
SMBus registers are reset to default values. When Byte0-Bit 6 = 0 (Hardware Control
Mode) PD RESET = high, all outputs are enabled
29
X1
Input
Crystal input. Integrated 6pF capacitance
30
X2
Output
Crystal output. Integrated 6pF capacitance
31
VDD
Power
3.3V Supply Pin
Power
GND
32
GND
(Continued)
11-0104
No connect. Leave open
No connect. Leave open
2
PS-01
04/19/11
PI6C49004A
PCIe® Gen 2 Networking Clock Generator
Pin Description (Cont..)
Pin #
Pin Name
Pin Type
Pin Description
33
VDD
Power
Connect to 3.3V
34
33/66/133M_Out1
Output
33/66/133MHz selectable LVCMOS output. When disabled, output is trisated and has
a nominal 110k-Ohm pull-down.
35
100M_Q6-
Output
100MHz HCSL output
36
100M_Q6+
Output
100MHz HCSL output
37
VDD
Power
3.3V Supply Pin
38
GND
Power
Ground
39
VDD
Power
3.3V Supply Pin
40
100M_Q5-
Output
100MHz HCSL output
41
100M_Q5+
Output
100MHz HCSL output
42
100M_Q4-
Output
100MHz HCSL output
43
100M_Q4+
Output
100MHz HCSL output
44
100M_Q3-
Output
100MHz HCSL output
45
100M_Q3+
Output
100MHz HCSL output
46
100M_Q2-
Output
100MHz HCSL output
47
100M_Q2+
Output
100MHz HCSL output
48
VDD
Power
3.3V Supply Pin
49
GND
Power
Ground
50
VDD
Power
3.3V Supply Pin
51
100M_Q1-
Output
100MHz HCSL output
52
100M_Q1+
Output
100MHz HCSL output
53
100M_Q0-
Output
100MHz HCSL output
54
100M_Q0+
Output
100MHz HCSL output
55
VDD
Power
3.3V Supply Pin
56
GND
Power
Ground
11-0104
3
PS-01
04/19/11
PI6C49004A
PCIe® Gen 2 Networking Clock Generator
50MHz Frequency Margining Table
FS3
FS2
FS1
FS0
50M_OUT1, 50M_OUT2
0
0
0
0
nominal
0
0
0
1
nominal + 1%
0
0
1
0
nominal + 2%
0
0
1
1
nominal + 3%
0
1
0
0
nominal + 4%
0
1
0
1
nominal + 5%
0
1
1
0
nominal + 6%
0
1
1
1
nominal + 8%
1
0
0
0
nominal + 10%
1
0
0
1
nominal - 1%
1
0
1
0
nominal - 2%
1
0
1
1
nominal - 3%
1
1
0
0
nominal - 4%
1
1
0
1
nominal - 6%
1
1
1
0
nominal - 8%
1
1
1
1
nominal - 10%
33/66/133 MHz Frequency Margining Table
FS6
FS5
FS4
33M/66M/133M_OUT1
0
0
0
33.3333MHz
0
0
1
66.6666MHz +2%
0
1
0
66.6666MHz +1%
0
1
1
66.6666MHz +0%
1
0
0
66.6666MHz -2%
1
0
1
66.6666MHz -4%
1
1
0
66.6666MHz -6%
1
1
1
133.3333MHz
11-0104
4
PS-01
04/19/11
PI6C49004A
PCIe® Gen 2 Networking Clock Generator
Serial Data Interface (SMBus)
PI6C49004A is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7-bit address and read/write bit as shown below.
Address Assignment
A6
A5
A4
A3
A2
A1
A0
R/W
1
1
0
1
0
0
1
0/1
How to Write
1 bit
8 bits
1
8 bits
1
8 bits
1
8 bits
1
Start
bit
D2H
Ack
Register
offset
Ack
Byte Count
=N
Ack
Data Byte
0
Ack
Note:
1.
…
8 bits
1
1 bit
Data Byte
N-1
Ack
Stop bit
Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0.
How to Read (M: abbreviation for Master or Controller; S: abbreviation for slave/clock)
1 bit
M:
Start
bit
8 bits
M: Send
"D2h"
1 bit
S:
sends
Ack
8 bits
M: send
starting
databyte
location:
N
1 bit
S:
sends
Ack
1 bit
M:
Start
bit
8 bits
M:
Send
"D3h"
1 bit
8 bits
S:
sends
Ack
S:
sends #
of data
bytes
that
will be
sent: X
1 bit
8 bits
1 bit
M:
sends
Ack
S:
sends
starting
data
byte
N
M:
sends
Ack
…
8 bits
1 bit
1 bit
…
S:
sends
data
byte
N+X-1
M: Not
Acknowledge
M:
Stop
bit
Byte 0: Spread Spectrum Control Register
Output(s)
Affected
Bit
Description
Type
Power Up
Condition
7
Spread Spectrum Selection for 100MHz HCSL PCIExpress clocks
RW
0
All 100MHz HCSL
PCI Express outputs
6
Enables hardware or software control of OE bits (see
Byte 0–Bit 6 and Bit 5 Functionality table)
RW
0
PD_RESET pin, bit 5
RW
1
All outputs
5
Software PD_RESET bit. Enables or disables all outputs
(see Byte 0–Bit 6 and Bit 5 Functionality table)
4
Frequency margining select bit FS3
RW
1
3
Frequency margining select bit FS2
RW
0
2
Frequency margining select bit FS1
RW
1
1
Frequency margining select bit FS0
RW
0
0
OE for single-ended 50MHz output 50M_Out2
RW
1
11-0104
5
50M_Out1 and 50M_
Out2
Single-ended 50MHz
output 50M_Out2
Notes
0=spread off
1 = -0.5% down spread
0 = hardware cntl
1 = software ctrl
0 = disabled
1 = enabled
See 50MHz Frequency
Margining Table on
Page 3
0 = disabled
1 = enabled
PS-01
04/19/11
PI6C49004A
PCIe® Gen 2 Networking Clock Generator
Byte 0 - Bit 6 and Bit 5 Functionality
Bit 6
Bit 5
Description
0
X
(PD_RESET = "H" will enable all outputs; SMBus cannot control each output.)
1
0
Disables all outputs and tri-states the outputs, PD_RESET HW pin/signal = DO NOT CARE
1
1
Enable outputs according to the SMBus default values; SMBus can control each output.
PD_RESET HW pin/signal = DON'T CARE
Byte 1: Control Register
Bit
Description
Type
Power Up Condition
Output(s) Affected
7
OE for 32.256M_Out1
RW
1
32.256M_Out1
6
OE for 50M_Out1
RW
1
50M_Out1
5
OE for 33/66/133M_Out1
RW
1
33/66/133M_Out1
4
OE for 100M_Q11 HCSL output
RW
1
100M_Q11
3
OE for 100M_Q10 HCSL output
RW
0
100M_Q10
2
OE for 100M_Q09 HCSL output
RW
0
100M_Q9
1
OE for 100M_Q08 HCSL output
RW
0
100M_Q8
0
OE for 100M_Q07 HCSL output
RW
0
100M_Q7
Output(s) Affected
Notes
33/66/133M_Out1
See 33/66/133MHz
Frequency Margining Table on Page 3
Notes
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
Byte 2: Control Register
Bit
Description
Type
Power Up Condition
7
Frequency margining select bit FS6
RW
1
6
Frequency margining select bit FS5
RW
0
5
Frequency margining select bit FS4
RW
0
4 to 0
Reserved
R
Undefined
11-0104
6
Not Applicable
PS-01
04/19/11
PI6C49004A
PCIe® Gen 2 Networking Clock Generator
Byte 3: Control Register
Bit
Description
Type
Power Up
Condition
Output(s) Affected
7
OE for 100M_Q6 HCSL Output
RW
0
100M_Q6
6
OE for 100M_Q5 HCSL Output
RW
0
100M_Q5
5
OE for 100M_Q4 HCSL Output
RW
0
100M_Q4
4
OE for 100M_Q3 HCSL Output
RW
0
100M_Q3
3
OE for 100M_Q2 HCSL Output
RW
0
100M_Q2
2
OE for 100M_Q1 HCSL Output
RW
1
100M_Q1
1
OE for 100M_Q0 HCSL Output
RW
1
100M_Q0
0
Reserved
R
Undefined
Not Applicable
Notes
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
Byte 4 & 5: Control Register
Bit
Description
Type
Power Up Condition
7 to 0
Reserved
R
Undefined
Not Applicable
Output(s) Affected
Notes
Byte 6: Control Register
Bit
Description
Type
Power Up Condition
Output(s) Affected
7
Revivsion ID bit 3
R
0
Not Applicable
6
Revivsion ID bit 2
R
0
Not Applicable
5
Revivsion ID bit 1
R
0
Not Applicable
4
Revivsion ID bit 0
R
0
Not Applicable
3
Vendor ID bit 3
R
0
Not Applicable
2
Vendor ID bit 2
R
0
Not Applicable
1
Vendor ID bit 1
R
1
Not Applicable
0
Vendor ID bit 0
R
1
Not Applicable
11-0104
7
Notes
PS-01
04/19/11
PI6C49004A
PCIe® Gen 2 Networking Clock Generator
Absolute Maximum Ratings1 (Over operating free-air temperature range)
Symbol
Parameters
Min.
Max.
VDD
3.3V I/O Supply Voltage
-0.5
4.6
VIH
Input High Voltage
VIL
Input Low Voltage
-0.5
Ts
Storage Temperature
-65
VESD
ESD Protection
2000
Units
4.6
V
150
°C
V
Note:
1. Stress beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
Maximum Ratings
(Above which useful life may be impaired. For user guidelines, not tested.)
Maximum Supply Voltage, VDD............................................................. 7V
All Inputs and Outputs................................................–0.5V to VDD +0.5V
Ambient Operating Temperature........................................ –40°C to +85°C
Storage Temperature......................................................... –65°C to +150°C
Junction Temperature.........................................................................125°C
Peak Soldering Temperature..............................................................260°C
Note:
Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is
a stress rating only and functional operation of the device
at these or any other conditions above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC Electrical Characteristics
Unless otherwise specified, VDD=3.3V±10%, Ambient Temperature –40°C to +85°C
Parameter
Symbol
Operating Supply
Voltage
VDD
3.0
3.6
Input High Voltage
VIH
2
VDD
Input Low Voltage
VIL
–0.3
0.8
Input High Voltage
VIH
SDATA, SCLK
0.7VDD
VDD
Input Low Voltage
VIL
SDATA, SCLK
Operating Supply Current
IDD
Min
Typ
Max
Units
V
0.3VDD
320
mA
IDD at Output Disable
Condition
Internal Pull-Up/PullDown Resistor
R PU/R PD
Input Capacitance
CIN
11-0104
Conditions
PD_RESET = 0
3.0
PD_RESET
216
All single-ended outputs
75
All input pins
6
8
k–Ohm
pF
PS-01
04/19/11
PI6C49004A
PCIe® Gen 2 Networking Clock Generator
Electrical Characteristics - Single-Ended
Unless otherwise specified, VDD=3.3V±10%, Ambient Temperature –40°C to +85°C
Parameter
Symbol
Input Clock Frequency
FIN
Conditions
Min
100
Minimum Pulse Width
of PD_RESET Input
FS0, FS6 = 0
Output Frequency
Error
32.256MHz
400
kHz
ns
0
tr, tf
7
VDD=3.3V, 0.8V to 2.4V
Measured at VDD/2
45
High-Level Output
Voltage
VOH
IOH = -4mA
VDD-0.4
High-Level Output
Voltage
VOH
IOH = -8mA
2.4
Low-Level Output
Voltage
VOL
IOL = 8mA
0.5
1
ns
50
55
%
V
0.4
50MHz clock output
140
200
33/66/133MHz clock output
125
175
32.256MHz clock output
115
150
50MHz clock output
120
175
33/66/133 MHz clock output
120
160
Clock Stabilization
Time from Power Up
11-0104
MHz
ppm
Output Clock Duty
Cycle
Cycle-to-Cycle Jitter
Units
100
Output Frequency
Error
Peak-to-Peak Jitter
Max
25
SCLK Frequency
Output Rise/Fall Time
Typ
3
9
ps
10
ms
PS-01
04/19/11
PI6C49004A
PCIe® Gen 2 Networking Clock Generator
Electrical Characteristics - 100MHz Differential HCSL Outputs
Unless otherwise specified, VDD=3.3V±10%, Ambient Temperature –40°C to +85°C
Parameter
Symbol
Conditions
Min
Typ
Output Frequency
Cycle-to-Cycle Jitter
PCIe 2.0 RMS Phase
Jitter
JRMS2.0
MHz
ps
86
PCIe 2.0 Test Method @
100MHz Output
3.1
ps
0
%
-0.5
Spread Modulation
Frequency
32
45
TDC
Rising/Falling Edge
Rate
100
Using PCIe jitter measurement method
Spread Modulation
Percentage
Duty Cycle
Units
150
TCC/Jitter
Peak-to-Peak Phase
Jitter
Max
Note 3, 4
50
0.6
VT = 50%(measurement
threshold)
kHz
55
%
4.5
V/ns
200
ps
Output Skew
TOSKEW
Clock Source DC Impedance, single ended
ZC-DC
High-Level Output
Voltage
VOH
Low-Level Output
Voltage
VOL
–0.20
0
0.05
IOH @ 6*IREF
IOH
–13
–14.2
-18.5
mA
Absolute Crossing
Point Voltage
VCROSS
Note 2, 5, 6
0.55
V
Variation of VCROSS
over all rising clock
edges
VCROSS Delta
Note 2, 5, 8
140
mV
Average Clock Period
Accuracy
TPERIOD AVG Note 3, 9, 10
–300
2800
ppm
9.847
10.203
ns
Absolute Period
(including jitter and
spread spectrum)
(Continued)
11-0104
TPERIOD ABS
50
Note 2, (RS=33-Ohm,
RT=50-Ohm)
0.65
0.71
Ohm
0.95
V
0.25
Note 3, 7
10
PS-01
04/19/11
PI6C49004A
PCIe® Gen 2 Networking Clock Generator
Notes:
1. Measured at the end of an 8-inch trace with a 5pF load.
2. Measurement taken from a single-ended waveform.
3. Measurement taken from a differential waveform.
4. Measured from -150 mV to +150 mV on the differential waveform. The signal is monotonic through the measurement region for rise and fall time. The 300 mV measurement window is centered on the differential zero crossing.
5. Measured at crossing point where the instantaneous voltage value of the rising edge of 100M+ equals the falling edge 100M–.
6. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement.
7. Defines as the absolute minimum or maximum instantaneous period. This includes cycle-to-cycle jitter, relative PPM tolerance, and spread spectrum modulation.
8. Defined as the total variation of all crossing voltages of rising 100M+ and falling 100M–.
9. Refer to section 4.3.2.1 of the PCI Express Base Specification, Revision 1.1 for information regarding PPM considerations.
10. 10) PPM refers to parts per million and is a DC absolute period accuracy specification. 1 PPM is 1/1,000,000th of 100 MHz exactly or 100 Hz. For 300 PPM
there is an error budget of 100Hz/PPM * 300 PPM = 30 kHz. The period is measured with a frequency counter with measurement window set at 100 ms or
greater. With spread spectrum turned off the error is less than ±300 ppm. With spread spectrum turned on there is an additional +2500 PPM nominal shift in
maximum period resulting from the -0.5% down spread.
Crystal Load Capacitors
If an input crystal is used, crystal should be connected from pins X1 to ground and X2 to ground to optimize the accuracy of the
output frequency.
CL = Crystal's load capacitance in pF
Crystal Capacitors (pF) = (CL - 8) *2
For example, for a crystal with a 18pF load cap, each external crystal cap would be 18pF. (18 - 8) *2 =18.
Application Notes
Crystal circuit connection
The following diagram shows PI6LC4830-01 crystal circuit connection with a parallel crystal. For the
CL=18pF crystal, it is suggested to use C1= 27pF, C2= 33pF. C1 and C2 can be adjusted to fine tune to the
target ppm of crystal oscillator according to different board layouts.
Crystal Oscillator Circuit
XTAL_IN
C1
27pF
SaRonix-eCera
CG2500003
Crystal�(CL�=�18pF)
XTAL_OUT
C2
33pF
11-0104
11
PS-01
04/19/11
PI6C49004A
PCIe® Gen 2 Networking Clock Generator
Recommended Crystal Specification
Pericom recommends:
a) GC2500003 XTAL 49S/SMD(4.0 mm), 25M, CL=18pF, +/-30ppm, http://www.pericom.com/pdf/datasheets/se/GC_GF.pdf
b) FY2500081, SMD 5x3.2(4P), 25M, CL=18pF, +/-30ppm, http://www.pericom.com/pdf/datasheets/se/FY_F9.pdf
c) FL2500047, SMD 3.2x2.5(4P), 25M, CL=18pF, +/-20ppm, http://www.pericom.com/pdf/datasheets/se/FL.pdf
Configuration test load board termination for HCSL Outputs
Rs
33Ω
5%
PI6C49004A
Clock
TLA
Rs
33Ω
5%
Clock#
TLB
475Ω
1%
Rp
49.9Ω
1%
Rp
49.9Ω
1%
2pF
5%
2pF
5%
Figure 4. Configuration Test Load Board Termination
11-0104
12
PS-01
04/19/11
PI6C49004A
PCIe® Gen 2 Networking Clock Generator
1
DATE: 09/11/06
Notes:
1. Controlling dimensions in millimeters.
2. Ref: JEDEC MO-153F/EE
3. Package Outline Exclusive of Mold Flash and Metal Burr
DESCRIPTION: 56-pin, 240-mil wide TSSOP
PACKAGE CODE: A56
DOCUMENT CONTROL #: PD-1502
REVISION: M
06-0736
Note:
For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php
Ordering Information(1-3)
Ordering Code
Package Code
Package Description
PI6C49004AAE
A
56-pin, Pb-free & Green, TSSOP, (A56)
Notes:
1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
2. E = Pb-free and Green
3. Adding an X suffix = Tape/Reel
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
11-0104
All trademarks are property of their respective owners.
13
PS-01
04/19/11