Datasheet

PI6C49003A
PCIe® Gen 2 Networking Clock Generator
Description
Features
• 3.3V +/-10% Supply Voltage
• Uses 25MHz xtal
• Five PCIe® Gen. 2 100MHz HCSL outputs with optional
-0.5% spread spectrum support
• Two LVCMOS 50MHz outputs that support +/- 10%
frequency margining
• One frequency selectable 33/66/133MHz LVCMOS output
• One 32.256MHz LVCMOS output
• Industrial temperature -40°C to 85°C
• Package: 48-pin TSSOP package
The PI6C49003A is a clock generator device intended for PCIe®
Gen2 networking applications. The device includes five 100MHz
differential Host Clock Signal Level (HCSL) outputs for PCIe Gen
2, two single-ended 50MHz outputs, one single-ended 32.256MHz
output, and one selectable single-ended 33/66/133MHz output.
Block Diagram
Pin Configuration
Using a serially programmable SMBUS interface, the PI6C49003A
incorporates spread spectrum modulation on the twelve 100MHz
HCSL PCIe Gen 2 outputs, and independent frequency margining
on the 50MHz output, 33.3333MHz and 66.6666MHz clock
outputs.
VDD
14
25 MHz
crystal or
clock input
Clock Buffer/
Crystal
Oscillator
5
100M_OUT(0-4)
50M_OUT(1-2)
PLL, Dividers,
Buffers, and
Logic
33/66/133M_OUT1
SCLK
32.256M_OUT1
SDATA
PD_RESET
10
GND
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ISET
475 Ohms
1%
14-0198
1
VDD
1
48
GND
IREF
2
47
VDD
NC
3
46
100M_Q0-
NC
4
45
100M_Q0+
VDD
5
44
100M_Q1+
VDD
6
43
100M_Q1-
GND
7
42
VDD
GND
8
41
GND
VDD
9
40
VDD
GND
10
39
100M_Q2+
VDD
11
38
100M_Q2-
SCLK
12
37
100M_Q3+
SDATA
13
36
100M_Q3-
GND
14
35
VDD
50M_Out1
15
34
GND
50M_Out2
16
33
VDD
VDD
17
32
100M_Q4+
GND
18
31
100M_Q4-
VDD
19
30
33/66/133M_Out1
32.256M_Out1
20
29
VDD
GND
21
28
GND
NC
22
27
VDD
NC
23
26
X2
PD_RESET
24
25
X1
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PI6C49003A
PCIe® Gen 2 Networking Clock Generator
Pin Description
Pin #
Pin Name
Pin Type
Pin Description
1
VDD
Power
3.3V Supply Pin
2
IREF
Output
Connect to 475-Ohm resistor to set HCSL output drive current
3
NC
No connect. Leave open
4
NC
No connect. Leave open
5
VDD
Power
3.3V Supply Pin
6
VDD
Power
3.3V Supply Pin
7
GND
Power
Ground
8
GND
Power
Ground
9
VDD
Power
3.3V Supply Pin
10
GND
Power
Ground
11
VDD
Power
3.3V Supply Pin
12
SCLK
Input
SMBus compatible input clock. Supports fast mode 400kHz input clock.
13
SDATA
I/O
SMBus compatible data line
14
GND
Power
Ground
15
50M_Out1
Output
50MHz LVCMOS output. When disabled, output is trisated and has a nominal 110kOhm pull-down.
16
50M_Out2
Output
50MHz LVCMOS output. When disabled, output is trisated and has a nominal 110kOhm pull-down.
17
VDD
Power
3.3V Supply Pin
18
GND
Power
Ground
19
VDD
Power
3.3V Supply Pin
20
32.256M_Out1
Output
32.256MHz LVCMOS output. When disabled, output is trisated and has a nominal
110k-Ohm pull-down.
21
GND
Power
Ground
22
NC
23
NC
24
PD_RESET
Input
Power down reset - when low all PLL's are powered down and outputs tristated.
SMBus registers are reset to default values.
25
X1
Input
Crystal input. Integrated 6pF capacitance
26
X2
Output
Crystal output. Integrated 6pF capacitance
27
VDD
Power
3.3V Supply Pin
28
GND
Power
Ground
29
VDD
Power
3.3V Supply Pin
30
33/66/133M_Out1
Output
33/66/133MHz selectable LVCMOS output. When disabled, output is trisated and has
a nominal 110k-Ohm pull-down.
31
100M_Q4-
Output
100MHz HCSL output
32
100M_Q4+
Output
100MHz HCSL output
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PI6C49003A
PCIe® Gen 2 Networking Clock Generator
Pin Description (Cont..)
Pin #
Pin Name
Pin Type
Pin Description
33
VDD
Power
3.3V Supply Pin
34
GND
Power
Ground
35
VDD
Power
3.3V Supply Pin
36
100M_Q3-
Output
100MHz HCSL output
37
100M_Q3+
Output
100MHz HCSL output
38
100M_Q2-
Output
100MHz HCSL output
39
100M_Q2+
Output
100MHz HCSL output
40
VDD
Power
3.3V Supply Pin
41
GND
Power
Ground
42
VDD
Power
3.3V Supply Pin
43
100M_Q1-
Output
100MHz HCSL output
44
100M_Q1+
Output
100MHz HCSL output
45
100M_Q0+
Output
100MHz HCSL output
46
100M_Q0-
Output
100MHz HCSL output
47
VDD
Power
3.3V Supply Pin
48
GND
Power
Ground
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PI6C49003A
PCIe® Gen 2 Networking Clock Generator
50MHz Frequency Margining Table
33/66/133MHz Frequency Margining
Table
FS3
FS2
FS1
FS0
50M_OUT1, 50M_OUT2
0
0
0
0
nominal
FS6
FS5
FS4
33M/66M/133M_OUT1
0
0
0
1
nominal + 1%
0
0
0
33.3333MHz
0
0
1
0
nominal + 2%
0
0
1
66.6666MHz +2%
0
0
1
1
nominal + 3%
0
1
0
66.6666MHz +1%
0
1
0
0
nominal + 4%
0
1
1
66.6666MHz +0%
0
1
0
1
nominal + 5%
1
0
0
66.6666MHz -2%
0
1
1
0
nominal + 6%
1
0
1
66.6666MHz -4%
0
1
1
1
nominal + 8%
1
1
0
66.6666MHz -6%
1
0
0
0
nominal + 10%
1
0
0
1
nominal - 1%
1
1
1
133.3333MHz
1
0
1
0
nominal - 2%
1
0
1
1
nominal - 3%
1
1
0
0
nominal - 4%
1
1
0
1
nominal - 6%
1
1
1
0
nominal - 8%
1
1
1
1
nominal - 10%
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PI6C49003A
PCIe® Gen 2 Networking Clock Generator
Serial Data Interface (SMBus)
PI6C49003A is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7-bit address and read/write bit as shown below.
Address Assignment
A6
A5
A4
A3
A2
A1
A0
W/R
1
1
0
1
0
0
1
0/1
How to Write
1 bit
8 bits
1
8 bits
1
8 bits
1
8 bits
1
Start
bit
D2H
Ack
Register
offset
Ack
Byte Count
=N
Ack
Data Byte
0
Ack
…
8 bits
1
1 bit
Data Byte
N-1
Ack
Stop bit
Note:
1. Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0.
How to Read (M: abbreviation for Master or Controller; S: abbreviation for slave/clock)
1 bit
M:
Start
bit
8 bits
M: Send
"D2h"
1 bit
S:
sends
Ack
8 bits
M: send
starting
databyte
location:
N
1 bit
S:
sends
Ack
1 bit
M:
Start
bit
8 bits
M:
Send
"D3h"
1 bit
8 bits
S:
sends
Ack
S:
sends #
of data
bytes
that
will be
sent: X
1 bit
8 bits
1 bit
M:
sends
Ack
S:
sends
starting
data
byte
N
M:
sends
Ack
…
8 bits
1 bit
1 bit
…
S:
sends
data
byte
N+X-1
M: Not
Acknowledge
M:
Stop
bit
Byte 0: Spread Spectrum Control Register
Output(s)
Affected
Bit
Description
Type
Power Up
Condition
7
Spread Spectrum Selection for 100MHz HCSL PCIExpress clocks
RW
0
All 100MHz HCSL
PCI Express outputs
6
Enables hardware or software control of OE bits (see
Byte 0–Bit 6 and Bit 5 Functionality table)
RW
0
PD_RESET pin, bit 5
RW
1
All outputs
5
Software PD_RESET bit. Enables or disables all outputs
(see Byte 0–Bit 6 and Bit 5 Functionality table)
4
Frequency margining select bit FS3
RW
1
3
Frequency margining select bit FS2
RW
0
2
Frequency margining select bit FS1
RW
1
1
Frequency margining select bit FS0
RW
0
0
OE for single-ended 50MHz output 50M_Out2
RW
1
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5
50M_Out1 and 50M_
Out2
Single-ended 50MHz
output 50M_Out2
Notes
0=spread off
1 = -0.5% down spread
0 = hardware cntl
1 = software ctrl
0 = disabled
1 = enabled
See 50MHz Frequency
Margining Table on
Page 3
0 = disabled
1 = enabled
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PI6C49003A
PCIe® Gen 2 Networking Clock Generator
Byte 0 - Bit 6 and Bit 5 Functionality
Bit 6
Bit 5
Description
0
X
(PD_RESET = "H" will enable all outputs; SMBus cannot control each output.)
1
0
Disables all outputs and tri-states the outputs, PD_RESET HW pin/signal = DO NOT CARE
1
1
Enable outputs according to the SMBus default values; SMBus can control each output.
PD_RESET HW pin/signal = DON'T CARE
Byte 1: Control Register
Bit
Description
Type
Power Up Condition
Output(s) Affected
7
OE for 32.256M_Out1
RW
1
32.256M_Out1
6
OE for 50M_Out1
RW
1
50M_Out1
5
OE for 33/66/133M_Out1
RW
1
33/66/133M_Out1
4
OE for 100M_Q11 HCSL output
RW
1
100M_Q11
3
OE for 100M_Q10 HCSL output
RW
0
100M_Q10
2
OE for 100M_Q09 HCSL output
RW
0
100M_Q9
1
OE for 100M_Q08 HCSL output
RW
0
100M_Q8
0
OE for 100M_Q07 HCSL output
RW
0
100M_Q7
Output(s) Affected
Notes
33/66/133M_Out1
See 33/66/133MHz
Frequency Margining Table on Page 3
Notes
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
Byte 2: Control Register
Bit
Description
Type
Power Up Condition
7
Frequency margining select bit FS6
RW
1
6
Frequency margining select bit FS5
RW
0
5
Frequency margining select bit FS4
RW
0
4 to 0
Reserved
R
Undefined
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14-0198
6
Not Applicable
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PI6C49003A
PCIe® Gen 2 Networking Clock Generator
Byte 3: Control Register
Bit
Description
Type
Power Up
Condition
Output(s) Affected
7
OE for 100M_Q6 HCSL Output
RW
0
100M_Q6
6
OE for 100M_Q5 HCSL Output
RW
0
100M_Q5
5
OE for 100M_Q4 HCSL Output
RW
0
100M_Q4
4
OE for 100M_Q3 HCSL Output
RW
0
100M_Q3
3
OE for 100M_Q2 HCSL Output
RW
0
100M_Q2
2
OE for 100M_Q1 HCSL Output
RW
1
100M_Q1
1
OE for 100M_Q0 HCSL Output
RW
1
100M_Q0
0
Reserved
R
Undefined
Not Applicable
Notes
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
Byte 4 & 5: Control Register
Bit
Description
Type
Power Up Condition
Output(s) Affected
7 to 0
Reserved
R
Undefined
Not Applicable
Notes
Byte 6: Control Register
Bit
Description
Type
Power Up Condition
Output(s) Affected
7
Revivsion ID bit 3
R
0
Not Applicable
6
Revivsion ID bit 2
R
0
Not Applicable
5
Revivsion ID bit 1
R
0
Not Applicable
4
Revivsion ID bit 0
R
0
Not Applicable
3
Vendor ID bit 3
R
0
Not Applicable
2
Vendor ID bit 2
R
0
Not Applicable
1
Vendor ID bit 1
R
1
Not Applicable
0
Vendor ID bit 0
R
1
Not Applicable
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Notes
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PI6C49003A
PCIe® Gen 2 Networking Clock Generator
Absolute Maximum Ratings1 (Over operating free-air temperature range)
Symbol
Parameters
Min.
Max.
VDD
3.3V I/O Supply Voltage
-0.5
4.6
VIH
Input High Voltage
VIL
Input Low Voltage
-0.5
Ts
Storage Temperature
-65
Units
4.6
V
150
°C
ESD Protection
2000
VESD
Note:
1. Stress beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
V
Maximum Ratings
(Above which useful life may be impaired. For user guidelines, not tested.)
Maximum Supply Voltage, VDD............................................................. 7V
All Inputs and Outputs................................................–0.5V to VDD +0.5V
Ambient Operating Temperature........................................ –40°C to +85°C
Storage Temperature......................................................... –65°C to +150°C
Junction Temperature.........................................................................125°C
Peak Soldering Temperature..............................................................260°C
Note:
Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is
a stress rating only and functional operation of the device
at these or any other conditions above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC Electrical Characteristics
Unless otherwise specified, VDD=3.3V±10%, Ambient Temperature –40°C to +85°C
Symbol
Parameter
Conditions
VDD
Operating Supply Voltage
3.0
3.6
VIH
Input High Voltage
2
VDD
VIL
Input Low Voltage
–0.3
0.8
VIH
Input High Voltage
SDATA, SCLK
0.7VDD
VDD
VIL
Input Low Voltage
SDATA, SCLK
IDD
Operating Supply Current
Typ
R PU/R PD
Internal Pull-Up/Pull-Down Resistor
CIN
Input Capacitance
14-0198
PD_RESET = 0
3.0
PD_RESET
216
All single-ended outputs
75
All input pins
6
8
Max
Units
V
0.3VDD
320
IDD at Output Disable Condition
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Min
mA
k–Ohm
pF
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PI6C49003A
PCIe® Gen 2 Networking Clock Generator
Electrical Characteristics - Single-Ended
Unless otherwise specified, VDD=3.3V±10%, Ambient Temperature –40°C to +85°C
Symbol
Parameter
Conditions
FIN
Input Clock Frequency
25
SCLK Frequency
100
Minimum Pulse Width of PD_RESET
Input
Min
Output Frequency Error
32.256MHz
Output Rise/Fall Time
VDD=3.3V, 0.8V to 2.4V
Output Clock Duty Cycle
Measured at VDD/2
45
VOH
High-Level Output Voltage
IOH = -4mA
VDD-0.4
VOH
High-Level Output Voltage
IOH = -8mA
2.4
VOL
Low-Level Output Voltage
IOL = 8mA
Cycle-to-Cycle Jitter
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14-0198
MHz
400
0
7
ns
50
55
%
140
200
33/66/133MHz clock output
125
175
32.256MHz clock output
115
150
50MHz clock output
120
175
33/66/133 MHz clock output
120
160
9
ppm
1
0.4
3
kHz
0.5
50MHz clock output
Clock Stabilization Time from Power Up
Units
ns
FS0, FS6 = 0
Peak-to-Peak Jitter
Max
100
Output Frequency Error
tr, tf
Typ
10
V
ps
ms
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PI6C49003A
PCIe® Gen 2 Networking Clock Generator
Electrical Characteristics - 100MHz Differential HCSL Outputs
Unless otherwise specified, VDD=3.3V±10%, Ambient Temperature –40°C to +85°C
Symbol
TCC/Jitter
JRMS2.0
TDC
Parameter
Conditions
Min
Typ
Max
Units
Output Frequency
100
MHz
Cycle-to-Cycle Jitter
150
ps
Peak-to-Peak Phase Jitter
Using PCIe jitter measurement method
86
PCIe 2.0 RMS Phase Jitter
PCIe 2.0 Test Method @
100MHz Output
3.1
ps
0
%
Spread Modulation Percentage
-0.5
Spread Modulation Frequency
32
Duty Cycle
45
Rising/Falling Edge Rate
Note 3, 4
TOSKEW
Output Skew
VT = 50%(measurement
threshold)
ZC-DC
Clock Source DC Impedance, single ended
VOH
High-Level Output Voltage
50
0.6
kHz
55
%
4.5
V/ns
200
ps
50
Note 2, (RS=33-Ohm,
RT=50-Ohm)
0.65
0.71
Ohm
0.95
V
VOL
Low-Level Output Voltage
–0.20
0
0.05
IOH
IOH @ 6*IREF
–13
–14.2
-18.5
mA
VCROSS
Absolute Crossing Point Voltage
Note 2, 5, 6
0.55
V
VCROSS Delta
Variation of VCROSS over all rising clock
edges
Note 2, 5, 8
140
mV
TPERIOD AVG Average Clock Period Accuracy
TPERIOD ABS
Absolute Period (including jitter and spread
spectrum)
0.25
Note 3, 9, 10
–300
2800
ppm
Note 3, 7
9.847
10.203
ns
Notes:
1. Measured at the end of an 8-inch trace with a 5pF load.
2. Measurement taken from a single-ended waveform.
3. Measurement taken from a differential waveform.
4. Measured from -150 mV to +150 mV on the differential waveform. The signal is monotonic through the measurement region for rise and fall time. The 300 mV measurement window is centered on the differential zero crossing.
5. Measured at crossing point where the instantaneous voltage value of the rising edge of 100M+ equals the falling edge 100M–.
6. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement.
7. Defines as the absolute minimum or maximum instantaneous period. This includes cycle-to-cycle jitter, relative PPM tolerance, and spread spectrum modulation.
8. Defined as the total variation of all crossing voltages of rising 100M+ and falling 100M–.
9. Refer to section 4.3.2.1 of the PCI Express Base Specification, Revision 1.1 for information regarding PPM considerations.
10. PPM refers to parts per million and is a DC absolute period accuracy specification. 1 PPM is 1/1,000,000th of 100 MHz exactly or 100 Hz. For 300 PPM there
is an error budget of 100Hz/PPM * 300 PPM = 30 kHz. The period is measured with a frequency counter with measurement window set at 100 ms or greater.
With spread spectrum turned off the error is less than ±300 ppm. With spread spectrum turned on there is an additional +2500 PPM nominal shift in maximum
period resulting from the -0.5% down spread.
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PI6C49003A
PCIe® Gen 2 Networking Clock Generator
Crystal Load Capacitors
If an input crystal is used, crystal should be connected from pins X1 to ground and X2 to ground to optimize the accuracy of the
output frequency.
CL = Crystal's load capacitance in pF
Crystal Capacitors (pF) = (CL - 8) *2
For example, for a crystal with a 18pF load cap, each external crystal cap would be 18pF. (18 - 8) *2 =18.
Application Notes
Crystal circuit connection
The following diagram shows PI6LC4830-01 crystal circuit connection with a parallel crystal. For the CL=18pF crystal, it is suggested to use C1= 27pF, C2= 33pF. C1 and C2 can be adjusted to fine tune to the target ppm of crystal oscillator according to different
board layouts.
Crystal Oscillator Circuit
XTAL_IN
C1
27pF
SaRonix-eCera
CG2500003
Crystal�(CL�=�18pF)
XTAL_OUT
C2
33pF
Recommended Crystal Specification
Pericom recommends:
a) GC2500003 XTAL 49S/SMD(4.0 mm), 25M, CL=18pF, +/-30ppm, http://www.pericom.com/pdf/datasheets/se/GC_GF.pdf
b) FY2500081, SMD 5x3.2(4P), 25M, CL=18pF, +/-30ppm, http://www.pericom.com/pdf/datasheets/se/FY_F9.pdf
c) FL2500047, SMD 3.2x2.5(4P), 25M, CL=18pF, +/-20ppm, http://www.pericom.com/pdf/datasheets/se/FL.pdf
Configuration test load board termination for HCSL Outputs
Rs
33Ω
5%
PI6C49003A
Clock
TLA
Rs
33Ω
5%
Clock#
TLB
475Ω
1%
Rp
49.9Ω
1%
Rp
49.9Ω
1%
2pF
5%
2pF
5%
Figure 4. Configuration Test Load Board Termination
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PI6C49003A
PCIe® Gen 2 Networking Clock Generator
Packaging Mechanical: 48-Contact TSSOP(A)
DOCUMENT CONTROL NO.
PD - 1501
48
REVISION: G
DATE: 03/09/05
.236
.244
6.0
6.2
See Note 4
1
.488 12.4
.496 12.6
See Note 3
.047
1.20 Max
SEATING PLANE
1
.004 0.09
.008 0.20
X.XX
X.XX
.0197
BSC
0.50
DENOTES DIMENSIONS
IN MILLIMETERS
.002
.006
0.05
0.15
.007
.010
0.17
0.27
Note:
1. Controlling dimensions in millimeters.
2. Ref: JEDEC MO-153F/ED
3. Dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions and gate burrs shall not exceed 0.15mm per side.
4. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion
shall not exceed 0.25mm per side.
0.45 .018
0.75 .030
.319
BSC
8.1
Pericom Semiconductor Corporation
3545 N. 1st Street, San Jose, CA 95134
1-800-435-2335 • www.pericom.com
DESCRIPTION: 48-Pin 240-Mil Wide TSSOP
PACKAGE CODE: A
Note: For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php
Ordering Information(1-3)
Ordering Code
Package Code
Package Description
PI6C49003AAE
A
48-pin, 240-Mil Wide (TSSOP)
Notes:
1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
2. E = Pb-free and Green
3. Adding an X suffix = Tape/Reel
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
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