PI2EQX5864C

PI2EQX5864C
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™
with Equalization, Emphasis, &I2C Control
Features
Description
•
•
•
•
Pericom Semiconductor’s PI2EQX5864C is a low power, PCIe®
compliant signal redriver. The device provides programmable
equalization, amplification, and de-emphasis by using 8 select
bits, to optimize performance over a variety of physical mediums
by reducing Inter-symbol interference.
PI2EQX5864C supports eight 100-Ohm Differential CML
data I/O’s between the Protocol ASIC to a switch fabric, across
a backplane, or extends the signals across other distant data
pathways on the user’s platform.
The integrated equalization circuitry provides flexibility with
signal integrity of the PCI Express signal before the ReDriver™,
whereas the integrated de-emphasis circuitry provides flexibility
with signal integrity of the signal after the redriver.
In addition to providing signal re-conditioning, Pericom’s
PI2EQX5864C also provides power management Stand-by mode
operated by a Bus Enable pin.
+
xyRx-
í
xyTx-
+
í
Output
Controls
B
Inputleveldetect
tocontrollogic
B0TX-
í
xyRx-
VDD
A1RX+
A1RXB1TXB1TX+
8
9
10
VDD
A2RX+
11
12
13
14
xxTx-
A0RX+
A0RXB0TX+
+
í
DataLaneRepeats4Times
A2RXB2TXB2TX+
Mode
Controlregisters
&logic
LB#
RXD_x
RES_x
VDD
A3RX+
A3RXB3TX+
B3TX-
Power
Management
SDA
SCL
09-0002
I2CControl
VDD
xyRx+
í
VDD
Equalizer
A
SDA
NC
RXD_A
+
xxTx+
Ax
1
41
40
39
15
16
17
18
19
20
A0TX+
A0TXB0RX+
B0RXVDD
A1TX+
A1TXB1RXB1RX+
38
VDD
A2TX+
37
36
35
34
B2RXB2RX+
VDD
33
32
31
30
29
21 22 23 24 25 26 27 28
VDD
RXD_B
xyTx+
Equalizer
56 55 54 53 52 51 50 49
1
48
2
47
3
46
4
45
5
44
6
43
7
42
+
A2TX-
A3TX+
A3TXB3RX+
B3RXVDD
A0
A1
LB#
xyRx+
Output
Controls
Inputleveldetect
tocontrollogic
A4
+
í
SCL
Pin Configuration
GND
GND
NC
Block Diagram
MODE
RESET#
•
•
•
•
•
•
•
•
Up to 5.0Gbps PCI Express® 2.0 Serial ReDriver
Supporting 8 differential channels or 4 lanes of PCIe Interface
I2C configuration controls
Adjustable receiver equalization and transmitter de-emphasis
and output levels
Variable input an output termination
1:2 channel broadcast
Channel loop-back
Electrical Idle fully supported
Receiver detect and individual output control
Single supply voltage, 1.2V ± 0.05V
Power down modes
Packaging: 56-contact TQFN, Pb-free & Green
PS8934D
07/08/09
PI2EQX5864C
5.0Gbps 4-Lane PCIe® 2.0 ReDdriver™
with Equalization, Emphasis and I2C Control
Pin Description
Pin #
Data Signals
2
3
48
47
7
8
43
42
12
13
38
37
17
18
33
32
46
45
4
5
41
40
9
10
36
35
14
15
31
30
19
20
Control Signals
Pin Name
Type
Description
A0RX+,
A0RXA0TX+,
A0TXA1RX+,
A1RXA1TX+,
A1TXA2RX+,
A2RXA2TX+,
A2TXA3RX+,
A3RXA3TX+,
A3TXB0RX+,
B0RXB0TX+,
B0TXB1RX-,
B1RX+
B1TX-,
B1TX+
B2RX-,
B2RX+
B2TX-,
B2TX+
B3RX+,
B3RXB3TX+,
B3TX-
I
I
O
O
I
I
O
O
I
I
O
O
I
I
O
O
I
I
O
O
I
I
O
O
I
I
O
O
I
I
O
O
CML inputs for Channel A0, with internal 50-Ohm pull down during normal
operation, and >200K-Ohm otherwise.
CML outputs for Channel A0, with internal 50-Ohm pull up during normal operation and 2K-Ohm pull up otherwise.
CML inputs for Channel A1, with internal 50-Ohm pull down during normal
operation, and >200K-Ohm otherwise.
CML outputs for Channel A1, with internal 50-Ohm pull up during normal operation and 2K-Ohm pull up otherwise.
CML inputs for Channel A2, with internal 50-Ohm pull down during normal
operation, and >200K-Ohm otherwise.
CML outputs for Channel A2, with internal 50-Ohm pull up during normal operation and 2K-Ohm pull up otherwise.
CML inputs for Channel A3 with internal 50-Ohm pull down during normal
operation, and >200K-Ohm otherwise.
CML outputs for Channel A3, with internal 50-Ohm pull up during normal operation and 2K-Ohm pull up otherwise.
CML inputs for Channel B0, with internal 50-Ohm pull down during normal
operation, and >200K-Ohm otherwise.
CML outputs for Channel B0, with internal 50-Ohm pull up during normal operation and 2K-Ohm pull up otherwise.
CML inputs for Channel B1, with internal 50-Ohm pull down during normal
operation, and >200K-Ohm otherwise.
CML outputs for Channel B1, with internal 50-Ohm pull up during normal operation and 2K-Ohm pull up otherwise.
CML inputs for Channel B2, with internal 50-Ohm pull down during normal
operation, and >200K-Ohm otherwise.
CML outputs for Channel B2, with internal 50-Ohm pull up during normal operation and 2K-Ohm pull up otherwise.
CML inputs for Channel B3, with internal 50-Ohm pull down during normal
operation, and >200K-Ohm otherwise.
CML outputs for Channel B3, with internal 50-Ohm pull up during normal operation and 2K-Ohm pull up otherwise.
26, 27, 25
A0, A1, A4
I
28
LB#
I
23
Mode
I
51
54
NC
NC
I2C programmable address bit A0, A1 and A4.
Loopback control input. Input with internal 100K-Ohm pull-up resistor. LB#
= High or open for normal operation. LB# = Low for loopback connection of
A_RX to A_TX and B_TX.
Enables I2C control when LOW. Has internal 100K-Ohm pull-up resistor. A
LVCMOS high level selects input pins control, and disables I2C operation. Note,
during startup, input status of the control pin (LB#, RES_A/B#, RXD_A/B) will
be latched to set the initial register state.
No Connect
No Connect
(Continued on Next Page)
09-0002
2
PS8934D
07/08/09
PI2EQX5864C
5.0Gbps 4-Lane PCIe® 2.0 ReDdriver™
with Equalization, Emphasis and I2C Control
Pin #
Pin Name
Type
24
RESET#
I
50
RXD_A
I
22
RXD_B
I
53
52
55, 56, Center Pad
1, 6, 11, 16, 21, 29,
34, 39, 44, 49
SCL
SDA
GND
I/O
I/O
PWR
Description
RESET# is an active low channel reset input for Channel A0, B0, A1, B1, A2,
B2, A3 and B3 with internal 100K-Ohm pull-up resistor. When low, receiver
detection cycle is reset, and normal detection cycle is carry on after the pin goes
high.
Receiver detect enable input for Channel A0, A1, A2 and A3 with internal 100KOhm pull-up resistor.
Receiver detect enable input for Channel B0, B1, B2 and B3 with internal 100KOhm pull-up resistor.
I2C SCL clock input.
I2C SDA data input.
Supply Ground
VDD
PWR
1.2V Supply Voltage
DESCRIPTION of OPERATION
Configuration Modes
Device configuration can be performed in two ways depending on the state of the MODE input. MODE determines whether IC
configuration status is from the input pins or via I2C control. When MODE is set high, the configuration input pins set the configuration operating state as stored in configuration registers. While MODE is set high, changes to these control registers are disabled and
the initial condition is protected from any changes to insuring a known operating state. When the MODE pin is low, reprogramming
of these control registers via I2C is allowed. Note that the MODE pin is not latched, and is always active to enable or disable I2C
access.
During initial power-on, the value at the configuration input pins: LB#, RESET#,RXD_A and RXD_B, will be latched to the configuration registers as initial startup states.
Equalizer Configuration
The PI2EQX5864C input equalizer compensates for signal attenuation and Inter-Symbol Interference (ISI) resulting from long signal
traces or cables, vias, signal crosstalk and other factors, by boosting the gain of high-frequency signal components. Because either
too little, or too much, signal compensation may be non-optimal eight levels are provided to adjust for any application.
Equalizer configuration can be programmed via I2C when the mode pin is low. Each group of four channels, A and B, has separate
equalization control, and all four channels within the group are assigned the same configuration state. The Equalizer Selection table
below describes the register state and associated operation of the equalizer.
Equalizer Selection
SEL2_[A:B]
SEL1_[A:B]
SEL0_[A:B]
@1.25GHz
@2.5GHz
0
0
0
0
0
0
1
1
0
1
0
1
0.5dB
0.6dB
1.0dB
1.9dB
1.2dB
1.5dB
2.6dB
4.3dB
1
0
0
2.8dB
5.8dB
1
0
1
3.6dB
7.1dB
1
1
1
1
0
1
5.0dB
7.7dB
9.0dB
12.3dB
09-0002
3
PS8934D
07/08/09
PI2EQX5864C
5.0Gbps 4-Lane PCIe® 2.0 ReDdriver™
with Equalization, Emphasis and I2C Control
Output Configuration
The PI2EQX5864C provides flexible output strength and emphasis controls to provide the optimum signal to pre-compensate for
losses across long trace or noisy environments so that the receiver gets a clean with good eye opening. Control of output configuration is grouped for the A and B channels, so that each channel within the group has the same setting.
Output configuration can be set via I2C when the mode pin is LOW. The Output Swing Control table shows available configuration
settings for output level control, as specified by the SELx_y registers.
Output Swing Control
S1_[A:B]
0
0
S0_[A:B]
0
1
Swing (Diff. VPP)
1V
0.5V
1
0
0.7V
1
1
0.9V
Emphasis settings are determined by the state of the Dx_y input pins and configuration registers, as shown below. De-Emphasis is
selected as the default power-on mode in following the PCI Express specification, but can be changed to Pre-emphasis via reprogramming the Loopback and Emphasis Control register using the I2C interface.
Output De-Emphasis Adjustment
D2_[A:B]
0
0
0
0
1
1
1
1
D1_[A:B]
0
0
1
1
0
0
1
1
D0_[A:B]
0
1
0
1
0
1
0
1
De-emphasis
0dB
-2.5dB
-3.5dB
-4.5dB
-5.5dB
-6.5dB
-7.5dB
-8.5dB
Input Level Detect
An input level detect and output squelch function is provided on each channel to eliminate re-transmission of input noise. A continuous signal level below the Vth- threshold causes the output driver to go to a high-impredance state, so that both the positive and negative output signal are pulled to VDD by the internal pull-up resistors. This feature supports L0S PCI Express Electrical Idle state.
09-0002
4
PS8934D
07/08/09
PI2EQX5864C
5.0Gbps 4-Lane PCIe® 2.0 ReDdriver™
with Equalization, Emphasis and I2C Control
Receiver Detect
Automatic Receiver Detection is a feature that can set the number of active channels. By sensing the presence of a load device
on the output, the channel can be automatically enabled for operation. This allows the PI2EQX5864C to configure itself properly
depending on the devices it is communicating with, whether it is a 4-lane, 3-lane, 2-lane or just 1-lane device or adapter card.
Receiver Detect is enabled by the RXD_A, or RXD_B pins, or alternatively via I2C programming. When RXD_A or RXD_B is set
to low, the Receiver Detect operation for that group of channels is disabled, and those channels go directly to 50-Ohm input termination to ground and 50-Ohm output termination to VDD (for a valid differential channel input level) or to 2K-Ohm (if the signal
level is less than the threshold level).
The RESET# input is used to reset the receiver detect state machine to its initial state. The start of the receiver detect cycle starts
when RESET# transitions from low to high.
When a Receiver Detect cycle begins the differential channel pins are enabled with a 2K-Ohm pull-up to VDD. A 50-Ohm Receiver termination will change the pin level. This pin level is evaluated after a fixed time-out, and the channel is then set into the proper
operating state. The register bits RX50_Ax and RX50_Bx represent the receiver detect result for their specific channels.
The I/O operation table summarizes the relationships and operation of receiver detect and other signals involved with I/O control.
I/O Operation Control
Control Inputs
Detection
States
RX50 SIG_x
Data Channel I/O
RXD_x
RESET#
X
X
X
X
Hi-Z
Hi-Z
0
0
X
X
Hi-Z
2K-Ohm pull-up
0
1
X
0
50-Ohm pulldown
2K-Ohm pull-up
0
1
X
1
50-Ohm pulldown
50-Ohm pull-up
1
0
X
X
Hi-Z
2K-Ohm pull-up
1
1
0
X
Hi-Z
2K-Ohm pull-up
1
1
1
0
50-Ohm pulldown
2K-Ohm pull-up
1
1
1
1
50-Ohm pulldown
50-Ohm pull-up
09-0002
Input Termination Output Termination
5
Mode
Full IC power down, all channels disabled
Channel disabled, output pulls to VDD.
Receiver detect reset
Channel enabled, no input signal, output
pulls to VDD. Receiver detect disabled
Channel enabled, valid input signal detected, output driving. Receiver detect
disabled.
Channel disabled. Receiver detect reset.
Channel disabled, output pulls to VDD. Receiver detect enabled, no receiver detected.
Channel inactive, output pulls to VDD.
Receiver detect enabled, receiver detected.
No input signal
Channel active, valid input signal detected,
output driving. Receiver detect enabled,
load detected.
PS8934D
07/08/09
PI2EQX5864C
5.0Gbps 4-Lane PCIe® 2.0 ReDdriver™
with Equalization, Emphasis and I2C Control
Loopback Operation
Each lane of the PI2EQX5864C provides a loopback mode for test purposes which is controlled by a strapping pin and I2C register
bit. The LB# pin controls all lanes together. When this pin is high normal data mode is enabled. When LB# is low the loopback
mode is enabled. The figure below diagrams this operation. Loopback is not intended to be dynamically switched, and the normal
system application is to initialize to one configuration or the other.
The Loopback mode can also support mux/demux operation. Using I2C configuration, unused inputs and outputs can be disabled to
minimize power and unnecessary noise.
A0
B0
A0
A0
B0
B0
Normal Operation
LB#=1
A0
B0
A0
B0
Loopback Mode
LB#=0
A0
A0
B0
B0
Mux Function
ODIS_AO = 1
Solid: LB_A0B0#=1
Dashed: LB_A0B0#=0
A0
B0
Demux Function
INDIS_BO = 1
Solid: LB=1
Dashed: LB=0
Loopback Modes
I2C Operation
The PI2EQX5864C I2C controller operates as a slave device, supporting standard rate operation of 100Kbps, with 7-bit addressing
mode. The data byte format is 8 bit bytes. The bytes must be accessed in sequential order from the lowest to the highest byte with
the ability to stop after any complete byte has been transferred. Address bits A4, A1 and A0 are programmable to support multiple
chips environment. The data is loaded until a Stop sequence is issued.
09-0002
6
PS8934D
07/08/09
PI2EQX5864C
5.0Gbps 4-Lane PCIe® 2.0 ReDdriver™
with Equalization, Emphasis and I2C Control
Configuration Register Summary
Byte
0
1
Mnemonic
SIG
RX50
2
LBEC
3
4
5
6
7
INDIS
OUTDIS
RESET
PWR
RXDE
Function
Signal Detect, indicates valid input signal level
Receiver Detect Output, indicates whether a receiver load was detected
Loopback and Emphasis Control, provides for control of the loopback function and emphasis mode (preemphasis or de-emphasis)
Channel Input Disable, controls whether a channels input buffer is enabled or disabled
Channel Output Disable: Controls whether a channels output buffer is enabled or disabled
Channel Reset
Power Down Control, enables power down for each channel individually
Receiver Detect Enable, controls the receiver detect operation
8
AEOC
A-Channels Equalizer and Output Control
9
10
11
BEOC
RSVD
RSVD
B-Channels Equalizer and Output Control
Reserved
Reserved
THE MOS-FET’S.
The requirements for the most important characteristics of the MOS-FET’s, used as bi-directional level shifter.
Type : N-channel enhancement mode MOS-FET.
Gate threshold voltage : VGS(th) min. 0.8V max. 1.5V
On resistance : RDS(on) max. 30 Ohm @ ID= 3mA, VGS= 2.5V
Input capacitance : Ciss max. 50 pF @ VDS= 1V, VGS = 0V
Switching times : ton toff max. 50 ns.
Allowed drain current : ID 30 mA or higher.
27k
10k
VDD2= 3.3 V
Vbias = 2.4V
100nf
VDD1= 1.2V
4.7k
4.7k
g
VDD2= 3.3 V
T1
s
2SK3018
d
g
10k
10k
SDA2
T2
s
d
SCL2
2SK3018
PI2EQX5864C
to I2C controller
PI2EQX5864C
“Lower voltage” section
“Higher voltage” section
Figure 2. Bi-directional Level Shifter Circuit
09-0002
7
PS8934D
07/08/09
PI2EQX5864C
5.0Gbps 4-Lane PCIe® 2.0 ReDdriver™
with Equalization, Emphasis and I2C Control
MOS-FET’s in table 1 are suitable to be used as level shifter. The 2SK3018 are low cost devices and have
good properties for 1.2V/3.3V level shifting, isolation and protection.
Manufacturer ManufacPart Number turer
2SK3018T106
Rohm
Drain to
Source Voltage (Vds)
30V
Current - Continuous Drain
(Id) @ 25° C
100mA
Input Capacitance (Ciss)
@ Vds
13pF @ 5V
Gate
threshold
voltage
0.8~1.5V
@100μA
Package /
Case
SOT-23
Transferring Data
Every byte put on the SDA line must be 8-bits long. Each byte has to be followed by an acknowledge
bit. Data is transferred with the most significant bit (MSB) first (see the I2C Data Transfer diagram). The
PI2EQX5864C will never hold the clock line SCL LOW to force the master into a wait state.
Note: Byte-write and byte-read transfers have a fixed offset of 0x00, because of the very small number of configuration bytes. An offset byte presented by a host to the PI2EQX5864C is not used.
Addressing
Up to eight PI2EQX5864C devices can be connected to a single I2C bus. The PI2EQX5864C supports 7-bit
addressing, with the LSB indicating either a read or write operation. The address for a specific device is determined by the A0, A1 and A4 input pins.
Address Assignment
A6
1
09-0002
A5
1
A4
Program
A3
0
A2
0
8
A1
A0
Programmable
R/W
1=R, 0=W
PS8934D
07/08/09
PI2EQX5864C
5.0Gbps 4-Lane PCIe® 2.0 ReDdriver™
with Equalization, Emphasis and I2C Control
Acknowledge
Data transfer with acknowledge is required from the master. When the master releases the SDA line (HIGH) during the acknowledge
clock pulse, the PI2EQX5864C will pull down the SDA line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse as indicated in the I2C Data Transfer diagram. The PI2EQX5864C will generate an acknowledge after each byte has been received.
Data Transfer
A data transfer cycle begins with the master issuing a start bit. After recognizing a start bit, the PI2EQX5864C will watch the next
byte of information for a match with its address setting. When a match is found it will respond with a read or write of data on the
following clocks. Each byte must be followed by an acknowledge bit, except for the last byte of a read cycle which ends with a stop
bit. For a write cycle, the first data byte following the address byte is a dummy or fill byte that is not used by the PI2EQX5864C.
This byte is provided to provided compatibility with systems implementing 10-bit addressing. Data is transferred with the most
significant bit (MSB) first. After each block write, address pointer will reset to byte 0.
Register Description
Byte 0 - Signal Detect (SIG)
SIG_xy=0=low input signal, SIG_xy=1=valid input signal
Bit
7
6
5
4
3
2
1
0
Name
SIG_A0
SIG_B0
SIG_A1
SIG_B1
SIG_A2
SIG_B2
SIG_A3
SIG_B3
Type
Power-on
State
R
R
R
R
R
R
R
R
X
X
X
X
X
X
X
X
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The Signal Detect register provides information on the instantaneous status of the channel input from the Input Level Threshold
Detect circuit. If the input level falls below the Vth- level the relevant SIG_xy bit will be 0, indicating a low-level noise or electrical idle input, resulting in the outputs going to the high-impedance off state or squelch mode. If the input level is above Vth-, then
SIG_xy is 1, indicating a valid input signal, and active signal recovery operation.
Byte 1 - Receiver Detect Output Register (RX50)
RX50_xy = 1 = load detected, RX50_xy = 0 = No receiver found
Bit
7
6
5
4
3
2
1
0
Name
RX50_A0
RX50_B0
RX50_A1
RX50_B1
RX50_A2
RX50_B2
RX50_A3
RX50_B3
Type
Power-on
State
R
R
R
R
R
R
R
R
X
X
X
X
X
X
X
X
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The RX50_xy bits report the result of a receiver detection cycle. One bit is assigned for each channel of the device. RX50_xy is
at a logic 1 level indicating a load and receiver was detected. When RX50_xy is 0 then a load device was not detected. The RX50
register is read-only, and is undefined after power-up until a Receiver Detection cycle completes.
09-0002
9
PS8934D
07/08/09
PI2EQX5864C
5.0Gbps 4-Lane PCIe® 2.0 ReDdriver™
with Equalization, Emphasis and I2C Control
Byte 2 - Loopback and Emphasis Control Register (LBEC)
LB_xyxy#=0=loopback mode, LB_xyxy#=1=normal mode, DE_x=0=pre-emphasis, DE_x=1=de-emphasis
Bit
7
6
5
4
3
2
1
0
Name
LB_A0B0#
LB_A1B1#
LB_A2B2#
LB_A3B3#
DE_A
DE_B
rsvd
rsvd
Type
Power-on
State
R/W
R/W
R/W
R/W
R/W
R/W
R
R
LB#
LB#
LB#
LB#
1
1
X
X
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
Individual control for each lane is provided for the loopback function via this register.
BYTE 3 - Channel Input Disable (INDIS)
INDIS_xy=0=enable input, INDIS_xy=1=disable input
Bit
7
6
5
4
3
2
1
0
Name
INDIS_A0
INDIS_B0
INDIS_A1
INDIS_B1
INDIS_A2
INDIS_B2
INDIS_A3
INDIS_B3
R/W
R/W
0
0
Type
R/W
R/W
R/W
R/W
R/W
R/W
Power-on
0
0
0
0
0
0
State
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The Channel Input Disable register, provides control over the input buffer of each channel independently. When and INDIS_xy bit is
logic 1, then the input buffer is switched off and the input termination is high impedance. This feature can be used for PCB testing,
and when only one input is used during Loopback as a demux function. When INDIS_xy is at a logic 0 state then the input buffer is
enabled (normal operating mode).
BYTE 4 - Channel Output Disable (OUTDIS)
ODIS_xy=0=enable output, ODIS_xy=1=disable output
Bit
7
6
5
4
3
2
1
0
Name
ODIS_A0
ODIS_B0
ODIS_A1
ODIS_B1
ODIS_A2
ODIS_B2
ODIS_A3
ODIS_B3
R/W
R/W
0
0
Type
R/W
R/W
R/W
R/W
R/W
R/W
Power-on
0
0
0
0
0
0
State
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The Channel Output Disable register, allows control over the output buffer of each channel independently. When and OUTDIS_xy
bit is logic 1, then the output buffer is switched off and the termination is high impedance. This feature can be used for PCB testing,
and when only one output is used during Loopback as a mux function. When INDIS_xy is at a logic 0 state then the input buffer is
enabled (normal operating mode).
09-0002
10
PS8934D
07/08/09
PI2EQX5864C
5.0Gbps 4-Lane PCIe® 2.0 ReDdriver™
with Equalization, Emphasis and I2C Control
BYTE 5 - Channel Reset (RESET)
RESET# =0=reset, RESET# =1=normal operation. Latch from RESET# input at startup
Bit
7
6
5
4
3
2
1
0
Name
RES_A0#
RES_B0#
RES_A1#
RES_B1#
RES_A2#
RES_B2#
RES_A3#
RES_B3#
R/W
R/W
1
1
Type
R/W
R/W
R/W
R/W
R/W
R/W
Power-on
1
1
1
1
1
1
State
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The Channel Reset register allows for restart of an individual channels Receiver Detect function. A transition from 0 to 1 initiates a
new Receiver Detect cycle (if the channel is enabled and receiver detect is enabled). While static at 0 or 1, the RESET# bit will have
no effect on operation. The Channel Reset bits are read/write allowing the current state to be checked.
BYTE 6 - Power Down Control (PWR)
PD_xy# =0=channel off/power down, PD_xy# =1=normal operation, Latch from PD# input at startup
Bit
7
6
5
4
3
2
1
0
Name
PD_A0#
PD_B0#
PD_A1#
PD_B1#
PD_A2#
PD_B2#
PD_A3#
PD_B3#
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Power-on
State
1
1
1
1
1
1
1
1
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The Power Down Control register allows for individual control over each channel for power savings. When PD_xy# is logic 0 the
channel is turned off. When PD_xy# is 1 then the channel is enabled for normal operation.
BYTE 7 - Receiver Detect Enable (RXD)
RXD_xy =0=channel off/power down, RXD_xy =1=normal operation, Latch from PD# input at startup
Bit
7
6
5
4
3
2
1
0
Name
RXD_A0
RXD_B0
RXD_A1
RXD_B1
RXD_A2
RXD_B2
RXD_A3
RXD_B3
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Power-on
State
1
1
1
1
1
1
1
1
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The Receiver Detect Enable register allows for control of the receiver detect state machine for each individual channel. When
RXD_xy is set to 0, then the receiver detect function is disabled. When RXD_xy is logic 1, then the receiver detect state machine is
enabled for operation. The initial state of the register bits are determined by the RXD_A and RXD_B input pins during power-up.
BYTE 8 - A-Channels Equalizer and Output Control (AEOC)
SELx_A: Equalizer configuration, Dx_A: Emphasis control, Sx_A: Output level control (see Configuration Table)
Bit
7
6
5
4
3
2
1
0
Name
SEL0_A
SEL1_A
SEL2_A
D0_A
D1_A
D2_A
S0_A
S1_A
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Power-on
State
1
1
1
1
1
1
1
1
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
09-0002
11
PS8934D
07/08/09
PI2EQX5864C
5.0Gbps 4-Lane PCIe® 2.0 ReDdriver™
with Equalization, Emphasis and I2C Control
The A-Channels Equalizer and Output Control register is used to control the configuration of the input equalizer and output emphasis
and levels of the four A channels. These register bits are loaded from the input configuration pins of the same name at power-on.
These bits may be changed if the MODE# input is set to allow I2C configuration. Please refer to the tables (1) Equalizer Configuration, (2) Output Swing Configuration and (3) Output Emphasis Configuration earlier in this document for setting information. All
four A channels get the same configuration settings.
BYTE 9 - B-Channels Equalizer and Output Control (BEOC)
SELx_B: Equalizer configuration, Dx_B: Emphasis control, Sx_B: Output level control (see Configuration Table)
Bit
7
6
5
4
3
2
1
0
Name
SEL0_B
SEL1_B
SEL2_B
D0_B
D1_B
D2_B
S0_B
S1_B
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Power-on
State
1
1
1
1
1
1
1
1
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The B-Channels Equalizer and Output Control register is used to control the configuration of the input equalizer and output emphasis
and levels of the four B channels. These register bits are loaded from the input configuration pins of the same name at power-on.
These bits may be changed if the MODE# input is set to allow I2C configuration. Please refer to the tables (1) Equalizer Configuration, (2) Output Swing Configuration and (3) Output Emphasis Configuration earlier in this document for setting information. All
four B channels get the same configuration settings.
BYTE 10 - Reserved
BYTE 11 - Reserved
Reserved Bytes 10 and 11 are also visible via the I2C interface. These bytes are R/W, are initialized to 0 at power up, are used for IC
manufacturing test purposes and should not be changed for normal operation.
Start & Stop Conditions
A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition. A LOW to HIGH transition on the
SDA line while SCL is HIGH defines a STOP condition, as shown in the figure below.
6
09-0002
12
PS8934D
07/08/09
PI2EQX5864C
5.0Gbps 4-Lane PCIe® 2.0 ReDdriver™
with Equalization, Emphasis and I2C Control
I2C Data Transfer
1.Readsequence
ACK
PI2EQX5864
DATAOUT ACK
ACK
ACK
ACK
DATAOUTN
NOACK
PI2EQX5864C
DEVSEL
stop
start
I2C Master
R/W
2.Writesequence
ACK
ACK
ACK
PI2EQX5864C
DEVSEL
R/W
DATAINN
DATAIN1
DUMMY BYTE
stop
start
I2C Master
3.Combinedsequence
ACK DUMMYBYTE ACK
ACK DATAOUT1 ACK
ACK DATAOUTN NOACK
PI2EQX5864C
stop
DEVSEL R/W
start
start
I2C Master
DEVSEL R/W
Notes:
1. only block read and block write from the lowest byte
are supported for this application.
2. for some I2C application, an offset address byte will be
presented at the second byte in write command, which
is called dummy byte here and will be simply ignored in
this application for correct interoperation.
09-0002
13
PS8934D
07/08/09
PI2EQX5864C
5.0Gbps 4-Lane PCIe® 2.0 ReDdriver™
with Equalization, Emphasis and I2C Control
Maximum Ratings
(Above which useful life may be impaired. For user guidelines, not tested.)
Storage Temperature...................................... –65°C to +150°C
Supply Voltage to Ground Potential........ –0.5V to +2.5V
DC SIG Voltage....................................... –0.5V to VDD +0.5V
Current Output ........................................ –25mA to +25mA
Power Dissipation Continuous ............... 1W
Operating Temperature............................ 0 to +70°C
ESD, HBM: I2C pins............................... –1kV to +1kV
ESD, HBM: All other pins....................... –2kV to +2kV
Note:
Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is
a stress rating only and functional operation of the device
at these or any other conditions above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
AC/DC Electrical Characteristics
Power Supply Characteristics (VDD = 1.2 ±0.05V, TA = 0 TO 70°C)
Symbol
Parameters
Conditions
Power supply current - acIDDactive
All channels switching
tive
Power supply current IDDstandby
PD_xy# all 0
standby
Power supply current - per
IDD-channel
channel, Active
Min.
5
ZRX-DC
VRX-DIFFP-P
VRX-CM-ACP
Vth09-0002
DC Input Impedance
Differential Input Peak-topeak Voltage
AC Peak Common Mode
Input Voltage
Signal detect threshold
voltage
Min.
Typ.
mA
10
mA
mA
Max. Units
750
ps
Min.
Typ.
Max.
Units
80
100
120
Ohms
40
50
60
Ohms
1.200
V
150
mV
150
mV
0.120
100
14
800
50
AC Performance Characteristics (VDD = 1.2 ±0.05V, TA = 0 TO 70°C)
Symbol
Parameters
Conditions
Channel latency from
Tpd
input to output
CML Receiver Input (VDD = 1.2 ±0.05V, TA = 0 TO 70°C)
Symbol
Parameters
Conditions
DC Differential Input
ZRX-DIFF-DC
Impedance
Typ. Max. Units
PS8934D
07/08/09
PI2EQX5864C
5.0Gbps 4-Lane PCIe® 2.0 ReDdriver™
with Equalization, Emphasis and I2C Control
Equalizer
Symbol
Parameters
Conditions
JRS-T
Residual jitter
JRS-D
JRM
Residual jitter
Random jitter
Min.
Typ.
Max.
Units
Total
0.3
Ulp-p
Deterministic
Note 2
0.2
Ulp-p
psrms
1.5
Notes
1. K28.7 pattern is applied differentially at point A as shown in AC test circuit (see figure).
2. Total jitter does not include the signal source jitter. Total jitter (TJ) = (14.1 × RJ + DJ) where RJ is random RMS jitter and DJ is maximum deterministic jitter. Signal source is a K28.5 ± pattern (00 1111 1010 11 0000 0101) for the deterministic jitter test and K28.7 (0011111000) or equivalent
for random jitter test. Residual jitter is that which remains after equalizing media-induced losses of the environment of Figure 1 or its equivalent.
The deterministic jitter at point B must be from media-induced loss, and not from clock source modulation. Jitter is measured at 0V at point C of
the AC test circuit (see figure).
CML Transmitter Output (VDD = 1.2V ± 0.05V, TA = 0 to 70°C)
Symbol
Parameters
Conditions
Single ended
Min.
Typ.
Max.
Units
40
50
60
Ohms
80
100
120
Ohms
1000
mVp-p
2.0
V
ZOUT
Output resistance
ZTX-DIFF-DC
DC Differential TX Impedance
VDIFFP
Output Voltage Swing,
Differential
|VTX-D+ - VTX-D-|
VTX-DIFFP-P
Differential Peak-to-peak
Ouput Voltage
VTX-DIFFP-P = 2 * | VTX-D+
0.4
- VTX-D- |
VTX-C
Common-Mode Voltage
| VTX-D+ + VTX-D- | / 2
tF, tR
Transition Time
20% to 80% (3)
(1)
CTX
AC Coupling Capacitor
Notes:
1. Recommended external coupling capacitor.
200
VDD- 0.3
75
Digital I/O DC Specifications (VDD = 1.2V ± 0.05V, TA = 0 to 70°C)
Symbol
Parameters
Conditions
Min.
Typ.
V
150
ps
200
nF
Max.
Units
VIH
DC input logic high
VDD/2 +0.2
VDD+0.3
V
VIL
DC input logic low
-0.3
VDD/2 -0.2
V
VOH
DC output logic high
IOH = 4mA
VOL
DC output logic low
IOL = 4mA
Vhys
Hysteresis of Schmitt
trigger input
IIH(1)
IIL1(2)
Input high current
Input low current
VDD-0.4
0.4
0.2
-20
IIL2
Input low current
-20
Notes:
1. Includes input signals A1, A2, A4, LB#, MODE#, RESET#, RXD_[A:B], SCL, SDA
2. For control inputs without pullups: A1, A2, A4, SCL, SDA
3. Control inputs with pull-ups include: LB#, MODE#, RESET#, RXD_[A:B]
15
V
V
100
(3)
09-0002
V
uA
uA
uA
PS8934D
07/08/09
PI2EQX5864C
5.0Gbps 4-Lane PCIe® 2.0 ReDdriver™
with Equalization, Emphasis and I2C Control
SDA and SCL I/O for I2C-bus (VDD = 1.2 ± 0.05v, TA = 0 to 70°C)
Symbol
Parameters
Conditions
Min.
DC input logic high
1.1
VIH
DC input logic low
-0.3
VIL
DC output logic low
IOL = 3mA
VOL
Hysteresis of Schmitt trigger input
0.2
Vhys
Characteristics of the SDA and SCL bus lines for F/S-mode I2C-bus devices(1)
Symbol
Parameter
Conditions
Min.
SCL clock frequency
0
fSCL
Hold time (repeated) START condition.
4.0
tHD;STA After this period, the first clock pulse is
generated
tLOW
LOW period of the SCL clock
4.7
tHIGH
HIGH period of the SCL clock
4.0
Set-up time for a repeated START condi4.7
tSU;STA
tion
5.0
tHD;DAT Data hold time
250
tSU;DAT Data set-up time
tr
Rise time of both SDA and SCL signals
–
tf
Fall time of both SDA and SCL signals
4.0
tSU;STO Set-up time for STOP condition
Buss free time between a STOP and
4.7
tBUF
STOP condition
Capacitive load for each bus line
–
Cb
Typ.
Max.
VDD + 0.3
0.7
0.4
Units
V
V
V
V
Typ.
Max.
100
Unit
kHz
–
μs
–
–
μs
μs
–
μs
–
–
100
300
–
μs
ns
ns
ns
μs
–
μs
400
pF
Notes:
1. All values referred to VIHmin and VILmax levels.
2. A device must initially provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined
region of the falling edge of SCL.
09-0002
16
PS8934D
07/08/09
PI2EQX5864C
5.0Gbps 4-Lane PCIe® 2.0 ReDdriver™
with Equalization, Emphasis and I2C Control
STOP
START
START
SDA
tf
tf
tSU;DAT
tLOW
tr
t HD;STA
tBUF
SCL
S
tHD;STA
tHD;DAT
HIGH
t SU;STA
Sr
t SU;STO
P
S
I2C Timing
Channel Latency, 5.0 Gbps
09-0002
17
PS8934D
07/08/09
PI2EQX5864C
5.0Gbps 4-Lane PCIe® 2.0 ReDdriver™
with Equalization, Emphasis and I2C Control
Output Level Settings (1V left, and 0.5V right at 5.0 Gbps)
–3.5 dB (Dx = 010)
0.0 dB (Dx = 000)
–8.5 dB (Dx = 111)
–6.5 dB (Dx = 101)
Output De-Emphasis Characteristics
09-0002
18
PS8934D
07/08/09
PI2EQX5864C
5.0Gbps 4-Lane PCIe® 2.0 ReDdriver™
with Equalization, Emphasis and I2C Control
Eye Diagrams 5.0Gbps (input left, output right)
Data Waveforms, 2.5Gbps (left) & 5.0Gbps (right)
FR4
Signal
Source
A
B
C
D.U.T.
SmA
Connector
SmA
Connector
In
Out
≤30IN
AC Test Circuit Referenced in the Electrical Characteristic Table
09-0002
19
PS8934D
07/08/09
PI2EQX5864C
5.0Gbps 4-Lane PCIe® 2.0 ReDdriver™
with Equalization, Emphasis and I2C Control
Packaging Mechanical: 56-Contact TQFN (ZF)
1
DATE: 05/15/08
DESCRIPTION: 56-contact, Thin Fine Pitch Quad Flat No-lead (TQFN)
PACKAGE CODE: ZF56
REVISION: C
DOCUMENT CONTROL #: PD-2024
08-0208
Ordering Information
Ordering Number
PI2EQX5864CZFE
Package Code
ZF
Package Description
Pb-free & Green 56-Contact TQFN
Notes:
• Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
• E = Pb-free and Green
• X suffix = Tape/Reel
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
09-0002
ReDriver is a trademark of Pericom Semiconductor.
PCIe® , and the PCI EXPRESS design mark® are trademarks of PCI-SIG® (www.pcisig.com)
20
PS8934D
07/08/09