BU2381FV Multimedia ICs Clock generator for digital still camera BU2381FV BU2381FV is a high-performance 3-channel PLL IC. PLL circuit generates necessary clocks by inputting standard clocks of crystal oscillator from outside. Changing a connection of wire can generate any clocks required for any applications of users. Jitter and S/N characteristic has achieved almost the same high-quality sound and vision as oscillating module because of optimization of PLL. Frequency can be changed by the internal dividing control. zApplications Digital still camera zExternal dimensions (Unit : mm) 5.0±0.2 9 1 8 0.3Min. 16 1.15±0.1 0.1 6.4±0.3 4.4±0.2 zFeatures 1) Generate clocks for video output, CDS, USB from standard clock input 2) No external elements required for PLL 3) Standard clocks apply to two kinds of NTSC/PAL 4) Single power supply of 3.3V operating 5) SSOP-B16 small package 0.65 0.15±0.1 0.1 0.22±0.1 SSOP-B16 zAbsolute maximum ratings (Ta=25°C) Symbol Limits Unit Applied voltage VDD −0.5 to +7.0 V Input voltage VIN −0.5 to VDD+0.5 V Tstg −30 to +125 Parameter Storage temperature range Power dissipation °C 450 ∗ Pd mW ∗Derating : 4.5mW/°C for operating above Ta=25°C ∗An operation is not guaranteed. ∗Radiation resistance design is not used. ∗Power dissipation is measured when BU2381FV is placed on the board. zRecommended operating conditions (Ta=25°C) Symbol Min. Typ. Max. Unit Supply voltage Parameter VDD 3.0 − 3.6 V Input "H" voltage range VIH 0.8VDD − VDD V Input "L" voltage range VIL 0 − 0.2VDD V Topr −5 − 70 °C CL − − 15 pF Operation temperature range Output maximum load 1/5 BU2381FV Multimedia ICs zBlock diagram Data1a Data1b Data1c PLL1 144M 180M 228M 71.877274MHz or 90.314686MHz or 114.54546MHz 1/2 CLK1 96.016044MHz 1/2 14.318182MHz XTAL_IN XTAL OSC XTAL_OUT PLL2 192MHz 1/2 96.016044MHz CLK2 48.008022MHz 1/4 CLK2ON PLL3 177MHz FS1 1 / 10 FS2 17.734450MHz REF_CLK 14.318182MHz FS3 zPin descriptions Functions Pin No. Pin name 1 REFCLK 2 VDD Analog VDD 3 FS3 CLK1, 2 output select with pull up 4 VSS Analog GND 5 XIN Standard crystal input 6 TEST Input for test mode (normally open) 14.3MHz / 17.7MHz clock output 7 XOUT Standard crystal output 8 FS2 CLK1, 2 output select with pull up 9 CLK1OUT 10 FS1 11 CLK2ON 12 VSS GND for CLK1, 2 clock output and Logic circuit 13 VDD VDD for CLK1, 2 clock output and Logic circuit 14 CLK2OUT 71M / 90M / 96M / 114MHz clock output REFCLK output select with pull up CLK2 output control with pull up H : enable L : disable 96M / 48M clock output 15 VSS GND for REFCLK clock output 16 VDD VDD for REFCLK clock output 2/5 BU2381FV Multimedia ICs zInput output circuits Pin No. Equivalent circuit Input PIN 3, 8, 10, 11 To inside IC with pull−up (PIN6 : TESTpin with pull down) OUTPUT PIN 1, 9, 14 From inside IC Crystal PIN 5, 7 XTALIN XTALOUT To inside IC 3/5 BU2381FV Multimedia ICs zElectrical characteristics (Unless specified otherwise Ta=25°C, VCC=3.3V) Parameter Power supply current Symbol Min. Typ. Max. Unit IDD − 40 50 mA Conditions No load − − − − − FS2 : H FS3 : H Fclk1-1 − 96.016044 − − Xtal ∗ (228 / 17) / 2 FS2 : H FS3 : L Fclk1-2 − 71.877274 − − Xtal ∗ (251 / 25) / 2 FS2 : L FS3 : L Fclk1-3 − 114.54546 − MHz Xtal ∗ (224 / 14) / 2 FS2 : L FS3 : H Fclk1-4 − 90.314686 − MHz Xtal ∗ (164 / 12) / 2 FS2 : L FS3 : L Fclk2-1 − 96.016044 − MHz Xtal ∗ (228 / 17) / 2 FS2, 3 : HL / LH / HH Fclk2-2 − 48.008022 − MHz Xtal ∗ (228 / 17) / 4 FS1 : H FS1 : L Fref1-1 Fref1-2 − − 14.318182 17.73445 − − MHz MHz Crystal direct output Xtal ∗ (706 / 57) / 10 Duty1 at 100MHz Duty1 45 50 55 % Measured at 1/2 VDD Duty2 at 100MHz Duty2 − 50 − % Measured at 1/2 VDD tr − 2.5 − nsec Output frequency CLK1 CLK2 REFCLK Rise time Fall time Period jitter 1σ Period jitter MIN-MAX Output Lock time Time between 0.2 VDD and 0.8 VDD tf − 2.5 − nsec Time between 0.8 VDD and 0.2 VDD P-J1σ − 30 − psec ∗1 P-JMINMAX − 180 − psec ∗2 Tlock − − 1 msec ∗3 Note) When input frequency is 14.318182MHz, output frequency is above rated value. ∗1) Period Jitter 1σ : This value is the standard deviation of an output period when using Time Interval Analyzer with 10,000 sampling. ∗2) Period Jitter MIN-MAX : This value is the max range of an output period when using Time Interval Analyzer with 10,000 sampling. ∗3) Output Lock time : This value is the time until the output clock gets stable after the power supply voltage leads to 3.0V. 4/5 BU2381FV Multimedia ICs zApplication example REFCLK output 1 16 0.1µF 2 15 3 14 4 13 FS3 H or L CLK2 output 0.1µF 0.1µF FS2 H or L 5 12 6 11 7 10 8 9 CLK2 ON H or L FS1 H or L CLK1 output Note) The BU2381FV is placed on the board normally. A decoupling capacitor (0.1µF) needs to be placed between pin2 and pin4, pin13 and pin12, pin16 and pin15. The decoupling capacitor is an close to the above pins as possible. 5/5