PLL1705 PLL1706 SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002 3.3-V DUAL PLL MULTICLOCK GENERATOR FEATURES D 27-MHz Master Clock Input D Generated Audio System Clock: – SCKO0: 768 fS (fS = 44.1 kHz) – SCKO1: 384 fS, 768 fS (fS = 44.1 kHz) – SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) – SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) D Zero PPM Error Output Clocks D Low Clock Jitter: 50 ps (Typical) D Multiple Sampling Frequencies: – fS = 32, 44.1, 48, 64, 88.2, 96 kHz D 3.3-V Single Power Supply D PLL1705: Parallel Control PLL1706: Serial Control D Package: 20-Pin SSOP (150 mil), Lead-Free Product APPLICATIONS D DVD Players D DVD Add-On Cards for Multimedia PCs D Digital HDTV Systems D Set-Top Boxes DESCRIPTION The PLL1705† and PLL1706† are low cost, phase-locked loop (PLL) multiclock generators. The PLL1705 and PLL1706 can generate four system clocks from a 27-MHz reference input frequency. The clock outputs of the PLL1705 can be controlled by sampling frequency-control pins and those of the PLL1706 can be controlled through serial-mode control pins. The device gives customers both cost and space savings by eliminating external components and enables customers to achieve the very low-jitter performance needed for high performance audio DACs and/or ADCs. The PLL1705 and PLL1706 are ideal for MPEG-2 applications which use a 27-MHz master clock such as DVD players, DVD add-on cards for multimedia PCs, digital HDTV systems, and set-top boxes. FUNCTIONAL BLOCK DIAGRAM (ML) SR (MC) FS2 (MD) FS1 CSEL Mode Control Interface VCC AGND VDD1–3 DGND1–3 Power Supply Reset PLL2 XT1 OSC PLL1 XT2 ( ): PLL1706 MCKO1 MCKO2 SCKO0 Divider Divider Divider SCKO1 SCKO2 SCKO3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. †The PLL1705 and PLL1706 use the same die and they are electrically identical except for mode control. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 2002, Texas Instruments Incorporated PLL1705 PLL1706 www.ti.com SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE CODE OPERATION TEMPERATURE RANGE PACKAGE MARKING PLL1705DBQ SSOP 20 20DBQ –25°C 25°C to 85°C PLL1705 PLL1706DBQ SSOP 20 20DBQ –25°C 25°C to 85°C PLL1706 ORDERING NUMBER TRANSPORT MEDIA PLL1705DBQ Tube PLL1705DBQR Tape and reel PLL1706DBQ Tube PLL1706DBQR Tape and reel ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) PLL1705 AND PLL1706 Supply voltage: VCC, VDD1–3 Supply voltage differences: VCC, VDD1–3 Ground voltage differences: AGND, DGND1–3 4V ±0.1 V ±0.1 V Digital input voltage: FS1 (MD), FS2 (MC), SR (ML), CSEL – 0.3 V to (VDD + 0.3) V Analog input voltage, XT1, XT2 – 0.3 V to (VCC + 0.3) V Input current (any pins except supplies) ±10 mA Ambient temperature under bias –40°C to 125°C Storage temperature –55°C to 150°C Junction temperature Lead temperature (soldering) 150°C 260°C, 5 s Package temperature (IR reflow, peak) 260°C (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2 PLL1705 PLL1706 www.ti.com SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002 ELECTRICAL CHARACTERISTICS all specifications at TA = 25°C, VDD1–VDD3 (= VDD) = VCC = 3.3 V, fM = 27 MHz, crystal oscillation, fS = 48 kHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUT/OUTPUT Logic input VIH (1) VIL (1) Input logic level IIH (1) IIL (1) Input logic current CMOS compatible 0.7VDD VIN = VDD VIN = 0 V Logic output VOH (2) VOL (2) Output logic level Samplingfrequency Sampling frequency 3.6 0.3 VDD 65 ±10 Input level(3) IIH IIL Input current(3) VDD – 0.4 V Vdc 0.4 Standard fS 32 44.1 48 Double fS 64 88.2 96 0.3 VCC ±10 VIN = VCC VIN = 0 V ±10 Vdc kHz MHz V µA 3.5 Vp-p Output rise time 20% to 80% of VDD 2.0 ns Output fall time 80% to 20% of VDD 2.0 ns Duty cycle For crystal oscillation 45% For external clock 48% Clock jitter (5) 50 Power-up time (6) 0.5 Output system clock frequency SCKO3 Selectable for 44.1 kHz 33.8688 256 fS 8.192 12.288 24.576 384 fS 12.288 18.432 36.864 20% to 80% of VDD 2.0 Output fall time 80% to 20% of VDD 2.0 Output duty cycle 45 ms MHz ns ns 50 55 % 50 100 ps PLL1705, to stated output frequency 50 150 ns PLL1706, to stated output frequency 80 200 ns 3 6 ms Output clock jitter (5) Power-up time (8) ps 1.5 33.8688 16.9344 Output rise time Frequency Settling Time(7) 55% 50% PLL AC CHARACTERISTICS (SCKO0–3) (fM = 27 MHz, CL = 20 pF on measurement pin) SCKO0 Fixed SCKO2 27.27 0.7 VCC Output voltage (4) SCKO1 µA CMOS IOH = –4 mA IOL = 4 mA MASTER CLOCK (MCKO1, 2) CHARACTERISTICS (fM = 27 MHz, C1 = C2 = 15 pF, CL = 20 pF on measurement pin) Master clock frequency 26.73 27 VIH VIL 100 Vdc To stated output frequency (1) Pins 5, 6, 7, 12: FS1/MD, FS2/MC, SR/ML, CSEL (Schmitt-trigger input with internal pulldown, 3.3-V tolerant) (2) Pins 2, 3, 14, 15, 18, 19: SCKO2, SCKO3, MCKO1, MCKO2, SCKO1, SCKO0 (3) Pin 10: XT1 (4) Pin 11: XT2 (5) Jitter performance is specified as standard deviation of jitter for 27-MHz crystal oscillation and default SCKO frequency setting. Jitter performance varies with master clock mode, SCKO frequency setting and load capacitance on each clock output. (6) The delay time from power on to oscillation (7) The settling time when the sampling frequency is changed (8) The delay time from power on to lockup (9) fM = 27-MHz crystal oscillation, no load on MCKO1, MCKO2, SCKO0, SCKO1, SCKO2, SCKO3. Power supply current varies with sampling frequency selection and load condition. (10) While all bits of CE[6:1] are 0, the PLL1706 goes into power-down mode. 3 PLL1705 PLL1706 www.ti.com SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002 ELECTRICAL CHARACTERISTICS(continued) all specifications at TA = 25°C, VDD1–VDD3 (= VDD) = VCC = 3.3 V, fM = 27 MHz, crystal oscillation, fS = 48 kHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 2.7 3.3 UNIT POWER SUPPLY REQUIREMENTS VCC, VDD IDD + ICC Supply voltage range 3.6 Vdc Supply current (9) VDD = VCC = 3.3 V, fS = 48 kHz Power down(10) 19 25 mA 320 500 µA Power dissipation VDD = VCC = 3.3 V, fS = 48 kHz 63 90 mW 85 °C TEMPERATURE RANGE Operatingtemperature –25 θJA Thermal resistance PLL1705/6DBQ: 20-pin SSOP (150 mil) 150 °C/W (1) Pins 5, 6, 7, 12: FS1/MD, FS2/MC, SR/ML, CSEL (Schmitt-trigger input with internal pulldown, 3.3-V tolerant) (2) Pins 2, 3, 14, 15, 18, 19: SCKO2, SCKO3, MCKO1, MCKO2, SCKO1, SCKO0 (3) Pin 10: XT1 (4) Pin 11: XT2 (5) Jitter performance is specified as standard deviation of jitter for 27-MHz crystal oscillation and default SCKO frequency setting. Jitter performance varies with master clock mode, SCKO frequency setting and load capacitance on each clock output. (6) The delay time from power on to oscillation (7) The settling time when the sampling frequency is changed (8) The delay time from power on to lockup (9) fM = 27-MHz crystal oscillation, no load on MCKO1, MCKO2, SCKO0, SCKO1, SCKO2, SCKO3. Power supply current varies with sampling frequency selection and load condition. (10) While all bits of CE[6:1] are 0, the PLL1706 goes into power-down mode. PIN ASSIGNMENTS PLL1705 (TOP VIEW) VDD1 SCKO2 SCKO3 DGND1 FS1 FS2 SR VCC AGND XT1 4 1 2 3 4 5 6 7 8 9 10 PLL1706 (TOP VIEW) 20 19 18 17 16 15 14 13 12 11 VDD3 SCKO0 SCKO1 DGND3 DGND2 MCKO2 MCKO1 VDD2 CSEL XT2 VDD1 SCKO2 SCKO3 DGND1 MD MC ML VCC AGND XT1 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD3 SCKO0 SCKO1 DGND3 DGND2 MCKO2 MCKO1 VDD2 CSEL XT2 PLL1705 PLL1706 www.ti.com SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002 Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. AGND 9 – Analog ground CSEL 12 IN SCKO1 frequency selection control(1) DGND1 4 – Digital ground 1 DGND2 16 – Digital ground 2 DGND3 17 – Digital ground 3 FS1(MD) 5 IN Sampling frequency group control in PLL1705, data input for serial control in PLL1706(1) FS2(MC) 6 IN Sampling frequency group control in PLL1705, bit clock input for serial control in PLL1706(1) MCKO1 14 OUT 27-MHz master clock output 1 MCKO2 15 OUT 27-MHz master clock output 2 SCKO0 19 OUT System clock output 0 (33.8688 MHz fixed) SCKO1 18 OUT System clock output 1 (selectable for 44.1 kHz) SCKO2 2 OUT System clock output 2 (256 fS) SCKO3 3 OUT System clock output 3 (384 fS) SR(ML) 7 IN Sampling rate control in PLL1705, load strobe input for serial control in PLL1706(1) VCC 8 – Analog power supply, 3.3 V VDD1 1 – Digital power supply 1, 3.3 V VDD2 13 – Digital power supply 2, 3.3 V VDD3 20 – Digital power supply 3, 3.3 V XT1 10 IN 27-MHz crystal oscillator, or external clock input XT2 11 OUT 27-MHz crystal oscillator, must be OPEN for external clock input mode (1) Schmitt-trigger input with internal pulldown. 5 PLL1705 PLL1706 www.ti.com SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002 TYPICAL PERFORMANCE CURVES JITTER vs LOAD CAPACITANCE JITTER vs SAMPLING FREQUENCY 70 70 60 60 Jitter – psrms Jitter – psrms SCKO3 50 50 SCKO2 SCKO1 40 40 MCKO1 SCKO0 SCKO2 MCKO2 SCKO1 SCKO3 MCKO2 MCKO1 30 30 30 40 50 60 70 80 90 0 100 5 Figure 1 70 60 60 SCKO0 SCKO3 SCKO0 Jitter – psrms SCKO1 50 SCKO2 SCKO1 MCKO2 MCKO1 40 40 3.3 VCC – Supply Voltage – V Figure 3 SCKO3 50 MCKO1 MCKO2 3.0 20 JITTER vs FREE-AIR TEMPERATURE 70 30 2.7 15 Figure 2 JITTER vs SUPPLY VOLTAGE SCKO2 10 CL – Load Capacitance – pF fS – Sampling Frequency – kHz Jitter – psrms SCKO0 3.6 30 –50 –25 0 25 50 75 100 TA – Free-Air Temperature – °C Figure 4 NOTE: All specifications at TA = 25°C, VDD1–3 (= VDD) = VCC = +3.3 V, fM = 27 MHz, crystal oscillation, C1, C2 = 15 pF, default frequency (33.8688 MHz for SCKO0, 33.8688 MHz for SCKO1, 256 fS and 384 fS of 48 kHz for SCKO2 and SCKO3), CL = 20 pF on measurement pin, unless otherwise noted. 6 PLL1705 PLL1706 www.ti.com SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002 DUTY CYCLE vs FREE-AIR TEMPERATURE 55 55 53 53 SCKO0 51 49 SCKO1 SCKO2 Duty Cycle – % Duty Cycle – % DUTY CYCLE vs SUPPLY VOLTAGE SCKO3 51 SCKO2 SCKO3 49 SCKO0 47 47 MCKO2 MCKO2 MCKO1 MCKO1 45 2.7 SCKO1 3.0 3.3 VCC – Supply Voltage – V Figure 5 3.6 45 –50 –25 0 25 50 75 100 TA – Free-Air Temperature – °C Figure 6 NOTE: All specifications at TA = 25°C, VDD1–3 (= VDD) = VCC = +3.3 V, fM = 27 MHz, crystal oscillation, C1, C2 = 15 pF, default frequency (33.8688 MHz for SCKO0, 33.8688 MHz for SCKO1, 256 fS and 384 fS of 48 kHz for SCKO2 and SCKO3), CL = 20 pF on measurement pin, unless otherwise noted. 7 PLL1705 PLL1706 www.ti.com SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002 THEORY OF OPERATION MASTER CLOCK AND SYSTEM CLOCK OUTPUT The PLL1705/6 consists of a dual PLL clock and master clock generator which generates four system clocks and two buffered 27-MHz clocks from a 27-MHz master clock. Figure 7 shows the block diagram of the PLL1705/6. The PLL is designed to accept a 27-MHz master clock. SCKO3 384 fS Counter N SCKO0–3 Frequency Control Phase Detector and Loop Filter Divider VCO Counter M Divider PLL2 PLL1 Counter M Phase Detector and Loop Filter VCO Counter N OSC XT1 XT2 MCKO1 27 MHz Divider MCKO2 27 MHz SCKO0 33.8688 MHz Figure 7. Block Diagram 8 SCKO1 33.8688/16.9344 MHz SCKO2 256 fS PLL1705 PLL1706 www.ti.com SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002 The master clock can be either a crystal oscillator placed between XT1 (pin 10) and XT2 (pin 11), or an external input to XT1. If an external master clock is used, XT2 must be open. Figure 8 illustrates possible system clock connection options, and Figure 9 illustrates the 27-MHz master clock timing requirement. MCKO2 MCKO2 MCKO1 MCKO1 27-MHz Internal Master Clock XT1 C1 Crystal Crystal OSC Circuit XT1 External Clock Crystal OSC Circuit XT2 27-MHz Internal Master Clock XT2 C2 PLL1705/PLL1706 PLL1705/PLL1706 C1, C2 = 10 pF to 33 pF Crystal Resonator Connection External Clock Input Connection Figure 8. Master Clock Generator Connection Diagram t(XT1H) 0.7 VCC XT1 0.3 VCC t(XT1L) DESCRIPTION SYMBOL MIN MAX UNIT Master clock pulse duration HIGH tXT1H 10 ns Master clock pulse duration LOW tXT1L 10 ns Figure 9. External Master Clock Timing Requirement The PLL1705/6 provides a very low-jitter, high-accuracy clock. SCKO0 outputs a fixed 33.8688-MHz clock, SCKO1 outputs 384 fS or 768 fS (fS = 44.1 kHz) which is selected by CSEL (pin 12) for a CD-DA DSP. The output frequency of the remaining clocks is determined by the sampling frequency (fS) under hardware or software control. SCKO2 and SCKO3 output 256-fS and 384-fS system clocks, respectively. Table 2 shows each sampling frequency, which can be programmed. The system clock output frequencies for programmed sampling frequencies are shown in Table 3. Table 1. Generated System Clock SCKO1 Frequency CSEL SCKO1 FREQUENCY LOW 33.8688 MHz HIGH 16.9344 MHz Table 2. Sampling Frequencies SAMPLING RATE SAMPLING FREQUENCY (kHz) Standard sampling frequencies 32 44.1 48 Double sampling frequencies 64 88.2 96 9 PLL1705 PLL1706 www.ti.com SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002 Table 3. Sampling Frequencies and System Clock Output Frequencies SAMPLING FREQUENCY (kHz) SAMPLING RATE SCKO2 (MHZ) SCKO3 (MHZ) 32 Standard 8.192 12.288 44.1 Standard 11.2896 16.9344 48 Standard 12.288 18.432 64 Double 16.384 24.576 88.2 Double 22.5792 33.8688 96 Double 24.576 36.864 Response time from power on (or applying the clock to XT1) to SCKO settling time is typically 3 ms. Delay time from sampling frequency change to SCKO settling is 200 ns maximum. This clock transient timing is not synchronized with the SCKOx signals. Figure 10 illustrates SCKO transient timing in the PLL1706. External buffers are recommended on all output clocks in order to avoid degrading the jitter performance of the PLL1705/6. ML 200 ns 1–2 Clocks of MCKO1,2 SCKO2 SCKO3 Stable Clock Transition Region SCKO0 SCKO1 Stable 33.8688 MHz, 384 or 768 of 44.1 kHz Figure 10. System Clock Transient Timing POWER-ON RESET The PLL1705/6 has an internal power-on reset circuit. The mode register of PLL1706 is initialized with default settings by power-on reset. Throughout the reset period, all clock outputs are enabled with the default settings after power up time. Initialization by internal power-on reset is done automatically during 1024 master clocks at VDD > 2.0 V (TYP). Power-on reset timing is shown in Figure 11. VDD 2.4 V 2.0 V 1.6 V Reset Internal Reset 1024 Master Clocks Master Clock Figure 11. Power-On Reset Timing 10 Reset Removal PLL1705 PLL1706 www.ti.com SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002 FUNCTION CONTROL The built-in functions of the PLL1705 can be controlled in the parallel mode (hardware mode), which uses SR (pin 7), FS1 (pin 5) and FS2 (pin 6). The PLL1706 can be controlled in the serial mode (software mode), which uses a three-wire interface by ML (pin 7), MC (pin 6), and MD (pin 5). The selectable functions are shown in Table 4. Table 4. Selectable Functions PARALLEL MODE SERIAL MODE Sampling frequency select (32 kHz, 44.1 kHz, 48 kHz) SELECTABLE FUNCTION Yes Yes Sampling rate select (standard/double) Yes Yes Each clock output enable/disable No Yes Power down No Yes PLL1705 (Parallel Mode) In the parallel mode, the following functions can be selected: Sampling Frequency Group Select The sampling frequency group can be selected by FS1 (pin 5) and FS2 (pin 6). FS2 (PIN 6) FS1 (PIN 5) SAMPLING FREQUENCY LOW LOW 48 kHz 44.1 kHz LOW HIGH HIGH LOW 32 kHz HIGH HIGH Reserved Sampling Rate Select The sampling rate can be selected by SR (pin 7) SR (PIN 7) SAMPLING RATE LOW Standard HIGH Double PLL1706 (Serial Mode) The built-in functions of the PLL1706 are shown in Table 5. These functions are controlled using the ML, MC, and MD serial control signals. Table 5. Selectable Functions SELECTABLE FUNCTION Sampling frequency select (32 kHz, 44.1 kHz, 48 kHz) Sampling rate select (standard/double) DEFAULT 48-kHz group Standard Each clock output enable/disable Enabled Power down Disabled 11 PLL1705 PLL1706 www.ti.com SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002 Program-Register Bit Mapping The built-in functions of the PLL1706 are controlled through a 16-bit program register. This register is loaded using MD, MC and ML. After the 16 data bits are clocked in using the rising edge of MC, ML is used to latch the data into the register. Table 6 shows the bit mapping of the register. The serial mode control format and control data input timing are shown in Figure 12 and Figure 13, respectively. ML MC MD D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Figure 12. Serial Mode Control Format t(MHH) t(MLL) ML VDD/2 t(MLS) t(MCH) t(MCL) t(MLS) t(MLH) MC VDD/2 t(MCY) MD MSB LSB VDD/2 t(MDH) t(MDS) DESCRIPTION SYMBOL MIN tMCY tMCL 100 ns 40 ns 40 ns MD hold time tMCH tMDH 40 ns MD setup time tMDS 40 ML low-level time tMLL 16 ns MC clocks(1) ML high-level time ML hold time(2) tMHH 200 ns tMLH 40 ns MC pulse cycle time MC pulse duration LOW MC pulse duration HIGH TYP ML setup time(3) tMLS 40 (1) MC clocks: MC clock period (2) MC rising edge for LSB to ML rising edge (3) ML rising edge to the next MC rising edge. If the MC clock is stopped after the LSB, any ML rise time is accepted. Figure 13. Control Data Input Timing 12 MAX UNIT ns PLL1705 PLL1706 www.ti.com SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002 Mode Register D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 1 0 0 CE6 CE5 CE4 CE3 CE2 CE1 RSV SR FS2 FS1 Table 6. Register Mapping REGISTER Mode control BIT NAME DESCRIPTION CE6 MCKO2 output enable/disable CE5 MCKO1 output enable/disable CE4 SCKO1 output enable/disable CE3 SCKO3 output enable/disable CE2 SCKO2 output enable/disable CE1 SCKO0 output enable/disable RSV Reserved, must be 0 SR Sampling rate select FS[2:1] Sampling frequency select FS[2:1]: Sampling Frequency Group Select FS2 FS1 SAMPLING FREQUENCY DEFAULT 0 0 48 kHz O 0 1 44.1 kHz 1 0 32 kHz 1 1 Reserved SR: Sampling Rate Select SR SAMPLING RATE DEFAULT 0 Standard O 1 Double CE [6:1]: Clock Output Control CE1–CE6 CLOCK OUTPUT CONTROL 0 Clock output disable 1 Clock output enable DEFAULT O While all the bits of CE [6:1] are 0, the PLL1706 goes into the power-down mode, all dynamic operation including PLLs and the oscillator halt, but serial mode control is enabled for resumption. CONNECTION DIAGRAM Figure 14 shows the typical connection circuit for the PLL1705. There are four grounds for digital and analog power supplies. However, the use of one common ground connection is recommended to avoid latch-up or other power-supply-related troubles. Power supplies should be bypassed as close as possible to the device. MPEG-2 APPLICATIONS Typical applications for the PLL1705/6 are MPEG-2 based systems such as DVD players, DVD add-on cards for multimedia PCs, digital HDTV systems, and set-top boxes. The PLL1705/6 provides audio system clocks for a CD-DA DSP, DVD DSP, Karaoke DSP, and DAC(s) from a 27-MHz video clock. 13 PLL1705 PLL1706 www.ti.com SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002 3.3 V (2) PLL1705/6 1 VDD1 2 VDD3 20 SCKO2 SCKO0 19 3 SCKO3 SCKO1 18 4 DGND1 DGND3 17 5 FS1 (MD) DGND2 16 6 FS2 (MC) MCKO2 15 7 SR(ML) MCKO1 14 8 VCC VDD2 13 9 AGND CSEL 12 XT2 11 (1) (1) (4) (1) (2) (1) 10 XT1 (3) (3) Clock Outputs (5) (1) 0.1-µF ceramic capacitor typical, depending on quality of power supply and pattern layout (2) 10-µF aluminum electrolytic capacitor typical, depending on quality of power supply and pattern layout (3) 27-MHz quartz crystal and 10–33 pF × 2 ceramic capacitors, which generate the appropriate amplitude of oscillation on XT1/XT2 (4) This connection is for PLL1705 (parallel mode); when PLL1706 (serial mode) is to be used, control pins must be connected to serial interfaced controller. (5) For good jitter performance, minimize the load capacitance on the clock output. Figure 14. Typical Connection Diagram 14 PLL1705 PLL1706 www.ti.com SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002 BLOCK DIAGRAM OF MPEG-2 BASED SYSTEM APPLICATION PLL1705/6 384 fS SCKO3 27-MHz Crystal 256 fS PCM1716 Front PCM1716 Surround SCKO2 MCKO1/2 27 MHz SCKO0 or 1 Center CD-DA/ DVD DSP MPEG/AC-3 Audio Decoder PCM1716 Subwoofer 15 PLL1705 PLL1706 www.ti.com SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002 MECHANICAL DATA DBQ (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 0.012 (0,30) 0.008 (0,20) 0.025 (0,64) 24 0.005 (0,13) 13 0.157 (3,99) 0.150 (3,81) 0.244 (6,20) 0.228 (5,80) 0.008 (0,20) NOM Gauge Plane 1 12 A 0.010 (0,25) 0°–8° 0.035 (0,89) 0.016 (0,40) 0.069 (1,75) MAX Seating Plane 0.010 (0,25) 0.004 (0,10) 0.004 (0,10) PINS ** 16 20 24 28 A MAX 0.197 (5,00) 0.344 (8,74) 0.344 (8,74) 0.394 (10,01) A MIN 0.189 (4,80) 0.337 (8,56) 0.337 (8,56) 0.386 (9,80) M0–137 VARIATION AB AD AE AF DIM D 4073301/F 02/02 NOTES:A. B. C. D. 16 All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MO–137. IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third–party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2002, Texas Instruments Incorporated