BU2279F Multimedia ICs Clock generator for PC BU2279F BU2279F is an IC that generates multiple clocks from the built-in PLL by inputting standard clocks from outside. This IC is suitable for digital appliances. 54 MHz for video and 33.333MHz of digital system clock for CPU can be generated from widely used 13.5 MHz clock. zExternal dimensions (Units : mm) zApplications DVD recorder, PC 1.5±0.1 1 8 0.3Min. 9 4.4±0.2 zFeatures 1) Clock signals are generated by crystal oscillator. 2) SOP16 package. 3) Single power supply 3.3V. 4) No external components for PLL 0.11 6.2±0.3 10.0±0.2 16 1.27 0.15±0.1 0.1 0.4±0.1 SOP16 zAbsolute maximum rating（Ta=25°C） Parameter Symbol Limits Unit Impressed voltage VDD −0.5 ~ 7.0 V Input voltage VIN V Storage temperature range Pd −0.5 ~ VDD+0.5 500 ∗ mW Tstg −30 ~ 125 °C Power dissipation ∗ Ratio above does not guarantee the operation. ∗ When the condition is over Ta=25 C, dissipatioin is decreased 5mWper 1 C. ∗ Radiation resistance design is not used. ∗ Power dissipation is. zRecommended operational conditions（Ta=25°C） Parameter Symbol Min. Typ. Max. Unit Power supply voltage VDD 3.0 – 3.6 V Voltage range of "H" input VIH 0.8VDD – VDD V Voltage range of "L" input Operation temperature range Maximum output load VIL 0 – 0.2VDD V Topr −5 – 70 °C CL – – 15 pF 1/2 BU2279F Multimedia ICs zElectric Characteristics (Unless any specification, Vcc=3.3V, Ta=25°C, Crystal frequency=13.500MHz) Parameter Output "L" voltage Symbol Min. Typ. Max. Unit VOL − − 0.4 V V Conditions IOL=4.0mA Output "H" voltage VOH 24 − − Operation current IDD − 30 60 mA VCLK VCLK − 54.00 − MHz Xtal 160 20 2 SCLK SCLK − 33.333 − MHz Xtal 400 27 6 VCLK Duty Duty V 45 50 55 % Measured at 1/2VDD SCLK Duty Measured at 1/2VDD IOH=−4.0mA No load + + Design assurances Duty S 48 53 58 % Jitter1 Jstd1 − 80 − psec Jitter 1σ Jitter2 Jstd2 − 400 − psec Jitter MIN=MAX tr − 2.5 − nsec tr − 2.5 − nsec tLOCK − − 1 msec Rise time Fall time LOCK time of output ∗ Remarks ) The output frequency is calculated from the input frequency of XTALIN. The value of output frequency above is the case of input frequency is 13.5MHz. The values of Jitter above are the center value of 10000 sampling by time interval analyzer. ∗) The time for output frequency to be stabled after the power supply become 3.0V. zApplication circuit Fixed to "L" Fixed to "L" 1 CTRL1 OE 16 2 TEST1 CTRL3 15 3 CTRL2 TEST2 14 4 AGND AVDD 13 5 DGND DVDD 12 6 DVDD SCLK 11 7 XTALIN DVDD 10 8 XTALOUT VCLK 9 Fixed to "L" 33.3MHz output 0.1µF 54MHz output BU2279F 0.1µF 0.1µF 0.1µF Remarks) The IC is basically needed to be on the board. (Unless it is on the board, the characteristics are not guaranteed.) Decoupling capacitance(0.1µF) is needed to be placed between 13PIN(AVDD) and 4PIN(AGND).Decoupling capacitance(0.1µF)is needed to be placed between 16PIN(DVDD) 10PIN(DVDD), 12PIN(DVDD) and 5PIN(DGND) each. To adjust the frequency of crystal, place a certain value of capacitance(pF) between 7 or 8PIN and DGND. 2pin and 4pin are needed to be fixed to "OPEN" through the operation. 2/2