PI6C410BS

PI6C410BS
Clock Generator for Intel
PCIe® Server Chipset
Features
Description
•
•
PI6C410BS is a high-speed, low-noise clock generator designed to
work with Intel Server PCIe® Chipset. The Spread Spectrum PLL
based clock generator reduces EMI emission and supports a wide
range of frequencies.
•
•
•
14.318 MHz Crystal Input
Selectable of 100, 133, 166, 200, 266, 333, and 400 MHz
CPU Output Frequencies
SMBus: Power Management Control
Spread Spectrum support (-0.5% down spread)
Packaging (Pb-free & Green):
—56-Pin TSSOP (A)
Jitter Performance
•
•
•
•
•
Output Features
•
•
•
•
•
Four Pairs of Differential CPU Clocks
Five Pairs of SRC Clocks
Seven PCI Clocks
One 48 MHz USB clock
Two REF clocks
Skew Performance
• < 100ps Output to output CPU clock skew
• < 500ps Output to output PCI clock skew
• < 250ps Output to output SRC clock skew
Block Diagram
XT AL_IN
XT AL_OUT
Pin Configuration
XT AL
OSC
PLL 2
SCL
SM Bus
Logic
FS_A
FS_C/TEST_SEL
VTT_PWRGD#
/PWRDWN
CONTROL
FS_B/TEST_MODE
VDD_PCI
VSS_PCI
PCI_0
PCI_1
PCI_2
PCI_3
VSS_PCI
VDD_PCI
PCIF_0
PCIF_1
PCIF_2
VDD_48
USB_48
VSS_48
VDD_SRC
SRC_0
SRC_0#
SRC_1#
SRC_1
VSS_SRC
SRC_2
SRC_2#
SRC_3#
SRC_3
VDD_SRC
SRC_4
SRC_4#
VDD_SRC
USB_48
REF [0:1]
PLL 1
SDA
DIV
PCI [0:3]
PCIF [0:2]
DIV
SRC [0:4]
SRC [0:4]#
DIV
CPU [0:3]
CPU [0:3]#
IREF
09-0003
< 85ps Cycle-to-Cycle CPU clock jitter
< 350ps Cycle-to-Cycle 48MHz clock jitter
< 500ps Cycle-to-Cycle PCI clock jitter
< 125ps Cycle-to-Cycle SRC clock jitter
< 1000ps Cycle-to-Cycle REF clock jitter
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
FS_C / TEST_SEL
REF_0
REF_1
VDD_REF
XTAL_IN
XTAL_OUT
VSS_REF
FS_B/TEST_MODE
FS_A
VDD_CPU
CPU_0
CPU_0#
VDD_CPU
CPU_1
CPU_1#
VSS_CPU
CPU_2
CPU_2#
VDD_CPU
CPU_3
CPU_3#
VDD_A
VSS_A
IREF
NC
VTT_PWRGD# / PWRDWN
SDA
SCL
PS8879G
10/15/09
PI6C410BS
Clock Generator for Intel PCIe® Server Chipset
Pin Descriptions
Pin Name
Type
Pin No
Descriptions
REF[0:1]
Output
54, 55
3.3V 14.31818 MHz outputs
XTAL_IN
Input
52
14.31818 MHz crystal input
XTAL_OUT
Output
51
14.31818 MHz crystal output
CPU[0:3] & CPU[0:3]#
Output
36, 37; 39, 40; 42,
43; 45, 46
SRC[0:4] & SRC[0:4]#
Output
16, 17; 18, 19; 21, 22;
23, 24; 26, 27
PCIF[0:2]
Output
9, 10, 11
33 MHz clocks outputs (free running)
PCI[0:3]
Output
3, 4, 5, 6
33 MHz clocks outputs
USB_48
Output
13
48 MHz clock output
FS_A
Input
48
3.3V LVTTL inputs for CPU frequency selection
FS_B / TEST_MODE
Input
49
3.3V LVTTL inputs for CPU frequency selection / Test Mode
select: 0 = Hi-Z, 1 = Ref/N
FS_C / TEST_SEL
Input
56
3.3V LVTTL inputs for CPU frequency selection / Test Mode
select if pulled to 3.3V when Vtt_Pwrgd# is asserted LOW
IREF
Input
33
External resistor connection for internal current reference
VTT_PWRGD# /
PWRDWN
Input
31
3.3V LVTTL Level sensitive strobe used to determine to latch the
FS_A, FS_B/TEST_MODE and FS_C/TEST_SEL inputs (active
low) / 3.3V LVTTL active high input for Power Down operation.
SDA
I/O
30
SMBus compatible SDATA
SCL
Input
29
SMBus compatible SCLOCK
VDD_PCI
Power
1, 8
3.3V Power Supply for Outputs
VDD_48
Power
12
3.3V Power Supply for Outputs
VDD_SRC
Power
15, 25, 28
3.3V Power Supply for Outputs
VDD_CPU
Power
38, 44, 47
3.3V Power Supply for Outputs
VDD_REF
Power
53
3.3V Power Supply for Outputs
VSS_PCI
Ground
2, 7
Ground for Outputs
VSS_48
Ground
14
Ground for Outputs
VSS_SRC
Ground
20
Ground for Outputs
VSS_CPU
Ground
41
Ground for Outputs
VSS_REF
Ground
50
Ground for Outputs
VDD_A
Power
35
3.3V Power Supply for PLL
VSS_A
Ground
34
Ground for PLL
09-0003
Differential CPU outputs
Differential Serial Reference Clock outputs
2
PS8879G
10/15/09
PI6C410BS
Clock Generator for Intel PCIe® Server Chipset
Functionality
Frequency Selection
FS_C
FS_B
FS_A
CPU
SRC
PCIF / PCI
REF
USB_48
Note
1
0
1
100 MHz
100 MHz
33 MHz
14.318 MHz
48 MHz
1
0
0
1
133 MHz
100 MHz
33 MHz
14.318 MHz
48 MHz
1
0
1
1
166 MHz
100 MHz
33 MHz
14.318 MHz
48 MHz
1
0
1
0
200 MHz
100 MHz
33 MHz
14.318 MHz
48 MHz
1
0
0
0
266 MHz
100 MHz
33 MHz
14.318 MHz
48 MHz
1
1
0
0
333 MHz
100 MHz
33 MHz
14.318 MHz
48 MHz
1
1
1
0
400 MHz
100 MHz
33 MHz
14.318 MHz
48 MHz
1
1
1
1
Reserved
100 MHz
33 MHz
14.318 MHz
48 MHz
1
Notes:
1. Refer to DC Electrical Characteristics for FS_A, FS_B and FS_C (Vih_FS, Vil_FS) threshold levels
Test Mode Selection
TEST_MODE
CPU
SRC
PCIF / PCI
REF
USB_48
Note
1
REF/N
REF/N
REF/N
REF
REF/N
2
0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
2
Notes:
2.
Test mode will occur where the SMBus Bit 6 of Byte 6 = 1, or FS_C/TEST_SEL is set to logic high level.
PWRDWN Functionality
PWRDWN
CPU
CPU#
SRC
SRC#
PCIF / PCI
REF
USB_48
0
Normal
Normal
Normal
Normal
33 MHz
14.318 MHz
48 MHz
1
Iref × 2 or
Float
Float
Iref × 2 or
Float
Float
Low
Low
Low
09-0003
3
PS8879G
10/15/09
PI6C410BS
Clock Generator for Intel PCIe® Server Chipset
Serial Data Interface (SMBus)
PI6C410BS is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7-bit address and read/write bit as shown below.
Address Assignment
A6
A5
A4
A3
A2
A1
A0
R/W
1
1
0
1
0
0
1
0/1
Data Protocol
1 bit
7 bits
Start
bit
Slave
Addr
1
R/W
1
8 bits
Ack
Register
offset
1
8 bits
Ack
Byte
Count = N
1
8 bits
Ack
Data Byte
0
1
8 bits
1
1 bit
Ack
Data Byte
N-1
Ack
Stop bit
…
Note:
1. Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0.
Data Byte 0: Control Register
Bit
Descriptions
Type
Power-Up
Condition
Output(s) Affected
Pin
Source Pin
0
SRC_0 Output Enable
1 = Enabled, 0 = Disabled (Hi-Z)
RW
1 = Enabled
SRC_0
17, 18
NA
1
SRC_1 Output Enable
1 = Enabled, 0 = Disabled (Hi-Z)
RW
1 = Enabled
SRC_1
19, 20
NA
2
SRC_2 Output Enable
1 = Enabled, 0 = Disabled (Hi-Z)
RW
1 = Enabled
SRC_2
22, 23
NA
3
SRC_3 Output Enable
1 = Enabled, 0 = Disabled (Hi-Z)
RW
1 = Enabled
SRC_3
24, 25
NA
4
SRC_4 Output Enable
1 = Enabled, 0 = Disabled (Hi-Z)
RW
1 = Enabled
SRC_4
26, 27
NA
5
Reserved
RW
6
Reserved
RW
7
Reserved
RW
09-0003
4
PS8879G
10/15/09
PI6C410BS
Clock Generator for Intel PCIe® Server Chipset
Data Byte 1: Control Register
Bit
Descriptions
Type
Power-Up
Condition
Output(s) Affected
Pin
Source Pin
NA
0
Spread Spectrum
1 = On, 0 = Off
RW
0 = Spread off
CPU[0:3], SRC[0:4],
PCI[0:3], PCIF[0:2]
3, 4, 5, 6, 9, 10,
11, 16, 17, 18, 19,
21, 22, 23, 24, 26,
27, 36, 37, 39, 40,
42, 43, 45, 46
1
CPU_0 output enable
1 = Enabled, 0 = Disabled (Hi-Z)
RW
1 = Enabled
CPU_0, CPU_0#
45, 46
NA
2
CPU_1 output enable
1 = Enabled, 0 = Disabled (Hi-Z)
RW
1 = Enabled
CPU_1, CPU_1#
42, 43
NA
3
Reserved
RW
4
CPU_2 output enable
1 = Enabled, 0 = Disabled (Hi-Z)
RW
1 = Enabled
CPU_2, CPU_2#
39, 40
NA
5
CPU_3 output enable
1 = Enabled, 0 = Disabled (Hi-Z)
RW
1 = Enabled
CPU_3, CPU_3#
36, 37
NA
6
REF0 Output Enable
1 = Enabled, 0 = Disabled
RW
1 = Enabled
REF_0
55
NA
7
REF1 Output Enable
1 = Enabled, 0 = Disabled
RW
1 = Enabled
REF_1
54
NA
Type
Power-Up
Condition
Output(s) Affected
Pin
Source Pin
Data Byte 2: Control Register
Bit
Descriptions
0
USB_48 Output Enable
1 = Enabled, 0 = Disabled
RW
1 = Enabled
USB_48
13
NA
1
PCIF_0 Output Enable
1 = Enabled, 0 = Disabled
RW
1 = Enabled
PCIF_0
9
NA
2
PCIF_1 Output Enable
1 = Enabled, 0 = Disabled
RW
1 = Enabled
PCIF_1
10
NA
3
PCIF_2 Output Enable
1 = Enabled, 0 = Disabled
RW
1 = Enabled
PCIF_2
11
NA
4
PCI_0 Output Enable
1 = Enabled, 0 = Disabled
RW
1 = Enabled
PCI_0
3
NA
5
PCI_1 Output Enable
1 = Enabled, 0 = Disabled
RW
1 = Enabled
PCI_1
4
NA
6
PCI _2 Output Enable
1 = Enabled, 0 = Disabled
RW
1 = Enabled
PCI_2
5
NA
7
PCI _3 Output Enable
1 = Enabled, 0 = Disabled
RW
1 = Enabled
PCI_3
6
NA
09-0003
5
PS8879G
10/15/09
PI6C410BS
Clock Generator for Intel PCIe® Server Chipset
Data Byte 3: Control Register
Bit
Descriptions
Type
Power-Up
Condition
Output(s) Affected
Pin
Source Pin
0
SRC_0 Output Control
0 = Free Running
1 = Stopped with PCI_STOP#
RW
0 = Free running
SRC_0, SRC_0#
16, 17
NA
1
SRC_1 Output Control
0 = Free Running
1 = Stopped with PCI_STOP#
RW
0 = Free running
SRC_1, SRC_1#
18, 19
NA
2
SRC_2 Output Control
0 = Free Running
1 = Stopped with PCI_STOP#
RW
0 = Free running
SRC_2, SRC_2#
21, 22
NA
3
SRC_3 Output Control
0 = Free Running
1 = Stopped with PCI_STOP#
RW
0 = Free running
SRC_3, SRC_3#
23, 24
NA
4
SRC_4 Output Control
0 = Free Running
1 = Stopped with PCI_STOP#
RW
0 = Free running
SRC_4, SRC_4#
26, 27
NA
5
PCIF0 Output Control
0 = Free Running
1 = Stopped with PCI_STOP#
RW
0 = Free running
PCIF_0
9
NA
6
PCIF1 Output Control
0 = Free Running
1 = Stopped with PCI_STOP#
RW
0 = Free running
PCIF_1
10
NA
7
PCIF2 Output Control
0 = Free Running
1 = Stopped with PCI_STOP#
RW
0 = Free running
PCIF_2
11
NA
09-0003
6
PS8879G
10/15/09
PI6C410BS
Clock Generator for Intel PCIe® Server Chipset
Data Byte 4: Control Register
Bit
Descriptions
Type
Power-Up
Condition
Output(s) Affected
Pin
Source Pin
0
CPU_0 Output Control
0 = Free Running
1 = Stopped with CPU_STOP#
RW
1 = Stopped with
CPU_STOP#
assertion
CPU_0, CPU0#
45, 46
NA
1
CPU_1 Output Control
0 = Free Running
1 = Stopped with CPU_STOP#
RW
1 = Stopped with
CPU_STOP#
assertion
CPU_1, CPU1#
42, 43
NA
2
CPU_2 Output Control
0 = Free Running
1 = Stopped with CPU_STOP#
RW
1 = Stopped with
CPU_STOP#
assertion
CPU_2, CPU2#
39, 40
NA
3
CPU_3 Output Control
0 = Free Running
1 = Stopped with CPU_STOP#
RW
1 = Stopped with
CPU_STOP#
assertion
CPU_3, CPU3#
36, 37
NA
4
CPU_0 Pwrdwn drive mode
1 = Hi-Z, 0 = Driven in Pwrdwn
RW
0 = Driven in
power down
CPU_0, CPU0#
45, 46
NA
5
CPU_1 Pwrdwn drive mode
1 = Hi-Z, 0 = Driven in Pwrdwn
RW
0 = Driven in
power down
CPU_1, CPU1#
42, 43
NA
6
CPU_2 Pwrdwn drive mode
1 = Hi-Z, 0 = Driven in Pwrdwn
RW
0 = Driven in
power down
CPU_2, CPU2#
39, 40
NA
CPU_3, CPU3#
36, 37
NA
7
CPU_3 Pwrdwn drive mode
1 = Hi-Z, 0 = Driven in Pwrdwn
RW
0 = Driven in
power down
Data Byte 5: Control Register
Bit
Descriptions
Type
Power-Up
Condition
Output(s) Affected
Pin
Source Pin
0
CPU_0 CPU_Stop drive mode
1 = Hi-Z, 0 = Driven in CPU Stop
RW
0 = Driven in
CPU_Stop
CPU_0, CPU0#
45, 46
NA
1
CPU_1 CPU_Stop drive mode
1 = Hi-Z, 0 = Driven in CPU Stop
RW
0 = Driven in
CPU_Stop
CPU_1, CPU1#
42, 43
NA
2
CPU_2 CPU_Stop drive mode
1 = Hi-Z, 0 = Driven in CPU Stop
RW
0 = Driven in
CPU_Stop
CPU_2, CPU2#
39, 40
NA
3
CPU_3 CPU_Stop drive mode
1 = Hi-Z, 0 = Driven in CPU Stop
RW
0 = Driven in
CPU_Stop
CPU_3, CPU3#
36, 37
NA
4
Reserved
RW
5
SRC_Pwrdwn drive mode
1 = Hi-Z,
0 = Driven in Pwrdwn
RW
0 = Driven in
power down
SRC[0:4] &
SRC[0:4]#
16, 17, 18, 19,
21, 22, 23, 24,
26, 27
NA
6
SRC_Stop drive mode
1 = Hi-Z,
0 = Driven in PCI_STOP
RW
0 = Driven in
PCI_STOP
SRC[0:4] &
SRC[0:4]#
16, 17, 18, 19,
21, 22, 23, 24,
26, 27
NA
7
Reserved
RW
09-0003
7
PS8879G
10/15/09
PI6C410BS
Clock Generator for Intel PCIe® Server Chipset
Data Byte 6: Control Register
Type
Power-Up
Condition
Output(s) Affected
Pin
Source Pin
0
FS_A Reflects the value of the
FS_A pin sampled on power up
0 = FS_A was low during
Vtt_Pwrgd# assertion
R
Externally
Selected
CPU[0:3]
36, 37, 39, 40,
42, 43, 45, 46
NA
1
FS_B Reflects the value of the
FS_B pin sampled on power up
0 = FS_B was low during
Vtt_Pwrgd# assertion
R
Externally
Selected
CPU[0:3]
36, 37, 39, 40,
42, 43, 45, 46
NA
2
FS_C Reflects the value of the
FS_C pin sampled on power up
0 = FS_C was low during
Vtt_Pwrgd# assertion
R
Externally
Selected
CPU[0:3]
36, 37, 39, 40,
42, 43, 45, 46
NA
3
PCI_Stop Output Control
0 = Enabled, all stoppable PCI
and SRC clocks are stopped,
1 = Disabled
RW
1 = Disabled
All PCI & SRC
clocks except PCIF
and SRC clocks set to
free-running
3, 4, 5, 6, 16,
17, 18, 19, 21,
22, 23, 24, 26,
27
NA
4
REF Output Drive Strength
0 = 1X, 1 = 2X
RW
1 = 2X
REF_0, REF_1
54, 55
NA
5
Reserved
RW
6
Test Clock Mode Entry Control
0 = Normal, 1 = REF/N or Hi-Z
RW
0 = Disabled
7
Test Clock Mode
0 = Hi-Z, 1 = REF/N
RW
0 = Hi-Z
Bit
Descriptions
NA
Data Byte 7: Pericom ID Register
Type
Power-Up
Condition
Output(s) Affected
Pin
R
0
NA
NA
R
0
NA
NA
R
0
NA
NA
3
R
0
NA
NA
4
R
0
NA
NA
R
0
NA
NA
R
0
NA
NA
R
0
NA
NA
Bit
Descriptions
0
1
Vendor ID
2
5
Revision Code
6
7
09-0003
8
PS8879G
10/15/09
PI6C410BS
Clock Generator for Intel PCIe® Server Chipset
Power Down (PWRDWN assertion)
PWRDWN
CPU, 133MHz
CPU#, 133MHz
SRC, 100MHz
SRC#, 100MHz
USB, 48MHz
PCI, 33MHz
REF, 14.318MHz
Figure 1. Power down sequence
Power Down (PWRDWN De-assertion)
Tstable
< 1.8ms
PWRDWN
CPU, 133MHz
CPU#, 133MHz
SRC, 100MHz
SRC#, 100MHz
USB, 48MHz
PCI, 33MHz
REF, 14.318MHz
Tdrive_PWRDWN
< 300us, >200mV
Figure 2. Power down de-assert sequence
09-0003
9
PS8879G
10/15/09
PI6C410BS
Clock Generator for Intel PCIe® Server Chipset
Tristate Specifications
CPU & SRC Tristate clock truth table
Signal
Pwrdwn pin
Pwrdwn Tristate Bit
Stoppable
Outputs
Non-stop
Outputs
0
X
Running
Running
1
0
Driven @ Iref x 2
Driven @ Iref x 2
1
1
Tristate
Tristate
CPU[0:3],
SRC[0:4],
Spread Spectrum Specifications
Supports Spread Spectrum clocking and can be enabled and disabled via SMBus control. The maximum Spread Spectrum Modulation is –0.5% down spread with frequency from 30KHz to 33K Hz.
Tperiod
SSC ON
Tperiod
SSC OFF
Min
Max
CPU @ 399.000MHz
2.4993
2.5133
CPU @ 332.500MHz
2.9991
CPU @ 266.000MHz
Unit
Min
Max
CPU @ 400.000MHz
2.4993
2.5008
3.0160
CPU @ 333.333MHz
2.9991
3.0009
3.7489
3.7700
CPU @ 266.666MHz
3.7489
3.7511
CPU @ 199.500MHz
4.9985
5.0266
CPU @ 200.000MHz
4.9985
5.0015
CPU @ 166.250MHz
5.9982
6.0320
CPU @ 166.666MHz
5.9982
6.0018
CPU @ 133.000MHz
7.4978
7.5400
CPU @ 133.333MHz
7.4978
7.5023
CPU @ 99.750MHz
9.9970
10.0533
CPU @ 100.000MHz
9.9970
10.0030
SRC @ 99.750MHz
9.9970
10.0533
SRC @ 100.000MHz
9.9970
10.0030
PCIF / PCI @
33.250MHz
29.9910
30.1598
PCIF / PCI @
33.333MHz
29.9910
30.0090
ns
Crystal Recommendations
Frequency
Cut
Loading
Load
Cap
Drive
Max.
Shunt
Cap Max.
Motional
Cap Max.
Tolerance
Max.
Stability
Max.
Aging
Max.
14.31818 MHz
AT
Parallel
20pF
0.1mW
5pF
0.016pF
50ppm
50ppm
5ppm
Notes:
1. External trim capacitors (Ce) are required by using this formula Ce = 2*CL – (Cs + Ci). Typical Ce = 33pF when Crystal Load = 20pF, Trace
capacitance (Cs) = 2.8pF and XTAL pins capacitance = 4.5pF.
09-0003
10
PS8879G
10/15/09
PI6C410BS
Clock Generator for Intel PCIe® Server Chipset
Current-mode output buffer characteristics of CPU and SRC
VDD
(3.3V ±5%)
Slope ~ 1/RO
RO
IOUT
ROS
IOUT
VOUT = 0.85V max
0.85V
0V
Figure 3. Simplified diagram of current-mode output buffer
Host Clock Buffer characteristics
Symbol
Minimum
Maximum
RO
3000Ω
N/A
ROS
unspecified
unspecified
VOUT
N/A
850mV
Current Accuracy
Symbol
Conditions
Configuration
Load
Min.
Max.
IOUT
VDD = 3.30 ±5%
RREF = 475Ω 1%
IREF = 2.32mA
Nominal test load for given
configuration
-12% INOMINAL
+12% INOMINAL
Note:
1. INOMINAL refers to the expected current based on the configuration of the device.
Host Clock Output Current
Board Target
Trace/Term Z
Reference R,
IREF = VDD/(3xRr)
Output Current
VOH @ Z
100Ω
(100Ω differential ≈ 8% coupling ratio)
RREF = 475Ω 1%,
IREF = 2.32mA
IOH = 6 x IREF
0.7V @ 50
09-0003
11
PS8879G
10/15/09
PI6C410BS
Clock Generator for Intel PCIe® Server Chipset
Absolute Maximum Ratings (Over operating free-air temperature range)
Symbol
Parameters
Min.
Max.
3.3V Core Supply Voltage
-0.5
4.6
VDD
3.3V I/O Supply Voltage
-0.5
4.6
VIH
Input High Voltage
VIL
Input Low Voltage
-0.5
Storage Temperature
-65
VDD_A
Ts
VESD
Units
V
4.6
ESD Protection
150
°C
2000
V
Note:
1. Stress beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
DC Electrical Characteristics (VDD = 3.3±5%, VDD_A = 3.3±5%)
Symbol
Min.
Max.
3.3V Core Supply Voltage
3.135
3.465
VDD
3.3V I/O Supply Voltage
3.135
3.465
VIH
3.3V Input High Voltage
2.0
VDD + 0.3
VIL
3.3V Input Low Voltage
VSS – 0.3
0.8
IIK
Input Leakage Current
-5
+5
VDD_A
Parameters
Condition
VDD
0 < VIN < VDD
Units
μA
VIH_FS
3.3V Input High Voltage
0.7
VDD + 0.3
VIL_FS
3.3V Input Low Voltage
VSS – 0.3
0.35
VOH
3.3V Output High Voltage
IOH = -1mA
VOL
3.3V Output Low Voltage
IOL = 1mA
CPU, SRC: IOH = 6 x Iref,
Iref = 2.32mA
IOH
Output High Current
VOH = 1.0V
USB
VOH = 1.0V
0.4
VOL = 1.95V
15.6
-29
-23
-33
VOL = 1.95V
REF, PCI
29
27
30
VOL = 0.4V
38
Cin
Input Pin Capacitance
3
6
Cxtal
Xtal Pin Capacitance
3
6
Cout
Output Pin Capacitance
6
Lpin
Pin Inductance
7
IDD
Power Supply Current
VDD = 3.465V, FCPU = 400MHz
500
ISS
Power Down Current
Driven outputs
85
ISS
Power Down Current
Tristate outputs
12
Ta
Ambient Temperature
09-0003
0
12
mA
-33
VOL = 0.4V
Output Low Current
V
V
V
V
12.2
VOH = 3.135V
USB
IOL
2.4
VOH = 3.135V
REF, PCI
V
pF
nH
mA
70
°C
PS8879G
10/15/09
PI6C410BS
Clock Generator for Intel PCIe® Server Chipset
AC Switching Characteristics (VDD = 3.3±5%, VDD_A = 3.3±5%)
Symbol
Outputs
Trise / Tfall
CPU, SRC
Trise / Tfall
PCI/PCIF, REF
Trise / Tfall
USB
ΔTrise /
ΔTfall
CPU, SRC
Tskew
Parameters
Min
Max.
Units
Notes
Rise and Fall Time
(measured between 0.175V to 0.525V)
175
700
ps
3, 4
Rise/Fall Edge Rate
(measured between 0.8V to 2.0V)
1.0
4.0
Rise/Fall Edge Rate
(measured between 0.8V to 2.0V)
1.0
6
V/ns
2.0
6
Rise and Fall Time Variation
125
CPU
CPU – CPU Skew
100
3, 5
Tskew
SRC
SRC – SRC Skew
250
3, 5
Tskew
PCI/PCIF, REF
PCI – PCI Skew / REF - REF Skew (measured at 1.5V)
500
6
Tjitter
CPU
Cycle – Cycle Jitter
85
Tjitter
SRC
Cycle – Cycle Jitter
125
3, 5, 7
Tjitter
PCI/PCIF
Cycle – Cycle Jitter (measured at 1.5V)
500
6, 7
Tjitter
USB
Cycle – Cycle Jitter (measured at 1.5V)
350
6, 7
Tjitter
REF
Cycle – Cycle Jitter (measured at 1.5V)
1000
6, 7
VHIGH
CPU, SRC
Voltage High including overshoot
(measured at 3.3V)
660
1150
3, 4
VLOW
CPU, SRC
Voltage Low including undershoot
-300
VCROSS
CPU, SRC
Absolute crossing point voltages
250
ΔVCROSS
CPU, SRC
Total Variation of Vcross over all edges
TDC
CPU, SRC
Duty Cycle
TDC
REF, USB,
PCI/PCIF
Duty Cycle (measured at 1.5V)
Tstable
Tdrive
Pwrdwn
Trise / Tfall
Pwrdwn
ps
3, 4
3, 5, 7
ps
mV
3, 4
550
3, 4
140
3, 4
45
55
3, 5
45
55
%
6
All clock stabilization from power-up
<1.8
ms
Fig 2
Differential output enable after PwrDwn
de-assertion
300
μs
Fig 2
PwrDwn rise and fall time
5.0
ns
Notes:
3. Test configuration is Rs = 33.2Ω, Rp = 49.9Ω, and 2pF.
4. Measurement taken from Single Ended waveform.
5. Measurement taken from Differential waveform.
6. 3.3 VCC, one load for PCI/PCIF and USB with RS= 33Ω5%. Three loads for REF with Rs=12Ω5%, Max 20" into 5pF load with 60Ω impedance.
7. Using M1 to measure.
09-0003
13
PS8879G
10/15/09
PI6C410BS
Clock Generator for Intel PCIe® Server Chipset
Configuration test load board termination
Rs
33Ω
5%
Clock
TLA
PI6C410B
Rs
33Ω
5%
Clock#
TLB
475Ω
1%
Rp
49.9Ω
1%
Rp
49.9Ω
1%
2pF
5%
2pF
5%
Figure 4. Configuration test load board termination
Note:
1. Maximum 10” trace length for CPU outputs at 200 MHz. Maximum 16” trace length for SRC outputs at 100 MHz.
09-0003
14
PS8879G
10/15/09
PI6C410BS
Clock Generator for Intel PCIe® Server Chipset
Packaging Mechanical: 56-Pin, 240-mil wide TSSOP (A)
DATE: 09/11/06
Notes:
1. Controlling dimensions in millimeters.
2. Ref: JEDEC MO-153F/EE
3. Package Outline Exclusive of Mold Flash and Metal Burr
DESCRIPTION: 56-pin, 240-mil wide TSSOP
PACKAGE CODE: A56
DOCUMENT CONTROL #: PD-1502
REVISION: M
06-0736
Note:
• For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php
Ordering Information(1,2,3)
Ordering Code
PI6C410BSAE
Package Code
A
Package Description
Pb-free & Green, 56-pin TSSOP
Notes:
1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
2. E = Pb-free & Green
3. Adding X suffix = Tape/Reel
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
09-0003
All trademarks are property of their respective owners.
15
PS8879G
10/15/09