PI6C410M/410MA Clock Generator for Intel PCI Express Mobile Chipset Features Description • 14.318 MHz Crystal Input PI6C410M is a high-speed, low-noise clock generator designed to work with the Intel Mobile PCI Express Chipset. This Spread Spectrum PLL based clock generator reduces EMI emission and supports a wide range of frequencies. • Selectable of 100, 133, 166, 200, 266, 333, and 400 MHz CPU Output Frequencies • SMBus: Power Management Control • Spread Spectrum support (-0.5% down spread) Jitter Performance • Packaging (Pb-free & Green available): — 56-Pin TSSOP • • • • • • Output Features • Two Pairs of Differential CPU Clocks • One selectable of CPU/SRC Clock < 85ps Cycle-to-Cycle CPU 0/1 clock jitter < 125ps Cycle-to-Cycle CPU 2 clock jitter < 350ps Cycle-to-Cycle 48 MHz clock jitter < 500ps Cycle-to-Cycle PCI clock jitter < 125ps Cycle-to-Cycle SRC clock jitter < 1000ps Cycle-to-Cycle REF clock jitter Skew Performance • Seven Pairs of SRC Clocks • • • • • Six PCI Clocks • One 48 MHz USB clock • One REF clock < 100ps Output-to-output CPU 0/1 clock skew < 150ps Output-to-output CPU 2 clock skew < 500ps Output-to-output PCI clock skew < 250ps Output-to-output SRC clock skew • One 96 MHz Differential clock Pin Configuration Block Diagram XTAL_IN XTAL_OUT SDA SCL XTAL OSC /2 FS_B / TEST_MODE FS_C / TEST_SEL VTT_PWRGD# / PWRDWN PLL 1 C O N T R O L Div PCI [2:5] PCIF[0:1] Div SRC [0:6] SRC [0:6]# CPU2_ITP / SRC7 CPU2_ITP# / SRC7# PCI_STOP# CPU_STOP# USB_48 / FS_A REF SMBus Logic PCIF_0 / ITP_EN USB_48 / FS_A DOT_96 DOT 96# PLL 2 Div CPU[0:1] CPU[0:1]# 1 VDD_PCI VSS_PCI PCI_3 PCI_4 PCI_5 VSS_PCI VDD_PCI PCIF_0 / ITP_EN PCIF_1 VTT_PWRGD# / PWRDWN VDD_48 USB_48/FS_A VSS_48 DOT_96 DOT_96# FS_B / TEST_MODE SRC_0 SRC_0# SRC_1 SRC_1# VDD_SRC SRC_2 SRC_2# SRC_3 SRC_3# SRC_4 SRC_4# VDD_SRC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 PCI_2 PCI_STOP# CPU_STOP# FS_C / TEST_SEL REF VSS_REF XTAL_IN XTAL_OUT VDD_REF SDA SCL VSS_CPU CPU_0 CPU_0# VDD_CPU CPU_1 CPU_1# IREF VSS_A VDD_A CPU2_ITP / SRC7 CPU2_ITP# / SRC7# VDD_SRC SRC_6 SRC_6# SRC_5 SRC_5# VSS_SRC PS8736C 12/19/05 PI6C410M/410MA Clock Generator for Intel PCI Express Mobile Chipset Pin Description Pin Name REF XTAL_IN XTAL_OUT CPU[0:1] & CPU[0:1]# Type Output Input Output Output SRC[0:6] & SRC[0:6]# Output CPU2_ITP / SRC_7 & CPU2_ITP# / SRC_7# Output PCIF_0 / ITP_EN PCIF_1 PCI[2:5] USB_48 / FS_A DOT_96 & DOT_96# Input / Output Output Output Input / Output Output Pin Number 52 50 49 40, 41, 43, 44 17, 18, 19, 20, 22, 23, 24, 25, 26, 27, 30, 31, 32, 33 Differential Serial Reference Clock outputs 35, 36 Selectable Differential CPU or SRC clock output ITP_EN = 0 @ Vtt_Pwrgd# assertion = SRC ITP_EN = 1 @ Vtt_Pwrgd# assertion = CPU 8 33 MHz clock output / CPU2 select when HIGH 9 3, 4, 5, 56 33 MHz clocks outputs (free running) 33 MHz clocks outputs 12 48 MHz clock output / 3.3V LVTTL inputs for CPU frequency selection 14, 15 96 MHz differential clock output 3.3V LVTTL active low input for PCI Stop operation. (150k-ohm internal pull-up resistor) 3.3V LVTTL active low input for CPU Stop operation. (150k-ohm internal pull-up resistor) 3.3V LVTTL inputs for CPU frequency selection / Test Mode select: 0 = Hi-Z, 1 = Ref/N 3.3V LVTTL inputs for CPU frequency selection / Test Mode select if pulled to 3.3V when Vtt_Pwrgd# is asserted LOW External resistor connection for internal current reference 3.3V LVTTL Level sensitive strobe used to determine to latch the FS_A, FS_B/TEST_MODE, FS_C/TEST_SEL and PCIF0/ITP_EN inputs (active low) / 3.3V LVTTL active high input for Power Down operation. SMBus compatible SDATA SMBus compatible SCLOCK 3.3V Power Supply for Outputs 3.3V Power Supply for Outputs 3.3V Power Supply for Outputs 3.3V Power Supply for Outputs 3.3V Power Supply for Outputs Ground for Outputs Ground for Outputs Ground for Outputs Ground for Outputs Ground for Outputs 3.3V Power Supply for PLL Ground for PLL PCI_STOP# Input 55 CPU_STOP# Input 54 FS_B / TEST_MODE Input 16 FS_C / TEST_SEL Input 53 IREF Input 39 VTT_PWRGD# / PWRDWN Input 10 I/O Input Power Power Power Power Power Ground Ground Ground Ground Ground Power Ground 47 46 1, 7 11 21, 28, 34 42 48 2, 6 13 29 45 51 37 38 SDA SCL VDD_PCI VDD_48 VDD_SRC VDD_CPU VDD_REF VSS_PCI VSS_48 VSS_SRC VSS_CPU VSS_REF VDD_A VSS_A Descriptions 3.3V 14.31818 MHz output 14.31818 MHz crystal input 14.31818 MHz crystal output Differential CPU outputs 2 PS8736C 12/19/05 PI6C410M/410MA Clock Generator for Intel PCI Express Mobile Chipset Functionality Frequency Selection(1) FS_C FS_B FS_A CPU SRC PCIF / PCI REF DOT_96 USB_48 1 0 1 100 MHz 100 MHz 33 MHz 14.318 MHz 96 MHz 48 MHz 0 0 1 133 MHz 100 MHz 33 MHz 14.318 MHz 96 MHz 48 MHz 0 1 1 166 MHz 100 MHz 33 MHz 14.318 MHz 96 MHz 48 MHz 0 1 0 200 MHz 100 MHz 33 MHz 14.318 MHz 96 MHz 48 MHz 0 0 0 266 MHz 100 MHz 33 MHz 14.318 MHz 96 MHz 48 MHz 1 0 0 333 MHz 100 MHz 33 MHz 14.318 MHz 96 MHz 48 MHz 1 1 0 400 MHz 100 MHz 33 MHz 14.318 MHz 96 MHz 48 MHz 1 1 1 Reserved 100 MHz 33 MHz 14.318 MHz 96 MHz 48 MHz Note: 1. Refer to DC Electrical Characteristics for FS_A, FS_B and FS_C (Vih_FS, Vil_FS) threshold levels. Test Mode Selection(2) TEST_MODE CPU SRC PCIF / PCI REF DOT_96 USB_48 1 REF/N REF/N REF/N REF REF/N REF/N 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Note: 2. Test mode will occur where the SMBus Bit 6 of Byte 6 = 1, or FS_C/TEST_SEL is set to logic high level. PWRDWN Functionality PWRDWN CPU CPU# SRC SRC# PCIF / PCI REF DOT_96 DOT_96# USB_48 0 Normal Normal Normal Normal 33 MHz 14.318 MHz Normal Normal 48 MHz 1 Iref × 2 or Float Float Iref × 2 or Float Float Low Low Iref × 2 or Float Float Low REF DOT_96 DOT_96# USB_48 Normal Normal 48 MHz Normal Normal 48 MHz DOT_96 DOT_96# USB_48 Normal Normal 48 MHz Normal Normal 48 MHz PCI_STOP# Functionality PCI_STOP# CPU CPU# SRC SRC# PCIF / PCI 1 Normal Normal Normal Normal 33 MHz 0 Normal Normal Iref × 6 or Float Low Low 14.318 MHz 14.318 MHz CPU_STOP# Functionality CPU_STOP# CPU CPU# SRC SRC# PCIF / PCI 1 Normal Normal Normal Normal 33 MHz 0 Iref × 6 or Float Low Normal Normal 33 MHz 3 REF 14.318 MHz 14.318 MHz PS8736C 12/19/05 PI6C410M/410MA Clock Generator for Intel PCI Express Mobile Chipset Serial Data Interface (SMBus) PI6C410M is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7-bit address and read/write bit as shown below. Address Assignment A6 A5 A4 A3 A2 A1 A0 R/W 1 1 0 1 0 0 1 I/0 Data Protocol(1) 1 bit 7 bits 1 1 8 bits 1 8 bits 1 8 bits 1 8 bits 1 1 bit Start bit Slave Addr R/W Ack Register offset Ack Byte Count =N Ack Data Byte 0 Ack Data Byte N -1 Ack Stop bit Note: 1 Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0. Data Byte 0: Control Register Bit Descriptions Type Power Up Condition Output(s) Affected Pin Source Pin 0 SRC_0 Output Enable 1 = Enabled, 0 = Disabled (Hi-Z) RW 1 = Enabled SRC_0 17, 18 NA 1 SRC_1 Output Enable 1 = Enabled, 0 = Disabled (Hi-Z) RW 1 = Enabled SRC_1 19, 20 NA 2 SRC_2 Output Enable 1 = Enabled, 0 = Disabled (Hi-Z) RW 1 = Enabled SRC_2 22, 23 NA 3 SRC_3 Output Enable 1 = Enabled, 0 = Disabled (Hi-Z) RW 1 = Enabled SRC_3 24, 25 NA 4 SRC_4 Output Enable 1 = Enabled, 0 = Disabled (Hi-Z) RW 1 = Enabled SRC_4 26, 27 NA 5 SRC_5 Output Enable 1 = Enabled, 0 = Disabled (Hi-Z) RW 1 = Enabled SRC_5 30, 31 NA 6 SRC_6 Output Enable 1 = Enabled, 0 = Disabled (Hi-Z) RW 1 = Enabled SRC_6 32, 33 NA 7 CPU_2 / SRC_7 Output Enable 1 = Enabled, 0 = Disabled (Hi-Z) RW 1 = Enabled CPU_2 / SRC_7 35, 36 NA 4 PS8736C 12/19/05 PI6C410M/410MA Clock Generator for Intel PCI Express Mobile Chipset Data Byte 1: Control Register Bit Descriptions Type Power Up Condition Output(s) Affected Pin Source Pin NA 0 Spread Spectrum 1 = Enable, 0 = Disable RW 0 = Spread off CPU[0:2], SRC[0:7], PCI[2:5], PCIF[0:1] 3, 4, 5, 8, 9, 17, 18, 19, 20, 22, 23, 24, 25, 26, 27, 30, 31, 32, 33, 35, 36, 40, 41, 43, 44, 56 1 CPU_0 output enable 1 = Enabled, 0 = Disabled (Hi-Z) RW 1 = Enabled CPU_0, CPU_0# 43, 44 NA 2 CPU_1 output enable 1 = Enabled, 0 = Disabled (Hi-Z) RW 1 = Enabled CPU_1, CPU_1# 40, 41 NA 3 Reserved RW 4 REF Output Enable 1 = Enabled, 0 = Disabled RW 1 = Enabled REF 52 NA 5 USB_48 Output Enable 1 = Enabled, 0 = Disabled RW 1 = Enabled USB_48 12 NA 6 DOT_96 Output Enable 1 = Enabled, 0 = Disabled (Hi-Z) RW 1 = Enabled DOT_96 & DOT96# 14, 15 NA 7 PCIF_0 Output Enable 1 = Enabled, 0 = Disabled RW 1 = Enabled PCIF_O 8 NA Type Power Up Condition Output(s) Affected Pin Source Pin 1 = Enabled PCIF_1 9 NA Data Byte 2: Control Register Bit Descriptions 0 PCIF_1 Output Enable 1 = Enabled, 0 = Disabled RW 1 Reserved RW 2 Reserved RW 3 Reserved RW 4 PCI _2 Output Enable 1 = Enabled, 0 = Disabled RW 1 = Enabled PCI_2 56 NA 5 PCI _3 Output Enable 1 = Enabled, 0 = Disabled RW 1 = Enabled PCI_3 3 NA 6 PCI _4 Output Enable 1 = Enabled, 0 = Disabled RW 1 = Enabled PCI_4 4 NA 7 PCI _5 Output Enable 1 = Enabled, 0 = Disabled RW 1 = Enabled PCI_5 5 NA NA 5 PS8736C 12/19/05 PI6C410M/410MA Clock Generator for Intel PCI Express Mobile Chipset Data Byte 3: Control Register Bit Descriptions Type Power Up Condition Output(s) Affected Pin Source Pin 0 SRC_0 Output Control 0 = Free Running, 1 = Stopped with PCI_STOP# RW 0 = Free running, not affected by PCI_STOP# SRC_0 17, 18 NA 1 SRC_1 Output Control 0 = Free Running, 1 = Stopped with PCI_STOP# RW 0 = Free running, not affected by PCI_STOP# SRC_1 19, 20 NA 2 SRC_2 Output Control 0 = Free Running, 1 = Stopped with PCI_STOP# RW 0 = Free running, not affected by PCI_STOP# SRC_2 22, 23 NA 3 SRC_3 Output Control 0 = Free Running, 1 = Stopped with PCI_STOP# RW 0 = Free running, not affected by PCI_STOP# SRC_3 24, 25 NA 4 SRC_4 Output Control 0 = Free Running, 1 = Stopped with PCI_STOP# RW 0 = Free running, not affected by PCI_STOP# SRC_4 26, 27 NA 5 SRC_5 Output Control 0 = Free Running, 1 = Stopped with PCI_STOP# RW 0 = Free running, not affected by PCI_STOP# SRC_5 30, 31 NA 6 SRC_6 Output Control 0 = Free Running, 1 = Stopped with PCI_STOP# RW 0 = Free running, not affected by PCI_STOP# SRC_6 32, 33 NA 7 SRC_7 Output Control 0 = Free Running, 1 = Stopped with PCI_STOP# RW 0 = Free running, not affected by PCI_STOP# SRC_7 35, 36 NA 6 PS8736C 12/19/05 PI6C410M/410MA Clock Generator for Intel PCI Express Mobile Chipset Data Byte 4: Control Register Bit Descriptions Type Power Up Condition Output(s) Affected Pin Source Pin 0 CPU_0 Output Control 0 = Free Running, 1 = Stopped with CPU_STOP# RW 1 = Stopped with CPU_STOP# assertion CPU_0 43, 44 NA 1 CPU_1 Output Control 0 = Free Running, 1 = Stopped with CPU_STOP# RW 1 = Stopped with CPU_STOP# assertion CPU_1 40, 41 NA 2 CPU_2 Output Control 0 = Free Running, 1 = Stopped with CPU_STOP# RW 1 = Stopped with CPU_STOP# assertion CPU_2 35, 36 NA 3 PCIF_0 Output Control 0 = Free Running, 1 = Stopped with PCI_STOP# RW 0 = Free running, not affected by PCI_STOP# PCIF_0 8 NA 4 PCIF_1 Output Control 0 = Free Running, 1 = Stopped with PCI_STOP# RW 0 = Free running, not affected by PCI_STOP# PCIF_1 9 NA 5 Reserved RW 6 DOT_Pwrdwn drive mode 1 = Hi-Z, 0 = Driven in Pwrdwn RW 0 = Driven in power down DOT_96 & DOT_96# 14, 15 NA 7 Reserved RW Data Byte 5: Control Register Bit Descriptions Type Power Up Condition Output(s) Affected Pin Source Pin 0 CPU_0 Pwrdwn drive mode 1 = Hi-Z, 0 = Driven in Pwrdwn RW 0 = Driven in power down CPU_0 & CPU_0# 43, 44 NA 1 CPU_1 Pwrdwn drive mode 1 = Hi-Z, 0 = Driven in Pwrdwn RW 0 = Driven in power down CPU_1 & CPU_1# 40, 41 NA 2 CPU_2 Pwrdwn drive mode 1 = Hi-Z, 0 = Driven in Pwrdwn RW 0 = Driven in power down CPU_2 & CPU_2# 35, 36 NA 3 SRC_Pwrdwn drive mode 1 = Hi-Z, 0 = Driven in Pwrdwn RW 0 = Driven in power down SRC[0:7] & SRC[0:7]# 17, 18, 19, 20, 22, 23, 24, 25, 26, 27, 30, 31, 32, 35, 36 NA 4 CPU_0 Stop drive mode 1 = Hi-Z, 0 = Driven in CPU Stop RW 0 = Driven in CPU_STOP CPU_0 & CPU_0# 43, 44 NA 5 CPU_1 Stop drive mode 1 = Hi-Z, 0 = Driven in CPU Stop RW 0 = Driven in CPU_STOP CPU_1 & CPU_1# 40, 41 NA 6 CPU_2 Stop drive mode 1 = Hi-Z, 0 = Driven in CPU Stop RW 0 = Driven in CPU_STOP CPU_2 & CPU_2# 35, 36 NA SRC[0:7] & SRC[0:7]# 17, 18, 19, 20, 22, 23 24, 25, 26, 27, 30, 31 32, 33, 35, 36 NA 7 SRC_Stop drive mode 1 = Hi-Z, 0 = Driven in PCI Stop RW 0 = Driven in PCI_STOP 7 PS8736C 12/19/05 PI6C410M/410MA Clock Generator for Intel PCI Express Mobile Chipset Data Byte 6: Control Register Type Power Up Condition Output(s) Affected Pin Source Pin 0 FS_A Reflects the value of the FS_A pin sampled on power up 0 = FS_A was low during Vtt_Pwrgd# assertion R Externally Selected CPU[0:2] 35, 36, 40, 41, 43, 44 NA 1 FS_B Reflects the value of the FS_B pin sampled on power up 0 = FS_B was low during Vtt_Pwrgd# assertion R Externally Selected CPU[0:2] 35, 36, 40, 41, 43, 44 NA 2 FS_C Reflects the value of the FS_C pin sampled on power up 0 = FS_C was low during Vtt_Pwrgd# assertion R Externally Selected CPU[0:2] 35, 36, 40, 41, 43, 44 NA 3 PCI_Stop control 1 = Disabled, 0 = Enabled, Stopped SRC and PCI clocks RW 1 = Disabled All PCI & SRC clocks except PCIF and SRC clocks set to free-running 3, 4, 5, 17, 18, 19, 20, 22, 23, 24, 25, 26, 27, 30, 31, 32, 33, 35, 36, 56 NA 4 REF Output Drive Strength 0 = 1x, 1 = 2x RW 1 = 2X REF 52 NA 5 Reserved RW 6 Test Clock Mode Entry Control 0 = Disabled, 1 = REF/N or Hi-Z RW CPU[0:2], SRC[0:7], PCI[2:5], PCIF[0:1], REF, USB_48, DOT_96 3, 4, 5, 8, 9, 12, 14, 15, 17, 18, 19, 20, 22, 23, 24, 25, 26, 27, 30, 31, 32, 33, 35, 36, 40, 41, 43, 44, 52, 56 NA Bit 7 Descriptions Test Clock Mode 0 = Hi-Z, 1 = REF/N RW 0 = Disabled 0 = Hi-Z DataByte 7: Control Register Bit Descriptions Type Power Up Condition Output(s) Affected Pin R 0 NA NA R 0 NA NA R 0 NA NA 3 R 0 NA NA 4 R 1 NA NA R 0 NA NA R 1 NA NA R 0 NA NA 0 1 2 5 6 7 Vendor ID Revision Code 8 PS8736C 12/19/05 PI6C410M/410MA Clock Generator for Intel PCI Express Mobile Chipset Vtt_Pwrgd# Timing Diagram Vcc to VRM 5/12V Vtt FS_A, FS_B, FS_C Vtt_Pwrgd from VRM Vtt_Pwrgd# Vcc Core PwrGood Vcc Clock Gen Clock State Clock Outputs Clock VCO 0.2-0.3ms Delay State 0 Wait for Vtt_Pwrgd# State 1 State 2 State 3 On Off On Off Figure 1. CPU power BEFORE clock power Vcc to VRM 5/12V Vtt FS_A, FS_B, FS_C Vtt_Pwrgd from VRM Vtt_Pwrgd# Vcc Core PwrGood Vcc Clock Gen Clock State Clock Outputs Clock VCO 0.2-0.3ms Delay State 0 Wait for Vtt_P wrgd# State 1 State 2 State 3 On Off On Off Figure 2. CPU power AFTER clock power 9 PS8736C 12/19/05 PI6C410M/410MA Clock Generator for Intel PCI Express Mobile Chipset Clock Power-Up State Machine Vdda = 2.0V S0 Power Off S1 Delay >0.25ms Vtt_Pwrgd# = Low S3 Normal Operation Vdda = Off S2 Sample Input Straps Enable Outputs Vtt_Pwrgd# = toggle Figure 3. Power-Up State Diagram Power Down (PWRDWN assertion) PWRDWN CPU, 133MHz CPU#, 133MHz SRC, 100MHz SRC#, 100MHz USB, 48MHz DOT, 96MHz DOT#, 96MHz PCI, 33MHz REF Figure 4. Power down sequence 10 PS8736C 12/19/05 PI6C410M/410MA Clock Generator for Intel PCI Express Mobile Chipset Power Down (PWRDWN De-assertion) Tstable <1.8ms PWRDWN CPU, 133MHz CPU#, 133MHz SRC, 100MHz SRC#, 100MHz USB, 48MHz DOT, 96MHz DOT#, 96MHz PCI, 33MHz REF Tdrive_PwrDwn <300us, >200mV Figure 5. Power down de-assetion CPU STOP (CPU_STOP# assertation) CPU_Stop# CPU CPU# Figure 6. Assertion of CPU_Stop# Waveforms 11 PS8736C 12/19/05 PI6C410M/410MA Clock Generator for Intel PCI Express Mobile Chipset CPU STOP (CPU_STOP# De-assertion) CPU_Stop# CPU CPU# CPU Internal CPU# Internal Tdrive_CPU_Stop#, 10ns >200mV Figure 7. CPU_STOP# De-assertion Waveform PCI STOP (PCI_STOP# assertion) T SU (10ns min.) PCI_Stop# PCIF[0:1], 33MHz PCI[2:5], 33MHz SRC, 100MHz SRC#, 100MHz Figure 8. Assertion of PCI_STOP# Waveform PCI STOP (PCI_STOP# De-assertion) T SU (10ns mins.) Tdrive_SRC < 15ns PCI_Stop# PCIF[0:1], 33MHz PCI[2:5], 33MHz SRC#, 100MHz SRC, 100MHz Figure 8. De-assertion of PCI_STOP# Waveform 12 PS8736C 12/19/05 PI6C410M/410MA Clock Generator for Intel PCI Express Mobile Chipset Tristate Specifications CPU Tristate clock truth table Signal CPU[0:2] Pwrdwn CPU_STOP# Pwrdwn Tristate Bit Non-stop Stoppable pin CPU_Stop Tristate Bit pin Outputs Outputs 0 1 X X Running Running 0 0 0 X Running Driven @ Iref x 6 0 0 1 X Running Tristate 1 X X 0 Driven @ Iref x 2 Driven @ Iref x 2 1 X X 1 Tristate Tristate SRC Tristate clock truth table Signal SRC[0:7] Pwrdwn PCI_STOP# Pwrdwn Tristate Bit Stoppable pin PCI_Stop Tristate Bit Non-stop pin Outputs Outputs 0 1 X X Running Running 0 0 0 X Running Driven @ Iref x 6 0 0 1 X Running Tristate 1 X X 0 Driven @ Iref x 2 Driven @ Iref x 2 1 X X 1 Tristate Tristate DOT Tristate clock truth table Signal DOT96 Pwrdwn Pwrdwn Tristate Bit pin Stoppable Outputs 0 X Running 1 0 Driven @ Iref x 2 1 1 Tristate CPU Clock Tristate Timing 1.8ms CPU_Stop# PWRDWN CPU (Free Running) CPU# (Free Running) CPU (Stoppable) CPU# (Stoppable) DOT DOT# Figure 10. CPU_STOP = Driven, CPU_PWRDWN = Driven, DOT_PWRDWN = Driven 13 PS8736C 12/19/05 PI6C410M/410MA Clock Generator for Intel PCI Express Mobile Chipset 1.8ms CPU_Stop# PWRDWN CPU (Free Running) CPU# (Free Running) CPU (Stoppable) CPU# (Stoppable) Figure 11. CPU_Stop = Tristate, CPU_PWRDWN = Driven 1.8ms CPU_Stop# PWRDWN CPU (Free Running) CPU# (Free Running) CPU (Stoppable) PU# (Stoppable) Figure 12. CPU_Stop = Driven, CPU_PWRDWN = Tristate 1.8ms CPU_Stop# PWRDWN CPU (Free Running) CPU# (Free Running) CPU (Stoppable) CPU# (Stoppable) DOT DOT# Figure 13. CPU_STOP = Tristate, CPU_PWRDWN = Tristate, DOT_PWRDWN = Tristate 14 PS8736C 12/19/05 PI6C410M/410MA Clock Generator for Intel PCI Express Mobile Chipset 1.8ms PCI_Stop# PCI (Free Running) PWRDWN CPU (Free Running) CPU# (Free Running) SRC (Stoppable) SRC# (Stoppable) 1 PCI clock max Figure 14. SRC_Stop = Driven, SRC_PWRDWN = Driven 1.8ms PCI_Stop# PCI (Free Running) PWRDWN CPU (Free Running) CPU# (Free Running SRC (Stoppable) SRC# (Stoppable) 1 PCI clock max Figure 15. SRC_Stop = Tristate, SRC_PWRDWN = Tristate 1.8ms PCI_Stop# PCI (Free Running) PWRDWN CPU (Free Running) CPU# (Free Running) SRC (Stoppable) SRC# (Stoppable) Figure 16. SRC_STOP = Tristate, SRC_PWRDWN = Tristate, PCI_STOP# = Asserted 15 PS8736C 12/19/05 PI6C410M/410MA Clock Generator for Intel PCI Express Mobile Chipset Spread Spectrum Specifications PI6C410M supports Spread Spectrum clocking and can be enabled and disabled via SMBus control. The maximum Spread Spectrum Modulation is –0.5% down spread with frequency from 30KHz to 33KHz. Tperiod SSC ON Min Max CPU @ 399.000 MHz 2.4993 2.5133 CPU @ 332.500 MHz 2.9991 CPU @ 266.000 MHz Tperiod SSC OFF Unit Min Max CPU @ 400.000 MHz 2.4993 2.5008 3.016 CPU @ 333.333 MHz 2.9991 3.0009 3.7489 3.77 CPU @ 266.666 MHz 3.7489 3.7511 CPU @ 199.500 MHz 4.9985 5.0266 CPU @ 200.000 MHz 4.9985 5.0015 CPU @ 166.250 MHz 5.9982 6.032 CPU @ 166.666 MHz 5.9982 6.0018 CPU @ 133.000 MHz 7.4978 7.54 CPU @ 133.333 MHz 7.4978 7.5023 CPU @ 99.750 MHz 9.997 10.0533 CPU @ 100.000 MHz 9.997 10.003 SRC @ 99.750 MHz 9.997 10.0533 SRC @ 100.000 MHz 9.997 10.003 PCIF / PCI @ 33.250 MHz 29.991 30.1598 PCIF / PCI @ 33.333 MHz 29.991 30.009 ns Current-mode output buffer characteristics of CPU, SRC, and DOT Vdd (3.3V ± 5%) Slope ~1/Ro Ro lout Ros lout Vout = 0.85V Max. 0.85V 0V Figure 17. Simplified diagram of a current-mode output buffer Host Clock Buffer Characteristics Min Max RO 3000 Ω N/A ROS unspecified unspecified VOUT N/A 850mV 16 PS8736C 12/19/05 PI6C410M/410MA Clock Generator for Intel PCI Express Mobile Chipset Cueernt Accuracy Conditions IOUT VDD = 3.30 ±5% Configuration Load Rref = 475Ω Nominal test load for given configuration Iref = 2.32mA Min. Max. -12% x INOMINAL +12% x INOMINAL Host Clock Output Current Board Target Trace/Term Z Reference R, Iref = VDD/(3xRr) 100Ω (100Ω differential ≈ 8% coupling ratio) Output Current Voh @ Z Ioh = 6 x Iref 0.7V @ 50 Rref = 475 Ω Iref = 2.32mA Crystal Recommendations(1) Frequency Cut Loading Load Cap Drive Max. Shunt Cap Max. Motional Cap Max. Tolerance Max. Stability Max. Aging Max. 14.31818 MHz AT Parallel 20pF 0.1mW 5pF 0.016pF 35ppm 30ppm 5ppm Note: 1. External trim capacitors (Ce) are required. Ce = 2*CL – (Cs + Ci). Typical Ce = 33pF when Crystal-load = 20pF, Ctrace (Cs) = 2.8pF and CXTAL = 4.5pF. Absolute Maximum Ratings(1) (Over operating free-air temperature range) Symbol Parameters Min. Max. VDD_A 3.3V Core Supply Voltage -0.5 4.6 VDD 3.3V I/O Supply Voltage -0.5 4.6 VIH Input High Voltage VIL Input Low Voltage -0.5 Ts Storage Temperature -65 VESD ESD Protection 2000 Units V 4.6 150 °C V Note: 1. Stress beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. 17 PS8736C 12/19/05 PI6C410M/410MA Clock Generator for Intel PCI Express Mobile Chipset DC Electrical Characteristics (VDD = 3.3±5%, VDD_A = 3.3±5%) Symbol Parameters VDD_A Condition Min. Max. 3.3V Core Supply Voltage 3.135 3.465 VDD 3.3V I/O Supply Voltage 3.135 3.465 VIH 3.3V Input High Voltage 2.0 VDD + 0.3 VIL 3.3V Input Low Voltage VSS – 0.3 0.8 IIK Input Leakage Current -5 +5 VIH_FS 3.3V Input High Voltage 0.7 VDD + 0.3 VIL_FS 3.3V Input Low Voltage VSS – 0.3 0.35 VOH 3.3V Output High Voltage IOH = -1mA VOL 3.3V Output Low Voltage IOL = 1mA VDD 0 < VIN < VDD CPU, SRC, DOT: IOH = 6 x Iref, Iref = 2.32mA IOH Output High Current VOH = 1.0V USB VOH = 1.0V VOL = 1.95V VOL = 1.95V REF, PCI -29 -23 -33 -33 mA 29 27 30 VOL = 0.4V 38 Cin Input Pin Capacitance 3 5 Cxtal Xtal Pin Capacitance 3 6 Cout Output Pin Capacitance 6 Lpin Pin Inductance 7 IDD Power Supply Current VDD = 3.465V, FCPU = 400 MHz 500 ISS Power Down Current Driven outputs 100 ISS Power Down Current Tristate outputs 12 Ta Ambient Temperature 0 18 V 15.6 VOL = 0.4V Output Low Current μA 12.2 VOH = 3.135V USB V 0.4 VOH = 3.135V REF, PCI IOL 2.4 Units 70 PS8736C pF nH mA °C 12/19/05 PI6C410M/410MA Clock Generator for Intel PCI Express Mobile Chipset AC Electrical Characteristics (VDD = 3.3±5%, VDD_A = 3.3±5%) Symbol Outputs Parameters Min. Max. Units Notes Trise / Tfall CPU, SRC, DOT Rise and fall Time (measured between 0.175V to 0.525V) 175 700 ps 1,2 Trise / Tfall PCI/PCIF, REF Rise and fall Time (measured between 0.8V to 2.0V) 0.5 2.0 Trise / Tfall USB Rise and fall Time (measured between 0.8V to 2.0V) 1.0 2.0 ΔTrise / ΔTfall CPU, SRC, DOT Rise and fall Time Variation 125 Tskew CPU0, CPU1 CPU – CPU Skew 100 Tskew CPU2 CPU – CPU Skew 200 Tskew SRC SRC – SRC Skew 250 Tskew PCI/PCIF, REF PCI – PCI Skew / REF - REF Skew (measured at 1.5V) 500 Tjitter CPU0, CPU1 Cycle – Cycle Jitter 85 Tjitter CPU2 Cycle – Cycle Jitter 125 Tjitter SRC Cycle – Cycle Jitter 125 Tjitter DOT Cycle – Cycle Jitter 250 Tjitter PCI/PCIF Cycle – Cycle Jitter (measured at 1.5V) 500 4 Tjitter USB Cycle – Cycle Jitter (measured at 1.5V) 350 5 Tjitter REF Cycle – Cycle Jitter (measured at 1.5V) 1000 4 VHIGH CPU, SRC, DOT Voltage HIGH including overshoot 660 VLOW CPU, SRC, DOT Voltage LOW including undershoot -300 Vcross CPU, SRC, DOT Absolute crossing poing voltages 250 ∆Vcross CPU, SRC, DOT Total variation of Vcross over all edges TDC CPU, SRC, DOT Duty-Cycle TDC REF, USB, PCI/PCIF Duty-Cycle (measured at 1.5V) 4 ns 5 ps 1,3,6 4 ps 550 mV 1, 2 140 45 55 % 1,3,6 45 55 % 4, 5 All clock stabilization from power-up <1.8 ms Tdrive Differential output enable after PwrDwn de-assertion 300 µs Power down rise and fall time 5.0 ns Trise / Tfall Pwrdwn 1, 3 1150 Tstable Pwrdwn 1, 2 Fig 2 Notes: 1. Test configuration is Rs = 33.2Ω, Rp = 49.9Ω, and CL = 2pF. 2. Single-Ended measurement. 3. Differential measurement. 4. PCI, PCIF, and REF CL(min) = 10pF, CL(max) = 30pF. 5. USB CL(min) = 10pF, CL(max) = 20pF. 6. CPU measured at 133 MHz. 19 PS8736C 12/19/05 PI6C410M/410MA Clock Generator for Intel PCI Express Mobile Chipset Configuration Test Load Board Termination Clock Rs = 33Ω TLA PI6C410M Clock# Rs = 33Ω Rp = 50Ω TLB Rp = 50Ω 2pF 2pF 33Ω Figure 18. Configuration test load board termination Note: 1. Maximum 10" trace length for CPU @ 200 MHz, 16" trace for SRC @ 100 MHz. 20 PS8736C 12/19/05 PI6C410M/410MA Clock Generator for Intel PCI Express Mobile Chipset Packaging Mechcanical: 56-Pin, 240mil wide, 0.5mm pitch TSSOP (A) �� ���� ���� � ���� ���� ��� ��� ���� ���� ���� ���� ���� ������������� ���� ���� ������ ���� ����� ���� ���� ���� ���� ���� ���� ���� ������������������� ���� �������������� ���� ���� ���� ���� ���� ���� ���� ���� ���� ��� ���� Ordering Information(1,2,3) Ordering Code Package Code Package Description PI6C410MA A 56-Pin, 240mil wide, 0.5mm pitch TSSOP PI6C410MAE A Pb-free & Green 56-Pin, 240mil wide, 0.5mm pitch TSSOP PI6C410MAAE A Pb-free & Green 56-Pin, 240mil wide, 0.5mm pitch TSSOP PI6C410MAAEX A Pb-free & Green 56-Pin, 240mil wide, 0.5mm pitch TSSOP , Tape and Reel Notes: 1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ 2. E = Pb-free and Green 3. X Suffix = Tape/Reel Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com 21 PS8736C 12/19/05