PT16820 OLED Driver IC DESCRIPTION The PT16820 is a single-chip CMOS OLED driver/controller for organic light emitting diode dot passive matrix display systems. It consists of 256 segments and 136 commons. The PT16820 communicates with the host microcontroller via an 8080/6800-series compatible parallel interface or a serial interface. The PT16820 has a set of control registers that can be addressed by the interface. - FEATURES Segment source current: 600µA (max.) Common sink current: 160mA 16/4/2 gray scale levels Gray Scale lookup table Embedded 256x136x4x2 bits SRAM 64-step output current adjustment Current reference controlled by external resistor Programmable frame rate Selectable MCU interface 8-bit 8080/6800-series parallel interface Serial interface On-chip oscillator Supports up to 256x136 dot matrix panel Power supply: - Low voltage power ( VDD ): 3.0 ~ 5.5V Core Logic power (VCC) 1.8V Segment power (VHA): 8.0V ~ 26V Common power (VHC): 18V (Max.) BLOCK DIAGRAM COM68 ~ COM135 SEG255 ~ SEG0 Cathode Driver CUR_IO IREF SEG/COM Driving Block Anode Driver Oscillator Cathode Driver Display Timing Controller Display SRAM 256x136x4x2 Bits CKSEL CLK_EXT ROSC COM0 ~ COM67 SYNC CLK2 M/S Control Registers Command Decoder VRO LDO_EN BG_DIS Regulator VHC VDD VCC GND VHA PGNDA R/W#-(WR#) D[7:0] SEL[1:0] CS# RS E-(RD#) TSTMOD INT RES# MCU Interface Tel: 886-66296288‧Fax: 886-29174598‧ http://www.princeton.com.tw‧2F, No. 233-1, Baociao Rd., Sindian Dist., New Taipei City 23145, Taiwan PT16820 CONTENTS 1. 2. 3. 4. 5. 6. APPLICATION CIRCUIT .........................................................................................................................................3 ORDER INFORMATION .........................................................................................................................................4 PIN CONFIGURATION ...........................................................................................................................................4 PIN DESCRIPTION.................................................................................................................................................5 INPUT/OUTPUT PINS EQUIVALENT CIRCUIT ....................................................................................................7 FUNCTION DESCRIPTION ....................................................................................................................................9 6.1 MCU INTERFACE .............................................................................................................................................9 6.2 ON-CHIP OSCILLATOR....................................................................................................................................9 6.3 GRAPHIC SRAM ...............................................................................................................................................9 6.4 SEGMENT AND COMMON DRIVER ................................................................................................................9 6.5 DUMMY SCAN ................................................................................................................................................10 6.6 MASTER/SLAVE CONFIGURATION ..............................................................................................................11 6.7 COMMAND TABLE .........................................................................................................................................11 6.8 COMMAND DESCRIPTION ............................................................................................................................13 7. ABSOLUTE MAXIMUM RATING ..........................................................................................................................33 8. DC CHARACTERISTICS ......................................................................................................................................34 9. AC CHARACTERISTICS ......................................................................................................................................36 9.1 PARALLEL 8080 INTERFACE (WRITE MODE) .............................................................................................36 9.2 WRITE TIMING TABLE (8080) .......................................................................................................................36 9.3 PARALLEL 8080 INTERFACE (READ MODE) ..............................................................................................37 9.4 READ TIMING TABLE (8080) .........................................................................................................................37 9.5 PARALLEL 6800 INTERFACE (WRITE MODE) .............................................................................................38 9.6 WRITE TIMING TABLE (6800) .......................................................................................................................38 9.7 PARALLEL 6800 INTERFACE (READ MODE) ..............................................................................................39 9.8 READ TIMING TABLE (6800) .........................................................................................................................39 9.9 SERIAL INTERFACE (WRITE ONLY) ............................................................................................................40 9.10 SERIAL TIMING TABLE ................................................................................................................................40 9.11 TIMING OF SEGMENTS AND COMMONS ..................................................................................................41 9.12 VDD AND VHA AND VHC POWER SEQUENCE TIMING ...........................................................................42 9.13 RESET TIMING .............................................................................................................................................43 10. PAD CONFIGURATION .......................................................................................................................................44 11. PAD LOCATION ...................................................................................................................................................45 IMPORTANT NOTICE .................................................................................................................................................. 62 V1.3 2 September 2014 RD# INT VDD WR# IREF CLK_EXT CKSEL ROSC D[5:0] RD# (parallel) / GND (serial) VDD VHC VDD VHA MS VHC VDD VHA GND PGNDA VCC VRO LDO_EN SEL[1:0] CS# RS D7 D6 WR# (parallel) / GND (serial) D7 (parallel) / SDIN (serial) RS CS1 D[5:0] (parallel) / GND (serial) D6 (parallel) / SCK (serial) CUR_IO PT16820 CLK2 SYNC RD# INT WR# D[5:0] D7 D6 PGNDA VCC VRO LDO_EN SEL[1:0] CS# RS VHC VDD VHA GND CUR_IO MS COM[67:101] IREF CLK_EXT CKSEL ROSC CLK2 VHC VDD VHA RS CS2 VDD VDD 1uF ~ 10uF 1uF ~ 10uF September 2014 3 V1.3 COM[67:34] COM[102:135] COM[0:33] SEG0 SEG255 COM[101:68] COM[67:0] PANEL COM[135:68] SEG255 SEG0 COM[33:0] 1uF ~ 10uF 1uF ~ 10uF COM[135:102] COM[34:67] SYNC PT16820 1. APPLICATION CIRCUIT PT16820 PT16820 2. ORDER INFORMATION Valid Part Number PT16820 Package Type Bare Chip Top Code PT16820-G 3. PIN CONFIGURATION 611 612 (44.99, 15403.975) 1 (45, 146.025) 342 330 V1.3 4 September 2014 PT16820 4. PIN DESCRIPTION Pin Name COM33~0 COM68~101 COM102~135 COM67~34 Dummy99, 2 Dummy1, 3 Dummy4~19 Dummy20~23 Dummy24~75 Dummy78~81 Dummy82~98 SEG0~255 I/O Description Pin No. 1~34 295~328 346~379 562~595 35, 36 293, 294, 329~345 380~383 396~447 558~561 596~612 37~292 384~387 554~557 388~391 550~553 392~395 546~549 448, 449 450~453 537~544 O Common (cathode) outputs. P Dummy pad O Segment (anode) outputs. VHA P Power pin to drive segment. PGNDA P Ground pin. VHC P Power pin to drive common Bumpcheck1, 2 A For bumping check VDD P 5V/3.3V power input. CKSEL I ROSC A GND P Ground pin. MS I Master/Slave selection. When MS = H, the chip is master. Clock signal for master and slave chips. When MS = H, the chip is a master chip and this pin outputs clock signal. When MS = L, the chip is a slave chip and this pin is a clock input by which the slave chip synchronizes with the master chip. Synchronization signal for master and slave chips. When MS = H, the chip is a master chip and this pin outputs frame synchronization signal. When MS = L, the chip is a slave chip, and this pin is an input by which the slave chip synchronizes with the master chip. External clock input. When internal oscillator is disabled (LOW in CKSEL pin), the pin is the input pin for external clock source. When internal oscillator is enabled (HIGH in CKSEL pin), this pin is not used and should be connected to ground. No connection pin. It should be left open or connected to ground. No connection pin. It should be left open or connected to ground Frame synchronization signal to be used by MCU. CLK2 IO SYNC IO CLK_EXT TEST_EN TSCAN_EN INT I I(PL) I(PL) O Internal clock selection pin. When this pin is pulled HIGH, internal oscillator is enabled. When this pin is pulled LOW, internal oscillator is disabled A resister connected between this pin and ground determines the oscillation frequency. Please isolate ROSC from switching noise, e.g. CLK2. If ROSC is interfered, the jitter of system clock increases. SEL0, 1 I Interface mode selection CS# I RS I Chip select pin. Interface data/command selection pin. When the pin is LOW, D[7:0] is a command. When the pin is HIGH, D[7:0] is RAM data or register data. 5 V1.3 454, 455 456, 457 458~461 526~529 462, 463 464, 465 466, 467 468, 469 470, 471 472, 473 474, 475 476, 477 478, 479 480, 481 482, 483 September 2014 PT16820 Pin Name WR# (W/R#) RD# (E) Description 6800 Parallel Interface: READ/WRITE or 8080 Parallel Interface: WRITE. 6800 Parallel Interface: data enable or 8080 Parallel Interface: READ. Bi-directional data bus. D0~7 IO In serial mode , D7 is serial data input (SDA) and D6 is serial clock input (SCLK), and D5 ~ D0 must be connected to GND. RES# I Low-active hardware reset pin. Test mode selection. TSTMOD I(PL) When this pin is HIGH, the chip accepts test mode command. When this pin is LOW, the chip doesn’t accept test mode command. Power pin for core logic circuit. VCC P If regulator is enabled, this pin is connected to VRO pin. If regulator is disabled, this pin is connected to external 1.8V power supply. Regulator voltage output pin for core logic. VRO P When LDO_EN is pulled HIGH, VRO output 1.8V. A 10uF capacitor load is recommended. Regulator enable pin. LDO_EN I When it is pulled HIGH, regulator is enabled. Segment current reference pin. A resistor should be connected between this IREF A pin and ground to generate the reference current for segment driver. BG_DIS I(PL) When this pin is pulled HIGH, the bandgap circuit is disabled. Tj A This pin can be used to monitor temperature of chip. Used for current matching between master and slave chips. CUR_IO A The resistance load of this pin must be less than 200Ω I = Input, O =Output, IO = Bi-directional (input/output), P = Power pin, A = Analog pin PL= Pulled-low V1.3 I/O I I 6 Pin No. 484, 485 486, 487 488~503 504, 505 506, 507 508~513 514~523 524, 525 530, 531 532, 533 534~536 545 September 2014 PT16820 IMPORTANT NOTICE Princeton Technology Corporation (PTC) reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and to discontinue any product without notice at any time. PTC cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a PTC product. No circuit patent licenses are implied. Princeton Technology Corp. 2F, 233-1, Baociao Road, Sindian Dist., New Taipei City 23145, Taiwan Tel: 886-2-66296288 Fax: 886-2-29174598 http://www.princeton.com.tw V1.3 62 September 2014