RENESAS R1QKA7236AB

R1QHA72 / R1QLA72 Series
R1QHA7236ABB / R1QHA7218ABB
R1QLA7236ABB / R1QLA7218ABB
72-Mbit DDRII+ SRAM
2-word Burst
R10DS0173EJ0011
Rev. 0.11
2013.01.15
Description
The R1Q#A7236 is a 2,097,152-word by 36-bit and the R1Q#A7218 is a 4,194,304-word by 18-bit synchronous
double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor
memory cell. It integrates unique synchronous peripheral circuitry and a burst counter. All input registers are
controlled by an input clock pair (K and /K) and are latched on the positive edge of K and /K. These products
are suitable for applications which require synchronous operation, high speed, low voltage, high density and
wide bit configuration. These products are packaged in 165-pin plastic FBGA package.
# = B: Latency =2.5, w/o ODT
# = E: Latency =2.5, w/ ODT
# = H: Latency =2.0, w/o ODT
# = L: Latency =2.0, w/ ODT
Features
႑ Power Supply
• 1.8 V for core (VDD), 1.4 V to VDD for I/O (VDDQ)
႑ Clock
• Fast clock cycle time for high bandwidth
• Two input clocks (K and /K) for precise DDR timing at clock rising edges only
• Two output echo clocks (CQ and /CQ) simplify data capture in high-speed systems
• Clock-stop capability with μs restart
႑ I/O
• Common data input/output bus
• Pipelined double data rate operation
• HSTL I/O
• User programmable output impedance
• DLL/PLL circuitry for wide output data valid window and future frequency scaling
• Data valid pin (QVLD) to indicate valid data on the output
႑ Function
• Two-tick burst for low DDR transaction size
• Internally self-timed write control
• Simple control logic for easy depth expansion
• JTAG 1149.1 compatible test access port
႑ Package
• 165 FBGA package (13 x 15 x 1.4 mm)
Notes: 1. QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress
Semiconductor, IDT, Samsung, and Renesas Electronics Corp. (QDR Co-Development Team)
2. The specifications of this device are subject to change without notice. Please contact your nearest
Renesas Electronics Sales Office regarding specifications.
3. Refer to
"http://www.renesas.com/products/memory/fast_sram/qdr_sram/index.jsp"
for the latest and detailed information.
4. Descriptions about x9 parts in this datasheet are just for reference.
Rev. 0.11 : 2013.01.15
R10DS0173EJ0011
Common
R1QHA72 / R1QLA72 Series
Part Number Definition
Part Number Definition Table
Column No.
Example
0
1
2
3
4
5
6
7
8
9 10 11 - 12 13 14 15 16
R 1 Q H A 7
2
1
8 A B B
-
2
5 R B 0
The above part number is just example for 72M DDRII+ B2 x18 400MHz, 13x15mm PKG, Pb-free part.
No.
0-1
2-3
R1
Q2
Q3
Q4
Q5
Q6
QA
QB
QC
QD
QE
QF
QG
QH
QJ
QK
QL
QM
QN
QP
-
Comments
Renesas Memory Prefix
[*1]
[*2]
(L15)
QDR II B2
QDR II B4
(L15)
DDR II B2
(L15)
DDR II B4
(L15)
No.
4
5-6
[*3]
DDR II B2 SIO
(L15)
[*2]
QDR II+ B4 L25
DDR II+ B2 L25
DDR II+ B4 L25
7-8
[*4]
QDR II+ B4 L25 w/ODT
DDR II+ B2 L25 w/ODT
DDR II+ B4 L25 w/ODT
QDR II+ B4 L20
DDR II+ B2 L20
DDR II+ B4 L20
QDR II+ B4 L20 w/ODT
DDR II+ B2 L20 w/ODT
DDR II+ B4 L20 w/ODT
QDR II+ B2 L20
QDR II+ B2 L20 w/ODT
9
10-11
A
36
72
44
88
09
18
36
R
A
B
C
D
E
F
BG
BB
Comments
Vdd = 1.8 V
Density = 36Mb
Density = 72Mb
Density = 144Mb
Density = 288Mb
Data width = 9bit
Data width = 18bit
Data width = 36bit
1st Generation
2nd Generation
3rd Generation
4th Generation
5th Generation
6th Generation
7th Generation
PKG= BGA 15x17 mm
PKG= BGA 13x15 mm
12-13
-
-
R
I
16
Note1:
[*1]
[*2]
[*3]
[*4]
Note2:
Package Marking Name
Pb-parts: Marking Name = Part Number(0-14)
Pb-free parts: Marking Name = Part Number(0-14) + "PB-F"
(Example) R1QAA4436RBG-20R Pb-F ----- Pb-parts
(Example) R1QAA4436RBG-20R PB-F ----- Pb-free parts
Note3:
Pb-free: RoHS Compliance Level = 5/6
Pb-free: RoHS Compliance Level = 6/6
Note4:
R1Q*A series support both "Commercial" and "Industrial" temperatures
by "Industrial" temperature parts.
60
50
40
36
33
30
27
25
22
20
19
18
14
15
-
Comments
Frequency = 167MHz
Frequency = 200MHz
Frequency = 250MHz
Frequency = 275MHz
Frequency = 300MHz
Frequency = 333MHz
Frequency = 375MHz
Frequency = 400MHz
Frequency = 450MHz
Frequency = 500MHz
Frequency = 533MHz
Frequency = 550MHz
Commercial temp.
Ta range = 0é to 70é
Industrial temp.
Ta range = -40é to 85é
Pb-and Tray
Pb-free and Tray
Pb-and Tape&Reel
Pb-free and Tape&Reel
A
B
T
S
0 to 9,
A to Z Renesas internal use
or None
B=Burst length (B2: Burst length=2, B4: Burst length=4)
L=Read Latency (L15: Read Latency = 1.5 cycle, L20: 2.0 cycle, L25: 2.5 cycle)
SIO=Separate I/O
ODT=On die termination
Rev. 0.11 : 2013.01.15
R10DS0173EJ0011
No.
PAGE:2
hinS=11111.1111.1111.1111.1111--00000.0000.0000.0000.0000--00000.0000.0000.0000.0000---072M
R1QHA72 / R1QLA72 Series
72M QDR/DDR SRAM (R1Q*A72 Series) Lineup
- Renesas supports or plans to support the parts listed below.
B2
QDRII
No
B2
1.5
B4
DDRII
B4
DDRII
SIO
B2
No
B2
2.5
QDRII+ B4
DDRII+
B4
Yes
B2
2.5
QDRII+ B4
DDRII+
B4
No
B2
2.0
QDRII+ B4
DDRII+
B4
B2
DDRII+
B4
Yes
QDRII+ B4
2.0
1
2
3
5
6
8
9
11
12
14
15
17
18
20
21
23
24
26
27
29
30
32
33
35
36
38
39
41
42
44
45
47
48
50
51
Organization
Burst
Length
Latency
(Cycle)
ODT
No
Product
Type
QDR II+ / DDR II+
x9
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
Frequency (max)
(MHz)
Cycle Time (min)
(ns)
Part NumberĄ yy ă
R1Q 2 A72 09 A Bv- yy
R1Q 2 A72 18 A Bv- yy
R1Q 2 A72 36 A Bv- yy
R1Q 3 A72 18 A Bv- yy
R1Q 3 A72 36 A Bv- yy
R1Q 4 A72 18 A Bv- yy
R1Q 4 A72 36 A Bv- yy
R1Q 5 A72 18 A Bv- yy
R1Q 5 A72 36 A Bv- yy
R1Q 6 A72 18 A Bv- yy
R1Q 6 A72 36 A Bv- yy
R1Q A A72 18 A Bv- yy
R1Q A A72 36 A Bv- yy
R1Q B A72 18 A Bv- yy
R1Q B A72 36 A Bv- yy
R1Q C A72 18 A Bv- yy
R1Q C A72 36 A Bv- yy
R1Q D A72 18 A Bv- yy
R1Q D A72 36 A Bv- yy
R1Q E A72 18 A Bv- yy
R1Q E A72 36 A Bv- yy
R1Q F A72 18 A Bv- yy
R1Q F A72 36 A Bv- yy
R1Q G A72 18 A Bv- yy
R1Q G A72 36 A Bv- yy
R1Q H A72 18 A Bv- yy
R1Q H A72 36 A Bv- yy
R1Q J A72 18 A Bv- yy
R1Q J A72 36 A Bv- yy
R1Q K A72 18 A Bv- yy
R1Q K A72 36 A Bv- yy
R1Q L A72 18 A Bv- yy
R1Q L A72 36 A Bv- yy
R1Q M A72 18 A Bv- yy
R1Q M A72 36 A Bv- yy
533
QDR II / DDR II
500
450
400
375
333
333
300
250
200
1.875 2.00
2.22
2.50
2.66
3.00
3.00
3.30
4.00
5.00
-22
-25
-27
-30
-30
-33
-40
-40
-50
-50
-40
-50
-19
-20
-19
-20
-22
-19
-20
-22
-19
-20
-22
-19
-20
-22
-19
-20
-22
-19
-20
-22
-30
-33
-40
-30
-33
-40
-30
-33
-40
-30
-33
-40
-25
-25
-25
-25
-25
-25
Notes:
1. "v" represents the package size. If "v" = "G" then size is 15 x 17 mm, and if "v" = "B" then 13 x 15 mm.
2. "yy" represents the speed bin. "R1QAA7236ABB-20" can operate at 500 MHz(max) of frequency, for example.
3. The part which is not listed above is not supported, as of the day when this datasheet was issued,
in spite of the existence of the part number or datasheet.
Rev. 0.11 : 2013.01.15
R10DS0173EJ0011
PAGE:3
R1QHA72 / R1QLA72 Series
Pin Arrangement
R1Q4A7236 (Top) / R1QB(H)A7236 (Mid) / R1QE(L)A7236 (Bottom)
1
2
3
4
5
6
7
8
9
10
11
A
/CQ
NC
SA
R-/W
/BW2
/K
/BW1
/LD
SA
SA
CQ
B
NC
SA
/BW3
/BW0
SA
NC
NC
DQ8
C
NC
DQ28
VSS
SA
SA
VSS
NC
DQ17
DQ7
D
NC
DQ29 DQ19
VSS
VSS
K
SA0
NC
NC
VSS
VSS
VSS
NC
NC
DQ16
E
NC
DQ20
VDDQ
VSS
VSS
VSS
VDDQ
NC
DQ15
DQ6
F
NC
DQ30 DQ21
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
DQ5
G
NC
DQ31 DQ22
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
DQ14
H
/DOFF
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
DQ27 DQ18
NC
NC
VREF
VDDQ
J
NC
NC
DQ32
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ13
DQ4
K
NC
NC
DQ23
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ12
DQ3
L
NC
DQ33 DQ24
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ2
DQ34
VSS
VSS
VSS
VSS
VSS
NC
DQ11
DQ1
DQ35 DQ25
VSS
SA
SA
VSS
NC
NC
DQ10
SA
SA
NC
DQ9
DQ0
SA
SA
SA
TMS
TDI
M
NC
N
NC
NC
P
NC
NC
DQ26
SA
R
TDO
TCK
SA
SA
SA
C
QVLD
SA
QVLD
/C
NC
SA
ODT
(Top View)
Top
ĸR1Q4A7236
Mid
ĸR1QB(H)A7236
Bottom ĸR1QE(L)A7236
Notes: 1. Address expansion order for future higher density SRAMs: 10A ĺ 2A ĺ 7A ĺ 5B.
2. NC pins can be left floating or connected to 0V ᨺ VDDQ.
R1Q4A7218 (Top) / R1QB(H)A7218 (Mid) / R1QE(L)A7218 (Bottom)
1
2
3
4
5
6
7
8
9
10
11
A
/CQ
SA
SA
R-/W
/BW1
/K
NC
/LD
SA
SA
CQ
B
NC
DQ9
NC
SA
NC
/BW0
SA
NC
NC
DQ8
C
NC
NC
NC
VSS
SA
SA
VSS
NC
DQ7
NC
D
NC
NC
DQ10
VSS
VSS
K
SA0
NC
NC
VSS
VSS
VSS
NC
NC
NC
E
NC
NC
DQ11
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ6
F
NC
DQ12
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
DQ5
G
NC
NC
DQ13
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
H
/DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ4
NC
K
NC
NC
DQ14
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
DQ3
L
NC
DQ15
NC
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ2
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
DQ1
NC
SA
SA
VSS
NC
NC
NC
C
QVLD
SA
SA
NC
NC
DQ0
P
NC
NC
DQ17
SA
SA
QVLD
/C
NC
SA
SA
SA
TMS
TDI
R
TDO TCK
SA
SA
SA
ODT
(Top View)
Notes: 1. Address expansion order for future higher density SRAMs: 10A ĺ 2A ĺ 7A ĺ 5B.
2. NC pins can be left floating or connected to 0V ᨺ VDDQ.
N
NC
Rev. 0.11 : 2013.01.15
R10DS0173EJ0011
NC
DQ16
VSS
SA
PAGE:4
R1QHA72 / R1QLA72 Series
Pin Arrangement
R1Q4A7209 (Top) / R1QB(H)A7209 (Mid) / R1QE(L)A7209 (Bottom)
Just Reference
1
2
3
4
5
6
7
8
9
10
11
A
/CQ
SA
SA
R-/W
NC
/K
NC
/LD
SA
SA
CQ
B
NC
NC
NC
SA
NC
K
/BW
SA
NC
NC
DQ4
C
NC
NC
NC
VSS
SA
SA
SA
VSS
NC
NC
NC
D
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
E
NC
NC
DQ5
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ3
F
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
G
NC
NC
DQ6
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
H
/DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ2
NC
K
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
L
NC
DQ7
NC
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ1
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
SA
SA
VSS
NC
NC
NC
C
QVLD
SA
SA
NC
NC
DQ0
P
NC
NC
DQ8
SA
SA
QVLD
/C
NC
SA
SA
SA
TMS
TDI
R
TDO TCK
SA
SA
SA
ODT
(Top View)
Notes: 1. Address expansion order for future higher density SRAMs: 10A ĺ 2A ĺ 7A ĺ 5B.
2. NC pins can be left floating or connected to 0V ᨺ VDDQ.
3. Note that 6C is not SA0 and 7C is not SA1 in x9 product. Thus ×9 product does not
permit random start address on the two least significant address bits. SA0, SA1 = 0
at the start of each address.
N
NC
Rev. 0.11 : 2013.01.15
R10DS0173EJ0011
NC
NC
VSS
SA
PAGE:5
hinS=00111.0011.0011.0011.0011
---00111.0011.0011.0011.0011--00111.0011.0011.0011.0011---DDR
R1QHA72 / R1QLA72 Series
Pin Descriptions
Name I/O type
SAx
Input
/LD
Input
R-/W
Input
/BWx
Input
K, /K
Input
C, /C
(II only)
Input
/DOFF
Input
TMS
TDI
Input
TCK
Input
Descriptions
Notes
Synchronous address inputs: These inputs are registered and must meet
the setup and hold times around the rising edge of K. All transactions
operate on a burst-of-four words (two clock periods of bus activity). SA0
and SA1 are used as the lowest two address bits for burst READ and
burst WRITE operations permitting a random burst start address on ×18
and ×36 of DDR II (not II+) devices. These inputs are ignored when
device is deselected or once burst operation is in progress.
Synchronous load: This input is brought low when a bus cycle sequence
is to be defined. This definition includes address and READ / WRITE
direction. All transactions operate on a burst-of-four data (two clock
periods of bus activity).
Synchronous read / write Input: When /LD is low, this input designates
the access type (READ when R-/W is high, WRITE when R-/W is low) for
the loaded address. R-/W must meet the setup and hold times around
the rising edge of K.
Synchronous byte writes: When low, these inputs cause their respective
byte to be registered and written during WRITE cycles. These signals
are sampled on the same edge as the corresponding data and must meet
setup and hold times around the rising edges of K and /K for each of the
two rising edges comprising the WRITE cycle. See Byte Write Truth
Table for signal to data relationship.
Input clock: This input clock pair registers address and control inputs on
the rising edge of K, and registers data on the rising edge of K and the
rising edge of /K. /K is ideally 180 degrees out of phase with K. All
synchronous inputs must meet setup and hold times around the clock
rising edges. These balls cannot remain VREF level.
Output clock: This clock pair provides a user-controlled means of tuning
device output data. The rising edge of /C is used as the output timing
reference for the first and third output data. The rising edge of C is used
as the output timing reference for second and fourth output data. Ideally,
1
/C is 180 degrees out of phase with C. C and /C may be tied high to
force the use of K and /K as the output reference clocks instead of having
to provide C and /C clocks. If tied high, C and /C must remain high and
not to be toggled during device operation. These balls cannot remain
VREF level.
DLL/PLL disable: When low, this input causes the DLL/PLL to be
bypassed for stable, low frequency operation.
IEEE1149.1 test inputs: 1.8 V I/O levels. These balls may be left not
connected if the JTAG function is not used in the circuit.
IEEE1149.1 clock input: 1.8 V I/O levels. This ball must be tied to VSS if
the JTAG function is not used in the circuit.
Notes:
1. R1Q2, R1Q3, R1Q4, R1Q5, R1Q6 series have C and /C pins. R1QA, R1QB, R1QC, R1QD,
R1QE, R1QF, R1QG, R1QH, R1QJ, R1QK, R1QL, R1QM, R1QN, R1QP series do not have C,
/C pins. In the series, K and /K are used as the output reference clocks instead of C and /C.
Therefore, hereafter, C and /C represent K and /K in this document.
Rev. 0.11 : 2013.01.15
R10DS0173EJ0011
PAGE:6
R1QHA72 / R1QLA72 Series
Name
I/O type
Descriptions
Notes
Output impedance matching input: This input is used to tune the device
outputs to the system data bus impedance. DQ and CQ output
impedance are set to 0.2 × RQ, where RQ is a resistor from this ball to
ground. This ball can be connected directly to VDDQ, which enables the
ZQ
Input minimum impedance mode. This ball cannot be connected directly to
VSS or left unconnected.
In ODT (On Die Termination) enable devices, the ODT termination
values tracks the value of RQ. The ODT range is selected by ODT
control input.
ODT control: When low;
[Option 1] Low range mode is selected. The impedance range is
between 52 Ω and 105 Ω (Thevenin equivalent), which follows 0.3 × RQ
for 175 Ω ” RQ ” 350 Ω.
[Option 2] ODT is disabled.
ODT
1
Input
When high; High range mode is selected. The impedance range is
(II+ only)
between 105 Ω and 150 Ω (Thevenin equivalent), which follows 0.6 × RQ
for 175 Ω ” RQ ” 250 Ω.
When floating; [Option 1] High range mode is selected.
[Option 2] ODT is disabled.
Synchronous data I/Os: Input data must meet setup and hold times
around the rising edges of K and /K. Output data is synchronized to the
respective C and /C, or to the respective K and /K if C and /C are tied
Input high.
DQ0 to
The ×9 device uses DQ0~DQ8.
/
DQn
output
DQ9~DQ35 should be treated as NC pin.
The ×18 device uses DQ0~DQ17.
DQ18~DQ35 should be treated as NC pin.
The ×36 device uses DQ0~DQ35.
Synchronous echo clock outputs: The edges of these outputs are tightly
matched to the synchronous data outputs and can be used as a data
CQ, /CQ Output
valid indication. These signals run freely and do not stop when DQ tristates.
TDO
Output IEEE 1149.1 test output: 1.8 V I/O level.
QVLD
Valid output indicator: The Q Valid indicates valid output data. QVLD is
Output
edge aligned with CQ and /CQ.
(II+ only)
Power supply: 1.8 V nominal. See DC Characteristics and Operating
Supply
VDD
2
Conditions for range.
Power supply: Isolated output buffer supply. Nominally 1.5 V. See DC
Supply
VDDQ
2
Characteristics and Operating Conditions for range.
Supply Power supply: Ground.
2
VSS
HSTL input reference voltage: Nominally VDDQ/2, but may be adjusted to
VREF
⎯
improve system noise margin. Provides a reference voltage for the
HSTL input buffers.
No connect: These pins can be left floating or connected to 0V ᨺ VDDQ.
NC
⎯
Notes:
1. Renesas status: Option 1 = Available, Option 2 = Possible.
2. All power supply and ground balls must be connected for proper operation of the device.
Rev. 0.11 : 2013.01.15
R10DS0173EJ0011
PAGE:7
R1QHA72 / R1QLA72 Series
Block Diagram (R1QxA7236 / R1QxA7218 series, x=4)
SA0'
Address
Registry
and
Logic
K
/K
Memory
Array
36/18
2
72
/36
DQ
36/18
C,/C
or
K,/K
C
or
K
K
72
/36
Output
Select
Output
Buffer
Data
Registry
and
Logic
Write Driver
/BWx
Write
Register
4/2
ZQ
CQ, /CQ
72
/36
R-/W
/LD
SA0'''
Output
Register
SA
/LD
R-/W
K
/K
Output
SA0'' Control
Logic
21/22
21/22
MUX
Burst
Logic
Sense Amp
SA0
Notes
1. C and /C pins do not exist in II+ series parts.
Block Diagram
(R1QxA7236 / R1QxA7218 / R1QyA7209 series,
20/21/22
Address
Registry
and
Logic
ZQ
K
/K
36/18/9
K
C
or
K
72
/36
/18
2
DQ
Output
Select
Output
Buffer
72
/36
/18
Output
Register
Memory
Array
Sense Amp
/BWx
Data
Registry
and
Logic
Write Driver
R-/W
/LD
Write
Register
CQ, /CQ
72
/36
/18
4/2/1
y=4,B,E,H,L)
20/21/22
MUX
SA
/LD
R-/W
K
/K
x=B,E,H,L,
36/18/9
C,/C
or
K,/K
Notes
1. C and /C pins do not exist in II+ series parts.
Rev. 0.11 : 2013.01.15
R10DS0173EJ0011
PAGE:8
hinS=11111.1111.1111.1111.1111--11111.1111.1111.1111.1111---00000.0000.0000.0000.0000--72M_36M
R1QHA72 / R1QLA72 Series
General Description
Power-up and Initialization Sequence
- VDD must be stable before K, /K clocks are applied.
- Recommended voltage application sequence : VSS ĺ VDD ĺ VDDQ & VREF ĺ VIN. (0 V to VDD, VDDQ < 200 ms)
- Apply VREF after VDDQ or at the same time as VDDQ.
- Then execute either one of the following three sequences.
1. Single Clock Mode (C and /C tied high)
- Drive /DOFF high (/DOFF can be tied high from the start).
- Then provide stable clocks (K, /K) for at least 1024 cycles (II series) or 20 us (II+ series).
These meet the QDR common specification of 20 us.
Whenclock
the operating
is less
180 MHz, 2048 cycles are required (II series).
1. Single
mode (C frequency
and /C pins
fixedthan
High)
Status
Power Up &
Unstable Stage
NOP &
Set-up Stage
Normal
Operation
VDD
VDDQ
VREF
Fix High (=Vddq)
/DOFF
SET-UP Cycle
K, /K
2. Double Clock Mode (C and /C control outputs) (II series only)
- Drive /DOFF high (/DOFF can be tied high from the start)
- Then provide stable clocks (K, /K , C, /C) for at least 1024 cycles (II series).
This meets the QDR common specification of 20 us.
Whenclock
the operating
2. Double
mode frequency is less than 180 MHz, 2048 cycles are required (II series).
Status
Power Up &
Unstable Stage
NOP &
Set-up Stage
Normal
Operation
VDD
VDDQ
VREF
Fix High (=Vddq)
/DOFF
SET-UP Cycle
K, /K
C, /C
3. DLL/PLL Off Mode (/DOFF tied low)
- In the "NOP and setup stage", provide stable clocks (K, /K) for at least 1024 cycles (II series) or 20 us (II+
series). These meet the QDR common specification of 20 us.
Rev. 0.11 : 2013.01.15
R10DS0173EJ0011
PAGE:9
Common
R1QHA72 / R1QLA72 Series
DLL/PLL Constraints
1. DLL/PLL uses K clock as its synchronizing input. The input should have low phase jitter which is
specified as tKC var.
2. The lower end of the frequency at which the DLL/PLL can operate is 120 MHz.
(Please refer to AC Characteristics table for detail.)
3. When the operating frequency is changed or /DOFF level is changed, setup cycles are required again.
Programmable Output Impedance
1. Output buffer impedance can be programmed by terminating the ZQ ball to VSS through a precision resistor
(RQ). The value of RQ is five times the output impedance desired. The allowable range of RQ to
guarantee impedance matching with a tolerance of 15% is 250 Ω typical. The total external capacitance of
ZQ ball must be less than 7.5 pF.
Rev. 0.11 : 2013.01.15
R10DS0173EJ0011
PAGE:10
IIP
R1QHA72 / R1QLA72 Series
QVLD (Valid data indicator)
(R1QA, R1QB, R1QC, R1QD, R1QE, R1QF, R1QG, R1QH, R1QJ, R1QK, R1QL, R1QM
R1QN, R1QP series)
1. QVLD is provided on the QDR-II+ and DDR-II+ to simplify data capture on high speed systems. The Q
Valid indicates valid output data. QVLD is activated half cycle before the read data for the receiver to be
ready for capturing the data. QVLD is inactivated half cycle before the read finish for the receiver to stop
capturing the data. QVLD is edge aligned with CQ and /CQ.
ODT (On Die Termination)
(R1QD, R1QE, R1QF, R1QK, R1QL, R1QM, R1QP series)
1. To reduce reflection which produces noise and lowers signal quality, the signals should be terminated,
especially at high frequency. Renesas offers ODT on the input signals to QDR-II+ and DDR-II+ family of
devices. (See the ODT pin table)
2. In ODT enable devices, the ODT termination values tracks the value of RQ. The ODT range is selected by
ODT control input. (See the ODT range table)
3. In DDR-II+ devices having common I/O bus, ODT is automatically enabled when the device inputs data
and disabled when the device outputs data.
4. There is no difference in AC timing characteristics between the SRAMs with ODT and SRAMs without
ODT.
5. There is no increase in the IDD of SRAMs with ODT, however, there is an increase in the IDDQ (current
consumption from the I/O voltage supply) with ODT.
ODT range
Unit
Notes
Option 1
Option 2
-
6
Low
0.3 × RQ
(ODT disable)
Ω
1, 4
High
0.6 × RQ
0.6 × RQ
Ω
2, 5
Floating
0.6 × RQ
(ODT disable)
Ω
3
ODT control pin
Thevenin equivalent resistance (RTHEV)
Notes:
1. Allowable range of RQ for Option 1 to guarantee impedance matching a tolerance of ± 20 % is
175 Ω ” RQ ” 350 Ω.
2. Allowable range of RQ to guarantee impedance matching a tolerance of ± 20 % is
175 Ω ” RQ ” 250 Ω.
3. Allowable range of RQ for Option 1 to guarantee impedance matching a tolerance of ± 20 % is
175 Ω ” RQ ” 250 Ω.
4. At option 1, ODT control pin is connected to VDDQ through 3.5 kΩ. Therefore it is recommended
to connect it to VSS through less than 100 Ω to make it low.
5. At option 2, ODT control pin is connected to VSS through 3.5 kΩ. Therefore it is recommended to
connect it to VDDQ through less than 100 Ω to make it high.
6. Renesas status: Option 1 = Available, Option 2 = Possible. If you need devices with option 2,
please contact Renesas sales office.
Rev. 0.11 : 2013.01.15
R10DS0173EJ0011
PAGE:11
IIP
R1QHA72 / R1QLA72 Series
Thevenin termination
SRAM with ODT
Other LSI
VDDQ
2 × RTHEV
ZQ
RQ
Output
Buffer
2 × RTHEV
Input
Buffer
VSS
VSS
ODT pin (R1QD, R1QE, R1QF, R1QK, R1QL, R1QM, R1QP series)
ODT On/Off timing
Option 2
Pin name
Option 1
D0 ~ Dn in separate I/O devices
DQ0 ~ DQn
in common I/O devices
Notes:
Notes
ODT pin = High
Always On
Off: First Read Command
+ Read Latency
- 0.5 cycle
On: Last Read Command
+ Read Latency
+ BL/2 cycle + 0.5 cycle
(See below timing chart)
ODT pin = Low
or Floating
3
Always Off
1
Always Off
2
/BWx
Always On
Always Off
K, /K
Always On
Always Off
1. Separate I/O devices are R1QD, R1QK, R1QP series.
2. Common I/O devices are R1QE, R1QF, R1QL, R1QM series.
3. Renesas status: Option 1 = Available, Option 2 = Possible. If you need devices with
option 2, please contact Renesas sales office.
Rev. 0.11 : 2013.01.15
R10DS0173EJ0011
PAGE:12
IIP
R1QHA72 / R1QLA72 Series
ODT on/off Timing Chart for R1QE series (DDR II+, Burst Length=2, Read Latency=2.5 cycle)
Status
Read Read Read
Write Write Write Write Read Read
NOP Read
(B2) (B2) (B2) (B2) NOP NOP NOP (B2) (B2) (B2) (B2) (B2) (B2)
K, /K
Command
Ra
Rb
Rc
DQ
Rd
We
Wf
Qa Qa Qb Qb Qc Qc Qd Qd
DQ ODT
Enabled
Wg
Wh
Ri
Rj
De De Df Df Dg Dg Dh Dh
Disabled
Qi Qi Qj
Enabled
Disabled
ODT on/off Timing Chart for R1QF series (DDR II+, Burst Length=4, Read Latency=2.5 cycle)
Status
NOP Read
(B4)
-
Read
(B4)
-
NOP NOP NOP Write
(B4)
Write
(B4)
-
Read
(B4)
-
-
K, /K
Command
Ra
Rc
DQ
We
Wg
Qa Qa Qa Qa Qc Qc Qc Qc
DQ ODT
Enabled
Ri
De De De De Dg Dg Dg Dg
Disabled
Qi Qi Qi
Enabled
Disabled
ODT on/off Timing Chart for R1QL series (DDR II+, Burst Length=2, Read Latency=2.0 cycle)
Status
Read Read Read
Write Write Write Write Read Read Read
NOP Read
(B2) (B2) (B2) (B2) NOP NOP (B2) (B2) (B2) (B2) (B2) (B2) (B2)
K, /K
Command
Ra
Rb
Rc
DQ
Rd
We
Qa Qa Qb Qb Qc Qc Qd Qd
DQ ODT
Enabled
Wf
Wg
Wh
Ri
Rj
Rk
De De Df Df Dg Dg Dh Dh
Disabled
Qi Qi Qj Qj Qk Qk
Enabled
Disabled
ODT on/off Timing Chart for R1QM series (DDR II+, Burst Length=4, Read Latency=2.0 cycle)
Status
NOP Read
(B4)
-
Read
(B4)
-
NOP NOP Write
(B4)
-
Write
(B4)
-
Read
(B4)
-
Read
(B4)
K, /K
Command
Ra
DQ
DQ ODT
Rc
We
Qa Qa Qa Qa Qc Qc Qc Qc
Enabled
Wg
Ri
De De De De Dg Dg Dg Dg
Disabled
Enabled
Rk
Qi Qi Qi Qi Qk Qk
Disabled
Notes
1. ODT on/off switching timings are edge aligned with CQ or /CQ.
Rev. 0.11 : 2013.01.15
R10DS0173EJ0011
PAGE:13
R1QHA72 / R1QLA72 Series
K Truth Table
Operation
Write Cycle:
Load address, input write
data on consecutive K
and /K rising edges
K
/LD
R-/W
DQ
Data in
Ĺ
L
L
Input
data
D(A1)
D(A2)
Input
clock
K(t+1)Ĺ
/K(t+1)Ĺ
Q(A1)
Q(A2)
RL*8=1.5
/C(t+1)Ĺ
C(t+2)Ĺ
RL=2.0
C(t+2)Ĺ
/C(t+2)Ĺ
RL=2.5
/C(t+2)Ĺ
C(t+3)Ĺ
Data out
Read Cycle:
Load address, output
read data on consecutive
C and /C rising edges
Ĺ
NOP (No operation)
Ĺ
Standby (Clock stopped) Stopped
L
H
Output
data
Input
clock
for Q
H
×
High-Z
×
×
Previous state
Notes:
1. H: high level, L: low level, ×: don’t care, Ĺ: rising edge.
2. Data inputs are registered at K and /K rising edges. Data outputs are delivered at C and /C
rising edges, except if C and /C are high, then data outputs are delivered at K and /K rising
edges.
3. /LD and R-/W must meet setup/hold times around the rising edges (low to high) of K and are
registered at the rising edge of K.
4. This device contains circuitry that will ensure the outputs will be in high-Z during power-up.
5. Refer to state diagram and timing diagrams for clarification.
6. When clocks are stopped, the following cases are recommended; the case of K = low, /K =
high, C = low and /C = high, or the case of K = high, /K = low, C = high and /C = low. This
condition is not essential, but permits most rapid restart by overcoming transmission line
charging symmetrically.
7. A1 refers to the address input during a WRITE or READ cycle. A2 refers to the next internal
burst address in accordance with the linear burst sequence.
8. RL = Read Latency (unit = cycle).
Burst Sequence
Linear Burst Sequence Table (R1Q4Aww36 / R1Q4Aww18 series )
External address
1st internal burst address
Rev. 0.11 : 2013.01.15
R10DS0173EJ0011
SA0
0
1
SA0
1
0
Notes
PAGE:14
Common
R1QHA72 / R1QLA72 Series
Byte Write Truth Table ( x 36 )
Operation
Write D0 to D35
Write D0 to D8
Write D9 to D17
Write D18 to D26
Write D27 to D35
Write nothing
K
/K
/BW0
/BW1
/BW2
/BW3
Ĺ
-
L
L
L
L
-
Ĺ
L
L
L
L
Ĺ
-
L
H
H
H
-
Ĺ
L
H
H
H
Ĺ
-
H
L
H
H
-
Ĺ
H
L
H
H
Ĺ
-
H
H
L
H
-
Ĺ
H
H
L
H
Ĺ
-
H
H
H
L
-
Ĺ
H
H
H
L
Ĺ
-
H
H
H
H
-
Ĺ
H
H
H
H
Notes:
1. H: high level, L: low level, Ĺ: rising edge.
2. Assumes a WRITE cycle was initiated. /BWx can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
Byte Write Truth Table ( x 18 )
Operation
Write D0 to D17
Write D0 to D8
Write D9 to D17
Write nothing
K
/K
/BW0
/BW1
Ĺ
-
L
L
-
Ĺ
L
L
Ĺ
-
L
H
-
Ĺ
L
H
Ĺ
-
H
L
-
Ĺ
H
L
Ĺ
-
H
H
-
Ĺ
H
H
Notes:
1. H: high level, L: low level, Ĺ: rising edge.
2. Assumes a WRITE cycle was initiated. /BWx can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
Byte Write Truth Table ( x 9 )
Operation
Write D0 to D8
Write nothing
Just Reference except R1Q2A**09 series
K
/K
/BW
Ĺ
-
L
-
Ĺ
L
Ĺ
-
H
-
Ĺ
H
Notes:
1. H: high level, L: low level, Ĺ: rising edge.
2. Assumes a WRITE cycle was initiated. /BWx can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
Rev. 0.11 : 2013.01.15
R10DS0173EJ0011
PAGE:15
R1QHA72 / R1QLA72 Series
Bus Cycle State Diagram
/LD = H & Count = 2
R-/W = L
/LD = L
&
Count = 2
/LD = H
NOP
/LD = L
Write Double
Count
= Count + 2
Load New
Address
Count = 0
Supply
voltage
provided
R-/W = H
Power
Up
/LD = L
&
Count = 2
Read Double
Count
= Count + 2
/LD = H & Count = 2
Notes:
1. SA0 is internally advanced in accordance with the burst order table. Bus cycle is terminated at
the end of this sequence (burst count = 2).
2. State machine control timing sequence is controlled by K.
Rev. 0.11 : 2013.01.15
R10DS0173EJ0011
PAGE:16
Common
R1QHA72 / R1QLA72 Series
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Notes
Input voltage on any ball
VIN
−0.5 to VDD + 0.5
(2.5 V max.)
V
1, 4
Input/output voltage
VI/O
−0.5 to VDDQ + 0.5
(2.5 V max.)
V
1, 4
Core supply voltage
VDD
−0.5 to 2.5
V
1, 4
Output supply voltage
VDDQ
−0.5 to VDD
V
1, 4
Junction temperature
Tj
+125 (max)
°C
5
Storage temperature
TSTG
−55 to +125
°C
Notes:
1. All voltage is referenced to VSS.
2. Permanent device damage may occur if Absolute Maximum Ratings are exceeded.
Functional operation should be restricted the Operation Conditions. Exposure to higher than
recommended voltages for extended periods of time could affect device reliability.
3. These CMOS memory circuits have been designed to meet the DC and AC specifications
shown in the tables after thermal equilibrium has been established.
4. The following supply voltage application sequence is recommended: VSS, VDD, VDDQ, VREF
then VIN. Remember, according to the Absolute Maximum Ratings table, VDDQ is not to
exceed 2.5 V, whatever the instantaneous value of VDDQ.
5. Some method of cooling or airflow should be considered in the system. (Especially for high
frequency or ODT parts)
Recommended DC Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Power supply voltage -- core
VDD
1.7
1.8
1.9
V
1
Power supply voltage -- I/O
VDDQ
1.4
1.5
VDD
V
1, 2
Input reference voltage -- I/O
VREF
0.68
0.75
0.95
V
3
Input high voltage
VIH (DC)
VREF + 0.1
⎯
VDDQ + 0.3
V
1, 4, 5
Input low voltage
VIL (DC)
−0.3
⎯
VREF − 0.1
V
1, 4, 5
Notes:
1. At power-up, VDD and VDDQ are assumed to be a linear ramp from 0V to VDD(min.) or
VDDQ(min.) within 200ms. During this time VDDQ < VDD and VIH < VDDQ.
During normal operation, VDDQ must not exceed VDD.
2. Please pay attention to Tj not to exceed the temperature shown in the absolute maximum
ratings table due to current from VDDQ.
3. Peak to peak AC component superimposed on VREF may not exceed 5% of VREF.
4. These are DC test criteria. The AC VIH / VIL levels are defined separately to measure timing
parameters.
5. Overshoot: VIH (AC) ≤ VDDQ + 0.5 V for t ≤ tKHKH/2
Undershoot: VIL (AC) ≥ −0.5 V for t ≤ tKHKH/2
During normal operation, VIH(DC) must not exceed VDDQ and VIL(DC) must not be lower than VSS.
Rev. 0.11 : 2013.01.15
R10DS0173EJ0011
PAGE:17
hinS=11111.1111.1111.1111.1111--00000.0000.0000.0000.0000--00000.0000.0000.0000.0000---072M
R1QHA72 / R1QLA72 Series
DC Characteristics
(Ta = 0 ~ +70°C @ R1Q*A*****BB-**R** series, Ta = -40 ~ +85°C @ R1Q*A*****BB-**I** series)
(VDD = 1.8V ±0.1V, VDDQ = 1.5V, VREF = 0.75V)
Operating Supply Current (Write / Read)
Symbol = IDD. Unit = mA. See Notes 1, 2 and 3 in the page after next.
B2
QDRII
No
B2
1.5
B4
DDRII
B4
DDRII
SIO
B2
No
B2
2.5
QDRII+ B4
DDRII+
B4
Yes
B2
2.5
QDRII+ B4
DDRII+
B4
No
Yes
B2
2.0
QDRII+ B4
2.0
1
2
3
5
6
8
9
11
12
14
15
17
18
20
21
23
24
26
27
29
30
32
33
35
36
38
39
41
42
44
45
47
48
50
51
DDRII+
B4
QDRII+ B4
B2
DDRII+
B4
Organization
Burst
Length
Latency
(Cycle)
ODT
No
Product
Type
QDR II+ / DDR II+
x9
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
Frequency (max)
(MHz)
Cycle Time (min)
(ns)
Part NumberĄ yy ă
R1Q 2 A72 09 A Bv- yy
R1Q 2 A72 18 A Bv- yy
R1Q 2 A72 36 A Bv- yy
R1Q 3 A72 18 A Bv- yy
R1Q 3 A72 36 A Bv- yy
R1Q 4 A72 18 A Bv- yy
R1Q 4 A72 36 A Bv- yy
R1Q 5 A72 18 A Bv- yy
R1Q 5 A72 36 A Bv- yy
R1Q 6 A72 18 A Bv- yy
R1Q 6 A72 36 A Bv- yy
R1Q A A72 18 A Bv- yy
R1Q A A72 36 A Bv- yy
R1Q B A72 18 A Bv- yy
R1Q B A72 36 A Bv- yy
R1Q C A72 18 A Bv- yy
R1Q C A72 36 A Bv- yy
R1Q D A72 18 A Bv- yy
R1Q D A72 36 A Bv- yy
R1Q E A72 18 A Bv- yy
R1Q E A72 36 A Bv- yy
R1Q F A72 18 A Bv- yy
R1Q F A72 36 A Bv- yy
R1Q G A72 18 A Bv- yy
R1Q G A72 36 A Bv- yy
R1Q H A72 18 A Bv- yy
R1Q H A72 36 A Bv- yy
R1Q J A72 18 A Bv- yy
R1Q J A72 36 A Bv- yy
R1Q K A72 18 A Bv- yy
R1Q K A72 36 A Bv- yy
R1Q L A72 18 A Bv- yy
R1Q L A72 36 A Bv- yy
R1Q M A72 18 A Bv- yy
R1Q M A72 36 A Bv- yy
533
QDR II / DDR II
500
450
400
375
333
333
300
250
200
1.875 2.00
2.22
2.50
2.66
3.00
3.00
3.30
4.00
5.00
-22
-25
-27
-30
-30
-33
-50
670
780
830
880
910
750
810
660
700
750
810
820
850
700
760
630
670
700
760
-40
760
890
950
730
750
630
680
590
630
630
680
-19
1220
1280
1030
1110
820
880
1220
1280
1030
1110
820
880
-20
1160
1220
990
1060
790
850
1160
1220
990
1060
790
850
1070
1130
920
990
750
800
1070
1130
920
990
750
800
1070 980
1150 1060
920 850
990 910
750 710
800 760
1070 980
1150 1060
920 850
990 910
750 710
800 760
Notes:
1. "v" represents the package size. If "v" = "G" then size is 15 x 17 mm, and if "v" = "B" then 13 x 15 mm.
2. "yy" represents the speed bin. "R1QAA7236ABB-20" can operate at 500 MHz(max) of frequency, for example.
Rev. 0.11 : 2013.01.15
R10DS0173EJ0011
PAGE:18
hinS=11111.1111.1111.1111.1111--00000.0000.0000.0000.0000--00000.0000.0000.0000.0000---072M
R1QHA72 / R1QLA72 Series
Standby Supply Current (NOP)
Symbol = ISB1. Unit = mA. See Notes 2, 4 and 5 in the next page.
B2
QDRII
No
B2
1.5
B4
DDRII
B4
DDRII
SIO
B2
2.5
No
Yes
B2
2.5
QDRII+ B4
DDRII+
B4
QDRII+ B4
B2
DDRII+
B4
No
Yes
B2
2.0
QDRII+ B4
2.0
1
2
3
5
6
8
9
11
12
14
15
17
18
20
21
23
24
26
27
29
30
32
33
35
36
38
39
41
42
44
45
47
48
50
51
DDRII+
B4
QDRII+ B4
B2
DDRII+
B4
Organization
Burst
Length
Latency
(Cycle)
ODT
No
Product
Type
QDR II+ / DDR II+
x9
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
Frequency (max)
(MHz)
Cycle Time (min)
(ns)
Part NumberĄ yy ă
R1Q 2 A72 09 A Bv- yy
R1Q 2 A72 18 A Bv- yy
R1Q 2 A72 36 A Bv- yy
R1Q 3 A72 18 A Bv- yy
R1Q 3 A72 36 A Bv- yy
R1Q 4 A72 18 A Bv- yy
R1Q 4 A72 36 A Bv- yy
R1Q 5 A72 18 A Bv- yy
R1Q 5 A72 36 A Bv- yy
R1Q 6 A72 18 A Bv- yy
R1Q 6 A72 36 A Bv- yy
R1Q A A72 18 A Bv- yy
R1Q A A72 36 A Bv- yy
R1Q B A72 18 A Bv- yy
R1Q B A72 36 A Bv- yy
R1Q C A72 18 A Bv- yy
R1Q C A72 36 A Bv- yy
R1Q D A72 18 A Bv- yy
R1Q D A72 36 A Bv- yy
R1Q E A72 18 A Bv- yy
R1Q E A72 36 A Bv- yy
R1Q F A72 18 A Bv- yy
R1Q F A72 36 A Bv- yy
R1Q G A72 18 A Bv- yy
R1Q G A72 36 A Bv- yy
R1Q H A72 18 A Bv- yy
R1Q H A72 36 A Bv- yy
R1Q J A72 18 A Bv- yy
R1Q J A72 36 A Bv- yy
R1Q K A72 18 A Bv- yy
R1Q K A72 36 A Bv- yy
R1Q L A72 18 A Bv- yy
R1Q L A72 36 A Bv- yy
R1Q M A72 18 A Bv- yy
R1Q M A72 36 A Bv- yy
533
QDR II / DDR II
500
450
400
375
333
333
300
250
200
1.875 2.00
2.22
2.50
2.66
3.00
3.00
3.30
4.00
5.00
-22
-25
-27
-30
-30
-33
-50
510
600
630
630
650
650
710
540
570
650
710
590
610
610
670
510
540
610
670
-40
570
670
710
520
540
560
610
480
500
560
610
-19
870
910
870
960
690
730
870
910
870
960
690
730
-20
830
870
840
920
660
710
830
870
840
920
660
710
780
810
780
860
630
670
780
810
780
860
630
670
780
830
780
860
630
670
780
830
780
860
630
670
720
770
720
790
590
630
720
770
720
790
590
630
Notes:
1. "v" represents the package size. If "v" = "G" then size is 15 x 17 mm, and if "v" = "B" then 13 x 15 mm.
2. "yy" represents the speed bin. "R1QAA7236ABB-20" can operate at 500 MHz(max) of frequency, for example.
Rev. 0.11 : 2013.01.15
R10DS0173EJ0011
PAGE:19
Common
R1QHA72 / R1QLA72 Series
Leakage Currents & Output Voltage
Parameter
Symbol
Min
Max
Unit
Input leakage current
ILI
−2
2
μA
10
Output leakage current
ILO
−5
5
μA
11
Output high voltage
VOH
(Low)
VDDQ − 0.2
VDDQ
V
|IOH| ≤ 0.1 mA
8, 9
VOH
VDDQ/2
− 0.12
VDDQ/2
+ 0.12
V
Note 6
8, 9
VOL
(Low)
VSS
0.2
V
IOL ≤ 0.1 mA
8, 9
VOL
VDDQ/2
− 0.12
VDDQ/2
+ 0.12
V
Note 7
8, 9
Output low voltage
Test condition
Notes
Notes:
1. All inputs (except ZQ, VREF) are held at either VIH or VIL.
2. IOUT = 0 mA. VDD = VDD max, tKHKH = tKHKH min.
3. Operating supply currents (IDD) are measured at 100% bus utilization. IDD of QDR family is current of
device with 100% write and 100% read cycle. IDD of DDR family is current of device with 100% write
cycle (if IDD(Write) > IDD(Read)) or 100% read cycle (if IDD(Write) < IDD(Read)).
4. All address / data inputs are static at either VIN > VIH or VIN < VIL.
5. Reference value. (Condition = NOP currents are valid when entering NOP after all pending READ and
WRITE cycles are completed. )
6. Outputs are impedance-controlled. |IOH| = (VDDQ/2)/(RQ/5) for values of 175 Ω ≤ RQ ≤ 350 Ω.
7. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 Ω ≤ RQ ≤ 350 Ω.
8. AC load current is higher than the shown DC values. AC I/O curves are available upon request.
9. HSTL outputs meet JEDEC HSTL Class I and Class II standards.
10. 0 ≤ VIN ≤ VDDQ for all input balls (except VREF, ZQ, TCK, TMS, TDI ball).
If R1QD, R1QE, R1QF, R1QK, R1QL, R1QM, R1QP series, balls with ODT do not follow this spec.
11. 0 ≤ VOUT ≤ VDDQ (except TDO ball), output disabled.
Rev. 0.11 : 2013.01.15
R10DS0173EJ0011
PAGE:20
hinS=11111.1111.1111.1111.1111---11111.1111.1111.1111.1111--00000.0000.0000.0000.0000---72M_36M
R1QHA72 / R1QLA72 Series
Thermal Resistance
Parameter
Symbol Airflow
Typ
Junction to Ambient
șJA
1 m/s
11.0
Junction to Case
șJC
-
4.4
Unit
Test condition
Notes
°C/W
EIA/JEDEC JESD51
1
Notes:
1. These parameters are calculated under the condition. These are reference values.
2. Tj = Ta + șJA ™ Pd
Tj = Tc + șJC ™ Pd
where
Tj : junction temperature when the device has achieved a steady-state
after application of Pd (rC)
Ta : ambient temperature (rC)
Tc : temperature of external surface of the package or case (rC)
șJA : thermal resistance from junction-to-ambient (rC/W)
șJC : thermal resistance from junction-to-case (package) (rC/W)
Pd : power dissipation that produced change in junction temperature (W) (cf.JESD51-2A)
Capacitance
(Ta = +25°C, Frequency = 1.0MHz, VDD = 1.8V, VDDQ = 1.5V)
Parameter
Symbol Min
Typ
Max
Unit
Test condition Notes
Input capacitance
(SA, /R, /W, /BW, D(separate))
CIN
⎯
4
5
pF
VIN = 0 V
1, 2
Clock input capacitance (K, /K, C, /C)
CCLK
⎯
4
5
pF
VCLK = 0 V
1, 2
Output capacitance
(Q(separate), DQ(common), CQ, /CQ)
CI/O
⎯
5
6
pF
VI/O = 0 V
1, 2
Notes:
1. These parameters are sampled and not 100% tested.
2. Except JTAG (TCK, TMS, TDI, TDO) pins.
AC Test Conditions
Input waveform (Rise/fall time ≤ 0.3 ns)
1.25V
0.75V
Test points
0.75V
VDDQ/2
Test points
VDDQ/2
0.25V
Output waveform
Rev. 0.11 : 2013.01.15
R10DS0173EJ0011
PAGE:21
Common
R1QHA72 / R1QLA72 Series
Output load conditions
Output load and voltage conditions
1.8V±0.1V
VDDQ / 2
= 0.75V
1.5V
VDD
VDDQ
VDDQ / 2
= 0.75V
VREF
50Ω
Z0 = 50Ω
Q
SRAM
250Ω
ZQ
VSS
AC Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Input high voltage
VIH (AC)
VREF + 0.2
⎯
⎯
V
1, 2, 3, 4
Input low voltage
VIL (AC)
⎯
⎯
VREF – 0.2
V
1, 2, 3, 4
Notes:
1. All voltages referenced to VSS (GND).
During normal operation, VDDQ must not exceed VDD.
2. These conditions are for AC functions only, not for AC parameter test.
3. Overshoot: VIH (AC) ≤ VDDQ + 0.5 V for t ≤ tKHKH/2
Undershoot: VIL (AC) ≥ −0.5 V for t ≤ tKHKH/2
Control input signals may not have pulse widths less than tKHKL (min) or operate at cycle rates
less than tKHKH (min).
4. To maintain a valid level, the transitioning edge of the input must:
a. Sustain a constant slew rate from the current AC level through the target AC level,
VIL (AC) or VIH (AC).
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to maintain at least the target DC level,
VIL (DC) or VIH (DC).
Rev. 0.11 : 2013.01.15
R10DS0173EJ0011
PAGE:22
hinS=00000.0000.0000.0111.0111--00000.0000.0000.0111.0111--00000.0000.0000.0000.0000---RL=2.0
R1QHA72 / R1QLA72 Series
AC Characteristics (Read Latency = 2.0 cycle)
(Ta = 0 ~ +70°C @ R1Q*A*****BB-**R** series)
(Ta = -40 ~ +85°C @ R1Q*A*****BB-**I** series)
(VDD = 1.8V ±0.1V, VDDQ = 1.5V, VREF = 0.75V)
Parameter
Symbol
-19
Min
-20
-22
-25
-27
-30
Unit Notes
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
2.00
4.00
2.22
4.00
2.50
4.00
2.66
4.00
3.00
4.00
ns
Clock
Average clock
cycle time
(K, /K)
tKHKH
1.875 4.00
Clock high time
(K, /K)
tKHKL
0.40
⎯
0.40
⎯
0.40
⎯
0.40
⎯
0.40
⎯
0.40
⎯
Cycle
Clock low time
(K, /K)
tKLKH
0.40
⎯
0.40
⎯
0.40
⎯
0.40
⎯
0.40
⎯
0.40
⎯
Cycle
Clock to /clock
(K to /K)
tKH/KH
0.425
⎯
0.425
⎯
0.425
⎯
0.425
⎯
0.425
⎯
0.425
⎯
Cycle
/Clock to clock
(/K to K)
t/KHKH
0.425
⎯
0.425
⎯
0.425
⎯
0.425
⎯
0.425
⎯
0.425
⎯
Cycle
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
DLL/PLL Timing
Clock phase
jitter
(K, /K)
tKC var
⎯
0.15
⎯
0.15
⎯
0.15
⎯
0.20
⎯
0.20
⎯
0.20
ns
3
Lock time
(K)
tKC lock
20
⎯
20
⎯
20
⎯
20
⎯
20
⎯
20
⎯
us
2
K static to
DLL/PLL reset
tKC reset
30
⎯
30
⎯
30
⎯
30
⎯
30
⎯
30
⎯
ns
7
K, /K high to
output valid
tCHQV
⎯
0.55
⎯
0.55
⎯
0.55
⎯
0.55
⎯
0.55
⎯
0.55
ns
K, /K high to
output hold
tCHQX
−0.35
⎯
−0.35
⎯
−0.35
⎯
−0.35
⎯
−0.35
⎯
−0.35
⎯
ns
K, /K high to
echo clock valid
tCHCQV
⎯
0.55
⎯
0.55
⎯
0.55
⎯
0.55
⎯
0.55
⎯
0.55
ns
K, /K high to
echo clock hold
tCHCQX
−0.35
⎯
−0.35
⎯
−0.35
⎯
−0.35
⎯
−0.35
⎯
−0.35
⎯
ns
CQ, /CQ high to
output valid
tCQHQV
⎯
0.15
⎯
0.15
⎯
0.15
⎯
0.20
⎯
0.20
⎯
0.20
ns
4, 7
CQ, /CQ high to
output hold
tCQHQX
−0.15
⎯
−0.15
⎯
−0.15
⎯
−0.20
⎯
−0.20
⎯
−0.20
⎯
ns
4, 7
K, /K high to
output high-Z
tCHQZ
⎯
0.55
⎯
0.55
⎯
0.55
⎯
0.55
⎯
0.55
⎯
0.55
ns
5, 6
K, /K high to
output low-Z
tCHQX1
−0.35
⎯
−0.35
⎯
−0.35
⎯
−0.35
⎯
−0.35
⎯
−0.35
⎯
ns
5
/CQ high to
QVLD valid
tQVLD
−0.15 0.15 −0.15 0.15 −0.15 0.15 −0.20 0.20 −0.20 0.20 −0.20 0.20
ns
7
Output Times
Rev. 0.11 : 2013.01.15
R10DS0173EJ0011
PAGE:23
hinS=00000.0000.0000.0111.0111--00000.0000.0000.0111.0111--00000.0000.0000.0000.0000---RL=2.0
R1QHA72 / R1QLA72 Series
Parameter
Symbol
-19
-20
-22
-25
-27
-30
Min Max Min Max Min Max Min Max Min Max Min Max
Unit Notes
Setup Times
tAVKH
Address valid to
K rising edge
(QDRII+ B2)
tAVKH
(QDRII+ B4 & DDRII+)
Control inputs
valid to
K rising edge
tIVKH
(QDRII+ B2)
tIVKH
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
0.30
⎯
0.33
⎯
0.40
⎯
0.40
⎯
0.40
⎯
0.40
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
0.30
⎯
0.33
⎯
0.40
⎯
0.40
⎯
0.40
⎯
0.40
⎯
tDVKH
0.20
⎯
0.22
⎯
0.25
⎯
0.28
⎯
0.28
⎯
0.28
⎯
tKHAX
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
0.30
⎯
0.33
⎯
0.40
⎯
0.40
⎯
0.40
⎯
0.40
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
(QDRII+ B4 & DDRII+)
Data-in valid to
K, /K rising edge
⎯
ns
1, 8
ns
1, 8
ns
1, 9
ns
1, 8
ns
1, 8
ns
1, 9
Hold Times
K rising edge
to address hold
(QDRII+ B2)
tKHAX
(QDRII+ B4 & DDRII+)
K rising edge
to control inputs
hold
tKHIX
(QDRII+ B2)
tKHIX
(QDRII+ B4 & DDRII+)
K, /K rising edge
to data-in hold
tKHDX
0.30
⎯
0.33
⎯
0.40
⎯
0.40
⎯
0.40
⎯
0.40
⎯
0.20
⎯
0.22
⎯
0.25
⎯
0.28
⎯
0.28
⎯
0.28
⎯
Notes:
1. This is a synchronous device. All addresses, data and control lines must meet the specified setup and
hold times for all latching clock edges.
2. VDD and VDDQ slew rate must be less than 0.1 V DC per 50 ns for DLL/PLL lock retention. DLL/PLL lock
time begins once VDD , VDDQ and input clock are stable.
It is recommended that the device is kept inactive during these cycles.
This specification meets the QDR common spec. of 20 us.
3. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
4. Echo clock is very tightly controlled to data valid / data hold. By design, there is a ±0.1 ns variation from
echo clock to data. The datasheet parameters reflect tester guardbands and test setup variations.
5. Transitions are measured ±100 mV from steady-state voltage.
6. At any given voltage and temperature tCHQZ is less than tCHQX1 and tCHQV.
7. These parameters are sampled.
8. tAVKH, tIVKH, tKHAX, tKHIX spec is determined by the actual frequency regardless of Part Number (Marking
Name). The following is the spec for the actual frequency.
0.30 ns for ”533MHz & >500MHz
0.33 ns for ”500MHz & >450MHz
0.40 ns for ”450MHz & •250MHz
9. tDVKH, tKHDX spec is determined by the actual frequency regardless of Part Number (Marking Name). The
following is the spec for the actual frequency.
0.20 ns for ”533MHz & >500MHz
0.22 ns for ”500MHz & >450MHz
0.25 ns for ”450MHz & >400MHz
0.28 ns for ”400MHz & •250MHz
Remarks:
1. Test conditions as specified with the output loading as shown in AC Test Conditions unless otherwise
noted.
2. Control input signals may not be operated with pulse widths less than tKHKL (min).
3. VDDQ is +1.5 V DC. VREF is +0.75 V DC.
4. Control signals are /R, /W (QDR series), /LD, R-/W (DDR series), /BW, /BW0, /BW1, /BW2 and /BW3.
Setup and hold times of /BWx signals must be the same as those of Data-in signals.
Rev. 0.11 : 2013.01.15
R10DS0173EJ0011
PAGE:24
Rev. 0.11 : 2013.01.15
R10DS0173EJ0011
tAVKH
tIVKH
tKHKH
/K
K
NOP
3
READ
4
READ
5
READ
A0
tCHQZ
NOP
A3
01
1x
tKH/KH t/KHKH
6
1x
7
NOP
tCHCQV
-tCHCQX
tCHQV
-tCHQX
tCHCQV
-tCHCQX
tCHQV
-tCHQX
8
WRITE
9
WRITE
10
WRITE
11
WRITE
12
READ
13
READ
A4
tQVLD
-tQVLD
tCQHQV
-tCQHQX
A6
00
A7
00
A8
01
tKHDX
tDVKH
tKHDX
tDVKH
D40 D41 D50 D51 D60 D61 D70 D71
A5
00
A9
01
(burst of 2) (burst of 2) (burst of 2) (burst of 2) (burst of 2) (burst of 2)
00
Q00 Q01 Q10 Q11 Q20 Q21 Q30 Q31
A2
01
tQVLD
-tQVLD
-tCHQX1
A1
tKHAX
tKHIX
01
tKHKL tKLKH
(burst of 2) (burst of 2) (burst of 2) (burst of 2)
READ
Timing Waveforms (DDRII+, B2, Read Latency = 2.0 cycle)
Notes:
1. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, etc.
2. Outputs are disabled (high-Z) N clock cycle after the last read cycle. Here, N = Read Latency + Burst Length × 0.5.
3. In this example, if address A8 = A7, then data Q80 = D70, Q81 = D71, etc. Write data is forwarded immediately as read results.
4. To control read and write operations, /BW signals must operate at the same timing as Data-in signals.
5. The second NOP cycle is not necessary for correct device operation; however, at high clock frequencies it may be required to prevent bus contention.
QVLD
/CQ
CQ
DQ
2
01
Qx2 Qx0 Qx1
SA
/LD:R-/W
K, /K
1
hinS=00000.0000.0000.0010.0010--00000.0000.0000.0010.0010---00000.0000.0000.0010.0010--R1QB_RL=2.0
R
R1QHA72 / R1QLA72 Series
PAGE:25
Common
R1QHA72 / R1QLA72 Series
JTAG Specification
These products support a limited set of JTAG functions as in IEEE standard 1149.1.
Disabling the Test Access Port
It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfering with
normal operation of the device, TCK must be tied to VSS to preclude mid level inputs.
TDI and TMS are internally pulled up and may be unconnected, or may be connected to VDD through a pull up
resistor.
TDO should be left unconnected.
Test Access Port (TAP) Pins
Symbol I/O Pin assignments Description
TCK
2R
Test clock input. All inputs are captured on the rising edge of
TCK and all outputs propagate from the falling edge of TCK.
TMS
10R
Test mode select. This is the command input for the TAP
controller state machine.
TDI
11R
Test data input. This is the input side of the serial registers
placed between TDI and TDO. The register placed between
TDI and TDO is determined by the state of the TAP controller
state machine and the instruction that is currently loaded in
the TAP instruction.
TDO
1R
Test data output. Output changes in response to the falling
edge of TCK. This is the output side of the serial registers
placed between TDI and TDO.
Notes
Notes:
The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while
TMS is held high for five rising edges of TCK. The TAP controller state is also reset on SRAM
POWER-UP.
Rev. 0.11 : 2013.01.15
R10DS0173EJ0011
PAGE:26
Common
R1QHA72 / R1QLA72 Series
TAP DC Operating Characteristics
(Ta = 0 ~ +70°C @ R1Q*A*****BB-**R** series)
(Ta = -40 ~ +85°C @ R1Q*A*****BB-**I** series)
(VDD = 1.8V ±0.1V)
Parameter
Symbol
Min
Typ
Max
Unit
Input high voltage
VIH
+1.3
⎯
VDD + 0.3
V
Input low voltage
VIL
−0.3
⎯
+0.5
V
Input leakage current
ILI
−5.0
⎯
+5.0
μA
0 V ≤ VIN ≤ VDD
Output leakage current
ILO
−5.0
⎯
+5.0
μA
0 V ≤ VIN ≤ VDD,
output disabled
VOL1
⎯
⎯
0.2
V
IOLC = 100 μA
VOL2
⎯
⎯
0.4
V
IOLT = 2 mA
VOH1
1.6
⎯
⎯
V
|IOHC| = 100 μA
VOH2
1.4
⎯
⎯
V
|IOHT| = 2 mA
Output low voltage
Output high voltage
Notes
Notes:
1. All voltages referenced to VSS (GND).
2. At power-up, VDD and VDDQ are assumed to be a linear ramp from 0V to VDD(min.) or
VDDQ(min.) within 200ms. During this time VDDQ < VDD and VIH < VDDQ.
During normal operation, VDDQ must not exceed VDD.
Rev. 0.11 : 2013.01.15
R10DS0173EJ0011
PAGE:27
Common
R1QHA72 / R1QLA72 Series
TAP AC Test Conditions
Parameter
Symbol
Conditions
Unit
Input timing measurement reference levels
VREF
0.9
V
Input pulse levels
VIL, VIH
0 to 1.8
V
Input rise/fall time
tr, tf
≤ 1.0
ns
0.9
V
Test load termination supply voltage (VTT)
0.9
V
Output load
See figures
Output timing measurement reference levels
Notes
Input waveform
1.8V
0.9V
Test points
0.9V
0.9V
Test points
0.9V
0V
Output waveform
Output load condition
VTT = 0.9V
DUT
50Ω
TDO
Z0 = 50Ω
20pF
External Load at Test
Rev. 0.11 : 2013.01.15
R10DS0173EJ0011
PAGE:28
Common
R1QHA72 / R1QLA72 Series
TAP AC Operating Characteristics
(Ta = 0 ~ +70°C @ R1Q*A*****BB-**R** series)
(Ta = -40 ~ +85°C @ R1Q*A*****BB-**I** series)
(VDD = 1.8V ±0.1V)
Parameter
Symbol
Min
Typ
Max
Unit
Test clock (TCK) cycle time
tTHTH
50
⎯
⎯
ns
TCK high pulse width
tTHTL
20
⎯
⎯
ns
TCK low pulse width
tTLTH
20
⎯
⎯
ns
Test mode select (TMS) setup
tMVTH
5
⎯
⎯
ns
Notes
TMS hold
tTHMX
5
⎯
⎯
ns
Capture setup
tCS
5
⎯
⎯
ns
1
Capture hold
tCH
5
⎯
⎯
ns
1
TDI valid to TCK high
tDVTH
5
⎯
⎯
ns
TCK high to TDI invalid
tTHDX
5
⎯
⎯
ns
TCK low to TDO unknown
tTLQX
0
⎯
⎯
ns
TCK low to TDO valid
tTLQV
⎯
⎯
10
ns
Notes:
1. tCS + tCH defines the minimum pause in RAM I/O pad transitions to assure pad data capture.
Rev. 0.11 : 2013.01.15
R10DS0173EJ0011
PAGE:29
Common
R1QHA72 / R1QLA72 Series
TAP Controller Timing Diagram
tTHTH
tTHTL
tTLTH
TCK
tMVTH
tTHMX
TMS
tDVTH
tTHDX
TDI
tTLQV
TDO
tTLQX
tCS
tCH
PI
(SRAM)
Test Access Port Registers
Register name
Length
Symbol
Instruction register
3 bits
IR [2:0]
Bypass register
1 bit
BP
ID register
32 bits
ID [31:0]
Boundary scan register
109 bits
BS [109:1]
Rev. 0.11 : 2013.01.15
R10DS0173EJ0011
Notes
PAGE:30
Common
R1QHA72 / R1QLA72 Series
TAP Controller Instruction Set
IR2 IR1 IR0 Instruction
0
0
0
0
Description
Notes
0 EXTEST
The EXTEST instruction allows circuitry external to the
component package to be tested. Boundary scan register cells
at output balls are used to apply test vectors, while those at
input balls capture test results. Typically, the first test vector to
1, 2, 3, 5
be applied using the EXTEST instruction will be shifted into the
boundary scan register using the PRELOAD instruction. Thus,
during the Update-IR state of EXTEST, the output driver is
turned on and the PRELOAD data is driven onto the output balls.
1 IDCODE
The IDCODE instruction causes the ID ROM to be loaded into
the ID register when the controller is in capture-DR mode and
places the ID register between the TDI and TDO balls in shiftDR mode. The IDCODE instruction is the default instruction
loaded in at power up and any time the controller is placed in
the Test-Logic-Reset state.
0
1
0 SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register,
all RAM outputs are forced to an inactive drive state (high-Z),
moving the TAP controller into the capture-DR state loads the
3, 4, 5
data in the RAMs input into the boundary scan register, and the
boundary scan register is connected between TDI and TDO
when the TAP controller is moved to the shift-DR state.
0
1
1 RESERVED
The RESERVED instructions are not implemented but are
reserved for future use. Do not use these instructions.
1
0
When the SAMPLE instruction is loaded in the instruction
register, moving the TAP controller into the capture-DR state
loads the data in the RAMs input and I/O buffers into the
boundary scan register. Because the RAM clock(s) are
independent from the TAP clock (TCK) it is possible for the TAP
SAMPLE
0
to attempt to capture the I/O ring contents while the input
3, 5
(/PRELOAD)
buffers are in transition (i.e., in a metastable state). Although
allowing the TAP to SAMPLE metastable input will not harm the
device, repeatable results cannot be expected. Moving the
controller to shift-DR state then places the boundary scan
register between the TDI and TDO balls.
1
0
1 RESERVED
-
1
1
0 RESERVED
-
1
1
1 BYPASS
The BYPASS instruction is loaded in the instruction register
when the bypass register is placed between TDI and TDO. This
occurs when the TAP controller is moved to the shift-DR state.
This allows the board level scan path to be shortened to
facilitate testing of other devices in the scan path.
Notes:
1. Data in output register is not guaranteed if EXTEST instruction is loaded.
2. After performing EXTEST, power-up conditions are required in order to return part to normal
operation.
3. RAM input signals must be stabilized for long enough to meet the TAPs input data capture
setup plus hold time (tCS plus tCH). The RAMs clock inputs need not be paused for any other
TAP operation except capturing the I/O ring contents into the boundary scan register.
4. Clock recovery initialization cycles are required after boundary scan.
5. For R1QD, R1QE, R1QF, R1QK, R1QL, R1QM, R1QP series, ODT is disabled in EXTEST,
SAMPLE-Z or SAMPLE mode.
Rev. 0.11 : 2013.01.15
R10DS0173EJ0011
PAGE:31
R1QHA72 / R1QLA72 Series
Boundary Scan Order
Signal names
Bit # Ball ID
x9
x18
x36
Bit # Ball ID
Signal names
x9
x18
x36
1
6R
/C or NC
or ODT
/C or NC
or ODT
/C or NC
or ODT
36
10E
NC
NC
DQ15
2
6P
C
or QVLD
C
or QVLD
C
or QVLD
37
10D
NC
NC
NC
3
6N
SA
SA
SA
38
9E
NC
NC
NC
4
7P
SA
SA
SA
39
10C
NC
DQ7
DQ17
5
7N
SA
SA
SA
40
11D
NC
NC
DQ16
6
7R
SA
SA
SA
41
9C
NC
NC
NC
7
8R
SA
SA
SA
42
9D
NC
NC
NC
8
8P
SA
SA
SA
43
11B
DQ4
DQ8
DQ8
9
9R
SA
SA
SA
44
11C
NC
NC
DQ7
10
11P
DQ0
DQ0
DQ0
45
9B
NC
NC
NC
11
10P
NC
NC
DQ9
46
10B
NC
NC
NC
12
10N
NC
NC
NC
47
11A
CQ
CQ
CQ
13
9P
NC
NC
NC
48
10A
SA
SA
SA
14
10M
NC
DQ1
DQ11
49
9A
SA
SA
SA
15
11N
NC
NC
DQ10
50
8B
SA
SA
SA
16
9M
NC
NC
NC
51
7C
SA
SA
SA
17
9N
NC
NC
NC
52
6C
SA
18
11L
DQ1
DQ2
DQ2
53
8A
/LD
/LD
/LD
19
11M
NC
NC
DQ1
54
7A
NC
NC
/BW1
20
9L
NC
NC
NC
55
7B
/BW
/BW0
/BW0
21
10L
NC
NC
NC
56
6B
K
K
K
22
11K
NC
DQ3
DQ3
57
6A
/K
/K
/K
23
10K
NC
NC
DQ12
58
5B
NC
NC
/BW3
24
9J
NC
NC
NC
59
5A
NC
/BW1
/BW2
25
9K
NC
NC
NC
60
4A
R-/W
R-/W
R-/W
26
10J
DQ2
DQ4
DQ13
61
5C
SA
SA
SA
27
11J
NC
NC
DQ4
62
4B
SA
SA
SA
28
11H
ZQ
ZQ
ZQ
63
3A
SA
SA
SA
29
10G
NC
NC
NC
64
2A
SA
SA
NC
30
9G
NC
NC
NC
65
1A
/CQ
/CQ
/CQ
31
11F
NC
DQ5
DQ5
66
2B
NC
DQ9
DQ27
32
11G
NC
NC
DQ14
67
3B
NC
NC
DQ18
33
9F
NC
NC
NC
68
1C
NC
NC
NC
34
10F
NC
NC
NC
69
1B
NC
NC
NC
35
11E
DQ3
DQ6
DQ6
70
3D
NC
DQ10
DQ19
Rev. 0.11 : 2013.01.15
R10DS0173EJ0011
SA0 or NC SA0 or NC
PAGE:32
R1QHA72 / R1QLA72 Series
Boundary Scan Order
Bit # Ball ID
Signal names
x9
x18
NC
NC
NC
NC
NC
NC
DQ5
DQ11
NC
NC
NC
NC
NC
NC
NC
DQ12
NC
NC
NC
NC
NC
NC
DQ6
DQ13
NC
NC
/DOFF
/DOFF
NC
NC
NC
NC
NC
DQ14
NC
NC
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
3C
1D
2C
3E
2D
2E
1E
2F
3F
1G
1F
3G
2G
1H
1J
2J
3K
3J
89
2K
NC
NC
90
1K
NC
NC
x36
DQ28
NC
NC
DQ20
DQ29
NC
NC
DQ30
DQ21
NC
NC
DQ22
DQ31
/DOFF
NC
NC
DQ23
DQ32
Bit # Ball ID
Signal names
x9
x18
DQ7
DQ15
NC
NC
NC
NC
NC
NC
NC
DQ16
NC
NC
NC
NC
NC
NC
DQ8
DQ17
NC
NC
NC
NC
NC
NC
SA
SA
SA
SA
SA
SA
SA
SA
SA
SA
SA
SA
x36
DQ33
DQ24
NC
NC
DQ25
DQ34
NC
NC
DQ26
DQ35
NC
NC
SA
SA
SA
SA
SA
SA
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
2L
3L
1M
1L
3N
3M
1N
2M
3P
2N
2P
1P
3R
4R
4P
5P
5N
5R
NC
109
⎯
INTERNAL
INTERNAL
INTERNAL
NC
⎯
⎯
⎯
⎯
⎯
Notes:
In boundary scan mode,
1. Clock balls (K, /K, C, /C) are referenced to each other and must be at opposite logic levels for
reliable operation.
2. CQ and /CQ data are synchronized to the respective C and /C (except EXTEST, SAMPLE-Z).
3. If C and /C tied high, CQ is generated with respect to K and /CQ is generated with respect to /K
(except EXTEST, SAMPLE-Z).
Rev. 0.11 : 2013.01.15
R10DS0173EJ0011
PAGE:33
Common
R1QHA72 / R1QLA72 Series
ID Register
#
Symbol
Revision
Type number
Start bit (0) ă Ň
Vendor JEDEC code
number
(28 : 12)
䊼
(31 :29)
(11 : 1)
䊼
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R R 0 C M M M A W W 0 1 Q Q Q B O S 0 0 1 0 0 0 1 0 0 0 1 1 1
R R R
0 0 0
0 0 1
0 1 0
0 1 1
:
Q
Revison 0
II (QDR-II, DDR-II)
0
Revison 1
II+ (QDR-II+, DDR-II+)
1
Revison 2
Q
DDR
Revison 3
0
:
QDR
1
C
Q
Latency=1.5 (@II), Latency=2.0 (@II+)
0 36M&72M w/o ODT, 144M,288M
0
Latency=2.5 (@II+)
1 36M&72M w/ ODT
1
M M M
B
Burst Length = 2 word burst
Density = 36Mb
0 1 0
0
Burst Length = 4 word burst
Density = 72Mb
0 1 1
1
Density = 144Mb
1 0 1
O
Density = 288Mb
without ODT
1 1 0
0
with ODT
A
1
0 144M&288M w/o ODT, 36M,72M S
Common I/O
1 144M&288M w/ ODT
0
Separate I/O
W W
1
x9
0 0
x18
1 0
x36
1 1
TAP Controller State Diagram
1
Test Logic Reset
0
Run Test/Idle
0
1
1
Select DR Scan
1
0
1
Capture DR
Capture IR
1
Exit1 DR
Shift IR
1
1
Exit1 IR
0
0
Exit2 DR
Pause IR
0
1
Exit2 IR
1
1
Update DR
1
1
0
0
Pause DR
1
0
0
Shift DR
0
0
0
0
1
Select IR Scan
0
Update IR
1
0
Notes:
The value adjacent to each state transition in this figure represents the signal present at TMS at
the time of a rising edge at TCK.
No matter what the original state of the controller, it will enter Test-Logic-Reset when TMS is held
high for at least five rising edges of TCK.
Rev. 0.11 : 2013.01.15
R10DS0173EJ0011
PAGE:34
hinS=11111.1111.1111.1111.1111--11111.1111.1111.1111.1111--00000.0000.0000.0000.0000---72M_36M
R1QHA72 / R1QLA72 Series
Package Dimensions and Marking Information
Both Pb parts and Pb-free parts are available.
JEITA Package Code
P-LBGA165-13x15-1.00
Renesas Code
PLBG0165FE-A
Previous Code
165FHG
D
A
Mass (typ.)
0.5g
B
Top View
R1QHA7218ABB-25R
YWWXXXX
JAPAN
PB-F
Index Mark
(Laser Mark)
This part
number or
mark is just
one example.
Marking Information
1st row : Vender name (RENESAS)
2nd row: Part number
3rd row : Y
: Year code
WW
: Week code
E
XXXX : Renesas
internal use
4th row : Country name (JAPAN)
+ "None" --- Pb-free parts
+ "PB-F" --- Pb-free parts
S
A
Side View
A1
- y S
ZD
[e]
R
Bottom View
C
D
E
F
G
H
J
K
L
M
N
P
[e]
A
B
ZE
1
2
3
4
5
6
Øb
Index Mark
Rev. 0.11 : 2013.01.15
R10DS0173EJ0011
7
8
9 10 11
- Øx(M) S AB
Reference
Symbol
D
E
A
A1
[e]
b
x
y
ZD
ZE
Dimension in mm
Min Nom Max
12.9 13.0 13.1
14.9 15.0 15.1
1.4
0.31 0.36 0.41
1.0
0.45 0.5 0.6
0.2
0.15
2.5
-
1.5
-
PAGE:35
hinS=00000.0010.0010.0010.0010--00000.0000.0000.0000.0000--00000.0000.0000.0000.0000---72M_DDRII+_B2
R1QHA72 / R1QLA72 Series
Appendix
Example of DC/AC characteristics data
Parts Number : R1QBA7236RBG-19R
IDD (Operating supply current) - tKHKH (Ta=70 degC)
ᵏᵐᵎᵎ
ᵱᵮᵣᵡ
ᵧᶂᶂᴾᵆᶋᵟᵇ
ᵏᵎᵎᵎ
ᵫᶃᵿᶑᶓᶐᶃᶂᴾᶂᵿᶒᵿ
ᵴᶂᶂᵛᵏᵌᵕᵴ
ᵖᵎᵎ
ᵴᶂᶂᵛᵏᵌᵖᵴ
ᵴᶂᶂᵛᵏᵌᵗᵴ
ᵔᵎᵎ
ᵏᵌᵓ
ᵐᵌᵎ
ᵐᵌᵓ
ᵑᵌᵎ
ᶒᵩᵦᵩᵦᴾᵆᶌᶑᵇ
tKHKH (Clock cycle time) Shmoo (Ta=70 degC)
Vdd
8QNVCIG
8
8
8
8
8
8
8
8
8
6+/'
05
05
05
05
05
05
222222222222222222222222222222222222222222222
222222222222222222222222222222222222222222222
2 2 2 2 2 222 2 222 2 222 2 222 2 222 2 222 2 222 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 222 2 222 2 222 2 222 2 222 2 222 2 222 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 222 2 222 2 222 2 222 2 222 2 222 2 222 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 222 2 222 2 222 2 222 2 222 2 222 2 222 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 222 2 222 2 222 2 222 2 222 2 222 2 222 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 222222222222222222222222222222222222222222222
222222222222222222222222222222222222222222222
05
05
05
05
05
05
2 2CUU
52'%
tKHKH
tCHQV (K, /K high to output valid) Shmoo (Ta=70 degC)
Vdd
8QNVCIG
8
8
8
8
8
8
8
8
8
6+/'
25
25
25
25
25
25
2222222222222222222222222222222
2222222222222222222222222222222
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 222 2 222 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 222 2 222 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 222 2 222 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 222 2 222 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 222 2 222 2 2 2222222222222222222222222222222
2222222222222222222222222222222
25
25
25
25
25
25
2 2CUU
52'%
tCHQV
Rev. 0.11 : 2013.01.15
R10DS0173EJ0011
PAGE:36
hinS=11111.1111.1111.1111.1111--11111.1111.1111.1111.1111--00000.0000.0000.0000.0000---72M_36M
R1QHA72 / R1QLA72 Series
Revision History (1)
4GX
&CVG
4GXC 4GXD
Revision
History
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4GXJ 4GXK 4GXC 4GXC 4GXC 4GXC 4GXC 4GXD 4GXE 4GXC 4GXC 4GXD Rev. 0.11 : 2013.01.15
R10DS0173EJ0011
PAGE:37
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R1QHA72 / R1QLA72 Series
Revision History (2)
Rev. 0.11 : 2013.01.15
R10DS0173EJ0011
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Common
Renesas Electronics Corporation
Headquarters: Nippon Bldg., 2-6-2, Ote-machi, Chiyoda-ku, Tokyo 100-0004, Japan
NOTES:
1.
This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither
makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any
intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document.
2.
Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document,
including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples.
3.
You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass
destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export
control laws and regulations, and procedures required by such laws and regulations.
4.
All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date
this document is issued. Such information, however,is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this
document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different
information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com )
5.
Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred
as a result of errors or omissions in the information included in this document.
6.
When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the
applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for
any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products.
7.
The products described in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring
equipment, industrial robotics, domestic appliances, etc.). The products are not designed, manufactured, tested or warranted for applications or otherwise in
systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and
reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power,
or undersea communication transmission. Unintended usage of the products shall be made at the customer’s own risk. Renesas shall have no liability for
damages arising out of the uses set forth above.
8.
Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing
applications shall indemnify and hold harmless Renesas Electronics Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range,
movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or
damages arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a
certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and
injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the
evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such
as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your
products. Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you
have any other inquiries.
Renesas Sales Offices
http://www.renesas.com
Refer to "http://www.renesas.com/" for the latest and detailed information.
Renesas Electronics America Inc.
2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A.
Tel: +1-408-588-6000, Fax: +1-408-588-6130
Renesas Electronics Canada Limited
1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada
Tel: +1-905-898-5441, Fax: +1-905-898-3220
Renesas Electronics Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire,
SL8 5FH, U.K
Tel: +44-1628-585-100, Fax: +44-1628-585-900
Renesas Electronics Europe GmbH
Arcadiastrasse 10, 40472 Düsseldorf, Germany
Tel: +49-211-6503-0, Fax: +49-211-6503-1327
Renesas Electronics (China) Co., Ltd.
7th Floor, Quantum Plaza, No.27 ZhiChunLu Haidian District,
Beijing 100083, P.R.China
Tel: +86-10-8235-1155, Fax: +86-10-8235-7679
Renesas Electronics Hong Kong Limited
Unit 1601-1613, 16/F., Tower 2, Grand Century Place,
193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: +852-2886-9318, Fax: +852 2886-9022/9044
Renesas Electronics Taiwan Co., Ltd.
7F, No. 363 Fu Shing North Road Taipei, Taiwan, R.O.C.
Tel: +886-2-8175-9600, Fax: +886 2-8175-9670
Renesas Electronics Singapore Pte. Ltd.
1 harbourFront Avenue, #06-10, keppel Bay Tower, Singapore 098632
Tel: +65-6213-0200, Fax: +65-6278-8001
Renesas Electronics Malaysia Sdn.Bhd.
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18,
Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: +60-3-7955-9390, Fax: +60-3-7955-9510
Renesas Electronics Korea Co., Ltd.
11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku,
Seoul 135-080, Korea
Tel: +82-2-558-3737, Fax: +82-2-558-5141
Renesas Electronics (Shanghai) Co., Ltd.
Unit 204, 205, AZIA Center, No.1233 Lujiazui Ring Rd., Pudong District,
Shanghai 200120, China
Tel: +86-21-5877-1818, Fax: +86-21-6887-7858 / -7898
--© 2013 Renesas Electronics Corporation. All rights reserved.