TSD-1952

TABLE 1: ELECTRICAL SPECIFICATIONS AT 25 OC
PARAMETER
MIN.
FIGURE 1: SCHEMATIC DIAGRAM
SPEC LIMITS
TYP.
MAX.
UNITS
WHITE DOT
DENOTES PIN #1
TURNS RATIO:
SEC #1 (12-8) : PRI (6-4)
SEC #2 (11-7) : PRI (6-4)
BIAS (2-1) : PRI (6-4)
----------------------
1 : 19.2
1 : 19.2
1 : 8.73
----------------------
+2%
+2%
+2%
PRIMARY INDUCTANCE (6-4)
VOLTAGE = 0.250Vrms
FREQUENCY = 100.0 KHz
800
850
900
µHY
PRI LEAKAGE INDUCTANCE (6-4)
VOLTAGE = 0.250Vrms
FREQUENCY = 100.0 KHz
-------
-------
TBD
µHY
2500
600
600
-------------------
-------------------
Vrms
Vrms
Vrms
12
1
BIAS
SEC #1
8
2
4
11
PRIMARY
HI-POT:
PRI & BIAS TO SECONDARIES
PRIMARY TO BIAS
BETWEEN SECONDARIES
SEC #2
6
7
MINIMUM INSULATION SYSTEM REQUIREMENTS:
1) ALL MATERIALS TO MEET UL, CSA & IEC REQUIREMENTS
2) ALL MATERIALS ARE RATED 130OC OR BETTER.
3) VARNISHED
FIGURE 2: PHYSICAL DIMENSIONS MM (inches)
12 11 10
9
8
FIGURE 3: RECOMMENDED PCB LAYOUT
DIMENSION IN MM, (inches)
7
24.8 (.976)
12x1.5 (.060)
1
12
5x2.5 (.100)
12x0.8 (.031)
PIN#1 I.D.
ON BOBBIN
1
2
3
4
5
20.5
(.807)
MAX
0.7
(.028)
20.6
(.811)
MAX
CORE
TAPE
TSD-1952
YYWW
1
TRIM/REMOVE PIN #3, #9, #10
6
6
7
10.5
(.413)
MAX
6
2.5
(.098)
0.13
(.005)
6
21.7
(.854)
25.0
(.984)
7
0.4
(.016)
UNLESS OTHERWISE SPECIFIED
DIMENSIONS ARE IN MM
DIMENSIONAL TOLERANCES ARE:
DECIMALS
ANGLES
.X
+ 0.5
+0 O 30'
.XX + 0.25
DO NOT SCALE DRAWING
REV.
01308/04
DESCRIPTION OF CHANGES
ORIGINAL RELEASE
FLYBACK TRANSFOMER CONTROL DRAWING
PREMIER P/N: TSD-1952
REVISION: 01/30/04
DRAWN BY: PETER PHAM
REF: TOP-202
SCALE: NONE
SHEET: 1 OF 2
BY
PP