RAiO RA8875

RAiO
RA8875
Character/Graphic
TFT LCD Controller
Specification
Version 1.2
January 10, 2012
RAiO Technology Inc.
©Copyright RAiO Technology Inc. 2011, 2012
RAiO TECHNOLOGY INC.
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
Update History
Version
1.0
1.1
Date
May 10, 2011
Preliminary Version
June 15, 2011
Remove Serial Flash Address 32 bit Mode
1. Modify REG[05h]
2. Remove REG [B3h]
3. Modify REG[E1h]
4. Modify Section 7-10-1 : DMA In Continuous Mode
5. Modify Section 7-10-2 : DMA In Block Mode
June 27, 2011
1. Modify REG[16h]、REG[89h] 、REG[F0h]
October 4, 2011
1.2
Description
1. Modify Figure 7-80、Figure 7-81
November 18, 2011
1. Modify Section 7-4-2
2. Modify Table 8-2
November 29, 2011
1. Add Figure 7-82
2. Modify Figure 6-41
January 10, 2012
RAiO TECHNOLOGY INC.
1. Modify Section 7-6 BTE Function
(Parallel MCU interface only)
2/175
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RA8875
Version 1.2
Chapter
Character / Graphic TFT LCD Controller
Contents
Page
1. Description................................................................................................ 7
2. Features .................................................................................................... 7
3. Block Diagram .......................................................................................... 8
3-1
3-2
Block Diagram .................................................................................................... 8
System Block Diagram....................................................................................... 8
4. Pin Description ......................................................................................... 9
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
MCU Interface ..................................................................................................... 9
Serial MCU Interface......................................................................................... 10
LCD Panel Interface.......................................................................................... 10
Serial Flash/ROM Interface .............................................................................. 11
Touch Interface................................................................................................. 11
KEYSCAN Interface .......................................................................................... 11
PWM Interface................................................................................................... 12
Clock and Power Interface............................................................................... 12
5. Register ................................................................................................... 13
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
5-15
5-16
Status Register ................................................................................................. 14
System & Configuration Registers ................................................................. 14
LCD Display Control Registers ....................................................................... 19
Active Window & Scroll Window Setting Registers ...................................... 24
Cursor Setting Registers ................................................................................. 27
Block Transfer Engine(BTE) Control Registers ............................................. 30
Touch Panel Control Registers ....................................................................... 36
Graphic Cursor Setting Registers................................................................... 38
PLL Setting Registers ...................................................................................... 39
PWM Control Registers.................................................................................... 40
Drawing Control Registers .............................................................................. 42
DMA Registers .................................................................................................. 47
Key & IO Control Registers.............................................................................. 50
Floating Window Control Registers................................................................ 51
Serial Flash Control Registers ........................................................................ 53
Interrupt Control Registers.............................................................................. 54
6. Hardware Interface ................................................................................. 56
6-1
MCU Interface ................................................................................................... 56
6-1-1 Protocol ................................................................................................................................ 57
6-1-1-1 Parallel I/F Protocol ....................................................................................................57
6-1-2 Serial I/F Protocol ................................................................................................................ 60
6-1-2-1 3-Wire SPI Interface ...................................................................................................60
6-1-2-2 4-Wire SPI Interface ...................................................................................................63
6-1-2-3 IIC I/F .......................................................................................................................... 65
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
6-1-3 Read Status Register ..........................................................................................................68
6-1-4 Write Command to Register ...............................................................................................69
6-1-5 Memory Read / Write Operation .........................................................................................70
6-1-6 Interrupt and Wait................................................................................................................ 71
6-1-6-1 Interrupt ......................................................................................................................71
6-1-6-2 Wait............................................................................................................................. 72
6-1-7 Data Format.......................................................................................................................... 73
6-1-7-1 MCU Data Bus 16- Bit ................................................................................................ 73
6-1-7-2 MCU Data Bus 8-Bit ...................................................................................................74
Driver I/F Color Setting Mode .......................................................................... 75
LCD Interface .................................................................................................... 76
External Serial Flash/ROM ............................................................................... 78
6-2
6-3
6-4
6-4-1 External Serial Font ROM ...................................................................................................81
6-4-2 External Serial Data ROM ...................................................................................................82
6-5
6-6
6-7
6-8
6-9
6-10
Touch Panel I/F ................................................................................................. 83
KEYSCAN .......................................................................................................... 85
PWM................................................................................................................... 86
Clock and PLL................................................................................................... 87
Reset.................................................................................................................. 89
Power................................................................................................................. 91
6-10-1 Power Pin Description ........................................................................................................91
6-10-2 Power Architecture .............................................................................................................91
7. Function Description ............................................................................. 92
7-1
Scroll Function ................................................................................................. 92
7-1-1 Scroll Window & Scroll Offset............................................................................................92
7-1-2 Horizontal Scroll & Vertical Scroll ..................................................................................... 92
7-1-3 Layer Mixed Scroll ............................................................................................................... 93
7-1-3-1 Layer 1/2 Scroll Simultaneously .................................................................................94
7-1-3-2 Only Layer 1 Scroll .....................................................................................................94
7-1-3-3 Only Layer 2 Scroll .....................................................................................................95
7-1-3-4 Buffer Scroll (Layer 2 is used as Scroll Buffer)...........................................................96
7-2
Active Window .................................................................................................. 97
7-2-1
7-2-2
7-2-3
7-2-4
7-3
Active Window
Active Window
Active Window
Active Window
for Font Write ............................................................................................ 97
for Geometric Input ..................................................................................98
for DMA......................................................................................................98
for Memory Write ...................................................................................... 98
Cursor & Pattern............................................................................................... 99
7-3-1 Cursor Type.......................................................................................................................... 99
7-3-1-1 Graphic Cursor ...........................................................................................................99
7-3-1-2 Memory Read Cursor ...............................................................................................101
7-3-1-3 Memory Write Cursor ...............................................................................................101
7-3-1-4 Font Write Cursor .....................................................................................................102
7-3-2 Cursor Attribute................................................................................................................. 102
7-3-2-1 Cursor Blinking .........................................................................................................102
7-3-2-2 Cursor Height and Width ..........................................................................................103
7-3-3 Pattern ................................................................................................................................ 105
7-4
Font.................................................................................................................. 106
7-4-1 Internal Font ROM .............................................................................................................106
7-4-2 External Font ROM ............................................................................................................111
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RA8875
Version 1.2
7-4-3
7-4-4
7-4-5
7-4-6
7-4-7
7-5
CGRAM ............................................................................................................................... 112
90 Degree Font................................................................................................................... 114
Enlargement, Transparent Font .......................................................................................114
Font Change Line when Setting Write Auto Move .........................................................115
Font Full-Alignment...........................................................................................................115
Geometric Pattern Drawing Engine .............................................................. 116
7-5-1
7-5-2
7-5-3
7-5-4
7-5-5
7-5-6
7-5-7
7-6
Character / Graphic TFT LCD Controller
Circle Input ......................................................................................................................... 116
Ellipse Input ....................................................................................................................... 117
Curve Input......................................................................................................................... 118
Square Input....................................................................................................................... 119
Line Input............................................................................................................................ 120
Triangle Input ..................................................................................................................... 121
Square Of Circle Corner Input..........................................................................................122
BTE (Block Transfer Engine) Function (Parallel MCU Interface Only)....... 123
7-6-1 Select BTE Start Point Address and Layer .....................................................................126
7-6-2 BTE Operations .................................................................................................................126
7-6-2-1 Write BTE .................................................................................................................126
7-6-2-2 Read BTE .................................................................................................................126
7-6-2-3 Move BTE .................................................................................................................126
7-6-2-4 Solid Fill ....................................................................................................................126
7-6-2-5 Pattern Fill.................................................................................................................126
7-6-2-6 Transparent Pattern Fill ............................................................................................126
7-6-2-7 Transparent Write BTE.............................................................................................126
7-6-2-8 Transparent Move BTE ............................................................................................126
7-6-2-9 Color Expansion .......................................................................................................127
7-6-2-10 Move BTE with Color Expansion ..............................................................................127
7-6-3 BTE Access Memory Method ...........................................................................................128
7-6-3-1 Block Memory Access ..............................................................................................128
7-6-3-2 Linear Memory Access .............................................................................................128
7-6-4 BTE Function Explaination...............................................................................................129
7-6-4-1 Write BTE with ROP .................................................................................................129
7-6-4-2 Read BTE (Burst Read Like Function) .....................................................................131
7-6-4-3 Move BTE in Positive Direction with ROP ................................................................132
7-6-4-4 Move BTE in Negative Direction with ROP ..............................................................134
7-6-4-5 Transparent Write BTE.............................................................................................136
7-6-4-6 Transparent Move BTE Positive Direction ............................................................... 138
7-6-4-7 Pattern Fill with ROP ................................................................................................139
7-6-4-8 Pattern Fill with Transparency ..................................................................................141
7-6-4-9 Color Expansion .......................................................................................................143
7-6-4-10 Color Expansion with Transparency.........................................................................146
7-6-4-11 Move BTE with Color Expansion ..............................................................................148
7-6-4-12 Move BTE with Color Expansion and Transparency................................................150
7-6-4-13 Solid Fill ....................................................................................................................151
7-7
Layer Mixed Function..................................................................................... 152
7-7-1
7-7-2
7-7-3
7-7-4
7-7-5
7-7-6
7-7-7
7-8
Only Layer One is Visible .................................................................................................153
Only Layer Two is Visible .................................................................................................153
Lighten-Overlay Mode.......................................................................................................154
Transparent Mode .............................................................................................................155
Boolean OR ........................................................................................................................ 155
Boolean AND...................................................................................................................... 155
Floating Window................................................................................................................156
Touch Panel Function .................................................................................... 157
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
7-8-1 Touch Panel Operation Mode...........................................................................................158
7-8-1-1 Auto Mode ................................................................................................................158
7-8-1-2 Manual Mode ............................................................................................................159
7-8-2 Touch Event Detection Modes .........................................................................................160
7-8-2-1 External Interrupt Mode ............................................................................................160
7-8-2-2 Software Polling Mode..............................................................................................160
7-8-3 Touch Panel Sampling Time Reference Table ...............................................................161
7-9 KEYSCAN ........................................................................................................ 162
7-10 DMA (Direct Memory Access)........................................................................ 165
7-10-1 DMA In Continuous Mode.................................................................................................165
7-10-2 DMA In Block Mode ...........................................................................................................167
7-11 PWM................................................................................................................. 168
7-12 Sleep Mode...................................................................................................... 170
8. AC/DC Characteristic ........................................................................... 172
8-1
8-2
Maximum Absolute Limit ............................................................................... 172
DC Characteristic ........................................................................................... 173
9. Package................................................................................................. 174
9-1
9-2
9-3
Pin Assignment .............................................................................................. 174
Package Outline Dimensions ........................................................................ 175
Product Number ............................................................................................. 175
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
1. Description
RA8875 is a text/graphic mixed display with 2 layers TFT LCD controller. It is designed to meet the
requirement of middle size TFT module up to 800x480 pixels with characters or 2D graphic application.
Embedded 768KB display RAM provides user a flexible solution for display buffer of almost application.
Besides, the interface of external serial flash is optional to provide the font bitmap up to 32x32 pixels for
BIG5/GB/UNICODE coding, by connecting with the font ROM of Genitop Inc. For graphic usage,
RA8875 supports a 2D Block Transfer Engine(BTE) that is compatible with 2D BitBLT function for
processing the mass data transfer. The advanced geometric speed-up engine provides user an easy
way to draw the programmable geometric shapes by hardware, like line, square, circle and ellipse.
Besides, for different end-user applications, many powerful functions are integrated with RA8875, such
as scroll function, floating window display, graphic pattern and font enlargement function. These
functions will save user a large of software effort during development period.
RA8875 is a powerful and cheap choice for color display application. To reduce the system cost,
RA8875 provides low cost and easy-to-use 8080/6800 parallel MCU interface. Because of the powerful
hardware speed-up function embedded in it, less data transfer is needed so more efficiency is improved,
RA8875 also provides serial SPI/I2C I/F with ultra-low pin-count. Useful device controller, such as
flexible 4-wire touch panel controller, PWM for adjusting panel back-light are also included to reduce the
system cost for customer. With the RA8875 design-in, user can achieve an easy-to-use, low-cost and
high performance system comparing with the other solution.
2. Features
‹
‹
‹
‹
‹
‹
‹
‹
‹
‹
‹
Support Text/Graphic Mixed Display Mode.
Embedded 768KB DDRAM.
Color Depth TFT: 256/65K Colors.
Supporting TFT 8/16 bpp Generic RGB
Interface.
Supporting TFT Panel Size:
„ 800x480 Pixels 2 Layers @ 256 Colors.
„ 800x480 Pixels 1 Layer @ 64K Colors.
„ 480x272 Pixels 2 Layers @ 64K Colors.
Supporting MCU Interface :
„ 8080/6800 with 8/16 Data Bus Width
„ I2C or 3/4-wire SPI I/F.
Powerful Block Scrolling Function for Vertical
or Horizontal Direction.
Embedded 10KB Character ROM with Font
Size 8x16 Dots and Supporting Character
Sets of ISO/IEC 8859-1/2/3/4.
External Serial Flash/ROM SPI I/F
Supporting.
Supporting Genitop Inc. UNICODE/BIG5/GB
Serial font ROM with 16x16/24x24/32X32
dots Font Size.
Font Enlargement Function X1, X2, X3, X4
for Horizontal/Vertical Direction.
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‹ Font Vertical Rotation Mode Function.
‹ Block Transfer Engine (BTE) Supports with 2D
Function, Compatible with 2D BitBLT Function.
‹ Embedded Geometric Speed-up Engine.
‹ Programmable Font Write Cursor for Writing
with Character.
‹ 32x32 pixels Graphic Cursor Function.
‹ User-defined Characters.
„ 256 Characters with 8x16 dots.
‹ Supporting 16 User-defined Patterns of 8x8
pixels, or 4 User-defined Pattern for 16x16
pixels.
‹ Two Programmable PWM for Back-Light
Adjusting or other's Application.
‹ Embedded 4-wire Touch Panel Controller.
‹ Sleep Mode with Low Power Consumption.
‹ Embedded Smart 4x5 Key-Scan Controller.
‹ 4 Sets of Programmable GPO and a fixed
GPOX.
‹ 5 Sets of Programmable GPI and a fixed GPIX
‹ Clock Source : Embedded Crystal Oscillator
Circuit with Programmable PLL.
‹ Operation Voltage: 3.0V~3.6V.
‹ Package: LQFP-100pin.
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
3. Block Diagram
3-1 Block Diagram
DB[15:0]
RD#/EN#
WR#/RW#
CS#
RS
C86
WAIT#
INT#
SCL
SDI
SDO
SCS#
SIFS0
SIFS1
IICA[1:0]
KOUT [3:0]/ GPO [3:0]
KIN [4:0]/ GPI [4:0]
GPOX
GPIX
MPU I/F
Block
I2C/SPI
KEYSCAN
Controller
Register
Block
DDRAM
Geometric
Speed-up
Engine
Generic
TFT
driver I/F
FONT
Engine
Serial
Flash/ROM
IF
ADC
2D-BTE
Engine
CGROM
4 wires
Touch Panel
Controller
PLL
XI
XO
TEST[2:0]
OSC
TEST
Circuit
Pattern/
Cursor
Scroll
Engine
PDAT[15:0]
HSYNC
VSYNC
PCLK
DE
SFCL
SFDI
SFDO
SFCS0#
SFCS1#
XP
XN
YP
YN
ADC_VREF
PWM
PWM1
PWM2
RESET
Control
RST#
Figure 3-1 : RA8875 Block Diagram
3-2 System Block Diagram
SPI
/I2C
Serial
Flash
8/16 bits
MPU
TFT LCD
Module
RA8875
4 wires
Touch
Panel
KEYPAD
/GPIO
PWM
Figure 3-2 : RA8875 System Block Diagram
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
4. Pin Description
4-1 MCU Interface
Pin Name
I/O
DB[15:0]
IO
RD#
(EN)
I
WR#
(RW#)
I
CS#
I
RS
I
C86
I
PS
I
INT#
O
WAIT#
O
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Pin Description
Data Bus
These are data bus for data transfer between MCU and RA8875.
When setting register number and register data, DB[7:0] is used.
When writing data to display RAM, DB[15:0] is used according to data
bus mode setting. DB[15:8] will be input and should be pull-low or pullhigh when 8-bit data bus mode is used.
Enable/Read Enable
When MCU interface (I/F) is 8080 series, this pin is used as RD# signal
(Data Read) , active low.
When MCU I/F is 6800 series, this pin is used as EN signal (Enable),
active high.
Write/Read-Write
When MCU I/F is 8080 series, this pin is used as WR# signal (data
write) , active low.
When MCU I/F is 6800 series, this pin is used as RW# signal (data
read/write control) . Active high for read and active low for write.
Chip Select Input
Low active chip select pin.
Command / Data Select Input
The pin is used to select command/data cycle. RS = 0, data Read/Write
cycle is selected. RS = 1, status read/command write cycle is selected.
In 8080 interface, usually it connects to “A0” address pin.
RS
0
0
1
1
WR#
0
1
0
1
Access Cycle
Data Write
Data Read
CMD Write
Status Read
MCU Interface Select
0: 8080 interface is selected
1: 6800 interface is selected
Parallel /Serial I/F Select Input
0: Parallel 8080/6800 I/F select
1: Serial 3/4-wire SPI or IIC I/F select.
PS input is used to select the active MCU interface, it must be set
correctly before the command /data cycle asserting.
Interrupt Signal Output
The interrupt output for MCU to indicate the status of RA8875.
Wait Signal Output
This is a WAIT# output to indicate the RA8875 is in busy state. The
RA8875 can’t access MCU cycle when WAIT# pin is active. It is active
low and could be used for MCU to poll busy status by connecting it to I/O
port.
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
4-2 Serial MCU Interface
Pin Name
I/O
SCL
I
SDI
I/O
SDO
I/O
SCS#
I
IICA[1:0]
I
SIFS[1:0]
I
Pin Description
SPI Clock
3-wire, 4-wire Serial or IIC I/F clock. If no use, please connect it to VDDP.
IIC data /4-wire SPI Data Input
4-wire SPI I/F: Data input for serial I/F.
3-wire SPI I/F: NC, please connect it to VDDP.
IIC I/F: Bi-direction data for serial I/F
If no use, please connect it to VDDP.
3-wire SPI Data /4-wire SPI Data Output
4-wire SPI I/F: Data output for serial I/F.
3-wire SPI I/F: Bi-direction data for serial I/F
IIC I/F: NC, if no use, please keep floating.
If no use, please keep floating.
SPI Chip Select
Chip select pin for 3-wire or 4-wire serial I/F.
IIC I/F : NC, please connect it to VDDP.
If no use, please connect it to VDDP.
IIC I/F: IIC Address Select.
Other I/F: NC, please connect it to VDDP.
Serial Interface Selection
00 : NC.
01 : 3-Wire SPI
10 : 4-Wire SPI
11 : IIC
If serial I/F is no use, please connect them to 00.
4-3 LCD Panel Interface
Pin Name
I/O
Pin Description
LCD Panel Data Bus
TFT LCD data bus output for source driver. RA8875 supports 256/64K
color depth by register (REG[10h]), user can connect corresponding RGB
bus for different setting. For unused pin please keeps it floating.
PDAT[15:0]
O
HSYNC
O
VSYNC
O
PCLK
O
DE
O
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Color Depth
256
64K
Red
PDAT[15:14]
PDAT[15:11]
Green
PDAT[10:8]
PDAT[10:5]
Blue
PDAT[4:3]
PDAT[4:0]
HSYNC Pulse
Generic TFT interface signal.
VSYNC Pulse
Generic TFT interface signal.
Pixel Clock
Generic TFT interface signal.
Data Enable
Generic TFT interface signal.
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
4-4 Serial Flash/ROM Interface
Pin Name
I/O
Pin Description
SFCL
O
SFDI/SIO0
I/O
SFDO/SIO1
I/O
SFCS0#
O
SFCS1#
O
External Serial Flash/ROM Clock
Serial Flash/ROM SPI I/F clock.
External Flash/ROM SPI Data Input
Single mode: Data input of serial Flash/ROM SPI I/F. For RA8875, it is
output (Default).
Dual mode: The signal is used as bi-direction data #0(SIO0).
External Flash/ROM SPI Data Output
Single mode: Data output of serial Flash/ROM SPI I/F. For RA8875, it is
input (Default).
Dual mode: The signal is used as bi-direction data #1(SIO1).
External Flash/ROM SPI Chip Select 0
Chip select pin for serial Flash/ROM SPI I/F #0.
External Flash/ROM SPI Chip Select 1
Chip select pin for serial Flash/ROM SPI I/F #1.
4-5 Touch Interface
Pin Name
I/O
YN
A
YP
A
XN
A
XP
A
ADC_VREF
A
Pin Description
YN Signal for Touch Panel
4-wire TP YN Control Signal.
YP Signal for Touch Panel
4-wire TP YP Control Signal.
XN Signal for Touch Panel
4-wire TP XN Control Signal.
XP Signal for Touch Panel
4-wire TP XP Control Signal.
TP ADC Reference Voltage
This pin is the reference voltage for ADC as 0.5*VDD. The reference
voltage could be generated by RA8875 (default) or from external circuit.
4-6 KEYSCAN Interface
Pin Name
KOUT[3:0]/
(GPO[3:0])
I/O
O
KIN[4:0]/
(GPI[4:0])
I
GPOX
O
GPIX
I
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Pin Description
Keypad Strobe Line or GPOs (General Purpose Output)
Keypad matrix strobe lines outputs with open-drain. (Default).
They could be programmed as GPOs by register setting, if don’t use,
please keep floating.
Keypad Data Line or GPIs (General Purpose Input)
Keypad data inputs (Default), please add pull-up resister.
They could be programmed as GPIs by register setting, if don’t use,
please connect it to GND.
Extra GPO (General Purpose Output)
Additional GPO signal, if don’t use, please keep floating.
Extra GPI (General Purpose Input)
Additional GPI signal, if don’t use, please connect it to GND.
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
4-7 PWM Interface
Pin Name
I/O
Pin Description
PWM1
O
PWM signal output 1
PWM2
O
PWM signal output 2
4-8 Clock and Power Interface
Pin Name
I/O
XI
I
XO
O
RST#
I
TEST[2:0]
I
VDDP
P
CORE_VDD
P
LDO_OUT
P
LDO_GND
P
OSC_VDDP
P
OSC_VDD
P
OSC_GNDP
P
OSC_GND
P
ADC_VDD
P
ADC_GND
P
GND
P
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Pin Description
Crystal Input Pin
Input pin for internal crystal circuit. It should be connected to external
crystal circuit. That will generate the system clock for RA8875.
Crystal Output Pin
Output pin for internal crystal circuit. It should be connected to external
crystal circuit. That will generate the system clock for RA8875.
Reset Signal Input
This active-low input performs a hardware reset on the RA8875. It is a
Schmitt-trigger input with pull-up resistor for enhanced noise immunity;
however, it must ensure that it is not triggered if the supply voltage is too
low.
Test Mode Input
For chip test function, should be connected to GND for normal operation.
IO VDD
3.3V IO power input.
CORE VDD
1.8 V Core power input.
LDO VDD Output
1.8V power generated by internal LDO. It must connect bypass
capacities to prevent power noise.
LDO GND
Ground signal for internal LDO.
OSC IO VDD
The separated OSC 3.3V IO power.
OSC VDD
OSC 1.8 V power input. It is used by OSC core. It is suggested to
connect the bypass capacitor nearby the pad.
OSC IO GND
The separated OSC IO ground signal.
OSC GND
OSC ground signal and are internally connected to OSC_GNDP.
ADC VDD
ADC 3.3V power signal.
ADC GND
ADC ground signal
GND
IO Cell/Core ground signal
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
5. Register
There are 4 types of cycles used in MCU interface of RA8875, please refer to Table 5-1 for detail. The
programming or reading of the registers in RA8875 is composed by the cycles. RA8875 includes a
status register and tens of instruction registers. The status register is read only and can be read by
“Status Read” cycle. The instruction registers, that is used to program almost functions, can be
programmed by “Command Write” cycle and “Data Write” cycle. The “Command Write” cycle sets the
register number to program, and the “Data Write” cycle set the data of the register. When reading the
specific instruction registers, MCU asserts a “Data read” cycle following the “Command Write cycle”. The
“Command Write” cycle sets the register number to program, and the “Data Read” cycle read the data of
the register. The instruction registers are classified to 15 categories as Table 5-2, most of which are
readable/writable. All of the registers will be illustrated in the following sections.
Table 5-1 : MCU Cycle Type
Cycle Type
RW#
RS
Description
Command Write
0
1
Register number write cycle
Status Read
1
1
Status read cycle
Data Write
0
0
Data Read
1
0
Corresponding Register data/Memory data write
cycle following the Command Write cycle.
Corresponding Register data/Memory data read cycle
following the Command Write cycle.
Table 5-2 : The Categories of the Instruction Registers
No.
Command Registers
Address
1
System and Configuration Registers
[01h], [02h], [04h],
[10h] ~ [1Fh]
2
LCD Display Control Registers
[20h] ~ [29h]
3
Active Window Setting Registers
[30h] ~ [3Fh]
4
Cursor Setting Registers
[40h] ~ [4Eh]
5
BTE Control Registers
[50h] ~ [67h]
6
Touch Panel Control Registers
[70h] ~ [74h]
7
Graphic Cursor Setting Registers
[80h] ~ [85h]
8
PLL Setting Registers
[88h], [89h]
9
PWM Control Registers
[8Ah] ~ [8Eh]
10
Drawing Control Registers
[90h] ~ [ACh]
11
DMA Control Registers
[B0h] ~ [BFh]
12
KEY & IO Control Registers
[C0h] ~ [C7h]
13
Floating Window Control Registers
[D0h] ~ [DBh]
14
Serial Flash Control Registers
[E0h] ~ [E2h]
15
Interrupt Control Registers
[F0h] ~ [F1h]
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
The registers function description is listed below, for each register, a register name and register number
is described upper each register function table. Each register contains up-to 8 bits data. In the register
function table, detail description, default value and access attribute (RO: Read only, WO: Write only, RW:
Read-able and Write-able) are described.
5-1 Status Register
Status Register (STSR)
Bit
7
6
5
4
3-1
0
Description
Memory Read/Write Busy (Include Font Write Busy)
0 : No Memory Read/Write event.
1 : Memory Read/Write busy.
BTE Busy
0 : BTE is done or idle.
1 : BTE is busy.
Touch Panel Event Detected
0 : Touch Panel is not touched.
1 : Touch Panel is touched.
This bit comes from the TP controller ADET signal directly and
not de-bounced. It’s suggested to check the validation for
multiple polling.
Sleep Mode Status
0: RA8875 in Normal mode.
1: RA8875 in Sleep mode.
N/A
Serial Flash/ROM Busy
Serial Flash/ROM busy status at Direct Access Mode.
0: idle
1: busy
Default
Access
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
Default
Access
0
RW
0
RO
0
RW
0
WO
Note : “RO” means read only.
5-2 System & Configuration Registers
REG[01h] Power and Display Control Register (PWRR)
Bit
7
6-2
1
0
Description
LCD Display Off
0 : Display off.
1 : Display on.
NA
Sleep Mode
0 : Normal mode.
1 : Sleep mode.
Note:
1. There are 3 ways to wake up from sleep mode:
Touch Panel wake up, Key Scan wake up, Software wake up.
2. When using IIC interface, this function is not supported.
Software Reset
0 : No action.
1 : Software Reset.
Note: The bit must be set to 1 and then set to 0 to complete a
software reset.
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
REG[02h] Memory Read/Write Command (MRWC)
Bit
7-0
Description
Write Function : Memory Write Data
Data to write in memory corresponding to the setting
MWCR1[3:2]. Continuous data write cycle can be accepted
bulk data write case.
Read Function : Memory Read Data
Data to read from memory corresponding to the setting
MWCR1[3:2]. Continuous data read cycle can be accepted
bulk data read case. Note that the first data read cycle
dummy read and need to be ignored.
Default
Access
--
RW
Default
Access
0
RW
0
RO
0
RW
Default
Access
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
of
in
of
in
is
REG[04h] Pixel Clock Setting Register (PCSR)
Bit
7
6-2
1-0
Description
PCLK Inversion
0 : PDAT is fetched at PCLK rising edge.
1 : PDAT is fetched at PCLK falling edge.
NA
PCLK Period Setting
Pixel clock (PCLK) period setting.
00b: PCLK period = System Clock period.
01b: PCLK period = 2 times of System Clock period.
10b: PCLK period = 4 times of System Clock period.
11b: PCLK period = 8 times of System Clock period.
REG[05h] Serial Flash/ROM Configuration Register (SROC)
Bit
7
6
5
4-3
2
1-0
Description
Serial Flash/ROM I/F # Select
0: Serial Flash/ROM 0 I/F is selected.
1: Serial Flash/ROM 1 I/F is selected.
Serial Flash/ROM Address Mode
0: 24 bits address mode
This bit must set to 0 for serial flash .
Serial Flash/ROM Waveform Mode
Mode 0.
Mode 3.
Serial Flash /ROM Read Cycle
00b: 4 bus Î no dummy cycle
01b: 5 bus Î1 byte dummy cycle
1Xb: 6 bus Î2 byte dummy cycle
Serial Flash /ROM Access Mode
0: Font mode
1: DMA mode
Serial Flash /ROM I/F Data Latch Mode Select
0Xb: Single Mode
10b: Dual Mode 0.
11b: Dual Mode 1.
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
REG[06h] Serial Flash/ROM CLK Setting Register(SFCLR)
Bit
7-2
1-0
Description
NA
Serial Flash/ROM Clock Frequency Setting
0xb: SFCL frequency = System clock frequency
(When DMA enable and Color depth = 256 color
SFCL frequency = System clock frequency /2)
10b: SFCL frequency = System clock frequency / 2
11b: SFCL frequency = System clock frequency / 4
Default
Access
0
RO
0
RW
Default
Access
0
RO
REG[10h] System Configuration Register (SYSR)
Bit
7-4
Description
N/A
3-2
Color Depth Setting
00b : 8-bpp generic TFT, i.e. 256 colors.
1xb : 16-bpp generic TFT, i.e. 65K colors.
0
RW
1-0
MCUIF Selection
00b : 8-bit MCU Interface.
1xb : 16-bit MCU Interface.
0
RW
Default
Access
0
RO
NA
RO
Default
Access
REG[12h] GPI
Bit
Description
7-5
NA
4-0
GPI[4:0] : General Purpose Input.
KEY_EN = 0: General Purpose Input from pin KIN[4:0]
KEY_EN = 1: NC
Note : KEY_EN : REG[C0h] bit 7
REG[13h] GPO
Bit
Description
7-4
NA
0
RO
3-0
GPO[3:0] : General Purpose Output
KEY_EN = 0: General Purpose Output to KOUT[3:0]
KEY_EN = 1: NC
0
RW
Default
Access
Note : KEY_EN : REG[C0h] bit 7
REG[14h] LCD Horizontal Display Width Register (HDWR)
Bit
Description
7
NA
0
RO
Horizontal Display Width Setting Bit[6:0]
The register specifies the LCD panel horizontal display width in
6-0
0
RW
the unit of 8 pixels resolution.
Horizontal display width(pixels) = (HDWR + 1)x8
Note : HDWR must be set less than 64h because that the maximum horizontal display width is 800 pixels.
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
REG[15h] Horizontal Non-Display Period Fine Tuning Option Register (HNDFTR)
Bit
7
6-4
3-0
Description
DE Polarity
0 : high active.
1 : low active.
NA
Horizontal Non-Display Period Fine Tuning(HNDFT) [3:0]
This register specifies the fine tuning for horizontal non-display
period; it is used to support the SYNC mode panel. Each level
of this modulation is 1-pixel.
Default
Access
0
RW
0
RO
0
RW
Default
Access
0
RO
0
RW
REG[16h] LCD Horizontal Non-Display Period Register (HNDR)
Bit
7-5
4-0
Description
NA
Horizontal Non-Display Period(HNDP) Bit[4:0]
This register specifies the horizontal non-display period.
Horizontal Non-Display Period (pixels)
=[(HNDR + 1)x8+HNDFTR+2
REG[17h] HSYNC Start Position Register (HSTR)
Bit
Description
Default
Access
7-5
NA
HSYNC Start Position[4:0]
The starting position from the end of display area to the
beginning of HSYNC. Each level of this modulation is 8-pixel.
HSYNC Start Position(pixels) = (HSTR + 1)x8
0
RO
0
RW
Default
Access
0
RW
0
RO
0
RW
Default
Access
0
RW
4-0
REG[18h] HSYNC Pulse Width Register (HPWR)
Bit
7
6-5
4-0
Description
HSYNC Polarity
0 : Low active.
1 : High active.
NA
HSYNC Pulse Width(HPW) [4:0]
The period width of HSYNC.
HSYNC Pulse Width(pixels) = (HPW + 1)x8
REG[19h] LCD Vertical Display Height Register (VDHR0)
Bit
7-0
Description
Vertical Display Height Bit[7:0]
Vertical Display Height(Line) = VDHR + 1
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
REG[1Ah] LCD Vertical Display Height Register0 (VDHR1)
Bit
Description
Default
Access
7-1
NA
0
RO
Vertical
Display
Height
Bit[8]
0
0
RW
Vertical Display Height(Line) = VDHR + 1
Note : The VDHR must be set less than 1E0h, because the maximum vertical display height is 480.
REG[1Bh] LCD Vertical Non-Display Period Register (VNDR0)
Bit
7-0
Description
Vertical Non-Display Period Bit[7:0]
Vertical Non-Display Period(Line) = (VNDR + 1)
Default
Access
0
RW
Default
Access
0
RO
0
RW
REG[1Ch] LCD Vertical Non-Display Period Register (VNDR1)
Bit
7-1
0
Description
NA
Vertical Non-Display Period Bit[8]
Vertical Non-Display Period(Line) = (VNDR + 1)
REG[1Dh] VSYNC Start Position Register (VSTR0)
Bit
Description
Default
Access
7-0
VSYNC Start Position[7:0]
The starting position from the end of display area to the
beginning of VSYNC.
VSYNC Start Position(Line) = (VSTR + 1)
0
RW
REG[1Eh] VSYNC Start Position Register (VSTR1)
Bit
Description
Default
Access
7-1
NA
VSYNC Start Position[8]
The starting from the end of display area to the beginning of
VSYNC.
VSYNC Start Position(Line) = (VSTR + 1)
0
RO
0
RW
Default
Access
0
RW
0
RW
0
REG[1Fh] VSYNC Pulse Width Register (VPWR)
Bit
7
6-0
Description
VSYNC Polarity
0 : Low active.
1 : High active.
VSYNC Pulse Width[6:0]
The pulse width of VSYNC in lines.
VSYNC Pulse Width(Line) = (VPWR + 1)
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
5-3 LCD Display Control Registers
REG[20h] Display Configuration Register (DPCR)
Bit
7
6-4
3
2
1-0
Description
Layer Setting Control
0 : One layer configuration is selected.
1 : Two layers configuration is selected..
NA
HDIR
Horizontal Scan Direction, for n = SEG number.
0 : SEG0 to SEG(n-1).
1 : SEG(n-1) to SEG0.
VDIR
Vertical Scan direction, for n = COM number
0 : COM0 to COM(n-1)
1 : COM(n-1) to COM0
NA
Default
Access
0
RW
0
RO
0
RW
0
RW
0
RO
Default
Access
0
RW
0
RO
0
RW
0
RO
0
RW
REG[21h] Font Control Register 0 (FNCR0)
Bit
7
6
5
4-2
1-0
Description
CGRAM/CGROM Font Selection Bit in Text Mode
0 : CGROM font is selected.
1 : CGRAM font is selected.
Note:
1. The bit is used to select the bit-map source when text-mode
is active(REG[40h] bit 7 is 1), when CGRAM is
writing(REG[41h] bit 3-2 =01b), the bit must be set as “0”.
2. When CGRAM font is select, REG[21h] bit 5 must be set as
1.
NA
External/Internal CGROM Selection Bit
0 : Internal CGROM is selected.(REG[2Fh] must be set 00h )
1 : External CGROM is selected.
NA
Font Selection for internal CGROM
When FNCR0 B7 = 0 and B5 = 0, Internal CGROM supports the
8x16 character sets with the standard coding of ISO/IEC 88591~4, which supports English and most of European country
languages.
00b : ISO/IEC 8859-1.
01b : ISO/IEC 8859-2.
10b : ISO/IEC 8859-3.
11b : ISO/IEC 8859-4.
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
REG[22h] Font Control Register1 (FNCR1)
Bit
7
6
5
4
3-2
1-0
Description
Full Alignment Selection Bit
0 : Full alignment is disable.
1 : Full alignment is enable.
Font Transparency
0 : Font with background color.
1 : Font with background transparency.
NA
Font Rotation
0 : Normal.
1 : 90 degree display.
Horizontal Font Enlargement
00b : X1.
01b : X2.
10b : X3.
11b : X4.
Vertical Font Enlargement
00b : X1.
01b : X2.
10b : X3.
11b : X4.
Default
Access
0
RW
0
RW
0
RO
0
RW
0
RW
0
RW
REG[23h] CGRAM Select Register (CGSR)
Bit
Description
Default
Access
7-0
CGRAM No.
The setting of the number of the character in CGRAM. It’s used
to write the user-defined character bitmap data into CGRAM. 16
continuous data write cycles compete the bitmap writing of a
8x16 character. Note that the MWCR1 bit 3-2 must be set as
01b(CGRAM) first. And more than 16 data write cycles will loop
back to the 1st data and cover the bitmap.
0
RW
REG[24h] Horizontal Scroll Offset Register 0 (HOFS0)
Bit
Description
Default
Access
7-0
Horizontal Display Scroll Offset [7:0]
The display offset of the horizontal direction, changing the value
will cause the effect of scrolling at horizontal direction.
0
RW
REG[25h] Horizontal Scroll Offset Register 1 (HOFS1)
Bit
Description
Default
Access
7-3
NA
Horizontal Display Scroll Offset [10:8]
The display offset of the horizontal direction, changing the value
will cause the effect of scrolling at horizontal direction.
0
RO
0
RW
2-0
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
REG[26h] Vertical Scroll Offset Register 0 (VOFS0)
Bit
Description
Default
Access
7-0
Vertical Display Scroll Offset [7:0]
The display offset of the vertical direction, changing the value
will cause the effect of scrolling at vertical direction.
0
RW
REG[27h] Vertical Scroll Offset Register 1 (VOFS1)
Bit
Description
Default
Access
7-2
NA
Vertical Display Scroll Offset [9:8]
The display offset of the vertical direction, changing the value
will cause the effect of scrolling at vertical direction.
0
RO
0
RW
1-0
REG[29h] Font Line Distance Setting Register (FLDR)
Bit
Description
Default
Access
7-5
NA
Font Line Distance Setting
Setting the font character line distance when setting memory
font write cursor auto move. (Unit: pixel)
0
RO
0
RW
Default
Access
0
RW
Default
Access
0
RO
0
RW
4-0
Active window
瑞佑科技
Font line distance
RA i O
Figure 5-1 : Character Line Distance
REG[2Ah] Font Write Cursor Horizontal Position Register 0 (F_CURXL)
Bit
7-0
Description
Font Write Cursor Horizontal Position[7:0]
The setting of the horizontal cursor position for font writing.
REG[2Bh] Font Write Cursor Horizontal Position Register 1 (F_CURXH)
Bit
7-2
1-0
Description
NA
Font Write Cursor Horizontal Position[9:8]
The setting of the horizontal cursor position for font writing.
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
REG[2Ch] Font Write Cursor Vertical Position Register 0 (F_CURYL)
Bit
7-0
Description
Font Write Cursor Vertical Position[7:0]
The setting of the vertical cursor position for font writing.
Default
Access
0
RW
Default
Access
0
RO
0
RW
Default
Access
0
RW
0
RW
REG[2Dh] Font Write Cursor Vertical Position Register 1 (F_CURYH)
Bit
7-1
0
Description
NA
Font Write Cursor Vertical Position[8]
The setting of the vertical cursor position for font writing.
REG[2Eh] Font Write Type Setting Register
Bit
Description
Font Size Setting
7-6
5-0
Full Size
Half-Size
00b
16x16
8x16
Variable
Width
NX16
01b
24x24
12x24
NX24
1Xb
32x32
16x32
NX32
Note: The font width indicated by “N” depends on the character
code of the FONT.
Font to Font Width Setting
00h : Font width off
01h : Font to Font width = 1 pixel
02h : Font to Font width = 2 pixels
.
.
3Fh : Font to Font width = 63 pixels
Font to Font width
R A
i
O
Figure 5-2 : Font to Font Width
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
REG[2Fh] Serial Font ROM Setting
Bit
7-5
4-2
Description
GT Serial Font ROM Select
000b: GT21L16TW / GT21H16T1W
001b: GT23L16U2W
010b: GT23L24T3Y / GT23H24T3Y
011b: GT23L24M1Z
100b: GT23L32S4W / GT23H32S4W
FONT ROM Coding Setting
For specific GT serial Font ROM, the coding method must be
set for decoding.
000b: GB2312
001b: GB12345/GB18030
010b: BIG5
011b: UNICODE
100b: ASCII
101b: UNI-Japanese
110b: JIS0208
111b: Latin/Greek/ Cyrillic / Arabic
ASCII / Latin/Greek/ Cyrillic / Arabic
Latin / Greek
ASCII
/Cyrillic
00b
Normal
Normal
1-0
01b
Arial
Variable Width
10b
Roman
NA
11b
Bold
NA
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Default
Access
0
RW
0
RW
0
RW
Arabic
NA
Presentation
Forms-A
Presentation
Forms-B
NA
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
5-4 Active Window & Scroll Window Setting Registers
REG[30h] Horizontal Start Point 0 of Active Window (HSAW0)
Bit
7-0
Description
Horizontal Start Point of Active Window [7:0]
Default
Access
0
RW
Default
Access
0
0
RO
RW
Default
Access
0
RW
Default
Access
0
0
RO
RW
Default
Access
0
RW
Default
Access
0
0
RO
RW
Default
Access
0
RW
Default
Access
0
0
RO
RW
REG[31h] Horizontal Start Point 1 of Active Window (HSAW1)
Bit
7-2
1-0
Description
NA
Horizontal Start Point of Active Window [9:8]
REG[32h] Vertical Start Point 0 of Active Window (VSAW0)
Bit
7-0
Description
Vertical Start Point of Active Window [7:0]
REG[33h] Vertical Start Point 1 of Active Window (VSAW1)
Bit
7-1
0
Description
NA
Vertical Start Point of Active Window [8]
REG[34h] Horizontal End Point 0 of Active Window (HEAW0)
Bit
7-0
Description
Horizontal End Point of Active Window [7:0]
REG[35h] Horizontal End Point 1 of Active Window (HEAW1)
Bit
7-2
1-0
Description
NA
Horizontal End Point of Active Window [9:8]
REG[36h] Vertical End Point of Active Window 0 (VEAW0)
Bit
7-0
Description
Vertical End Point of Active Window [7:0]
REG[37h] Vertical End Point of Active Window 1 (VEAW1)
Bit
7-1
0
Description
NA
Vertical End Point of Active Window [8]
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
(HSAW,VSAW)
Active Window
(HEAW,VEAW)
Figure 5-3 : Active Window
REG[38h] Horizontal Start Point 0 of Scroll Window (HSSW0)
Bit
7-0
Description
Horizontal Start Point of Scroll Window [7:0]
Default
Access
0
RW
Default
Access
0
0
RO
RW
Default
Access
0
RW
Default
Access
0
0
RO
RW
Default
Access
0
RW
Default
Access
0
0
RO
RW
REG[39h] Horizontal Start Point 1 of Scroll Window (HSSW1)
Bit
7-2
1-0
Description
NA
Horizontal Start Point of Scroll Window [9:8]
REG[3Ah] Vertical Start Point 0 of Scroll Window (VSSW0)
Bit
7-0
Description
Vertical Start Point of Scroll Window [7:0]
REG[3Bh] Vertical Start Point 1 of Scroll Window (VSSW1)
Bit
7-1
0
Description
NA
Vertical Start Point of Scroll Window [8]
REG[3Ch] Horizontal End Point 0 of Scroll Window (HESW0)
Bit
7-0
Description
Horizontal End Point of Scroll Window [7:0]
REG[3Dh] Horizontal End Point 1 of Scroll Window (HESW1)
Bit
7-2
1-0
Description
NA
Horizontal End Point of Scroll Window [9:8]
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
REG[3Eh] Vertical End Point 0 of Scroll Window (VESW0)
Bit
7-0
Description
Vertical End Point of Scroll Window [7:0]
Default
Access
0
RW
Default
Access
0
0
RO
RW
REG[3Fh] Vertical End Point 1 of Scroll Window (VESW1)
Bit
7-1
0
Description
NA
Vertical End Point of Scroll Window [8]
(HSSW,VSSW)
Scroll Window
(HESW,VESW)
Figure 5-4 : Scroll Window
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
5-5 Cursor Setting Registers
REG[40h] Memory Write Control Register 0 (MWCR0)
Bit
7
6
5
4
3-2
1
0
Description
Text Mode Enable
0 : Graphic mode.
1 : Text mode.
Font Write Cursor/ Memory Write Cursor Enable
0 : Font write cursor/ Memory Write Cursor is not visible.
1 : Font write cursor/ Memory Write Cursor is visible.
Font Write Cursor/ Memory Write Cursor Blink Enable
0 : Normal display.
1 : Blink display.
NA
Memory Write Direction (Only for Graphic Mode)
00b : Left Æ Right then Top Æ Down.
01b : Right Æ Left then Top Æ Down.
10b : Top Æ Down then Left Æ Right.
11b : Down Æ Top then Left Æ Right.
Memory Write Cursor Auto-Increase Disable
0 : Cursor auto-increases when memory write.
1 : Cursor doesn’t auto-increases when memory write.
Memory Read Cursor Auto-Increase Disable
0 : Cursor auto-increases when memory read.
1 : Cursor doesn’t auto-increases when memory read.
Default
Access
0
RW
0
RW
0
RW
0
RO
0
RW
0
RW
0
RW
Default
Access
0
RW
0
RW
0
RW
0
RO
0
RW
REG[41h] Memory Write Control Register1 (MWCR1)
Bit
7
6-4
3-2
1
0
Description
Graphic Cursor Enable
0 : Graphic Cursor disable.
1 : Graphic Cursor enable.
Graphic Cursor Selection Bit
Select one from eight graphic cursor types. (000b to 111b)
000b : Graphic Cursor Set 1.
001b : Graphic Cursor Set 2.
010b : Graphic Cursor Set 3.
:
:
111b : Graphic Cursor Set 8.
Write Destination Selection
00b : Layer 1~2.
01b : CGRAM.
10b : Graphic Cursor.
11b : Pattern.
Note : When CGRAM is selected (01b), REG[21h] bit 7 must be
set as “0”.
NA
Layer No. for Writing Selection
When resolution =< 480x400 or color depth = 8bpp:
0 : Layer 1.
1 : Layer 2.
When resolution > 480x400 and color depth > 8bpp:
NA, always writing to Layer 1.
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
REG[44h] Blink Time Control Register (BTCR)
Bit
7-0
Description
Text Blink Time Setting (Unit: Frame)
00h : 1 frame time.
01h : 2 frames time.
02h : 3 frames time.
:
:
:
FFh : 256 frames time.
Default
Access
0
RW
Default
Access
0
RO
0
RW
Default
Access
0
RW
Default
Access
REG[45h] Memory Read Cursor Direction (MRCD)
Bit
7-2
1-0
Description
NA
Memory Read Direction (Only for Graphic Mode)
00b : Left Æ Right then Top Æ Down.
01b : Right Æ Left then Top Æ Down.
10b : Top Æ Down then Left Æ Right.
11b : Down Æ Top then Left Æ Right.
REG[46h] Memory Write Cursor Horizontal Position Register 0 (CURH0)
Bit
7-0
Description
Memory Write Cursor Horizontal Location[7:0]
REG[47h] Memory Write Cursor Horizontal Position Register 1 (CURH1)
Bit
Description
7-2
NA
0
RO
1-0
Memory Write Cursor Horizontal Location[9:8]
0
RW
Default
Access
0
RW
REG[48h] Memory Write Cursor Vertical Position Register 0 (CURV0)
Bit
7-0
Description
Memory Write Cursor Vertical Location[7:0]
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
REG[49h] Memory Write Cursor Vertical Position Register 1 (CURV1)
Bit
7-1
0
Description
Default
Access
NA
0
RO
Memory Write Cursor Vertical Location[8]
0
RW
Default
Access
0
RW
Default
Access
REG[4Ah] Memory Read Cursor Horizontal Position Register 0 (RCURH0)
Bit
7-0
Description
Memory Read Cursor Horizontal Location[7:0]
REG[4Bh] Memory Read Cursor Horizontal Position Register 1 (RCURH01)
Bit
Description
7-2
NA
0
RO
1-0
Memory Read Cursor Horizontal Location[9:8]
0
RW
Default
Access
0
RW
Default
Access
NA
0
RO
Memory Read Cursor Vertical Location[8]
0
RW
REG[4Ch] Memory Read Cursor Vertical Position Register 0 (RCURV0)
Bit
7-0
Description
Memory Read Cursor Vertical Location[7:0]
REG[4Dh] Memory Read Cursor Vertical Position Register 1 (RCURV1)
Bit
7-1
0
Description
REG[4Eh] Font Write Cursor and Memory Write Cursor Horizontal Size Register (CURHS)
Bit
Description
Default
Access
7-5
NA
Font Write Cursor Horizontal Size Setting[4:0]
Unit : Pixel
Note : When font is enlarged, the cursor setting will multiply the
same times as the font enlargement.
0
RO
7h
RW
4-0
REG[4Fh] Font Write Cursor Vertical Size Register (CURVS)
Bit
Description
Default
Access
7-5
NA
Font Write Cursor Vertical Size Setting[4:0]
Unit : Pixel
Note : When font is enlarged, the cursor setting will multiply the
same times as the font enlargement.
0
RO
0
RW
4-0
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
5-6 Block Transfer Engine(BTE) Control Registers
REG[50h] BTE Function Control Register 0 (BECR0)
Bit
7
6
5
4-0
Description
BTE Function Enable / Status
Write
0 : No action.
1 : BTE function enable.
Read
0 : BTE function is idle.
1 : BTE function is busy.
BTE Source Data Select
0 : Block mode, the Source BTE is stored as a rectangular
region of memory.
1 : Linear mode, the Source BTE is stored as a continuous
block of memory.
BTE Destination Data Type Select
0 : Block mode, the Destination BTE is stored as a rectangular
region of memory.
1 : Linear mode, the Destination BTE is stored as a continuous
block of memory.
NA
Default
Access
0
RW
0
RW
0
RW
0
RO
Default
Access
0
RW
0
RW
REG[51h] BTE Function Control Register1 (BECR1)
Bit
7-4
3-0
Description
BTE ROP Code Bit[3:0]
ROP is the acronym for Raster Operation. Some of BTE
operation code has to collocate with ROP for the detailed
function. (Please refer to the Section 7-6)
BTE Operation Code Bit[3:0]
RA8875 includes a 2D BTE Engine, it can execute 13 BTE
functions, the operation code range is from 1100b to 0000b and
1111b to 1101b are not used. Some of BTE Operation Code
has to collocate with the ROP code for the advance function.
(Please refer to the Section 7-6)
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
REG[52h] Layer Transparency Register0 (LTPR0)
Bit
7-6
5
4-3
2-0
Description
Layer1/2 Scroll Mode
00b : Layer 1/2 scroll simultaneously.
01b : Only Layer 1 scroll.
10b : Only Layer 2 scroll.
11b: Buffer scroll (using Layer 2 as scroll buffer)
Floating Windows Transparency Display With BGTR
0: Disable
1: Enable
NA
Layer1/2 Display Mode
000b : Only Layer 1 is visible.
001b : Only Layer 2 is visible.
010b : Lighten-overlay mode.
011b : Transparent mode.
100b : Boolean OR.
101b : Boolean AND.
110b : Floating window mode.
111b : Reserve.
Default
Access
0
RW
0
RW
0
RO
0
RW
Note : It's suggested that REG[40h] Bit 7 should be set as 1'b0 when using "buffer scroll function".
REG[53h] Layer Transparency Register1 (LTPR1)
Bit
7-4
3-0
Description
Layer Transparency Setting for Layer 2
0000b : Total display.
0001b : 7/8 display.
0010b : 3/4 display.
0011b : 5/8 display.
0100b : 1/2 display.
0101b : 3/8 display.
0110b : 1/4 display.
0111b : 1/8 display.
1000b : Display disable.
Layer Transparency Setting for Layer 1
0000b : Total display.
0001b : 7/8 display.
0010b : 3/4 display.
0011b : 5/8 display.
0100b : 1/2 display.
0101b : 3/8 display.
0110b : 1/4 display.
0111b : 1/8 display.
1000b : Display disable.
Default
Access
0
RW
0
RW
Default
Access
0
RW
REG[54h] Horizontal Source Point 0 of BTE (HSBE0)
Bit
7-0
Description
Horizontal Source Point of BTE [7:0]
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
REG[55h] Horizontal Source Point 1 of BTE (HSBE1)
Bit
7-2
1-0
Description
NA
Horizontal Source Point of BTE [9:8]
Default
Access
0
0
RO
RW
Default
Access
0
RW
Default
Access
0
RW
0
0
RO
RW
Default
Access
0
RW
Default
Access
0
0
RO
RW
Default
Access
0
RW
Default
Access
0
RW
0
RO
0
RW
REG[56h] Vertical Source Point 0 of BTE (VSBE0)
Bit
7-0
Description
Vertical Source Point of BTE [7:0]
REG[57h] Vertical Source Point 1 of BTE (VSBE1)
Bit
7
6-1
0
Description
BTE Source Layer Selection
0 : Layer 1.
1 : Layer 2.
NA
Vertical Source Point of BTE [8]
REG[58h] Horizontal Destination Point 0 of BTE (HDBE0)
Bit
7-0
Description
Horizontal Destination Point of BTE [7:0]
REG[59h] Horizontal Destination Point 1 of BTE (HDBE1)
Bit
7-2
1-0
Description
NA
Horizontal Destination Point of BTE [9:8]
REG[5Ah] Vertical Destination Point 0 of BTE (VDBE0)
Bit
7-0
Description
Vertical Destination Point of BTE [7:0]
REG[5Bh] Vertical Destination Point 1 of BTE (VDBE1)
Bit
7
6-1
0
Description
BTE Destination Layer Selection
0 : Layer 1.
1 : Layer 2.
NA
Vertical Destination Point of BTE [8]
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
REG[5Ch] BTE Width Register 0 (BEWR0)
Bit
7-0
Description
BTE Width Setting[7:0]
Default
Access
0
RW
Default
Access
REG[5Dh] BTE Width Register 1 (BEWR1)
Bit
Description
7-2
NA
0
RO
1-0
BTE Width Setting [9:8]
0
RW
Default
Access
0
RW
Default
Access
REG[5Eh] BTE Height Register 0 (BEHR0)
Bit
7-0
Description
BTE Height Setting[7:0]
REG[5Fh] BTE Height Register 1 (BEHR1)
Bit
Description
7-2
NA
0
RO
1-0
BTE Height Setting [9:8]
0
RW
Default
Access
0
R0
0
RW
Default
Access
0
R0
0
RW
REG[60h] Background Color Register 0 (BGCR0)
Bit
Description
7-5
NA
Background Color Red[4:0]
If REG[10h] Bit[3:2] is set to 256 colors, the register only uses
4-0
Bit[2:0].
If REG[10h] Bit[3:2] is set to 65K colors, the register uses
Bit[4:0].
The Register is used to set the red part of BTE background colors.
REG[61h] Background Color Register 1 (BGCR1)
Bit
Description
7-6
NA
Background Color Green[5:0]
If REG[10h] Bit[3:2] is set to 256 colors, the register only uses
5-0
Bit[2:0].
If REG[10h] Bit[3:2] is set to 65K colors, the register uses
Bit[5:0].
The Register is used to set the green part of BTE background colors.
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
REG[62h] Background Color Register 2 (BGCR2)
Bit
Description
7-5
NA
Background Color Blue[4:0]
If REG[10h] Bit[3:2] is set to 256 colors, the register only uses
4-0
Bit[1:0].
If REG[10h] Bit[3:2] is set to 65K colors, the register uses
Bit[4:0].
The Register is used to set the blue part of BTE background colors.
Default
Access
0
R0
0
RW
Default
Access
0
R0
1Fh
RW
Default
Access
0
R0
3Fh
RW
REG[63h] Foreground Color Register 0 (FGCR0)
Bit
Description
7-5
NA
Foreground Color Red[4:0]
If REG[10h] Bit[3:2] is set to 256 colors, the register only uses
4-0
Bit[2:0].
If REG[10h] Bit[3:2] is set to 65K colors, the register uses
Bit[4:0].
The Register is used to set the red part of BTE foreground colors.
REG[64h] Foreground Color Register 1 (FGCR1)
Bit
Description
7-6
NA
Foreground Color Green[5:0]
If REG[10h] Bit[3:2] is set to 256 colors, the register only uses
5-0
Bit[2:0].
If REG[10h] Bit[3:2] is set to 65K colors, the register uses
Bit[5:0].
The Register is used to set the green part of BTE foreground colors.
REG[65h] Foreground Color Register 2 (FGCR2)
Bit
Description
Default
Access
7-5
NA
Foreground Color Blue[4:0]
If REG[10h] Bit[3:2] is set to 256 colors, the register only uses
Bit[1:0].
If REG[10h] Bit[3:2] is set to 65K colors, the register uses
Bit[4:0].
0
R0
1Fh
RW
4-0
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
REG[66h] Pattern Set No for BTE (PTNO)
Bit
7
6-4
3-0
Description
Pattern Format
0: 8x8
1: 16x16
NA
Pattern Set No
If pattern Format = 8x8 then Pattern Set [3:0] is valid
If pattern Format = 16x16 then Pattern Set [1:0] is valid
Default
Access
0
RW
0
RO
0
RW
REG[67h] Background Color Register for Transparent 0 (BGTR0)
Bit
Description
Default
Access
7-5
NA
Background Color Register for Transparent Red[4:0]
If REG[10h] Bit[3:2] is set to 256 colors, the register only uses
Bit[2:0].
If REG[10h] Bit[3:2] is set to 65K colors, the register uses
Bit[4:0].
0
R0
0
RW
4-0
REG[68h] Background Color Register for Transparent 1 (BGTR1)
Bit
Description
Default
Access
7-6
NA
Foreground Color Green[5:0]
If REG[10h] Bit[3:2] is set to 256 colors, the register only uses
Bit[2:0].
If REG[10h] Bit[3:2] is set to 65K colors, the register uses
Bit[5:0].
0
R0
0
RW
5-0
REG[69h] Background Color Register for Transparent 2 (BGTR2)
Bit
Description
Default
Access
7-5
NA
Foreground Color Blue[4:0]
If REG[10h] Bit[3:2] is set to 256 colors, the register only uses
Bit[1:0].
If REG[10h] Bit[3:2] is set to 65K colors, the register uses
Bit[4:0].
0
R0
0
RW
4-0
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
5-7 Touch Panel Control Registers
REG[70h] Touch Panel Control Register 0 (TPCR0)
Bit
7
6-4
3
2-0
Description
Touch Panel Enable Bit
0 : Disable
1 : Enable
TP Sample Time Adjusting
000b : Wait 512 system clocks period for ADC data ready.
001b : Wait 1024 system clocks period for ADC data ready.
010b : Wait 2048 system clocks period for ADC data ready.
011b : Wait 4096 system clocks period for ADC data ready.
100b : Wait 8192 system clocks period for ADC data ready.
101b : Wait 16384 system clocks period for ADC data ready.
110b : Wait 32768 system clocks period for ADC data ready.
111b : Wait 65536 system clocks period for ADC data ready.
Touch Panel Wakeup Enable
0 : Disable the Touch Panel wake-up function.
1 : Touch Panel can wake-up the sleep mode.
ADC Clock Setting
000b : System CLK
001b : (System CLK) / 2.
010b : (System CLK) / 4.
011b : (System CLK) / 8.
100b : (System CLK) / 16.
101b : (System CLK) / 32.
110b : (System CLK) / 64.
111b : (System CLK) / 128.
Default
Access
0
RW
0
RW
0
RW
0
RW
REG[71h] Touch Panel Control Register 1 (TPCR1)
Bit
Description
Default
Access
7
N/A
TP Manual Mode Enable
0 : Auto mode.
1 : Using the manual mode.
TP ADC Reference Voltage Source
0 : Vref generated from internal circuit. No external voltage is
needed.
1 : Vref from external source, 1/2 VDD is needed for ADC.
NA
De-bounce Circuit Enable for Touch Panel Interrupt
0: De-bounce circuit disable.
1: De-bounce circuit enable.
Mode Selection for TP Manual Mode
00b : IDLE mode: Touch Panel in idle mode.
01b : Wait for TP event, Touch Panel event could cause the
interrupt or be read from REG[F1h] Bit2.
10b : Latch X data, in the phase, X Data can be latched in
REG[72h] and REG[74h].
11b : Latch Y data, in the phase, Y Data can be latched in
REG[73h] and REG[74h].
1
RO
0
RW
0
RW
0
RO
0
R/W
0
RW
6
5
4-3
2
1-0
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
REG[72h] Touch Panel X High Byte Data Register (TPXH)
Bit
7-0
Description
Touch Panel X Data Bit[9:2]
Default
Access
0
RW
Default
Access
0
RW
Default
Access
REG[73h] Touch Panel Y High Byte Data Register (TPYH)
Bit
7-0
Description
Touch Panel Y Data Bit[9:2]
REG[74h] Touch Panel X/Y Low Byte Data Register (TPXYL)
Bit
Description
1
RO
6-4
ADET
Touch Event Detector
0 : Touch Panel is touched.
1 : Touch Panel is not touched.
NA
0
RO
3-2
Touch Panel Y Data Bit[1:0]
0
RW
1-0
Touch Panel X Data Bit[1:0]
0
RW
7
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
5-8 Graphic Cursor Setting Registers
REG[80h] Graphic Cursor Horizontal Position Register 0 (GCHP0)
Bit
7-0
Description
Graphic Cursor Horizontal Location[7:0]
Default
Access
0
RW
Default
Access
REG[81h] Graphic Cursor Horizontal Position Register 1 (GCHP1)
Bit
Description
7-2
NA
0
RO
1-0
Graphic Cursor Horizontal Location[9:8]
0
RW
Default
Access
0
RW
Default
Access
NA
0
RO
Graphic Cursor Vertical Location[8]
0
RW
Default
Access
0
RW
Default
Access
0
RW
REG[82h] Graphic Cursor Vertical Position Register 0 (GCVP0)
Bit
7-0
Description
Graphic Cursor Vertical Location[7:0]
REG[83h] Graphic Cursor Vertical Position Register 1 (GCVP1)
Bit
7-1
0
Description
REG[84h] Graphic Cursor Color 0 (GCC0)
Bit
7-0
Description
Graphic Cursor Color 0 with 256 Colors
RGB Format [7:0] = RRRGGGBB.
REG[85h] Graphic Cursor Color 1 (GCC1)
Bit
7-0
Description
Graphic Cursor Color 1 with 256 Colors
RGB Format [7:0] = RRRGGGBB.
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
5-9 PLL Setting Registers
REG[88h] PLL Control Register 1 (PLLC1)
Bit
7
6-5
4-0
Description
PLLDIVM
PLL Pre-driver parameter.
0 : divided by 1.
1 : divided by 2.
NA
PLLDIVN[4:0]
PLL input parameter, the value should be 1~31. (i.e. value 0 is
forbidden).
Default
Access
0
RW
0
RO
07h
RW
Default
Access
0
RO
03h
RW
REG[89h] PLL Control Register 2 (PLLC2)
Bit
7-3
2-0
Description
NA
PLLDIVK[2:0]
PLL Output divider
000b : divided by 1.
001b : divided by 2.
010b : divided by 4.
011b : divided by 8.
100b : divided by 16.
101b : divided by 32.
110b : divided by 64.
111b : divided by 128.
Note :
1. Default PLL output is as same as OSC clock (FIN) frequency.
2. After REG[88h] or REG[89h] is programmed, a lock time (< 100us) must be kept to guarantee
the stability of the PLL output.
3. The input OSC frequency (FIN) must greater than 15MHz and less than 30MHz. The internal
multiplied clock frequency FPLL = FIN * ( PLLDIVN [4:0] +1 ) must be equal to or greater
than 110 MHz. The following table is the reference setting of OSC clock (FIN) and REG[88h]
Bit[4:0]:
OSC Clock（FIN）
X’tal（MHz）
PLLDIVN[4:0]
REG[88h] Bit[4:0]
15
16
20
25
30
>= 7
>= 7
>= 5
>= 4
>= 3
4. The system clock of RA8875 is generated by oscillator and internal PLL circuit. The following
formula is used for system clock calculation:
SYS_CLK = FIN * ( PLLDIVN [4:0] +1 ) / (( PLLDIVM+1 ) * ( 2^PLLDIVK [2:0] ))
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
5-10 PWM Control Registers
REG[8Ah] PWM1 Control Register (P1CR)
Bit
7
6
Description
PWM1 Enable
0 : Disable, PWM1_OUT level depends on P1CR bit6.
1 : Enable.
PWM1 Disable Level
0 : PWM1_OUT is Normal L when PWM disable or Sleep mode.
1 : PWM1_OUT is Normal H when PWM disable or Sleep
mode.
The bit is only usable when P1CR bit 4 is 0.
Default
Access
0
RW
0
RW
5
Reserved
0
RO
4
PWM1 Function Selection
0 : PWM1 function.
1 : PWM1 output a fixed frequency signal and it is equal to 1 /16
oscillator clock.
PWM1 = FOSC / 16 (Note)
0
RW
0
RW
Default
Access
0
RW
PWM1 Clock Source Divide Ratio
3-0
0000b : SYS_CLK / 1
0001b : SYS_CLK / 2
0010b : SYS_CLK / 4
0011b : SYS_CLK / 8
0100b : SYS_CLK / 16
0101b : SYS_CLK / 32
0110b : SYS_CLK / 64
0111b : SYS_CLK / 128
1000b : SYS_CLK / 256
1001b : SYS_CLK / 512
1010b : SYS_CLK / 1024
1011b : SYS_CLK / 2048
1100b : SYS_CLK / 4096
1101b : SYS_CLK / 8192
1110b : SYS_CLK / 16384
1111b : SYS_CLK / 32768
For example, if the system clock is 20MHz and Bit[3:0] =0001b,
then the clock source of PWM1 is 10MHz.
Note : FOSC is the frequency of external oscillator.
REG[8Bh] PWM1 Duty Cycle Register (P1DCR)
Bit
7-0
Description
PWM Cycle Duty Selection Bit
00h Æ 1 / 256 Duty with PWM1 clock source.
01h Æ 2 / 256 Duty with PWM1 clock source.
02h Æ 3 / 256 Duty with PWM1 clock source.
:
:
:
FEh Æ 255 / 256 Duty with PWM1 clock source.
FFh Æ 256 / 256 Duty with PWM1 clock source.
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
REG[8Ch] PWM2 Control Register (P2CR)
Bit
7
6
5
4
Description
PWM2 Enable
0 : Disable, PWM_OUT level depends on P2CR bit6.
1 : Enable.
PWM2 Disable Level
0 : PWM2_OUT is Normal L when PWM disable or Sleep mode.
1 : PWM2_OUT is Normal H when PWM disable or Sleep
mode.
The bit is only usable when P2CR bit 4 is 0.
Reserved
PWM2 Function Selection
0 : PWM2 function.
1 : PWM2 output a signal which is the same with system clock.
PWM2 = SYS_CLK / 16
PWM2 Clock Source Divide Ratio
0000b : SYS_CLK / 1
0001b : SYS_CLK / 2
0010b : SYS_CLK / 4
0011b : SYS_CLK / 8
0100b : SYS_CLK / 16
0101b : SYS_CLK / 32
0110b : SYS_CLK / 64
0111b : SYS_CLK / 128
3-0
1000b : SYS_CLK / 256
1001b : SYS_CLK / 512
1010b : SYS_CLK / 1024
1011b : SYS_CLK / 2048
1100b : SYS_CLK / 4096
1101b : SYS_CLK / 8192
1110b : SYS_CLK / 16384
1111b : SYS_CLK / 32768
Default
Access
0
RW
0
RW
0
RO
0
RW
0
RW
Default
Access
0
RW
For example, if the system clock is 20MHz and Bit[3:0]
=0010b,then the clock source of PWM2 is 5MHz.
REG[8Dh] PWM2 Control Register (P2DCR)
Bit
7-0
Description
PWM Cycle Duty Selection Bit
00h Æ 1 / 256 Duty with PWM2 clock source.
01h Æ 2 / 256 Duty with PWM2 clock source.
02h Æ 3 / 256 Duty with PWM2 clock source.
:
:
FEh Æ 255 / 256 Duty with PWM2 clock source.
FFh Æ 256 / 256 Duty with PWM2 clock source.
PWM Output
PWM CLK
System CLK
2*PWM CLK
256*PWM CLK
Ex : PWM source CLK = System CLK/4 and 2/256 High Period
Figure 5-5 : Duty of PWM
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
REG[8Eh] Memory Clear Control Register (MCLR)
Bit
7
6
5-0
Description
Memory Clear Function
0 : End or Stop. When write 0 to this bit RA8875 will stop the
Memory clear function. Or if read back this bit is 0, it
indicates that Memory clear function is complete.
1 : Start the memory clear function.
Memory Clear Area Setting
0 : Clear the full window. (Please refer to the setting of
REG[14h], [19h], [1Ah])
1 : Clear the active window(Please refer to the setting of
REG[30h~37h]). The layer to be cleared is according to the
setting REG[41h] Bit0.
NA
Default
Access
0
RW
0
RW
0
RO
Default
Access
0
RW
0
RW
0
RW
0
RW
0
RO
0
RW
5-11 Drawing Control Registers
REG[90h] Draw Line/Circle/Square Control Register (DCR)
Bit
7
6
5
4
3-1
0
Description
Draw Line/Square/Triangle Start Signal
Write Function
0 : Stop the drawing function.
1 : Start the drawing function.
Read Function
0 : Drawing function complete.
1 : Drawing function is processing.
Draw Circle Start Signal
Write Function
0 : Stop the circle drawing function.
1 : Start the circle drawing function.
Read Function
0 : Circle drawing function complete.
1 : Circle drawing function is processing.
Fill the Circle/Square/Triangle Signal
0 : Non fill.
1 : Fill.
Draw Line or Square Select Signal
0 : Draw line.
1 : Draw square.
NA
Draw Triangle or Line/Square Select Signal
0 : Draw Line or Square
1 : Draw Triangle
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
(DLHSR, DLVSR)
(DLHSR, DLVSR)
(DLHER, DLVER)
(DLHSR, DLVSR)
(DLHER, DLVER)
(DLHER, DLVER)
Draw Line
Draw Square fill
Draw Square
(DLHER, DLVER)
(DLHER, DLVER)
Radius
Radius
(DCHR, DCVR)
Draw Circle
(DCHR, DCVR)
Draw Circle fill
(DTPH, DTPV)
(DLHSR, DLVSR)
Draw Triangle
(DTPH, DTPV)
(DLHSR, DLVSR)
Draw Triangle fill
Figure 5-6 : Drawing Function Parameter
REG[91h] Draw Line/Square Horizontal Start Address Register0 (DLHSR0)
Bit
7-0
Description
Draw Line/Square Horizontal Start Address[7:0]
Default
Access
0
RW
Default
Access
0
0
RO
RW
Default
Access
0
RW
Default
Access
0
0
RO
RW
Default
Access
0
RW
REG[92h] Draw Line/Square Horizontal Start Address Register1 (DLHSR1)
Bit
7-2
1-0
Description
NA
Draw Line/Square Horizontal Start Address[9:8]
REG[93h] Draw Line/Square Vertical Start Address Register0 (DLVSR0)
Bit
7-0
Description
Draw Line/Square Vertical Start Address[7:0]
REG[94h] Draw Line/Square Vertical Start Address Register1 (DLVSR1)
Bit
7-1
0
Description
NA
Draw Line/Square Vertical Start Address[8]
REG[95h] Draw Line/Square Horizontal End Address Register0 (DLHER0)
Bit
7-0
Description
Draw Line/Square Horizontal End Address[7:0]
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
REG[96h] Draw Line/Square Horizontal End Address Register1 (DLHER1)
Bit
7-2
1-0
Description
Default
Access
0
0
RO
RW
Default
Access
0
RW
Default
Access
NA
0
RO
Draw Line/Square Vertical End Address[8]
0
RW
Default
Access
0
RW
Default
Access
NA
Draw Line/Square Horizontal End Address[9:8]
REG[97h] Draw Line/Square Vertical End Address Register0 (DLVER0)
Bit
7-0
Description
Draw Line/Square Vertical End Address[7:0]
REG[98h] Draw Line/Square Vertical End Address Register1 (DLVER1)
Bit
7-1
0
Description
REG[99h] Draw Circle Center Horizontal Address Register0 (DCHR0)
Bit
7-0
Description
Draw Circle Center Horizontal Address[7:0]
REG[9Ah] Draw Circle Center Horizontal Address Register1 (DCHR1)
Bit
Description
7-2
NA
0
RO
1-0
Draw Circle Center Horizontal Address[9:8]
0
RW
Default
Access
0
RW
Default
Access
0
0
RO
RW
Default
Access
0
RW
REG[9Bh] Draw Circle Center Vertical Address Register0 (DCVR0)
Bit
7-0
Description
Draw Circle Center Vertical Address[7:0]
REG[9Ch] Draw Circle Center Vertical Address Register1 (DCVR1)
Bit
7-1
0
Description
NA
Draw Circle Center Vertical Address[8]
REG[9Dh] Draw Circle Radius Register (DCRR)
Bit
7-0
Description
Draw Circle Radius[7:0]
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
REG[A0h] Draw Ellipse/Ellipse Curve/Circle Square Control Register
Bit
7
6
5
4
Description
Default
Access
0
RW
0
RW
0
RW
0
RW
Draw Ellipse/Circle Square Start Signal
Write Function
0 : Stop the drawing function.
1 : Start the drawing function.
Read Function
0 : Drawing function complete.
1 : Drawing function is processing.
Fill the Ellipse/Circle Square Signal
0 : Non fill.
1 : fill.
Draw Ellipse/ Ellipse Curve or Circle Square Select Signal
0 : Draw Ellipse/ Ellipse Curve.(Depend on bit4)
1 : Draw Circle Square.
Draw Ellipse or Ellipse Curve Select Signal
0 : Draw Ellipse
1 : Draw Ellipse Curve
3-2
NA
0
RO
1-0
Draw Ellipse Curve Part Select(DECP)
0
RW
ELL_B
ELL_A
ELL_B
(DEHR, DEVR)
(DEHR, DEVR)
Draw Ellipse
ELL_A
ELL_B
ELL_A
Draw Ellipse Fill
ELL_A
(DLHSR, DLVSR)
ELL_B
(DLHER, DLVER)
(DLHER, DLVER)
Draw Circle Square
DECP = 2’b01
DECP = 2’b00
DECP = 2’b10
DECP = 2’b11
(DLHSR, DLVSR)
Draw Circle Square Fill
DECP = 2’b01
DECP = 2’b00
Draw Ellipse curve
DECP = 2’b10
DECP = 2’b11
Draw Ellipse curve fill
Figure 5-7 : The Drawing Function
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
REG[A1h] Draw Ellipse/Circle Square Long axis Setting Register (ELL_A0)
Bit
7-0
Description
Default
Access
0
RW
Default
Access
0
RO
0
RW
Default
Access
0
RW
Default
Access
NA
0
RO
Draw Ellipse/Circle Square Short axis[8]
0
RW
Draw Ellipse/Circle Square Long axis[7:0]
REG[A2h] Draw Ellipse/Circle Square Long axis Setting Register (ELL_A1)
Bit
7-2
1-0
Description
NA
Draw Ellipse/Circle Square Long axis[9:8]
REG[A3h] Draw Ellipse/Circle Square Short axis Setting Register (ELL_B0)
Bit
7-0
Description
Draw Ellipse/Circle Square Short axis[7:0]
REG[A4h] Draw Ellipse/Circle Square Short axis Setting Register (ELL_B1)
Bit
7-1
0
Description
REG[A5h] Draw Ellipse/Circle Square Center Horizontal Address Register0 (DEHR0)
Bit
Description
Default
Access
7-0
Draw Ellipse/Circle Square Center Horizontal Address[7:0]
0
RW
REG[A6h] Draw Ellipse/Circle Square Center Horizontal Address Register1 (DEHR1)
Bit
Description
Default
Access
7-2
NA
0
RO
1-0
Draw Ellipse/Circle Square Center Horizontal Address[9:8]
0
RW
REG[A7h] Draw Ellipse/Circle Square Center Vertical Address Register0 (DEVR0)
Bit
7-0
Description
Draw Ellipse/Circle Square Center Vertical Address[7:0]
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Default
Access
0
RW
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
REG[A8h] Draw Ellipse/Circle Square Center Vertical Address Register1 (DEVR1)
Bit
Description
Default
Access
7-1
NA
0
RO
0
Draw Ellipse/Circle Square Center Vertical Address[8]
0
RW
Default
Access
0
RW
Default
Access
REG[A9h] Draw Triangle Point 2 Horizontal Address Register0 (DTPH0)
Bit
7-0
Description
Draw Triangle Point 2 Horizontal Address[7:0]
REG[AAh] Draw Triangle Point 2 Horizontal Address Register1 (DTPH1)
Bit
Description
7-2
NA
0
RO
1-0
Draw Triangle Point 2 Horizontal Address[9:8]
0
RW
Default
Access
0
RW
Default
Access
REG[ABh] Draw Triangle Point 2 Vertical Address Register0 (DTPV0)
Bit
7-0
Description
Draw Triangle Point 2 Vertical Address [7:0]
REG[ACh] Draw Triangle Point 2 Vertical Address Register1 (DTPV1)
Bit
Description
7-1
NA
0
RO
0
Draw Triangle Point 2 Vertical Address [8]
0
RW
Default
Access
0
RW
Default
Access
0
RW
5-12 DMA Registers
REG[B0h] Source Starting Address REG0 (SSAR0)
Bit
Description
7-0
DMA Source START ADDRESS [7:0]
REG[B1h] Source Starting Address REG 1 (SSAR1)
Bit
7-0
Description
DMA Source START ADDRESS [15:8]
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
REG[B2h] Source Starting Address REG 2 (SSAR2)
Bit
7-0
Description
Default
Access
0
RW
Default
Access
0
RW
Default
Access
DMA Source START ADDRESS [23:16]
REG[B4h] Block Width REG 0(BWR0) / DMA Transfer Number REG 0 (DTNR0)
Bit
7-0
Description
When REG[BFh] bit 1 = 0 (Continuous Mode)
DMA Transfer Number [7:0]
When REG[BFh] bit 1 = 1 (Block Mode)
DMA Block Width [7:0]
REG[B5h] Block Width REG 1 (BWR1)
Bit
Description
7-2
NA
0
RO
1-0
DMA Block Width [9:8]
0
RW
Default
Access
0
RW
Default
Access
REG[B6h ] Block Height REG 0(BHR0) /DMA Transfer Number REG 1 (DTNR1)
Bit
7-0
Description
When REG[BFh] bit 1 = 0 (Continuous Mode)
DMA Transfer Number [15:8]
When REG[BFh] bit 1 = 1 (Block Mode)
DMA Block Height [7:0]
REG[B7h] Block Height REG 1 (BHR1)
Bit
Description
7-2
NA
0
RO
1-0
DMA Block Height [9:8]
0
RW
REG[ B8h] Source Picture Width REG 0(SPWR0) / DMA Transfer Number REG 2(DTNR2)
Bit
Description
Default
Access
7-3
DMA Source Picture Width [7:3]
0
RW
2-0
When REG[BFh] bit 1 = 0 (Continuous Mode)
DMA Transfer Number [18:16]
When REG[BFh] bit 1 = 1 (Block Mode)
DMA Source Picture Width [2:0]
0
RW
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
REG[B9h] Source Picture Width REG 1 (SPWR1)
Bit
7-2
1-0
Description
NA
DMA Source Picture Width [9:8]
Source Serial ROM Address
Default
Access
0
0
RO
RW
Default
Access
0
RO
0
RW
0
RW
Destination Display Memory
(CURH, CURV)
SSAR
DMA
Continuous Mode
DNTR
Active Windows
Source Serial ROM Address
Destination Display Memory
SPWR
(CURH, CURV)
SSAR
DMA
BHR
Active Windows
BWR
Block Mode
Figure 5-8 : DMA Continuous and Block Mode
REG[BFh] DMA Configuration REG (DMACR)
Bit
7-2
1
0
Description
NA
DMA Continuous or Block Read/Write Select Bit
0: Continuous / 1: Block
Write FunctionÎ DMA Start Bit
Set to 1 by MCU and reset to 0 automatically
Read FunctionÎ DMA Busy Check Bit
0:Idle / 1:Busy
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
5-13 Key & IO Control Registers
REG [C0h] Key-Scan Control Register 1 (KSCR1)
Bit
Description
Default
Access
7
Key-Scan Enable Bit(KEY_EN)
1 : Enable.
0 : Disable.
0
R/W
6
LongKey Enable Bit
1 : Enable. Long key period is set by KSCR2 bit4-2.
0 : Disable.
0
RW
Key-Scan Data Sampling Times
De-bounce times of scan frequency.
00b : 4
01b : 8
10b : 16
11b : 32
0
R/W
NA
0
RO
0
R/W
Default
Access
Key-Scan Wakeup Function Enable Bit
0: Key-Scan Wakeup function is disable.
1: Key-Scan Wakeup function is enable.
0
R/W
NA
0
RO
0
R/W
0
RO
5-4
3
KF2-0: Key-Scan Frequency
KF2 KF1 KF0
System Clock
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
2-0
Key-Scan Cycle (4x5)
20MHz
40MHz
60MHz
128µs
64µs
42.67us
256µs
128µs
85.33µs
512µs
256µs
170.67µs
1.024ms
512µs
341.33µs
2.048ms 1.024ms 682.67us
4.096ms 2.048ms
1.365ms
8.192ms 4.096ms
2.731ms
16.384ms 8.192ms
5.461ms
REG [C1h] Key-Scan Controller Register 2 (KSCR2)
Bit
7
6-4
Description
Long Key Timing Adjustment
3-2
1-0
System Clock
00b
01b
10b
11b
20MHz
1.25 sec
2.5 sec
3.75 sec
5 sec
40MHz
0.625 sec
1.25 sec
1.875 sec
2.5 sec
60MHz
0.3125 sec
0.625 sec
0.9375 sec
1.25 sec
Numbers of Key Hit.
00b :No key is pressed
01b :One key is pressed, read REG[C2h] for the key code.
10b :Two keys are pressed, read REG[C2h ~ C3h] for the key
codes.
11b :Three keys are pressed, read REG[C2h ~ C4h] for the key
codes.
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
REG [C2h] Key-Scan Data Register (KSDR0)
Bit
7-0
Description
Key Strobe Data0
The corresponding key code 0 that is pressed.
Please refer to section 7-9 for detail description.
Default
Access
NA
RO
Default
Access
NA
RO
Default
Access
NA
RO
Default
Access
0
RO
NA
RW
Default
Access
0
RW
Default
Access
REG [C3h] Key-Scan Data Register (KSDR1)
Bit
7-0
Description
Key Strobe Data1
The corresponding key code 1 that is pressed.
Please refer to section 7-9 for detail description.
REG [C4h] Key-Scan Data Register (KSDR2)
Bit
7-0
Description
Key Strobe Data2
The corresponding key code 2 that is pressed.
Please refer to section 7-9 for detail description.
REG[C7h] Extra General Purpose IO Register (GPIOX)
Bit
7-1
0
Description
NA
The GPIX/GPOX Data Bit
Read: Input data from GPIX pin.
Write: Output data to GPOX pin.
5-14 Floating Window Control Registers
REG [D0h] Floating Windows Start Address XA 0 (FWSAXA0)
Bit
7-0
Description
Floating Windows Start Address XA [7:0]
REG [D1h] Floating Windows Start Address XA 1 (FWSAXA1)
Bit
Description
7-2
NA
0
RO
1-0
Floating Windows Start Address XA [9:8]
0
RW
Default
Access
0
RW
REG [D2h] Floating Windows Start Address YA 0 (FWSAYA0)
Bit
7-0
Description
Floating Windows Start Address YA [7:0]
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Version 1.2
Character / Graphic TFT LCD Controller
REG [D3h] Floating Windows Start Address YA 1 (FWSAYA1)
Bit
7-1
0
Description
NA
Floating Windows Start Address YA [8]
Default
Access
0
0
RO
RW
Default
Access
0
RW
Default
Access
0
0
RO
RW
Default
Access
0
RW
Default
Access
REG [D4h] Floating Windows Width 0 (FWW0)
Bit
7-0
Description
Floating Windows Width Setting [7:0]
REG [D5h] Floating Windows Width 1 (FWW1)
Bit
7-2
1-0
Description
NA
Floating Windows Width Setting [9:8]
REG [D6h] Floating Windows Height 0 (FWH0)
Bit
7-0
Description
Floating Windows Height Setting[7:0]
REG [D7h] Floating Windows Height 1 (FWH1)
Bit
Description
7-2
NA
0
RO
1-0
Floating Windows Height Setting [9:8]
0
RW
Default
Access
0
RW
Default
Access
REG [D8h] Floating Windows Display X Address 0 (FWDXA0)
Bit
7-0
Description
Floating Windows Display X Address [7:0]
REG [D9h] Floating Windows Display X Address 1 (FWDXA1)
Bit
Description
7-2
NA
0
RO
1-0
Floating Windows Display X Address [9:8]
0
RW
Default
Access
0
RW
REG [DAh] Floating Windows Display Y Address 0 (FWDYA0)
Bit
7-0
Description
Floating Windows Display X Address [7:0]
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
REG [DBh] Floating Windows Display Y Address 1 (FWDYA1)
Bit
7-1
0
Description
Default
Access
NA
0
RO
Floating Windows Display Y Address [8]
0
RW
(FWSAXA, FWSAYA)
FWW
(FWDXA, FWDYA)
FWW
FWH
FWH
Floating Windows
Layer2
Layer1
Display Windows
Figure 5-9 : Floating Windows
5-15 Serial Flash Control Registers
SACS_MODE REG [E0h] Serial Flash/ROM Direct Access Mode
Bit
Description
Default
Access
7-1
NA
0: direct access mode disable, then user can use for FONT/DMA
mode.
1: direct access mode enable , then FONT/DMA mode disable
0
RO
0
RW
0
SACS_ADDR REG [E1h] Serial Flash/ROM Direct Access Mode Address
Bit
Description
Default
Access
7-0
Direct access mode Address
Serial Flash/ROM have 24 bit address data, user must be write 3
times E1 for address setting.
0
WO
Default
Access
0
RO
SACS_DATA [E2h] Serial Flash/ROM Direct Access Data Read
Bit
7-0
Description
Direct access mode Read Data buffer
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
5-16 Interrupt Control Registers
REG[F0h] Interrupt Control Register1 (INTC1)
Bit
Description
Default
Access
7-5
NA
KEYSCAN Interrupt Enable Bit
0 : Disable KEYSCAN interrupt.
1 : Enable KEYSCAN interrupt.
DMA Interrupt Enable Bit
0 : Disable DMA interrupt.
1 : Enable DMA interrupt.
Touch Panel Interrupt Enable Bit
0 : Disable Touch interrupt.
1 : Enable Touch interrupt.
BTE Process Complete Interrupt Enable Bit
0 : Disable BTE process complete interrupt.
1 : Enable BTE process complete interrupt.
When MCU-relative BTE operation is selected(*1) and BTE
Function is Enabled(REG[50h] Bit7 = 1), this bit is used to
Enable the BTE Interrupt for MCU R/W:
0 : Disable BTE interrupt for MCU R/W.
1 : Enable BTE interrupt for MCU R/W.
When the BTE Function is Disabled, this bit is used to
Enable the Interrupt of Font Write Function:
0 : Disable font write interrupt.
1 : Enable font write interrupt.
0
RO
0
RW
0
RW
0
RW
0
RW
0
RW
4
3
2
1
0
Note :
1. MCU-relative BTE operations include “Write BTE with ROP”, “Read BTE”, “Transparent Write BTE”,
“Color Expand”, “Color Expand with transparency”.
2. Font Write Interrupt indicates the completion of the font character writing to the DDRAM.
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
REG[F1h] Interrupt Control Register2 (INTC2)
Bit
Description
Default
Access
7-5
NA
Write FunctionÎ KEYSCAN Interrupt Clear Bit
0 : No operation.
1 : Clear the keyscan interrupt.
Read Function Î KEYSCAN Interrupt Status
0 : No keyscan interrupt happens.
1 : Keyscan interrupt happens.
Write FunctionÎ DMA Interrupt Clear Bit
0 : No operation.
1 : Clear the DMA interrupt.
Read Function Î DMA Interrupt Status
0 : No DMA interrupt happens.
1 : DMA interrupt happens.
Write FunctionÎ Touch Panel Interrupt Clear Bit
0 : No operation.
1 : Clear the touch interrupt.
Read Function Î Touch Panel Interrupt Status
0 : No Touch Panel interrupt happens.
1 : Touch Panel interrupt happens.
Write FunctionÎ BTE Process Complete Interrupt Clear Bit
0 : No operation.
1 : Clear BTE process complete interrupt.
Read FunctionÎBTE Interrupt Status
0: No BTE process complete interrupt happens.
1: BTE process complete interrupt happens.
When MCU-relative BTE operation is selected (*1) and BTE
Function is Enabled ( REG[50h] Bit7 = 1 )
Write FunctionÎ BTE Interrupt for MCU R/W Enable Bit
0 : No operation.
1 : Clear BTE MCU R/W interrupt.
Read Function Î BTE R/W Interrupt Status
0: No BTE interrupt for MCU R/W happens.
1: BTE interrupt for MCU R/W happens.
When BTE is not Enable and Text Mode is Enable
Write FunctionÎ Font Write Interrupt (*2) Enable Bit
0 : No operation.
1 : Clear font write interrupt.
Read Function Î Font Write Interrupt Status
0: No font write interrupt happens.
1: Font write interrupt happens.
0
RO
0
RW
0
RW
0
RW
0
RW
0
RW
4
3
2
1
0
Note :
1. MCU-relative BTE operations include “Write BTE with ROP”, “Read BTE”, “Transparent Write BTE”,
“Color Expand”, “Color Expand with transparency”.
2. Font Write Interrupt indicates the completion of the font character writing to the DDRAM.
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
6. Hardware Interface
6-1 MCU Interface
The RA8875 supports 8080 and 6800 series MCU interface, the type of MCU interface is decided by
C86 pin. If C86 pin is set to logic low, then the MCU interface of RA8875 is defined as 8080 series. If
the C86 is connected to logic high, then the MCU interface of RA8875 is used as 6800 series.
Please refer to the Figure 6-1 and Figure 6-2.
8080 MCU
RA8875
A0
A1-A7/A1-A15
IORQ
RS
Decoder
CS#
C86
DB[0-7]/DB[0-15]
DB[0-7]/DB[0-15]
RD
RD#
WR
RES
WR#
RST#
WAIT
WAIT#
GND
INT#
INT
Figure 6-1 : 8080 MCU Interface
6800 MCU
RA8875
A0
A1-A7/A1-A15
VMA
RS
Decoder
VDD
CS#
C86
DB[0-7]/DB[0-15 ]
DB[0-7]/DB[0-15 ]
EN
EN
R/W
RES
RW#
RST#
WAIT
WAIT#
INT#
INT
Figure 6-2 : 6800 MCU Interface
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
6-1-1
Protocol
6-1-1-1 Parallel I/F Protocol
The following timing charts are used to decribe the timing specification of the standard 8080 and
6800 interfaces.
6800 – 8/16-bit Interface
E
tCYC6
tAW6
tEW
R/W
tAH6
A0, CS
tDS6
tDH6
DB[7:0]
(Write)
tACC6
tOH6
DB[7:0]
(Read)
Figure 6-3 : 6800 MCU Waveform
Table 6-1 : 6800 MCU I/F Timing
Symbol
Rating
Parameter
Unit
Min.
Max.
tCYC6
Cycle time
50
--
ns
tEW
Strobe Pulse width
20
--
ns
tAW6
Address setup time
0
--
ns
tAH6
Address hold time
10
--
ns
tDS6
Data setup time
20
--
ns
tDH6
Data hold time
10
--
ns
tACC6
Data output access time
0
20
ns
tOH6
Data output hold time
0
20
ns
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Symbol
tc is one system clock period:
tc = 1/SYS_CLK
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
8080 – 8/16-bit Interface
Figure 6-4 : 8080 Waveform
Table 6-2 : 8080 MCU I/F Timing
Symbol
Rating
Parameter
Unit
Min.
Max.
tCYC8
Cycle time
50
--
ns
tCC8
Strobe Pulse width
20
--
ns
tAS8
Address setup time
0
--
ns
tAH8
Address hold time
10
--
ns
tDS8
Data setup time
20
--
ns
tDH8
Data hold time
10
--
ns
tACC8
Data output access time
0
20
ns
tOH8
Data output hold time
0
20
ns
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Symbol
tc is one system clock period:
tc = 1/SYS_CLK
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
The data bus width of RA8875 can be selected to 8-bit/16-bit by setting the Bit [1:0] of SYSR.
When Bit [1:0] of SYSR is cleared to “00”, then the data bus is 8-bit. If Bit [1:0] of SYSR is set to
“11”, then the data transition is set as16-bit. No matter what type of MCU I/F is selected
(6800/8080), both of them can be changed the bus width when need. But if the 8-bit is used, it
needs double transmission time than 16-bit bus and all of the registers must be accessed by 8bit data.
The continuous data write speed determines the display update speed. The cycle-to-cycle
interval must be larger than 4 times of system clock period. Over the specification may cause
the data lose or function fail. Please refer to Figure 6-5 and Figure 6-6 for waveform detail.
In order to reduce the transmission interference between MCU interface and RA8875, It is
suggested that a small capacitor to the GND should be added at the signal of CS#, RD#, WR#.
If using cable to connect MCU and RA8875, please keep the cable lengh less than 20cm.
Otherwise it’s suggested to add 1~10Kohm pull-up resistors on pins CS#, RD#, WR# and RS.
MPU6800 Data Write Speed Limit
SYS_CLK
RS
WR
RD
ZCS
Min. > 5xSYS_CLK
Figure 6-5 : 6800 I/F Continuous Data Write Cycle Waveform
MPU8080 Data Write Speed Limit
SYS_CLK
RS
WR
RD
ZCS
Min. > 5xSYS_CLK
Figure 6-6 : 8080 I/F Continuous Data Write Cycle Waveform
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RA8875
Version 1.2
6-1-2
Character / Graphic TFT LCD Controller
Serial I/F Protocol
6-1-2-1 3-Wire SPI Interface
RA8875
MPU
VDD
PS
SIFS1
VDD
SIFS0
ZCS
SCS# (ZCS)
SDA
SDO (SDA)
SCK
SCL (SCK)
Figure 6-7 : The MCU Interface Diagram of 3-Wire SPI
RA8875 provides a SPI slave controller. The SPI I/F are available through the chip select line (ZCS),
serial transfer clock line (SCK) and serial input/output line (SDA). SCK is driven by the master
controller, which is used to latch the SDA signal when ZCS is active. The SPI can be configured in
command/data write mode or status/data read mode by setting MSB two bits of first byte of protocol.
Before a data transmission begins, low active ZCS must be set to low, and keep low until the
transmission is finished. When the SPI module is in command/data write mode (Figure 6-8, Figure
6-10), the 2nd byte of the protocol is write data asserted by the master controller via SDA pin. When
the SPI module is in status/data read mode (Figure 6-9, Figure 6-11), the 2nd byte is the read data
or status byte which is sent from RA8875 to the controller via SDA according to the activation of
SCK from the master controller. Please refer to Figure 6-8, Figure 6-9, Figure 6-10 and Figure 6-11
for detail of the SPI protocol.
Transfer End
Transfer Start
SCS#
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
SCL
MSB
SDA
RS RW
0
LSB
DB DB DB DB DB DB DB DB
6
5
4
3
2
1
0
7
REG_DAT/
0
MEM_DAT
FROM MPU TO RA8875
RS 0:Data,
1:COMMAND/STATUS
RW 0:WRITE,
1:READ
FROM RA8875 TO MPU
Figure 6-8 : Date Write on 3-Wire SPI-Bus
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
Transfer End
Transfer Start
SCS#
1
2
3
4
6
5
8
7
1
2
3
4
6
5
8
7
SCL
MSB
SDA
DB DB DB DB DB DB DB DB
7 6
5
4
3
2
1
0
RS RW
0
LSB
1
REG_DAT/
MEM_DAT
RS 0:Data,
1:COMMAND/STATUS
RW 0:WRITE, 1:READ
FROM MPU TO RA8875
FROM RA8875 TO MPU
Figure 6-9 : Data Read on 3-Wire SPI-Bus
Transfer End
Transfer Start
SCS#
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
SCL
MSB
SDA
RS RW
1
LSB
DB DB DB DB DB DB DB DB
6
5
4
3
2
1
0
7
0
REG_NO
RS 0:Data,
1:COMMAND/STATUS
RW 0:WRITE, 1:READ
FROM MPU TO RA8875
FROM RA8875 TO MPU
Figure 6-10 : CMD Write on 3-Wire SPI-Bus
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
Transfer End
Transfer Start
SCS#
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
SCL
MSB
SDA
RS RW
1
DB DB DB DB DB DB DB DB
6
5
4
3
2
1
0
7
1
FROM MPU TO RA8875
LSB
STUS_DAT
RS 0:Data,
1:COMMAND/STATUS
RW 0:WRITE, 1:READ
FROM RA8875 TO MPU
Figure 6-11 : Status Read on 3-Wire SPI-Bus
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
6-1-2-2 4-Wire SPI Interface
MPU
RA8875
VDD
PS
SIFS1
SIFS0
ZCS
SCS# (ZCS)
SDI
SDO
SDO
SDI
SCK
SCL (SCK)
Figure 6-12 : The MCU Interface Diagram of 4-Wire SPI
The 4-wire SPI I/F is similar with 3-wire SPI I/F, the only difference is the data signal. In 3-wire SPI
I/F, the bi-direction SDA signal is used as data and can be driven by slave/master controller. In 4wire SPI I/F. the SDA signal function is separated into SDI and SDO signal. SDI is the data pin from
the SPI master, SDO is the data output from the SPI slave. About the detail protocol, please refer to
Figure 6-13, Figure 6-14, Figure 6-15 and Figure 6-16.
Transfer End
Transfer Start
SCS#
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
SCL
MSB
SDI
DB DB DB DB DB DB DB DB
6
5
4
3
2
1
0
7
RS RW
0
LSB
REG_DAT/
0
MEM_DAT
SDO
RS 0:Data,
1:COMMAND/STATUS
RW 0:WRITE, 1:READ
FROM MPU TO RA8875
FROM RA8875 TO MPU
Figure 6-13 : Date Write on 4-Wire SPI-Bus
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
Transfer End
Transfer Start
SCS#
1
2
3
4
6
5
8
7
1
2
3
4
6
5
8
7
SCL
SDI
RS RW
0
1
MSB
LSB
SDO
DB DB DB DB DB DB DB DB
7 6
5
4
3
2
1
0
REG_DAT/
MEM_DAT
RS 0:Data,
1:COMMAND/STATUS
RW 0:WRITE, 1:READ
FROM MPU TO RA8875
FROM RA8875 TO MPU
Figure 6-14 : Data Read on 4-Wire SPI-Bus
Transfer End
Transfer Start
SCS#
1
2
3
4
5
6
7
8
1
2
3
4
5
6
MSB
RS RW
1
7
8
LSB
DB DB DB DB DB DB DB DB
6
5
4
3
2
1
0
7
0
REG_NO
SDO
RS 0:Data,
1:COMMAND/STATUS
RW 0:WRITE, 1:READ
FROM MPU TO RA8875
FROM RA8875 TO MPU
Figure 6-15 : CMD Write on 4-Wire SPI-Bus
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
Transfer End
Transfer Start
SCS#
1
2
3
4
5
6
7
8
1
2
3
4
6
5
8
7
SCL
SDI
RS RW
1
1
MSB
LSB
SDO
DB DB DB DB DB DB DB DB
7 6
5
4
3
2
1
0
STUS_DAT
FROM MPU TO RA8875
RS 0:Data,
1:COMMAND/STATUS
RW 0:WRITE, 1:READ
FROM RA8875 TO MPU
Figure 6-16 : Status Read on 4-Wire SPI-Bus
6-1-2-3 IIC I/F
MPU
RA8875
VDD
PS
SIFS1
SIFS0
VDD
VDD VDD
1KΩ~10KΩ
IICA1
IICA0
SDA
SDI (SDA)
SCK
SCL (SCK)
50pF
Figure 6-17 : The MCU Interface Diagram of IIC
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
The IIC I/F are accessed by only two bus line, SCK and SDA. It is compatible with standard IIC
interface. The first 7bits of IIC protocol, indicated as the IIC slave address to program in IIC Spec.,
is divided into 2 parts in RA8875. The first 6 bits indicates the IIC device ID of RA8875. The next
1bit is RS bit which indicates the cycle type. For RS = 1, the following cycle is a Command/Status. If
RS = 0, it’s a data cycle. If the MSB 6bits of IIC address (Total 7 bits) match the RA8875 device ID,
the RA8875 IIC slave is active.
The device ID of RA8875 is programmable, but only the 2bits of LSB, which can be set from the
IICA[1:0] pins directly. The other 4 bits of MSB is fixed to 0(Refer to Table 6-3). There are 4 types of
cycles for RA8875: “Command writes cycle”, “Status read cycle”, “Data write cycle”, and “Data read
cycle”. The cycle type is set by the RS bit and RW bit, about the detail protocol, please refer to
Figure 6-18, Figure 6-19, Figure 6-20 and Figure 6-21.
Table 6-3 : IIC DEVICE ID
IICA [5:0]
BIT5
BIT4
BIT3
BIT2
0000b
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BIT1
BIT0
IICA1
IICA0
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
START
STOP
1
2
3
4
5
6
7
8
9
1
2
3
4
5
7
6
8
9
SCL
MSB
SDA
RS RW A
IICA[5:0]
0
S
LSB
DB DB DB DB DB DB DB DB A/A
7
0
6
5
4
3
2
1
0
REG_DAT /
P
MEM_DAT
FROM MPU TO RA8875
RS 0:Data,
1:COMMAND/STATUS
RW 0:WRITE, 1:READ
FROM RA8875 TO MPU
A/A: ACKNOWLEDGE/NOT ACKNOWLEDGE
Figure 6-18 : Data Write on IIC-Bus
START
STOP
1
2
3
4
5
6
7
8
9
1
2
3
4
6
5
7
9
8
SCL
MSB
SDA
RS RW A
IICA[5:0]
0
S
LSB
DB DB DB DB DB DB DB DB A/A
7
6 5 4 3 2 1
0
1
P
REG_DAT /
MEM_DAT
RS 0:Data,
1:COMMAND/STATUS
RW 0:WRITE, 1:READ
A/A: ACKNOWLEDGE/NOT ACKNOWLEDGE
FROM MPU TO RA8875
FROM RA8875 TO MPU
Figure 6-19 : Data Read on IIC-Bus
START
STOP
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SCL
MSB
SDA
IICA[5:0]
RS RW A
1
S
LSB
DB DB DB DB DB DB DB DB A/A
7
0
6
5
4
3
2
1
0
REG_NO
P
FROM MPU TO RA8875
RS 0:Data,
1:COMMAND/STATUS
RW 0:WRITE, 1:READ
FROM RA8875 TO MPU
A/A: ACKNOWLEDGE/NOT ACKNOWLEDGE
Figure 6-20 : CMD Write on IIC-Bus
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
STOP
START
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SCL
MSB
SDA
IICA[5:0]
RS RW
1
S
A
LSB
DB DB DB DB DB DB DB DB A/A
7
0
6
5
4
3
2
1
1
P
STUS_DAT
RS 0:Data,
1:COMMAND/STATUS
RW 0:WRITE, 1:READ
FROM MPU TO RA8875
FROM RA8875 TO MPU
A/A: ACKNOWLEDGE/NOT ACKNOWLEDGE
Figure 6-21 : Status Read on IIC-Bus
6-1-3
Read Status Register
The following Table 6-4 shows that RA8875 can be accessed under 4 different cycles, i.e. “Data
Write”, “Data Read”, “Command Write” and “Status read”. As it is introduced in the Chapter 5,
the status register is a read only register. If MCU executes the read cycle to RA8875 while /RS
pin is setting high, then data of status register will be read back to MCU. Please refer to the
Figure 6-22.
Table 6-4 : Access Cycle of RA8875
RS
WR#
Access Cycle
0
0
Data Write
0
1
Data Read
1
0
CMD Write
1
1
Status Read
RS
CS#
WR#
RD#
DB[7:0]
Status DATA
Status Register Read
Figure 6-22 : Read Status Register
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RA8875
Version 1.2
6-1-4
Character / Graphic TFT LCD Controller
Write Command to Register
RA8875 contains dozens of registers. If users want to write a command into the register of
RA8875, they must execute the command write cycle first, i.e. the address of register, and then
execute the data write cycle for storing a new data into the target register. So “Write Command”
means that it will write a new data into the register. Please refer to the Figure 6-23 (1) for the
related access timing.
RS
CS #
WR#
RD#
DB [7:0]
REG#
DATA
(1) Command Write (Write Data to Regi ster)
RS
CS #
WR#
RD#
DB [7:0]
REG#
DATA
(2) Read Data from Register
Figure 6-23 : Register Write/Register Read
To read the register contents of RA8875, it has to execute the command write cycle first, and
then a “Data Read cycle” follows it. Please refer to the Figure 6-23 (2). But please note that the
Figure 6-23 is based on 8080 interface.
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RA8875
Version 1.2
6-1-5
Character / Graphic TFT LCD Controller
Memory Read / Write Operation
A signal memory(Note) memory read/write operation is composed by two cycles, a command
write cycle to the register “02h” then following a data read/write cycle. The command write cycle
of register “02h”, also called “memory read/write command”, sets RA8875 in memory read/write
mode. The data read/write cycle then performs the data latch/write to memory. When more
memory data are read or written, just doing the data read/write cycle again following the
previous data read/write cycle, don’t need to do the memory read/write command cycle again.
The data read/write cycles can keep doing until completing all data transfers. To note that it’s
not allowed to interlace the data read cycles and data write cycle in the memory read/write
mode. Because the cursor for memory read operation and memory write operation is different.
The data read/write cycles can interleave each other. For the detail description please refer to
the section 7-3. To note that the memory read operation should insert a “dummy read cycle”
before first data is read. The dummy read cycle is a data read cycle, but the data of the dummy
read cycle is un-used. The data read cycles after it will be the correct data. Please refer to the
waveform in Figure 6-24 for detail.
Note : The memory might be Display Data Memory(DDRAM) or Character Generation RAM
(CGRAM).
Figure 6-24 : Memory Write/Memory Read
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RA8875
Version 1.2
6-1-6
Character / Graphic TFT LCD Controller
Interrupt and Wait
RA8875 provides 2 ways of hardware status reporting. Interrupt and polling. For interrupt
method, there is an interrupt pin “INT#” for triggering the external interrupt pin of MCU. For
polling method, it also supports an output signal pin “WAIT#” which can indicate RA8875 is busy
or not. Both of the two signals are both active low. Please refer to the Figure 6-1 and Figure 6-2
for connecting reference.
6-1-6-1 Interrupt
There are five kinds of interrupt events for RA8875, each maps to the corresponding status
bits in REG[F1h]:
‹
‹
‹
‹
‹
‹
The MCU data access for Font or BTE is completed. Bit 0 of REG [F1h] is set to 1.
The font access is completed. Bit 0 of REG [F1h] is set to 1.
The moving/filling BTE function is completed. Bit 1 of REG [F1h] is set to 1.
Touch event occurs. Bit 2 of REG[F1h] is set to 1.
DMA event is completed.
KEYSCAN event is active.
All of the above interrupts function can be enable/disable by setting INTC1(REG[F0h]). In
addition, if the system of customer can not provide the hardware interrupt, RA8875 also
supports a software polling method; MCU can detect the interrupt status through the related
status flag. When hardware interrupts of RA8875 are active, the related interrupt masks
must be disable(Set to 1) first. There is an example for describing the interrupt procedure of
Touch Panel as below :
‹ RA8875 sends an interrupt signal to MCU.
‹ When MCU receives interrupt signal, the program counter (PC) will jump to ISR start
address.
‹ In the mean time, the corresponding interrupt status flag of RA8875 will be set to “1”
(REG[F1h]). For example, when Touch event generates an interrupt, the Touch
Panel Interrupt Status bit will be set to “1”.
‹ After the ISR completes, the status flag should be cleared, i.e., write “1” to the
corresponding bit of status register.
By software interrupt, user can read INTC2 register for detecting interrupt event without any
external device. Besides, Interrupt mask function is only applied to hardware interrupt, not
to INTC2 status flag. It should be noted that, INTC2 status flag must be cleared manually at
the tail of the ISR, i.e., writing the Bit2 of Register INTC2(REG[F1h]) with 1, because the
INTC2 status flag will not be cleared automatically.
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
6-1-6-2 Wait
RA8875 also provides a wait signal, when the busy flag is cleared to “0”, it means that
RA8875 is busy and can not access the DDRAM. There are three ways in which busy may
occur :
1． When RA8875 is set as text mode for writing FONT, RA8875 need different
processing time for differnert FONT sizes to write to DDRAM, RA8875 can’t
receive MCU cycle any more during the time of font writing, because it is in the
status of memory writing busy.
2． When RA8875 is executing the memory clear function, it also generates the write
cycle of memory interface to clear the DDRAM and cause RA8875 is in the status
of memory write busy.
3． When processing BTE move function, RA8875 will automatically executing the
memory read/write cycle, at the time, any DDRAM read/write access by MCU will
cause a BTE fail.
4． When MCU is sending a command, RA8875 needs one system clock to latch the
command, if the clock frequency of MCU is much faster than the one of RA8875;
it is possible that RA8875 meets two or more commands in one system clock. In
the situation, it’s suggested that MCU should check the RA8875 busy status .In
the most other conditions, it doesn’t need to be checked.
If MCU writes data to DDRAM when memory writing busy, it will cause the lost of the writing
data. So user must check the RA8875 busy status in upper 4 situations.
In normally, user can connect “WAIT#” signal to MCU input. It is used for MCU to monitor
the busy status before writing data to RA8875.
RS, CS#
t WST
WR#
DB[7:0]
(Write)
t WAIT
WAIT#
Figure 6-25 : WAIT# Timing Chart
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RA8875
Version 1.2
6-1-7
Character / Graphic TFT LCD Controller
Data Format
6-1-7-1 MCU Data Bus 16- Bit
RA8875 supports the 8-bit/16-bit color depth TFT-LCD Panel, i.e. 256 and 65K colors TFTLCD panel. The RA8875 supports 8/16 bits MCU I/F data bus, when writing to display
memory, the RGB color bit mapping should fit the corresponding format. Please refer to
Figure 6-26.
65K colors
15
0
MPU DATA BUS R4 R3 R2 R1 R0 G5G4G3G2G1G0 B4 B3 B2 B1 B0
256 colors
15
7
MPU DATA BUS
0
R2 R1 R0 G2G1G0 B1 B0
Figure 6-26 : Color illustrations for 16-Bit Data Bus MCU
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
6-1-7-2 MCU Data Bus 8-Bit
The following illustration is used for 8-bit MCU.
65K colors
7
0
MPU DATA BUS R4 R3 R2 R1 R0 G5G4G3
7
1st cycle
0
MPU DATA BUS G2G1G0 B4 B3 B2 B1 B0 2nd cycle
256 colors
7
0
MPU DATA BUS R2 R1 R0 G2G1G0 B1 B0
Figure 6-27 : Color illustrations for 8-Bit Data Bus MCU
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
6-2 Driver I/F Color Setting Mode
There are 16 bits data bus of the logic TFT driver interface of RA8875, supporting up to 65K colors
data format. By the setting of the register, RA8875 can provide 256 colors data format in 16 bit TFT
interface to achieve the same display effect. About the register setting of color mode, please refer to
REG[10h](SYSR) Bit 3-2, the definition of data format is described below.
256 color mode
Color format
7
PDAT[15:0]
0
15
R2 R1 R0 G2G1G0 B1 B0
11 10
5 4
0
R2 R1 R0 R2 R1 G2G1G0G2G1G0 B1 B0 B1 B0 B1
65K color mode
Color format
15
PDAT[15:0]
0
15
R4 R3 R2 R1 R0 G5G4G3G2G1G0 B4 B3 B2 B1 B0
11 10
5 4
0
R4 R3 R2 R1 R0 G5G4G3G2G1G0 B4 B3 B2 B1 B0
Figure 6-28 : Color Mode Setting
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
6-3 LCD Interface
RA8875 supports the 8-bit/16-bit colors format with the panel size of 320x240 with 2 layers display
and up-to 800x480 with 1 layer. RA8875 also supports the 8-bit/16-bit colors format with the panel
size that from 320x240 to 480x272 with 2 layers and the 8-bit colors format with the panel size that
from 640x480 to 800x480 with 2 layers.
RA8875 supports the general digital TFT I/F. By arranging the connection of data bus, it can
correctly works with almost module. Table 6-5 is the interface and connection description for the
digital TFT-LCD module and RA8875. The related waveform timing is described in Figure 6-29.
About the application circuit please refer to Figure 6-30. Besides, the PWM output of RA8875 could
be used to control the LED back-light of TFT Panel. Please refer to Section 6-7 for the detail
description.
Table 6-5 : Digital TFT Interface Description
Pin Name
Type
Pin#
HSYNC
VSYNC
PCLK
DE
PDAT[15]
PDAT[14]
PDAT[13]
PDAT[12]
PDAT[11]
PDAT[10]
PDAT[9]
PDAT[8]
PDAT[7]
PDAT[6]
PDAT[5]
PDAT[4]
PDAT[3]
PDAT[2]
PDAT[1]
PDAT[0]
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
47
48
49
50
69
68
67
66
65
64
63
59
58
57
56
55
54
53
52
51
RAiO TECHNOLOGY INC.
8-bit
R2
R1
R0
G2
G1
G0
B1
B0
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Digital TFT Panel
16-bit
18-bit
HSYNC Pulse
VSYNC Pulse
Pixel Clock
Data Enable
R4
R5, R0
R3
R4
R2
R3
R1
R2
R0
R1
G5
G5
G4
G4
G3
G3
G2
G2
G1
G1
G0
G0
B4
B5, B0
B3
B4
B2
B3
B1
B2
B0
B1
24-bit
R7, R2
R6, R1
R5, R0
R4
R3
G7, G1
G6, G0
G5
G4
G3
G2
B7, B2
B6, B1
B5, B0
B4
B3
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
VPW
VND
VST
VDH
VSYNC
HSYNC
PDATA
LINE
N
LINE
1
LINE
N
DE
HSYNC
HPW
HDW
HND
HST
PCLK
DE
PDATA
Valid Data
Figure 6-29 : Digital TFT Panel Timing
8080 MCU
Digital TFT
Display
RA8875
RS
A0
A1-A7/A1-A15
IORQ
Decoder
CS#
DB[15:0]
DATA[15:0]
RD
RD#
WR
RES
WR#
RST#
WAIT
WAIT#
INT
GND
INT#
C86
VSYNC
VSYNC
HSYNC
HSYNC
DE
PCLK
PDAT[15:0]
DE
CLK
D[15:0]
GPIO0
DISP_OFF
GPIO1
GPIO2
PWM
LCD_RST
PWR_Ctrl
Back light_Ctrl
Figure 6-30 : The Interface of RA8875 and Digital TFT
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
6-4 External Serial Flash/ROM
RA8875 builds in a Serial Flash/ROM interface, supporting for protocol of 4-BUS (Normal Read), 5BUS (FAST Read), Dual mode 0, Dual mode 1, Mode 0 and Mode 3.
Serial Flash/ROM function can be used for FONT mode, DMA mode and Direct Access Mode. FONT
mode means that the external serial Flash/ROM is treated as a source of FONT bitmap. To support
the most useful FONT characters, RA8875 is compatible with the FONT ROM of professional FONT
vendor—Genitop Inc. in Shanghai. About the detail, please refer to the explanation of section 6-4-1.
DMA mode means that the external Flash/ROM is treated as the data source of DMA(Direct Memory
Access). User can speed up the data transfer to display RAM by the mode. The 3rd mode is Direct
Access Mode. External serial Flash/ROM can be accessed directly by the serial interface. For
different Serial Flash/ROM type, RA8875 can set REG [06h] for Serial Flash/ROM Clock that is
RA8875 SFCL pin. Note: When Direct Access mode REG[E0h] enable, then RA8875 will ignore
REG [05h] FONT / DMA setting.
SFCL
SFDI
RA8875
SFDO
SERIAL
ROM 0
SFCS0
SFCS1
SERIAL
ROM 1
Figure 6-31 : RA8875 Serial Flash/ROM System
About Serial Flash/ROM protocol setting, please refer to Table 6-6 as below :
Table 6-6 : Serial Flash/ROM Protocol REG Parameter
Protocol
REG [05h] BIT[3]
REG [05h] BIT [1:0]
4-BUS (Normal Read)
0h
0h
5- BUS (FAST Read)
1h
0h
Dual Mode 0
0h
2h
Dual Mode 1
0h
3h
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
SFCS0
SFCL (MODE3)
SFCL (MODE0)
SFDI
SFDO
Figure 6-32 : Mode 0 and Mode 3 Protocol
8T
24T/32T
8T
8T
SFCS0
SFCL
SFDI
03h
Addr [23:0]/Addr[31:0]
SFDO
D0
D1
D2
If REG[05h] Bit 6 set to 0, Then Addr state will be 24T
If REG[05h] Bit 6 set to 1, Then Addr state will be 32T
Figure 6-33 : 4-BUS (Normal) Read
8T
24T/32T
8T
8T
SFCS0
SFCL
SFDI
0Bh
Dummy
Addr [23:0]/Addr[31:0]
SFDO
D0
D1
If REG[05h] Bit 6 set to 0, Then Addr state will be 24T
If REG[05h] Bit 6 set to 1, Then Addr state will be 32T
Figure 6-34 : 5-BUS (Fast) Read
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
8T
24T/32T
8T
4T
4T
4T
4T
3Bh
Addr [23:0] / Addr [31:0]
Dummy
D0
D1
D2
D3
D0
D1
D2
D3
SFCS0
SFCL
SFDI
SFDO
If REG[05h] Bit 6 setting 0, Then Addr state will be 24T
SFDI
B7
B5
B3
B1
If REG[05h] Bit 6 setting 1 , Then Addr state will be 32T
SFDO
B6
B4
B2
B0
Figure 6-35 : Dual – 0 Read
COMMAND
= BBh
ADDRESS
8T
12T/16T
DUMMY
D0
4T
D1~Dn-1
Dn
4T
4T
SFCS0
SFCL
SFDI
7
6
SFDO
1 0 23 21
31 29
5 3 1
7 5 3 1 7 5 3 1
7 5 3 1
22 20
4 2 0
6 4 2 0 6 4 2 0
6 4
2 0
30 28
If REG[05h] Bit 6 setting 0, Then Addr state will be 12T
If REG[05h] Bit 6 setting 1 , Then Addr state will be 16T
Figure 6-36 : Dual – 1 Read
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RA8875
Version 1.2
6-4-1
Character / Graphic TFT LCD Controller
External Serial Font ROM
The RA8875 supports the various fonts writing to DDRAM by using external Genitop Inc. serial
Font ROM. RA8875 is compatible with the following products of Genitop Inc.,
GT21L16TW/GT21H16T1W, GT23L16U2W, GT23L24T3Y/GT23H24T3Y, GT23L24M1Z, and
GT23L32S4W/GT23H32S4W. This various fonts include 16x16, 24x24, 32x32, and variablewidth font size.
There are 3 types of font code format, 1 byte/2 bytes/4 bytes data, as explained below :
1. 1 byte font code – ASCII code for all font ROMs
2. 4/2 bytes GB font code – The standard decoding of GB18030 in GT23L24M1Z
3. 2 bytes font code + 2 bytes Index code – Only used in UNI-CODE decoding of
GT23L16U2W
4. Other font code length are 2 bytes only
Before adapting the specific font ROM product, it is suggested that user should know the coding
rule of it first. For the detail of the mapping rule and characters set table, please contact with
Genitop Inc.
To note that in GT23L16U2W datasheet, the UNI-CODE font code needs to refer to extra table
called “ZFindex Table” to determine the actually bitmap ROM address, If user write a UNICODE in the range of 00A1h~33D5h or E76Ch~FFE5h, which is a special coding area, then the
extra 2bytes font code is needed for reference of “ZFindex table”. Other UNICODE code outside
the range only need 2 bytes of font code. About the detail, please also refer to the datasheet of
GT23L16U2W.
EX: If user will be written UNI-CODE (00A2) with GT23L16U2W, which is located in the range of
00A1h~33D5h, then MCU must write extra 2 bytes of font code indexed from ZFindex to
RA8875.
1st Byte
00h
2nd Byte
A2h
3rd Byte
00h
ZFindex MSB
4th Byte
01h
ZFindex LSB
Figure 6-37
Note : Other information reference 7-4-2.
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RA8875
Version 1.2
6-4-2
Character / Graphic TFT LCD Controller
External Serial Data ROM
External serial Flash/ROM interface can be treated as the source of data. It can be accessed by
2 methods in RA8875.
‹ DMA (Direct Memory Access) Mode
The serial Flash/ROM interface can be used as the data source of DMA function. The
Flash/ROM is treated as mass data storage. For the detail, please refer to sector 7-10.
‹ Direct Access Mode
The serial Flash/ROM interface also can be directly accessed by RA8875. The address is set by
internal register first. The data of set address then can be read from specific register. Please
refer to the Figure 6-38 program flowchart below.
Start
REG [E1h] Setting
Addr [7:0]
REG [05h]
ROM Protocol
REG [E0h] Enable
Direct Access
Check
Status
BIT0
REG [E1h] Setting
READ REG [E2h]
Addr [23:16]
Read Next Address Data
REG [E1h] Setting
Read Next Data
REG [E0h] Disable
Addr [15:8]
Direct Access
End
Figure 6-38 : Direct Access Mode Flow
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
6-5 Touch Panel I/F
RA8875 includes a built-in 10-bit ADC and control circuits to connect with 4-wire resistive type Touch
Panel. It is composed of two layers extremely thin resistive panel, such as Figure 6-39, there is a
small gap between these two-layer panels. When external force press a certain point, the two-layer
resistive panels will be touched and short, Because the end points of two-layer have electrodes
(XP,XN,YP,YN), such as Figure 6-40, a comparative location will be detected with some switches in
coordination.
YU(YT)
XR
XL
YD(YB)
Figure 6-39 : 4-wire Touch Panel Structure
VDD
YP
XP
XN
VDD
YN
Figure 6-40 : Control Switch of 4-wire Touch Panel
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
Using RA8875 4-wire Touch Panel function only need to connect the Touch Panel signals –
XR,XL,YD,YU to RA8875. It will continuously monitor the panel and wait for touch event. When touch
event is occurred, a divided voltage on panel caused by touch is sensed and transferred by ADC to
determine the location. After the value of X-axis and Y-axis are transferred and stored in
corresponding registers respectively, the Touch Panel controller will issue an interrupt to inform MCU
to process it.
The Figure 6-41 shows application circuit for 4-wire Touch Panel.
The pin ADC_VREF is the reference voltage input of ADC. The Bit5 of Register [71h] is used to
select the reference voltage from external or generated by RA8875. When use external reference
voltage, it need only add two resistors to generated 1/2 VDD (±5%) for ADC_VREF. And have to add
a capacitor (1~10uF) to GND to increase the stability of ADC.
RA8875
VDD
10~100kΩ
VDD
10kΩ
1%
ADC_VREF
10kΩ
1%
Touch Panel
XP
XR
XN
XL
YP
YD(YB)
YN
YU(YT)
1uF
30pFx4
Figure 6-41 : 4-wire Touch Panel Application Circuit
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
6-6 KEYSCAN
RA8875 features with Key-Scan circuit, and could be used as Keyboard function. It will help to
integrate the system circuit that includes keyboard application. The below Figure 6-42 shows the
basic application circuit of 4x5 Key-Pad.
KIN4
KIN3
KIN2
KIN1
KIN0
Column #
RA8875
KOUT0
KOUT1
Row #
KOUT2
KOUT3
Figure 6-42 : 4x5 Key-Pad Application
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
6-7 PWM
RA8875 provides 2 channels programmable PWM (Pulse Width Modulation) for backlight adjustment
or the other application. The PWM frequency and duty can be set by register.
Figure 6-43 shows the reference circuit of PWM contrast backlight application. The PWM duty cycle
varies from 0% to 100% will varies LED current from about 20mA to 0mA.
Figure 6-43 : PWM Reference Circuit for LCD Backlight Brightness Adjustment
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
6-8 Clock and PLL
The system clock of RA8875 is generated by the external crystal connected between pins XI and XO
(15MHz~30MHz). The clock is used as the source of internal PLL circuit to generate the system
clock for RA8875. The PLL output clock frequency is programmable by internal register((REG[88h]
and [89h]). The related description is shown below.
Figure 6-44 : Diagram for RA8875 System Clock
Formula for system clock frequency calculation of RA8875:
System Clock = Y1x ( PLLDIVN [4:0] +1 ) / ( ( PLLDIVM+1 ) x ( 2^PLLDIVK [2:0] ) )
Example:
Y1 = 15MHz
PLLDIVM = 0， ( PLLDIVMÎBit7 of REG[88h] )
PLLDIVN [4:0] = 01001b， ( PLLDIVNÎBit[4:0] of REG[88h] )
PLLDIVK [2:0] = 001b， ( PLLDIVKÎBit[2:0] of REG[89h] )
System Clock = 15MHz x ( 9+1 ) / ( ( 0+1 ) x ( 2^1 ) )
= 15MHz x10 / 2
= 75MHz
The default value of system clock frequency (SYS_CLK) is set as the same as the frequency of
external crystal (Fin). And it should be noted that, when REG[88h] or REG[89h] is programmed, to
make sure that the stability of the PLL output, a period of "frequency and phase lock time"(About
<30us) must be waited to complete the procedure of PLL frequency modification.
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
RA8875 supports the variety of LCD modules; the setting of clock depending on different resolution
of LCD module is listed at below table.
Table 6-7 : Clock Setting for Different Display Application
Display
Resolution
320x240
320x480
480x272
640x480
640x480
800x480
800x480
RAiO TECHNOLOGY INC.
Layer
No.
2
2
2
2
1
2
1
Color Depth
( Bits )
16
16
16
8
16
8
16
Frame
Hz )
60
60
60
60
60
60
60
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Pixel Clock ( PCLK )
6.4MHz
12.8MHz
9MHz
25MHz
25MHz
30~33MHz
30~33MHz
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
6-9 Reset
Before programming the RA8875, it’s suggested that a reset process should be done. The RA8875
requires a reset low pulse at least 1024 external crystal clock periods after power-on in order to reinitialize its internal state. If the external crystal frequency is 25MHz, then the Reset pulse is at least
40.96µs. For reliability consideration, it is not recommended to apply a DC voltage to the LCD panel
while the RA8875 is reset. Turn off the LCD power supplies for at least one frame period after the
start of the reset pulse.
Figure 6-45 : Suggestion circuit for RST# Pin
Figure 6-45 is an example for Reset application circuit. It could be controlled by MCU such as (1) of
Figure 6-45, or generated by a RC circuit such as (2) of Figure 6-45.
The RA8875 cannot receive commands while it is reset. Commands to initialize the internal registers
should be issued after the reset process complete. During period of ZRST keeping low, the LCD
driver signals such as PDATA, HSYNC and VSYNC may be halted and kept as L or H. A delay of
1ms (minimum) is required following the rising edges of RST# to allow for system stabilization.
Please refer to Figure 6-46 for more detail description.
Figure 6-46 : Reset Timing
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
When reset RA8875 (RST# = Low), please refer to Table 6-8 for the status of relative output signal.
Table 6-8 : The Reset Status of Relative Output Signal
RAiO TECHNOLOGY INC.
Signal Name
Output Status
WAIT#, INT#
High
PWM1, PWM2
Low
PDAT[15:0]
Low
VSYNC, HSYNC
High
PCLK, DE
Low
KOUT[3:0]
Low
GPOX
Low
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
6-10 Power
6-10-1 Power Pin Description
RA8875 operates at 3.3V IO power and 1.8V core power. User can provide the 3.3V only for
chip LDO source and ADC/DAC/OSC IO signals. The internal LDO will generate the 1.8V power
source for internal core circuit. For the reason of chip reliability, it is not suggested to connect
the LDO output as the power source of other devices. For the detailed description, please refer
to Section 4-8.
6-10-2 Power Architecture
The architecture of the power is depicted below Figure 6-47. Note that for each power pad, the
bypass capacitors are suggested to add beside the pad as near as possible. It is recommended
to connect a 1uF bypass capacitor individually at the LDO output - LDO_CAP and LDO_OUT for
more stable power supply.
3.3V
0.1uF
3.3V
OSC_VDDP
ADC_VDD
OSC_GNDP
0.1uF
ADC
OSC_VDD
OSC_GND
0.1uF
VDDP
0.1uF
LDO_OUT
ADC_GND
0.1uF
OSC & PLL
GND
LDO
LDO_GND
0.1uF
VDDP
CORE
GND
0.1uF
CORE_VDD
Figure 6-47 : The Power Connection for RA8875
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
7. Function Description
7-1 Scroll Function
The RA8875 provides both horizontal scroll and vertical scroll function. By programming the “Offset
Value” of the display in the scroll window, the display can be shifted as the programmed offset and
that area that is shifted out of the right boundary will be “scrolled” cross the window and be displayed
from the starting of the display window, just like the effect of “scrolling”.
7-1-1
Scroll Window & Scroll Offset
The scroll window defines the range of scrolling function. The scroll offset defines the scroll effect of
the scroll windows. The display inside the range will be shifted with a scroll offset setting in the unit of
pixel. To increasing or decreasing the scroll offset by register will cause the effect of “scrolling”. The
area outside the range will not be affected by the “scroll offset”. The scroll window is set by two
points in display area, i.e., start point and end point. The start/end point is indicated by the method of
coordination. For the registers of scroll window and scroll offset. Please refer to Table 7-1 below.
Note that HSSW must be smaller than HESW, and VSSW must be smaller than VESW or the scroll
function will not be correct.
Table 7-1 : Scroll Window Setting Register
Reg. NO.
Abbreviation
Description
38h, 39h
HSSW[9:0]
Horizontal Start Point of Scroll Window
3Ah, 3Bh
VSSW[8:0]
Vertical Start Point of Scroll Window
3Ch, 3Dh
HESW[9:0]
Horizontal End Point of Scroll Window
3Eh, 3Fh
VESW[8:0]
Vertical End Point of Scroll Window
Table 7-2 : Scroll Offset Setting Register
7-1-2
Reg. NO.
Abbreviation
24h, 25h
HOFS[10:0]
26h, 27h
VOFS[9:0]
Description
Horizontal Scroll Offset Register
Vertical Scroll Offset Register
Horizontal Scroll & Vertical Scroll
The RA8875 provides horizontal scroll feature. Users could flexibly assign the scrolling window
in the display area and by increasing or decreasing the value of horizontal offset as the unit of
pixels. Users can achieve the effect of block scrolling. Please refer to Figure 7-1 as the display
example.
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
RAiO
RAiO
RAiO
．．．
O
RAi
Figure 7-1 : Horizontal Scroll
Note : The value of offset HOFS must smaller then HESW - HSSW.
The vertical scroll feature is similar with the function of horizontal scroll. The difference is the
method of registers setting. Change the horizontal offset cause the horizontal scroll and
changing the vertical offset will cause the vertical scroll effect. Please refer to Figure 7-2 as a
vertical display example. Note that the horizontal offset & vertical offset can be set
simultaneously, i.e. 2 dimensions motion display.
RAiO RA8875
RAiO RA8875
RAiO
RAiO
RA8875
．．．
RA8875
RA8875
Figure 7-2 : Vertical Scroll Offset
Note : The value of offset VOFS must small then VESW - VSSW .
7-1-3
Layer Mixed Scroll
Layer mixed scroll function is similar to the scroll function described in previous sections. There
are four kinds of layer mixed scroll mode for user to apply. Only layer 1 scrolling, only layer 2
scrolling, two layers scrolling simultaneously and scrolling with layer 2 as a buffer. About the
register setting, please refer to Table 7-3 below.
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
Table 7-3 : Register Setting for Scroll Function.
Reg. NO.
Abbreviation
Description
Layer Transparency Register 0
B[7:6]Layer 1/2 Scroll mode
00b:Layer 1/2 scroll simultaneously.
LTPR0
01b:Only Layer 1 scroll
10b:Only Layer 2 scroll
11b:Buffer scroll (use Layer 2 as buffer)
52h
7-1-3-1 Layer 1/2 Scroll Simultaneously
When layer 1/2 scroll mode is set to 00b, users could flexibly assign the scrolling range in the
display area and by increasing or decreasing the value of offset(*Note) as the unit of pixels and
layer 1/2 will scroll at the same time The layer 1 and 2 overlay type is set by the LTPR0[2:0].
Note that if “Layer 1/2 scroll at the same time” is set, and LTPR0[2:0] is set as “only layer 1 is
visible” or “Only layer 2 is visible”, then only one layer will display. The display effect please
refers to the example of Figure 7-3.
RAiO
Layer 1
+
Layer 2
= RAiO
RAiO
RAiO
RAiO
…
RAiO
Layer 1/2 scroll at the same time
Figure 7-3 : The Effect of Layer 1/2 Scroll Simultaneously
7-1-3-2 Only Layer 1 Scroll
When LTPR0[7:6] is set to 01b, only the layer 1 is displayed in scroll window. So adjusting the
display effect please refers to the example of Figure 7-4.
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
RAiO
Layer 1
+
Layer 2
= RAiO
RAiO
RAiO
RAiO
…
RAiO
Only Layer 1 scroll
Figure 7-4 : The Effect of Only Layer 1 Scroll
7-1-3-3 Only Layer 2 Scroll
When LTPR0[7:6] is set to 10b, only the layer 2 is displayed in scroll window. Similar with layer
1 only display, it provides the flexibility for different applications. About the display effect please
refer to the example of Figure 7-5.
RAiO
Layer 1
+
Layer 2
= RAiO
RAiO
RAiO
RAiO
…
RAiO
Only Layer 2 scroll
Figure 7-5 : The Effect of Only Layer 2 Scroll
Note : The value of offset HOFS(REG[24h-25h]) must smaller then HESW – HSSW and the
value of offset VOFS(REG[26h-27h]) must small then VESW - VSSW.
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
7-1-3-4 Buffer Scroll (Layer 2 is used as Scroll Buffer)
When LTPR0[7:6] is set to 11b, the buffer scroll mode is set. The memory area inside the scroll
window for layer 1 and layer 2 is treating as a continuous memory for scroll display. No matter
horizontal or vertical. The scroll horizontal/vertical offset(*Note) can be set as two times of the
width or the length of the scroll window. It is useful for real application because there is always a
block of scroll area is invisible. User can update it when it’s invisible so the scroll effect will be
smoothly going. For the effect example, please refer to Figure 7-6.
RAiO
Layer 1
Layer 2
RAiO
O
…
RAiO
…
RAiO
Buffer scroll (use Layer 2 as buffer)
Figure 7-6 : The Effect of Buffer Scroll
Note : The value of offset HOFS(REG[24h-25h]) must be 0 ≦ HOFS ≦ (2{ HESW – HSSW} +
1) and the value of offset VOFS(REG[26h-27h]) must be 0 ≦ VOFS ≦ (2{ VESW –
VSSW} + 1).
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
7-2 Active Window
7-2-1
Active Window for Font Write
When executing the font write function in RA8875, the boundary of characters write will be
dominated by a window area called “Active Window”. The font write direction is left to right then
top to bottom as default. When the written character is met the horizontal right boundary, then
the font write cursor will jump to the left boundary of next line. If the next line position crosses
the bottom boundary. The cursor will jump to the starting of the window, i.e. the left and top
boundary. Figure 7-7 shows the effect of font write in active window. To note that, if the font
write cursor is set outside the area of active window, the character still writes at the position of
font write cursor. Until the right boundary or the display boundary is met. When it is met, the font
write cursor will change line then follows the rule of active window. Please refer to the Figure 7-8
as an example.
RA8875 is a text/graphic mixed disp
lay with 2 layers
Active window
Figure 7-7 : The Font Write Effect in Active Window
RA8875 is a text/graphic mixed display wit
h 2 layers
Touch the Active window
Active window
Figure 7-8 : The Font Write Effect when Font Write Cursor is Outside the Active Window
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RA8875
Version 1.2
7-2-2
Character / Graphic TFT LCD Controller
Active Window for Geometric Input
Active window also dominates the drawing area for geometric input function. Only the part of the
active window will be drawn. Please refer to Figure 7-9 as an example.
Over the Active Window,
will not be draw
Within the Active Window,
will be draw
Active window
Figure 7-9 : A Line Drawing Example with Active Window
Note: The active window function for geometric has 2 exceptions as below.
1. When drawing ellipse, the active window is not supported.
2. When drawing circle, assume that the circle center is (X, Y) and the circuit radius is R, with
the condition of Y + R >= 512, the active window for the function will not be active.
7-2-3
Active Window for DMA
Active window also provides the boundary for DMA function. The destination of the DMA
function is set by active window. To note that if the sources of DMA function defines bigger area
than the area of active window. The data will be overlaid from the beginning of the active
window. About the detail, please refer to section 7-10 description.
7-2-4
Active Window for Memory Write
When executing the memory write function in RA8875, the boundary of the function will be also
dominated by Active Window. The memory write direction is left to right then top to bottom as
default. When the written character is met the horizontal right boundary, then the font write
cursor will jump to the left boundary of next line. If the next line position crosses the bottom
boundary. The cursor will jump to the starting of the window, to note that, if the memory write
cursor is set outside the area of active window, it still writes at the position of memory write
cursor. Until the right boundary or the display boundary is meet. When it is met, the memory
write cursor will change line then follows the rule of active window.
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
7-3 Cursor & Pattern
According to different applications, RA8875 provides flexibility and powerful functions of cursor and
pattern. There are four kinds of cursors defined in RA8875, i.e. graphic cursor; memory read cursor,
memory write cursor and font write cursor. The graphic cursor provides a 32x32 pixels graphic cursor
which can be displayed at user-defined position. When the position is changed, the graphic cursor is
moved. The memory read cursor and memory write cursor is for the use of memory read/write. The
memory read/write cursor position move automatically after memory read/write cycle. The memory
write cursor defines the position that the data is written by memory write operation and read cursor is
defined separately that the data in it is read by memory read operation.
The memory write cursor defines the location that the data will be written in. The memory read
cursor and memory write cursor can be set as automatic moving or not separately. Also the move
directions of them can be individually programmed. The default settings of both are auto-increasing
with the direction left to right, top to down. To note that only the memory write cursor is visible. The
memory read cursor can’t be displayed in the panel. The font write cursor provides a text relative
cursor for font write function. The shape of it is a block and the height and width is programmable.
The display location of font write cursor indicates the location of text being currently written.
Besides, RA8875 also support the “Pattern” function. The “Pattern” is a print with 8x8/16x16 pixels of
size and at most 16bpp color depth for each pixel. The colors depth of pattern follows the setting of
REG[10h] bit 3-2. By operating with the BTE function, it can be used to duplicate and fill a print in a
specific area. And speed up the repeating writing operation and reduce the loading of MCU.
7-3-1
Cursor Type
7-3-1-1 Graphic Cursor
The size of graphic cursor is 32x32 pixels, each pixel is composed by 2-bit, which indicates 4
colors setting (color 0, color 1, background color, the inversion of background color). It
represents that a graphic cursor takes 256 bytes(32x32x2/8). RA8875 provides eight groups of
graphic cursor for selection; users could use them just by setting related registers. By the way,
the graphic cursor position is controlled by register GCHP0 (REG[80h]), GCHP1(REG[81h]),
GCVP0(REG[82h]) and GCVP1(REG[83h]). The color of it is set by register GCC0(REG[84h])/
GCC1(REG[85h])/ Background color/ Inversion of Background color, depending on the data of it.
Please refer to Figure 7-10 example for the detail explanation.
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
2 Bits Represent 1 Pixel
Pixel Color
00b
GCC0 (REG[84h])
01b
GCC1 (REG[85h])
10b
Background Color
11b
The Inversion of Background Color
0
1
GCC0 Color
GCC1 Color
Background Color
~Background Color
...
...
256 Bytes
0 0 0 1 0 0 0 1
2 Bits Represent 1 Pixel
255 0 1 0 1 0 0 0 0
Figure 7-10 : Relation of Memory Mapping for Graphic Cursor
Usage :
1. Setting up GCC0 color and GCC1 color by setting register GCC0[REG[84h] and
register GCC0[REG[85h].
2. Setting MWCR1(REG[41h]) to select graphic cursor set and change write destination
selection to “Graphic Cursor”.
3. Using graphic mode to write data into graphic cursor storage space.
4. Enable graphic cursor(REG[41h] Bit7).
5. Writing to GCHP0(REG[80h]), GCHP1(REG[81h]), GCVP0(REG[82h]) and
GCVP1(REG[83h]) to change graphic cursor position. The Figure 7-11 shows the
display with graphic cursor.
RA8875
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Figure 7-11 : The Display with Graphic Cursor
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
7-3-1-2 Memory Read Cursor
Memory read cursor is the location of memory for memory read operation. The memory read
cursor is invisible. The location of it is independent with memory write cursor and font write
cursor. It can be set as auto-increasing or not auto-increasing. Four directions of the cursor
moving option can be set. To note that the memory read cursor is available for graphic mode or
text mode. Please refer to Table 7-4 below for description.
Table 7-4 : Memory Read Cursor Related Register Table
Register Name Bit Num
7
MWCR0
0
MRCD
1-0
RCURH0/1
RCURV0/1
9-0
8-0
Function Description
Text Mode Enable
0 : Graphic mode.
1 : Text mode.
Memory Read Cursor Auto-Increase Disable
Memory Read Direction
00b : Left Æ Right then Top Æ Down.
01b : Right Æ Left then Top Æ Down.
10b : Top Æ Down then Left Æ Right.
11b : Down Æ Top then Left Æ Right.
Memory Read Cursor Horizontal Location
Memory Read Cursor Vertical Location
Address
[40h]
[45h]
[4Ah]、[4Bh]
[4Ch]、[4Dh]
7-3-1-3 Memory Write Cursor
Memory write cursor is the location of memory for memory write operation in graphic mode. The
memory write cursor is visible. The location of it is independent with memory read cursor and
font write cursor. It can be set as auto-increasing or not auto-increasing and blink or not. Four
directions of the cursor moving option can be set. Please refer to Table 7-5 below for description.
Table 7-5 : Memory Write Cursor Related Register Table
Register
Name
Bit Num
7
6
MWCR0
5
3-2
1
CURH0/1
CURV0/1
9-0
8-0
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Function Description
Address
Text Mode Enable
0 : Graphic mode.
1 : Text mode.
Font Write Cursor/ Text Write Cursor Enable
0 : Font write cursor/ Text Write Cursor is not visible.
1 : Font write cursor/ Text Write Cursor is visible.
Font Write Cursor/ Text Write Cursor Blink Enable
0 : Normal display.
[40h]
1 : Blink display.
Memory Write Direction (Only for Graphic Mode)
00b : Left Æ Right then Top Æ Down.
01b : Right Æ Left then Top Æ Down.
10b : Top Æ Down then Left Æ Right.
11b : Down Æ Top then Left Æ Right.
Memory Write Cursor Auto-Increase Disable
0 : Cursor auto-increases when memory write.
1 : Cursor doesn’t auto-increases when memory write.
[46h]、[47h]
Memory Write Cursor Horizontal Location
[48h]、[49h]
Memory Write Cursor Vertical Location
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
7-3-1-4 Font Write Cursor
Font write cursor is used only in text mode. It is visible. The location of it can be set
independently from memory read cursor and font write cursor. Similar with the memory write
cursor, the font write cursor can also be set as auto-increasing or not auto-increasing and blink
or not. Cursor auto-move function is dominated by the active window. When a text is write, the
cursor automatically move to next position for font writing. It depends on the font size and font
direction. When meeting the boundary of active window. Cursor will change to next row. The
interval between the rows can also be set in pixels. Table 7-6 list the relative registers
description.
Table 7-6 : Font Write Cursor Related Register Table
Register
Name
Bit Num Function Description
Address
FLDR
4-0
Font Line Distance Setting Register(FLDR)
CURH0/1
9-0
Font Write Cursor Horizontal Location
[2Ah]、[2Bh]
CURV0/1
8-0
Font Write Cursor Vertical Location
[2Ch]、[2Dh]
7
MWCR0
6
5
7-3-2
Text Mode Enable
0 : Graphic mode.
1 : Text mode.
Font Write Cursor/Memory Write Cursor Enable
0 : Font write cursor/Memory Write Cursor is not visible.
1 : Font write cursor/Memory Write Cursor is visible.
Font Write Cursor/Memory Write Cursor Blink Enable
0 : Normal display.
1 : Blink display.
[29h]
[40h]
Cursor Attribute
7-3-2-1 Cursor Blinking
The memory write cursor and font write cursor can be set as on or off or blinking with a fixed
frequency. Both of them are controlled by same register. The control register is
MWCR0(REG[40h]). The effect of blinking is repeating the cursor on(visible) and
off(invisible). The blinking time of it is programmable and can be calculated as the formula
below in unit of second.
Blink Time (sec) = BTCR[44h]x(1/Frame_Rate).
Figure 7-12 show the example of cursor blink. The cursor position will follow the last data or
character be written.
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Figure 7-12 : Cursor Blinking
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
7-3-2-2 Cursor Height and Width
Besides the graphic cursor and memory read cursor, the shape of the other 2 cursors is
programmable. The font write cursor is a block with height and width programmable. The
control register is CURHS(REG[4Eh]) and CURVS(REG[4Fh]). The memory write cursor is a
line with width programmable and height fixed to 1 pixel. The width control register is the
same as font write cursor, i.e. CURHS(REG[4Eh]). Please refer to Figure 7-13 and Figure
7-14 below. The height and width of font write cursor is also relative with an extra factors, the
font enlargement setting(REG[2Eh] Bit3~0). With the enlargement factor of 1, the width is set
by CURHS/CURVS as 1~32 pixels. For enlargement factor is not 1, the real width and height
of the cursor will be multiplied with the factor. Figure 7-13 is the example as font
horizontal/vertical enlargement factor is 1. Note that the font writes cursor will not affected by
the font rotation, if the font is rotated with 90 degree. The shape of font write cursor is still the
same with the normal one. About the display please refer to Figure 7-16 and Figure 7-16
below as examples.
REG[4Eh] Font Write Cursor and Memory Write Cursor Horizontal Size Register (CURHS)
CURHS[4:0]
Width (Unit : Pixel)
00000b ~ 11111b
1 ~ 32
1 pixel
2-pixel
3-pixel
32-pixel
REG[4Fh] Font Write Cursor Vertical Size Register (CURVS)
CURVS[4:0]
Height (Unit : Pixel)
00000b ~ 11111b
1 ~32
1 pixel
2-pixel
3-pixel
32-pixel
Figure 7-13 : Font Write Cursor Height and Width Setting
REG[4Eh] Font Write Cursor and Memory Write Cursor Horizontal Size Register (CURHS)
CURHS[4:0]
Width (Unit : Pixel)
00000b ~ 11111b
1 ~ 32
1 pixel
2-pixel
3-pixel
32-pixel
Figure 7-14 : Memory Write Cursor Width Setting
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
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Figure 7-15 : Font Write Cursor Movement for Normal Font
Figure 7-16 : Font Write Cursor Movement for Vertical Font
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RA8875
Version 1.2
7-3-3
Character / Graphic TFT LCD Controller
Pattern
The RA8875 includes a pattern memory for pattern function. The data in the memory defines the
“pattern data”, a bitmap description for a figure. When 2D pattern relative function is active, the
specified pattern memory data will fill in specified area.
User can use REG[41h] to assign pattern memory to program, and use REG[66h] to specify
pattern format and pattern number to access. The RA8875 supports 8x8/16x16 pixels pattern
format. If pattern format is 8x8 pixels, then RA8875 can define at most 16 patterns for user’s
request. If pattern format is 16x16 pixels, then RA8875 can only define 4 patterns for user’s
request. The pattern number and pattern format will decide the memory location for accessing
pattern.
Pattern Memory
RA8875
8-bit /16-bit
Logic
MCU
8-bit /16-bit
REG[41h] bit3-2=Pattern
REG[66h] =Pattern No
Figure 7-17 : Pattern Initial
Table 7-7 : Related Register Table
Register Name
Bit Num
Function Description
Address
MWCR1
3-2
[41h]
PTNO
7-0
Memory control register for setting pattern
memory to access.
Pattern Number, the index of pattern for
MCU to access pattern memory
[66h]
About the detail of pattern function, please refer to Section 7-6 BTE function.
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
7-4 Font
7-4-1
Internal Font ROM
The RA8875 embedded 8x16 dots ASCII Font ROM that provides user a convenient way to
input characters by code. The embedded character set supports ISO/IEC 8859-1~4 coding
standard. Besides, user can choose the font foreground color by setting the REG[60h~62h] and
background color by setting the REG[63h~65h]. For the procedure of characters writing please
refers to below figure:
Text mode
REG[40h] bit7=1
Background color
Internal Font ROM Select
REG[21h] bit7=0, bit5=0
Foreground color
Font foreground and background color Select
REG[63h~65h], REG[60h~62h]
Write the font Code
CMD_WR[02h]
DATA_WR[font_code]
Figure 7-18 : ASCII Font ROM Programming Procedure
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
Table 7-8 shows the standard character encoding of ISO/IEC 8859-1. ISO means International
Organization for Standardization. The ISO/IEC 8859-1, generally called “Latin-1”, is the first 8-bit
coded character sets that developed by the ISO. It refers to ASCII that consisting of 192
characters from the Latin script in range 0xA0-0xFF. This character encoding is used throughout
Western Europe, includes Albanian, Afrikaans, Breton, Danish, Faroese, Frisian, Galician,
German, Greenlandic, Icelandic, Irish, Italian, Latin, Luxembourgish, Norwegian, Portuguese,
Rhaeto-Romanic, Scottish Gaelic, Spanish, Swedish. English letters with no accent marks also
can use ISO/IEC 8859-1.
In addition, it is also commonly used in many languages outside Europe, such as Swahili,
Indonesian, Malaysian and Tagalong.
Table 7-8 : ASCII Block 1(ISO/IEC 8859-1)
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
Table 7-9 shows the standard characters of ISO/IEC 8859-2. ISO/IEC 8859-2 also cited as
Latin-2 is the part 2 of the 8-bit coded character sets developed by ISO/IEC 8859. These code
values can be used in almost any data interchange system to communicate in the following
European languages: Croatian, Czech, Hungarian, Polish, Slovak, Slovenian, and Upper
Sorbian. The Serbian, English, German, Latin can use ISO/IEC 8859-2 as well. Furthermore it is
suitable to represent some western European languages like Finnish (with the exception of å
used in Swedish and Finnish)
Table 7-9 : ASCII Block 2 (ISO/IEC 8859-2)
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
Table 7-10 shows the standard characters of ISO/IEC 8859-3. ISO/IEC 8859-3 also known as
Latin-3 or “South European” is an 8-bit character encoding, third part of the ISO/IEC 8859
standard. It was designed originally to cover Turkish, Maltese and Esperanto, though the
introduction of ISO/IEC 8859-9 superseded it for Turkish. The encoding remains popular with
users of Esperanto and Maltese, though it also supports English, German, Italian, Latin and
Portuguese.
Table 7-10 : ASCII Block 3 (ISO/IEC 8859-3)
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
Table 7-11 shows the standard characters of ISO/IEC 8859-4. ISO/IEC 8859-4 is known as
Latin-4 or “North European” is the forth part of the ISO/IEC 8859 8-bit character encoding. It was
designed originally to cover Estonian, Greenlandic, Latvian, Lithuanian, and Sami. This
character set also supports Danish, English, Finnish, German, Latin, Norwegian, Slovenian, and
Swedish.
Table 7-11 : ASCII Block 4 (ISO/IEC 8859-4)
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RA8875
Version 1.2
7-4-2
Character / Graphic TFT LCD Controller
External Font ROM
External serial ROM interface is a flexible way for RA8875 to provide more characters set for
different applications. It is compatible with a serial of font ROM of Genitop Inc., which is a
professional font ROM vendor. The supporting product numbers are GT21L16TW,
GT23L16U2W, GT23L24T3Y, GT23L24M1Z, and GT23L32S4W. According to different product,
there are different font’s size including 16x16, 24x24, 32x32, and variable width font size in them.
The REG[06h] provides user modulating the speed of access external serial Flash/ROM cycle
speed so that can match the ROM require access timing. The procedure of writing font just
refers to below figure:
Text mode
REG[40h] bit7=1
Background color
External Font ROM Select
REG[21h] bit7=0, bit5=1
Foreground color
External Font ROM Cycle Speed Select
REG[06h]
External Font ROM type and font type select
REG[05h], REG[2Eh], REG[2Fh]
Font foreground and background color Select
REG[63h~65h], REG[60h~62h]
Write the font code
CMD_WR[02h]
DATA_WR[font_code0]
DATA_WR[font_code1]
DATA_WR[font_code3]
Figure 7-19 : External Font ROM Programming Procedure
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RA8875
Version 1.2
7-4-3
Character / Graphic TFT LCD Controller
CGRAM
The RA8875 supports 256 half size space that lets user can create fonts or symbols they want.
User just writes the font or symbol data to the indicated space and then writes the
corresponding font code, RA8875 will write the font or symbol to the DDRAM. Also, user can
choose the font foreground color by setting the REG[63h~65h] and background color by setting
the REG[60h~62h].The procedure of creating and writing just refers to below figure:
1.Create the font or symbol
2.Write the font or symbol to display RAM
Graphic mode
REG[40h] bit7=0
Text mode
REG[40h] bit7=1
CGRAM Space Select
REG[23h]
CGRAM Select
REG[21h] bit7=1
Write to the CGRAM
REG[21h] bit7=0
REG[41h] bit3=0,bit2=1
Write to the Bank1 or Bank2
REG[41h] bit3=0,bit2=0
Write the font or symbol data
CMD_WR[02h]
DATA_WR[data0]
DATA_WR[data1]
I
DATA_WR[data15]
Write the font or symbol
CMD_WR[02h]
DATA_WR[font_code]
Figure 7-20 : CGRAM Programming Procedure
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
CGRAM space
CGRAM NO = 0x02
data0
data1
CGRAM NO 0x00 0x01 0x02 0x03
0xFE 0xFF
data15
CGRAM NO = 0x03
data0
data1
1.
Display RAM
data15
1.Write half size CGRAM font
(DATA_WR[00h])
2.
2.Write two half size CGRAM font
(DATA_WR[02h], DATA_WR[03h])
Background color
foreground color
Figure 7-21 : CGRAM Description
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RA8875
Version 1.2
7-4-4
Character / Graphic TFT LCD Controller
90 Degree Font
The RA8875 supports the 90 degree font write by setting the REG[22h] Bit4 = 1. And collocating
the VDIR(REG[20h] Bit2), LCD module can show the 90 degree font.
Figure 7-22 : Font 90∘Rotation
7-4-5
Enlargement, Transparent Font
RA8875 also supports enlargement (REG[22h] Bit[3:0]), and transparent function(REG[22h]
Bit6). Moreover, these functions can use simultaneously. The behaviors of these functions just
refer to below figure:
Horizontal x2
Vertical x2
RAiO
transparent
RAiO
Figure 7-23 : Boldface and Transparent Font
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RA8875
Version 1.2
7-4-6
Character / Graphic TFT LCD Controller
Font Change Line when Setting Write Auto Move
RA8875 supports the auto move of font write and it will auto change line with active window. By
setting REG[40h] Bit1 = 0, the position of font will move automatically and change line when the
font over the range of horizontal or vertical active window. Refer the below figure to view the
behavior of auto move.
技
Auto move
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Horizontal range of active window
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技
Vertical range of active window
瑞佑科
Active window
Figure 7-24 : Auto Change Line in Font Mode
7-4-7
Font Full-Alignment
RA8875 supports font full-alignment that makes the fonts to align each other when writing half
and full fonts on the DDRAM. By setting REG[22h] Bit7 = 1, the behavior of writing half and full
fonts will be the below figure:
瑞
R
瑞
R
歡
迎
佑
A i
科
O
佑
A i
科
光
臨
瑞
Non full-alignment
技
O
佑
Full-alignment
技
科
技
Display RAM
Figure 7-25 : Full-Alignment Function
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
7-5 Geometric Pattern Drawing Engine
7-5-1
Circle Input
RA8875 supports hardware circle drawing function on the DDRAM. User can largely reduce the
effort of MCU by the function. By setting the center of a circle REG[99h~9Ch] ,the radius of a
circle REG[9Dh] and the color of circle REG[63h~65h], and then setting start draw REG[90h]
Bit6 = 1, RA8875 will implements a corresponding circle on the DDRAM automatically. Moreover,
user can decide whether to fill the circle by setting REG[90h] Bit5 as 0(not fill) or 1(fill). The
procedure of drawing circle just refers to the below figure:
Set the center of a circle
REG[99h~9Ch]
Don’t fill a circle
REG[90h] bit5=0
fill a circle
REG[90h] bit5=1
Start drawing circle
REG[90h] bit6=1
Start drawing circle
REG[90h] bit6=1
Set the radius of a circle
REG[9Dh]
Set the color of a circle
REG[63h~65h]
center
radius
color
center
radius
color
Figure 7-26 : Geometric Pattern Drawing- Draw Circle
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
7-5-2
Ellipse Input
RA8875 supports draw ellipse drawing function makes user to draw ellipse on the DDRAM only
use by few MCU cycles. By setting the center of a ellipse REG[A5h~A8h] ,the long and short
axis of a ellipse REG[A1h~A4], the color of ellipse REG[63h~65h], the draw ellipse condition
REG[A0h] Bit5=0 and Bit4=0, and then setting start draw REG[A0h] Bit7 = 1, RA8875 will draw
a corresponding Ellipse on the DDRAM. Moreover, user can fill the circle by setting REG[A0h]
Bit6 = 1. The procedure of drawing ellipse just refers to the below figure:
Set the center of a ellipse
REG[A5h~A8h]
Don’t fill a ellipse
REG[A0h] bit6=0
fill a ellipse
REG[A0h] bit6=1
Start drawing ellipse
REG[A0h] bit7=1
Start drawing ellipse
REG[A0h] bit7=1
Set the long and short axis
of a ellipse
REG[A1h~A4h]
Set the color of a ellipse
REG[63h~65h]
short axis
Set draw ellipse condition
REG[A0h] bit5=0,bit4=0
short axis
Long axis
center
Long axis
center
color
color
Figure 7-27
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RA8875
Version 1.2
7-5-3
Character / Graphic TFT LCD Controller
Curve Input
RA8875 supports curve drawing function for user to draw curve on the DDRAM only by few
MCU cycles. By setting the center of a curve REG[A5h~A8h] ,the long and short axis of a curve
REG[A1h~A4], the color of curve REG[63h~65h], the draw curve condition REG[A0h] Bit5=0
and Bit4=1, the curve part of the ellipse REG[A0h] Bit[1:0], and then setting start draw REG[A0h]
Bit7 = 1, RA8875 will draw a corresponding curve on the DDRAM. Moreover, user can fill the
curve by setting REG[A0h] Bit6 = 1. The procedure of drawing circle just refers to the below
figure:
Set the center of a curve
REG[A5h~A8h]
Don’t fill a curve
REG[A0h] bit6=0
fill a curve
REG[A0h] bit6=1
Start drawing curve
REG[A0h] bit7=1
Start drawing curve
REG[A0h] bit7=1
Set the long and short axis
of a curve
REG[A1h~A4h]
Set the color of a curve
REG[63h~65h]
DECP = 01
DECP = 10
short axis
Set draw curve condition
REG[A0h] bit5=0,bit4=1
short axis
Long axis
center
color
DECP = 00
Long axis
center
color
DECP = 11
Set draw curve part select
REG[A0h] bit[1:0](DECP)
Figure 7-28
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RA8875
Version 1.2
7-5-4
Character / Graphic TFT LCD Controller
Square Input
RA8875 supports square drawing function for user to draw square on the DDRAM only by few
MCU cycles. By setting the start point of a square REG[91h~94h] ,the end point of a square
REG[95h~98h] and the color of a square REG[63h~65h], then setting draw a square REG[90h]
Bit4=1, Bit0=0 and start draw REG[90h] Bit7 = 1, RA8875 will draw a corresponding square on
the DDRAM. Moreover, user can fill the square by setting REG[90h] Bit5 = 1. The procedure of
drawing square just refers to the below figure:
Set start point of a square
REG[91h~94h]
Don’t fill a square
REG[90h] bit5=0
fill a square
REG[90h] bit5=1
Start drawing square
REG[90h] bit7=1
Start drawing square
REG[90h] bit7=1
Set the end of a square
REG[95h~98h]
Set the color of a square
REG[63h~65h]
Start point
color
Set draw a square
REG[90h] bit4=1, bit0=0
Start point
End point
color
End point
Figure 7-29 : Geometric Pattern Drawing- Draw Rectangle
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RA8875
Version 1.2
7-5-5
Character / Graphic TFT LCD Controller
Line Input
RA8875 supports line drawing function for user to draw line on the DDRAM only by few MCU
cycles. By setting the start point of a line REG[91h~94h] ,the end point of a line REG[95h~98h]
and the color of a line REG[63h~65h], then setting draw a line REG[90h] Bit4 = 0, Bit0=0 and
start draw REG[90h] Bit7 = 1, RA8875 will draw a corresponding line on the DDRAM. The
procedure of drawing line just refers to the below figure:
Set start point of a line
REG[91h~94h]
Set draw a line
REG[90h] bit4=0
Set the end of a line
REG[95h~98h]
Start drawing line
REG[90h] bit7=1
Set the color of a line
REG63h~65h]
Start point
End point
color
color
End point
Start point
Figure 7-30 : Geometric Pattern Drawing- Draw Line
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RA8875
Version 1.2
7-5-6
Character / Graphic TFT LCD Controller
Triangle Input
RA8875 supports triangle drawing function for user to draw line on the DDRAM only by few
MCU cycles. By setting the point0 of a triangle REG[91h~94h], the point1 of a triangle
REG[95h~98h], the point2 of a triangle REG[A9h~ACh]
and the color of a triangle
REG[63h~65h], then setting draw a triangle REG[90h] Bit0 = 1 and start draw REG[90h] Bit7 = 1,
RA8875 will draw a corresponding triangle on the DDRAM. Moreover, user can fill the triangle
by setting REG[90h] Bit5 = 1. The procedure of drawing triangle just refers to the below figure:
Set point0 of a triangle
REG[91h~94h]
Don’t fill a triangle
REG[90h] bit5=0
fill a triangle
REG[90h] bit5=1
Start drawing triangle
REG[90h] bit7=1
Start drawing triangle
REG[90h] bit7=1
Set point1 of a triangle
REG[95h~98h]
Set point2 of a triangle
REG[A9h~ACh]
point1
point1
Set the color of a triangle
REG[63h~65h]
Set draw a triangle
REG[90h] bit0=1
point0
color
point2
point0
color
point2
Figure 7-31
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
7-5-7
Square Of Circle Corner Input
RA8875 supports circle-square drawing function for user to draw circle square on the DDRAM
by few MCU cycles. By setting the start point of a square REG[91h~94h] ,the end point of a
square REG[95h~98h], circle corner REG[A1h~A4h] and the color of a circle square
REG[63h~65h], then setting draw a circle square REG[A0h] Bit5=1 and start draw REG[A0h]
Bit7 = 1, RA8875 will draw a corresponding circle square on the DDRAM. Moreover, user can fill
the square by setting REG[A0h] Bit6 = 1. The procedure of drawing square just refers to the
below figure:
Set start point of a circle square
REG[91h~94h]
Don’t fill a circle square
REG[A0h] bit6=0
fill a circle square
REG[A0h] bit6=1
Start drawing circle square
REG[A0h] bit7=1
Start drawing circle square
REG[A0h] bit7=1
Set the end of a circle square
REG[95h~98h]
Set circle corner of a circle square
REG[A1h~A4h]
Start point
Start point
Set the color of a circle square
REG[63h~65h]
color
Set draw a circle square
REG[A0h] bit5=1
End point
Circle corner
color
End point
Circle corner
Figure 7-32
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
7-6 BTE (Block Transfer Engine) Function (Parallel MCU Interface Only)
The RA8875 embedded a built-in 2D Block Transfer Engine(BTE) which can increase the
performance of block transfer operation. When a block of data needs to be moved or do some logic
operation with dedicated data, RA8875 can speed up the operation by BTE hardware and also
simplify the MCU program. BTE function is compatible with 2D BitBLT standard function. This
section will discuss the BTE engine operation and functionality.
Before using the BTE function, use must select the corresponding BTE operation. RA8875 supports
13 BTE operations. About the operation description, please mention the Table 7-12 below. For each
BTE operation, maximum 16 raster operations (ROP) are supported for different application. They
could provide the different logic combinations for ROP source and ROP destination. Through the
combination of the BTE operation and ROP, user can achieve many useful application operations.
The ROP source or destination can be set as a rectangular of display area (block mode) or a
continuous memory section (Linear addressing mode). Please refer to the behind chapters for detail
description.
The BTE function has 2 methods for checking the completion of BTE process. One way is checking
busy by software, and the other way is using hardware interrupt. When BTE engine is operating, the
busy flag in the status register will be set, the bit responses the system is busy or not. BTE operation
is a kind of busy condition. User can read it to determine if it is done. (Please refer to Section 5-1
Status Register.) Hardware interrupt (INT#) is another way to check BTE process end, user can
enable interrupt function by REG[F0h] first. If BTE function completes, RA8875 will generate
hardware interrupt to note MCU, and user checks the interrupt status to confirm the BTE status.
When BTE is operating, it is suggested that the user should not write command to RA8875 except
REG[02h] or REG[F1h] to prevent the un-expected result. Please note the BTE function must use
under Graphic Mode (REG [40h] Bit7 = 0).
Table 7-12 : BTE Operation Function
BTE Operation
REG[51h] Bits [3:0]
BTE Operation
0000b
Write BTE with ROP. Please refer to Table 7-13.
0001b
Read BTE.
0010b
Move BTE in positive direction with ROP. Please refer to Table 7-13.
0011b
Move BTE negative direction with ROP. Please refer to Table 7-13.
0100b
Transparent Write BTE.
0101b
Transparent Move BTE in positive direction.
0110b
Pattern Fill with ROP. Please refer to Table 7-13.
0111b
Pattern Fill with transparency.
1000b
Color Expansion. Please refer to Table 7-14
1001b
Color Expansion with transparency. Please refer to Table 7-14.
1010b
Move BTE with Color Expansion. Please refer to Table 7-15.
Move BTE with Color Expansion and transparency.
Please refer to Table 7-15.
Solid Fill.
1011b
1100b
Other combinations
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
Table 7-12 describes 13 BTE operation modes of RA8875, if the operation code is “0000”, “0010”,
“0011” and “0110” then it has to collocate with raster operation code for the variety functions. Please
refer to Table 7-13.
Table 7-13 : ROP Function (1)
ROP Bits
REG[51h] Bit[7:4]
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b
1010b
1011b
1100b
1101b
1110b
1111b
Boolean Function
Operation
0 ( Blackness )
~S・~D or ~ ( S+D )
~S・D
~S
S・~D
~D
S^D
~S+~D or ~ ( S・D )
S・D
~ ( S^D )
D
~S+D
S
S+~D
S+D
1 ( Whiteness )
Note:
1. ROP Function S: Source Data, D: Destination Data.
2. For pattern fill functions, the source data indicates the pattern data.
Example:
If ROP function setting Ch, then Destination Data = Source Data
If ROP function setting Eh, then Destination Data = S + D
If ROP function setting 2h, then Destination Data = ~S・D
If ROP function setting Ah, then Destination Data = Destination Data
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
Table 7-14 : ROP Function (2)
ROP Bits
REG[51h] Bit[7:4]
Start Bit Position for Color Expansion
BTE operation code = 1000 / 1001
16-bit MCU
Interface
8-bit MCU
Interface
0000b
0001b
Bit0
Bit1
Bit0
Bit1
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b
1010b
1011b
1100b
1101b
1110b
1111b
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Bit8
Bit9
Bit10
Bit11
Bit12
Bit13
Bit14
Bit15
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Table 7-15 : ROP Function (3)
ROP Bits
REG[51h] Bit[7:4]
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b
1010b
1011b
1100b
1101b
1110b
1111b
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Start Bit Position for Move Color Expansion
BTE operation code = 1010 / 1011
Color Depth
= 65Kcolors
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Bit8
Bit9
Bit10
Bit11
Bit12
Bit13
Bit14
Bit15
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Color Depth
= 256 colors
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
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RA8875
Version 1.2
7-6-1
Character / Graphic TFT LCD Controller
Select BTE Start Point Address and Layer
In the 2 layers display configuration, The ROP source and destination could come from the
selectable layer. To program the ROP source or ROP destination, the start point of horizontal
and vertical address is set first. Please refer to register VSBE0/1 and VDBE0/1. The layer
selection number is also set from the part of address of VSBE1 Bit[7], VDBE1 Bit[7], where the
VSBE1 Bit[7] is source layer selection and the VDBE1 Bit[7] is destination layer selection.
7-6-2
BTE Operations
7-6-2-1 Write BTE
The Write BTE provides 16 ROP functions with two operands, where BTE engine will write
the result of ROP function to the destination address.
7-6-2-2 Read BTE
The Read BTE supports data read function from the source to the host. No ROP function is
applied.
7-6-2-3 Move BTE
The Move BTE provides 16 ROP functions with two operands, and is supported in both a
positive and negative direction.
7-6-2-4 Solid Fill
The Solid Fill BTE function fills a specified BTE area(source) with a solid color as defined in
the BTE Foreground Color Register.
7-6-2-5 Pattern Fill
The Pattern Fill BTE function fills a specified BTE area with an 8 pixels by 8 lines pattern
defined in off-screen DDRAM ram area.
7-6-2-6 Transparent Pattern Fill
The Transparent Pattern Fill function fills a specified BTE area with an 8 pixels by 8 lines
pattern in off-screen DDRAM ram area. When the pattern color is equal to the key color,
which is defined in Background Color Register, the destination area is not updated. For the
function no raster operation is applied.
7-6-2-7 Transparent Write BTE
The Transparent Write BTE supports bit block transfers from the host to DDRAM ram area.
When the source color is equal to the key color, which is defined in BTE Background Color
Register, the destination area is not updated. For this function no raster operation is applied.
7-6-2-8 Transparent Move BTE
The Transparent Move BTE supports block transfers from DDRAM ram to DDRAM ram in
positive direction only. When the source color is equal to key color, which is defined in BTE
Background Color Register, the destination area is not updated. For this BTE no raster
operation is applied.
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
7-6-2-9 Color Expansion
The Color Expansion BTE expands the host’s monochrome data to 8 or 16 bpp color format.
A 1 expands to the color defined in the BTE Foreground Color Register.
A 0 expands to the color defined in the BTE Background Color Register.
If background transparency is enabled, then the destination color will remain untouched.
7-6-2-10 Move BTE with Color Expansion
The Move BTE with Color Expansion expands off-screen source’s monochrome data to 8 or
16 bpp color format .The source data “1” will expand BTE Foreground Color to the DDRAM.
The source data is “0” then expands BTE Background Color to DDRAM. If background
transparency is enabled, then the destination data will remain.
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RA8875
Version 1.2
7-6-3
Character / Graphic TFT LCD Controller
BTE Access Memory Method
The BTE has two methods to access memory, the block memory access and linear memory
access. The area or size is defined by REG[5Ch], [5Dh], [5Eh] and [5Fh]. About the description
of two types of memory access, please refer to following section.
7-6-3-1 Block Memory Access
With the setting, The BTE memory source/destination data is treated as a block of display
area. The block width and height is defined in REG[5Ch-5Fh].The below example shows
both the source and destination address are defined as block access method:
DPRAM - Layer
Source Address
Destination Address
Figure 7-33 : Block Memory Access of BTE Function
7-6-3-2 Linear Memory Access
With the setting, The BTE memory source/destination data is treated as a continuous area
of display area. The area length is calculated from the REG[5Ch-5Fh], the length equals to
(BTE_WIDTH x BTE_HEIGHT).
The below example shows both the source and destination address are defined as linear
access method.
Source Linear
Total Process Data length = BTE Width * High
Destination Linear
Figure 7-34 : Linear Memory Access of BTE Function
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RA8875
Version 1.2
7-6-4
Character / Graphic TFT LCD Controller
BTE Function Explaination
7-6-4-1 Write BTE with ROP
The Write BTE increases the speed of transferring data from MCU interface to the DDRAM.
The Write BTE with ROP fills a specified area of the DDRAM with data supplied by the
MCU. The Write BTE supports all 16 ROPs. It also supports both Destination Linear and
Destination Block modes. The Write BTE requires the MCU to provide data.
User can use this function by hardware interrupt or software check busy to get BTE process
status. If user checks BTE process status by software, the BECR0(REG[50h]) Bit7 or status
register(STSR) Bit6 can indicate the BTE status. By another way, user can check BTE
process status by hardware interrupt, the INT# must connect to MCU and REG[F1h] is used
to check the interrupt source comes from BTE when INT# is active.
RA8875
DDRAM
MPU
Figure 7-35 : Write BTE with ROP
The suggested programming steps and registers setting are listed below as reference.
1.
2.
3.
4.
5.
6.
7.
8.
Setting destination position
Æ REG[58h], [59h], [5Ah], [5Bh]
Setting BTE width register
Æ REG[5Ch], [5Dh]
Setting BTE height register
Æ REG[5Eh], [5Fh]
Setting register Destination = source Æ REG[51h] = Ch
Enable BTE function
Æ REG[50h] Bit7 = 1
Check STSR Bit7
Write next image data
Repeat step 6, 7 until image data = block image data. Or Check STSR Bit6
Figure 7-36 : After BTE Function
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
The following process using INT# to confirm the complete of BTE operation. By using the
method, user must make sure that the INT# signal is connected to MCU interrupt pin first.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
Setting INTC1 register
Æ REG[F0h]
Setting Destination position
Æ REG[58h], [59h], [5Ah], [5Bh]
Setting BTE width register
Æ REG[5Ch], [5Dh]
Setting BTE height register
Æ REG[5Eh], [5Fh]
Setting register Destination = source Æ REG[51h] = C0h
Enable BTE function
Æ REG[50h] Bit7 = 1
Wait for Interrupt generate
Clear INTC2 BTE Read/Write status Æ REG[F1h] Bit0 = 1
CMD [02h]
Write next image data
Wait for Interrupt generate
Clear INTC2 BTE Read/Write status Æ REG[F1h] Bit0 = 1
Repeat step 9,10,11,12 until image data = block image data. Or check STSR Bit6
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
7-6-4-2 Read BTE (Burst Read Like Function)
This Read BTE increases the speed of transferring data from the DDRAM to the MCU
interface. This Read BTE function is typically used to save a part of data in the DDRAM to
the system memory. Once the Read BTE begins, the BTE engine remains active to provide
the data from DDRAM for MCU until all the data have been read. The number of data for
BTE is calculated by REG[5Ch-5Fh] as (BTE_WIDTH x BTE_HEIGHT).
RA8875
MPU
DDRAM
Figure 7-37 : Read BTE
The suggested programming steps and registers setting are listed below as reference.
1.
2.
3.
4.
5.
6.
7.
8.
Setting source position
Æ REG[54h], [55h], [56h], [57h]
Setting BTE width register
Æ REG[5Ch], [5Dh]
Setting BTE height register Æ REG[5Eh], [5Fh]
Setting register operation
Æ REG[51h] = 01h
Enable BTE function
Æ REG[50h] Bit7 = 1
Check STSR Bit7
Read next image data
Repeat step 6, 7 until image data = block image data.
The following process using INT# to confirm the complete of BTE operation. By using the
method, user must make sure that the INT# signal is connected to MCU interrupt pin first.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
Setting INT# Æ REG[F0h]
Setting source position
Æ REG[54h], [55h], [56h], [57h]
Setting BTE width register
Æ REG[5Ch], [5Dh]
Setting BTE height register
Æ REG[5Eh], [5Fh]
Setting register operation
Æ REG[51h] = 01h
Enable BTE function
Æ REG[50h] Bit7 = 1
Wait for Interrupt generate
Read next image data
Clear INT# BTE Read/Write status Æ REG[F1h] Bit1 = 1
Repeat step 7, 8, 9 until image data all read. Or Check STSR Bit6
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
7-6-4-3 Move BTE in Positive Direction with ROP
The Move BTE moves a specific area of the DDRAM to a different area of the DDRAM. This
operation can speed up the data copy operation from one block to another and save a lot of
MCU processing time and loading.
Destination
Source
Figure 7-38 : Move BTE in Position Direction with ROP
The Move BTE source/destination can be a rectangular area or a linear area. This function
allows the temporary saving of a portion of the visible DDRAM to an off-screen area for later
usage. Or copy the off-screen data to the visible area.
The suggested programming steps and registers setting are listed below as reference.
1.
2.
3.
4.
5.
6.
Setting source layer and address
Setting destination layer and address
Setting BTE width and height
Setting BTE operation and ROP function
Enable BTE function
Check STSR REG Bit6
Æ REG[54h], [55h], [56h], [57h]
Æ REG[58h], [59h], [5Ah], [5Bh]
Æ REG[5Ch], [5Dh], [5Eh], [5Fh]
Æ REG[51h] Bit[3:0] = 2h
Æ REG[50h] Bit7 = 1
Æ check 2D final
Figure 7-39 : Before BTE Function
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
Figure 7-40 : After BTE Function
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
7-6-4-4 Move BTE in Negative Direction with ROP
The Move BTE in Negative Direction with ROP function operates almost the same behavior
as the “Move BTE in Positive Direction with ROP”. But the operating direction is opposite. It
moves the latest data of the BTE source to the latest data of BTE destination first, and then
operates backward to the starting point of BTE source/destination. For the application that
BTE source and destination are overlay, the different direction of Move BTE will cause
different result.
Source
Destination
Figure 7-41 : Move BTE in Negative Direction with ROP
The Move BTE moves a specific area of the DDRAM to a different area of the DDRAM. This
operation can speed up the data copy operation from one block to another.
The suggested programming steps and registers setting are listed below as reference.
1.
2.
3.
4.
5.
6.
Setting source layer and address
Setting destination layer and address
Setting BTE width and height
Setting BTE operation and ROP function
Enable BTE function
Check STSR REG Bit6
Æ REG[54h], [55h], [56h], [57h]
Æ REG[58h], [59h], [5Ah], [5Bh]
Æ REG[5Ch], [5Dh], [5Eh], [5Fh]
Æ REG[51h] Bit[3:0] = 3h
Æ REG[50h] Bit[7] = 1
Æ check 2D final
Figure 7-42 : Before BTE Function
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
Figure 7-43 : After BTE Function
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Version 1.2
Character / Graphic TFT LCD Controller
7-6-4-5 Transparent Write BTE
The Transparent Write BTE increases the speed of transferring data from MCU interface to
the DDRAM. Once the Transparent Write BTE begins, the BTE engine remains active until
all pixels have been written.
“Transparent Write BTE” updates a specified area of the DDRAM with data supplied by the
MCU. Unlike “Write BTE” operation, the “Transparent Write BTE” will ignore the operation
of a dedicated color that is set as “Transparent Color”. In RA8875, the “Transparent Color”
is set as “BTE Foreground Color“ in the “Transparent Write BTE” operation. When the
source color of the operation meets the “Transparent Color”, no write function will be done.
This function is useful to copy a color image partially from MCU interface to the DDRAM.
When setting one color as the “transparent color”, the source pixel with the transparent
color is not transferred. This allows a fast paste function of a dedicated image to an
arbitrary background. For example, considering a source image has a red circle on a blue
background. By selecting the blue color as the transparent color and using the Transparent
Write BTE on the whole rectangles, the effect is a BTE of the red circle only. The
Transparent Write BTE supports both Destination Linear and Destination Block modes.
Image
RA8875
MPU
DDRAM
Figure 7-44 : Transparent Write BTE
The suggested programming steps and registers setting are listed below as reference.
1.
2.
3.
4.
5.
6.
7.
8.
9.
Setting destination position
Æ REG[58h], [59h], [5Ah], [5Bh]
Setting BTE width register
Æ REG[5Ch], [5Dh]
Setting BTE height register
Æ REG[5Eh], [5Fh]
Setting Transparency Color –Background Color Æ REG[63h], [64h], [65h]
Setting BTE operation code and ROP Code
Æ REG[51h] = C4h
Enable BTE function
Æ REG[50h] Bit7 = 1
Write next image data
Check STSR Bit7
Repeat step 7, 8 until image data = block image data. Or Check STSR Bit6
Figure 7-45 : Before BTE Function
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
Figure 7-46 : After BTE Function
The suggested programming steps and registers setting are listed below as reference.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
Setting INT#
Æ REG[F0h]
Setting Destination position
Æ REG[58h], [59h], [5Ah], [5Bh]
Setting BTE width register
Æ REG[5Ch], [5Dh]
Setting BTE height register
Æ REG[5Eh], [5Fh]
Setting register Destination = source Æ REG[51h] = C4h
Enable BTE function
Æ REG[50h] Bit7 = 1
Wait for Interrupt generate
Clear INT# BTE Read/Write status Æ REG[F1h] Bit0 = 1
CMD [02h]
Write next image data
Wait for Interrupt generate
Clear INT# BTE Read/Write status Æ REG[F1h] Bit0 = 1
Repeat step 9,10,11,12 until image data = block image data. Or Check STSR Bit6
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
7-6-4-6 Transparent Move BTE Positive Direction
“Transparent Move BTE in Positive Direction” moves an area of the DDRAM to a different
area of the DDRAM with ignoring the “Transparent Color”. The same with the “Transparent
Write BTE” operation, it allows for setting a transparent color which is not moved during the
BTE. The difference between “Transparent Write” and “Transparent Move” is the source of
the operation. , “Transparent Write” source comes from MCU interface or MCU and
“Transparent Move” source comes from DDRAM. Because the source is DDRAM, the
direction of the operation must be defined. RA8875 supports positive direction only for
“Transparent Move” function.
The source of “Transparent Move BTE” may be
depending on the user setting. The destination
the source area. One thing should be
case(source/destination area), the source of
“Transparent Move” is done.
specified as linear mode or rectangle mode,
area of the operation could be overlay with
note is that in some special overlay
the operation may be modified after the
The suggested programming steps and registers setting are listed below as reference.
1.
2.
3.
4.
5.
6.
7.
Setting source layer and address
Æ REG[54h], [55h], [56h], [57h]
Setting destination layer and address
Æ REG[58h], [59h], [5Ah], [5Bh]
Setting BTE width and height
Æ REG[5Ch], [5Dh], [5Eh], [5Fh]
Setting Transparency Color – Front ground ColorÆ REG[63h], [64h], [65h]
Setting BTE operation and ROP function
Æ REG[51h] Bit[3:0] = 5h
Enable BTE function
Æ REG[50h] Bit7 = 1
Check STSR REG Bit6
Æ check 2D final
Figure 7-47 : Before BTE Function
Figure 7-48 : After BTE Function
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
7-6-4-7 Pattern Fill with ROP
“Pattern Fill BTE with ROP” operation fills a specified rectangular area of the DDRAM with a
dedicated pattern repeatedly. The fill pattern is an array of 8x8/16x16 pixels stored in the offscreen DDRAM. The pattern can be logically combined with the destination using one of the
16 ROP codes. The operation can be used to speed up the application with duplicate pattern
write in an area, such as background paste function.
Pattern
Panel Display Result
Figure 7-49 : Pattern Fill with ROP
The suggested programming steps and registers setting are listed below as reference.
1.
2.
3.
4.
5.
Setting destination layer and address
Æ REG[58h], [59h], [5Ah], [5Bh]
Setting BTE width and height
Æ REG[5Ch], [5Dh], [5Eh], [5Fh]
Setting BTE operation and ROP function Æ REG[51h] Bit[3:0] = 06h
Enable BTE function
Æ REG[50h] Bit7 = 1
Check STSR REG Bit6
Æ check 2D final
Figure 7-50 : Before BTE Function
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
Figure 7-51 : Pattern
Figure 7-52 : After BTE Function
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
7-6-4-8 Pattern Fill with Transparency
The Pattern Fill BTE with Transparency fills a specified rectangular area of the DDRAM with
a pattern. The function is the same with “Pattern Fill” and with the setting of “Transparent
Color”. In the pattern fill operation, the transparent color is ignored. The fill pattern is an eight
by eight array of pixels stored in off-screen DDRAM. The fill pattern must be loaded to offscreen DDRAM prior to the BTE starting. It should be noted that for “Pattern Fill with
Transparency” function, transparent color is only available for 256 colors. i.e. Only BIT[4:2] of
REG[63h], BIT [5:3] of REG[64h]and BIT[4:3] of REG[65h] BIT [4:3] are valid, please refer to
the relative register for detail description.
Pattern
Panel Display result , if set blue color is transparency color
Figure 7-53 : Pattern Fill with Transparency
The suggested programming steps and registers setting are listed below as reference.
1.
2.
3.
4.
5.
6.
Setting destination layer and address
Setting BTE width and height
Setting Transparency Color – Front ground Color
Setting BTE operation and ROP function
Enable BTE function
Check STSR Bit6
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Æ REG[58h], [59h], [5Ah], [5Bh]
Æ REG[5Ch], [5Dh], [5Eh], [5Fh]
Æ REG[63h], [64h], [65h]
Æ REG[51h] Bit[3:0] = 07h
Æ REG[50h] Bit7 = 1
Æ check 2D final
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
Figure 7-54 : Before BTE Function
Figure 7-55 : Pattern Image
Figure 7-56 : After BTE Function
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
7-6-4-9 Color Expansion
“Color Expand” is a useful operation to translate monochromes data of MCU interface to
color one. In the operation, the source data will be treated as a monochromes bit-map. The
bit-wise data is translated to multi-bits per pixel color data by the setting of “BTE Foreground
Color” and “BTE Background Color”. The source bit “1” will be translated to “BTE Foreground
Color” and the source bit ”0” is translated to “BTE Background Color”. This function can
largely reduce the effort when system translation from mono system to color system. “Color
Expand” operation will be continuously feeding a 16-bit/8-bit (Reference MCU interface
setting) data package. When the end of the line is reached, any unused bits will be discarded.
The data for the next line will be taken from the next data package. Each bit is serially
expanded to the destination data starting from MSB to LSB.
RA8875
Mono
Color
MPU
DDRAM
Bitmap
Mono Color Bitmap
Color Image
RAIO production
is very good
RAIO production
is very good
Figure 7-57 : Color Expansion Data Block
The suggested programming steps and registers setting are listed below as reference.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
Setting destination position
Æ REG[58h], [59h], [5Ah], [5Bh]
Setting BTE width register
Æ REG[5Ch], [5Dh]
Setting BTE height register
Æ REG[5Eh], [5Fh]
Setting Background Color – The transferred color when bitmap = 0
Æ
REG[60h], [61h], [62h]
Setting Foreground Color –The transferred color when bitmap = 1
Æ REG[63h],
[64h], [65h]
Setting BTE operation and ROP function Æ REG[51h] Bit[3:0] = 08h
Enable BTE function
Æ REG[50h] Bit7 = 1
Check STSR Bit7
Write next image data
Repeat step 6, 7 until image data = block image data. Or Check STSR Bit6
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
The following process using INT# to confirm the complete of BTE operation. By using the
method, user must make sure that the INT# signal is connected to MCU interrupt pin first.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
Setting INT#
Æ REG[F0h]
Setting Destination position
Æ REG[58h], [59h], [5Ah], [5Bh]
Setting BTE width register
Æ REG[5Ch], [5Dh]
Setting BTE height register
Æ REG[5Eh], [5Fh]
Setting Background Color – The transferred color when bitmap = 0
ÆREG[60h],
[61h], [62h]
Setting Foreground Color –The transferred color when bitmap = 1
ÆREG[63h],
[64h], [65h]
Setting BTE operation and ROP function Æ REG[51h] Bit[3:0] = 08h
Enable BTE function
Æ REG[50h] Bit7 = 1
Wait for Interrupt generate
Clear INT# BTE Read/Write status
Æ REG[F1h] Bit0 = 1
Write next image data
Continue run step 9, 10, 11 until image data = block image data. Or Check STSR Bit6
Figure 7-58 : Before BTE Function
Figure 7-59 : After BTE Function
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
Note:
1.
Calculate send data numbers per row = ((BTE Width size REG – (MCU interface
bits – (start bit + 1)) ) / MCU interface bits) + ((start bit + 1) % (MCU interface ))
2.
Total data number = (send data numbers per row ) x BTE Vertical REG setting
D4 8bit
D0
D1
D2
D3
MPU send to RA8875
data, the data have 8bit
for one transmitter data,
and serial send
D0,D1,D2 ,D3,D4 ~~
Dn to RA8875
start bit =4
D0
D1
D2
D3
Not Expansion
Not Expansion
BTE High REG [5Ah]
[5Bh] setting
Expansion
BTE Width REG
[58h] [59h] setting
Figure 7-60 : Color Expansion Data Diagram
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
7-6-4-10 Color Expansion with Transparency
This BTE operation is virtually identical to the Color Expand BTE, except the background
color is completely ignored. All bits set to 1 in the source monochrome bitmap are color
expanded to the “BTE Foreground Color”. All bits set to 0 in source monochrome bitmap that
would be expanded to the “BTE Background Color” are not expanded at all.
RA8875
Mono
Color
Bitmap
MPU
Mono Color Bitmap
DDRAM
Color Image
RAIO production
is very good
RAIO production
is very good
Figure 7-61 : Color Expansion with Transparency
The suggested programming steps and registers setting are listed below as reference.
1.
2.
3.
4.
5.
6.
7.
8.
9.
Setting destination position
Æ REG[58h], [59h], [5Ah], [5Bh]
Setting BTE width register
Æ REG[5Ch], [5Dh]
Setting BTE height register
Æ REG[5Eh], [5Fh]
Setting BTE Foreground Color – the transferred color when bitmap data = 1 Æ
REG[63h], [64h], [65h]
Setting BTE operation and ROP function Æ REG[51h] Bit[3:0] = 09h
Enable BTE function
Æ REG[50h] Bit7 = 1
Check STSR Bit7
Write next image data
Continue run step 6, 7 until image data = block image data. Or Check STSR Bit6
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
Destination address
Mono Bitmap
RAIO production
Is very good .
2D color
Expansion
RAIO production
Is very good .
Figure 7-62 : Color Expansion with Transparency
The following process using INT# to confirm the complete of BTE operation. By using the
method, user must make sure that the INT# signal is connected to MCU interrupt pin first.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
Setting INT#
Æ REG[F0h]
Setting Destination position
Æ REG[58h], [59h], [5Ah], [5Bh]
Setting BTE width register
Æ REG[5Ch], [5Dh]
Setting BTE height register
Æ REG[5Eh], [5Fh]
Setting BTE operation and ROP function Æ REG[51h] Bit[3:0] = 09h
Enable BTE function
Æ REG[50h] Bit7 = 1
Wait for Interrupt generate
Clear INT# BTE Read/Write status
Æ REG[F1h] Bit0 = 1
Write next image data
Continue run step 7, 8, 9 until image data = block image data. Or check STSR Bit6
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
7-6-4-11 Move BTE with Color Expansion
The “Move BTE with Color Expansion” takes a monochrome bitmap as the source and color
expands it into the destination. Color expansion moves all bits in the monochrome source to
pixels in the destination. All bits in the source set to one are expanded into destination pixels
of the selected foreground color. All bits in the source set to zero are expanded into pixels of
the selected background color.
The Move BTE with Color Expansion is used to accelerate monochrome to color translation
on the screen. A monochrome bitmap in off-screen memory occupies very little space and
takes advantage of the hardware acceleration. Since the foreground and background colors
are programmable, text of any color can be created.
The Move BTE with Color Expansion may move data from one rectangular area to another,
or it may be specified as linear. The linear configuration may be applied to the source or
destination. Defining the Move BTE as linear allows each line of the Move BTE area to be
placed directly after the previous line, rather than requiring a complete row of address space
for each line.
8bit/pixel
16bit/pixel
1bit/pixel
DPRAM
Color Image
Mono color Bitmap
Mono Color Bitmap
Color expansion
Color Image
RAIO production
is very good
RAIO production
is very good
Figure 7-63 : Move BTE with Color Expansion
The suggested programming steps and registers setting are listed below as reference.
1.
2.
3.
4.
5.
6.
7.
8.
Setting source layer and address
Æ REG[54h], [55h], [56h], [57h]
Setting destination layer and address
Æ REG[58h], [59h], [5Ah], [5Bh]
Setting BTE width and height
Æ REG[5Ch], [5Dh], [5Eh], [5Fh]
Setting Background Color – The transferred color when bitmap data = 0 Æ REG[60h],
[61h], [62h]
Setting Foreground Color –The transferred color when bitmap data = 1 Æ REG[63h],
[64h], [65h]
Setting BTE operation and ROP function Æ REG[51h] Bit[3:0] = 0Ah
Enable BTE function
Æ REG[50h] Bit7 = 1
Check STSR REG Bit6
Æ check 2D final
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
Figure 7-64 : Before BTE Function
Figure 7-65 : After BTE Function
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
7-6-4-12 Move BTE with Color Expansion and Transparency
The “Transparent Move BTE with Color Expansion” is virtually identical to the Move BTE with
Color Expansion. The background color is ignored and bits in the monochrome source
bitmap set to 0 are not Color expanded
Figure 7-66 : Move BTE with Color Expansion and Transparency
The suggested programming steps and registers setting are listed below as reference.
1.
2.
3.
4.
Setting source layer and address
Æ REG[54h], [55h], [56h], [57h]
Setting destination layer and address
Æ REG[58h], [59h], [5Ah], [5Bh]
Setting BTE width and height
Æ REG[5Ch], [5Dh], [5Eh], [5Fh]
Setting Foreground Color – The transferred color when bitmap data = 1
Æ REG[63h], [64h], [65h]
5. Setting BTE operation and ROP function Æ REG[51h] Bit[3:0] = 0Bh
6. Enable BTE function
Æ REG[50h] Bit7 = 1
7. Check STSR REG Bit6
Æ check 2D final
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
7-6-4-13 Solid Fill
The Solid Fill BTE fills a rectangular area of the DDRAM with a solid color. This operation is
used to paint large screen areas or to set areas of the DDRAM to a given value. The Solid
Fill color data is setting by “BTE Foreground Color”.
Figure 7-67 : Solid Fill
The suggested programming steps and registers setting are listed below as reference:
1.
2.
3.
4.
5.
6.
Setting destination layer and address
Æ REG[58h], [59h], [5Ah], [5Bh]
Setting BTE width and height
Æ REG[5Ch], [5Dh], [5Eh], [5Fh]
Setting BTE operation and ROP function Æ REG[51h] Bit[3:0] = 0Ch
Setting foreground Color
Æ REG[63h], [64h], [65h]
Enable BTE function
Æ REG[50h] Bit7 = 1
Check STSR REG Bit6
Æ check 2D final
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RA8875
Version 1.2
7-7
Character / Graphic TFT LCD Controller
Layer Mixed Function
RA8875 provides two layers overlay display function, when two layers configuration of
DPCR(REG[20h] Bit7=1) is selected, users could use LTPR0(REG[52h]), LTPR1(REG[53h]) and
BGTR(REG[67h] ~ REG[69h]) to generate different combination effect of layer one and layer two.
The function of LTPR0, LTPR1 and BGTR refer to Table 7-16.
Table 7-16 : The Function of LTPR0, LTPR1 and BGTR
Reg. NO.
Abbreviation
Description
Layer Transparency Register 0
B[5] Floating Windows Display Related With BGTR
B[2:0] Layer1/2 Display Mode
000b: Only Layer 1 is visible
001b: Only Layer 2 is visible
011b: Transparent mode
52h
LTPR0
010b: Lighten-overlay mode
100b: Boolean OR
101b: Boolean AND
110b: Floating Windows
111b: Reserved
Layer Transparency Register 1
B[7:4] Layer Transparency Setting for Layer 2
0000b: Total display
0001b: 7/8 display
0010b: 3/4 display
0011b: 5/8 display
0100b: 1/2 display
0101b: 3/8 display
0110b: 1/4 display
0111b: 1/8 display
1000b: Display disable
53h
LTPR1
B[3:0] Layer Transparency Setting for Layer 1
0000b: Total display
0001b: 7/8 display
0010b: 3/4 display
0011b: 5/8 display
0100b: 1/2 display
0101b: 3/8 display
0110b: 1/4 display
0111b: 1/8 display
1000b: Display disable
Background Color Register for Transparent
B[4:0] Background Color for Transparent Red
67h
BGTR0
68h
BGTR1
B[5:0] Background Color for Transparent Green
69h
BGTR2
B[4:0] Background Color for Transparent Blue
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RA8875
Version 1.2
7-7-1
Character / Graphic TFT LCD Controller
Only Layer One is Visible
If LTPR0 B[2:0] is set to 000b, only Layer 1 image will be shown on the panel screen. Please
refer to Figure 7-68 as example. This function also could be associated with LTPR1[3:0] and
BGTR to show similar the effect of filter. Refer to the following example as Figure 7-69.
RA8875
RAiO
Layer 2
RAiO
Layer 1
Figure 7-68 : Only Layer One is Visible
RAiO
Layer 1
+
=
LTPR0 B[2:0]= 00h
RAiO
LTPR1 B[3:0] = 04h
BGTR0 B[4:0] = 1Fh
BGTR1 B[5:0] = 00h
BGTR2 B[4:0] = 00h
Figure 7-69 : The Effect of Register LTPR1 and BGTR
7-7-2
Only Layer Two is Visible
If LTPR0 B[2:0] is set to 001b, only Layer 2 image will be show on the panel screen. Refer to the
following example as Figure 7-70 . This function also could be associated with LTPR1[7:4] and
BGTR to show similar the effect of filter. Refer to the following example as Figure 7-71.
RA8875
RAiO
Layer 2
RA8875
Layer 1
Figure 7-70 : Only Layer Two is Visible
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
Layer 2
+
RA8875
= RA8875
LTPR1 B[7:4] = 04h
LTPR0 B[2:0]= 01h
BGTR0 B[4:0] = 00h
BGTR1 B[5:0] = 3Fh
BGTR2 B[4:0] = 00h
Figure 7-71 : The effect of Register LTPR1 and BGTR
7-7-3
Lighten-Overlay Mode
The transparent mode makes the pixel of layer 1 with background color as “transparence”, that
is, Lighten-Overlay Mode provides further visual enhancement image which one image
gradually fades into another image. The following equation describes the lighten-overlay
technique used.
[r,g,b]Lighten-Overlay =χ[r,g,b] Layer 1 +(1- χ)[r,g,b] Layer 2
Where [r,g,b] is pixel data and χ is the weighting factor, it depends on the setting of LTPR1[3:0].
In other word, if LTPR1[3:0] is set as 0100b, the weighting factor χ is equal to 1/2. The
[r,g,b]Lighten-Overlay =1/2[r,g,b] Layer 1 + 1/2[r,g,b]Layer 2 .
About the display effect please refer to the example of Figure 7-72.
RAiO
Layer 1
Layer 2
+
= RAiO
RA8875
RA8875
Figure 7-72 : The Effect of Light-Overlay
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RA8875
Version 1.2
7-7-4
Character / Graphic TFT LCD Controller
Transparent Mode
The transparent mode makes the pixel of layer 1 with BGTR color as “transparence”, that is, the
color of layer 2 of the pixel will be displayed. The function can be used to set the foreground and
background picture overlay display. The foreground picture is written on layer 1 and background
picture is written on layer 2. And then, the transparent area of foreground is written with
background color set by register BGTR. About the display effect please refer to the example of
Figure 7-73.
BGTR Color
RAiO
Layer 1
Layer 2
+
RAiO
=
RA8875
Figure 7-73 : Effect of Transparent
7-7-5
Boolean OR
Layer 1 pixel data and Layer 2 pixel data are displayed on panel screen after logic “OR”
operation.
RAiO
Layer 2
Layer 1
+
RA8875
=
RAiO
RA8875
Figure 7-74 : The Effect of Boolean OR
7-7-6
Boolean AND
Layer 1 pixel data and Layer 2 pixel data are displayed on panel screen after logic “AND”
operation.
RAiO
Layer 2
Layer 1
+
RA8875
=
8875
Figure 7-75 : The Effect of Boolean AND
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RA8875
Version 1.2
7-7-7
Character / Graphic TFT LCD Controller
Floating Window
Floating Windows mode provides the effect of picture in picture (PIP). We could use floating
window function to show a specific part of Layer 2 image on Layer 1 display screen. About the
display effect please refer to the example of Figure 7-76. Floating Windows also could be set to
related with BGTR, when REG[52h] Bit[5] is set to 1. The data within Floating Windows could be
set to related with BGTR. It is similar to transparent mode function, the pixel of layer 2 with
BGTR color as “transparence”, that is, the color of layer 1 of the pixel will be displayed. About
the display effect please refer to the example of Figure 7-77.
Usage:
1. Setting up Floating Windows Start Address by setting register
FWSAXA0[D0h],FWSAXA1[D1h], FWSAYA0[D2h], and FWSAYA0[D3h].
2. Setting up Floating Windows Width and Height by setting register FWW0[D4h],
FWW1[D5h], FWH0[D6h] and FWH1[D7h].
3. Setting up Floating Windows Display Address by setting register FWDXA0[D8h],
FWDXA 1[D9h], FWDYA 0[DAh], and FWDYA 0[DBh].
4. If you want to use Floating Windows related with BGTR function. Remember to enable
REG[52h] bit 5, and set up BGTR color by setting register BGTR0[67h], BGTR1[68h]
and BGTR2[69h].
Layer 2
(FWDXA, FWDYA)
FWW
FWH
RAiO
Layer 1
(FWSAXA, FWSAYA)
FWW
FWH
Floating Windows
Figure 7-76 : The Effect of Floating Windows
Layer 2
(FWDXA, FWDYA)
Layer 1
(FWSAXA, FWSAYA)
FWH
FWW
RAiO RA8875 ★
FWH
FWW
RA8875 ★
BGTR COLOR
Floating Windows
Figure 7-77 : The Effect of Floating Windows Related with BGTR
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
7-8 Touch Panel Function
The one channel and 10 bits resolution A/D converter are implemented in RA8875 for 4-wire Touch
Panel application. The operation method and application information please refer to section 6-5.
There are two types of ADC operating mode for user selection: Auto mode or Manual mode. When
using the manual mode, the touch Event can be detected by an Interrupt signal or the flag detecting
(Polling flag status), it depends on the system configuration. The related descriptions are explained
as following.
There are 4 states for RA8875 touch panel controller: “Idle state”, “touch event checking state”,
“Latch X data state” and “Latch Y data state”. RA8875 provides 2 operation modes for it, that is auto
mode and manual mode. Auto mode runs the operations and justifies the touch event validation
automatically. The manual mode is preferred for some unstable or special applications. The
operation is controlled by manually. So users can arrange the state by themselves, it will be more
flexible than the auto mode.
When touch event is active, there are 2 detection methods provided by RA8875. Hardware interrupts
mode or software polling mode. Table 7-17 show the brief control method for the RA8875 touch
panel controller.
Table 7-17 : Operation Mode and Event Detection for Touch Panel Function
Operation
Mode
Auto
Event
Detection
Description
Interrupt
When touch event happens, read the corresponding X, Y coordination.
Polling
Interrupt
Manual
Polling
RAiO TECHNOLOGY INC.
Polling the touch event, read the corresponding X, Y coordination.
Set the operation state to “Checking touch event” for checking the
touch event, when touch event interrupt happens, set the state to
“Latch X data” and “Latch Y data” for latching the corresponding X, Y
coordination, then read the X, Y data and set operation state to “Idle
state”
Polling the touch event, and read the corresponding X, Y coordination.
Set the operation state to “Checking touch event” for checking the
touch event. Polling the touch event status before confirming the touch
event, set the state to “Latch X data” and “Latch Y data” for latching
the corresponding X, Y coordination, then read the X, Y data and set
operation state to “Idle state”
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
7-8-1
Touch Panel Operation Mode
7-8-1-1 Auto Mode
Auto mode is the easiest way to implement Touch Panel application. User only needs to enable
the related register and RA8875 will execute the touch panel function and latch the touch data
automatically. Please refer to the follow chart as below.
START
ISR
Enable Touch Panel
(Reg[70h] B7=1)
0
Check INT State
Reg[F1h] B2=?
Set Auto Mode
(Reg[71h] B6=0)
1
Read X,Y-axis
Read Reg[72h]
Read Reg[73h]
Read Reg[74h]
Enable TP INT
(RegpF0h] B2 = 1)
Other Functions
Cause the
Interrupt
Execute Function
Other Function
Clear TP INT Status
(Write Reg[F1h] B2=1)
Figure 7-78 : Auto Mode Flowchart for Touch Panel
Table 7-18 : Related Registers for Auto-Mode of T/P Function
Reg.
Bit_Num
TPCR0
TPCR1
Description
Reference
Bit7
Enable Touch Panel function
REG[70h]
Bit6
“Auto-Mode” = 0
Bit2
Set de-bounce enable for ADET(note)
REG[71h]
TPXH
Bit[7:0]
Touch Panel SEG data MSB byte
REG[72h]
TPYH
Bit[7:0]
Touch Panel COM data MSB byte
REG[73h]
Bit[3:2]
Touch Panel COM data LSB 2bit
Bit[1:0]
Touch Panel SEG data LSB 2bit
TPXYL
REG[74h]
Note : It is suggested to set the de-bounce function for ADET in auto mode. Or the noise may
cause the mistake judgment of touch event.
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
7-8-1-2 Manual Mode
The “Manual Mode” means that the operation states are manually operated by user. Including
“Touch event checking” 、 “Latch X data” and “Latch Y data”. The whole operations are
completed by setting the mode with register(TPCR1[1:0]). The advantage of using Manual Mode
is the flexibility for applications. The debounce time for X, Y data and mode switch time can be
decided by user. It will decrease the possibility of failures for Auto mode in some tough case.
Under the ”Manual Mode”, user needs to justify the validation of the touch event by continue
polling the status of register. Generally, an enough times of continue accessing the activity of
touch event from status register will be confirmed as a valid touch event. The method allows
more flexibility and less mistake of justification for different application, but more MCU resource
will be occupied.
START
Enable Touch Panel
(Reg[70h] B7=1)
Set Manual Mode
(Reg[71h] B6=1)
Enable TP INT
(RegpF0h] B2 = 1)
Set state to
“Checking Touch Event”
(Reg[71h] B1~0=01b)
Other Function
ISR
0
Check INT State
Reg[F1h] B2=?
1
Set state to
“Latch X data”
(Reg[71h] B1~0=10b)
Set state to
“Idle”
(Reg[71h] B1~0=00b)
Other Functions
Cause the
Interrupt
Read X,Y-axis
Read Reg[72h]
Read Reg[73h]
Read Reg[74h]
Wait Enough time
for Stability
Set state to
“Latch Y data”
(Reg[71h] B1~0=11b)
Execute Function
Wait Enough time
for Stability
Clear TP INT Status
(Write Reg[F1h] B2=1)
Figure 7-79 : Manual Mode Flowchart for Touch Panel
Table 7-19 : Related Registers for Manual-Mode of T/P Function
Reg.
Bit_Num
TPCR0
Bit7
Enable Touch Panel function
Bit6
“Manual-Mode” = 1
Bit2
Set de-bounce function for ADET(note)
TPCR1
Description
Reference
REG[70h]
REG[71h]
Bit[1:0]
Mode Selection for TP Manual Mode
TPXH
Bit[7:0]
Touch Panel SEG data MSB byte
REG[72h]
TPYH
Bit[7:0]
Touch Panel COM data MSB byte
REG[73h]
Bit[3:2]
Touch Panel COM data LSB 2bit
Bit[1:0]
Touch Panel SEG data LSB 2bit
TPXYL
REG[74h]
Note: If user don’t do the software de-bounce for touch event, it can be set as de-bounce enable. Or
user can do the de-bounce by software. Then the function can be set as disable.
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RA8875
Version 1.2
7-8-2
Character / Graphic TFT LCD Controller
Touch Event Detection Modes
Touch Event can be detected from “Interrupt Mode” or “Polling Mode” that depend on the
system configuration. The description of the “Interrupt Mode” and “Polling Mode” are explained
as following sections.
7-8-2-1 External Interrupt Mode
Under the “Interrupt Mode” RA8875 hardware interrupt pin(INT) must be connected correctly
to the MCU interrupt input pin first. The major processes are listed as follows:
1.
2.
3.
4.
5.
6.
7.
Enable Touch Panel function. ( REG[70h] Bit7 = 1 )
Set operation mode for TP controller as Auto mode or Manual mode.（REG[71h] Bit6）
Enable Touch Panel Interrupt. ( REG[F0h] Bit6 = 1 )
When interrupt asserts, the IP jumps to the entry of ISR and check if TP interrupt.
If yes, according to the operation mode, doing the data latch for X, Y axis.
Process the corresponding jobs for the touch event.
Clear the interrupt status bit. ( set REG[F1h] Bit2 = 1 ) and quit the ISR
7-8-2-2 Software Polling Mode
Under the ”Polling Mode”, no interrupt pin is needed for connection. The status of touch
event can be read from 3 methods. Listed as follows:
1. From the status register(STSR) bit 5. The status comes from the hardware directly and
don’t do any de-bounce for it. It is suggested to confirm the events by software debounce.
2. From TPXYL(REG[74h]) bit 7. The bit comes from the hardware directly too. It’s the
same as STSR bit 5.
3. From the INTC2(REG[F1h] bit2), the same behavior like the hardware interrupt. Just by
software polling the event of interrupt.
To sum up, programmer can check the status of Touch Panel Event from the Bit5 of STSR or
Bit2 of INTC2, the difference between those of two methods is described below :
1. The Bit5 of STSR reflects the current Touch status. When touch event occurring, the Bit5
is set to 1. On the other hand, Bit5 will be automatically updated to 0 without touch event
occurring. This method is usually used in the manual mode.
2. The Bit2 of INTC2 records the Touch Panel status. When a touch event is occurring, this
bit will be set to 1. But please take care that, the bit2 of INTC2 won’t be automatically
cleared to 0 after touch event is disappear; it need to be cleared by programmer. This
function is usually used in the external interrupt mode.
Note : The bit5 of STSR is controlled by ADC circuit directly, once the Touch Panel is
touched, this bit will be set to 1. If the touch event is unstable, it might need a debounced solution to make sure the touch event is valid. The bit5 of STSR is only
active at “Manual mode”. When setting RA8875 to “Auto-mode, the touch event will
be automatically checked. Only the valid touch event will cause the interrupt.
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RA8875
Version 1.2
7-8-3
Character / Graphic TFT LCD Controller
Touch Panel Sampling Time Reference Table
When using the auto mode of Touch Panel function, and the touch event occurring, RA8875
adapts a specific wait time for X, Y data stability. It is recommended to select a suitable T/P
sampling time to avoid the mistake of ADC data latch. Please refer to the following table for the
ADC sampling time.
Table 7-20 : Touch Panel Sampling Time Reference Table
Touch Panel Sampling Time - REG[70h] Bit[6:4]
SYS_CLK
REG[70h] [2:0]
000b
001b
010b
011b
100b
101b
110b
111b
10M
20M
30M
40M
50M
000
000
000
001
010
011
100
101
--000
001
010
011
100
101
--000
000
001
010
011
100
---000
001
010
011
100
---000
001
010
011
100
Note : The clock source of ADC can not exceed 10MHz.
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
7-9 KEYSCAN
The key-scan controller in RA8875 provides a smart interface for key application. The related
registers of key-scan function are KSCR(REG[C0h], [C1h]), and KSDR(REG[C2h], [C3h], [C4h])..
The RA8875 Key-Scan controller features are given below :
1. Supporting with up-to 4x5 Key-Scan Matrix
2. Programmable setting of sampling times and scan frequency of Key-Scan
3. Adjustable long key-press timing
4. Multi-Key is available (up-to 3 keys at the same time)
5. The function of “Key stroke to wake-up the system”
KSCR is the KEYSCAN control and status register, it is used to configure the options for KEYSCAN,
such as data sample time, sample clock frequency or long key function enable etc. When key-press
is active, user can sense it from the interrupt of KEYSCAN. The status bit of KSCR2(REG[C1h]
bit1~0 will update the number of current key press. Then user can get the key code directly from
KSDR. Table 7-21 is the key code mapping to key-pad matrix for normal press(note). The key code
will be stored in KSDR0~2(REG[C2h~C4h]) when key was pressed. If it was a long time press(note),
then the key code is show as
Table 7-22.
Table 7-21 : Key Code Mapping Table (Normal Key)
Column# (KIN#)
Row# (KOUT#)
C0
C1
C2
C3
C4
R0
00h
01h
02h
03h
04h
R1
10h
11h
12h
13h
14h
R2
20h
21h
22h
23h
24h
R3
30h
31h
32h
33h
34h
Table 7-22 : Key Code Mapping Table (Long Key)
Column# (KIN#)
Row# (KOUT#)
C0
C1
C2
C3
C4
R0
80h
81h
82h
83h
84h
R1
90h
91h
92h
93h
94h
R2
A0h
A1h
A2h
A3h
A4h
R3
B0h
B1h
B2h
B3h
B4h
Note : “Normal key” means a key press that qualified by the sample time of RA8875. “Long Key”
means a key press that keeps “pressed” for a specified long time period. That is, a “Long
Key” must be a “Normal Key” first. Sometimes they need to be separated for some
applications.
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
When the multi-key function is applied, the up to 3 pressed keys data will be saved in the register of
KSDR0, KSDR1 and KSDR2. Note that the order of keys saving is determined on the position(or key
code) of the keys, not the order of keys being pressed; please refer to the following example:
Press the key-code in turn of 0x34, 0x00 and 0x22, press multi-key at the same time, the key-code
will be saved in KSDR0~2:
KSDR0 = 0x00
KSDR1 = 0x22
KSDR2 = 0x34
The basic features of above Key-Scan settings are introduced as follows:
Table 7-23
Reg.
KSCR1
Bit_Num
Bit 7
Bit 6
Bit [5:4]
Bit [2:0]
Bit [7]
KSCR2
KSDR0
KSDR1
KSDR2
INTR
INTC2
Description
Key-Scan enable bit
Long Key Enable bit
Key-Scan sampling times setting
Key-Scan scan frequency setting
Reference
REG[C0h]
Key-Scan Wakeup Function Enable Bit
REG[C1h]
Bit [3:2]
long key timing adjustment
Bit [1:0]
The number of key hit
Bit [7:0]
Key code for pressed key
REG[C2h ~ C4h]
Bit 4
Bit 4
Key-Scan interrupt enable
Key-Scan Interrupt Status bit
REG[F0h]
REG[F1h]
Enabling the Key-Scan functions, programmer can use following methods to check keystroke.
1) Software check method: to know the key be pressed from keeping check the status of KeyScan (Bit-4 of INTC2 REG[F1h])
2) Hardware check method: to know the key be pressed from external interrupt signal
Please be aware that when key-scan interrupt enable bit(INTC1 bit 4) is set as “1” and key event of
interrupt happens, the interrupt status of Key-Scan (Bit-4 of INTC2) is always set to “1”, no matter
which method is used, programmer have to clear the status to 0 after reading the correct Key Code,
otherwise the interrupt will be kept that no more interrupt is generated again.
Besides, RA8875 allows the “Key-stroke wakeup function” for sleep mode. By setting the function on,
any legal key-stroke event can wakeup RA8875 from sleep mode. To sense the wakeup event,
RA8875 can assert hardware interrupt for MCU which can do software polling from RA8875. Table
7-24 lists the relative register and function description for reference.
Table 7-24
Reg.
Bit_Num
Description
Reference
KSCR2
Bit 7
Enable Key-Scan wake-up function
REG[C1h]
INTR
Bit 4
Wake-up interrupt enable bit
REG[F0h]
INTC2
Bit4
Key-Scan Interrupt Status bit
REG[F1h]
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
The flowchart of register settings for above applications are shown as following:
1. Software Method
Start
Enable Key Scan (KS)
Execute Function
(REG[C0] B7 = 1)
0
Check KS status
Clear KS status
REG [F1h] B4 = 1
(REG [F1h] B4 = 1)
1
Read Key Press Number
End
Read Key Code –
REG C2h,
REG C3h,
REG C4h
Figure 7-80 : Key-Scan Flowchart for Software Polling
2. Hardware Method
Start
ISR
Enable Key Scan (KS)
(REG [C0h] B7 = 1)
Check KS status
(REG[F1h] B4 = ?)
Enable KS INT Mask
Other INT Functions
(REG[F0h] B4 = 1)
Read Key Press Number
Read Key Code
Ext.INT Event
REG[C2h],REG[C3h],REG[C4h]
Execute Functions
Other Functions
Clear KS status
(REG[F1h] B4=?)
ISR Termination
Figure 7-81 : Key-Scan for Hardware Interrupt
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
7-10 DMA (Direct Memory Access)
DMA function provides a faster method for user to update/transfer mass data to DDRAM. The only
source of DMA function in RA8875 is external serial Flash/ROM interface. There are two kinds of
data type defined for the DMA source. One is continuous mode and the other is block mode. It
provides a flexible selection for user to apply. The destination of DMA function is dominated by active
window in DDRAM and the specific data in serial Flash/ROM is depended by Color Depth Setting
(REG[10h] Bit 3-2). When DMA function is active, the specific data in serial Flash/ROM (refer to
Figure 7-82) will be transferred one by one to DDRAM by RA8875 automatically. After the DMA
function is completed, an interrupt will be asserted to note MCU. About the detail operation, please
refer to following sections.
24’h000
R2 R1 R0 G2 G1 G0 B1 B0
24’h000
R4 R3 R2 R1 R0 G5 G4 G3
24’h001
R2 R1 R0 G2 G1 G0 B1 B0
24’h001
G2 G1 G0 B4 B3 B2 B1 B0
24’h002
R2 R1 R0 G2 G1 G0 B1 B0
24’h002
R4 R3 R2 R1 R0 G5 G4 G3
24’h003
R2 R1 R0 G2 G1 G0 B1 B0
24’h003
G2 G1 G0 B4 B3 B2 B1 B0
.
.
.
.
.
.
.
.
.
.
.
.
the specific 8-bit data in serial Flash/ROM
the specific 16-bit data in serial Flash/ROM
Figure 7-82 : The Specific Data in Serial Flash/ROM
7-10-1 DMA In Continuous Mode
In this mode, DMA controller reads data from source serial Flash/ROM address that is set by
source starting address register(SSAR) to the end address of source starting address
register(SSAR) + DMA transfer number register(DTNR). Users just set up the range of active
windows to write to destination display memory.
Usage:
1. Setting up the range of active windows(REG[30h] ~REG[37h]) and memory write
cursor position(REG[46h] ~REG[49h])
2. Setting up Serial Flash/ROM configuration(REG[05h]).
3. Setting up DMA source starting address(REG[B0h] ~REG[B2h]).
4. Setting up DMA transfer number(REG[B4h], REG[B6h]and REG[B8h]).
5. Enable DMA start and check DMA busy signal by REG[BFh] bit 0.
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
Source Serial ROM Address
Destination Display Memory
SSAR
(CURH, CURV)
PIC1
DTNR
DMA
PIC2
Active Windows
Continuous Mode
PIC3
Figure 7-83 : DMA Continuous Mode
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
7-10-2 DMA In Block Mode
In this mode, users could read block data flexibly. DMA controller reads data from source serial
Flash/ROM address that is set by source starting address register(SSAR) to the end address of
source starting address register(SSAR) and depends on the values of block width
register(BWR), block height register(BHR) and source picture width register(SPWR) to calculate
block address. Users just set up the range of active windows to write to destination display
memory.
1. Setting up the range of active windows(REG[30h] ~REG[37h]) and memory write
cursor position(REG[46h] ~REG[49h])
2. Setting up serial Flash/ROM configuration(REG[05h]).
3. Setting up DMA source starting address(REG[B0h] ~REG[B2h]).
4. Setting up DMA block width(REG[B4h] and REG[B5h]).
5. Setting up DMA block height(REG[B6h] and REG[B7h]).
6. Setting up DMA source picture width(REG[B8h] and REG[B9h]).
7. Enable DMA block mode by setting REG[BFh] bit 1.
8. Enable DMA start and check DMA busy signal by setting REG[BFh] bit 0.
Source Serial ROM Address
Destination Display Memory
SPWR
PIC1
(CURH, CURV)
SSAR
DMA
BHR
Active Windows
PIC2
BWR
Active Windows
Block Mode
PIC3
Figure 7-84 : DMA Block Mode
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
7-11 PWM
RA8875 provide two sets of programmable PWM (Pulse Width Modulation). The PWM frequency
and duty can be set by register. Besides, if the PWM function is disabled, it can use as normal output
signal. The relative function setting please refers to the Table 7-25 as below.
Table 7-25 : PWM Setting
Reg.
Description
Bit_Num
P1CR
P1DCR
P2CR
P2DCR
Bit7
PWM1 Function Enable
Bit6
PWM1 Disable
Bit[3:0]
Clock Source Divide Ratio Select
Bit[7:0]
PWM1 Duty Cycle Select
Bit7
PWM2 Function Enable
Bit6
PWM2 Disable
Bit[3:0]
Clock Source Divide Ratio Select
Bit[7:0]
PWM2 Duty Cycle Select
Reference
REG[8Ah]
REG[8Bh]
REG[8Ch]
REG[8Dh]
The two PWM outputs are independent. Register REG[8Bh] and REG[8Dh] are used to control the
duty of PWM outputs. The normal application is used to control the LED back-light of TFT Panel.
Please refer to Section 6-6 and Figure 6-43 for detail. The following Figure 7-85 and Figure 7-86
are two examples to show the PWM output.
TPWM
TH
TL
Example-2:
System Clock = 10Mhz,
Register P1CR Bit[3:0] = 0010b Æ Clock Source = 10MHz/4 = 2.5MHz
TPWM = 256*(1/2.5MHz) = 102.4 µs
Register P1DCR Bit[7:0] = 7Fh Æ
TH = 128*(1/2.5MHz) = 51.2µs
TL = (256-128) * (1/ 2.5MHz) = 51.2µs
Figure 7-85 : Example 1 of PWM_OUT Pulse
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
TPWM
TH
TL
Example-1:
System Clock = 10Mhz,
Register P1CR Bit[3:0] = 0001b Æ Clock Source = 10MHz/2 = 5MHz
TPWM = 256*(1/5MHz) = 51.2µs
Register P1DCR Bit[7:0] = 0Fh Æ
TH = 16*(1/5MHz) = 3.2µs
TL = (256-16) * (1/ 5MHz) = 48µs
Figure 7-86 : Example 2 of PWM_OUT Pulse
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
7-12 Sleep Mode
RA8875 provides a Sleep Mode function for power saving request. The Sleep mode stops the
system oscillator, DDRAM, Font ROM and ignores external signal in order to conserve power. But
the output status of PWM function is still keeping as register setting.
The device provides three wake-up methods for quitting from sleep mode. One is “Register Setting
Wakeup”, another method is “Touch Panel Event Wakeup”, and latest one is “KEYSCAN Event
Wakeup”. “Register Setting Wakeup” is to quit the sleep function by setting bit1 of REG[01h] to 0.
That is, wakeup function is operated by MCU. The “Touch Panel Event Wakeup” is another method
to wakeup RA8875 from sleep mode. One must set both REG [70h] bit7(TP enable) and bit3(TP
wakeup enable) to 1 before RA8875 enters sleep mode, and RA8875 will quit from sleep mode while
touch event occurring. To note that if TP manual mode is set, the “Wait for TP event” state must be
set or the “touch event” will not be detected. The third method for wakeup function is using the
“Keystroke Event”. Similar with previous TP wakeup, the enable bit of KEYSCAN function and
Wakeup function should be set. The KEYSCAN enable bit is REG[C0h] bit 7 and KEYSCAN wakeup
enable bit is REG[C1h] bit 7. Please set it as “1” before entering “Sleep mode”. Any keystroke of
KEY wills wakeup RA8875. It should be noted that when RA8875 quits from the sleep mode, the key
that is pressed will not be recorded by RA8875.
When wake-up event occurs, it is suggested that a period of time must be waited before accessing
RA8875. Because an extra delay time is needed for ensuring the stabilization of the oscillator and
the internal PLL, this delay time takes about 10ms to resume normal operation. The relative register
description is listed below.
Table 7-26 : Sleep and Wake-up Relative Register Setting
Reg.
Bit_Num
PWRR
Bit1
Bit7
TPCR0
Bit3
KSCR1
Bit7
KSCR2
Bit7
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Description
Sleep Mode
0 : Normal mode.
1 : Sleep mode.
Touch Panel Enable Bit
0 : Disable
1 : Enable
Touch Panel Wakeup Enable
0 : Disable the Touch Panel wake-up function.
1 : Touch Panel can wake-up the sleep mode.
Key-Scan Enable Bit(KEY_EN)
1 : Enable.
0 : Disable.
Key-Scan Wakeup Function Enable Bit
0: Key-Scan Wakeup function is disable.
1: Key-Scan Wakeup function is enable.
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Reference
REG[01h]
REG[70h]
REG[C0h]
REG[C1h]
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
When RA8875 in Sleep mode, the status of output signals are show as Table 7-27.
Table 7-27 : The Signals State of Sleep Mode
Signals
State
WAIT#
High
INT#
High
PWM1, PWM2
Low
GPIO[5:0]
Low
VA[18:0]
Low
RAM_OE#
Low
RAM_CS#, RAM_WR#, ROM_CS#
High
PDAT[15:0]
Low
VSYNC, HSYNC
High
PCLK, DE
High
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
8. AC/DC Characteristic
8-1 Maximum Absolute Limit
Table 8-1 : Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
VDDP
Supply Voltage Range (Note 4)
OSC_VDDP
-0.3V~4.0V
V
ADC_VDD
Input Voltage Range
VIN
-0.3 to VDD+0.3
V
Power Dissipation
PD
≦150
mW
Operation Temperature Range
TOPR
-30 to +85
℃
Storage Temperature
TST
-45 to +125
℃
TSOLDER
260
℃
Soldering Temperature (10 seconds, Note 1)
Note :
1. The humidity resistance of the flat package may be reduced if the package is immersed in
solder. Use a soldering technique that does not heat stress the package.
2. If the power supply has a high impedance, a large voltage differential can occur between
the input and supply voltages. Take appropriate care with the power supply and the layout
of the supply lines.
3. All supply voltages are referenced to GND = 0V.
4. CORE_VDD、LDO_OUT、OSC_VDD are power output and not be included.
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
8-2 DC Characteristic
Table 8-2 : DC Characteristic Table
Parameter
Symbol
Min.
Typ.
Max.
Unit
ADC_VDD
VDDP
3.0
3.3
3.6
V
1.6
1.8
2.0
V
Add External 1uF
Capacitor
ADC_VREF
--
0.5VDD3
(±5%)
--
V
Add External 1uF
Capacitor
FOSC
--
15
30
MHz
VDD3 = 3.3 V
SYS_CLK
1
20~30
60
MHz
VDD3 = 3.3 V
Input High Voltage
VIH
0.8 VDD3
--
VDD3
V
Input Low Voltage
VIL
GND
--
0.2 VDD3
V
Output High Voltage
VOH
VDD-0.4
--
VDD3
V
Output Low Voltage
VOL
GND
--
GND +0.4
V
Input High Voltage
VIH
0.7 VDD3
--
VDD3
V
Input Low Voltage
VIL
GND
--
0.3 VDD3
V
IIH
--
--
+2
μA
(Note 2)
IIL
--
--
-2
μA
(Note 2)
Operation Current
IOPR
20
--
50
mA
Sleep Mode
ISLP
--
320
--
μA
System Voltage(VDD3)
Core Voltage(VDD18)
ADC Reference Voltage
LDO_OUT
CORE_VDD
Oscillator Clock
PLL Output Clock
Condition
Input
Output
Schmitt-Trigger Input (Note 1)
Input Leakage
Current 1
Input Leakage
Current 2
(Note 2)
Note :
1. Signals RD#, WR#, CS#, RS, RST# are inputs of Schmitt-trigger.
2. Case 2. : VDDP = VDD3 = 3.3V, Oscillator Clock = 25MHz, System Clock = 20~60MHz,
Source = 800, Gate = 480, VSYNC = 45~65Hz, TA=25℃.
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
9. Package
XP
YN
YP
XN
ADC_VREF
ADC_GND
PDAT15
PDAT14
PDAT13
PDAT12
PDAT11
PDAT10
PDAT9
VDDP
LDO_GND
LDO_OUT
PDAT8
PDAT7
PDAT6
PDAT5
PDAT4
PDAT3
PDAT2
PDAT1
PDAT0
9-1 Pin Assignment
75
ADC_VDD
RD# / EN
WR# / RW#
CS#
RS
C86
DB0
DB1
DB2
GND
CORE_VDD
VDDP
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
70
65
60
55
51
50
76
80
45
TM
RAiO
85
40
RA8875L3N
90
35
1020-N
95
Date code (Year 2010, 20th week)
30
100
○
26
5
10
15
20
25
OSC_GNDP
OSC_VDDP
XI
XO
OSC_VDD
OSC_GND
WAIT#
INT#
RST#
TEST0
TEST1
TEST2
VDDP
PWM1
PWM2
GND
CORE_VDD
SFCL
SFDI
SFDO
SFCS0#
SFCS1#
IICA0
IICA1
PS
1
DE
PCLK
VSYNC
HSYNC
GPOX
GPIX
SCL
SDI
SDO
SCS#
VDDP
GND
CORE_VDD
KIN0 / GPI0
KIN1 / GPI1
KIN2 / GPI2
KIN3 / GPI3
KIN4 / GPI4
KOUT0 / GPO0
KOUT1 / GPO1
KOUT2 / GPO2
KOUT3 / GPO3
SIFS0
SIFS1
GND
Figure 9-1 : RA8875 Pin Assignment
RAiO TECHNOLOGY INC.
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RA8875
Version 1.2
Character / Graphic TFT LCD Controller
9-2 Package Outline Dimensions
Figure 9-2 : RA8875 Package Outline Dimensions
9-3 Product Number
The complete product number of RA8875 is “RA8875L3N”, RAiO is dedicated to environmental
protection and Now RAiO has already started to supply customers with environmentally friendly Lead
Free devices in order to reduce or eliminate hazardous substances contained within the packaging.
RAiO guarantees that its product contents will conform to the limitation of European Union materials
restrictions :
„
„
„
The Restriction of Hazardous Substances Directive RoHS (2002/95/EC)
Restriction on Perfluorooctane sulfonates PFOS & PFOA (2006/122/EC)
Registration, Evaluation, Authorisation and restriction of CHemicals REACH (1907/2006)
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