RAiO RA8872 - RAiO Technology Inc.

RAiO
RA8872
Character/Graphic
TFT LCD Controller
Specification
Version 1.4
December 11, 2014
RAiO Technology Inc.
©Copyright RAiO Technology Inc. 2010, 2011, 2012, 2013, 2014
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
Update History
Version
Date
1.0
April 20, 2010
1.1
Description
Preliminary version.
September 14, 2010
1. Update pin description of Section 4-4 : ADC_VDD、ADC_GND
2. Update Section 5-9 : REG[88h] - the reference setting of OSC
clock (FIN) and REG[88h] Bit[4:0]
3. Update Figure 6-17、Figure 6-20
4. Update Table 8-2 : DC Characteristic
5. Update Figure 10-2 (Add part model and parameter)
6. Update Chapter 11: Demo Program
December 07, 2010
1. Update Table 8-2 : DC Characteristic
December 19, 2011
1. Update Table 7-19
1. Update Table 6-6
December 22, 2011
2. Update Table 8-2
3. Update Chapter 11: Demo Program
1.2
February 10, 2012
1. Add the Note of REG[21h]Bit7
February 7, 2013
1. Update Section 4-4 : the description of CORE_VDD
November 11, 2014
1. Add the Note of REG[04h]Bit0~1
November 20, 2014
1. Update Section 7-4-3 : Pattern
December 11, 2014
1. Add REG[02h] description in BTE flow step for write/read data
(7-7-4-1, 7-7-4-2, 7-7-4-5, 7-7-4-9, 7-7-4-10)
1.3
1.4
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RA8872
Version 1.4
Chapter
1.
2.
3.
4.
Character / Graphic TFT LCD Controller
Content
Page
Description................................................................................................ 6
Feature ...................................................................................................... 6
Block Diagram .......................................................................................... 7
Pin Definition ............................................................................................ 8
4-1
4-2
4-3
4-4
MCU Interface ....................................................................................................... 8
LCD Panel Interface ............................................................................................. 9
Touch Panel and PWM Interface ......................................................................... 9
Clock and Power Interface ................................................................................ 10
5. Register Table......................................................................................... 12
5-1 Status Register ................................................................................................... 12
5-2 System & Configuration Registers ................................................................... 13
5-3 LCD Display Control Registers ......................................................................... 18
5-4 Active Window Setting Registers ..................................................................... 21
5-5 Cursor Setting Registers ................................................................................... 24
5-6 Block Transfer Engine(BTE) Control Registers ............................................... 27
5-7 Touch Panel Control Registers ......................................................................... 32
5-8 Graphic Cursor Setting Registers..................................................................... 34
5-9 PLL Setting Registers ........................................................................................ 35
5-10 PWM Control Registers.................................................................................... 36
5-11 Drawing Control Registers .............................................................................. 40
6. Hardware Interface ................................................................................. 43
6-1 MCU Interface ..................................................................................................... 43
6-1-1 Protocol................................................................................................................................. 44
6-1-2 Read Status Register ...........................................................................................................46
6-1-3 Write Command to Register ................................................................................................47
6-1-4 Display RAM Read / Write....................................................................................................48
6-1-5 Interrupt and Wait................................................................................................................. 49
6-1-5-1 Interrupt .....................................................................................................................49
6-1-5-2 Wait............................................................................................................................ 50
6-1-6 Data Format........................................................................................................................... 51
6-2
6-3
6-4
6-5
6-6
6-7
6-8
Color Setting Mode ............................................................................................ 52
LCD Interface ...................................................................................................... 53
Touch Panel I/F ................................................................................................... 56
PWM .................................................................................................................... 58
Clock and PLL .................................................................................................... 59
Reset ................................................................................................................... 61
Power .................................................................................................................. 63
6-8-1 Power Pin Description .........................................................................................................63
6-8-2 Power Architecture............................................................................................................... 63
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
7. Function Description ............................................................................. 64
7-1 Screen Rotation.................................................................................................. 64
7-1-1
7-1-2
7-1-3
7-1-4
Normal ................................................................................................................................... 64
90 Degree .............................................................................................................................. 64
180 Degree ............................................................................................................................ 65
270 Degree ............................................................................................................................ 65
7-2 Scroll Function ................................................................................................... 66
7-2-1 Horizontal Scroll ................................................................................................................... 66
7-2-2 Vertical Scroll........................................................................................................................ 66
7-3 Active Window.................................................................................................... 67
7-3-1 Normal and 90 Degree Rotation..........................................................................................67
7-3-2 180 Degree and 270 Degree Rotation.................................................................................67
7-4 Cursor & Pattern................................................................................................. 68
7-4-1 Graphic Cursor ..................................................................................................................... 68
7-4-2 Text Cursor............................................................................................................................ 70
7-4-2-1 Cursor Position ..........................................................................................................70
7-4-2-2 Cursor Blinking ..........................................................................................................70
7-4-2-3 Cursor Height and Width ...........................................................................................71
7-4-3 Pattern ................................................................................................................................... 72
7-5 Font ..................................................................................................................... 73
7-5-1
7-5-2
7-5-3
7-5-4
7-5-5
7-5-6
Internal Font ROM ................................................................................................................ 73
CGRAM .................................................................................................................................. 78
90 Degree Font ..................................................................................................................... 79
Bold, Enlargement, Transparent Font ................................................................................79
Font Change Line when Setting Write Auto Move ............................................................ 80
Font Full-Alignment ............................................................................................................. 80
7-6 Geometric Pattern Drawing Engine .................................................................. 81
7-6-1 Circle Input............................................................................................................................ 81
7-6-2 Square Input ......................................................................................................................... 82
7-6-3 Line Input .............................................................................................................................. 83
7-7 BTE (Block Transfer Engine) Function............................................................. 84
7-7-1 Select BTE Start Point Address and Layer ........................................................................87
7-7-2 BTE Operations .................................................................................................................... 87
7-7-2-1 Write BTE ..................................................................................................................87
7-7-2-2 Read BTE ..................................................................................................................87
7-7-2-3 Move BTE ..................................................................................................................87
7-7-2-4 Solid Fill .....................................................................................................................87
7-7-2-5 Pattern Fill..................................................................................................................87
7-7-2-6 Transparent Pattern Fill .............................................................................................87
7-7-2-7 Transparent Write BTE ..............................................................................................87
7-7-2-8 Transparent Move BTE..............................................................................................87
7-7-2-9 Color Expansion ........................................................................................................88
7-7-2-10 Move BTE with Color Expansion ...............................................................................88
7-7-3 BTE Access Memory Method ..............................................................................................89
7-7-3-1 Block Memory Access ............................................................................................... 89
7-7-3-2 Linear Memory Access ..............................................................................................89
7-7-4 BTE Function Explaination..................................................................................................90
7-7-4-1 Write BTE with ROP ..................................................................................................90
7-7-4-2 Read BTE (Burst Read like function)......................................................................... 92
7-7-4-3 Move BTE in Positive Direction with ROP.................................................................93
7-7-4-4 Move BTE in Negative Direction with ROP ...............................................................95
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
7-7-4-5
7-7-4-6
7-7-4-7
7-7-4-8
7-7-4-9
7-7-4-10
7-7-4-11
7-7-4-12
7-7-4-13
Transparent Write BTE ..............................................................................................97
Transparent Move BTE Positive Direction................................................................. 99
Pattern Fill with ROP ...............................................................................................100
Pattern Fill with Transparency .................................................................................102
Color Expansion ......................................................................................................104
Color Expansion with Transparency ........................................................................107
Move BTE with Color Expansion .............................................................................109
Move BTE with Color Expansion and Transparency ............................................... 111
Solid Fill 112
7-8 Layer Mixed Function ...................................................................................... 113
7-8-1
7-8-2
7-8-3
7-8-4
7-8-5
7-8-6
7-8-7
Only Layer One is Visible .................................................................................................. 114
Only Layer Two is Visible .................................................................................................. 115
Transparent Mode .............................................................................................................. 115
Lighten-Overlay Mode........................................................................................................ 116
Boolean OR......................................................................................................................... 116
Boolean AND....................................................................................................................... 116
Layer in Scroll Mode .......................................................................................................... 117
7-9 Touch Panel Function ...................................................................................... 118
7-9-1 Auto Mode........................................................................................................................... 118
7-9-2 Manual Mode....................................................................................................................... 119
7-9-2-1 External Interrupt Mode ...........................................................................................120
7-9-2-2 Polling Mode ............................................................................................................122
7-9-3 Touch Panel Sampling Time Reference Table .................................................................124
7-10 PWM................................................................................................................. 125
7-11 Sleep Mode ....................................................................................................... 127
8. AC/DC Characteristic ........................................................................... 128
8-1 Maximum Absolute Limit ................................................................................. 128
8-2 DC Characteristic ............................................................................................. 129
9. Package................................................................................................. 130
9-1 Pin Assignment ................................................................................................ 130
9-2 Package Outline ............................................................................................... 131
9-3 Product Number ............................................................................................... 131
10. Application Circuit.............................................................................. 132
11. Demo Program.................................................................................... 134
12. Summary of Register Table ............................................................... 147
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
1. Description
RA8872 is a TFT LCD controller which supports the character and graphic mixed display. It is designed to
meet the requirement of middle size TFT module up to 320x240 pixels with characters or 2D graphic
application. With internal RAM, RA8872 can supports 65K color for 320x240 dots TFT Panel, 4K color for
640x240 display, or 4K color for 320x240 dots with 2-Layers.
The embedded CGROM is capable to display the alphaset of international standard ISO 8859-1/2/3/4. It
includes 256x4 characters and can satisfiies almost English or Eurpean language family countries. For
graphic usage, RA8872 supports a 2D Block Transfer Engine(BTE) that is compatible with 2D BitBLT
function for processing the mass data transfer function. The geometric speed-up engine provides user an
easy way to draw the programmable geometric shape by hardware, like line, square and circle. Besides,
many powerful functions are combined with RA8872, such as screen rotation function, scroll function,
graphic pattern, 2-layer mixed display and font enlargement function. These functions will save user a
large of software effort during developement period.
RA8872 is a powerful and cheap choice for color application. To reduce the system cost, RA8872 proivde
low cost 8080/6800 MCU I/F, a flexible 4-wires Touch Panel controller, PWM for adjusting panel
back-light and some GPIOs. With the RA8872 design-in, user can achieve an easy-to-use, low-cost and
high performace system compared with the other solution.
2. Feature
Internal PLL.
‹ Sleep Mode with Low Power Consumption.
‹ Operation Voltage: 3.0V~3.6V
‹ Package: LQFP-100pin.
‹ Support Text/Graphic Mixed Display Mode.
‹ Support 8/12/16-Bits Generic RGB TFT
Panel:
2 Layers: Up to 320x240 Pixels 4K Color.
1 Layer: Up to 320x240 Pixels 65K Color.
‹ Color Depth TFT: 256/4K/65K Colors.
‹ Supporting MCU Interface: 8080/6800 with 8
Data Bus Width.
‹ Internal DDRAM Size: 230KB
‹ Embedded 10KB Character ROM with Font
Size 8x16 Dots and Supporting Character
Set of ISO8859-1/2/3/4.
‹ Embedded Block Transfer Engine (BTE) with
2D Function.
‹ Embedded Geometric Speed-up Engine.
‹ Font Enlargement X1, X2, X3, X4 for
Horizontal or Vertical Direction.
‹ Screen Display Rotation 90°, 180° and 270°
for Different Panel Type.
‹ Support Font Vertical Rotation.
‹ Support Block Scroll for Vertical or Horizontal
Direction.
‹ Text Cursor for Character Writing.
‹ 32X32 Pixel Graphic Cursor Function.
‹ Support 256 User-defined 8x16 Characters.
‹ Support 32 User-defined Patterns of 8x8
Pixels.
‹ 2 programmable PWM for Back-Light
Adjusting or Other's Application.
‹ Embedded 4-Wires Touch Panel Controller.
‹ 6 Sets of Programmable GPIO (GPIO0~5).
‹ Clock Source: External X’tal Clock Input with
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
3. Block Diagram
DB[0:7]
RD# / EN
WR# / RW#
CS#
RS
C86
WAIT#
INT#
CGROM
MPU I/F
Block
XI
Register
Block
OSC/
PLL
XO
Geometric
Speed-up
Engine
Internal
DPRAM
Font
Engine
Pattern/
Cursor
TCON
Power
Control
RST#
PWM
ADC
XP
XN
YP
YN
4-wires
Touch Panel
Controller
2D-BTE
Engine
Scroll
Engine
PDAT[0:15]
HSYNC
VSYNC
PCLK
DE
PWM1
PWM2
GPIO
GPIO[0:5]
Test
TEST[0:2]
Figure 3-1 : Internal Block Diagram
TFT Driver
8bits
8080/6800 MPU
Booster
(Back-light Adj.)
RA8872
TFT Panel
4-Wires
Touch Panel
Crystal
Figure 3-2 : System Block Diagram
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
4. Pin Definition
4-1
MCU Interface
Pin Name
I/O
DB[0:7]
IO
8mA
I
RD# / EN
Pin#
Pin Description
14, 15,
Data Bus
19~
These are data bus for data transfer between MCU and RA8872.
24
9
Enable/Read Enable
When MCU interface (I/F) is 8080 series, this pin is used as data
read (RD#), active low.
When MCU I/F is 6800 series, this pin is used as Enable (EN),
active high.
WR# / RW#
I
10
Write/Read-Write
When MCU I/F is 8080 series, this pin is used as data write (WR#),
active low.
When MCU I/F is 6800 series, this pin is used as data read/write
control (RW#). Active high for read and active low for write.
CS#
I
11
Chip Select Input
Low active chip select pin.
Command / Data Select Input
The pin is used to select command/data cycle. RS = 0, data
Read/Write cycle is selected. RS = 1, status read/command write
cycle is selected.
I
RS
12
In 8080 interface, usually it connects to “A0” address pin.
RS
0
0
1
1
WR#
0
1
0
1
Access Cycle
Data Write
Data Read
CMD Write
Status Read
C86
I
13
MCU Interface Select
0 : 8080 interface is selected.
1 : 6800 interface is selected.
INT#
O
8mA
37
Interrupt Signal Output
The interrupt output for MCU to indicate the status of RA8872.
36
Wait Signal Output
This is a WAIT output to indicate the RA8872 is in busy state. The
RA8872 can’t access MCU cycle when WAIT# pin is active. It is
active low and could be used for MCU to poll busy status by
connecting it to I/O port.
WAIT#
O
8mA
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RA8872
Version 1.4
4-2
Character / Graphic TFT LCD Controller
LCD Panel Interface
Pin Name
PDAT[0:15]
4-3
I/O
Pin#
Pin Description
LCD Panel Data Bus
O
85~100 Data bus output for TFT LCD panel driver IC. This data bus must
4mA
be connected to the corresponding bus of TFT-LCD panel.
HSYNC
O
4mA
81
HSYNC Pulse
When generic TFT is selected, the signal is used as HSYNC.
VSYNC
O
4mA
82
VSYNC Pulse
When generic TFT is selected, the signal is used as VSYNC.
PCLK
O
4mA
83
Pixel Clock
When generic TFT is selected, the signal is used as PCLK.
DE
O
4mA
84
Data Enable
When generic TFT is selected, the signal is used as DE.
Touch Panel and PWM Interface
Pin Name
I/O
Pin#
XP
A
8
XP Signal for Touch Panel
This pin connects to XP switch signal of 4-wires touch panel.
XN
A
5
XN Signal for Touch Panel
This pin connects to XN switch signal of 4-wires touch panel.
6
YP Signal for Touch Panel
Touch Panel control signal.
This pin connects to YP switch signal of 4-wires touch panel. It
must be connected a 100KΩ pull-up resistor when the Touch Panel
function is enable.
A
YP
Pin Description
YN
A
7
YN Signal for Touch Panel
Touch Panel control signal.
This pin connects to YN switch signal of 4-wires touch panel.
PWM1
PWM2
O
8mA
33,
34
PWM Output
PWM output pins. The duty could be programmed by register
setting.
GPIO[0:5]
General Purpose I/O
IO 64~66,
4mA 69~71 These signals are used as GPIO signals; user can program it by
register.
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RA8872
Version 1.4
4-4
Character / Graphic TFT LCD Controller
Clock and Power Interface
Pin Name
I/O
Pin#
Pin Description
XI
I
28
Crystal Input Pin
Input pin for internal crystal circuit. It should be connected to
external crystal to generate the source of PLL circuit. That will
generate the system clock for RA8872.
XO
O
29
Crystal Output Pin
Output pin for internal crystal circuit.
38
Reset Signal Input
This active-low input performs a hardware reset on the RA8872. It
is a Schmitt-trigger input for enhanced noise immunity; however,
care should be taken to ensure that it is not triggered if the supply
voltage is lowered.
RST#
I
TEST[0:2]
I
VR1
A
76
Reference Voltage Input
This is a reference voltage input. For normal operation, it only need
add a 0.1uF capacitor to ground.
VR2
A
74
Reference Voltage Output
This is a reference voltage output. For normal operation, it only
need add a 0.2uF capacitor to ground.
ADC_VREF
A
4
ADC Reference Voltage
This pin is the reference voltage input of ADC. The reference
voltage could be generated by RA8872 or from external circuit.
Test Mode Input
40~42 For chip test function, should be connected to GND for normal
operation.
27,
LDO VDD
3.3V power source for LDO. The internal LDO will generate the
1.8V power output.
LDO_VDD
P
LDO_GND
P
LDO_OUT
P
80
LDO Output
1.8V power generated by internal LDO. It must connect bypass
capacities to prevent power noise.
LDO_CAP
P
30
LDO Capacitor Input
It must connect 1uF bypass capacities to prevent power noise.
CORE_VDD
P
ADC_VDD
P
2
ADC VDD
ADC 3.3V power signals. Please connect this signal to 3.3V.
ADC_GND
P
3
ADC GND
ADC ground signal. Please connect this signal to ground.
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79,
25,
78
17,
57
LDO GND
Ground signal for internal LDO.
CORE VDD
Core VDD is 1.8V.The core power input that connect to LDO_OUT.
It must connect 1uF bypass capacities to prevent power noise.
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
Pin Name
I/O
Pin#
P
18,
32,
61,
77
IO VDD
3.3V IO power input.
P
1,
16,
31,
35,
50,
51,
59
GND
IO Cell/Core ground signals.
VDD
NC
VR2
NC
NC
GPIO5
GPIO4
GPIO3
NC
NC
GPIO2
GPIO1
GPIO0
NC
NC
VDD
NC
GND
NC
CORE_VDD
NC
NC
NC
NC
NC
GND
GND
Pin Description
VR1
VDD
LDO_GND
LDO_VDD
LDO_OUT
HSYNC
VSYNC
PCLK
DE
PDAT0
PDAT1
PDAT2
PDAT3
PDAT4
PDAT5
PDAT6
PDAT7
PDAT8
PDAT9
PDAT10
PDAT11
PDAT12
PDAT13
PDAT14
PDAT15
70
75
65
60
55
50
80
RAiO
85
TM
45
40
RA8872L3N
90
35
1012
95
30
Date code (Year 2010, 12th week)
100
5
10
15
20
25
GND
ADC_VDD
ADC_GND
ADC_VREF
XN
YP
YN
XP
RD#
WR#
CS#
RS
C86
DB0
DB1
GND
CORE_VDD
VDD
DB2
DB3
DB4
DB5
DB6
DB7
LDO_GND
○
GND
NC
NC
NC
NC
NC
NC
NC
TEST2
TEST1
TEST0
NC
RST#
INT#
WAIT#
GND
PWM2
PWM1
VDD
GND
LDO_CAP
XO
XI
LDO_VDD
NC
Figure 4-1 : Pin Assignment
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
5. Register Table
RA8872 includes a status register and tens of instruction registers. The status register can be read only.
If MCU executes the read cycle to RA8872 while /RS pin is setting high, then the data of status will be
read back to MCU. If MCU executes the write cycle to RA8872 while RS pin is setting high, it means that
MCU will write a command to RA8872. The other registers are classified to 11 categories as Table 5-1,
most of which are readable/writable. All of the registers will be illustrated in the following sections. And
Chapter 12 is the summary of these registers.
Table 5-1 : Command Registers
No.
5-1
Command Registers
Address
1
System and Configuration Registers
[01h], [02h], [04h],
[10h] ~ [1Fh]
2
LCD Display Control Registers
[20h] ~ [27h] , [29h],
3
Active Window Setting Registers
[30h] ~ [3Fh]
4
Cursor Setting Registers
[40h] ~ [4Eh]
5
BTE Control Registers
[50h] ~ [67h]
6
Touch Panel Control Registers
[70h] ~ [74h]
7
Graphic Cursor Setting Registers
[80h] ~ [85h]
8
PLL Setting Registers
[88h], [89h]
9
PWM Control Registers
[8Ah] ~ [8Fh]
10
Drawing Control Registers
[90h] ~ [9Dh]
Status Register
Status Register (STSR)
Bit
7
6
5
4
3-0
Description
Memory Read/Write Busy (Include Font Write Busy)
0 : No Memory Read/Write event.
1 : Memory Read/Write busy.
BTE Busy
0 : BTE is done or idle.
1 : BTE is busy.
Touch Panel Event Detected
0 : Touch Panel untouched.
1 : Touch Panel touched.
This bit is used when Touch Panel function and Manual mode
enable.
Sleep Mode Status
0: RA8872 in Normal mode.
1: RA8872 in Sleep mode.
NA
Default
Access
0
RO
0
RO
0
RO
0
RO
0
RO
Note: “RO” means read only.
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RA8872
Version 1.4
5-2
Character / Graphic TFT LCD Controller
System & Configuration Registers
REG[01h] Power and Display Control Register (PWRR)
Bit
7
6-2
1
0
Description
LCD Display Off
0 : Display off.
1 : Display on.
NA
Sleep Mode
0 : Normal mode.
1 : Sleep mode.
Note: There are 2 ways to wake up from sleep mode:
Touch Panel wake up and software wake up.
Software Reset
0 : No action.
1 : Software Reset.
Note: The bit must be set to 1 and then set to 0 to complete a
software reset. When read this bit, it is fix get 0.
Default
Access
0
RW
0
RO
0
RW
0
RW
Default
Access
--
RW
Default
Access
0
RW
0
RO
0
RW
Note: RW means readable and writable.
REG[02h] Memory Read/Write Command (MRWC)
Bit
7-0
Description
Write : Memory Write Data
Read : Memory Read Data
REG[04h] Pixel Clock Setting Register (PCLK)
Bit
7
6-2
1-0
Description
PCLK Inversion
0 : PDAT is fetched at PCLK rising edge.
1 : PDAT is fetched at PCLK falling edge.
NA
PCLK Pulse Width Setting(PPWS)
Pixel clock (PCLK) width setting.
PCLK= System Clock / ( (2^(Layer Setting Control + 1)) * (2^( PPWS) )
Note : When in Internal DDRAM 65k color mode, Layer Setting
Control is regarded as 1. About other pixel clock setting for
different display application, please refer to Table 6-6.
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
REG[10h] System Configuration Register (SYSR)
Bit
Description
Default
Access
7
Must keep low.
0
RW
6
Parallel or Serial Mode Selection (Only for Digital Panel)
0 : Parallel data output.
1 : Serial data out. (Translate the parallel data to serial.)
0
RW
5
Must keep low.
0
RW
4
Must keep low.
0
RW
0
RW
0
RW
Default
Access
0
RO
0
RW
0
RO
0
RW
3-2
1-0
Color Depth Setting
00 : 8-bpp generic TFT, ie. 256 colors.
01 : 12-bpp generic TFT, ie. 4K colors.
1x : 16-bpp generic TFT, ie. 65K colors.
The Bit5 of SYSR must be cleared to 0 when the display color
depth is less than 4096 color which means that RA8872 must use
internal SRAM only.
Must keep 00.
REG[11h] Panel Data Type Register (DRGB)
Bit
7
6-4
3
2-0
Description
NA
Odd Lines of Serial Panel Data Out Sequence
000 : RGB.
001 : RBG.
010 : GRB.
011 : GBR.
100 : BRG.
101 : BGR.
Others: reserved. (Note)
NA
Even Lines of Serial Panel Data Out Sequence
000 : RGB.
001 : RBG.
010 : GRB.
011 : GBR.
100 : BRG.
101 : BGR.
Others: reserved. (Note)
Note: Switch data sequence to meet delta and stripe type TFT LCD panel, when REG[10h] bit6 is 1.
First dot
PCLK
ODD LINE
R1
G1
B1
R2
EVEN LINE
B1
R1
G1
B2
Figure 5-1：Output Data for Serial Delta Panel
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
First dot
PCLK
ODD LINE
R1
G1
B1
R2
EVEN LINE
R1
G1
B1
R2
Figure 5-2：Output Data for Serial Stripe Panel
REG[12h] GPIO Configure Register (IOCR)
Bit
Description
Default
Access
7
6
Must keep low.
NA
OE[5:0]
When GPIO_EN = 0, OE [5:0] can be used for GPIO input/output
setting.
0 : Output.
1 : Input.
0
0
RW
RO
0
RW
Default
Access
0
RO
0
RW
5-0
REG[13h] GPIO Data Register (IODR)
Bit
7-6
5-0
Description
NA
IO_DAT[5:0]
When OEN = Input, IO_DATN is the input buffer of GPION.
When OEN = Output, IO_DATN the written buffer of GPION.
REG[14h] LCD Horizontal Display Width Register (HDWR)
Bit
Description
Default
Access
7
NA
Horizontal Display Width Setting Bit[6:0]
The register specifies the LCD panel horizontal display width, in
8 pixel resolution.
Horizontal display width(pixels) = (HDWR + 1)*8
0
RO
0
RW
6-0
REG[15h] Horizontal Non-Display Period Fine Tuning Option Register(HNDFTR)
Bit
7
6-4
3-0
Description
DE Polarity (For Generic TFT function)
0 : high active.
1 : low active.
NA
Horizontal Non-Display Period Fine Tuning[3:0]
This register specifies the fine tuning for horizontal non-display
period; it is used to support the SYNC mode panel. Each level of
this modulation is 1-pixel.
Default
Access
0
RW
0
RO
0
RW
Horizontal Non-Display Fine Tuning Period (pixels)= HNDFTR
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
REG[16h] LCD Horizontal Non-Display Period Register (HNDR)
Bit
Description
Default
Access
7-5
NA
Horizontal Non-Display Period Bit[4:0]
This register specifies the horizontal non-display period. Each
level of this modulation is 8-pixel.
0
RO
0
RW
4-0
Horizontal Non-Display Period (pixels)
= (HNDR + 1)*8 + HNDFTR
REG[17h] HSYNC Start Position Register (HSTR)
Bit
Description
Default
Access
7-5
NA
HSYNC Start Position[4:0]
The starting position from the end of display area to the
beginning of HSYNC. Each level of this modulation is 8-pixel.
0
RO
0
RW
Default
Access
0
RW
0
RO
0
RW
Default
Access
0
RW
Default
Access
0
RO
0
RW
Default
Access
0
RW
4-0
HSYNC Start Position(pixels) = (HSTR + 1)*8
REG[18h] HSYNC Pulse Width Register (HPWR)
Bit
7
6-5
4-0
Description
HSYNC Polarity
0 : Low active.
1 : High active.
NA
HSYNC Pulse Width [4:0]
The period width of HSYNC.
HSYNC Pulse width(pixels) = (HPWR + 1)*8
REG[19h] LCD Vertical Display Height Register (VDHR0)
Bit
Description
Vertical Display Height Bit[7:0]
7-0
Vertical Display Height(Line) = VDHR + 1
REG[1Ah] LCD Vertical Display Height Register0 (VDHR1)
Bit
7-1
Description
NA
Vertical Display Height Bit[8]
0
Vertical Display Height(Line) = VDHR + 1
REG[1Bh] LCD Vertical Non-Display Period Register (VNDR0)
Bit
Description
Vertical Non-Display Period Bit[7:0]
7-0
Vertical Non-Display Period(Line) = (VNDR + 1)
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
REG[1Ch] LCD Vertical Non-Display Period Register (VNDR1)
Bit
7-1
0
Description
NA
Vertical Non-Display Period Bit[8]
Vertical Non-Display Period(Line) = (VNDR + 1)
Default
Access
0
RO
0
RW
REG[1Dh] VSYNC Start Position Register (VSTR0)
Bit
Description
Default
Access
7-0
VSYNC Start Position[7:0]
The starting position from the end of display area to the beginning
of VSYNC.
0
RW
VSYNC Start Position(Line) = (VSTR + 1)
REG[1Eh] VSYNC Start Position Register (VSTR1)
Bit
Description
Default
Access
7-1
NA
VSYNC Start Position[8]
The starting from the end of display area to the beginning of
VSYNC.
0
RO
0
RW
Default
Access
0
RW
0
RW
0
VSYNC Start Position(Line) = (VSTR + 1)
REG[1Fh] VSYNC Pulse Width Register (VPWR)
Bit
7
6-0
Description
VSYNC Polarity
0 : Low active.
1 : High active.
VSYNC Pulse Width[6:0]
The pulse width of VSYNC.
VSYNC Pulse Width(Line) = (VPWR + 1)
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RA8872
Version 1.4
5-3
Character / Graphic TFT LCD Controller
LCD Display Control Registers
REG[20h] Display Configuration Register (DPCR)
Bit
7
6-4
3
2
1-0
Description
Layer Setting Control
0 : One layer configuration is selected.
1 : Two layers configuration is selected..
Note 1: The bit is only available when the size is below 320x240.
Note 2: This bit must be set to zero, when RA8872 is operated at
Internal SRAM and color depth is 16-bpp(65K colors).
NA
HDIR
Horizontal Scan direction, for n = SEG number.
0 : SEG0 to SEG(n-1).
1 : SEG(n-1) to SEG0.
VDIR
Vertical Scan direction, for n = COM number
0 : COM0 to COM(n-1)
1 : COM(n-1) to COM0
Scan Rotate Control Bit[1:0]
00b : Normal.
01b : Rotate 90 degree.
10b : Rotate 180 degree.
11b : Rotate 270 degree.
Default
Access
0
RW
0
RO
0
RW
0
RW
0
RW
REG[21h] Font Control Register 0 (FNCR0)
Bit
Description
Default
Access
7
CGRAM/CGROM Font Selection Bit.
0 : CGROM font is selected.
1 : CGRAM font is selected.
Note:
The bit is used to select the bit-map source when text-mode is
active(REG[40h] bit 7 is 1), when CGRAM is writing(REG[41h] bit
3-2 =01b), the bit must be set as “0”.
0
RW
6
Must keep low.
0
RW
5
Must keep low.
0
RW
4
Must keep high.
0
RW
Must keep 00.
ISO8859 Font Selection
00b : ISO8859-1.
01b : ISO8859-2.
10b : ISO8859-3.
11b : ISO8859-4.
0
RW
0
RW
3-2
1-0
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
REG[22h] Font Control Register1 (FNCR1)
Bit
7
6
5
4
3-2
1-0
Description
Full Alignment Selection Bit
0 : Full alignment is disable.
1 : Full alignment is enable.
Font Transparency
0 : Font with background color.
1 : Font with background transparency.
Font Bold
0 : Normal.
1 : Bold.
Font Rotation
0 : Normal.
1 : 90 Degree.
Horizontal Font Enlargement
00b : X1.
01b : X2.
10b : X3.
11b : X4.
Vertical Font Enlargement
00b : X1.
01b : X2.
10b : X3.
11b : X4.
Default
Access
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
Default
Access
0
RW
REG[23h] CGRAM Select Register (CGSR)
Bit
7-0
Description
CGRAM No.
REG[24h] Horizontal Scroll Offset Register 0 (HOFS0)
Bit
Description
Default
Access
7-0
Horizontal Display Scroll Offset [7:0]
The display offset of the horizontal direction, changing the value
will cause the effect of scrolling at horizontal direction.
0
RW
REG[25h] Horizontal Scroll Offset Register 1 (HOFS1)
Bit
Description
Default
Access
7-2
NA
Horizontal Display Scroll Offset [9:8]
The display offset of the horizontal direction, changing the value
will cause the effect of scrolling at horizontal direction.
0
RO
0
RW
1-0
REG[26h] Vertical Scroll Offset Register 0 (VOFS0)
Bit
Description
Default
Access
7-0
Vertical Display Scroll Offset [7:0]
The display offset of the vertical direction, changing the value will
cause the effect of scrolling at vertical direction.
0
RW
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
REG[27h] Vertical Scroll Offset Register 1 (VOFS1)
Bit
Description
Default
Access
7-1
NA
Vertical Display Scroll Offset [8]
The display offset of the vertical direction, changing the value will
cause the effect of scrolling at vertical direction.
0
RO
0
RW
0
REG[29h] Font Line Distance Setting Register(FLDR)
Bit
Description
Default
Access
7-5
NA
Font line Distance Setting
Setting the font line distance when setting memory write cursor
auto move. (Unit: pixel)
0
RO
0
RW
4-0
Active window
瑞佑科技
Font line distance
RA i O
Figure 5-3 : Character Line Distance
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RA8872
Version 1.4
5-4
Character / Graphic TFT LCD Controller
Active Window Setting Registers
REG[30h] Horizontal Start Point 0 of Active Window (HSAW0)
Bit
7-0
Description
Horizontal Start Point of Active Window [7:0]
Default
Access
0
RW
Default
Access
REG[31h] Horizontal Start Point 1 of Active Window (HSAW1)
Bit
Description
7-2
NA
0
RO
1-0
Horizontal Start Point of Active Window [9:8]
0
RW
Default
Access
0
RW
Default
Access
NA
0
RO
Vertical Start Point of Active Window [8]
0
RW
Default
Access
0
RW
Default
Access
REG[32h] Vertical Start Point 0 of Active Window (VSAW0)
Bit
7-0
Description
Vertical Start Point of Active Window [7:0]
REG[33h] Vertical Start Point 1 of Active Window (VSAW1)
Bit
7-1
0
Description
REG[34h] Horizontal End Point 0 of Active Window (HEAW0)
Bit
7-0
Description
Horizontal End Point of Active Window [7:0]
REG[35h] Horizontal End Point 1 of Active Window (HEAW1)
Bit
Description
7-2
NA
0
RO
1-0
Horizontal End Point of Active Window [9:8]
0
RW
Default
Access
0
RW
Default
Access
NA
0
RO
Vertical End Point of Active Window [8]
0
RW
REG[36h] Vertical End Point of Active Window 0 (VEAW0)
Bit
7-0
Description
Vertical End Point of Active Window [7:0]
REG[37h] Vertical End Point of Active Window 1 (VEAW1)
Bit
7-1
0
Description
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
(HSAW,VSAW)
Active Window
(HEAW,VEAW)
Figure 5-4 : Active Window
REG[38h] Horizontal Start Point 0 of Scroll Window (HSSW0)
Bit
7-0
Description
Horizontal Start Point of Scroll Window [7:0]
Default
Access
0
RW
Default
Access
REG[39h] Horizontal Start Point 1 of Scroll Window (HSSW1)
Bit
Description
7-2
NA
0
RO
1-0
Horizontal Start Point of Scroll Window [9:8]
0
RW
Default
Access
0
RW
Default
Access
NA
0
RO
Vertical Start Point of Scroll Window [8]
0
RW
Default
Access
0
RW
Default
Access
REG[3Ah] Vertical Start Point 0 of Scroll Window (VSSW0)
Bit
7-0
Description
Vertical Start Point of Scroll Window [7:0]
REG[3Bh] Vertical Start Point 1 of Scroll Window (VSSW1)
Bit
7-1
0
Description
REG[3Ch] Horizontal End Point 0 of Scroll Window (HESW0)
Bit
7-0
Description
Horizontal End Point of Scroll Window [7:0]
REG[3Dh] Horizontal End Point 1 of Scroll Window (HESW1)
Bit
Description
7-2
NA
0
RO
1-0
Horizontal End Point of Scroll Window [9:8]
0
RW
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
REG[3Eh] Vertical End Point 0 of Scroll Window (VESW0)
Bit
7-0
Description
Default
Access
0
RW
Default
Access
NA
0
RO
Vertical End Point of Scroll Window [8]
0
RW
Vertical End Point of Scroll Window [7:0]
REG[3Fh] Vertical End Point 1 of Scroll Window (VESW1)
Bit
7-1
0
Description
(HSSW,VSSW)
Scroll Window
(HESW,VESW)
Figure 5-5 : Scroll Window
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RA8872
Version 1.4
5-5
Character / Graphic TFT LCD Controller
Cursor Setting Registers
RA8872 provides two kinds of cursors for different applications. One is memory read/write index
cursor, the other is graphic cursor. Memory index cursor indicates the memory read/write position.
Memory read cursor and memory write index cursors are independent and only the write index cursor
is visible. Both of them can be set as auto increasing or not. The cursor moving directions are also
programmable and the moving range is dominated by the setting of active window. Graphic cursor are
used as a 32x32 pixels graphic pattern, RA8872 provides 8 sets of graphic cursors that can be
programmed by customers. User can set the display position by register.
REG[40h] Memory Write Control Register 0 (MWCR0)
Bit
7
6
5
4
3-2
1
0
Description
Text Mode Enable
0 : Graphic mode.
1 : Text mode.
Text Cursor Enable
0 : Text Cursor is not visible.
1 : Text Cursor is visible.
Text Cursor Blink Enable
0 : Normal display.
1 : Blink display.
NA
Memory Write Direction (Only for Graphic Mode)
00b : Left Æ Right then Top Æ Down.
01b : Right Æ Left then Top Æ Down.
10b : Top Æ Down then Left Æ Right.
11b : Down Æ Top then Left Æ Right.
Memory Write Cursor Auto-Increase Disable
0 : Cursor auto-increases when memory write.
1 : Cursor doesn’t auto-increases when memory write.
Memory Read Cursor Auto-Increase Disable
0 : Cursor auto-increases when memory read.
1 : Cursor doesn’t auto-increases when memory read.
Default
Access
0
RW
0
RW
0
RW
0
RO
0
RW
0
RW
0
RW
Default
Access
0
RW
0
RW
0
RW
0
RO
REG[41h] Memory Write Control Register1 (MWCR1)
Bit
7
6-4
3-2
1
Description
Graphic Cursor Enable
0 : Graphic Cursor disable.
1 : Graphic Cursor enable.
Graphic Cursor Selection bit
Select one from eight graphic cursor types. (000b to 111b)
000b : Graphic Cursor Set 1.
001b : Graphic Cursor Set 2.
010b : Graphic Cursor Set 3.
:
:
:
:
111b : Graphic Cursor Set 8.
Write Destination Selection
00b : Bank 1~2.
01b : CGRAM.
10b : Graphic Cursor.
11b : Pattern.
NA
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RA8872
Version 1.4
0
Character / Graphic TFT LCD Controller
Bank No. for Writing Selection
When resolution =< 320x240 :
0 : Bank 1.
1 : Bank 2.
When resolution > 320x240 :
NA, always writing to Bank 1.
0
RW
REG[42h] Text Foreground Color Register (TFCR)
Bit
Description
Default
Access
7-0
Text Foreground Color
Forward color of text with 256 color RGB format [7:0] =
RRRGGGBB.
FFh
RW
REG[43h] Text Background Color Register (TBCR)
Bit
Description
Default
Access
7-0
Text Background Color
Background color of text with 256 color RGB format [7:0] =
RRRGGGBB.
0
RW
Default
Access
0
RW
REG[44h] Blink Time Control Register (BTCR)
Bit
Description
7-0
Text Blink Time Setting(Unit: Frame)
00h : 1 frames time.
01h : 2 frames time.
02h : 3 frames time.
:
:
:
FFh : 256 frames time.
REG[45h] Text Cursor Size Register (CURS)
Bit
Description
Default
Access
7-4
Text Cursor Horizontal Size Setting[3:0]
Unit : Pixel
Text Cursor Vertical Size Setting[3:0]
Unit : Pixel
Note: When font is enlarged, the cursor setting will multiply the
same times as the font enlargement.
7h
RW
0
RW
Default
Access
0
RW
Default
Access
3-0
REG[46h] Memory Write Cursor Horizontal Position Register 0 (CURH0)
Bit
7-0
Description
Memory Write Cursor Horizontal Location[7:0]
REG[47h] Memory Write Cursor Horizontal Position Register 1 (CURH1)
Bit
Description
7-2
NA
0
RO
1-0
Memory Write Cursor Horizontal Location[9:8]
0
RW
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
REG[48h] Memory Write Cursor Vertical Position Register 0 (CURV0)
Bit
7-0
Description
Default
Access
0
RW
Default
Access
NA
0
RO
Memory Write Cursor Vertical Location[8]
0
RW
Default
Access
0
RW
Default
Access
Memory Write Cursor Vertical Location[7:0]
REG[49h] Memory Write Cursor Vertical Position Register 1 (CURV1)
Bit
7-1
0
Description
REG[4Ah] Memory Read Cursor Horizontal Position Register 0 (RCURH0)
Bit
7-0
Description
Memory Read Cursor Horizontal Location[7:0]
REG[4Bh] Memory Read Cursor Horizontal Position Register 1 (RCURH01)
Bit
Description
7-2
NA
0
RO
1-0
Memory Read Cursor Horizontal Location[9:8]
0
RW
Default
Access
0
RW
Default
Access
NA
0
RO
Memory Read Cursor Vertical Location[8]
0
RW
Default
Access
0
RO
0
RW
REG[4Ch] Memory Read Cursor Vertical Position Register 0 (RCURV0)
Bit
7-0
Description
Memory Read Cursor Vertical Location[7:0]
REG[4Dh] Memory Read Cursor Vertical Position Register 1 (RCURV1)
Bit
7-1
0
Description
REG[4Eh] Memory Read Cursor Direction (MRCD)
Bit
7-2
1-0
Description
NA
Memory Read Direction (Only for Graphic Mode)
00b : Left Æ Right then Top Æ Down.
01b : Right Æ Left then Top Æ Down.
10b : Top Æ Down then Left Æ Right.
11b : Down Æ Top then Left Æ Right.
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RA8872
Version 1.4
5-6
Character / Graphic TFT LCD Controller
Block Transfer Engine(BTE) Control Registers
REG[50h] BTE Function Control Register 0 (BECR0)
Bit
7
6
5
4-0
Description
BTE Function Enable / Status
Write:
0 : No action.
1 : BTE function enable.
Read:
0 : BTE function is idle.
1 : BTE function is busy.
BTE Source Data Select
0 : Block mode, the Source BTE is stored as a rectangular region
of memory.
1 : Linear mode, the Source BTE is stored as a contiguous block
of memory.
BTE Destination Data Select
0 : Block mode, the Destination BTE is stored as a rectangular
region of memory.
1 : Linear mode, the Destination BTE is stored as a contiguous
block of memory.
NA
Default
Access
0
RW
0
RW
0
RW
0
RO
Default
Access
0
RW
0
RW
Default
Access
0
RW
0
RO
0
RW
REG[51h] BTE Function Control Register1 (BECR1)
Bit
7-4
3-0
Description
BTE ROP Code Bit[3:0]
ROP is the acronym for Raster Operation. Some of BTE
operation code has to collocate with ROP for the detailed
function. (Please refer to the Section 7-7)
BTE Operation Code Bit[3:0]
RA8872 includes a 2D BTE Engine, it can execute 13 BTE
functions, the operation code range is from 1100 to 0000 and
1111 to 1101 are not used. Some of BTE Operation Code has to
collocate with the ROP code for the advance function. (Please
refer to the Section 7-7)
REG[52h] Layer Transparency Register0 (LTPR0)
Bit
7-6
5-3
2-0
Description
Layer1/2 Scroll Mode
00b : Layer 1/2 scroll at the same time.
01b : Only Layer 1 scroll.
1xb : Only Layer 2 scroll.
NA
Layer1/2 Display Mode
000b : Only Layer 1 is visible.
001b : Only Layer 2 is visible.
x10b : Lighten-overlay mode.
x11b : Transparent mode.
100b : Boolean OR.
101b : Boolean AND.
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
REG[53h] Layer Transparency Register1 (LTPR1)
Bit
7-4
3-0
Description
Layer Transparency Setting for Layer 2
0000b : Total display.
0001b : 7/8 display.
0010b : 3/4 display.
0011b : 5/8 display.
0100b : 1/2 display.
0101b : 3/8 display.
0110b : 1/4 display.
0111b : 1/8 display.
1000b : Display disable.
Layer Transparency Setting for Layer 1
0000b : Total display.
0001b : 7/8 display.
0010b : 3/4 display.
0011b : 5/8 display.
0100b : 1/2 display.
0101b : 3/8 display.
0110b : 1/4 display.
0111b : 1/8 display.
1000b : Display disable.
Default
Access
0
RW
0
RW
Default
Access
0
RW
Default
Access
REG[54h] Horizontal Source Point 0 of BTE (HSBE0)
Bit
Description
7-0
Horizontal Source Point of BTE [7:0]
REG[55h] Horizontal Source Point 1 of BTE (HSBE1)
Bit
Description
7-2
NA
0
RO
1-0
Horizontal Source Point of BTE [9:8]
0
RW
Default
Access
0
RW
Default
Access
0
RW
0
RO
0
RW
REG[56h] Vertical Source Point 0 of BTE (VSBE0)
Bit
7-0
Description
Vertical Source Point of BTE [7:0]
REG[57h] Vertical Source Point 1 of BTE (VSBE1)
Bit
7
6-1
0
Description
Source Layer Selection
0 : Layer 1.
1 : Layer 2.
NA
Vertical Source Point of BTE [8]
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
REG[58h] Horizontal Destination Point 0 of BTE (HDBE0)
Bit
7-0
Description
Horizontal Destination Point of BTE [7:0]
Default
Access
0
RW
Default
Access
REG[59h] Horizontal Destination Point 1 of BTE (HDBE1)
Bit
Description
7-2
NA
0
RO
1-0
Horizontal Destination Point of BTE [9:8]
0
RW
Default
Access
0
RW
Default
Access
0
RW
0
RO
0
RW
Default
Access
0
RW
REG[5Ah] Vertical Destination Point 0 of BTE (VDBE0)
Bit
7-0
Description
Vertical Destination Point of BTE [7:0]
REG[5Bh] Vertical Destination Point 1 of BTE (VDBE1)
Bit
7
6-1
0
Description
Destination Layer Selection
0 : Layer 1.
1 : Layer 2.
NA
Vertical Destination Point of BTE [8]
REG[5Ch] BTE Width Register 0 (BEWR0)
Bit
7-0
Description
BTE Width Setting[7:0]
REG[5Dh] BTE Width Register 1 (BEWR1)
Default
Access
7-2
Bit
NA
Description
0
RO
1-0
BTE Width Setting [9:8]
0
RW
Default
Access
0
RW
Default
Access
REG[5Eh] BTE Height Register 0 (BEHR0)
Bit
7-0
Description
BTE Height Setting[7:0]
REG[5Fh] BTE Height Register 1 (BEHR1)
Bit
Description
7-2
NA
0
RO
1-0
BTE Height Setting [9:8]
0
RW
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
REG[60h] BTE Background Color Register 0 (BGCR0)
Bit
Description
Default
Access
7-5
NA
BTE Background Color Red[4:0]
If REG[10h] Bit[3:2] is set to 256 colors, the register only uses
Bit[4:2].
If REG[10h] Bit[3:2] is set to 4K colors, the register only uses
Bit[4:1].
If REG[10h] Bit[3:2] is set to 65K colors, the register only uses
Bit[4:0].
0
R0
0
RW
4-0
REG[61h] BTE Background Color Register 1 (BGCR1)
Bit
Description
Default
Access
7-6
NA
BTE Background Color Green[5:0]
If REG[10h] Bit[3:2] is set to 256 colors, the register only uses
Bit[5:3].
If REG[10h] Bit[3:2] is set to 4K colors, the register only uses
Bit[5:2].
If REG[10h] Bit[3:2] is set to 65K colors, the register only uses
Bit[5:0].
0
R0
0
RW
5-0
REG[62h] BTE Background Color Register 2 (BGCR2)
Bit
Description
Default
Access
7-5
NA
BTE Background Color Blue[4:0]
If REG[10h] Bit[3:2] is set to 256 colors, the register only uses
Bit[4:3].
If REG[10h] Bit[3:2] is set to 4K colors, the register only uses
Bit[4:1].
If REG[10h] Bit[3:2] is set to 65K colors, the register only uses
Bit[4:0].
0
R0
0
RW
Default
Access
0
R0
0
RW
4-0
REG[63h] BTE Foreground Color Register 0 (FGCR0)
Bit
Description
7-5
NA
BTE Foreground Color Red[4:0]
If REG[10h] Bit[3:2] is set to 256 colors, the register only uses
Bit[4:2].
4-0
If REG[10h] Bit[3:2] is set to 4K colors, the register only uses
Bit[4:1].
If REG[10h] Bit[3:2] is set to 65K colors, the register only uses
Bit[4:0].
Note: For pattern fill transparency function, only Bit[4:2] is valid.
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
REG[64h] BTE Foreground Color Register 1 (FGCR1)
Bit
Description
7-6
NA
BTE Foreground Color Green[5:0]
If REG[10h] Bit[3:2] is set to 256 colors, the register only uses
Bit[5:3].
5-0
If REG[10h] Bit[3:2] is set to 4K colors, the register only uses
Bit[5:2].
If REG[10h] Bit[3:2] is set to 65K colors, the register only uses
Bit[5:0].
Note: For pattern fill transparency function, only Bit[5:3] is valid.
Default
Access
0
R0
0
RW
Default
Access
0
R0
0
RW
Default
Access
0
RO
0
RW
REG[65h] BTE Foreground Color Register 2 (FGCR2)
Bit
Description
7-5
NA
BTE Foreground Color Blue[4:0]
If REG[10h] Bit[3:2] is set to 256 colors, the register only uses
Bit[4:3].
4-0
If REG[10h] Bit[3:2] is set to 4K colors, the register only uses
Bit[4:1].
If REG[10h] Bit[3:2] is set to 65K colors, the register only uses
Bit[4:0].
Note: For pattern fill transparency function, only Bit[4:3] is valid.
REG[66h] Pattern Set No for BTE (PTNO)
Bit
7-5
4-0
Description
NA
Pattern Set No
00h Î Pattern Set #0.
01h Î Pattern Set #1.
02h Î Pattern Set #2.
:
:
:
1Fh Î Pattern Set #31.
REG[67h] Background Color Register for Transparent (BGTR)
Bit
Description
Default
Access
7-0
Background Color for Transparent Mode
Background color of transparent with 256 color RGB format [7:0]
= RRRGGGBB.
0
RW
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RA8872
Version 1.4
5-7
Character / Graphic TFT LCD Controller
Touch Panel Control Registers
REG[70h] Touch Panel Control Register 0 (TPCR0)
Bit
7
6-4
3
2-0
Description
Touch Panel Enable Bit
0 : Disable
1 : Enable
TP Sample Time Adjusting
000 : Wait 512 system clocks period for ADC data ready.
001 : Wait 1024 system clocks period for ADC data ready.
010 : Wait 2048 system clocks period for ADC data ready.
011 : Wait 4096 system clocks period for ADC data ready.
100 : Wait 8192 system clocks period for ADC data ready.
101 : Wait 16384 system clocks period for ADC data ready.
110 : Wait 32768 system clocks period for ADC data ready.
111 : Wait 65536 system clocks period for ADC data ready.
Touch Panel Wakeup Enable
0 : Disable the Touch Panel wake-up function.
1 : Touch Panel can wake-up the sleep mode.
ADC Clock Setting
000 : System CLK
001 : (System CLK) / 2.
010 : (System CLK) / 4.
011 : (System CLK) / 8.
100 : (System CLK) / 16.
101 : (System CLK) / 32.
110 : (System CLK) / 64.
111 : (System CLK) / 128.
Default
Access
0
RW
0
RW
0
RW
0
RW
REG[71h] Touch Panel Control Register 1 (TPCR1)
Bit
Description
Default
Access
7
Must keep high.
TP Manual Mode Enable
0 : Auto mode.
1 : Using the manual mode.
TP ADC Reference Voltage Source
0 : Vref generated from internal circuit. No external voltage is
needed.
1 : Vref from external source, 1/2 VDD is needed for ADC.
NA
De-bounce circuit enable for Touch Panel Interrupt.
0: De-bounce circuit disable.
1: De-bounce circuit enable.
Mode Selection for TP Manual Mode
00 : IDLE mode: Touch Panel in idle mode.
01 : Wait for TP event, Touch Panel event could cause the
interrupt or be read from REG[0Fh] Bit2.
10 : Latch X data, in the phase, X Data can be latched in
REG[72h] and REG[74h].
11 : Latch Y data, in the phase, Y Data can be latched in
REG[73h] and REG[74h].
0
RW
0
RW
0
RW
0
RW
0
R/W
0
RW
6
5
4-3
2
1-0
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
REG[72h] Touch Panel X High Byte Data Register (TPXH)
Bit
Default
Access
0
RW
Default
Access
0
RW
Description
Default
Access
Touch event detection bit, the bit is only available at
manual mode.
0
RO
6-4
NA
0
RO
3-2
Touch Panel Y Data Bit[1:0] (Common)
0
RW
1-0
Touch Panel X Data Bit[1:0] (Segment)
0
RW
7-0
Description
Touch Panel X Data Bit[9:2] (Segment)
REG[73h] Touch Panel Y High Byte Data Register (TPYH)
Bit
7-0
Description
Touch Panel Y Data Bit[9:2] (Common)
REG[74h] Touch Panel Segment/Common Low Byte Data Register (TPXYL)
Bit
ADET
7
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RA8872
Version 1.4
5-8
Character / Graphic TFT LCD Controller
Graphic Cursor Setting Registers
REG[80h] Graphic Cursor Horizontal Position Register 0 (GCHP0)
Bit
7-0
Description
Graphic Cursor Horizontal Location[7:0]
Default
Access
0
RW
Default
Access
REG[81h] Graphic Cursor Horizontal Position Register 1 (GCHP1)
Bit
Description
7-2
NA
0
RO
1-0
Graphic Cursor Horizontal Location[9:8]
0
RW
Default
Access
0
RW
Default
Access
NA
0
RO
Graphic Cursor Vertical Location[8]
0
RW
Default
Access
0
RW
Default
Access
0
RW
REG[82h] Graphic Cursor Vertical Position Register 0 (GCVP0)
Bit
7-0
Description
Graphic Cursor Vertical Location[7:0]
REG[83h] Graphic Cursor Vertical Position Register 1 (GCVP1)
Bit
7-1
0
Description
REG[84h] Graphic Cursor Color 0 (GCC0)
Bit
7-0
Description
Graphic Cursor Color 0 with 256 Color
RGB Format [7:0] = RRRGGGBB.
REG[85h] Graphic Cursor Color 1 (GCC1)
Bit
7-0
Description
Graphic Cursor Color 1 with 256 Color
RGB Format [7:0] = RRRGGGBB.
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RA8872
Version 1.4
5-9
Character / Graphic TFT LCD Controller
PLL Setting Registers
REG[88h] PLL control Register 1 (PLLC1)
Bit
7
Description
PLLDIVM
PLL Pre-driver
0 : divided by 1.
1 : divided by 2.
The system clock of RA8872 is generated by oscillator and
internal PLL circuit. The following formula is used for system
clock calculation:
Default
Access
0
RW
0
RO
03b
RW
SYS_CLK = FIN* ( PLLDIVN [4:0] +1 ) / ( ( PLLDIVM+1 ) *
( 2^PLLDIVK [2:0] ) )
6-5
4-0
NA
PLLDIVN[4:0]
PLL input parameter, the value should be 1~63. (i.e. value 0 is
forbidden).
Note:
1. Default PLL output is as same as OSC clock (FIN) frequency.
2. After REG[88h] or REG[89h] is programmed, a lock time (< 30us) must be kept to guarantee
the stability of the PLL output. After the lock time period, a software reset must be asserted
and user must re-program the RA8872 to complete the procedure.
3. FIN* ( PLLDIVN [4:0] +1 ) must be greater than or equal 120MHz. The following table is the
reference setting of OSC clock (FIN) and REG[88h] Bit[4:0]::
PLLDIVN[4:0]
REG[88h] Bit[4:0]
OSC Clock（FIN）
X’tal（MHz）
15
16
20
25
30
>= 7
>= 7
>= 5
>= 4
>= 3
REG[89h] PLL Control Register 2 (PLLC2)
Bit
7-3
2-0
Description
NA
PLLDIVK[2:0]
PLL Output divider
000 : divided by 1.
001 : divided by 2.
010 : divided by 4.
011 : divided by 8.
100 : divided by 16.
101 : divided by 32.
110 : divided by 64.
111 : divided by 128.
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Default
Access
0
RO
02h
RW
www.raio.com.tw
RA8872
Version 1.4
Character / Graphic TFT LCD Controller
5-10 PWM Control Registers
REG[8Ah] PWM1 Control Register (P1CR)
Bit
7
6
5
4
Description
PWM1 Enable
0 : Disable, PWM1_OUT level depends on the Bit6.
1 : Enable.
PWM1 Disable Level
0 : PWM1_OUT is Normal L when PWM disable or Sleep mode.
1 : PWM1_OUT is Normal H when PWM disable or Sleep mode.
The bit is only usable when REG[8Ah] bit 4 is 0.
Reserved
PWM1 Function Selection
0 : PWM1 function.
1 : PWM1 output a fixed frequency signal and it is equal to 1 /16
oscillator clock.
PWM1 = Fin / 16
Default
Access
0
RW
0
RW
0
RO
0
RW
0
RW
Default
Access
0
RW
PWM1 Clock Source Divide Ratio
3-0
0000b : SYS_CLK / 1
1000b : SYS_CLK / 256
0001b : SYS_CLK / 2
1001b : SYS_CLK / 512
0010b : SYS_CLK / 4
1010b : SYS_CLK / 1024
0011b : SYS_CLK / 8
1011b : SYS_CLK / 2048
0100b : SYS_CLK / 16
1100b : SYS_CLK / 4096
0101b : SYS_CLK / 32
1101b : SYS_CLK / 8192
0110b : SYS_CLK / 64
1110b : SYS_CLK / 16384
0111b : SYS_CLK / 128
1111b : SYS_CLK / 32768
For example, if the system clock is 20MHz and Bit[3:0] =0001b,
then the clock source of PWM1 is 10MHz.
REG[8Bh] PWM1 Duty Cycle Register (P1DCR)
Bit
7-0
Description
PWM Cycle Duty Selection Bit
00h Æ 1 / 256 High period.
01h Æ 2 / 256 High period.
02h Æ 3 / 256 High period.
:
:
:
FEh Æ 255 / 256 High period.
FFh Æ 256 / 256 High period.
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
REG[8Ch] PWM2 Control Register (P2CR)
Bit
7
6
5
Description
PWM2 Enable
0 : Disable, PWM_OUT level depends on the Bit6.
1 : Enable.
PWM2 Disable Level
0 : PWM2_OUT is Normal L when PWM disable or Sleep mode.
1 : PWM2_OUT is Normal H when PWM disable or Sleep mode.
The bit is only usable when REG[8Ch] bit 4 is 0.
Reserved
Default
Access
0
RW
0
RW
0
RO
0
RW
0
RW
Default
Access
0
RW
PWM2 Function Selection
4
0 : PWM2 function.
1 : PWM2 output a signal which is the same with system clock.
PWM2 = SYS_CLK / 16
PWM2 Clock Source Divide Ratio
3-0
0000b : SYS_CLK / 1
1000b : SYS_CLK / 256
0001b : SYS_CLK / 2
1001b : SYS_CLK / 512
0010b : SYS_CLK / 4
1010b : SYS_CLK / 1024
0011b : SYS_CLK / 8
1011b : SYS_CLK / 2048
0100b : SYS_CLK / 16
1100b : SYS_CLK / 4096
0101b : SYS_CLK / 32
1101b : SYS_CLK / 8192
0110b : SYS_CLK / 64
1110b : SYS_CLK / 16384
0111b : SYS_CLK / 128
1111b : SYS_CLK / 32768
For example, if the system clock is 20MHz and Bit[3:0]
=0010b,then the clock source of PWM2 is 5MHz.
REG[8Dh] PWM2 Control Register (P2DCR)
Bit
7-0
Description
PWM Cycle Duty Selection Bit
00h Æ 1 / 256 High period.
01h Æ 2 / 256 High period.
02h Æ 3 / 256 High period.
:
:
:
FEh Æ 255 / 256 High period
FFh Æ 256 / 256 High period
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
PWM Output
PWM CLK
System CLK
2*PWM CLK
256*PWM CLK
Ex : PWM source CLK = System CLK/4 and 2/256 High Period
Figure 5-6 : Duty of PWM
REG[8Eh] Memory Clear Control Register (MCLR)
Bit
7
6
5-1
0
Description
Memory Clear Function
0 : End or Stop. When write 0 to this bit RA8872 will stop the
Memory clear function. Or if read back this bit is 0, it
indicates that Memory clear function is complete.
1 : Start the memory clear function.
Memory Clear Area Setting
0 : Clear the full window. (Please refer to the setting of
REG[14h], [19h], [1Ah])
1 : Clear the active window(Please refer to the setting of
REG[30h~37h]). The layer to be cleared is according to the
setting REG[41h] Bit0.
NA
Memory Clear Color Setting
0 : Memory clear with BTE background color.
Note: BTE background color mode is fixed to 16bpp, i.e., 65K
color, not determined by REG[10h] Bit[3:2].
1 : Memory clear with Font background color.
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Default
Access
0
RW
0
RW
0
RO
0
RW
www.raio.com.tw
RA8872
Version 1.4
Character / Graphic TFT LCD Controller
REG[8Fh] Interrupt Control Register (INTC)
Bit
Description
Default
Access
7
NA
Touch Panel Interrupt Enable Bit
0 : Disable Touch interrupt.
1 : Enable Touch interrupt.
BTE Process Complete Interrupt Enable Bit
0 : Disable BTE process complete interrupt.
1 : Enable BTE process complete interrupt.
When the BTE function is enabled, this bit is used to enable
the MCU R/W interrupt of BTE:
0 : Disable BTE MCU R/W interrupt.
1 : Enable BTE MCU R/W interrupt.
When the BTE function is disabled, this bit is used to enable
the interrupt of font write function:
0 : Disable font write interrupt.
1 : Enable font write interrupt.
NA
Write FunctionÎ Touch Panel Interrupt Clear Bit
0 : No operation.
1 : Clear the touch interrupt.
Read Function Î Touch Panel Interrupt Status
0 : No Touch Panel interrupt happens.
1 : Touch Panel interrupt happens.
Write FunctionÎ BTE Process Complete Interrupt Clear Bit
0 : No operation.
1 : Clear BTE process complete interrupt.
Read FunctionÎBTE interrupt status
0: No BTE process complete interrupt happens.
1: BTE process complete interrupt happens.
0
RO
0
RW
0
RW
0
RW
0
RO
0
RW
0
RW
0
RW
6
5
4
3
2
1
0
When BTE function is enabled ( REG[50h] Bit7 = 1 ) :
Write FunctionÎ BTE MCU R/W Interrupt Enable Bit
0 : No operation.
1 : Clear BTE MCU R/W interrupt.
Read Function Î BTE R/W Interrupt Status
0: No BTE MCU R/W interrupt happens.
1: BTE MCU R/W interrupt happens.
Write FunctionÎ Font Write Interrupt Enable Bit
0 : No operation.
1 : Clear font write interrupt.
Read Function Î Font Write Interrupt Status
0: No font write interrupt happens.
1: Font write interrupt happens.
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
5-11 Drawing Control Registers
REG[90h] Draw Line/Circle/Square Control Register (DCR)
Bit
7
6
5
4
3 -0
Description
Draw Line/Square Start Signal
Write Function
0 : Stop the drawing function.
1 : Start the drawing function.
Read Function
0 : Drawing function complete.
1 : Drawing function is processing.
Draw Circle Start Signal
Write Function
0 : Stop the circle drawing function.
1 : Start the circle drawing function.
Read Function
0 : Circle drawing function complete.
1 : Circle drawing function is processing.
Fill the Circle/Square Signal
0 : Non fill.
1 : fill.
Draw Line or Square Select Signal
0 : Draw line.
1 : Draw square.
NA
(DLHSR, DLVSR)
(DLHSR, DLVSR)
(DLHER, DLVER)
Draw Line
Radius
(DCHR, DCVR)
Draw Circle
Default
Access
0
RW
0
RW
0
RW
0
RW
0
RO
(DLHSR, DLVSR)
(DLHER, DLVER)
Draw Square
(DLHER, DLVER)
Draw Square Fill
Radius
(DCHR, DCVR)
Draw Circle Fill
Figure 5-7 : Drawing Function Parameter
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
REG[91h] Draw Line/Square Horizontal Start Address Register0 (DLHSR0)
Bit
7-0
Description
Draw Line/Square Horizontal Start Address[7:0]
Default
Access
0
RW
Default
Access
REG[92h] Draw Line/Square Horizontal Start Address Register1 (DLHSR1)
Bit
Description
7-2
NA
0
RO
1-0
Draw Line/Square Horizontal Start Address[9:8]
0
RW
Default
Access
0
RW
Default
Access
NA
0
RO
Draw Line/Square Vertical Start Address[8]
0
RW
Default
Access
0
RW
REG[93h] Draw Line/Square Vertical Start Address Register0 (DLVSR0)
Bit
7-0
Description
Draw Line/Square Vertical Start Address[7:0]
REG[94h] Draw Line/Square Vertical Start Address Register1 (DLVSR1)
Bit
7-1
0
Description
REG[95h] Draw Line/Square Horizontal End Address Register0 (DLHER0)
Bit
7-0
Description
Draw Line/Square Horizontal End Address[7:0]
REG[96h] Draw Line/Square Horizontal End Address Register1 (DLHER1)
Default
Access
7-2
Bit
NA
Description
0
RO
1-0
Draw Line/Square Horizontal End Address[9:8]
0
RW
Default
Access
0
RW
Default
Access
NA
0
RO
Draw Line/Square Vertical End Address[8]
0
RW
Default
Access
0
RW
REG[97h] Draw Line/Square Vertical End Address Register0 (DLVER0)
Bit
7-0
Description
Draw Line/Square Vertical End Address[7:0]
REG[98h] Draw Line/Square Vertical End Address Register1 (DLVER1)
Bit
7-1
0
Description
REG[99h] Draw Circle Center Horizontal Address Register0 (DCHR0)
Bit
7-0
Description
Draw Circle Center Horizontal Address[7:0]
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
REG[9Ah] Draw Circle Center Horizontal Address Register1 (DCHR1)
Bit
Description
Default
Access
7-2
NA
0
RO
1-0
Draw Circle Center Horizontal Address[9:8]
0
RW
Default
Access
0
RW
Default
Access
NA
0
RO
Draw Circle Center Vertical Address[8]
0
RW
Default
Access
0
RW
REG[9Bh] Draw Circle Center Vertical Address Register0 (DCVR0)
Bit
7-0
Description
Draw Circle Center Vertical Address[7:0]
REG[9Ch] Draw Circle Center Vertical Address Register1 (DCVR1)
Bit
7-1
0
Description
REG[9Dh] Draw Circle Radius Register (DCRR)
Bit
7-0
Description
Draw Circle Radius[7:0]
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
6. Hardware Interface
6-1
MCU Interface
The RA8872 supports 8080 and 6800 series MPU interface, the interface is decided by C86 pin. If we
clear the C86 pin to logic low, and then the MCU interface of RA8872 is defined as 8080 series. If the
C86 is connected to logic high, then the MCU interface of RA8872 is used as 6800 series. Please
refer to the Figure 6-1 and Figure 6-2.
8080 MCU
RA8872
A0
A1-A7/A1-A15
IORQ
RS
Decoder
CS#
C86
DB[0-7]
DB[0-7]
RD
RD#
WR
RES
WR#
RST#
WAIT
WAIT#
GND
INT#
INT
Figure 6-1 : 8080 MCU Interface
6800 MCU
RA8872
A0
A1-A7/A1-A15
VMA
RS
Decoder
VDD
CS#
C86
DB[0-7]
DB[0-7]
EN
EN
R/W
RES
RW#
RST#
WAIT
WAIT#
INT#
INT
Figure 6-2 : 6800 MCU Interface
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
6-1-1
Protocol
The following timing charts are used to decribe the timing specification of the standard 8080 and
6800 interfaces.
6800 – 8-bit Interface
E
tCYC6
tAW6
tEW
R/W
tAH6
A0, CS
tDH6
tDS6
DB[7:0]
(Write)
tACC6
tOH6
DB[7:0]
(Read)
Figure 6-3 : 6800 MCU Waveform
Table 6-1 : 6800 MCU I/F Timing
Symbol
Rating
Parameter
Unit
Min.
Max.
tCYC6
Cycle time
50
--
ns
tEW
Strobe Pulse width
20
--
ns
tAW6
Address setup time
0
--
ns
tAH6
Address hold time
10
--
ns
tDS6
Data setup time
20
--
ns
tDH6
Data hold time
10
--
ns
tACC6
Data output access time
0
20
ns
tOH6
Data output hold time
0
20
ns
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
8080 – 8-bit Interface
A0, CS
tAW8
tAH8
tCYC8
WR, RD
tCC
tDH8
tDS8
DB[7:0]
(Write)
tACC8
tOH8
DB[7:0]
(Read)
Figure 6-4 : 8080 Waveform
Table 6-2 : 8080 MCU I/F Timing
Symbol
Rating
Parameter
Unit
Min.
Max.
tCYC8
Cycle time
50
--
ns
tCC8
Strobe Pulse width
20
--
ns
tAS8
Address setup time
0
--
ns
tAH8
Address hold time
10
--
ns
tDS8
Data setup time
20
--
ns
tDH8
Data hold time
10
--
ns
tACC8
Data output access time
0
20
ns
tOH8
Data output hold time
0
20
ns
In order to reduce the transmission interference between MPU interface and RA8872, we
suggest that a small capacitor to the GND should be added at the signal of CS#, RD#, WR#. If
use cable to connect MCU and RA8872, please keep the cable lengh less than 20cm. Otherwise
the we recommend add 1~10Kohm pull-up resistors on pins CS#, RD#, WR# and RS.
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
6-1-2 Read Status Register
The following Table 6-3 shows that RA8872 can be accessed under 4 different cycles, i.e. “Data
Write”, “Data Read”, “Command Write” and “Status read”. As we have introduced in the Chapter 5,
the status register is a read only register. If MCU executes the read cycle to RA8872 while /RS
pin is setting high, then data of status register will be read back to MCU. Please refer to the
Figure 6-5.
Table 6-3 : Access cycle of RA8872
RS
WR#
Access Cycle
0
0
Data Write
0
1
Data Read
1
0
CMD Write
1
1
Status Read
RS
CS#
WR#
RD#
DB[7:0]
Status DATA
Status Register Read
Figure 6-5 : Read Status Register
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
6-1-3 Write Command to Register
RA8872 contains dozens of registers. If users want to write a command into the register of
RA8872, they must execute the command write cycle first, i.e. the address of register, and then
execute the data write cycle for storing a new data into the target register. So “Write Command”
means that it will write a new data into the register. Please refer to the Figure 6-6 (1) for the
related access timing.
RS
CS #
WR#
RD#
DB [7:0]
REG#
DATA
(1) Command Write (Write Data to Regi ster)
RS
CS #
WR#
RD#
DB [7:0]
REG#
DATA
(2) Read Data from Register
Figure 6-6 : Register Write/Register Read
If we want to read the register contents of RA8872, it has to execute the command write cycle
first, and then the second access cycle must use “Data Read cycle”. Please refer to the Figure
6-6 (2). But please note that the Figure 6-6 is based on 8080 interface.
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
6-1-4 Display RAM Read / Write
When we want to write data into the memory (Note), it must execute the command write cycle to
the register “02H”. If we want to read data from the memory, it is also needed to execute the
command write cycle to the register “02H” before starting the read command. Please refer to the
Figure 6-7.
Note : The memory might be display memory or Character Generation RAM (CGRAM).
Figure 6-7 : Memory Write/Memory Read
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
6-1-5
Interrupt and Wait
RA8872 provides an interrupt pin “INT#” for triggering the external interrupt pin of MCU, it also
supports an output signal pin “WAIT#” which can indicate RA8872 is busy or not. Both of the two
signals are active at logic low. Please refer to the Figure 6-1 and Figure 6-2.
6-1-5-1
Interrupt
There are four ways in which the interrupt may occur :
‹
‹
‹
‹
Touch event occurs. Bit 2 of RE G[8Fh] is set to 1.
The moving/filling BTE function is completed. Bit 1 of REG [8Fh] is set to 1.
The data access of BTE is completed. Bit 1 of REG [8Fh] is set to 1.
The font access is completed. Bit 0 of REG [8Fh] is set to 1.
All of the above interrupts can be enable/disable by setting INTC ( REG[8Fh] ) . In addition, if
the system of end user can not provide the hardware interrupt, RA8872 also supports a
polling method; they can detect the interrupt status through the related status flag. When we
want to use the hardware interrupt of RA8872, then the related interrupt mask must be
enabled first. There is an example for describing the interrupt procedure of Touch Panel as
below :
‹
‹
‹
RA8872 send an interrupt signal to MCU.
When MCU receives interrupt signal , the program counter (PC) will jump to ISR
start address
In the mean time, the corresponding interrupt status flag of RA8872 will be set to
“1” (REG[8Fh]). For example, when Touch event generate an interrupt, the Touch
Panel Interrupt Status bit will be set to “1”.
By software interrupt, user can read INTC register for detecting interrupt event without any
external device. Besides, Interrupt mask function is only applied to hardware interrupt, not to
INTC status flag. User should be noting that, INTC status flag must be cleared manually at
the tail of the ISR, i.e., writing the Bit2 of Register INTC(REG[8Fh]) with 1, because the INTC
status flag will not be cleared automatically.
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
6-1-5-2
Wait
RA8872 also provides a wait signal, when the busy flag is cleared to “0”, it means that
RA8872 is busy and can not be accessed the DDRAM. There are three ways in which busy
may occur :
1． When RA8872 is set as text mode for writing FONT, RA8872 need different
processing time for differnert FONT sizes to write to DDRAM, RA8872 can’t
receive MCU cycle any more during the time of font writing, because it is in the
status of memory writing busy.
2． When RA8872 executing the memory clear function, it also generates the memory
write cycle to clear the DDRAM and cause RA8872 is in the status of memory
write busy.
3． When RA8872 processing BTE move function, RA8872 will automatically
executing the memory read/write cycle, at the time, any DDRAM read/write access
by MCU will cause a BTE fail.
4． When MCU sending a command, RA8872 need one system clock to latch the
command, if the clock frequency of MCU is much faster than the one of RA8872, it
is possible that RA8872 meets two or more commands in one system clock. In the
situation, we suggest that MCU should check the RA8872 busy status .In the most
other conditions, it doesn’t need to be checked.
If MCU writes data to DDRAM when memory writing busy, it will cause the lost of the writing
data. So user must check the RA8872 busy status in upper 4 situations.
In normally, user can connect “WAIT#” signal to MCU input. It is used for MCU to monitor the
busy status before writing data to RA8872.
RS, CS#
t WST
WR#
DB[7:0]
(Write)
t WAIT
WAIT#
Figure 6-8 : WAIT# Timing Chart
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
6-1-6
Data Format
RA8872 supports the 8-bit/12-bit/16-bit color depth TFT-LCD Panel, i.e. 256, 4K and 65K colors
TFT-LCD panel. As the number of bits increases, the number of possible colors becomes
impractically large for a color map. So in higher color depths, the color value typically directly
encodes relative brightness’s of red, green, and blue to specify a color in the RGB color model.
The related illustrations are following below.The following illustration is used for 8-bit MCU.
65K Colors
7
0
MPU Data Bus R4 R3 R2 R1 R0 G5 G4 G3
7
1st cycle
0
MPU Data Bus G2 G1 G0 B4 B3 B2 B1 B0
2nd cycle
4K Colors
7
MPU Data Bus
0
R3 R2 R1 R0
7
1st cycle
0
MPU Data Bus G3 G2 G1 G0 B3 B2 B1 B0
2nd cycle
256 Colors
7
0
MPU Data Bus R2 R1 R0 G2 G1 G0 B1 B0
Figure 6-9 : Color illustrations for MCU
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RA8872
Version 1.4
6-2
Character / Graphic TFT LCD Controller
Color Setting Mode
There are 16 bits data bus of the logic TFT driver interface of RA8872, supporting up to 65K colors
data format. By the setting of the register, RA8872 can provides 256 colors or 4K colors data format in
16 bit TFT interface to achieve the same display effect. About the register setting of color mode,
please refer to REG[10h](SYSR) Bit 3-2, the definition of data format is described below.
256 Color mode
Color format
7
0
R2 R1 R0G2G1G0 B1 B0
15
11 10
PDAT[15:0]
5 4
0
R2 R1 R0 R2 R1 G2G1G0G2G1G0 B1 B0 B1 B0 B1
4K Color mode
11
Color format
PDAT[15:0]
0
R3 R2 R1 R0 G3G2G1G0 B3 B2 B1 B0
Color format
15
11 10
5 4
15
R4 R3 R2 R1 R0 G5G4G3G2G1G0 B4 B3 B2 B1 B0
5 4
0
R3 R2 R1 R0 R3 G3G2G1G0G3G2 B3 B2 B1 B0 B3
65K Color mode
0
11 10
15
PDAT[15:0]
11 10
5 4
0
R4 R3 R2 R1 R0 G5G4G3G2G1G0 B4 B3 B2 B1 B0
Figure 6-10 : Color Mode Setting
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RA8872
Version 1.4
6-3
Character / Graphic TFT LCD Controller
LCD Interface
RA8872 supports digital TFT interface, which support the 8-bit/12-bit colors format with as the panel
resolution of 320x240 with 2 layers. Or 16-bit colors format for 320x240 one layer.
The Table 6-4 is the interface description for the digital TFT-LCD application of RA8872. The related
timing as Figure 6-11 and the application circuit please refer to the Figure 6-12. The PWM output of
RA8872 could used to control the LED back-light of TFT Panel. Please refer to Section 6-6 and
application circuit of Chapter 10 for the detail description.
Table 6-4 : Digital TFT Interface Description
Pin Name
Type
Pin#
HSYNC
VSYNC
PCLK
DE
PDAT[15]
PDAT[14]
PDAT[13]
PDAT[12]
PDAT[11]
PDAT[10]
PDAT[9]
PDAT[8]
PDAT[7]
PDAT[6]
PDAT[5]
PDAT[4]
PDAT[3]
PDAT[2]
PDAT[1]
PDAT[0]
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
74
75
76
77
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
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R2
R1
R0
G2
G1
G0
B1
B0
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Digital TFT Panel
16-bit
18-bit
HSYNC Pulse
VSYNC Pulse
Pixel Clock
Data Enable
R4
R5, R0
R3
R4
R2
R3
R1
R2
R0
R1
G5
G5
G4
G4
G3
G3
G2
G2
G1
G1
G0
G0
B4
B5, B0
B3
B4
B2
B3
B1
B2
B0
B1
24-bits
R7, R2
R6, R1
R5, R0
R4
R3
G7, G1
G6, G0
G5
G4
G3
G2
B7, B2
B6, B1
B5, B0
B4
B3
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
VPW
VND
VST
VDH
VSYNC
HSYNC
FPDATA
LINE
N
LINE
1
LINE
N
DE
HSYNC
HPW
HDW
HND
HST
PCLK
DE
FPDATA
Valid Data
Figure 6-11 : Digital TFT Panel Timing
8080 MCU
Digital TFT
Display
RA8872
RS
A0
A1-A7/A1-A15
Decoder
IORQ
CS#
DB[7:0]
DATA[7:0]
RD
RD#
WR
RES
WR#
RST#
WAIT
WAIT#
INT
GND
INT#
C86
VSYNC
VSYNC
HSYNC
HSYNC
DE
PCLK
PDAT[15:0]
DE
CLK
D[15:0]
GPIO0
DISP_OFF
GPIO1
GPIO2
PWM
LCD_RST
PWR_Ctrl
Back light_Ctrl
Figure 6-12 : The Interface of RA8872 and Digital TFT
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
RA8872 contains 230Kbytes internal display memory and the maximum resolution is 640x240 pixels
with 4K color depth. Please refer to the Table 6-5.
Table 6-5 : DDRAM Demand and Display Resolution
DDRAM
Demand
Internal
Internal
Internal
Internal
Internal
RAiO TECHNOLOGY INC.
Display
Resolution
320x240
320x240
320x240
320x480
640x240
Layer No.
Color Depth
1
1
2
1
1
8/12
16
8/12
8/12
8/12
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RA8872
Version 1.4
6-4
Character / Graphic TFT LCD Controller
Touch Panel I/F
RA8872 built in a 10-bits ADC and control circuits to connect with 4-wires resistance type Touch
Panel. The 4-wire resistive Touch Panel is composed of two layer extremely thin resistive panel, such
as Figure 6-13, there is a small gap between these two-layer panels. When external force press a
certain point, the two-layer resistive panels will be touched, which is short, Because the end points of
two-layer have electrodes (XP, XN, YP, YN), such as Figure 6-14, a comparative location will be
detected with some switches in coordination.
YU (YT)
XR
XL
YD (YB)
Figure 6-13: 4-wire Touch Panel Structure
VDD
YP
VDD
XP
XN
YN
Figure 6-14: Control Switch of 4-wire Touch Panel
Using RA8872 4-wires Touch Panel function only need to connect the Touch Panel signals – XP, XN,
YP and YN to RA8872. It will continuously monitor the panel and wait for touch event. When the event
is occurred, a divided voltage on panel caused by touch is sensed and transferred by ADC to
determine the location. After the value of X-axis and Y-axis are transferred and stored in
corresponding registers respectively, the Touch Panel controller will issue an interrupt to inform MCU
to process it.
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
The Figure 6-15 shows application circuit for 4-wires Touch Panel. Please add a 10K~39KΩ pull-up
resistor on the YP pin when using Touch Panel function.
The pin ADC_VREF is the reference voltage input of ADC. The Bit5 of Register [71h] is used to select
the reference voltage is from external or generated by RA8872. When use external reference voltage,
it need only add two resistors to generated 1/2 VDD (±5%) for ADC_VREF. And have to add a
capacitor (1~10uF) to GND to increase the stability of ADC.
RA8872
VDD
100kΩ
VDD
XR
LL
10kΩ
1%
ADC_VREF
10kΩ
1%
Touch Panel
LR
XL
UL
YD (YB)
UR
YU (YT)
1uF
0.001uFx4
Figure 6-15 : 4-wire Touch Panel Application Circuit
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RA8872
Version 1.4
6-5
Character / Graphic TFT LCD Controller
PWM
RA8872 provides 2 channels programmable PWM (Pulse Width Modulation) for backlight adjustment
or the other application. The PWM frequency and duty can be set by register. Besides, the driving
capability of PWM pin is larger than other output pin about 4 multiples.
Figure 6-16 shows the reference circuit of PWM contrast backlight application. This designed so that
PWM duty cycle 0%~100% varies LED current from 20mA~0mA.
Figure 6-16 : PWM Reference Circuit for LCD Backlight Brightness Adjustment
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
6-6 Clock and PLL
The system clock of RA8872 is generated by an external crystal connected between pins XI and XO
(15MHz~30MHz). From this clock source an internal circuit “PLL” generates a clock source which is
required by the system of RA8872, the system clock of RA8872 can be divided into different
frequency by PLL circuit or register adjustment (REG[88h] and [89h]). The related description is
shown below.
RA8872
~
10MHz
30MHz
XI
30pF
Oscillator
F IN
30pF
PLL
S ystem
Clock
XO
1MΩ
Figure 6-17 : Diagram for RA8872 System Clock
Formula for system of RA8872 calculation:
System Clock = Y1* ( PLLDIVN [4:0] +1 ) / ( ( PLLDIVM+1 ) * ( 2^PLLDIVK [2:0] ) )
Example:
Y1 = 20MHz
PLLDIVM = 0， ( PLLDIVMÎBit7 of REG[88h] )
PLLDIVN [4:0] = 1001， ( PLLDIVNÎBit[4:0] of REG[88h] )
PLLDIVK [2:0] = 001， ( PLLDIVKÎBit[2:0] of REG[89h] )
System Clock = 20MHz * ( 9+1 ) / ( ( 0+1 ) * ( 2^1 ) )
= 20MHz *10 / 4
= 50MHz
The default value of system clock frequency (SYS_CLK) is set as the same as the frequency of
external crystal (Fin). And it should be noted that, when REG[88h] or REG[89h] is programmed, to
make sure that the stability of the PLL output, a period of "frequency and phase lock time"(About
<30us) must be waited. After the "frequency and phase lock time" passing, user must generate a
software reset to complete the procedure of PLL frequency modification.
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
RA8872 supports the variety of LCD modules; the setting of clock depending on different resolution of
LCD module is list at below table.
Table 6-6 : Clock Setting for Different Display Application
DDRAM
Demand
Display
Resolution
Layer
No.
Color
Depth
( Bits )
Frame
( Hz )
System Clock
( SYS_CLK )
Internal
320x240
1
8/12
60
12.3MHz
Internal
320x240
1
16
60
24.6MHz
Internal
320x240
2
8/12
60
24.6MHz
Internal
320x480
1
8/12
60
24.6MHz
Internal
640x240
1
8/12
60
24.6MHz
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Pixel Clock
( PCLK )
6.15MHz
( SYS_CLK/2 )
6.15MHz
( SYS_CLK /4 )
6.15MHz
( SYS_CLK /4 )
12.3MHz
( SYS_CLK /2 )
12.3MHz
( SYS_CLK /2 )
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
6-7 Reset
The RA8872 requires a reset pulse at least 1024*tc long after power-on in order to re-initialize its
internal state. If the oscillator frequency is 25Mhz, then the Reset pulse is at least 40.96µs. For
maximum reliability, it is not recommended to apply a DC voltage to the LCD panel while the RA8872
is reset. Turn off the LCD power supplies for at least one frame period after the start of the reset pulse.
RA8872
RA8872
VDD
100KΩ
From MCU
RST#
RST#
1uF
0.1uF
SW
(Option)
(1)
(2)
Figure 6-18: Examples of RST# Pin
Figure 6-18 is an example for Reset application circuit. It could be controlled by MCU such as (1) of
Figure 6-18, or generated by a RC circuit such as (2) of Figure 6-18.
The RA8872 cannot receive commands while it is reset. Commands to initialize the internal registers
should be issued soon after a reset. During reset, the LCD drive signals XD, LP and FR are halted. A
delay of 1ms (minimum) is required following the rising edges of both RST# and VDD to allow for
system stabilization. Please refer to Figure 6-19 for more detail description.
t RS
t RH
0.8VDD
VDD
Reset Complete
ZRST
t RST
0.8VDD
0.2VDD
Max.
Typ.
Min.
Unit
tRS
Reset setup time
--
--
1
ms
tRH
Reset hold time
--
--
1
ms
tRST
Reset active time
--
--
1024
t c (*)
*t C is the period of system clock,
for example: 10MHz, t C = 100ns
Figure 6-19 : Reset Timing
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
When reset RA8872 (RST# = Low), please refer to Table 6-7 for the status of relative output signal.
Table 6-7: The Reset Status of Relative Output Signal
Sig na l Name
O utp ut Stat us
WAIT#, INT#
High
PWM1, PWM2
Low
GPIO[5:0]
Low
PDAT[15:0]
Low
VSYNC, HSYNC
High
PCLK, DE
Low
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
6-8 Power
6-8-1
Power Pin Description
RA8872 operates at 3.3V IO power and 1.8V core power. User can provide the 3.3V only for chip
LDO source and ADC/OSC IO signals. The internal LDO will generate the 1.8V power source for
Oscillator to guarantee the stability of the clock source. For the reason of chip reliability, it is not
suggested to connect the LDO output as the power source of other devices. For the detailed
description, please refer to Section 4-4.
6-8-2
Power Architecture
The architecture of the power is depicted below Figure 6-20. Note that for each power pad, the
bypass capacitors are suggested to add beside the pad as near as possible. It is recommended
to connect a 1uF bypass capacitor individually at the LDO output - LDO_CAP and LDO_OUT for
more stable power supply.
3.3V
3.3V
0.1uF
LDO_VDD
ADC_VDD
LDO_GND
1uF
LDO_CAP
1uF
LDO_OUT
LDO
OSC & PLL
ADC
CORE_VDD
ADC_GND
0.1uF
VDD
0.1uF
CORE
GND
GND
Figure 6-20 : The Power Connection for RA8872
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
7. Function Description
7-1
Screen Rotation
RA8872 provide the function of 90 degree, 180 degree and 270 degree display rotation to fit different
type of LCD panel. For example: panel size of 240x320 and 320x240.
7-1-1
Normal
MEMORY SCAN SEQUENCE
PANEL DISPLAY
RA8872
RA8872
RAiO
RAiO
Figure 7-1 : Memory and Panel Scan Direction in Normal
7-1-2
90 Degree
MEMORY SCAN SEQUENCE
PANEL DISPLAY
RA8872
RA8872
RAiO
RAiO
Figure 7-2 : Memory and Panel Scan Direction in Rotate 90 Degree
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
7-1-3
180 Degree
MEMORY SCAN SEQUENCE
PANEL DISPLAY
RAiO
RA8872
RA8872
RAiO
Figure 7-3 : Memory and Panel Scan Direction in Rotate 180 Degree
7-1-4
270 Degree
PANEL DISPLAY
RAiO
MEMORY SCAN SEQUENCE
RAiO
RA8872
RA8872
Figure 7-4 : Memory and Panel Scan Direction in Rotate 270 Degree
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RA8872
Version 1.4
7-2
Character / Graphic TFT LCD Controller
Scroll Function
The RA8872 provides both horizontal scroll and vertical scroll.
7-2-1
Horizontal Scroll
The RA8872 provides horizontal scroll feature. Users could flexibly assign the scrolling range in
the display area and by increasing or decreasing the value of offset as the unit of pixels. Users
can achieve the effect of block scrolling. Please refer to Figure 7-5 as the display example.
RAiO
RAiO
RAiO
．．．
O
RAi
Figure 7-5 : Horizontal Scroll
Note: The value of offset ({HOFS1,HOFS0}) must smaller then {HESW1,HESW0} {HSSW1,HSSW0}.
7-2-2
Vertical Scroll
The vertical scroll feature is similar with the function of horizontal scroll. The difference is that the
offset will cause the vertical scroll effect. So increasing or decreasing the offset will cause the
effect of vertical scrolling. Refer to Figure 7-6 as a display example.
RAiO RA8872
RAiO RA8872
RAiO
RAiO
RA8872
．．．
RA8872
RA8872
Figure 7-6 : Vertical Scroll Offset
Note: The value of offset ({VOFS1, VOFS0}) must small then {VESW1, VESW0} - {VSSW1,
VSSW0} .
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RA8872
Version 1.4
7-3
Character / Graphic TFT LCD Controller
Active Window
7-3-1
Normal and 90 Degree Rotation
Panel
Panel
y
x
y
Act Window
Act Window
x
Figure 7-7 : Active Window in Normal and 90
7-3-2
180 Degree and 270 Degree Rotation
Panel
Panel
Act Window
x
y
x
Act Window
y
Figure 7-8 : Active Window in 180 and 270
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
7-4 Cursor & Pattern
According to different applications, RA8872 provides flexibility and powerful functions of cursor and
pattern. There are two cursors defined in RA8872 - graphic cursor and text cursor. The first one
provides a 32x32 pixels graphic cursor which can be displayed at user-defined position. The later
provides a text relative cursor that can be set for height and width. Besides, RA8872 also support
“Pattern” function. The “Pattern” is a print with 8x8 pixels of size and at most 12bpps color depth for
each pixel. By operating with the BTE function, it can be used to duplicate and fill a print in a specific
area. And speed up the repeating writing operation and reduce the loading of MCU.
7-4-1
Graphic Cursor
The size of graphic cursor is 32x32 pixels, each pixel is composed by 2-bits, which indicate 4
colors setting (color 0, color 1, background color, the inversion of background color). It represents
that a graphic cursor takes 256 bytes(32x32x2/8). We provide eight groups of graphic cursor for
selection; users could use them just by setting related registers. By the way, the graphic cursor
position is controlled by register GCHP0(REG[80h]), GCHP1(REG[81h]), GCVP0(REG[82h]) and
GCVP1(REG[83h]).
Figure 7-9 : Relation of Memory Mapping and Graphic Cursor
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
The figure direction of graphic cursor won’t be changed after rotation. Refer to Figure 7-10 as
example.
Usage:
1. Set up color 0 and color 1 by setting register GCC0[REG[84h] and register
GCC0[REG[85h].
2. Setting MWCR1(REG[41h]) to select graphic cursor set and change write destination
selection to “Graphic Cursor”.
3. Using graphic mode to write data into graphic cursor storage space.
4. Enable graphic cursor(REG[41h] Bit7).
Normal
90 Degree
RA8872
RA8872
RAiO
RAiO
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270 Degree
180 Degree
RA8872
RAiO
RA8872
Figure 7-10 : Graphic Cursor Position and Direction after Rotation
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
7-4-2
Text Cursor
7-4-2-1
Cursor Position
The “Text Cursor” is a dedicated cursor to indicate the location for reading/writing data or text.
The position of text cursor is set by the registers of CURH0(REG[46h]), CURH1(REG[47h]),
CURV0(REG[48h]) and CURV1(REG[49h]). The text cursor could display at both text and
graphic mode. When setting as text mode, the height and width of text cursor can be
programmed. But in graphic mode, only the width of text cursor can be programmed and the
height of it is dominated as 1 pixel. It is also set as Auto-Increase mode for write DDRAM or
read data from DDRAM. When Auto-Increase mode is set, each read/write data cycle from/to
DDRAM will cause the text cursor to move to next location. In text mode, the cursor moves
the width of a text. In graphic mode, the cursor moves a pixel only. The cursor-moving
boundary depends on the setting of active window. When moving to the boundary of the
display, the part that over the display will be ignored.
7-4-2-2
Cursor Blinking
The user could control cursor on/off or blinking. The register BTCR(REG[44h]) is used to set
up blinking. Blinking time = BTCR[44h]*(1/Frame_Rate).
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Figure 7-11 : Cursor Blinking
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
7-4-2-3
Cursor Height and Width
The cursor height and width is controlled by register CURS(REG[45h]) show on Table 7-1.
The height and width could be set as 1~16 pixels with user’s requirement. About the cursor
movement for normal and vertical font, please refer to Figure 7-12 and Figure 7-13 as
example.
Table 7-1 : Cursor Height and Width
RAiO
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Figure 7-12 : Cursor Movement for Normal Font
Figure 7-13 : Cursor Movement for Vertical Font
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
7-4-3
Pattern
The RA8872 have pattern memory that for writing pattern data in it. If 2D pattern function active,
the specified pattern memory data will fill in specify area.
The RA8872 Pattern memory can use REG[41h], [66h] to specify pattern memory. In RA8872
memory have 32 pattern memories, each have 8x8 pixels. Internal RAM is 12-bit width. So if
MCU interface is 8-bit mode, and MCU write 8-bit data in, RA8872 will be expansion 8-bit Æ
12-bit. If MCU interface is 16-bit, the RA8872 will be transferred to16-bit Æ 12-bit and write
through pattern memory.
RA8872
Internal RAM
12bit
8
logic
MCU
REG[44h] =Pattern
REG[66h] =Pattern No
Figure 7-14 : 8-Bits Mode
RA8872
Internal RAM
16
12bit
Logic
MPU
REG[44h] =Pattern
REG[66h] =Pattern No
Figure 7-15 : 16-Bits Mode
Table 7-2 : Related Register Table
Register Name
Bit Num
Function Description
Address
MWCR1
3-2
[41h]
PTNO
7-0
Memory control register for setting write
pattern memory
Pattern Number register, that is specified
pattern number for MCU to write pattern
memory
[66h]
How to use Pattern function; please refers to Section 7-7 BTE function.
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RA8872
Version 1.4
7-5
Character / Graphic TFT LCD Controller
Font
7-5-1
Internal Font ROM
The RA8872 embedded 8x16 dots ASCII Font ROM that user can write the font into DDRAM by
using standard font code. The embedded ASCII Font ROM supports ISO8859-1~4 font. Besides,
user can choose the font foreground color by setting the REG[42h] and background color by
setting the REG[43h]. The procedure of writing font just refers to below figure:
Text Mode
REG[40h] bit7=1
Background color
Internal Font ROM Select
REG[21h] bit7=0, bit5=0
Foreground color
Font foreground and background color Select
REG[42h], REG[43h]
Write the font Code
CMD_WR[02h]
DATA_WR[font_code]
Figure 7-16 : ASCII Font ROM Programming Procedure
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
Table 7-3 shows the standard character encoding of ISO/IEC 8859-1. ISO means International
Organization for Standardization. The ISO 8859-1 also less formally called “Latin-1” is the first
8-bit coded character sets that developed by the ISO. It refers to ASCII that consisting of 192
characters from the Latin script in range 0xA0-0xFF. This character encoding is used throughout
Western Europe, includes Albanian, Afrikaans, Breton, Danish, Faroese, Frisian, Galician,
German, Greenlandic, Icelandic, Irish, Italian, Latin, Luxembourgish, Norwegian, Portuguese,
Rhaeto-Romanic, Scottish Gaelic, Spanish, Swedish. English letters with no accent marks also
can use ISO 8859-1.
In addition, it also commonly used in many languages outside Europe, such as Swahili,
Indonesian, Malaysian and Tagalong.
Table 7-3 : ASCII Block 1(ISO 8859-1)
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
Table 7-4 shows the standard characters of ISO/IEC 8859-2. ISO 8859-2 also cited as Latin-2 is
the part 2 of the 8-bit coded character sets developed by ISO/IEC 8859. These code values can
be used in almost any data interchange system to communicate in the following European
languages: Croatian, Czech, Hungarian, Polish, Slovak, Slovenian, and Upper Sorbian. The
Serbian, English, German, Latin can use ISO 8859-2 as well. Furthermore it is suitable to
represent some western European languages like Finnish (with the exception of å used in
Swedish and Finnish)
Table 7-4 : ASCII Block 2(ISO 8859-2)
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
Table 7-5 shows the standard characters of ISO/IEC 8859-3. ISO 8859-3 also known as Latin-3
or “South European” is an 8-bit character encoding, third part of the ISO 8859 standard. It was
designed originally to cover Turkish, Maltese and Esperanto, though the introduction of ISO
8859-9 superseded it for Turkish. The encoding remains popular with users of Esperanto and
Maltese, though it also supports English, German, Italian, Latin and Portuguese.
Table 7-5 : ASCII Block 3(ISO 8859-3)
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
Table 7-6 shows the standard characters of ISO/IEC 8859-4. ISO 8859-4 is known as Latin-4 or
“North European” is the forth part of the ISO 8859 8-bit character encoding. It was designed
originally to cover Estonian, Greenlandic, Latvian, Lithuanian, and Sami. This character set also
supports Danish, English, Finnish, German, Latin, Norwegian, Slovenian, and Swedish.
Table 7-6 : ASCII Block 4(ISO 8859-4)
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
7-5-2
CGRAM
The RA8872 supports 256 half size or 128 full size CGRAM space that lets user can create fonts
or symbols they want. User just writes the font or symbol data to the indicated space and then
writes the corresponding font code, RA8872 will write the font or symbol to the DDRAM. Also,
user can choose the font foreground color by setting the REG[42h] and background color by
setting the REG[43h].The procedure of creating and writing just refers to below figure:
1.Create the font or symbol
2.Write the font or symbol to display RAM
Graphic mode
REG[40h] bit7=0
Text mode
REG[40h] bit7=1
CGRAM Space Select
REG[23h]
CGRAM Select
REG[21h] bit7=1
Write to the CGRAM
REG[41h] bit3=0,bit2=1
Write to the Bank1 or Bank2
REG[41h] bit3=0,bit2=0
Write the font or symbol data
CMD_WR[02h]
DATA_WR[data0]
DATA_WR[data1]
I
DATA_WR[data15]
CGRAM half size
REG[21h] bit6=0
CGRAM full size
REG[21h] bit6=1
Write the font or symbol
CMD_WR[02h]
DATA_WR[font_code]
Write the font or symbol
CMD_WR[02h]
DATA_WR[font_code]
Figure 7-17 : CGRAM Programming Procedure
Figure 7-18 : CGRAM Description
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
7-5-3
90 Degree Font
The RA8872 supports the 90 degree font write by setting the REG[22h] Bit4 = 1. And collocating
the VDIR(REG[20h] Bit2), LCD module can show the 90 degree font.
Figure 7-19 : Font 90∘Rotation
7-5-4
Bold, Enlargement, Transparent Font
RA8872 also supports font bold (REG[22h] Bit5), enlargement (REG[22h] Bit[3:0]), and
transparent function(REG[22h] Bit6). Moreover, these functions can use simultaneously. The
behaviors of these functions just refer to below figure:
Figure 7-20 : Boldface and Transparent Font
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
7-5-5
Font Change Line when Setting Write Auto Move
RA8872 supports the auto move of font write and it will auto change line with active window. By
setting REG[40h] Bit1 = 0, the position of font will move automatically and change line when the
font over the range of horizontal or vertical active window. Refer the below figure to view the
behavior of auto move.
技
Auto move
瑞佑科技
RAiO
Horizontal range of active window
瑞佑科
技
Vertical range of active window
瑞佑科
Active window
Figure 7-21 : Auto Change Line in Font Mode
7-5-6
Font Full-Alignment
RA8872 supports font full-alignment that let the fonts align each other when writing half and full
fonts on the DDRAM. By setting REG[22h] Bit7 = 1, the behavior of writing half and full fonts will
be the below figure:
瑞
R
瑞
R
歡
迎
佑
A i
科
O
佑
A i
科
光
臨
瑞
Non full-alignment
技
O
Full-alignment
技
佑
科
技
Display RAM
Figure 7-22 : Full-Alignment Function
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RA8872
Version 1.4
7-6
Character / Graphic TFT LCD Controller
Geometric Pattern Drawing Engine
7-6-1
Circle Input
RA8872 supports draw circle function let user can draw circle on the DDRAM only use few MCU
cycles. By setting the center of a circle REG[99h~9Ch] ,the radius of a circle REG[9Dh] and the
color of circle REG[42h], and then setting start draw REG[90h] Bit6 = 1, RA8872 will draw a
corresponding circle on the DDRAM. Moreover, user can fill the circle by setting REG[90h] Bit5 =
1. The procedure of drawing circle just refers to the below figure:
Set the center of a circle
REG[99h~9Ch]
Don’t fill a circle
REG[90h] bit5=0
fill a circle
REG[90h] bit5=1
Start drawing circle
REG[90h] bit6=1
Start drawing circle
REG[90h] bit6=1
Set the radius of a circle
REG[9Dh]
Set the color of a circle
REG[42h]
center
radius
color
center
radius
color
Figure 7-23 : Geometric Pattern Drawing- Draw Circle
Note:
Circle input will be dominated in the range of active windows. But it must fit the condition below :
Assume coordination of the center of the circle is (X, Y) , the radius is R, then Y1+R < 512。
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
7-6-2
Square Input
RA8872 supports draw square function let user can draw square on the DDRAM only use few
MCU cycles. By setting the start point of a square REG[91h~94h] ,the end point of a square
REG[95h~98h] and the color of a square REG[42h], then setting draw a square REG[90h] Bit4 =
1 and start draw REG[90h] Bit7 = 1, RA8872 will draw a corresponding square on the DDRAM.
Moreover, user can fill the square by setting REG[90h] Bit5 = 1. The procedure of drawing square
just refers to the below figure:
Set start point of a square
REG[91h~94h]
Don’t fill a square
REG[90h] bit5=0
fill a square
REG[90h] bit5=1
Start drawing square
REG[90h] bit7=1
Start drawing square
REG[90h] bit7=1
Set the end of a square
REG[95h~98h]
Set the color of a square
REG[42h]
Start point
color
Set draw a square
REG[90h] bit4=1
Start point
End point
color
End point
Figure 7-24 : Geometric Pattern Drawing- Draw Rectangle
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
7-6-3
Line Input
RA8872 supports draw line function let user can draw line on the DDRAM only use few MCU
cycles. By setting the start point of a line REG[91h~94h] ,the end point of a line REG[95h~98h]
and the color of a line REG[42h], then setting draw a line REG[90h] Bit4 = 0 and start draw
REG[90h] Bit7 = 1, RA8872 will draw a corresponding line on the DDRAM. The procedure of
drawing line just refers to the below figure:
Set start point of a line
REG[91h~94h]
Set draw a line
REG[90h] bit4=0
Set the end of a line
REG[95h~98h]
Start drawing line
REG[90h] bit7=1
Set the color of a line
REG[42h]
Start point
End point
color
color
End point
Start point
Figure 7-25 : Geometric Pattern Drawing- Draw Line
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RA8872
Version 1.4
7-7
Character / Graphic TFT LCD Controller
BTE (Block Transfer Engine) Function
The RA8872 embedded a built-in 2D Block Transfer Engine(BTE) which can increase the
performance of block transfer operation. When a block of data needs to be moved or do some logic
operation with dedicated data, RA8872 can speed up the operation by BTE hardware and also
simplify the MCU program. BTE function is compatible with 2D BitBLT standard function. This section
will discuss the BTE engine operation and functionality.
Before using the BTE function, use must select the corresponding BTE operation. RA8872 supports
13 BTE operations. About the operation description, please mention the Table 7-7 below. For each
BTE operation, maximum 16 raster operations (ROP) are supported for different application. They
could provide the different logic combinations for ROP source and ROP destination. Through the
combination of the BTE operation and ROP, user can achieve many useful application operations.
The ROP source or destination can be set as a rectangular of display area(block mode) or a
continuous memory section(Linear addressing mode). Please refer to the behind chapters for detail
description.
The BTE function has 2 methods for checking the complete of BTE process. One way is checking
busy by software, and the other way is using hardware interrupt. When BTE engine is operating, the
busy flag in the status register will be set, the bit responses the system is busy or not. BTE operation
is a kind of busy condition. User can read it to determine if it is done. (Please reference Section 5-1
Status Register.) Hardware interrupt(INT#) is another way to check BTE process end, user can
enable interrupt function by REG[8Fh] first. If BTE final, RA8872 will generate hardware interrupt to
note MCU, and user checks the interrupt status to confirm the BTE status. When BTE is operating, it
is suggested that the user should not write command to RA8872 except REG[02h] or REG[8Fh] to
prevent the un-expected result. Please note the BTE function must use under Graphic Mode (REG
[40h] Bit7 = 0).
Table 7-7 : BTE Operation Function
BTE Operation
REG[51h] Bits [3:0]
BTE Operation
0000
Write BTE with ROP. Please refer to Table 7-8.
0001
Read BTE.
0010
Move BTE in positive direction with ROP. Please refer to Table 7-8.
0011
Move BTE negative direction with ROP. Please refer to Table 7-8.
0100
Transparent Write BTE.
0101
Transparent Move BTE in positive direction.
0110
Pattern Fill with ROP. Please refer to Table 7-8.
0111
Pattern Fill with transparency.
1000
Color Expansion. Please refer to Table 7-9
1001
Color Expansion with transparency. Please refer to Table 7-9.
1010
Move BTE with Color Expansion. Please refer to Table 7-10.
Move BTE with Color Expansion and transparency.
Please refer to Table 7-10.
Solid Fill.
1011
1100
Other combinations
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
Table 7-7describes 13 BTE operation modes of RA8872, if the operation code is “0000”, “0010”,
“0011” and “0110” then it has to collocate with raster operation code for the variety functions. Please
refer to Table 7-8.
Table 7-8 : ROP Function (1)
ROP Bits
REG[51h] Bit[7:4]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Boolean Function
Operation
0 ( Blackness )
~S・~D or ~ ( S+D )
~S・D
~S
S・~D
~D
S^D
~S+~D or ~ ( S・D )
S・D
~ ( S^D )
D
~S+D
S
S+~D
S+D
1 ( Whiteness )
Note:
1. ROP Function S: Source Data, D: Destination Data.
2. For pattern fill functions, the source data indicates the pattern data.
Example:
If ROP function setting Ch, then Destination Data = Source Data
If ROP function setting Eh, then Destination Data = S + D
If ROP function setting 2h, then Destination Data = ~S・D
If ROP function setting Ah, then Destination Data = Destination Data
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Version 1.4
Character / Graphic TFT LCD Controller
Table 7-9 : ROP Function (2)
ROP Bits
REG[51h] Bit[7:4]
Start Bit Position for Color Expansion
BTE operation code = 1000 / 1001
8-bit MCU Interface
0000
0001
Bit0
Bit1
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Table 7-10 : ROP Function (3)
ROP Bits
REG[51h] Bit[7:4]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
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Start Bit Position for Move Color Expansion
BTE operation code = 1010 / 1011
Color Depth
= 65Kcolors
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Bit8
Bit9
Bit10
Bit11
Bit12
Bit13
Bit14
Bit15
Color Depth
= 4K colors
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Bit8
Bit9
Bit10
Bit11
Invalid
Invalid
Invalid
Invalid
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Color Depth
= 256 colors
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
7-7-1
Select BTE Start Point Address and Layer
In the 2 layer display configuration, The ROP source and destination can comes from the
selectable layer. To program the ROP source or ROP destination, the start point of horizontal and
vertical address is set first. Please refer to register VSBE0/1 and VDBE0/1. The layer selection is
also looking us a part of address of VSBE1 Bit[7], VDBE1 Bit[7], where the VSBE1 Bit[7] is
source layer selection and the VDBE1 Bit[7] is destination layer selection.
7-7-2
BTE Operations
7-7-2-1
Write BTE
The Write BTE provides 16 ROP functions with two-operands, where BTE engine will write
the result of ROP function to the destination address.
7-7-2-2
Read BTE
The Read BTE supports data read function from the source to the host. No ROP function is
applied.
7-7-2-3
Move BTE
The Move BTE provides 16 ROP functions with two operands, and is supported in both a
positive and negative direction.
7-7-2-4
Solid Fill
The Solid Fill BTE fill a specified BTE area(source) with a solid color as define in the BTE
Foreground Color Register.
7-7-2-5
Pattern Fill
The Pattern Fill BTE fill a specified BTE area with an 8 pixel by 8 line pattern defined in
off-screen DDRAM ram area.
7-7-2-6
Transparent Pattern Fill
The Transparent Pattern Fill function fills a specified BTE area with an 8 pixel by 8 line
pattern in off-screen DDRAM ram area. When the pattern color is equal to the key color,
which is defined in Background Color Register, the destination area is not updated. For the
function no raster operation is applied.
7-7-2-7
Transparent Write BTE
The Transparent Write BTE supports bit block transfers from the host to DDRAM ram area.
When the source color is equal to the key color, which is defined in BTE Background Color
Register, the destination area is not updated. For this function no raster operation is applied.
7-7-2-8
Transparent Move BTE
The Transparent Move BTE supports block transfers from DDRAM ram to DDRAM ram in
positive direction only. When the source color is equal to key color, which is defined in BTE
Background Color Register, the destination area is not updated. For this BTE no raster
operation is applied.
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
7-7-2-9
Color Expansion
The Color Expansion BTE expands the host’s monochrome data to 8 or 12 or 16 bpp color
format.
A 1 expands to the color defined in the BTE Foreground Color Register.
A 0 expands to the color defined in the BTE Background Color Register.
If background transparency is enabled, then the destination color will remain untouched.
7-7-2-10 Move BTE with Color Expansion
The Move BTE with Color Expansion expands off-screen source’s monochrome data to 8 or
12 or 16 bpp color format .The source data is 1 expands BTE Foreground Color to the
DDRAM. The MEM data is 0 expands BTE Background Color Register to the DDRAM. If
background transparency is enabled, then the destination MEM data will remain.
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
7-7-3
BTE Access Memory Method
The BTE have two methods to access memory, the block memory access and linear memory
access. The area or size is defined by REG[5Ch], [5Dh], [5Eh] and [5Fh]. About the description of
two types of memory access, please refer to following section.
7-7-3-1
Block Memory Access
With the setting, The BTE memory source/destination data is treated as a block of display
area. The block width and height is defined in REG[5Ch-5Fh].The below example shows
both the source and destination address are defined as block access method:
DPRAM - Layer
Source Address
Destination Address
Figure 7-26 : Block Memory Access of BTE Function
7-7-3-2
Linear Memory Access
With the setting, The BTE memory source/destination data is treated as a continuous area of
display area. The area length is calculated from the REG[5Ch-5Fh], the length equal to
(BTE_WIDTH * BTE_HEIGHT).
The below example shows both the source and destination address are defined as linear
access method.
Source Linear
Total Process Data length = BTE Width * High
Destination Linear
Figure 7-27 : Linear memory access of BTE function
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
7-7-4
BTE Function Explaination
7-7-4-1
Write BTE with ROP
The Write BTE increases the speed of transferring data from system memory to the DDRAM.
The Write BTE with ROP fills a specified area of the DDRAM with data supplied by the MCU.
The Write BTE supports all 16 ROPs. It also supports both Destination Linear and
Destination Block modes. The Write BTE requires the MCU to provide data.
User can use this function by hardware interrupt or software check busy to get BTE process
status. If User check BTE process status by software, the BECR0(REG[50h]) Bit7 or status
register(STSR) Bit6 can indicate the BTE status. By another way, user can check BTE
process status by hardware interrupt, the INT# must connect to MCU and REG[8Fh] is used
to check the interrupt source comes from BTE when INT# is active.
RA8872
DDRAM
MPU
Figure 7-28 : Write BTE with ROP
The suggested programming steps and registers setting are list below as reference.
1.
2.
3.
4.
5.
6.
7.
8.
9.
Setting destination position
Æ REG[58h], [59h], [5Ah], [5Bh]
Setting BTE width register
Æ REG[5Ch], [5Dh]
Setting BTE height register
Æ REG[5Eh], [5Fh]
Setting register Destination = source Æ REG[51h] = Ch
Enable BTE function
Æ REG[50h] Bit7 = 1
Enable REG[02h]
Check STSR Bit7
Write next image data
Continue run step 7, 8 until image data = block image data. Or Check STSR Bit6
Figure 7-29 : After BTE Function
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
The following process using INT# to confirm the complete of BTE operation. By using the
method, user must make sure that the INT# signal is connected to MCU interrupt pin first.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
Setting INTC register
Æ REG[8Fh]
Setting Destination position
Æ REG[58h], [59h], [5Ah], [5Bh]
Setting BTE width register
Æ REG[5Ch], [5Dh]
Setting BTE height register
Æ REG[5Eh], [5Fh]
Setting register Destination = source Æ REG[51h] = C0h
Enable BTE function
Æ REG[50h] Bit7 = 1
Wait for Interrupt generate
Clear INTC BTE Read/Write status
Æ REG[8Fh] Bit0 = 1
Enable REG[02h]
Write next image data
Wait for Interrupt generate
Clear INTC BTE Read/Write status
Æ REG[8Fh] Bit0 = 1
Continue run step 9,10,11,12 until image data = block image data. Or check STSR Bit6
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
7-7-4-2
Read BTE (Burst Read like function)
This Read BTE increases the speed of transferring data from the DDRAM to system memory.
This Read BTE function is typically used to save a part of data in the DDRAM to the system
memory. Once the Read BTE begins, the BTE engine remains active to provide the data
from DDRAM for MCU until all the data have been read. The number of data for BTE is
calculated by REG[5Ch-5Fh] as (BTE_WIDTH * BTE_HEIGHT).
RA8872
MPU
DDRAM
Figure 7-30 : Read BTE
The suggested programming steps and registers setting are list below as reference.
1.
2.
3.
4.
5.
6.
7.
8.
9.
Setting source position
Æ REG[54h], [55h], [56h], [57h]
Setting BTE width register
Æ REG[5Ch], [5Dh]
Setting BTE height register
Æ REG[5Eh], [5Fh]
Setting register operation
Æ REG[51h] = 01h
Enable BTE function
Æ REG[50h] Bit7 = 1
Enable REG[02h]
Check STSR Bit7
Read next image data
Continue run step 7,8 until image data = block image data. Or Check STSR Bit6
The following process using INT# to confirm the complete of BTE operation. By using the
method, user must make sure that the INT# signal is connected to MCU interrupt pin first.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
Setting INT#
Æ REG[8Fh]
Setting source position
Æ REG[54h], [55h], [56h], [57h]
Setting BTE width register
Æ REG[5Ch], [5Dh]
Setting BTE height register
Æ REG[5Eh], [5Fh]
Setting register operation
Æ REG[51h] = 01h
Enable BTE function
Æ REG[50h] Bit7 = 1
Wait for Interrupt generate
Check REG[8Fh] Bit 0 = 1
Enable REG[02h]
Read next image data
Clear INT# BTE Read/Write status
Æ REG[8Fh] Bit0 = 1
Continue run step 7, 8, 9 ,10,11 until image data all read. Or Check STSR Bit6
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
7-7-4-3
Move BTE in Positive Direction with ROP
The Move BTE moves a specific area of the DDRAM to a different area of the DDRAM. This
operation can speed up the data copy operation from one block to another. And save a lot of
MCU processing time and loading.
Destination
Source
Figure 7-31 : Move BTE in Position Direction with ROP
The Move BTE source/destination can be a rectangular area or a linear area. This function
allows the temporary saving of a portion of the visible DDRAM to an off-screen area for later
using. Or copy the off-screen data to the visible area.
The suggested programming steps and registers setting are list below as reference.
1.
2.
3.
4.
5.
6.
Setting source layer and address
Setting destination layer and address
Setting BTE width and height
Setting BTE operation and ROP function
Enable BTE function
Check STSR REG Bit6
Æ REG[54h], [55h], [56h], [57h]
Æ REG[58h], [59h], [5Ah], [5Bh]
Æ REG[5Ch], [5Dh], [5Eh], [5Fh]
Æ REG[51h] Bit[3:0] = 2h
Æ REG[50h] Bit7 = 1
Æ check 2D final
Figure 7-32 : Before BTE Function
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
Figure 7-33 : After BTE Function
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
7-7-4-4
Move BTE in Negative Direction with ROP
The Move BTE in Negative Direction with ROP function operates almost the same behavior
as the Positive Direction. But the direction is opposite to it. It moves the latest data of the
BTE source to the latest data of BTE destination first, then operating backward to the starting
point of BTE source/destination. For the application that BTE source and destination are
overlay, the different direction of Move BTE will cause different result.
Source
Destination
Figure 7-34 : Move BTE in Negative Direction with ROP
The Move BTE moves a specific area of the DDRAM to a different area of the DDRAM. This
operation can speed up the data copy operation from one block to another.
The suggested programming steps and registers setting are list below as reference.
1.
2.
3.
4.
5.
6.
Setting source layer and address
Setting destination layer and address
Setting BTE width and height
Setting BTE operation and ROP function
Enable BTE function
Check STSR REG Bit6
Æ REG[54h], [55h], [56h], [57h]
Æ REG[58h], [59h], [5Ah], [5Bh]
Æ REG[5Ch], [5Dh], [5Eh], [5Fh]
Æ REG[51h] Bit[3:0] = 3h
Æ REG[50h] Bit[7] = 1
Æ check 2D final
Figure 7-35 : Before BTE Function
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
Figure 7-36 : After BTE Function
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
7-7-4-5
Transparent Write BTE
The Transparent Write BTE increases the speed of transferring data from system memory to
the DDRAM. Once the Transparent Write BTE begins, the BTE engine remains active until
all pixels have been written.
“Transparent Write BTE” updates a specified area of the DDRAM with data supplied by the
MCU. Unlike “Write BTE” operation, the “Transparent Write BTE” will ignore the operation of
a dedicated color that is set as “Transparent Color”. In RA8872, the “Transparent Color” is
set as “BTE Foreground Color“ in the “Transparent Write BTE” operation. When the source
color of the operation meets the “Transparent Color”, no write function will be done. This
function is useful to copy a color image partially from system memory to the DDRAM. When
setting one color as the “transparent color”, the source pixel with the transparent color is not
transferred. This allows a fast paste function of a dedicated image to an arbitrary background.
For example, considering a source image has a red circle on a blue background. By
selecting the blue color as the transparent color and using the Transparent Write BTE on the
whole rectangles, the effect is a BTE of the red circle only. The Transparent Write BTE
supports both Destination Linear and Destination Block modes.
Image
RA8872
MPU
DDRAM
Figure 7-37 : Transparent Write BTE
The suggested programming steps and registers setting are list below as reference.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
Setting destination position
Æ REG[58h], [59h], [5Ah], [5Bh]
Setting BTE width register
Æ REG[5Ch], [5Dh]
Setting BTE height register
Æ REG[5Eh], [5Fh]
Setting Transparency Color –Background Color Æ REG[63h], [64h], [65h]
Setting BTE operation code and ROP Code
Æ REG[51h] = C4h
Enable BTE function
Æ REG[50h] Bit7 = 1
Enable REG[02h]
Write next image data
Check STSR Bit7
Continue run step 8, 9ntil image data = block image data. Or Check STSR Bit6
Figure 7-38 : Before BTE Function
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
Figure 7-39 : After BTE Function
The suggested programming steps and registers setting are list below as reference.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
Setting INT#
Æ REG[8Fh]
Setting Destination position
Æ REG[58h], [59h], [5Ah], [5Bh]
Setting BTE width register
Æ REG[5Ch], [5Dh]
Setting BTE height register
Æ REG[5Eh], [5Fh]
Setting register Destination = source Æ REG[51h] = C4h
Enable BTE function
Æ REG[50h] Bit7 = 1
Wait for Interrupt generate
Clear INT# BTE Read/Write status
Æ REG[8Fh] Bit0 = 1
Enable REG[02h]
Write next image data
Wait for Interrupt generate
Clear INT# BTE Read/Write status
Æ REG[8Fh] Bit0 = 1
Continue run step 9,10,11,12 until image data = block image data. Or Check STSR Bit6
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
7-7-4-6
Transparent Move BTE Positive Direction
“Transparent Move BTE in Positive Direction” moves an area of the DDRAM to a different
area of the DDRAM with ignoring the “Transparent Color”. The same with the “Transparent
Write BTE” operation, it allows for setting a transparent color which is not moved during the
BTE. The difference between “Transparent Write” and “Transparent Move” is the source of the
operation. , “Transparent Write” source comes from system memory or MCU and
“Transparent Move” source comes from DDRAM. Because the source is DDRAM, the
direction of the operation must be defined. RA8872 supports positive direction only for
“Transparent Move” function.
The source of “Transparent Move BTE” may be specified as linear mode or rectangle mode,
depending on the user setting. The destination area of the operation could be overlay with the
source area. One thing should be note is that in some special overlay case(source/destination
area), the source of the operation may be modified after the “Transparent Move” is done.
The suggested programming steps and registers setting are list below as reference.
1.
2.
3.
4.
5.
6.
7.
Setting source layer and address
Setting destination layer and address
Setting BTE width and height
Setting Transparency Color – Front ground Color
Setting BTE operation and ROP function
Enable BTE function
Check STSR REG Bit6
Æ REG[54h], [55h], [56h], [57h]
Æ REG[58h], [59h], [5Ah], [5Bh]
Æ REG[5Ch], [5Dh], [5Eh], [5Fh]
Æ REG[63h], [64h], [65h]
Æ REG[51h] Bit[3:0] = 5h
Æ REG[50h] Bit7 = 1
Æ check 2D final
Figure 7-40 : Before BTE Function
Figure 7-41 : After BTE Function
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
7-7-4-7
Pattern Fill with ROP
“Pattern Fill BTE with ROP” operation fills a specified rectangular area of the DDRAM with a
dedicated pattern repeatedly. The fill pattern is an array of 8x8 pixels stored in the off-screen
DDRAM. The pattern can be logically combined with the destination using one of the 16 ROP
codes. The operation can be used to speed up the application with duplicate pattern write in
an area, such as background paste function.
RA8872
DDRAM
Pattern
Panel Display Result
Figure 7-42 : Pattern Fill with ROP
The suggested programming steps and registers setting are list below as reference.
1.
2.
3.
4.
5.
Setting destination layer and address
Setting BTE width and height
Setting BTE operation and ROP function
Enable BTE function
Check STSR REG Bit6
Æ REG[58h], [59h], [5Ah], [5Bh]
Æ REG[5Ch], [5Dh], [5Eh], [5Fh]
Æ REG[51h] Bit[3:0] = 06h
Æ REG[50h] Bit7 = 1
Æ check 2D final
Figure 7-43 : Before BTE Function
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
Figure 7-44 : Pattern
Figure 7-45 : After BTE Function
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
7-7-4-8
Pattern Fill with Transparency
The Pattern Fill BTE with Transparency fills a specified rectangular area of the DDRAM with a
pattern. The function is the same with “Pattern Fill” and with the setting of “Transparent Color”.
In the pattern fill operation, the transparent color is ignored. The fill pattern is an eight by eight
array of pixels stored in off-screen DDRAM. The fill pattern must be loaded to off-screen
DDRAM prior to the BTE starting. It should be noted that for “Pattern Fill with Transparency”
function, transparent color is only available for 256 colors. i.e. Only BIT[4:2] of REG[63h], BIT
[5:3] of REG[64h]and BIT[4:3] of REG[65h] BIT [4:3] are valid, please refer to the relative
register for detail description.
Pattern
RA8872
DDRAM
Panel Display result , if set blue color is
transparency color
Figure 7-46 : Pattern Fill with Transparency
The suggested programming steps and registers setting are list below as reference.
1.
2.
3.
4.
5.
6.
Setting destination layer and address
Setting BTE width and height
Setting Transparency Color – Front ground Color
Setting BTE operation and ROP function
Enable BTE function
Check STSR Bit6
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Æ REG[58h], [59h], [5Ah], [5Bh]
Æ REG[5Ch], [5Dh], [5Eh], [5Fh]
Æ REG[63h], [64h], [65h]
Æ REG[51h] Bit[3:0] = 07h
Æ REG[50h] Bit7 = 1
Æ check 2D final
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
Figure 7-47 : Before BTE Function
Figure 7-48 : Pattern Image
Figure 7-49 : After BTE Function
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
7-7-4-9
Color Expansion
“Color Expand” is a useful operation to translate monochromes data of system memory to
color one. In the operation, the source data will be treated as a monochromes bit-map. The
bit-wise data is translated to multi-bits per pixel color data by the setting of “BTE Foreground
Color” and “BTE Background Color”. The source bit “1” will be translated to “BTE Foreground
Color” and the source bit ”0” is translated to “BTE Background Color”. This function can
largely reduce the effort when system translation from mono system to color system. “Color
Expand” operation will be continuously feeding a 16-bit/8-bit (Reference MPU interface
setting) data package. When the end of the line is reached, any unused bits will be discarded.
The data for the next line will be taken from the next data package. Each bit is serially
expanded to the destination data starting from MSB to LSB.
RA8872
Mono
Color
MPU
DDRAM
Bitmap
Color Image
Mono Color Bitmap
RAIO production
is very good
RAIO production
is very good
Figure 7-50 : Color Expansion Data Block
The suggested programming steps and registers setting are list below as reference.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
Setting destination position
Æ REG[58h], [59h], [5Ah], [5Bh]
Setting BTE width register
Æ REG[5Ch], [5Dh]
Setting BTE height register
Æ REG[5Eh], [5Fh]
Setting Background Color – The transferred color when bitmap = 0
Æ REG[60h], [61h], [62h]
Setting Foreground Color –The transferred color when bitmap = 1
Æ REG[63h], [64h], [65h]
Setting BTE operation and ROP function
Æ REG[51h] Bit[3:0] = 08h
Enable BTE function
Æ REG[50h] Bit7 = 1
Enable REG[02h]
Check STSR Bit7
Write next image data
Continue run step 9,10 until image data = block image data. Or Check STSR Bit6
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
The following process using INT# to confirm the complete of BTE operation. By using the
method, user must make sure that the INT# signal is connected to MCU interrupt pin first.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
Setting INT#
Æ REG[8Fh]
Setting Destination position
Æ REG[58h], [59h], [5Ah], [5Bh]
Setting BTE width register
Æ REG[5Ch], [5Dh]
Setting BTE height register
Æ REG[5Eh], [5Fh]
Setting Background Color – The transferred color when bitmap = 0
Æ REG[60h], [61h], [62h]
Setting Foreground Color –The transferred color when bitmap = 1
Æ REG[63h], [64h], [65h]
Setting BTE operation and ROP function
Æ REG[51h] Bit[3:0] = 08h
Enable BTE function
Æ REG[50h] Bit7 = 1
Wait for Interrupt generate
Clear INT# BTE Read/Write status
Æ REG[8Fh] Bit0 = 1
Enable REG[02h]
Write next image data
Wait for Interrupt generate
Clear INT# BTE Read/Write status
Æ REG[8Fh] Bit0 = 1
Continue run step 11,12,13,14 until image data = block image data. Or Check STSR Bit6
Figure 7-51 : Before BTE Function
Figure 7-52 : After BTE Function
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
Note:
1.
Calculate send data numbers per row = ((BTE Width size REG – (MCU interface
bits – (start bit + 1)) ) / MCU interface bits) + ((start bit + 1) % (MCU interface ))
2.
Total data number = (send data numbers per row ) * BTE Vertical REG setting
D4 8bit
D0
D1
D2
D3
MPU send to RA8870
data,The data have 8bit
for one transmitter data,
and serial send
D0,D1,D2 ,D3,D4 ~~
Dn to RA8870
start bit =4
D0
D1
D2
D3
Not Expansion
Not Expansion
BTE High REG [5Ah]
[5Bh] setting
Expansion
BTE Width REG
[58h] [59h] setting
Figure 7-53 : Color Expansion Data Diagram
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
7-7-4-10 Color Expansion with Transparency
This BTE operation is virtually identical to the Color Expand BTE, except the background
color is completely ignored. All bits set to 1 in the source monochrome bitmap are color
expanded to the “BTE Foreground Color”. All bits set to 0 in source monochrome bitmap that
would be expanded to the “BTE Background Color” are not expanded at all
RA8872
Mono
Color
Bitmap
MPU
Mono Color Bitmap
RAIO production
is very good
DDRAM
Color Image
RAIO production
is very good
Figure 7-54 : Color Expansion with Transparency
The suggested programming steps and registers setting are list below as reference.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
Setting destination position
Æ REG[58h], [59h], [5Ah], [5Bh]
Setting BTE width register
Æ REG[5Ch], [5Dh]
Setting BTE height register
Æ REG[5Eh], [5Fh]
Setting BTE Foreground Color – the transferred color when bitmap data = 1
Æ REG[63h], [64h], [65h]
Setting BTE operation and ROP function
Æ REG[51h] Bit[3:0] = 09h
Enable BTE function
Æ REG[50h] Bit7 = 1
Enable REG[02h]
Check STSR Bit7
Write next image data
Continue run step 8, 9 until image data = block image data. Or Check STSR Bit6
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
Destination address
Mono Bitmap
RAIO production
Is very good .
2D color
Expansion
RAIO production
Is very good .
Figure 7-55 : Color Expansion with Transparency
The following process using INT# to confirm the complete of BTE operation. By using the
method, user must make sure that the INT# signal is connected to MCU interrupt pin first.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
Setting INT#
Æ REG[8Fh]
Setting Destination position
Æ REG[58h], [59h], [5Ah], [5Bh]
Setting BTE width register
Æ REG[5Ch], [5Dh]
Setting BTE height register
Æ REG[5Eh], [5Fh]
Setting BTE operation and ROP function
Æ REG[51h] Bit[3:0] = 09h
Enable BTE function
Æ REG[50h] Bit7 = 1
Wait for Interrupt generate
Clear INT# BTE Read/Write status
Æ REG[8Fh] Bit0 = 1
Enable REG[02h]
Write next image data
Wait for Interrupt generate
Clear INT# BTE Read/Write status
Æ REG[8Fh] Bit0 = 1
Continue run step 9,10,11,12 until image data = block image data. Or check STSR Bit6
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
7-7-4-11 Move BTE with Color Expansion
The “Move BTE with Color Expansion” takes a monochrome bitmap as the source and color
expands it into the destination. Color expansion moves all bits in the monochrome source to
pixels in the destination. All bits in the source set to one are expanded into destination pixels
of the selected foreground color. All bits in the source set to zero are expanded into pixels of
the selected background color.
The Move BTE with Color Expansion is used to accelerate monochrome to color translation
on the screen. A monochrome bitmap in off-screen memory occupies very little space and
takes advantage of the hardware acceleration. Since the foreground and background colors
are programmable, text of any color can be created.
The Move BTE with Color Expansion may move data from one rectangular area to another, or
it may be specified as linear. The linear configuration may be applied to the source or
destination. Defining the Move BTE as linear allows each line of the Move BTE area to be
placed directly after the previous line, rather than requiring a complete row of address space
for each line.
8bit/pixel
12bit/pixel
DDRAM
Color Image
16bit/pixel
1bit/pixel
Mono color Bitmap
Mono Color Bitmap
RAIO production
is very good
Color expansion
Color Image
RAIO production
is very good
Figure 7-56 : Move BTE with Color Expansion
The suggested programming steps and registers setting are list below as reference.
1.
2.
3.
4.
5.
6.
7.
8.
Setting source layer and address
Æ REG[54h], [55h], [56h], [57h]
Setting destination layer and address
Æ REG[58h], [59h], [5Ah], [5Bh]
Setting BTE width and height
Æ REG[5Ch], [5Dh], [5Eh], [5Fh]
Setting Background Color – The transferred color when bitmap data = 0
Æ REG[60h], [61h], [62h]
Setting Foreground Color –The transferred color when bitmap data = 1
Æ REG[63h], [64h], [65h]
Setting BTE operation and ROP function
Æ REG[51h] Bit[3:0] = 0Ah
Enable BTE function
Æ REG[50h] Bit7 = 1
Check STSR REG Bit6
Æ check 2D final
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
Figure 7-57 : Before BTE Function
Figure 7-58 : After BTE Function
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
7-7-4-12 Move BTE with Color Expansion and Transparency
The “Transparent Move BTE with Color Expansion” is virtually identical to the Move BTE with
Color Expansion. The background color is ignored and bits in the monochrome source bitmap
set to 0 are not Color expanded
Figure 7-59 : Move BTE with Color Expansion and Transparency
The suggested programming steps and registers setting are list below as reference.
1.
2.
3.
4.
Setting source layer and address
Æ REG[54h], [55h], [56h], [57h]
Setting destination layer and address
Æ REG[58h], [59h], [5Ah], [5Bh]
Setting BTE width and height
Æ REG[5Ch], [5Dh], [5Eh], [5Fh]
Setting Foreground Color – The transferred color when bitmap data = 1
Æ REG[63h], [64h], [65h]
5. Setting BTE operation and ROP function
Æ REG[51h] Bit[3:0] = 0Bh
6. Enable BTE function
Æ REG[50h] Bit7 = 1
7. Check STSR REG Bit6
Æ check 2D final
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
7-7-4-13 Solid Fill
The Solid Fill BTE fills a rectangular area of the DDRAM with a solid color. This operation is
used to paint large screen areas or to set areas of the DDRAM to a given value. The Solid Fill
color data is setting by “BTE Foreground Color”.
Figure 7-60 : Solid Fill
The suggested programming steps and registers setting are list below as reference:
1.
2.
3.
4.
5.
6.
Setting destination layer and address
Setting BTE width and height
Setting BTE operation and ROP function
Setting foreground Color
Enable BTE function
Check STSR REG Bit6
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Æ REG[58h], [59h], [5Ah], [5Bh]
Æ REG[5Ch], [5Dh], [5Eh], [5Fh]
Æ REG[51h] Bit[3:0] = 0Ch
Æ REG[63h], [64h], [65h]
Æ REG[50h] Bit7 = 1
Æ check 2D final
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RA8872
Version 1.4
7-8
Character / Graphic TFT LCD Controller
Layer Mixed Function
RA8872 provides two layers display function, when two layers configuration of DPCR(REG[20h]
Bit7=1) is selected, users could use LTPR0(REG[52h]), LTPR1(REG[53h]) and BGTR(REG[67h]) to
generate different combination effect of layer one and layer two. The function of LTPR0, LTPR1 and
BGTR refer to Table 7-11.
Table 7-11 : The Function of LTPR0, LTPR1 and BGTR
Reg. NO.
52h
53h
67h
Abbreviation
LTPR0
LTPR1
Description
Layer Transparency Register 0
B[7:6] Layer1/2 Scroll Mode
00b : Layer 1/2 scroll at the same time
01b : Only Layer 1 scroll
1xb : Only Layer 2 scroll
B[2:0] Layer1/2 Display Mode
000b : Only Layer 1 is visible
001b : Only Layer 2 is visible
x11b : Transparent mode
x10b : Lighten-overlay mode
100b : Boolean OR
101b : Boolean AND
Layer Transparency Register 1
B[7:4] Layer Transparency Setting for Layer 2
0000b : Total display
0001b : 7/8 display
0010b : 3/4 display
0011b : 5/8 display
0100b : 1/2 display
0101b : 3/8 display
0110b : 1/4 display
0111b : 1/8 display
1000b : Display disable
B[3:0] Layer Transparency Setting for Layer 1
0000b : Total display
0001b : 7/8 display
0010b : 3/4 display
0011b : 5/8 display
0100b : 1/2 display
0101b : 3/8 display
0110b : 1/4 display
0111b : 1/8 display
1000b : Display disable
Background Color Register for Transparent
B[7:0] Background Color for Transparent Mode
BGTR
Background color of transparent with 256 color RGB format [7:0]
= RRRGGGBB
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
7-8-1
Only Layer One is Visible
If LTPR0 B[2:0] is set to 3’b000, only Layer 1 image will be shown on the panel screen. Please
refer to Figure 7-61 as example. This function also could be associated with LTPR1[3:0] and
BGTR to show similar the effect of filter. Refer to the following example as Figure 7-62.
RA8872
RAiO
Layer 2
RAiO
Layer 1
Figure 7-61 : Only Layer One is Visible
RAiO
Layer 1
LTPR0 B[2:0]= 3’b000
+
=
RAiO
LTPR1 B[3:0] = 4’b0100
BGTR
B[7:0] = 8’hE0
Figure 7-62 : Effect of Register LTPR1 and BGTR
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
7-8-2
Only Layer Two is Visible
If LTPR0 B[2:0] is set to 3’b001, only Layer 2 image will be show on the panel screen. Refer to
the following example as Figure 7-63 . This function also could be associated with LTPR1[7:4]
and BGTR to show similar the effect of filter. Refer to the following example as Figure 7-64.
RA8872
RAiO
Layer 2
RA8872
Layer 1
Figure 7-63 : Only Layer Two is Visible
Layer 2
+
RA8872
LTPR0 B[2:0]= 3’b001
= RA8872
LTPR1 B[7:4] = 4’b0100
BGTR
B[7:0] = 8’h1C
Figure 7-64 : Effect of Register LTPR1 and BGTR
7-8-3
Transparent Mode
The transparent mode makes the pixel of layer 1 with background color as “transparence”, that is,
the color of layer 2 of the pixel will be displayed. The function can be used to set the foreground
and background picture overlay display. The foreground picture is written on layer 1 and
background picture is written on layer 2. And the transparent area of foreground is written with
background color set by register BGTR. About the display effect please refer to the example of
Figure 7-65.
Key Color
RAiO
Layer 1
Layer 2
+
= RAiO
RA8872
Figure 7-65 : Effect of Transparent
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
7-8-4
Lighten-Overlay Mode
Lighten-Overlay Mode provides further visual enhancement image which one image gradually
fades into another image. The following equation describes the lighten-overlay technique used.
[r,g,b]Lighten-Overlay =χ[r,g,b] Layer 1 +(1- χ)[r,g,b] Layer 2
Where [r,g,b] is pixel data and χ is the weighting factor, it depends on the setting of LTPR1[3:0].
In other word, if LTPR1[3:0] is set as 4’b0100, the weighting factor χ is equal to 1/2. The
[r,g,b]Lighten-Overlay =1/2[r,g,b] Layer 1 + 1/2[r,g,b]Layer 2 .
About the display effect please refer to the example of Figure 7-66.
RAiO
Layer 1
Layer 2
+
= RAiO
RA8872
RA8872
Figure 7-66 : Effect of Light-Overlay
7-8-5
Boolean OR
Layer 1 pixel data and Layer 2 pixel data are displayed on panel screen after logic “OR”
operation.
RAiO
Layer 2
Layer 1
+
RA8872
=
RAiO
RA8872
Figure 7-67 : Boolean OR
7-8-6
Boolean AND
Layer 1 pixel data and Layer 2 pixel data are displayed on panel screen after logic “AND”
operation.
RAiO
Layer 2
Layer 1
+
RA8872
= RAiO
8872
Figure 7-68 : Effect of Boolean AND
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
7-8-7
Layer in Scroll Mode
We support three kinds of scroll mode for user to apply. You could scroll only layer one or only
layer two and also could scroll two layers at the same time.
Figure 7-69 : Effect of Layer 1 and Layer 2 Scroll Mode
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RA8872
Version 1.4
7-9
Character / Graphic TFT LCD Controller
Touch Panel Function
The 1 channel and 10 bits resolution A/D converter are implemented in RA8872 for 4-wires Touch
Panel application. The operation method and application information please refer to Chapter 6-4.
There are two types of ADC operating mode for user selection: Auto mode or Manual mode. When
using the manual mode, the touch Event can be detected by an Interrupt signal or the flag detecting
(Polling flag status), it is depend on the system configuration. The related descriptions are explained
as following.
7-9-1
Auto Mode
Auto mode is the easiest way to implement Touch Panel application. Users just need to enable
the related register and RA8872 will execute the Touch Panel function automatically. Please refer
to the follow chart as below.
Table 7-12 : Operation Mode for Touch Panel Function
Operation
Mode
Auto
Event
Detection
Description
Interrupt
When touch event happens, read the corresponding X, Y coordination.
Polling the touch event, read the corresponding X, Y coordination.
Polling
Manual
Interrupt
When touch event happens, read the corresponding X, Y coordination.
Polling
Polling the touch event, and read the corresponding X, Y coordination.
ISR
START
Enable Touch Panel
(Reg[70h] B7 = 1)
Check INT State
(REG [8Fh] B2 = ?)
0
1
Set Auto Mode
Read X,Y-axis
(Reg[71h] B6 = 0)
Read Reg [72h]
Read Reg [73h]
Enable TP INT
(Reg[8Fh] B6 = 1)
Other
Functions
Cause the
Interrupt
Read Reg [74h]
Execute Function
..
..
.
Clear TP INT Status
Other Function
(write REG[8Fh] B2 = 1)
Figure 7-70 : Auto-Mode Follow Chart
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
Clear TP INT Status
START
(write REG[8Fh] B2 = 1)
Enable Touch Panel
(Reg[70h] B7 = 1)
Check INT State
(REG [8Fh] B2 = ?)
1
Set Auto Mode
(Reg[71h] B6 = 0)
Read X,Y-axis
Read Reg [72h]
Enable TP INT
(Reg[8Fh] B6 = 1)
0
Read Reg [73h]
Other
Functions
Cause the
Interrupt
Read Reg [74h]
Clear TP INT Status
..
..
.
(write REG[8Fh] B2 = 1)
Execute Function
Figure 7-71 : Auto-Mode Flowchart for Touch Panel
Table 7-13 : Related Registers for Auto-Mode of T/P Function
Reg.
Bit_Num
TPCR0
TPCR1
INTC
Description
Reference
Bit7
Enable Touch Panel function
REG[70h]
Bit6
“Auto-Mode” or “Manual Mode” selection bit
REG[71h]
Touch Panel Hardware Interrupt setting bit
REG[8Fh]
Bit6
Bit2
TPXH
Bit[7:0]
Touch Panel SEG data MSB byte
REG[72h]
TPYH
Bit[7:0]
Touch Panel COM data MSB byte
REG[73h]
Bit[3:2]
Touch Panel COM data LSB 2bit
Bit[1:0]
Touch Panel SEG data LSB 2bit
TPXYL
7-9-2
REG[74h]
Manual Mode
The “ Manual Mode” means that the operation process from “Touch event checking function” to
“input Latch X data Y data”, the whole operation and setting process ( includes TPCR1[1:0]) and
receiving data from XY coordinates are manual operated by programmer. The advantage of
using Manual Mode is it allows programmer more flexible applications. In the condition that is
over the range of RA8872 register setting, the user can still use the software method to control
the TP function in a correct way.
Touch Event can be detected from “Interrupt Mode” or “Polling Mode” that depend on the system
configuration. The difference between the “Interrupt Mode” and “Polling Mode” are explained as
following.
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
7-9-2-1
External Interrupt Mode
Under the “Interrupt Mode” the touch event detecting way is almost the same as “Auto Mode”.
The major processes are list as follows:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
Enable Touch Panel function. ( REG[70h] Bit7 = 1 )
Change mode to “Manual mode”. （REG[71h] Bit6 = 1）
Set the switch to 「Wait for touch event」. ( REG[71h] Bit[1:0 ]= 01 )
Enable Touch Panel Interrupt. ( REG[8Fh] Bit6 = 1 )
When interrupt asserts, check if TP interrupt.
If yes, change the switch to 「Latch X Data」, Set TPCR1[1:0] to 10b, wait for enough time
to make the latch data stable and latched to TPXH and TPXYL.
Change the switch to 「Latch Y Data」, Set TPCR1[1:0] to 11b, wait for enough time to
make the latch data stable and latched to TPYH and TPXYL.
Change TP mode to “IDLE mode” ( REG[71h] Bit[1:0 ]= 00 )
Read X, Y data from TPXH, TPYH and TPXYL, and clear the interrupt status.
Change TP mode to “Wait for touch event」. ( REG[71h] Bit[1:0 ]= 01 )
Goto Step 6.
Start
ISR
Enable Touch Panel
(Reg[70h] B7 = 1)
Set Manual Mode
(Reg[71h] B6 = 1)
Wait for TP event Mode
(Reg[71h] [1:0] = 01)
Enable TP INT
(Reg[8Fh] B6 = 1)
Ext INT Event
Check INT Status
(Reg[8Fh] B2 = ? )
0
1
Other
Functions
Cause the
Interrupt
Latch X Data
(Reg [71h] [1:0] = 10)
TP IDLE Mode
(Reg[71h] [1:0] = 00)
Delay Time for Data
Stability
Read X,Y – axis
(Reg[72h], Reg[73h], Reg[74h])
Latch Y Data
(Reg [71h] [1:0] = 11)
Execute Function
..
..
.
Clear TP INT Status
(Reg[8Fh] B2 = 1)
Delay Time for Data
Stability
Wait for TP event Mode
(Reg[71h] [1:0] = 01)
Other Functions
Figure 7-72 : T/P Programming Procedure for External Interrupt Mode
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
The registers for Interrupt Mode are explained as below table:
Table 7-14 : Related Registers for External Interrupt Mode
Reg.
Bit_Num
TPCR0
Bit7
Enable Touch Panel Function
Bit6
TP Manual Mode Enable
TPCR1
INTC
Bit[1:0]
Description
Mode selection for TP manual Mode
Bit6
Touch Panel Interrupt Mask
Bit2
Touch Panel Detect Status Bit
Reference
REG[70h]
REG[71h]
REG[8Fh]
TPXH
Bit[7:0]
Touch Panel X Data Bit[9:2] (Segment)
REG[72h]
TPYL
Bit[7:0]
Touch Panel Y Data Bit[9:2] (Common)
REG[73h]
Bit[3:2]
Touch Panel Y Data Bit[1:0] (Common)
Bit[1:0]
Touch Panel X Data Bit[1:0] (Segment)
TPXY
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REG[74h]
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
7-9-2-2
Polling Mode
Under the ”Polling Mode”, users need to decide and set the de-bounce time after the touch
event, as well as the sampling time after latch by considering the real situation, thus more
flexibilities for users apply this mode.
The development procedures are explained as follows:
1.
2.
3.
4.
Enable Touch Panel function.
Change mode to “Manual mode”.
Set the switch to「Wait for Touch Event」, i.e., set TPCR1[1:0] to 01b.
Read Touch Panel Event status from status register, check if the “Touch Event”
happens.
5. When touch event happens, confirm the stability of it and set the switch to 「Latch
X Data」, i.e., TPCR1[1:0] set to 10b, wait for enough time to make the latch data
stable and latched to TPXH and TPXYL.
6. Set the switch to「Latch Y Data」, i.e., TPCR1[1:0] set to 11b, wait for enough time
to make the latch data stable and latched to TPYH and TPXYL.
7. Read X, Y data from TPXH, TPYH and TPXYL, and clear the interrupt status.
Start
Enable Touch Panel
Latch X Data
(REG[70h] B7 = 1)
(REG[71h][1:0] = 10)
Set Auto Mode
Delay Enoug h Time
(REG[71h] B6 = 1)
Latch Y Data
(REG[71h][1:0] = 11)
Wait for TP event Mo de
(REG[71h][1:0] = 01)
Delay Enough Time
Read X,Y - axis
Check TP Event
( Reg [8Fh] B2 = ?)
(Read Reg[72h],
Reg[73h] , Reg[74h])
Check TP Event
valid
E xecute Functi on
invalid
Clear TP INT Status
100 times ?
(Reg[8Fh] B2 = 1)
Other Function
Figure 7-73 : T/P Programming Procedure for the Polling Mode
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
The settings for manual interrupt mode are described in the following table:
Table 7-15 : Related Registers for the Polling Mode
Reg.
Bit_Num
TPCR0
Bit7
Enable Touch Panel function
Bit6
Select operation mode to Auto-mode or Manual-mode.
TPCR1
INTC
Bit[1:0]
Description
The switch of ADC controller for manual mode
Bit6
Touch Panel event(Only activate in TP Manual mode)
Bit2
Touch Panel Detect Status bit
Reference
REG[70h]
REG[71h]
REG[8Fh]
TPXH
Bit[7:0]
Touch Panel X Data Bit[9:2] (Segment)
REG[72h]
TPYH
Bit[7:0]
Touch Panel Y Data Bit[9:2] (Common)
REG[73h]
Bit[3:2]
Touch Panel Y Data Bit[1:0] (Common)
Bit[1:0]
Touch Panel X Data Bit[1:0] (Segment)
TPXYL
REG[74h]
Programmer can check the status of Touch Panel Event from the Bit5 of STSR or Bit2 of
INTC, the difference between those of two methods is described below :
1. The Bit5 of STSR reflects the current Touch status. When touch event occurring, the Bit5 is
set to 1. On the other hand, Bit5 will be automatically cleared to 0 without touch event
occurring. This method is usually used in the polling mode.
2. The Bit2 of INTC records the Touch Panel status. When a touch event is occurring, this bit
will be set to 1. But please take note of this mode, the bit2 of INTC won’t be automatically
cleared to 0 after touch event disappear; it has to clear by programmer. This function is
usually used in the external interrupt mode.
Note: The bit5 of STSR is controlled by ADC circuit directly, once the Touch Panel is touched,
this bit will be set to 1. If the touch event is unstable, it might need a de-bounced
solution to make sure the touch event is valid. The bit5 of STSR is only active at
“Manual mode”. When setting RA8872 to “Auto-mode, the touch event will be
automatically checked. Only the valid touch event will cause the interrupt.
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
7-9-3
Touch Panel Sampling Time Reference Table
When using the auto mode of Touch Panel function, when the Touch Panel function is enabled to
auto mode and the touch event occurring, an extra delay time is needed for ensuring a stable
touch status. It is also recommended to select suitable T/P sampling time due to avoid the ADC
converting error. Please refer to the following table for the ADC sampling time.
Table 7-16 : Touch Panel Sampling Time Reference Table
Touch Panel Sampling Time - REG[70h] Bit[6:4]
SYS_CLK
REG[70h] [2:0]
000
001
010
011
100
101
110
111
10M
20M
30M
40M
50M
000
000
000
001
010
011
100
101
--000
001
010
011
100
101
--000
000
001
010
011
100
---000
001
010
011
100
---000
001
010
011
100
Note: The clock source of ADC can not exceed 10MHz.
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
7-10 PWM
RA8872 provide two set of programmable PWM (Pulse Width Modulation). The PWM frequency and
duty can be set by register. Besides, if the PWM function is disabled, it can use as normal output
signal. The relative function setting please refers to the Table 7-17 as below.
Table 7-17 : PWM Setting
Reg.
Bit_Num
P1CR
P1DCR
P2CR
P2DCR
Description
Bit7
PWM1 Function Enable
Bit6
PWM1 Disable
Bit[3:0]
Clock Source Divide Ratio Select
Bit[7:0]
PWM1 Duty Cycle Select
Bit7
PWM2 Function Enable
Bit6
PWM2 Disable
Bit[3:0]
Clock Source Divide Ratio Select
Bit[7:0]
PWM2 Duty Cycle Select
Reference
REG[8Ah]
REG[8Bh]
REG[8Ch]
REG[8Dh]
The two PWM outputs are independent. Register REG[8Bh] and REG[8Dh] are used to control the
duty of PWM outputs. The normal application is used to control the LED back-light of TFT Panel.
Please refer to Section 6-5 and Figure 6-16 for detail. The following Figure 7-74 and Figure 7-75 are
two examples to show the PWM output.
TPWM
TH
TL
Example-2:
System Clock = 10Mhz,
Register P1CR Bit[3:0] = 0010b Æ Clock Source = 10MHz/4 = 2.5MHz
TPWM = 256*(1/2.5MHz) = 102.4 µs
Register P1DCR Bit[7:0] = 7Fh Æ
TH = 128*(1/2.5MHz) = 51.2µs
TL = (256-128) * (1/ 2.5MHz) = 51.2µs
Figure 7-74 : Example 1 of PWM_OUT Pulse
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
TPWM
TH
TL
Example-1:
System Clock = 10Mhz,
Register P1CR Bit[3:0] = 0001b Æ Clock Source = 10MHz/2 = 5MHz
TPWM = 256*(1/5MHz) = 51.2µs
Register P1DCR Bit[7:0] = 0Fh Æ
TH = 16*(1/5MHz) = 3.2µs
TL = (256-16) * (1/ 5MHz) = 48µs
Figure 7-75 : Example 2 of PWM_OUT Pulse
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
7-11 Sleep Mode
RA8872 provides a Sleep Mode function Provides sleep mode for power saving request. The Sleep
mode stops the system oscillator, DDRAM, Font ROM and ignores external signal in order to
conserve power. But the output status of PWM function is still keeping as register setting.
The device provides two wake-up methods for quitting sleep mode, one is to clear the bit1 of register
[01h] to 0. The other is to set the bit3 of register [70h] to 1 before RA8872 enters the sleep mode, and
then we can quit the sleep mode by touch event occurring.
If wake-up events occur, please do not access RA8872 immediately, because it needs an extra delay
time for ensuring the system oscillator and the PLL is started and stabilized, this delay time takes
about 10ms to resume normal operation.
Table 7-18 : Sleep and Wake-up Mode
Enter Sleep Mode
Wake-up from the Sleep Mode
1. Set REG[01h] Bit1 = 0
Set REG[01h] Bit1 = 1
2. Touch Panel Wake-up (Enable the TP wake-up by
REG[70h] Bit3 first.)
When RA8872 in Sleep mode, the status of output signals are show as Table 7-19.
Table 7-19 : The Signals State of Sleep Mode
S i g na ls
State
WAIT#
High
INT#
High
PWM1, PWM2
Low
GPIO[5:0]
Low
PDAT[15:0]
Low
VSYNC, HSYNC
High
PCLK, DE
High
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
8. AC/DC Characteristic
8-1
Maximum Absolute Limit
Table 8-1 : Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Supply Voltage Range
VDD
3.0V~3.6V
V
Input Voltage Range
VIN
-0.3 to VDD+0.3
V
Power Dissipation
PD
≦80
mW
Operation Temperature Range
TOPR
-30 to +85
℃
Storage Temperature
TST
-45 to +125
℃
TSOLDER
260
℃
Soldering Temperature (10 seconds, Note 1)
Note:
1. The humidity resistance of the flat package may be reduced if the package is immersed in
solder. Use a soldering technique that does not heat stress the package.
2. If the power supply has a high impedance, a large voltage differential can occur between
the input and supply voltages. Take appropriate care with the power supply and the layout
of the supply lines.
3. All supply voltages are referenced to GND = 0V.
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RA8872
Version 1.4
8-2
Character / Graphic TFT LCD Controller
DC Characteristic
Table 8-2 : DC Characteristic Table
Parameter
Symbol
Min.
Typ.
Max.
Unit
Operating Voltage
VDD
ADC_VDD
LDO_VDD
3.0
3.3
3.6
V
LDO Output Voltage
LDO_OUT
1.6
1.8
2.0
V
Add External 1uF
Capacitor
ADC Reference Voltage
ADC_VREF
--
0.5VDD
(±5%)
--
V
Add External 1uF
Capacitor
FIN
--
15
30
MHz
VDD = 3.3 V
SYS_CLK
1
20~30
66
MHz
VDD = 3.3 V
Input High Voltage
VIH
0.8VDD
--
VDD
V
Input Low Voltage
VIL
GND
--
0.2VDD
V
Output High Voltage
VOH
VDD-0.4
--
VDD
V
Output Low Voltage
VOL
GND
--
GND +0.4
V
Input High Voltage
VIH
0.7VDD
--
VDD
V
Input Low Voltage
VIL
GND
--
0.3VDD
V
IIH
--
--
+2
μA
(Note 2)
IIL
--
--
-2
μA
(Note 2)
Operation Current
IOPR
--
25
50
mA
(Note 2)
Sleep Mode
ISLP
--
1.25
--
mA
(Note 2, 3)
Oscillator Clock
PLL Clock
Condition
Input
Output
Schmitt-Trigger Input (Note 1)
Input Leakage
Current 1
Input Leakage
Current 2
Note:
1. Signals RD#, WR#, CS#, RS, RST# are inputs of Schmitt-trigger.
2. Case 2. : VDDP = VDD = 3.3V, Oscillator Clock = 25MHz, System Clock = 25MHz,
Source = 320, Gate = 240, FRM = 60Hz, TA=25℃.
3. The current not include internal LDO power consumption.
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
9. Package
Pin Assignment
NC
VR2
NC
NC
GPIO5
GPIO4
GPIO3
NC
NC
GPIO2
GPIO1
GPIO0
NC
NC
VDD
NC
GND
NC
CORE_VDD
NC
NC
NC
NC
NC
GND
9-1
VR1
VDD
LDO_GND
LDO_VDD
LDO_OUT
HSYNC
VSYNC
PCLK
DE
PDAT0
PDAT1
PDAT2
PDAT3
PDAT4
PDAT5
PDAT6
PDAT7
PDAT8
PDAT9
PDAT10
PDAT11
PDAT12
PDAT13
PDAT14
PDAT15
70
75
65
60
55
50
80
RAiO
85
TM
45
40
RA8872L3N
90
35
1012
95
30
Date code (Year 2010, 12th week)
100
5
10
15
20
25
GND
ADC_VDD
ADC_GND
ADC_VREF
XN
YP
YN
XP
RD#
WR#
CS#
RS
C86
DB0
DB1
GND
CORE_VDD
VDD
DB2
DB3
DB4
DB5
DB6
DB7
LDO_GND
○
GND
NC
NC
NC
NC
NC
NC
NC
TEST2
TEST1
TEST0
NC
RST#
INT#
WAIT#
GND
PWM2
PWM1
VDD
GND
LDO_CAP
XO
XI
LDO_VDD
NC
Figure 9-1 : RA8872 Pin Assignment
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RA8872
Version 1.4
9-2
Character / Graphic TFT LCD Controller
Package Outline
Figure 9-2 : RA8872 Outline Dimensions
9-3 Product Number
The complete product number of RA8872 is “RA8872L3N”, RAiO is dedicated to environmental
protection and Now RAiO has already started to supply customers with environmentally friendly Lead
Free devices in order to reduce or eliminate hazardous substances contained within the packaging.
RAiO guarantees that its product contents will conform to the limitation of European Union materials
restrictions :
„
„
„
The Restriction of Hazardous Substances Directive RoHS (2002/95/EC)
Restriction on Perfluorooctane sulfonates PFOS & PFOA (2006/122/EC)
Registration, Evaluation, Authorisation and restriction of CHemicals REACH (EC
1907/2006)
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
10. Application Circuit
The Figure 10-2 is application circuit of RA8872. It provides the 8-bit MCU interface, and FPC connector
interface for TFT Module. Figure 10-2 also shows the PWM to control back-light power circuit. The
following Figure 10-1 is the block diagram of the application circuit.
USB1
U1
U2
LCD1
RA8872
TFT LCD
Module
Connector
USB I/F
8-Bit
MCU
SD1
SD I/F
TP1
CON1
Mini SD
CON3
4-wires
TP I/F
8-Bit
MCU I/F
CON2
LCD I/F
ISP I/F
Header 20x2
Header 12x2
Header 5x2
U3
DC Input
To RA8872
To MCU
To LCD Module
3.3V
Regulator
U4
Booster
LED Back-Light
(For LCD Module)
Figure 10-1 : Application Circuit Diagram
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
Figure 10-2 : Application Circuit
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
11. Demo Program
RAiO provides the “C” base demo program and related sub-routinethe for end user development. In
addition, the related demo program for RA8872 is also available on our web site, it will help user to speed
up the product development process and improves time to market. Please visit the website
“www.raio.com.tw” or contact with our Distributor for above information. The following programming
example illustrates how to setup and implement RA8872 with the 320x240 pixel digital TFT-LCD panel,
besides, this demo code is based on standard 8051 MCU and used to show a rectangle, a circle and
English string. Please refer to the Figure 11-1.
//#include <stdio.h>
#include <intrins.h>
#include "REG_MPC82G516.H"
//#include "AT89X52.H"
//===== MCU Interface =====
#define Parallel_8080
//set RA8872 pin C86 to GND
//#define Parallel_6800
//set RA8872 pin C86 to VCC
//===== LCD Panel Size =====
#define P320x240
//----------------------------------------------//User Parameter Defines
//----------------------------------------------typedef unsigned char uchar;
typedef unsigned int uint;
typedef unsigned short ushort;
typedef unsigned long ulong;
#define
#define
#define
#define
#define
#define
#define
#define
cSetD0
cSetD1
cSetD2
cSetD3
cSetD4
cSetD5
cSetD6
cSetD7
0x01
0x02
0x04
0x08
0x10
0x20
0x40
0x80
#define
#define
#define
#define
#define
#define
#define
#define
cClrD0
cClrD1
cClrD2
cClrD3
cClrD4
cClrD5
cClrD6
cClrD7
0xfe
0xfd
0xfb
0xf7
0xef
0xdf
0xbf
0x7f
#define cClrD1D0
#define cClrD1SetD0
#define cSetD1ClrD0
#define cSetD1D0
#define cClrD3D2
#define cClrD3SetD2
#define cSetD3ClrD2
#define cSetD3D2
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0xfc
0x01
0x02
0x03
0xf3
0x04
0x08
0x0c
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
#define cClrD2D1D0
#define cClrD2D1SetD0
#define cClrD2SetD1ClrD0
#define cClrD2SetD1D0
#define cSetD2ClrD1D0
#define cSetD2ClrD1SetD0
0xf8
0x01
0x02
0x03
0x04
0x05
#define cClrD6D5D4
#define cClrD6D5SetD4
#define cClrD6SetD5ClrD4
#define cClrD6SetD5D4
#define cSetD6ClrD5D4
#define cSetD6ClrD5SetD4
#define cSetD6D5ClrD4
#define cSetD6D5D4
0x8f
0x10
0x20
0x30
0x40
0x50
0x60
0x70
//===== MCU Interface =====
#ifdef Parallel_8080
#define DATA_BUS
P0 //external pullups 1k~10k
#define RS
P2_0
#define CS
P3_4
#define WR
P3_6
#define RD
P3_7
#define RST
P3_3
#endif
//---------------------------------------------------------//
#ifdef Parallel_6800
#define DATA_BUS P0
//external pullups 1k~10k
#define RS
P2_0//A0
#define CS
P3_4
#define WR
P3_6
#define RD
P3_7// EN
#define RST
P3_3
#endif
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
void Delay2us(uchar Counter)
{ while(--Counter);
}
void Delay100us(uchar Counter)
{ while(Counter--)
{
Delay2us(100);
}
}
void Delay1ms(uchar Counter)
{ while(Counter--)
{
Delay100us(11);
}
}
void Delay10ms(uchar Counter)
{ while(Counter--)
{
Delay1ms(11);
}
}
void Delay100ms(uchar Counter)
{ while(Counter--)
{
Delay1ms(101);
}
}
//----------------------//
void LCD_CmdWrite(uchar cmd)
{
#ifdef Parallel_8080
CS = 0;
RS = 1;
DATA_BUS = cmd;
WR = 0;
WR = 1;
CS = 1;
#endif
#ifdef Parallel_6800
CS = 0;
RS = 1;
WR = 0;
//WRITE
DATA_BUS = cmd;
RD = 1;
//EN
RD = 0;
CS = 1;
#endif
}
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
//----------------------//
void LCD_DataWrite(uchar Data)
{
#ifdef Parallel_8080
CS = 0;
RS = 0;
DATA_BUS = Data;
WR = 0;
WR = 1;
CS = 1;
#endif
#ifdef Parallel_6800
CS = 0;
RS = 0;
WR = 0;
//WRITE
DATA_BUS = Data;
RD = 1;
//EN
RD = 0;
CS = 1;
#endif
}
//----------------------//
uchar LCD_CmdRead(void)
{
uchar Data;
DATA_BUS = 0xff;
#ifdef Parallel_8080
CS = 0;
RS = 1;
RD = 0;
_nop_();
Data = DATA_BUS;
RD = 1;
CS = 1;
#endif
#ifdef Parallel_6800
CS = 0;
RS = 1;
WR = 1;
//READ
RD = 1;
//EN
_nop_();
Data = DATA_BUS;
RD = 0;
CS = 1;
#endif
//DATA_BUS = 0x00;
return Data;
}
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
//----------------------//
uchar LCD_DataRead(void)
{
uchar Data;
DATA_BUS = 0xff;
#ifdef Parallel_8080
CS = 0;
RS = 0;
RD = 0;
_nop_();
Data = DATA_BUS;
RD = 1;
CS = 1;
#endif
#ifdef Parallel_6800
CS = 0;
RS = 0;
WR = 1;
//READ
RD = 1;
//EN
_nop_();
Data = DATA_BUS;
RD = 0;
CS = 1;
//DATA_BUS = 0x00;
#endif
return Data;
}
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
//-----------------------//
uchar LCD_StatusRead(void)
{
uchar Data;
DATA_BUS = 0xff;
#ifdef
Parallel_8080
CS = 0;
RS = 1;
RD = 0;
_nop_();
Data = DATA_BUS;
RD = 1;
CS = 1;
#endif
#ifdef Parallel_6800
CS = 0;
RS = 1;
WR = 1;
//READ
RD = 1;
//EN
_nop_();
Data = DATA_BUS;
RD = 0;
CS = 1;
#endif
//DATA_BUS = 0x00;
return Data;
}
void Chk_Busy(void)
{
do
{
}while((LCD_StatusRead()&0x80)==0x80);
}
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
//-----------------------//
void LCD_Reset(void)
{ RST = 0;
Delay100ms(1);
RST = 1;
Delay100ms(1);
}
//PLL setting for system clock
void RA8870_PLL_ini(void)
{ //Base on crystal = 20MHZ
//system clk = 20*(a+1)/2^2 =55MHZ
LCD_CmdWrite(0x88);
LCD_DataWrite(0x0a);
LCD_CmdWrite(0x89);
LCD_DataWrite(0x02); //
Delay1ms(1);
LCD_CmdWrite(0x01);
LCD_DataWrite(0x01);
LCD_DataWrite(0x00);
Delay100ms(1);
}
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
//------------------------------------------//
void LCD_Initial(void)
{
RA8870_PLL_ini();
LCD_CmdWrite(0x10);
//LCD_DataWrite(0x3C);
//SYSR bit[4:3]=00 256 color bit[2:1]= 00 8bit MPU interface
//
01 4k color
01 12bit
//
1x 64k color
1x 16bit
//external memory
LCD_DataWrite(0x0C); //if set internal memory
//Horizontal set
LCD_CmdWrite(0x14); //HDWR//Horizontal Display Width Setting Bit[6:0]
LCD_DataWrite(0x27); //Horizontal display width(pixels) = (HDWR + 1)*8
LCD_CmdWrite(0x15); //HNDFCR//Horizontal Non-Display Period fine tune Bit[3:0]
LCD_DataWrite(0x02); //(HNDR + 1)*8 +HNDFCR
LCD_CmdWrite(0x16); //HNDR//Horizontal Non-Display Period Bit[4:0]
LCD_DataWrite(0x03); //Horizontal Non-Display Period (pixels) = (HNDR + 1)*8
LCD_CmdWrite(0x17); //HSTR//HSYNC Start Position[4:0]
LCD_DataWrite(0x01); //HSYNC Start Position(PCLK) = (HSTR + 1)*8
LCD_CmdWrite(0x18); //HPWR//HSYNC Polarity ,The period width of HSYNC.
LCD_DataWrite(0x03); //HSYNC Width [4:0] HSYNC Pulse width(PCLK) = (HPWR + 1)*8
//Vertical set
LCD_CmdWrite(0x19); //VDHR0 //Vertical Display Height Bit [7:0]
LCD_DataWrite(0xef); //Vertical pixels = VDHR + 1
LCD_CmdWrite(0x1a); //VDHR1 //Vertical Display Height Bit [8]
LCD_DataWrite(0x00); //Vertical pixels = VDHR + 1
LCD_CmdWrite(0x1b); //VNDR0 //Vertical Non-Display Period Bit [7:0]
LCD_DataWrite(0x0F); //Vertical Non-Display area = (VNDR + 1)
LCD_CmdWrite(0x1c); //VNDR1 //Vertical Non-Display Period Bit [8]
LCD_DataWrite(0x00); //Vertical Non-Display area = (VNDR + 1)
LCD_CmdWrite(0x1d); //VSTR0 //VSYNC Start Position[7:0]
LCD_DataWrite(0x0e); //VSYNC Start Position(PCLK) = (VSTR + 1)
LCD_CmdWrite(0x1e); //VSTR1 //VSYNC Start Position[8]
LCD_DataWrite(0x06); //VSYNC Start Position(PCLK) = (VSTR + 1)
LCD_CmdWrite(0x1f); //VPWR //VSYNC Polarity ,VSYNC Pulse Width[6:0]
LCD_DataWrite(0x01); //VSYNC Pulse Width(PCLK) = (VPWR + 1)
LCD_CmdWrite(0x04); //setting PCLK = 55MHZ /4/2 = 6.875MHZ
LCD_DataWrite(0x01);
//LCD_CmdWrite(0x28); //if use external font ROM (Speed setting)
//LCD_DataWrite(0x02);
}
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
void Active_Window(uint XL,uint XR ,uint YT ,uint YB)
{
//setting active window X
LCD_CmdWrite(0x30);//HSAW0
LCD_DataWrite(XL);
LCD_CmdWrite(0x31);//HSAW1
LCD_DataWrite(XL>>8);
LCD_CmdWrite(0x34);//HEAW0
LCD_DataWrite(XR);
LCD_CmdWrite(0x35);//HEAW1
LCD_DataWrite(XR>>8);
//setting active window Y
LCD_CmdWrite(0x32);//VSAW0
LCD_DataWrite(YT);
LCD_CmdWrite(0x33);//VSAW1
LCD_DataWrite(YT>>8);
LCD_CmdWrite(0x36);//VEAW0
LCD_DataWrite(YB);
LCD_CmdWrite(0x37);//VEAW1
LCD_DataWrite(YB>>8);
}
//--------------------------//
void XY_Coordinate(uint X,uint Y)
{
LCD_CmdWrite(0x46);
LCD_DataWrite(X);
LCD_CmdWrite(0x47);
LCD_DataWrite(X>>8);
LCD_CmdWrite(0x48);
LCD_DataWrite(Y);
LCD_CmdWrite(0x49);
LCD_DataWrite(Y>>8);
}
void Memory_Clear(void)
{
uchar temp;
LCD_CmdWrite(0x8e);//MCLR
temp = LCD_DataRead();
temp |= cSetD7 ;
LCD_DataWrite(temp);
}
void Text_Foreground_Color(uchar color)
{
LCD_CmdWrite(0x42);//TFCR
LCD_DataWrite(color);
}
void Text_Background_Color(uchar color)
{
LCD_CmdWrite(0x43);//TBCR
LCD_DataWrite(color);
}
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
//=========================================================
//REG[8Ah] PWM1 Control Register (P1CR)
//=========================================================
void PWM1_enable(void)
{
uchar temp;
LCD_CmdWrite(0x8a);//MCLR
temp = LCD_DataRead();
temp |= cSetD7 ;
LCD_DataWrite(temp);
}
void PWM1_disable(void)
{
uchar temp;
LCD_CmdWrite(0x8a);//MCLR
temp = LCD_DataRead();
temp &= cClrD7 ;
LCD_DataWrite(temp);
}
void PWM1_disable_level_low(void)
{
uchar temp;
LCD_CmdWrite(0x8a);//MCLR
temp = LCD_DataRead();
temp &= cClrD6 ;
LCD_DataWrite(temp);
}
void PWM1_disable_level_high(void)
{
uchar temp;
LCD_CmdWrite(0x8a);//MCLR
temp = LCD_DataRead();
temp &= cSetD6 ;
LCD_DataWrite(temp);
}
void PWM1_fnuction_sel(void)
{
uchar temp;
LCD_CmdWrite(0x8a);//MCLR
temp = LCD_DataRead();
temp &= cClrD4 ;
LCD_DataWrite(temp);
}
void PWM1_clock_ratio(uchar setx) //bit0~3
{
uchar temp,temp1;
temp1= setx&0x0f;
LCD_CmdWrite(0x8a);//MCLR
temp = LCD_DataRead();
temp &= 0xf0;
temp |= temp1 ;
LCD_DataWrite(temp);
}
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
//=========================================================
//REG[8Bh] PWM1 Duty Cycle Register (P1DCR)
//=========================================================
void PWM1_duty_cycle(uchar setx) //bit0~7
{
LCD_CmdWrite(0x8b);//PTNO
LCD_DataWrite(setx);
}
void Memory_Clear_with_Font_BgColor(void)
{
uchar temp;
LCD_CmdWrite(0x8e);//MCLR
temp = LCD_DataRead();
temp |= cSetD0 ;
LCD_DataWrite(temp);
}
void Geometric_Coordinate(uint XL,uint XR ,uint YT ,uint YB)//
{
LCD_CmdWrite(0x91);
LCD_DataWrite(XL);
LCD_CmdWrite(0x92);
LCD_DataWrite(XL>>8);
LCD_CmdWrite(0x95);
LCD_DataWrite(XR);
LCD_CmdWrite(0x96);
LCD_DataWrite(XR>>8);
LCD_CmdWrite(0x93);
LCD_DataWrite(YT);
LCD_CmdWrite(0x94);
LCD_DataWrite(YT>>8);
LCD_CmdWrite(0x97);
LCD_DataWrite(YB);
LCD_CmdWrite(0x98);
LCD_DataWrite(YB>>8);
}
void Circle_Coordinate_Radius(uint X,uint Y,uint R)
{
LCD_CmdWrite(0x99);
LCD_DataWrite(X);
LCD_CmdWrite(0x9a);
LCD_DataWrite(X>>8);
LCD_CmdWrite(0x9b);
LCD_DataWrite(Y);
LCD_CmdWrite(0x9c);
LCD_DataWrite(Y>>8);
LCD_CmdWrite(0x9d);
LCD_DataWrite(R);
}
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
void Text_Mode(void)
{
uchar temp;
LCD_CmdWrite(0x40);//MWCR0
temp = LCD_DataRead();
temp |= cSetD7 ;
LCD_DataWrite(temp);
}
void Show_String(uchar *str,uint n)
{
LCD_CmdWrite(0x02);
while(*str != '\0')
{
LCD_DataWrite(*str);
++str;
Chk_Busy();
}
Delay1ms(n);
}
//================== main process start ==================//
void main(void)
{
P0 = 0xff;
P1 = 0xff;
P2 = 0xff;
#ifdef Parallel_8080
P3 = 0xff;
#endif
#ifdef Parallel_6800
P3 = 0x77;
#endif
LCD_Reset();
LCD_Initial();
Active_Window(0,319,0,239);
Memory_Clear_with_Font_BgColor();
Text_Background_Color(0xfc);
Memory_Clear();
Chk_Busy();
//******************
LCD_CmdWrite(0x01);
LCD_DataWrite(0x80);
//******************
//display on
//----PWM initial for Backlight add by mountain
PWM1_enable();
PWM1_fnuction_sel();
PWM1_clock_ratio(0x08); //bit0~3
for 3.5"TFT RA8872 DEMO BOARD VER:1.1
//PWM1_duty_cycle(0x80);//半亮
PWM1_duty_cycle(0xff); // 全亮 ( backlight ON)
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
while(1)
{
Text_Foreground_Color(0xe0);// set draw color red
Geometric_Coordinate(0,319,0,239); //
LCD_CmdWrite(0x90);
LCD_DataWrite(0x90); //enable draw square
Chk_Busy();
Text_Foreground_Color(0x1c); // set draw color green
Circle_Coordinate_Radius(160,120,100);
LCD_CmdWrite(0x90);
LCD_DataWrite(0x60); //enable draw circle and fill
Chk_Busy();
Text_Foreground_Color(0x02); // set color blue
Text_Mode();
XY_Coordinate(140,110);
LCD_CmdWrite(0x02);
Show_String("RAiO",0);
while(1);
}
}
RAIO
Figure 11-1 : Display Pattern for Above Demo Program
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
12. Summary of Register Table
System and Configuration Registers
REG
Name
DB7
DB6
DB5
DB4
00h
PCOD
0
1
1
1
01h
PWRR
LCD_EN
02h
MRWC
D7
04h
PCLK
CK_INV
10h
SYSR
0
11h
DRGB
NA
12h
IOCR
0
13h
IODR
14h
HDWR
NA
15h
HNDFTR
DE_P
16h
HNDR
NA
HNDR[4:0]
LCD Horizontal Non-Display Period Register.
17h
HSTR
NA
HSTR[4:0]
HSYNC Start Position Register.
18h
HPWR
HS_P
VPWR[4:0]
HSYNC PWM Register.
19h
VDHR0
D7
1Ah
VDHR1
1Bh
VNDR0
1Ch
VNDR1
1Dh
VSTR0
1Eh
VSTR1
1Fh
VPWR
RAiO TECHNOLOGY INC.
DB3 DB2
0
D5
DB0
0
0
0
NA
D6
DB1
SL_EN RST_EN
D4
D3
D2
D1
NA
PAR_S
0
0
CLS_S[1:0]
RGB_OSQ[2:0]
NA
NA
System Configuration Register.
D5
GPIO Data Register.
LCD Horizontal Display Width Register.
D6
D5
D3
D2
D1
D5
D4
D3
D2
D1
D0
D8
D4
D3
D2
D1
D0
D8
NA
VS_P
D0
D8
NA
D6
Horizontal Non-Display Period Fine Tuning Option Register.
HNDFTR[4:0]
D4
Panel Data Type Register.
GPIO Configure Register.
NA
D7
0
HDWR[6:0]
D6
Memory Read / Write Command.
0
IO_DATA[5:0]
NA
Power and Display Controller Register.
Pixel Clock Register.
RGB_ESQ[2:0]
NA
Product Code Register.
PPWS[1:0]
IO_OE[5:0]
NA
D7
D0
Description
LCD Vertical Display Height Register.
LCD Vertical Non-Display Period Register.
VSYNC Start Position Register.
VSYNC PWM Register.
VPWR[6:0]
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RA8872
Version 1.4
Character / Graphic TFT LCD Controller
LCD Display Control Registers
REG
Name
DB7
20h
DPCR
LAYER
21h
FNCR0
FT_S
22h
FNCR1
23h
CGSR
D7
D6
D5
D4
D3
D2
D1
D0
24h
HOFS0
D7
D6
D5
D4
D3
D2
D1
D0
25h
HOFS1
D9
D8
26h
VOFS0
D1
D0
27h
VOFS1
29h
FLDR
RAiO TECHNOLOGY INC.
DB6
DB5
DB4
NA
0
0
TX_AL TX_TM BOLD
1
TX_RT
DB3
DB2
DB1
HDIR
VDIR
ROT[1:0]
0
0
ISO8859[1:0]
Font Control Register 0.
TX_V[1:0]
Font Control Register 1.
TX_H[1:0]
NA
D7
D6
D5
D4
D3
D2
D8
NA
NA
DB0
TX_DIST[4:0]
148/154
Description
Display Configuration Register.
CGRAM Select Register.
Horizontal Scroll Offset Register.
Vertical Scroll Offset Register.
Font Line Distance Setting Register.
www.raio.com.tw
RA8872
Version 1.4
Character / Graphic TFT LCD Controller
Active Window Setting Registers
REG
Name
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
30h
HSAW0
D7
D6
D5
D4
D3
D2
D1
D0
31h
HSAW1
D9
D8
32h
VSAW0
D1
D0
33h
VSAW1
34h
HEAW0
35h
HEAW1
36h
VEAW0
37h
VEAW1
38h
HSSW0
39h
HSSW1
3Ah
VSSW0
3Bh
VSSW1
3Ch
HESW0
3Dh
HESW1
3Eh
VESW0
3Fh
VESW1
RAiO TECHNOLOGY INC.
NA
D7
D6
D5
D4
D3
D2
D8
NA
D7
D6
D5
D4
D3
D2
NA
D7
D6
D5
D4
D3
D2
D1
D0
D9
D8
D1
D0
D8
NA
D7
D6
D5
D4
D3
D2
NA
D7
D6
D5
D4
D3
D2
D1
D0
D9
D8
D1
D0
D8
NA
D7
D6
D5
D4
D3
D2
NA
D7
D6
D5
D4
D3
D2
D1
D0
D9
D8
D1
D0
D8
NA
149/154
Description
Horizontal Start Point of Active Window.
Vertical Start Point of Active Window.
Horizontal End Point of Active Window.
Vertical End Point of Active Window.
Horizontal Start Point of Scroll Window.
Vertical Start Point of Scroll Window.
Horizontal End Point of Scroll Window.
Vertical End Point of Scroll Window.
www.raio.com.tw
RA8872
Version 1.4
Character / Graphic TFT LCD Controller
Cursor Setting Registers
REG
Name
40h
MWCR0
TX_MD TX_CR CR_BK
41h
MWCR1
GR_CR
42h
TFCR
R2
R1
R0
43h
TBCR
R2
R1
44h
BTCR
D7
D6
45h
CURS
46h
CURH0
47h
CURH1
48h
CURV0
49h
CURV1
4Ah
RCURH0
4Bh
RCURH01
4Ch
RCURV0
4Dh
RCURV1
4Eh
MRCD
RAiO TECHNOLOGY INC.
DB7
DB6
DB5
DB4
DB3
D6
NA
WR_L
Memory Write Control Register 1.
G2
G1
G0
B1
B0
Text Foreground Color Register.
R0
G2
G1
G0
B1
B0
Text Background Color Register.
D5
D4
D3
D2
D1
D0
Blink Time Control Register.
D5
D5
D6
D5
D4
D3
D2
D4
D3
D2
D1
D0
D9
D8
D1
D0
D8
D4
D3
D2
NA
D7
D6
D5
D4
D3
D2
D1
D0
D9
D8
D1
D0
D8
NA
NA
Text Cursor Size Register.
TCUR_V[3:0]
NA
D7
Description
WR_DS[1:0]
NA
D7
DB0
Memory Write Control Register 0.
GRCR_S[2:0]
D6
DB1
MWR_D[1:0] WRC+1 RDC+1
NA
TCUR_H[3:0]
D7
DB2
MRD_D[1:0]
150/154
Memory Write Cursor Horizontal Position Register.
Memory Write Cursor Vertical Position Register.
Memory Read Cursor Horizontal Position Register.
Memory Read Cursor Vertical Position Register.
Memory Read Cursor Direction.
www.raio.com.tw
RA8872
Version 1.4
Character / Graphic TFT LCD Controller
BTE Control Registers
REG
Name
50h
BECR0
51h
BECR1
52h
LTPR0
53h
LTPR1
54h
HSBE0
55h
HSBE1
56h
VSBE0
D7
57h
VSBE1
D7
58h
HDBE0
D7
59h
HDBE1
5Ah
VDBE0
D7
5Bh
VDBE1
BTE_L
5Ch
BEWR0
D7
5Dh
BEWR1
5Eh
BEHR0
5Fh
BEHR1
60h
BGCR0
61h
BGCR1
62h
BGCR2
NA
BC_BLUE[4:0]
BTE Background Color Register – BLUE.
63h
FGCR0
NA
FC_RED[4:0]
BTE Foreground Color Register – RED.
64h
FGCR1
65h
FGCR2
NA
66h
PTNO
NA
67h
BGTR
RAiO TECHNOLOGY INC.
DB7
DB6
DB5
BTE_EN BM_S
BM_D
DB4
DB3
ROP_CD[3:0]
SC_MD[1:0]
D6
D5
DB1
OP_CD[3:0]
BTE Function Control Register 1.
D5
D3
D4
D5
D2
D3
D2
D4
D3
D2
D5
D4
D3
D2
D0
D9
D8
D1
D0
D6
D7
D1
D0
D9
D8
D1
D0
D8
NA
D5
D4
D3
D2
NA
D6
D5
D4
D3
D2
NA
NA
D1
D0
D9
D8
D1
D0
D9
D8
Vertical Destination Point of BTE .
BTE Width Register.
BTE Height Register.
BTE Foreground Color Register – BLUE.
FC_BLUE[4:0]
R0
Horizontal Destination Point of BTE.
BTE Foreground Color Register – GREEN.
FC_GREEN[5:0]
R1
Vertical Source Point of BTE.
BTE Background Color Register – GREEN.
BC_GREEN[5:0]
NA
Horizontal Source Point of BTE.
BTE Background Color Register – RED.
BC_RED[4:0]
NA
R2
D1
D9
NA
D6
Layer Transparency Register 1.
TRAN_L1[3:0]
NA
D6
Layer Transparency Register 0.
LY_SEL[2:0]
D4
Description
BTE Function Control Register 0.
NA
D6
DB0
NA
NA
TRAN_L2[3:0]
D7
DB2
D4
D3
D2
D1
D0
Pattern Set Number for BTE.
G2
G1
G0
B1
B0
Background Color Register for Transparent.
151/154
www.raio.com.tw
RA8872
Version 1.4
Character / Graphic TFT LCD Controller
Touch Panel Control Registers
REG
Name
DB7
DB6
DB5
DB4
70h
TPCR0
TP_EN
71h
TPCR1
1
72h
TPXH
XD9
XD8
XD7
XD6
XD5
XD4
XD3
XD2
Touch Panel X High Byte Data Register.
73h
TPYH
YD9
YD8
YD7
YD6
YD5
YD4
YD3
YD2
Touch Panel Y High Byte Data Register.
74h
TPXYL
ADET
YD1
YD0
XD1
XD0
Touch Panel Segment / Common Low Byte Data Register.
TP_TM[2:0]
DB3
DB2
NA
NA
DB0
Description
TP_CK[2:0]
Touch Panel Control Register 0.
DB_EN TP_MMD[1:0]
Touch Panel Control Register 1.
TP_WK
TP_MD VREF
DB1
Graphic Cursor Setting Registers
REG
Name
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
80h
GCHP0
D7
D6
D5
D4
D3
D2
D1
D0
81h
GCHP1
D9
D8
82h
GCVP0
D1
D0
83h
GCVP1
84h
GCC0
R2
R1
R0
G2
G1
G0
B1
B0
Graphic Cursor Color Selection – 0.
85h
GCC1
R2
R1
R0
G2
G1
G0
B1
B0
Graphic Cursor Color Selection – 1.
DB6
DB5
DB4
DB3
DB2
DB1
DB0
NA
D7
D6
D5
D4
D3
D2
D8
NA
Description
Graphic Cursor Horizontal Position Register.
Graphic Cursor Vertical Position Register.
PLL Setting Registers
REG
Name
DB7
88h
PLLC0
PL_DV
89h
PLLC1
RAiO TECHNOLOGY INC.
NA
PLLDIVN[4:0]
NA
PLLDIVK[2:0]
152/154
Description
PLL Control Register 0.
PLL Control Register 1.
www.raio.com.tw
RA8872
Version 1.4
Character / Graphic TFT LCD Controller
PWM Control Registers
REG
Name
DB7
DB6
8Ah
P1CR
8Bh
P1DCR
8Ch
P2CR
8Dh
P2DCR
D7
D6
8Eh
MCLR
D7
D6
8Fh
INTC
NA
D6
D5
D4
NA
D2
DB6
DB5
DB4
DB3
DB2
P1_EN P1_P
D7
D6
P2_EN P2_P
DB5
DB4
NA
P1_S
D5
D4
NA
P2_S
D5
D4
DB3
DB2
DB1
DB0
PWM1 Control Register.
PWM1_CK[3:0]
D3
D2
D1
D0
D2
D1
PWM1 Duty Cycle Register.
PWM2 Control Register.
PWM2_CK[3:0]
D3
Description
D0
PWM2 Control Register.
D0
Memory Clear Control Register.
D1
D0
Interrupt Control Register.
DB1
DB0
NA
Drawing Control Registers
REG
Name
90h
DCR
91h
DLHSR0
92h
DLHSR1
93h
DLVSR0
94h
DLVSR1
95h
DLHER0
96h
DLHER1
97h
DLVER0
98h
DLVER1
99h
DCHR0
9Ah
DCHR1
9Bh
DCVR0
9Ch
DCVR1
9Dh
DCRR
RAiO TECHNOLOGY INC.
DB7
DL_ST DC_ST FL_EN DL_EN
D7
D6
D5
D4
D2
NA
D7
D6
D5
D4
Draw Line/Circle / Square Control Register.
NA
D3
D3
D2
D1
D0
D9
D8
D1
D0
D8
NA
D7
D6
D5
D4
D3
D2
NA
D7
D6
D5
D4
D3
D2
D1
D0
D9
D8
D1
D0
D8
NA
D7
D6
D5
D4
D3
D2
NA
D7
D6
D5
D4
D3
D2
D1
D0
D9
D8
D1
D0
D8
NA
D7
D6
D5
D4
D3
D2
Description
D1
153/154
D0
Draw Line / Square Horizontal Start Address Register.
Draw Line / Square Vertical Start Address Register.
Draw Line / Square Horizontal End Address Register.
Draw Line / Square Vertical End Address Register.
Draw Circle Center Horizontal Address Register.
Draw Circle Center Vertical Address Register.
Draw Circle Radius Register.
www.raio.com.tw
RA8872
Version 1.4
RAiO TECHNOLOGY INC.
Character / Graphic TFT LCD Controller
154/154
www.raio.com.tw