RAiO RA8835A Dot Matrix LCD Controller Specification Version 1.3 June 06, 2008 RAiO Technology Inc. ©Copyright RAiO Technology Inc. 2006, 2007, 2008 RAiO TECHNOLOGY INC. 1/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller Update History Version Date 0.9 1.0 February 7, 2007 1.1 December 17, 2007 Description Preliminary version First Release Update Section 10-3-3 Display Memory Read Timing, the clock period of “EXT Φ0”. Update Section 7-8 “Reset” – The minimum timing requirement 1.2 January 16, 2008 1.3 June 6, 2008 RAiO TECHNOLOGY INC. for the following the rising edges of both RES and VDD to allow for system stabilization. Note: The specification of this version is for RA8835AP3N and RA8835AP4N. Update Section 10-3-7 “LCD Output Timing” and Parameters 2/88 www.raio.com.tw RA8835A Version 1.3 Chapter Dot Matrix LCD Controller Contents Pages 1. Overview .........................................................................................................6 2. Features ..........................................................................................................6 3. Block Diagram................................................................................................6 4. Package ..........................................................................................................7 5. Pin Descriptions.............................................................................................7 5-1 Pin Functions ................................................................................................................7 5-1-1 MCU Interface .......................................................................................................................................7 5-1-2 Display Memory Control ......................................................................................................................8 5-1-3 LCD Drive Signals ................................................................................................................................9 5-1-4 Oscillator and Power............................................................................................................................9 5-2 RA8835A Pin Summary...............................................................................................10 6. Instruction Set..............................................................................................11 6-1 The Command Set.......................................................................................................11 6-2 System Control Commands .......................................................................................12 6-2-1 SYSTEM SET...................................................................................................................................... 12 6-2-2 SLEEP IN ............................................................................................................................................ 20 6-3 Display Control Commands .......................................................................................21 6-3-1 DISP ON/OFF...................................................................................................................................... 21 6-3-2 SCROLL.............................................................................................................................................. 23 6-3-3 CSRFORM .......................................................................................................................................... 27 6-3-4 CSRDIR............................................................................................................................................... 28 6-3-5 OVLAY ................................................................................................................................................ 29 6-3-6 CGRAM ADR ...................................................................................................................................... 30 6-3-7 HDOT SCR.......................................................................................................................................... 31 6-4 Drawing Control Commands......................................................................................32 6-4-1 CSRW.................................................................................................................................................. 32 6-4-2 CSRR .................................................................................................................................................. 32 6-5 Memory Control Commands ......................................................................................33 6-5-1 MWRITE .............................................................................................................................................. 33 6-5-2 MREAD ............................................................................................................................................... 33 7. Functions Description .................................................................................34 7-1 MCU Bus Interface ......................................................................................................34 7-1-1 8080 Series......................................................................................................................................... 34 7-1-2 6800 Series......................................................................................................................................... 34 7-2 MCU Synchronization .................................................................................................34 7-2-1 Display Status Indication Output..................................................................................................... 34 7-2-2 Internal Register Access .................................................................................................................. 35 7-2-3 Display Memory Access ................................................................................................................... 35 7-3 MCU Interface Examples ............................................................................................36 7-3-1 Z80 to RA8835A Interface ................................................................................................................. 36 RAiO TECHNOLOGY INC. 3/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 7-3-2 6802 to RA8835A Interface ............................................................................................................... 36 7-4 Static RAM ...................................................................................................................37 7-5 Supply Current during Display Memory Access ......................................................37 7-6 Oscillator Circuit .........................................................................................................38 7-7 Status Flag...................................................................................................................38 7-8 Reset ............................................................................................................................40 7-9 Character Configuration.............................................................................................40 7-10 Screen Configuration................................................................................................41 7-10-1 Screen Configuration...................................................................................................................... 41 7-10-2 Display Address Scanning ............................................................................................................. 42 7-10-3 Display Scan Timing ....................................................................................................................... 44 7-11 Cursor Control...........................................................................................................45 7-11-1 Cursor Register Function ............................................................................................................... 45 7-11-2 Cursor Movement ............................................................................................................................ 45 7-11-3 Cursor Display Layers .................................................................................................................... 45 7-12 Memory to Display Relationship..............................................................................47 7-13 Scrolling.....................................................................................................................50 7-13-1 On-page Scrolling ........................................................................................................................... 50 7-13-2 Inter-page Scrolling......................................................................................................................... 50 7-13-3 Horizontal Scrolling ........................................................................................................................ 51 7-13-4 Bi-directional Scrolling ................................................................................................................... 51 7-13-5 Scroll Units....................................................................................................................................... 52 7-14 CG Characteristics....................................................................................................52 7-14-1 Internal Character Generator ......................................................................................................... 52 7-14-2 External Character Generator ROM............................................................................................... 52 7-14-3 Character Generator RAM .............................................................................................................. 52 7-15 CG Memory Allocation..............................................................................................53 7-16 Setting Character Generator Address.....................................................................54 7-16-1 M1 = 1................................................................................................................................................ 54 7-16-2 CG RAM Addressing Example ....................................................................................................... 55 7-17 Character Codes .......................................................................................................56 8. Application Notes ........................................................................................57 8-1 Initialization Parameters.............................................................................................57 8-1-1 System Set Instruction and Parameters ......................................................................................... 57 8-1-2 Initialization Example........................................................................................................................ 59 8-1-3 Display Mode Setting Example 1: combining text and graphics.................................................. 64 8-1-4 Display Mode Setting Example 2: combining graphics and graphics ......................................... 65 8-1-5 Display Mode Setting Example 3: combining three graphics layers ........................................... 66 8-2 System Overview ........................................................................................................68 8-3 System Interconnection .............................................................................................69 8-4 Smooth Horizontal Scrolling ......................................................................................71 8-5 Layered Display Attributes.........................................................................................72 RAiO TECHNOLOGY INC. 4/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 8-5-1 Inverse Display .................................................................................................................................. 72 8-5-2 Half-tone Display ............................................................................................................................... 73 8-5-3 Flashing Area..................................................................................................................................... 73 8-6 16 x 16-dot Graphic Display .......................................................................................74 8-6-1 Command Usage ............................................................................................................................... 74 8-6-2 Kanji Character Display .................................................................................................................... 74 8-7 Internal Character Generator Font.............................................................................76 9. Package Dimensions ...................................................................................77 10. Specifications.............................................................................................78 10-1 Absolute Maximum Ratings .....................................................................................78 10-2 DC Characteristic ......................................................................................................79 10-3 Timing Diagrams .......................................................................................................81 10-3-1 8080 Family Interface Timing ......................................................................................................... 81 10-3-2 6800 Family Interface Timing ......................................................................................................... 82 10-3-3 Display Memory Read Timing ........................................................................................................ 83 10.3-4 Display Memory Write Timing ........................................................................................................ 84 10-3-5 Sleep In Command Timing ............................................................................................................. 85 10-3-6 External Oscillator Signal Timing .................................................................................................. 86 10-3-7 LCD Output Timing ......................................................................................................................... 87 RAiO TECHNOLOGY INC. 5/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 1. Overview The RA8835A is a controller IC that can display text and graphics on LCD panel. It can display layered text and graphics, scroll the display in any direction and partition the display into multiple screens. It also stores text, character codes and bitmapped graphics data in external frame buffer memory. Display controller functions include transferring data from the controlling microprocessor to the buffer memory, reading memory data, converting data to display pixels and generating timing signals for the buffer memory, LCD panel. The RA8835A has an internal character generator with 160, 5x7 pixel characters in internal mask ROM. The character generators support up to 64, 8x16 pixel characters in external character generator RAM and up to 256, 8x16 pixel characters in external character generator ROM. 2. Features Text, graphics and combined text/graphics display modes Three overlapping screens in graphics mode Up to 640x256 pixel LCD panel display resolution Programmable cursor control Smooth horizontal and vertical scrolling of all or part of the display 1/2-duty to 1/256-duty LCD drive Up to 640x256 pixel LCD panel display resolution memory 160, 5x7 pixel characters in internal maskprogrammed character generator ROM Up to 64, 8x16 pixel characters in external character generator RAM Up to 256, 8x16 pixel characters in external character generator ROM 6800 and 8080 family microprocessor interfaces Low power consumption: 3.5mA operating current (VDD = 3.5V), 0.05μA standby current Package(ROHS Compliance): RA8835AP3N: QFP-60 pin RA8835AP4N: TQFP-60 pin Power: 2.7 to 5.5 V 3. Block Diagram V A [1 5 :0 ], V D [7 :0 ], TE S T V C E , V R D , V W R 2 5 6 B y te C G R O M D is p la y R A M I/F S y s te m C o n fig u r e R e g is te r s B lo c k C u rs o r C o n t r o lle r D a ta L a tc h M C U I/F X ’ta l O S C T im in g G e n e ra to r D [7 :0 ], C S , R D , W R X D A 0, R E S , S E L1, S E L2 X G Y D IS , L P , W F , X S C L , Y D , Y S C L , X D [3 :0 ] Figure 3-1: Block Diagram RAiO TECHNOLOGY INC. 6/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller XG SEL1 SEL2 WR RD NC NC RES VRD VCE VWR VA0 VA1 VA2 VA3 VA4 VA5 VA6 VA7 VD4 VD5 VD6 VD7 YSCL YD YDIS WF LP GND XSCL SECL XD0 XD1 XD2 4. Package 45 XD CS A0 VDD D0 D1 D2 D3 D4 D5 D6 50 45 RAiO 40 35 TM 30 60 RA8835AP3N 1 29 07xx Index 25 Date Code(Year 2007) 5 10 15 20 NC VA14 VA15 VD0 VD1 VD2 VD3 VD2 VD1 VD0 VA15 VA14 VA13 VA12 VA11 VA10 VA9 VA8 VA7 VA6 NC 31 30 46 RAiO XD3 D7 D6 D5 D4 D3 D2 D1 D0 VDD A0 CS XD XG SEL1 TM RA8835AP4N 07xx Index 60 Date Code(Year 2007) 16 15 1 VA5 VA4 VA3 VA2 VA1 VA0 VWR VCE VRD RES NC NC RD WR SEL2 D7 XD3 XD2 XD1 XD0 XECL XSCL GND LP WF YDIS YD YSCL VD7 VD6 VD5 VD4 VD3 6 VA8 VA9 VA10 VA11 VA12 VA13 Figure 4-1: RA8835AP3N(QFP-60 Pin) Figure 4-2: RA8835AP4N (TQFP-60 Pin) 5. Pin Descriptions 5-1 Pin Functions 5-1-1 MCU Interface Pin Name D0 to D7 Function MCU Data Bus. Tristate input/output pins. Connect these pins to an 8- or 16-bit microprocessor bus. MCU Interface Select. The RA8835A series supports both 8080 family processors (such as the 8085 and Z80®) and 6800 family processors (such as the 6802 and 6809). SEL1, SEL2 SEL1 SEL2* Interface A0 RD WR CS 0 0 8080 family A0 RD WR CS 1 0 6800 family A0 E R/ W CS SEL1 should be tied directly to VDD or VSS to prevent noise. If noise does appear on SEL1, decouple it to ground using a capacitor placed as close to the pin as possible. RD or E Read Control or Enable. When the 8080 family interface is selected, this signal acts as the active-LOW read strobe. The RA8835A series output buffers are enabled when this signal is active. When the 6800 family interface is selected, this signal acts as the active-HIGH enable clock. Data is read from or written to the RA8835A series when this clock goes HIGH. RAiO TECHNOLOGY INC. 7/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller WR or R/ W CS Write Control or Read/Write Control. When the 8080 family interface is selected, this signal acts as the active-LOW write strobe. The bus data is latched on the rising edge of this signal. When the 6800 family interface is selected, this signal acts as the read/write control signal. Data is read from the RA8835A series if this signal is HIGH, and written to the RA8835A series if it is LOW. Chip Select. This active-LOW input enables the RA8835A series. It is usually connected to the output of an address decoder device that maps the RA8835A series into the memory space of the controlling microprocessor. Command/Data Select. 8080 Family Interface: A0 0 1 0 1 A0 RD 0 0 1 1 WR 1 1 0 0 Function Status flag read Display data and cursor address read Display data and parameter write Command write E 1 1 1 1 Function Status flag read Display data and cursor address read Display data and parameter write Command write 6800 Family Interface: A0 0 1 0 1 RES R/ W 1 1 0 0 Hardware Reset. This active-LOW input performs a hardware reset on the RA8835A series. It is an Schmitt-trigger input for enhanced noise immunity; however, care should be taken to ensure that it is not triggered if the supply voltage is lowered. 5-1-2 Display Memory Control The RA8835A series can directly access static RAM and PROM. The designer may use a mixture of these two types of memory to achieve an optimum trade-off between low cost and low power consumption. Pin Name VA0 to VA15 VD0 to VD7 VWR VRD VCE Function 16-bit Display Memory Address. When accessing character generator RAM or ROM, VA0 to VA3, reflect the lower 4 bits of the RA8835A series’ row counter. Display Memory Data Bus. 8-bit tristate display memory data bus. These pins are enabled when VR/ W is LOW. Display Memory Write Control. Active-LOW display memory write control output. Display Memory Read Control. Active-LOW display memory read control output. Display Memory Chip Select. Active-LOW static memory standby control signal. VCE can be used with CS . RAiO TECHNOLOGY INC. 8/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 5-1-3 LCD Drive Signals In order to provide effective low-power drive for LCD matrixes, the RA8835A series can directly control both the X- and Y-drivers using an enable chain. Pin Name XD0 to XD3 XSCL XECL LP WF YSCL YD YDIS Function Data Output for Driver. 4-bit X-driver (column drive) data outputs. Connect these outputs to the inputs of the X-driver chips. Latch Clock. The falling edge of XSCL latches the data on XD0 to XD3 into the input shift registers of the X-drivers. To conserve power, this clock halts between LP and the start of the following display line (See Section 10-3-7). Trigger Clock for Chain Cascade. The falling edge of XECL triggers the enable chain cascade for the X-drivers. Every 16th clock pulse is output to the next X-driver. Latch Pulse. LP latches the signal in the X-driver shift registers into the output data latches. LP is a falling-edge triggered signal, and pulses once every display line. Connect LP to the Y-driver shift clock on modules. AC Drive Output. The WF period is selected to be one of two values with SYSTEM SET command. Latch Clock for YD. The falling edge of YSCL latches the data on YD into the input shift registers of the Ydrivers. YSCL is not used with driver ICs that use LP as the Y-driver shift clock. Data Pulse Output for Y Drivers. It is active during the last line of each frame, and is shifted through the Y drivers one by one (by YSCL), to scan the display’s common connections. Power-down Output Signal. YDIS is HIGH while the display drive outputs are active. YDIS goes LOW one or two frames after the sleep command is written to the RA8835A series. All Y-driver outputs are forced to an intermediate level (de-selecting the display segments) to blank the display. In order to implement power-down operation in the LCD unit, the LCD power drive supplies must also be disabled when the display is disabled by YDIS. 5-1-4 Oscillator and Power Pin Name Function Crystal Connection for Internal Oscillator This pin can be driven by an external clock source that satisfies the timing specifications of the EXT f0 signal (See Section 10-3-6). Crystal Connection for Internal Oscillator XD Leave this pin open when using an external clock source. 2.7 to 5.5V Supply. VDD This may be the same supply as the controlling microprocessor. GND Ground Note: The peak supply current drawn by the RA8835A series may be up to ten times the average supply current. The power supply impedance must be kept as low as possible by ensuring that supply lines are sufficiently wide and by placing 0.47μF decoupling capacitors that have good high-frequency response near the device’s supply pins. XG RAiO TECHNOLOGY INC. 9/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 5-2 RA8835A Pin Summary Name Number Type Description RA8835AP3N RA8835AP4N VA0 to VA15 27 to 28 30 to 43 1 to 6 50 to 59 Output VRAM address bus VWR 44 7 Output VRAM write signal VCE 45 8 Output Memory control signal VRD 46 9 Output VRAM read signal RES NC 47 28, 48, 49 10 11, 12, 60 Input — Reset No connection RD 50 13 Input 8080 family: Read signal 6800 family: Enable clock (E) WR 51 14 Input 8080 family: Write signal 6800 family: R/ W signal SEL2 SEL1 XG XD CS A0 VDD 52 53 54 55 15 16 17 18 19 20 21 Input Input Input Output Input Input Supply 22 to 29 Input/output 7 to 10 30 to 33 Output X-driver data 11 12 13 14 15 34 35 36 37 38 Output Output Supply Output Output YDIS 16 39 Output YD YSCL VD0 to VD7 17 18 40 41 Output Output X-driver enable chain clock X-driver data shift clock Ground Latch pulse Frame signal Power-down signal when display is blanked Scan start pulse Y-driver shift clock 19 to 26 42 to 49 Input/output D0 to D7 56 57 58 59 to 60 1 to 6 XD0 to XD3 XECL XSCL VSS LP WF RAiO TECHNOLOGY INC. 10/88 8080 or 6800 family interface select 8080 or 6800 family interface select Oscillator connection Oscillator connection Chip select Data type select 2.7 to 5.5V supply Data bus VRAM data bus www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 6. Instruction Set 6-1 The Command Set Table-1: Command Set Command Code Class Command Hex Command Description RD WR A0 D7 D6 D5 D4 D3 D2 D1 D0 System Control SYSTEM SET SLEEP IN DISPLAY ON/OFF 0 1 0 1 0 0 0 0 0 0 40 1 0 1 0 1 0 1 0 0 1 1 53 0 1 0 1 0 1 1 0 0 D No. of Bytes 1 1 Read Parameters 58, 59 Initialize device and display Enter standby mode Section 8 9-2-1 0 9-2-2 1 9-3-1 10 9-3-2 2 9-3-3 2 9-3-6 0 9-3-4 1 9-3-7 1 9-3-5 Enable and disable display and display flashing Set display start SCROLL 1 0 1 0 1 0 0 0 1 0 0 44 address and display regions CSRFORM Display CGRAM Control ADR CSRDIR 1 0 1 0 1 0 1 1 1 0 1 5D Set cursor type Set start address of 1 0 1 0 1 0 1 1 1 0 0 5C character generator RAM 1 0 1 0 1 0 0 1 1 CD CD 1 0 4C to 4F HDOT SCR 1 0 1 0 1 0 1 1 0 1 0 5A OVLAY 1 0 1 0 1 0 1 1 0 1 1 5B Set direction of cursor movement Set horizontal scroll position Set display overlay format Drawing CSRW 1 0 1 0 1 0 0 0 1 1 0 46 Set cursor address 2 9-r1 Control CSRR 1 0 1 0 1 0 0 0 1 1 1 47 Read cursor address 2 9-4-2 MWRITE 1 0 1 0 1 0 0 0 0 1 0 42 — 9-5-1 MREAD 1 0 1 0 1 0 0 0 0 1 1 43 — 9-5-2 Memory Control Write to display memory Read from display memory Notes: 1. In general, the internal registers of the RA8835A series are modified as each command parameter is input. However, the microprocessor does not have to set all the parameters of a command and may send a new command before all parameters have been input. The internal registers for the parameters that have been input will have been changed but the remaining parameter registers are unchanged. 2-byte parameters (where two bytes are treated as 1 data item) are handled as follows: a. CSRW, CSRR: Each byte is processed individually. The microprocessor may read or write just the low byte of the cursor address. b. SYSTEM SET, SCROLL, CGRAM ADR: Both parameter bytes are processed together. If the command is changed after half of the parameter has been input, the single byte is ignored. 2. APL and APH are 2-byte parameters, but are treated as two 1-byte parameters. RAiO TECHNOLOGY INC. 11/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 6-2 System Control Commands 6-2-1 SYSTEM SET Initializes the device, sets the window sizes, and selects the LCD interface format. Since this command sets the basic operating parameters of the RA8835A series, an incorrect SYSTEM SET command may cause other commands to operate incorrectly. MSB LSB D7 D6 D5 D4 D3 C 0 1 0 0 P1 0 0 IV P2 WF 0 P3 0 0 0 D2 D1 0 0 1 1 W/S M2 M1 M0 0 0 1 0 0 0 0 1 0 0 0 0 1 FX FY 0 A0 WR RD 1 0 0 D0 P4 C/R 0 0 1 P5 TC/R 0 0 1 P6 L/F 0 0 1 P7 APL 0 0 1 P8 APH 0 0 1 Figure 6-1: SYSTEM SET Instruction 6-2-1-1 C This control byte performs the following: 1. Resets the internal timing generator 2. Disables the display 3. Cancels sleep mode Parameters following P1 are not needed if only canceling sleep mode. 6-2-1-2 M0 Select the internal or external character generator ROM. The internal character generator ROM contains 160, 5 X 7 pixel characters, as shown in Figure 8-14. These characters are fixed at fabrication by the metallization mask. The external character generator ROM, on the other hand, can contain up to 256 user-defined characters. M0 = 0: Internal CG ROM M0 = 1: External CG ROM Note that if the CG ROM address space overlaps the display memory address space, that portion RAiO TECHNOLOGY INC. 12/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller of the display memory cannot be written to. 6-2-1-3 M1 Select the memory configuration for user-definable characters. The CG RAM codes select one of the 64 codes shown in figure 7-29. M1 = 0: No D6 correction. The CG RAM1 and CG RAM2 address spaces are not contiguous, the CG RAM1 address space is treated as character generator RAM, and the CG RAM2 address space is treated as character generator ROM. M1 = 1: D6 correction. The CG RAM1 and CG RAM2 address spaces are contiguous and are both treated as character generator RAM. 6-2-1-4 M2 Select the height of the character bitmaps. Characters more than 16 pixels high can be displayed by creating a bitmap for each portion of each character and using the RA8835A series graphics mode to reposition them. M2 = 0: 8-pixel character height (2716 or equivalent ROM) M2 = 1: 16-pixel character height (2732 or equivalent ROM) 6-2-1-5 W/S Select the LCD drive method. W/S = 0: Single-panel drive W/S = 1: Dual-panel drive EI X driver X driver YD Y driver LCD Figure 6-2: Single-panel Display RAiO TECHNOLOGY INC. 13/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller EI X driver X driver YD Upper Panel Y driver Lower Panel X driver X driver Figure 6-3: Above and Below Two-panel Display EI X driver X driver X driver X driver YD Y driver Left Panel Right Panel Figure 6-4: Left-and-Right Two-panel Display Note: There are no RAiO LCD units in the configuration shown in Figure 6-4. RAiO TECHNOLOGY INC. 14/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller Table-2: LCD Parameters Parameter W/S = 0 W/S = 1 IV = 1 IV = 0 IV = 1 IV = 0 C/R TC/R C/R TC/R C/R TC/R (See note 1.) C/R TC/R C/R TC/R L/F L/F L/F L/F SL1 00H to L/F (L/F) / 2 (L/F) / 2 SL2 00H to L/F L/F 00H to L/F + 1 (See note 2.) 00H to L/F + 1 (See note 2.) First screen block Second screen block Third screen block (L/F) / 2 (L/F) / 2 SAD1 SAD2 SAD3 SAD4 Cursor movement range First screen block Second screen block Third screen block Invalid Invalid Continuous movement over whole screen First screen block Second screen block Third screen block First screen block Second screen block Third screen block Fourth screen block Fourth screen block Above-and-below configuration: continuous movement over whole screen Notes: 1. See Table-24 for further details on setting the C/R and TC/R parameters when using 2. The value of SL when IV = 0 is equal to the value of SL when IV = 1, plus one. 6-2-1-6 IV Screen origin compensation for inverse display. IV is usually set to 1. The best way of displaying inverted characters is to Exclusive-OR the text layer with the graphics background layer. However, inverted characters at the top or left of the screen are difficult to read as the character origin is at the top-left of its bitmap and there are no background pixels either above or to the left of these characters. The IV flag causes the RA8835A series to offset the text screen against the graphics back layer by one vertical pixel. Use the horizontal pixel scroll function (HDOT SCR) to shift the text screen 1 to 7 pixels to the right. All characters will then have the necessary surrounding background pixels that ensure easy reading of the inverted characters. See Section 7-13 for information on scrolling. IV = 0: Screen top-line correction IV = 1: No screen top-line correction Display start point IV HDOT SCR Character Dots 1 to 7 Figure 6-5: IV and HDOT SCR Adjustment RAiO TECHNOLOGY INC. 15/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 6-2-1-7 FX Define the horizontal character size. The character width in pixels is equal to FX + 1, where FX can range from 00 to 07H inclusive. If data bit 3 is set (FX is in the range 08 to 0FH) and an 8-pixel font is used, a space is inserted between characters. Table-3: Horizontal Character Size Selection FX [FX] character D D D D width (pixels) HEX 3 2 1 0 00 0 0 0 0 1 01 0 0 0 1 2 ↓ ↓ ↓ ↓ ↓ ↓ 07 0 1 1 1 8 Since the RA8835A series handles display data in 8-bit units, characters larger than 8 pixels wide must be formed from 8-pixel segments. As Figure 6-6 shows, the remainder of the second eight bits are not displayed. This also applies to the second screen layer. In graphics mode, the normal character field is also eight pixels. If a wider character field is used, any remainder in the second eight bits is not displayed. FX FY FX 8 bits FY 8 bits 8 bits 8 bits Non-display area Address A Address B Figure 6-6: FX and FY Display Addresses 6-2-1-8 WF Select the AC frame drive waveform period. WF is usually set to 1. WF = 0: 16-line AC drive WF = 1: two-frame AC drive In two-frame AC drive, the WF period is twice the frame period. In 16-line AC drive, WF inverts every 16 lines. Although 16-line AC drive gives a more readable display, horizontal lines may appear when using high LCD drive voltages or at high viewing angles. RAiO TECHNOLOGY INC. 16/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 6-2-1-9 FY Set the vertical character size. The height in pixels is equal to FY + 1. FY can range from 00 to 0FH inclusive. Set FY to zero (vertical size equals one) when in graphics mode. Table-4: Vertical Character Size Selection FY [FY] character D D D D height (pixels) HEX 3 2 1 0 00 0 0 0 0 1 01 0 0 0 1 2 ↓ ↓ ↓ ↓ ↓ ↓ 07 0 1 1 1 8 ↓ ↓ ↓ ↓ ↓ ↓ 0E 1 1 1 0 15 0F 1 1 1 1 16 6-2-1-10 C/R Set the address range covered by one display line, that is, the number of characters less one, multiplied by the number of horizontal bytes per character. C/R can range from 0 to 239. For example, if the character width is 10 pixels, then the address range is equal to twice the number of characters, less 2. See Section 8-1-1 for the calculation of C/R. [C/R] cannot be set to a value greater than the address range. It can, however, be set smaller than the address range, in which case the excess display area is blank. The number of excess pixels must not exceed 64. HEX 00 01 ↓ 4F ↓ EE EF D7 0 0 ↓ 0 ↓ 1 1 RAiO TECHNOLOGY INC. D6 0 0 ↓ 1 ↓ 1 1 Table-5: Display Line Address Range C/R [C/R] bytes per display line D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 1 0 0 0 0 0 1 2 ↓ ↓ ↓ ↓ ↓ ↓ ↓ 0 0 1 1 1 1 80 ↓ ↓ ↓ ↓ ↓ ↓ ↓ 1 0 1 1 1 0 239 1 0 1 1 1 1 240 17/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 6-2-1-11 TC/R Set the length, including horizontal blanking, of one line. The line length is equal to TC/R + 1, where TC/ R can range from 0 to 255. TC/R must be greater than or equal to C/R + 4. Provided this condition is satisfied, [TC/R] can be set according to the equation given in Section 8-1-1 in order to hold the frame period constant and minimize jitter for any given main oscillator frequency, fOSC. HEX 00 01 ↓ 52 ↓ FE FF D7 0 0 ↓ 0 ↓ 1 1 D6 0 0 ↓ 1 ↓ 1 1 D5 0 0 ↓ 0 ↓ 1 1 Table-6: Line Length Selection TC/R [TC/R] line length (bytes) D4 D3 D2 D1 D0 0 0 0 0 0 1 0 0 0 0 1 2 ↓ ↓ ↓ ↓ ↓ ↓ 1 0 0 1 0 83 ↓ ↓ ↓ ↓ ↓ ↓ 1 1 1 1 0 255 1 1 1 1 1 256 6-2-1-12 L/F Set the height, in lines, of a frame. The height in lines is equal to L/F + 1, where L/F can range from 0 to 255. Table-7: Frame Height Selection L/F [L/F] lines per frame HEX D7 D6 D5 D4 D3 D2 D1 D0 00 0 0 0 0 0 0 0 0 1 01 0 0 0 0 0 0 0 1 2 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ 7F 0 1 1 1 1 1 1 1 128 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ FE 1 1 1 1 1 1 1 0 255 FF 1 1 1 1 1 1 1 1 256 If W/S is set to 1, selecting two-screen display, the number of lines must be even and L/F must, therefore, be an odd number. RAiO TECHNOLOGY INC. 18/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 6-2-1-13 AP Define the horizontal address range of the virtual screen. APL is the least significant byte of the address. Figure 6-7: AP Parameters Table-8: Horizontal Address Range Hex code [AP] addresses per line APH APL 0 0 0 0 0 0 0 0 1 1 ↓ ↓ ↓ ↓ ↓ 0 0 5 0 80 ↓ ↓ ↓ ↓ ↓ F F F E 216– 2 F F F F 216– 1 Display area C/R Display memory limit AP Figure 6-8: AP and C/R Relationship RAiO TECHNOLOGY INC. 19/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 6-2-2 SLEEP IN Place the system in standby mode. This command has no parameter bytes. At least one blank frame after receiving this command, the RA8835A halts all internal operations, including the oscillator, and enters the sleep state. Blank data is sent to the X-drivers, and the Y-drivers have their bias supplies turned off by the YDIS signal. Using the YDIS signal to disable the Y-drivers guards against any spurious displays. The internal registers of the RA8835A series maintain their values during the sleep state. The display memory control pins maintain their logic levels to ensure that the display memory is not corrupted. The RA8835A series can be removed from the sleep state by sending the SYSTEM SET command with only the P1 parameter. The DISP ON command should be sent next to enable the display. Figure 6-9: SLEEP IN Instruction 1. The YDIS signal goes LOW between one and two frames after the SLEEP IN command is received. Since YDIS forces all display driver outputs to go to the deselected output voltage, YDIS can be used as a power-down signal for the LCD unit. This can be done by having YDIS turn off the relatively high power LCD drive supplies at the same time as it blanks the display. 2. Since all internal clocks in the RA8835A series are halted while in the sleep state, a DC voltage will be applied to the LCD panel if the LCD drive supplies remain on. If reliability is a prime consideration, turn off the LCD drive supplies before issuing the SLEEP IN command. 3. Note that, although the bus lines become high impedance in the sleep state, pull-up or pulldown resistors on the bus will force these lines to a known state. RAiO TECHNOLOGY INC. 20/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 6-3 Display Control Commands 6-3-1 DISP ON/OFF Turn the whole display on or off. The single-byte parameter enables and disables the cursor and layered screens, and sets the cursor and screen flash rates. The cursor can be set to flash over one character or over a whole line. MSB LSB C 0 1 0 1 1 0 0 D P1 FP5 FP4 FP3 FP2 FP1 FP0 FC1 FC0 Figure 6-10: DISP ON/OFF Parameters 6-3-1-1 D Turn the display ON or OFF. The D bit takes precedence over the FP bits in the parameter. D = 0: Display OFF D = 1: Display ON 6-3-1-2 FC Enables/disables the cursor and sets the flash rate. The cursor flashes with a 70% duty cycle (ON/OFF). Table-9: Cursor Flash Rate Selection FC1 FC0 Cursor display 0 0 OFF (blank) 0 1 No flashing Flash at fFR/32 Hz 1 0 (approx. 2 Hz) ON Flash at fFR/64 Hz 1 1 (approx. 1 Hz) Note: As the MWRITE command always enables the cursor, the cursor position can be checked even when performing consecutive writes to display memory while the cursor is flashing. RAiO TECHNOLOGY INC. 21/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 6-3-1-3 FP Each pair of bits in FP sets the attributes of one screen block, as follows. The display attributes are as follows: Table-10: Screen Block Attribute Selection FP1 FP0 First screen block (SAD1) Second screen block FP3 FP2 (SAD2, SAD4). See note. FP5 FP4 Third screen block (SAD3) 0 0 OFF (blank) 0 1 No flashing Flash at fFR/32 Hz 1 0 ON (approx. 2 Hz) Flash at fFR/4 Hz 1 1 (approx. 16 Hz) Note: If SAD4 is enabled by setting W/S to 1, FP3 and FP2 control both SAD2 and SAD4. The attributes of SAD2 and SAD4 cannot be set independently. RAiO TECHNOLOGY INC. 22/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 6-3-2 SCROLL 6-3-2-1 C Set the scroll start address and the number of lines per scroll block. Parameters P1 to P10 can be omitted if not required. The parameters must be entered sequentially as shown in Figure 6-11. M SB LSB C 0 1 0 0 0 1 0 0 P1 A7 A6 A5 A4 A3 A2 A1 A0 (SAD 1L) P2 A15 A14 A13 A12 A11 A10 A9 A8 (SAD 1H ) P3 L7 L6 L5 L4 L3 L2 L1 L0 (SL1) P4 A7 A6 A5 A4 A3 A2 A1 A0 (SAD 2L) P5 A15 A14 A13 A12 A11 A10 A9 A8 (SAD 2H ) P6 L7 L6 L5 L4 L3 L2 L1 L0 P7 A7 A6 A5 A4 A3 A2 A1 A0 (SAD 3L) P8 A15 A14 A13 A12 A11 A10 A9 A8 (SAD 3H ) P9 A7 A6 A5 A4 A3 A2 A1 A0 (SAD 4L) P10 A15 A14 A13 A12 A11 A10 A9 A8 (SAD 4H ) (SL2) Figure 6-11: SCROLL Instruction Parameters Note: Set parameters P9 and P10 only if both two-screen drive (W/S = 1) and two-layer configuration are selected. SAD4 is the fourth screen block display start address. HEX 00 01 ↓ 7F ↓ FE FF L7 0 0 ↓ 0 ↓ 1 1 RAiO TECHNOLOGY INC. Table-11: Screen Block Start Address Selection SL1, SL2 [SL] screen lines L6 L5 L4 L3 L2 L1 L0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 2 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ 1 1 1 1 1 1 1 128 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ 1 1 1 1 1 1 0 255 1 1 1 1 1 1 1 256 23/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 6-3-2-2 SL1, SL2 SL1 and SL2 set the number of lines per scrolling screen. The number of lines is SL1 or SL2 plus one. The relationship between SAD, SL and the display mode is described below. W/S Table-12: Text Display Mode Screen First Layer Second Layer First screen block SAD1 SAD2 Second screen block SL1 SL2 SAD3 (see note 1) Third screen block (partitioned screen) Set both SL1 and SL2 to L/F + 1 if not using a partitioned screen. Screen configuration example: SAD2 0 SL2 SAD1 Graphics display page 2 SL1 Character display page 1 SAD3 Character display page 3 Layer 2 Layer 1 SAD1 SL1 SAD3 Lower screen (See note 2) Set both SL1 and SL2 to ((L/F) / 2 + 1) Screen configuration example: Upper screen SAD2 SL2 SAD4 (See note 2) SAD2 1 SAD1 SL1 Graphics display page 2 Character display page 1 SAD3 Graphics display page 4 Character display page 3 (SAD4) Layer 1 Layer 2 Notes: 1. SAD3 has the same value as either SAD1 or SAD2, whichever has the least number of lines (set by SL1 and SL2). 2. Since the parameters corresponding to SL3 and SL4 are fixed by L/F, they do not have to be set in this mode. RAiO TECHNOLOGY INC. 24/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller Table-13: Graphics Display Mode Screen First Layer Second Layer SAD1 SAD2 Two-layer composition SL1 SL2 SAD3 (see note 3) Upper screen Set both SL1 and SL2 to L/F + 1 if not using a partitioned screen Screen configuration example: W/S Third Layer — — SAD2 SL2 0 SAD1 Graphics display page 2 SL1 Character display page 1 SAD3 Character display page 3 Layer 1 Layer 2 SAD1 SAD2 SL1 = L/F + 1 SL1 = L/F + 1 Screen configuration example: Three-layer configuration SAD3 — SAD3 Graphics display page 3 SAD2 SAD1 SL2 0 Graphics display page 2 SL1 Graphics display page 1 Layer 1 RAiO TECHNOLOGY INC. 25/88 Layer 2 Layer 3 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller Table-13: Graphics Display Mode (continued) Screen First Layer Second Layer SAD1 SAD2 Upper screen SL1 SL2 SAD3 SAD4 Lower screen (See note 2) (See note 2) Screen configuration example (See note 3): W/S Third Layer — — SAD2 1 SAD1 SL1 Graphics display page 2 Graphics display page 1 SAD3 Graphics display page 4 Graphics display page 3 Layer 1 Layer 2 Notes: 1. SAD3 has the same value as either SAD1 or SAD2; whichever has the least number of lines (set by SL1 and SL2). 2. Since the parameters corresponding to SL3 and SL4 are fixed by L/F, they do not have to be set. 3. If, and only if, W/S = 1, the differences between SL1 and (L/F + 1) / 2, and between SL2 and (L/F + 1) / 2, are blanked. Upper Panel SL1 L Lower Panel Graphics L/2 Figure 6-12: Two-panel Display Height RAiO TECHNOLOGY INC. 26/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 6-3-3 CSRFORM Set the cursor size and shape. Although the cursor is normally only used in text displays, it may also be used in graphics displays when displaying special characters. MSB LSB C 0 1 0 1 P1 0 0 0 0 P2 CM 0 0 0 1 1 0 1 X3 X2 X1 X0 Y3 CRY Y1 Y2 Y0 CRX Figure 6-13: CSRFORM Parameter Bytes 6-3-3-1 CRX Set the horizontal size of the cursor from the character origin. CRX is equal to the cursor size less one. CRX must be less than or equal to FX. Table-14: Horizontal Cursor Size Selection [CRX] cursor CRX width HEX X3 X2 X1 X0 (pixels) 0 0 0 0 0 1 1 0 0 0 1 2 ↓ ↓ ↓ ↓ ↓ ↓ 4 0 1 0 0 9 ↓ ↓ ↓ ↓ ↓ ↓ E 1 1 1 0 15 F 1 1 1 1 16 6-3-3-2 CRY Set the location of an underscored cursor in lines, from the character origin. When using a block cursor, CRY sets the vertical size of the cursor from the character origin. CRY is equal to the number of lines less one. Table-15: Cursor Height Selection [CRY] cursor CRY height HEX Y3 Y2 Y1 Y0 (lines) 0 0 0 0 0 Illegal 1 0 0 0 1 2 ↓ ↓ ↓ ↓ ↓ ↓ 8 1 0 0 0 9 ↓ ↓ ↓ ↓ ↓ ↓ E 1 1 1 0 15 F 1 1 1 1 16 RAiO TECHNOLOGY INC. 27/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller Character start point 0 1 2 3 4 5 6 7 8 9 01 2 3 4 5 6‧‧‧ ‧ CRX = 5 dots CRY = 9 dots CM = 0 Figure 6-14: Cursor Size and Position 6-3-3-3 CM Set the cursor shape. Always set CM to 1 when in graphics mode. CM = 0: Underscore cursor CM = 1: Block cursor 6-3-4 CSRDIR Set the direction of automatic cursor increment. The cursor can move left or right one character, or up or down by the number of bytes specified by the address pitch, AP. When reading from and writing to display memory, this automatic cursor increment controls the display memory address increment on each read or write. MSB C LSB 0 1 0 0 1 1 CD1 CD2 Figure 6-15: CSRDIR Parameters 10 01 -AP -1 1 00 +AP 11 Figure 6-16: Cursor Direction RAiO TECHNOLOGY INC. 28/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller Table-16: Cursor Shift Direction C CD1 CD0 Shift direction 4CH 0 0 Right 4DH 0 1 Left 4EH 1 0 Up 4FH 1 1 Down Note: Since the cursor moves in address units even if FX ≥ 9 , the cursor address increment must be preset for movement in character units. See Section 7-11. 6-3-5 OVLAY Selects layered screen composition and screen text/ graphics mode. MSB LSB C 0 1 0 1 1 0 1 1 P1 0 0 0 OV DM2 DM1 MX1 MX0 Figure 6-17: OVLAY Parameters 6-3-5-1 MX0, MX1 MX0 and MX1 set the layered screen composition method, which can be either OR, AND, Exclusive-OR or Priority- OR. Since the screen composition is organized in layers and not by screen blocks, when using a layer divided into two screen blocks, different composition methods cannot be specified for the individual screen blocks. The Priority-OR mode is the same as the OR mode unless flashing of individual screens is used. MX1 MX0 0 0 0 1 1 0 1 1 Table-17: Composition Method Selection Functio Composition Method Applications n L1 ∪ L2 Underlining, rules, mixed text OR ∪ L3 and graphics (L1 ♁ Inverted characters, flashing Exclusive-OR L2) ∪ L3 regions, underlining (L1 ∩ AND L2) ∪ L3 Simple animation, threedimensional appearance L1 > L2 Priority-OR > L3 Notes: L1: First layer (text or graphics). If text is selected, layer L3 cannot be used. L2: Second layer (graphics only) L3: Third layer (graphics only) RAiO TECHNOLOGY INC. 29/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller Layer 1 Layer 2 Layer 3 Visible display 1 ABCDE ABCDE OR 2 ABCDE ABCDE Exclusive OR 3 ABCDE CDE 4 ABCDE ABCDE AND Prioritized OR Figure 6-18: Combined Layer Display Notes: L1: Not flashing L2: Flashing at 1 Hz L3: Flashing at 2 Hz 6-3-5-2 DM1, DM2 DM1 and DM2 specify the display mode of screen blocks 1 and 3, respectively. DM1/2 = 0: Text mode DM1/2 = 1: Graphics mode Note 1: Screen blocks 2 and 4 can only display graphics. Note 2: DM1 and DM2 must be the same, regardless of the setting of W/S. 6-3-5-3 OV Specifies two- or three-layer composition in graphics mode. OV = 0: Two-layer composition OV = 1: Three-layer composition Set OV to 0 for mixed text and graphics mode. 6-3-6 CGRAM ADR Specifies the CG RAM start address. LSB MSB C 0 1 0 1 1 1 0 0 P1 A7 A6 A5 A4 A3 A2 A1 A0 SAGL P2 A15 A14 A13 A12 A11 A10 A9 A8 SAGH Figure 6-19: CGRAM ADR Parameters Note: See Section 7-14 for information on the SAG parameters. RAiO TECHNOLOGY INC. 30/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 6-3-7 HDOT SCR While the SCROLL command only allows scrolling by characters, HDOT SCR allows the screen to be scrolled horizontally by pixels. HDOT SCR cannot be used on individual layers. MSB LSB C 0 1 0 1 1 0 1 0 P1 0 0 0 0 0 D2 D1 D0 Figure 6-20: HDOT SCR Parameters 6-3-7-1 D0 to D2 Specifies the number of pixels to scroll. The C/R parameter has to be set to one more than the number of horizontal characters before using HDOT SCR. Smooth scrolling can be simulated if the controlling microprocessor repeatedly issues the HDOT SCR command to the RA8835A series. See Section 7-13 for more information on scrolling the display. HEX 00 01 02 ↓ 06 07 Table-18: Scroll Step Selection Number of pixels to P1 scroll D2 D1 D0 0 0 0 0 0 0 1 1 0 1 0 2 ↓ ↓ ↓ ↓ 1 1 0 6 1 1 1 7 A B A Z Z X B A Y B X Display width M=0 N=0 Y X Y N M/N is the number of bits(dots) that parameter 1 (P1) is incremented/decremented by. Figure 6-21 Horizontal Scrolling RAiO TECHNOLOGY INC. 31/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 6-4 Drawing Control Commands 6-4-1 CSRW The 16-bit cursor address register contains the display memory address of the data at the cursor position as shown in Figure 6-22. Note that the microprocessor cannot directly access the display memory. The MREAD and MWRITE commands use the address in this register. LSB MSB C 0 1 0 0 0 1 1 0 P1 A7 A6 A5 A4 A3 A2 A1 A0 (CSRL) P2 A15 A14 A13 A12 A11 A10 A9 A8 (CSRH) Figure 6-22: CSRW Parameters The cursor address register can only be modified by the CSRW command, and by the automatic increment after an MREAD or MWRITE command. It is not affected by display scrolling. If a new address is not set, display memory accesses will be from the last set address or the address after previous automatic increments. 6-4-2 CSRR Read from the cursor address register. After issuing the command, the data read address is read twice, for the low byte and then the high byte of the register. MSB LSB C 0 1 0 0 0 1 1 1 P1 A7 A6 A5 A4 A3 A2 A1 A0 (CSRL) P2 A15 A14 A13 A12 A11 A10 A9 A8 (CSRH) Figure 6-23: CSRR Parameters RAiO TECHNOLOGY INC. 32/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 6-5 Memory Control Commands 6-5-1 MWRITE The microprocessor may write a sequence of data bytes to display memory by issuing the MREAD command and then writing the bytes to the RA8835A series. There is no need for further MWRITE commands or for the microprocessor to update the cursor address register after each byte as the cursor address is automatically incremented by the amount set with CSRDIR, in preparation for the next data write. LSB MSB C 0 1 0 0 0 0 1 0 P1 P2 Pn N>1 Figure 6-24: MWRITE Parameters Note: P1, P2, ..., Pn: display data. 6-5-2 MREAD Put the RA8835A series into the data output state. Each time the microprocessor reads the buffer, the cursor address is incremented by the amount set by CSRDIR and the next data byte fetched from memory, so a sequence of data bytes may be read without further MREAD commands or by updating the cursor address register. If the cursor is displayed, the read data will be from two positions ahead of the cursor. LSB MSB C 0 1 0 0 0 0 1 1 P1 P2 Pn N>1 Figure 6-25: MREAD Parameters RAiO TECHNOLOGY INC. 33/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 7. Functions Description 7-1 MCU Bus Interface SEL1, SEL2, A0, RD , WR and CS are used as control signals for the microprocessor data bus. A0 is normally connected to the lowest bit of the system address bus. SEL1 and SEL2 change the operation of the RD and WR pins to enable interfacing to either an 8080 or 6800 family bus, and should have a pull-up or pull-down resistor. With microprocessors using an 8080 family interface, the RA8835A series is normally mapped into the I/O address space. 7-1-1 8080 Series Table-19: 8080 Series Interface Signals A0 0 RD 0 WR 1 1 0 1 0 1 1 1 0 0 Function Status flag read Display data and cursor address read Display data and parameter write Command write 7-1-2 6800 Series Table-20A: 6800 Series Interface Signals 0 R/ W 1 1 1 1 0 1 0 0 1 1 A0 E Function 1 Status flag read Display data and cursor address read Display data and parameter write Command write 7-2 MCU Synchronization The RA8835A series interface operates at full bus speed, completing the execution of each command within the cycle time, tCYC. The controlling microprocessor’s performance is thus not hampered by polling or handshaking when accessing the RA8835A series. Display flicker may occur if there is more than one consecutive access that cannot be ignored within a frame. The microprocessor can minimize this either by performing these accesses intermittently, or by continuously checking the status flag (D6) and waiting for it to become HIGH. 7-2-1 Display Status Indication Output When CS , A0 and RD are LOW, D6 functions as the display status indication output. It is HIGH during the TV-mode vertical retrace period or the LCD-mode horizontal retrace period, and LOW, during the period the controller is writing to the display. By monitoring D6 and writing to the data memory only during retrace periods, the display can be updated without causing screen flicker. RAiO TECHNOLOGY INC. 34/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 7-2-2 Internal Register Access The SYSTEM SET and SLEEP IN commands can be used to perform input/output to the RA8835A series independently of the system clock frequency. These are the only commands that can be used while the RA8835A series is in sleep mode. 7-2-3 Display Memory Access The RA8835A series supports a form of pipelined processing, in which the microprocessor synchronizes its processing to the RA8835A series timing. When writing, the microprocessor first issues the MWRITE command. It then repeatedly writes display data to the RA8835A series using the system bus timing. This ensures that the microprocessor is not slowed down even if the display memory access times are slower than the system bus access times. See Figure 7-1A. tCYC WR Command write Microprocessor Data write Data write D0 to D7 VR/ W VRW VD0 to VD7 Figure 7-1A: Display Memory Write Cycle When reading, the microprocessor first issues the MREAD command, which causes the RA8835A series to load the first read data into its output buffer. The microprocessor then reads data from the RA8835A series using the system bus timing. With each read, the RA8835A series reads the next data item from the display memory ready for the next read access. See Figure 7-1B. Figure 7-1B: Display Memory Read Cycle Note: A possible problem with the display memory read cycle is that the system bus access time, tACC, does not depend on the display memory access time, tACV. The microprocessor may RAiO TECHNOLOGY INC. 35/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller only make repeated reads if the read loop time exceeds the RA8835A series cycle time, tCYC. If it does not, NOP instructions may be inserted in the program loop. tACC, tACV and tCYC limits are given in Section 10-2. 7-3 MCU Interface Examples 7-3-1 Z80 to RA8835A Interface IORQ A0 A1 to A15 Z80 A0 Decoder D0 to D7 CS D0 to D7 RD RD WR WR RESET RA8835 SEL1 SEL2 RES RESET Figure 7-2A: Z80 to RA8835A Interface 7-3-2 6802 to RA8835A Interface VMA A0 A0 A1 to A15 6802 Decoder CS D0 to D7 D0 to D7 E RD R/W WR RESET RA8835 RES VDD SEL1 SEL2 RESET Figure 7-2B: 6802 to RA8835A Interface RAiO TECHNOLOGY INC. 36/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 7-4 Static RAM The figure below shows the interface between an 8Kx8 static RAM and the RA8835A series. Note that bus buffers are required if the bus is heavily loaded. Note VA0 to VA12 A0 to A12 HC138 VA13 toVA15 A-C CS1 Y VDD RA8835 CE2 WRD OE VWR WR 2764-pin Compatible memory I/O1 to I/O8 VD0 to VD7 Figure 7-3: Static RAM Interface Note: If the bus loading is too much, use a bus buffer. 7-5 Supply Current during Display Memory Access The 24 address and data lines of the RA8835A series cycle at one-third of the oscillator frequency, fOSC. The charge and discharge current on these pins, IVOP, is given by the equation below. When IVOP exceeds IOPR, it can be estimated by: IVOP ∝ C V f Where C is the capacitance of the display memory bus, V is the operating voltage, and f is the operating frequency. If VOPR = 5.0V, f = 1.0 MHz, and the display memory bus capacitance is 1.0 pF per line: IVOP ≤ 120 mA / MHz x pF To reduce current flow during display memory accesses, it is important to use low-power memory, and to minimize both the number of devices and the parasitic capacitance. RAiO TECHNOLOGY INC. 37/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 7-6 Oscillator Circuit The RA8835A series incorporates an oscillator circuit. A stable oscillator can be constructed simply by connecting an AT-cut crystal and two capacitors to XG and XD, as shown in the figure below. If the oscillator frequency is increased, CD and CG should be decreased proportionally. Note that the circuit board lines to XG and XD must be as short as possible to prevent wiring capacitance from changing the oscillator frequency or increasing the power consumption. Figure 7-4: Crystal Oscillator 7-7 Status Flag The RA8835A series has a single bit status flag. D6: X line standby Figure 7-5: Status Flag The D6 status flag is HIGH for the tC/R period, and go Low at tTC/R - tC/R period where the RA8835A series is not reading the display memory. The microprocessor may use this period to update display memory without affecting the display, however it is recommended that the display be turned off when refreshing the whole display. LP tTC/R tm tC/R XSCL Figure 7-6: C/R to TC/R Time Difference RAiO TECHNOLOGY INC. 38/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller CS A0 RD 0 0 0 D6(flag) 0: Period of retrace lines 1: Period of display Figure 7-7: Flowchart for Busy Flag Checking • Precaution on the write timing to VRAM The allowable writing duration is since “5 x 9 x tOSC” has elapsed (tOSC = 1/fOSC: a cycle of the oscillation frequency) from the positive going edge of LP up to {(TCR) – (C/R) – 7} x 9 x tOSC. Currently employed D6 status flag reading method does not identify the timing when the read D6 = Low took place. Thus, negative going edge of LP should be used as the interrupt signal when implementing the writing in above timing. If you try to access the display memory in other timing than the above, flickering of the display screen will result. RAiO TECHNOLOGY INC. 39/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 7-8 Reset VDD 10*tc reset pulse 0.7VDD RES 0.3VDD Figure 7-8: Reset Timing The RA8835A series requires a reset pulse at least 10*tc long after power-on in order to re-initialize its internal state. If the oscillator frequency is 10Mhz, then the Reset pulse is at least 1µs. For maximum reliability, it is not recommended to apply a DC voltage to the LCD panel while the RA8835A series is reset. Turn off the LCD power supplies for at least one frame period after the start of the reset pulse. The RA8835A series cannot receive commands while it is reset. Commands to initialize the internal registers should be issued soon after a reset. During reset, the LCD drive signals XD, LP and FR are halted. A delay of 3 ms (minimum) is required following the rising edges of both RES and VDD to allow for system stabilization. 7-9 Character Configuration The origin of each character bitmap is in the top left corner as shown in Figure 7-9. Adjacent bits in each byte are horizontally adjacent in the corresponding character image. Although the size of the bitmap is fixed by the character generator, the actual displayed size of the character field can be varied in both dimensions. Character start point FX Character height FY Space Character Space width data R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 D7 0 1 1 0 1 0 1 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 to 1 0 0 1 0 1 0 1 1 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D0 0 0 0 0 0 0 0 0 0 0 0 0 Space 0 data 0 0 0 Space data Figure 7-9: Example of Character Display ([FX] ≤ 8) and Generator Bitmap If the area outside the character bitmap contains only zeros, the displayed character size can easily be increased by increasing FX and FY, as the zeros ensure that the extra space between displayed characters is blank. The displayed character width can be set to any value up to 16 even if each horizontal row of the bitmap is two bytes wide. RAiO TECHNOLOGY INC. 40/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller Horizontal non-display area FX Character Hight FY 16 dots Space 8 dots 8 dots Character width Space data Figure 7-10: Character Width Greater Than One Byte Wide ([FX]=9) Note: The RA8835A series does not automatically insert spaces between characters. If the displayed character size is 8 pixels or less and the space between character origins is nine pixels or more, the bitmap must use two bytes per row, even though the character image requires only one. 7-10 Screen Configuration 7-10-1 Screen Configuration Character memory area A/P C/R 0000H 0800H 07FFH Graphics memory area Display memory window 47FFH (0,YM) (XM,YM) (X,Y) Y (0,0) (XM,0) X Figure 7-11: Virtual and Physical Screen Relationship RAiO TECHNOLOGY INC. 41/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller The basic screen configuration of the RA8835A series is as a single text screen or as overlapping text and graphics screens. The graphics screen uses eight times as much display memory as the text screen. Figure 7-11 shows the relationship between the virtual screens and the physical screen. 7-10-2 Display Address Scanning The RA8835A series scans the display memory in the same way as a raster scan CRT screen. Each row is scanned from left to right until the address range equals C/R. Rows are scanned from top to bottom. In graphics mode, at the start of each line, the address counter is set to the address at the start of the previous line plus the address pitch, AP. 1 ‧ ‧ 8 9 ‧ ‧ 16 17 ‧ ‧ SAD SAD+AP SAD+1 SAD+2 SAD+C/R SAD+AP +1 SAD+AP +2 SAD+AP +C/R SAD+2AP 24 ‧ ‧ ‧ C/R WS=0,FX=8,FY=8 Figure 7-12: Character Position Parameters Note: One byte of display memory corresponds to one character. 1 SAD 2 SAD+AP 3 SAD+2AP SAD+1 SAD+2 SAD+C/R SAD+AP +1 SAD+AP +2 SAD+AP +C/R SAD SAD+1 SAD+2 Line 1 AP SAD+C/R ‧ ‧ ‧ ‧ ‧ ‧ SAD+AP SAD+AP+1 Line 2 AP SAD+AP+C/R SAD+2AP C/R Line 3 WS=0,FX=8 Figure 7-13: Character Parameters vs. Memory Note: One bit of display memory corresponds to one pixel. RAiO TECHNOLOGY INC. 42/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller In text mode, the address counter is set to the same start address, and the same character data is read, for each row in the character bitmap. However, a new row of the character generator output is used each time. Once all the rows in the character bitmap have been displayed, the address counter is set to the start address plus AP and the next line of text is displayed. 1 ‧ ‧ 8 9 ‧ ‧ 16 17 ‧ ‧ SAD+C/R SAD SAD+1 SAD1+2 SAD1+AP SAD1+AP SAD1+AP +1 +2 SAD1+AP +C/R SAD1+2AP 24 ‧ ‧ ‧ (L/F)/2=β β+1 SAD3+2 ‧ SAD3+1 ‧ β+8 β+9 ‧ SAD3+AP SAD3+AP SAD3+AP +1 +2 ‧ β+1 β+1 6 7 ‧ SAD3+2AP ‧ β+2 4 β+2 5 ‧ ‧ ‧ SAD3+C/R SAD3+AP +C/R (L/F) C/R WS=1,FX=8,FY=8 Figure 7-14: Two-panel Display Address Indexing Note: In two-panel drive, the RA8835A series reads line 1 and line b + 1 as one cycle. The upper and lower panels are thus read alternately, one line at a time. RAiO TECHNOLOGY INC. 43/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 7-10-3 Display Scan Timing Figure 7-15 shows the basic timing of the RA8835A series. One display memory read cycle takes nine periods of the system clock, ψ0 (fOSC ). This cycle repeats (C/R + 1) times per display line. When reading, the display memory pauses at the end of each line for (TC/R - C/R) display memory read cycles, though the LCD drive signals are still generated. TC/R may be set to any value within the constraints imposed by C/R, fOSC , fFR , and the size of the LCD panel, and it may be used to fine tune the frame frequency. The microprocessor may also use this pause to access the display memory data. ¢ 0 T0 T1 T2 Display read cycle interal VCE Character read interal Graphics read interal Graphics generator read interal VA Figure 7-15: Display Memory Basic Read Cycle Display period Divider frequency period TC/R C/R Frame period Line 1 0 R 2 0 R 3 0 R ‧ ‧ ‧ ‧ (L/F) 0 R LP Figure 7-16: Relationship Between TC/R and C/R Note: The divider adjustment interval (R) applies to both the upper and lower screens even if W/S = 1. In this case, LP is active only at the end of the lower screen’s display interval. RAiO TECHNOLOGY INC. 44/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 7-11 Cursor Control 7-11-1 Cursor Register Function The RA8835A series cursor address register functions as both the displayed cursor position address register and the display memory access address register. When accessing display memory outside the actual screen memory, the address register must be saved before accessing the memory and restored after memory access is complete. Figure 7-17: Cursor Addressing Note that the cursor may disappear from the display if the cursor address remains outside the displayed screen memory for more than a few hundred milliseconds. 7-11-2 Cursor Movement On each memory access, the cursor address register changes by the amount previously specified with CSRDIR, automatically moving the cursor to the desired location. 7-11-3 Cursor Display Layers Although the RA8835A series can display up to three layers, the cursor is displayed in only one of these layers: Two-layer configuration: First layer (L1) Three-layer configuration: Third layer (L3) The cursor will not be displayed if it is moved outside the memory for its layer. Layers may be swapped or the cursor layer moved within the display memory if it is necessary to display the cursor on a layer other than the present cursor layer. Although the cursor is normally displayed for character data, the RA8835A series may also display a dummy cursor for graphical characters. This is only possible if the graphics screen is displayed, the text screen is turned off and the microprocessor generates the cursor control address. Figure 7-18: Cursor Display Layers RAiO TECHNOLOGY INC. 45/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller Consider the example of displaying Chinese characters on a graphics screen. To write the display data, the cursor address is set to the second screen block, but the cursor is not displayed. To display the cursor, the cursor address is set to an address within the blank text screen block. Since the automatic cursor increment is in address units, not character units, the controlling microprocessor must set the cursor address register when moving the cursor over the graphical characters. Figure 7-19: Cursor Movement If no text screen is displayed, only a bar cursor can be displayed at the cursor address. If the first layer is a mixed text and graphics screen and the cursor shape is set to a block cursor, the RA8835A series automatically decides which cursor shape to display. On the text screen it displays a block cursor, and on the graphics screen, a bar cursor. RAiO TECHNOLOGY INC. 46/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 7-12 Memory to Display Relationship The RA8835A series supports virtual screens that are larger than the physical size of the LCD panel address range, C/R. A layer of the RA8835A series can be considered as a window in the larger virtual screen held in display memory. This window can be divided into two blocks, with each block able to display a different portion of the virtual screen. This enables, for example, one block to dynamically scroll through a data area while the other acts as a status message display area. See Figure 7-20 and 7-21. AP C/R SAD1 W/S=0 Character page1 SAD1 Character page3 SAD3 SAD3 Display page 1 W/S=1 Graphics page 1 Graphics page 3 Graphics page 2 Layer 1 SAD2 Graphics page 2 SAD4 Display page 2 Layer 1 Graphics page 2 Graphics page 4 C/R Layer 2 Layer 2 CG RAM SAD1 C/R Character page1 SAD1 Display page1 SAD3 Display page3 C/R SAD3 Graphics page 3 Layer 1 C/R SAD2 SAD2 Display page2 Graphics page 2 Layer 2 C/R SAD3 Character page3 C/R SAD3 SAD2 SAD2 Graphics page 2 Display page3 C/R Display page2 SAD1 SAD1 Display page1 Graphics page 1 Layer 1 Layer 2 Layer 3 Figure 7-20: Display Layers and Memory RAiO TECHNOLOGY INC. 47/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller Figure 7-21: Display Windows and Memory RAiO TECHNOLOGY INC. 48/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller Figure 7-22: Memory Map and Magnified Characters RAiO TECHNOLOGY INC. 49/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 7-13 Scrolling The controlling microprocessor can set the RA8835A series scrolling modes by overwriting the scroll address registers SAD1 to SAD4, and by directly setting the scrolling mode and scrolling rate. 7-13-1 On-page Scrolling The normal method of scrolling within a page is to move the whole display up one line and erase the bottom line. Since the RA8835A series does not automatically erase the bottom line, it must be erased with blanking data when changing the scroll address register. Figure 7-23: On-page Scrolling 7-13-2 Inter-page Scrolling Scrolling between pages and page switching can be performed only if the display memory capacity is greater than one screen. Figure 7-24: Inter-page Scrolling RAiO TECHNOLOGY INC. 50/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 7-13-3 Horizontal Scrolling The display can be scrolled horizontally in one-character units, regardless of the display memory capacity. Figure 7-25: Horizontal Wraparound Scrolling 7-13-4 Bi-directional Scrolling Bi-directional scrolling can be performed only if the display memory is larger than the physical screen both horizontally and vertically. Although scrolling is normally done in single-character units, the HDOT SCR command can be used to scroll horizontally in pixel units. The Single-pixel scrolling of both horizontally and vertically can be performed by using the SCROLL and HDOT SCR commands. See Section 8-4. Figure 7-26: Bi-directional Scrolling RAiO TECHNOLOGY INC. 51/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 7-13-5 Scroll Units Table-20B: Scroll Units Mode Vertical Horizontal Pixels or Text Characters characters Graphics Pixels Pixels Note that in a divided screen, each block cannot be independently scrolled horizontally in pixel units. 7-14 CG Characteristics 7-14-1 Internal Character Generator The internal character generator is recommended for minimum system configurations containing a RA8835A series, display RAM, LCD panel, single-chip microprocessor and power supply. Since the internal character generator uses a CMOS mask ROM, it is also recommended for low-power applications. • 5 x 7-pixel font (See Section 8-7.) • 160 JIS standard characters • Can be mixed with character generator RAM (maximum of 64 CG RAM characters) • Can be automatically spaced out up to 8 x 16 pixels 7-14-2 External Character Generator ROM The external CG ROM can be used when fonts other than those in the internal ROM are needed. Data is stored in the external ROM in the same format used in the internal ROM. (See Section 716) • Up to 8 x 8-pixel characters (M2 = 0) or 8 x 16-pixel characters (M2 = 1) • Up to 256 characters (192 if used together with the internal ROM) • Mapped into the display memory address space at F000H to F7FFH (M2 = 0) or F000H to FFFFH (M2 = 1) • Characters can be up to 8 x 16-pixels; however, excess bits must be set to zero. 7-14-3 Character Generator RAM The user can freely use the character generator RAM for storing graphics characters. The character generator RAM can be mapped by the microprocessor anywhere in display memory, allowing effective use of unused address space. • Up to 8 x 8-pixel characters (M2 = 0) or 8 x 16 characters (M2 = 1) • Up to 256 characters if mapped at F000H to FFFFH (64 if used together with character generator ROM) • Can be mapped anywhere in display memory address space if used with the character generator ROM • Mapped into the display memory address space at F000H to F7FFH if not used with the character generator ROM (more than 64 characters are in the CG RAM). Set SAG0 to F000H and M1 to zero when defining characters number 193 upwards. RAiO TECHNOLOGY INC. 52/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 7-15 CG Memory Allocation Since the RA8835A series uses 8-bit character codes, it can handle no more than 256 characters at a time. However, if a wider range of characters is required, character generator memory can be bankswitched using the CGRAM ADR command. Figure 7-27: Internal and External Character Mapping Note that there can be no more than 64 characters per bank. Table-21: Character Mapping Item Parameter Internal/external character generator M0 selection 1 to 8 pixels M2 = 0 Character field 9 to 16 pixels M2 = 1 height Greater than 16 pixels Graphics mode (8 bits ´1 line) Internal CG ROM/RAM select Automatic External CG ROM/RAM select CG RAM bit 6 correction M1 CG RAM data storage address External CG ROM Address 192 characters or less More than 192 characters RAiO TECHNOLOGY INC. Specified with CG RAM ADR command Remarks Determined by the character code Can be moved anywhere in the display memory address space Other than the area of Figure 7-2A Set SAG to F000H and overly SAG and the CG ROM table 53/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 7-16 Setting Character Generator Address The CG RAM addresses in the VRAM address space are not mapped directly from the address in the SAG register. The data to be displayed is at a CG RAM address calculated from SAG + character code + ROW select address. This mapping is shown in Table-22A and –22B. SAG Character code +ROW select address CG RAM address Table-22A: Character Fonts, Number of Lines ≤ 8 (M2 = 0, M1 = 0) A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R2 R1 R0 VA8 VA7 VA6 VA5 VA4 VA3 VA2 VA1 VA0 VA15 VA14 VA13 VA12 VA11 VA10 VA9 Table-22B: Character Fonts, 9 ≤ Number of Lines ≤ 16 (M2 = 1, M1 = 0) A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 SAG Character code +ROW select address CG RAM address A1 A0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R3 R2 R1 R0 VA15 VA14 VA13 VA12 VA11 VA10 VA9 VA8 VA7 VA6 VA5 VA4 VA3 VA2 VA1 VA0 Figure 7-28: Row Select Address Note: Lines = 1: lines in the character bitmap ≤ 8 Lines = 2: lines in the character bitmap ≤ 9 7-16-1 M1 = 1 The RA8835A series automatically converts all bits set in bit 6 of character code for CG RAM 2 to zero. Because of this, the CG RAM data areas become contiguous in display memory. When writing data to CG RAM: • Calculate the address as for M1 = 0. • Change bit 6 of the character code from “1” to “0”. RAiO TECHNOLOGY INC. 54/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 7-16-2 CG RAM Addressing Example • Define a pattern for the “A” in Figure 7-9. • The CG RAM table start address is 4800H. • The character code for the defined pattern is 80H (the first character code in the CG RAM area). As the character code table in Figure 7-29 shows, codes 80H to 9FH and E0H to FFH are allocated to the CG RAM and can be used as desired. 80H is thus the first code for CG RAM. As characters cannot be used if only using graphics mode, there is no need to set the CG RAM data. Table-23: Character Data Example CGRAM AD 5CH Reverse the CG RAM address calculation to calculate SAG P1 00H P2 40H CSRDIR 4CH CSRW 46H P1 00H P2 48H MWRITE 42H P 70H Write ROW 0 data P2 88H Write ROW 1 data P3 88H Write ROW 2 data P4 88H Write ROW 3 data P5 F8H Write ROW 4 data P6 88H Write ROW 5 data P7 88H Write ROW 6 data P8 00H Write ROW 7 data P8 00H Write ROW 8 data ↓ ↓ P16 00H RAiO TECHNOLOGY INC. Set cursor shift direction to right CG RAM start address is 4800H ↓ Write ROW 15 data 55/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 7-17 Character Codes The following figure shows the character codes and the codes allocated to CG RAM. The CG RAM if not using the internal ROM can use all codes. Upper 4bites Lower 4bites 0 1 2 3 4 5 6 7 0 @ P ` p 1 ! 1 A Q a q 2 “ 2 B R b r 3 # 3 C S c s 4 $ 4 D T d t 5 & 5 E U e u 6 % 6 F V f v 7 ' 7 G W g w 8 ( 8 H X h x ) 9 I Y i y A * : J Z j z B + ; K [ k { C , < L ¥ l ¦ D . = M ] m } E - > N ^ n → F / ? O _ o ← 0 9 8 9 CG RAM 1 A B C D E F CG RAM2 M1=0 M1=1 Figure 7-29: On-chip Character Codes RAiO TECHNOLOGY INC. 56/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 8. Application Notes 8-1 Initialization Parameters The parameters for the initialization commands must be determined first. Square brackets around a parameter name indicate the number represented by the parameter, rather than the value written to the parameter register. For example, [FX] = FX + 1. 8-1-1 System Set Instruction and Parameters ◎ FX The horizontal character field size is determined from the horizontal display size in pixels [VD] and the number of characters per line [VC]. [VD] ≤ [FX] [VC] ◎ C/R C/R can be determined from VC and FX. [C/R] = RND( [FX] ) × [VC] 8 Where RND(x) denotes ´ rounded up to the next highest integer. [C/R] is the number of bytes per line, not the number of characters. ◎ TC/R TC/R must satisfy the condition [TC/R] ≥ [C/R] + 4 . ◎ fOSC and fFR Once TC/R has been set, the frame frequency, fFR, and lines per frame [L/F] will also have been set. The lower limit on the oscillator frequency fOSC is given by: fOSC ≥ ([TC/R] + 1) × 9 × ([L/F] + 1) × fFR ◎ If no standard crystal close to the calculated value of fOSC exists, a higher frequency crystal can be used and the value of TC/R revised using the above equation. ◎ Symptoms of an incorrect TC/R setting are listed below. If any of these appears, check the value of TC/R and modify it if necessary. • Vertical scanning halts and a high-contrast horizontal line appears. • All pixels are on or off. • The LP output signal is absent or corrupted. • The display is unstable. RAiO TECHNOLOGY INC. 57/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller Table-24: RAiO LCD Unit Example Parameters Product name and resolution (X ´Y) 256 x 64 512 x 64 256 x 128 512 x 128 [FX] [FX] = 6 pixels: 256 / 6 = 42 remainder 4 = 4 blank pixels [FX] = 6 pixels: 512 / 6 = 85 remainder 2 = 2 blank pixels [FX] = 8 pixels: 256 / 8 = 32 remainder 0 = no blank pixels [FX] = 10 pixels: 512 / 10 = 51 remainder 2 = 2 blank pixels [FY] 8 or 16, depending on the screen 8 or 16, depending on the screen 8 or 16, depending on the screen 8 or 16, depending on the screen [C/R] [C/R] = 42 = 2AH bytes: C/R = 29H. When using HDOT SCR, [C/R] = 43 bytes [C/R] = 85 = 55H bytes: C/R = 54H. When using HDOT SCR, [C/R] = 86 bytes [C/R] = 32 = 20H bytes: C/R = 19H. When using HDOT SCR, [C/R] = 33 bytes [C/R] = 102 = 66H bytes: C/R = 65H. When using HDOT SCR, [C/R] = 103 bytes TC/R fOSC (MHz) See Note 2. 2DH 1.85 58H 3.59 22H 2.90 69H 8.55 Notes: 1. The remainder pixels on the right-hand side of the display are automatically blanked by the RA8835A. There is no need to zero the display memory corresponding to these pixels. 2. Assuming a frame frequency of 60 Hz. RAiO TECHNOLOGY INC. 58/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 8-1-2 Initialization Example The initialization example shown in Figure 8-1 is for a RA8835A series with an 8-bit microprocessor interface bus and a display unit (320 x 240 pixels). Figure 8-1: Initialization Procedure Note: Set the cursor address to the start of each screen’s layer memory, and use MWRITE to fill the memory with space characters, 20H (text screen only) or 00H (graphics screen only). Determining which memory to clear is explained in Section 8-1-3. RAiO TECHNOLOGY INC. 59/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller No. 1 2 3 4 Table-25: Initialization Procedure Command Operation Power-up Supply SYSTEM SET C = 40H P1 = 30H M0: Internal CG ROM M1: CG RAM is 32 characters maximum M2: 8 lines per character W/S: Two-panel drive IV: No top-line compensation P2 = 87H FX: Horizontal character size = 8 pixels WF: Two-frame AC drive P3 = 07H FY: Vertical character size = 8 pixels P4 = 27H C/R: 39 display addresses per line P5 = 2FH TC/R: Total address range per line = 47 fOSC = 8.0 MHz, fFR = 70 Hz P6 = EFH L/F: 239 display lines AP: Virtual screen horizontal size is 40 P7 = 28H addresses P8 = 00H SCROLL C = 44H P1 = 00H First screen block start address P2 = 00H Set to 0000H P3 = F0H Display lines in first screen block = 240 P4 = 80H Second screen block start address P5 = 25H Set to 1000H P6 = F0H Display lines in second screen block = 240 P7 = 00H Third screen block start address P8 = 4BH Set to 4B00H P9 = 00H Fourth screen block start address P10 = 00H Set to 0000H Display memory 5 HDOT SCR C = 5AH P1 = 00H (SAD1) 0000H 1st display memory page (SAD2) 2580H 2nd display memory page (SAD3) 4B00H 3rd display memory page (SAD4) 0000H 4th display memory page Set horizontal pixel shift to zero (continued) RAiO TECHNOLOGY INC. 60/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller No. 6 7 8 9 Table-25: Initialization Procedure (continued) Command Operation OVLAY C = 5BH P1 = 01H MX 1, MX 0: Inverse video superposition DM 1: First screen block is text mode DM 2: Third screen block is text mode DISP ON/OFF C = 58H D: Display OFF P1 = 56H FC1, FC0: Flash cursor at 2 Hz FP1, FP0: First screen block ON FP3, FP2: Second and fourth screen blocks ON FP5, FP4: Third screen block ON Fill first screen layer memory with 20H (space Clear data in first layer character) Fill second screen layer memory with 00H Clear data in second layer (blank data) Display Character code in every position 1st layer Black code in every position 2nd layer 10 11 CSRW C = 46H P1 = 00H P2 = 00H CSR FORM C = 5DH P1 = 04H P2 = 86H 12 DISP ON/OFF C = 59H Set cursor to start of first screen block CRX: Horizontal cursor size = 5 pixels CRY: Vertical cursor size = 7 pixels CM: Block cursor Display ON Display 13 CSR DIR C = 4CH Set cursor shift direction to right (continued) RAiO TECHNOLOGY INC. 61/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller No. 14 15 16 17 18 19 Table-25: Initialization Procedure (continued) Command Operation MWRITE C = 42H P1 = 20H ‘‘ P2 = 52H ‘R’ P3 = 41H ‘A’ P4 = 49H ‘I’ P5 = 4FH ‘O’ CSRW C = 46H P1 = 00H P2 = 10H CSR DIR C = 4FH MWRITE C = 42H P1 = FFH ↓ P9 = FFH CSRW C = 46H P1 = 01H P2 = 10H MWRITE C = 42H P1 = FFH Set cursor to start of second screen block Set cursor shift direction to down Fill a square to the left of the ‘E’ Set cursor address to 1001H Fill in the second screen block in the second column of line 1 ↓ P9 = FFH (continued) RAiO TECHNOLOGY INC. 62/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller Table-25: Initialization Procedure (continued) Command Operation Repeat operations 18 and 19 to fill in the CSRW background under ‘RAIO’ No. 20 ↓ 29 MWRITE 30 CSRW 31 C = 46H P1 = 00H P2 = 01H CSR DIR C = 4CH MWRITE C = 42H 32 Set cursor to line three of the first screen block Set cursor shift direction to right Inverse display P1 = 44H RAIO ‘D’ Dot matrix LCD P2 = 6FH P3 = 74H P4 = 20H P5 = 4DH P6 = 61H P7 = 74H P8 = 72H P9 = 69H P10 = 78H P11 = 20H P12 = 4CH P13 = 43H P14 = 44H RAiO TECHNOLOGY INC. ‘o’ ‘t’ ‘’ ‘M’ ‘a’ ‘t’ ‘r’ ‘i’ ‘x’ ‘’ ‘L’ ‘C’ ‘D’ 63/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 8-1-3 Display Mode Setting Example 1: combining text and graphics ◎ Conditions 320 x 200 pixels, single-panel drive (1/200 duty cycle) First layer: text display Second layer: graphics display 8 x 8-pixel character font CG RAM not required ◎ Display Memory Allocation First layer (text): 320/8 = 40 characters per line, 200/8 = 25 lines. Required memory size = 40 x 25 = 1000 bytes. Second layer (graphics): 320/8 = 40 characters per line, 200/1 = 200 lines. Required memory size = 40 x 200 = 8000 bytes. Figure 8-2: Character Over Graphics Layers ◎ Register Setup Procedure SYSTEM SET TC/R calculation C = 40H P1 = 30H fOSC = 6 MHz P2 = 87H fFR = 70 Hz P3 = 07H P4 = 27H (1/6) x 9 x [TC/R] x 200 = 1/70 P5 = 2FH [TC/R] = 48, so TC/R = 2FH P6 = C7H P7 = 28H P8 = 00H SCROLL C = 44H P1 = 00H P2 = 00H P3 = C8H P4 = E8H P5 = 03H P6 = C8H P7 = XH P8 = XH P9 = XH P10 = XH CSR FORM C = 5DH RAiO TECHNOLOGY INC. 64/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller P1 = 04H P2 = 86H HDOT SCR C = 5AH P1 = 00H OVLAY C = 5BH P1 = 00H DISP ON/OFF C = 59H P1 = 16H X = Don’t care 8-1-4 Display Mode Setting Example 2: combining graphics and graphics ◎ Conditions 320x200 pixels, single-panel drive (1/ 200 duty cycle) First layer: graphics display Second layer: graphics display ◎ Display Memory Allocation First layer (graphics): 320/8 = 40 characters per line, 200/1 = 200 lines. Required memory size = 40x200 = 8000 bytes. Second layer (graphics): 320/8 = 40 characters per line, 200/1 = 200 lines. Required memory size = 8000 bytes. 1F40H 2nd graphics layer (8000 bytes) 0000H 1st graphics layer (8000 bytes) 3E7FH 1F3FH Figure 8-3: Two Layer Graphics ◎ Register Setup Procedure SYSTEM SET TC/R calculation C = 40H P1 = 30H fOSC = 6 MHz P2 = 87H fFR = 70 Hz P3 = 07H P4 = 27H (1/6) x 9 x [TC/R] x 200 = 1/70 P5 = 2FH [TC/R] = 48, so TC/R = 2FH P6 = C7H P7 = 28H RAiO TECHNOLOGY INC. 65/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller P8 = 00H SCROLL C = 44H P1 = 00H P2 = 00H P3 = C8H P4 = 40H P5 = 1FH P6 = C8H P7 = XH P8 = XH P9 = XH P10 = XH CSR FORM C = 5DH P1 = 07H P2 = 87H HDOT SCR C = 5AH P1 = 00H OVLAY C = 5BH P1 = 0CH DISP ON/OFF C = 59H P1 = 16H X = Don’t care 8-1-5 Display Mode Setting Example 3: combining three graphics layers ◎ Conditions 320x200 pixels, single-panel drive (1/200 duty cycle) First layer: graphics display Second layer: graphics display Third layer: graphics display ◎ Display Memory Allocation All layers (graphics): 320/8 = 40 characters per line, 200/1 = 200 lines. Required memory size = 40x200 = 8000 bytes. RAiO TECHNOLOGY INC. 66/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 3E80H 3rd graphics layer (8000 bytes) 1F40H 2nd graphics layer (8000 bytes) 5DBFH 0000H 1st graphics layer (8000 bytes) 3E7FH 1F3FH Figure 8-4: Three Layer Graphics ◎ Register Setup Procedure SYSTEM SET TC/R calculation C = 40H P1 = 30H fOSC = 6 MHz P2 = 87H fFR = 70 Hz P3 = 07H P4 = 27H (1/6) x 9 x [TC/R] x 200 = 1/70 P5 = 2FH [TC/R] = 48, so TC/R = 2FH P6 = C7H P7 = 28H P8 = 00H SCROLL C = 44H P1 = 00H P2 = 00H P3 = C8H P4 = 40H P5 = 1FH P6 = C8H P7 = 80H P8 = 3EH P9 = XH P10 = XH CSR FORM C = 5DH P1 = 07H P2 = 87H HDOT SCR C = 5AH P1 = 00H OVLAY C = 5BH P1 = 1CH RAiO TECHNOLOGY INC. 67/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller DISP ON/OFF C = 59H P1 = 16H X = Don’t care 8-2 System Overview Figure 8-5 shows the RA8835A series in a typical system. The microprocessor issues instructions to the RA8835A series, and the RA8835A series drives the LCD panel and may have up to 64KB of display memory. Since all of the LCD control circuits are integrated onto the RA8835A series, few external components are required to construct a complete medium- resolution liquid crystal display. RA8835A RA8835 Character generator Microprocessor Display Address control Driver control Display memory Address bus Exter character Generator memory Display memory Display memory data bus LCD unit Drive bus Mainmemory X drive Y drive Data bus Address bus Control bus X drive X drive LCD panel Figure 8-5: System Block Diagram RAiO TECHNOLOGY INC. 68/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 8-3 System Interconnection 10MHz crystal A0 A0 Micro processor A1 To A7 XG CS Decoder XD VA13 To VA15 VCE HC138 Y7 A Y6 B to C Y0 CS 7 CS 6 to CS 0 VRD VA0 RA8835A RA8835 IORQ To VA 12 D0 to D7 RD RD WR WR RESET A0 to A 12 WE (RAM 2) CS 1 CS 2 D0 to D 7 OE D0 to D 7 OE A0 to A 11 (CGROM ) OE CE D0 to D 7 VD0 To VD7 XECL XSCL LP WF YDIS YD YSCL RESET RESET XD0 To XD3 A0 to A 12 WE (RAM 1) CS 1 CS 2 LAT DI LCD INH FR YSCL POFF E0 V3 FR EI E0 FR EI E0 LP XSCL ECL D0 to D3 FR EI V2 LP XSCL ECL D0 to D3 V REG V1 LP XSCL ECL D0 to D3 Power Supply converter V4 V5 LCD UNIT Figure 8-6: System Interconnection Diagram The RA8835A series layered screens and flexible scrolling facilities support a range of display functions and reduces the load on the controlling microprocessor when displaying underlining, inverse display, text overlaid on graphics or simple animation. These facilities are supported by the RA8835A series ability to divide display memory into up to four different areas. ◎ Character code table Contains character codes for text display Each character requires 8 bits Table mapping can be changed by using the scroll start function ◎ Graphics data table Contains graphics bitmaps Word length is 8 bits Table mapping can be changed RAiO TECHNOLOGY INC. 69/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller ◎ CG RAM table Character generator memory can be modified by the external microprocessor Character sizes up to 8x16-pixels (16 bytes per character) Maximum of 64 characters Table mapping can be changed ◎ CG ROM table Used when the internal character generator is not adequate Can be used in conjunction with the internal character generator and external character generator RAM Character sizes up to 8x16-pixels (16 bytes per character) Maximum of 256 characters Fixed mapping at F000H to FFFFH RAiO TECHNOLOGY INC. 70/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 8-4 Smooth Horizontal Scrolling Figure 8-7 illustrates smooth display scrolling to the left. When scrolling left, the screen is effectively moving to the right, over the larger virtual screen. Instead of changing the display start address SAD and shifting the display by eight pixels, smooth scrolling is achieved by repeatedly changing the pixelshift parameter of the HDOT SCR command. When the display has been scrolled seven pixels, the HDOT SCR pixel-shift parameter is reset to zero and SAD incremented by one. Repeating this operation at a suitable rate gives the appearance of smooth scrolling. To scroll the display to the right, the reverse procedure is followed. When the edge of the virtual screen is reached, the microprocessor must take appropriate steps so that the display is not corrupted. The scroll must be stopped or the display modified. Note that the HDOT SCR command cannot be used to scroll individual layers. HDOT SCR parameter SAD SAD+1 SAD+2 P1=00H Magnified AP P1=01H SAD=SAD Display P1=02H C/R P1=03H Virtual screen P1=07H P1=00H SAD=SAD+1 Not visible Visible Figure: 8-7 HDOT SCR Example Note: The response time of LCD panels changes considerably at low temperatures. Smooth scrolling under these conditions may make the display difficult to read. RAiO TECHNOLOGY INC. 71/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 8-5 Layered Display Attributes RA8835A series incorporates a number of functions for enhanced displays using monochrome LCD panels. It allows the display of inverse characters, half-intensity menu pads and flashing of selected screen areas. These functions are controlled by the OVLAY and DISP ON/OFF commands. A number of means can be used to achieve these effects, depending on the display configuration. These are listed below. Note, however, that not all of these can be used in the one layer at the same time. Attribute MX1 MX0 0 1 Reverse 1 0 1 0 1 0 1 0 0 0 1 0 0 1 1 1 Half-tone Local flashing Ruled line Combined layer display 1st layer display IV RAIO IV RAIO ME Yes,No ME Yes, No BL Error BL RL LINE LINE RL 2ndt layer display Error LINE LINE Figure 8-8: Layer Synthesis 8-5-1 Inverse Display The first layer is text, the second layer is graphics. 1. CSRW, CSDIR, MWRITE Write is into the graphics screen at the area to be inverted. 2. OVLAY: MX0 = 1, MX1 = 0 Set the combination of the two layers to Exclusive-OR. 3. DISP ON/OFF: FP0 = FP1 = 1, FP1 = FP3 = 0. Turn on layers 1 and 2. RAiO TECHNOLOGY INC. 72/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 8-5-2 Half-tone Display The FP parameter can be used to generate half-intensity display by flashing the display at 17 Hz. Note that this mode of operation may cause flicker problems with certain LCD panels. SAD1 Half-tone SAD2 AB AB + 1st layer 2nd layer Combined layer display Figure 8-9: Half-tone Character and Graphics 8-5-2-1 Menu pad display 1. OVLAY: P1 = 00H 2. DISP ON/OFF: P1 = 34H 8-5-2-2 Graph display To present two overlaid graphs on the screen, configure the display as for the menu bar display and put one graph on each screen layer. The difference in contrast between the half- and fullintensity displays will make it easy to distinguish between the two graphs and help create an attractive display. 1. OVLAY: P1 = 00H 2. DISP ON/OFF: P1 = 34H 8-5-3 Flashing Area 8-5-3-1 Small area To flash selected characters, the MPU can alternately write the characters as character codes and blank characters at intervals of 0.5 to 1.0 seconds. 8-5-3-1 Large area Divide layer 1 and layer 2 into two screen blocks each, layer 2 being divided into the area to be flashed and the remainder of the screen. Flash the layer 2 screen block at 2 Hz for the area to be flashed and combine the layers using the OR function. ABC ABC XYZ XYZ Figure 8-10: Localized Flashing RAiO TECHNOLOGY INC. 73/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 8-6 16 x 16-dot Graphic Display 8-6-1 Command Usage This example shows how to display 16 x 16-pixel characters. The command sequence is as follows: CSRW Set the cursor address. CSRDIR Set the cursor auto-increment direction. MWRITE Write to the display memory. 8-6-2 Kanji Character Display The program for writing large characters operates as follows: 1. The microprocessor reads the character data from its ROM. 2. The microprocessor sets the display address and writes to the VRAM. The flowchart is shown in Figure 8-13. A0 = 0 0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH A0 = 1 O8 O7 O6 O5 O4 O3 O2 O1 O8 O7 O6 O5 O4 O3 O2 O1 (2) (1) (4) (3) (6) (5) (8) (7) (10) (9) (12) (11) (14) (13) (16) (15) (18) (17) (20) (19) (22) (21) (24) (23) (26) (25) (28) (27) (30) (29) (32) (31) 1st column (n) shows the CG ROM data readout order 2nd column (6) (4) (2) (19) (17) (15) (13) (11) (9) (7) (5) (3) (1) Data held in the microprocessor memory 2nd column memory area (4) (2) 1st column memory area (3) (1) Data written into the RA8835 display memory Figure 8-11: Graphics Address Indexing RAiO TECHNOLOGY INC. 74/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller Figure 8-12: Graphics Bit Map Figure 8-13: 16 x16-dot Display Flowchart Using an external character generator ROM, and 8 x 16 pixel font can be used, allowing a 16 x 16pixel character to be displayed in two segments. The external CG ROM EPROM data format is described in Section 7-9. This will allow the display of up to 128, 16 x 16-pixel characters. If CG RAM is also used, 96 fixed characters and 32 bank-switchable characters can also be supported. RAiO TECHNOLOGY INC. 75/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 8-7 Internal Character Generator Font Character code bits 0 to 3 0 1 2 3 4 5 6 7 8 9 A B C D E F 2 3 Character code bit 4 to 7 4 5 6 7 A B C D 1 Figure 8-14: On-chip Character Set Note: The shaded positions indicate characters that have the whole 6 x 8 bitmap blackened. RAiO TECHNOLOGY INC. 76/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 9. Package Dimensions QFP-60 pin 24.8 + 0.25 20.0 + 0.1 18.35 + 0.2 36 54 30 RA8835AP3N 1 29 Index 1.82+ 0.1 5 6 14.0 + 0.1 60 18.8 + 0.25 35 12.35 + 0.2 1.65+ 0.1 55 24 23 15 0.82 + 0.1 0.82 + 0.1 0.15 + 0.05 2.7 + 0.12 1.82 + 0.1 1.0 + 0.1 0.35 + 0.1 0 to 7 ° 1.35+0.15 2.4 Figure 9-1: RA8835AP3N (Unit: mm) T Q F P-60 pin 17.2 + 0.4 14.0 + 0.3 45 31 46 17.2+ 0.4 R A 8835A P 4N 14.0+ 0.3 11.55 + 0.3 30 Index 60 16 0.0 1 1.62 + 0.0 1 2.7+ 0.2 0.15 + 0.05 0.82 + 1.62 + 0.0 1 1 0.8+ 15 0.1 5 0.35+ 0.0 5 0 to 7 o 1.6 0.8+ 0.3 Figure 9-2: RA8835AP4N (Unit: mm) Note: Both of the RA8835AP3N and RA8835AP4N are use “lead-free” package for ROHS compliance. RAiO TECHNOLOGY INC. 77/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 10. Specifications 10-1 Absolute Maximum Ratings Parameter Symbol Rating Unit Supply voltage range VDD –0.3 to 7.0 V Input voltage range VIN –0.3 to VDD+ 0.3 V Power dissipation PD 300 mW Operating temperature range Topg –20 to 75 °C Storage temperature range Tstg –65 to 150 °C Tsolder 260 °C Soldering temperature (10 seconds). See note 1. Notes: 1. The humidity resistance of the flat package may be reduced if the package is immersed in solder. Use a soldering technique that does not heatstress the package. 2. If the power supply has a high impedance, a large voltage differential can occur between the input and supply voltages. Take appropriate care with the power supply and the layout of the supply lines. (See Section 10-2) 3. All supply voltages are referenced to VSS = 0V. RAiO TECHNOLOGY INC. 78/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 10-2 DC Characteristic VDD = 4.5 to 5.5V, VSS = 0V, Ta = –20 to 75℃ Parameter Symbol Rating Condition Unit Min. Typ. Max. V Supply voltage VDD 4.5 5.0 5.5 V Register data retention voltage VOH 2.0 — 6.0 V Input leakage current ILI VI= VDD. See note 5. — 0.05 2.0 μA Output leakage current ILO VI= VSS. See note 5. — 0.10 5.0 μA Operating supply current Iopr See note 4. — 3.5 8 mA Quiescent supply current IQ Sleep mode, VOSC1= V( CS )= V( RD )= VDD — 0.05 20.0 μA 1.0 — 18.0 MHz 1.0 — 18.0 MHz 0.5 1.0 3.0 MΩ Oscillator frequency fOSC External clock frequency fCL Oscillator feedback resistance Rf Measured at crystal, 47.5% duty cycle. See note 6. Input HIGH-level input voltage VIHC See note 1, 2 0.5 VDD — VDD V LOW-level input voltage VILC See note 1, 2 VSS — 0.2 VDD V VDD – 0.4 — — V — — VSS + 0.4 V Output HIGH-level output voltage VOHC LOW-level output voltage VOLC IOH= 4.0 mA. See note 1, 2 IOL= -2 mA. See note 1, 2 Schmitt-trigger Rising-edge threshold voltage Falling-edge threshold voltage VT+ See note 3. 0.5 VDD 0.7 VDD 0.8 VDD V VT– See note 3. 0.2 VDD 0.3 VDD 0.5 VDD V Notes: 1. CS , RD , WR , A0, SEL1, SEL2 and TEST are inputs. VA0 to VA15, ( VRD ), ( VWR ), ( VCE ), YD, XD0 to XD3, XSCL, LP, WF, YDIS are outputs. 2. D0 to D7, VD0 to VD7 are Bi-direction. 3. The RES are Schmitt-trigger inputs. The pulse width on RES must be at least 10*tc. Note that pulses of more than a few seconds will cause DC voltages to be applied to the LCD panel. 4. fOSC = 10 MHz, no load (no display memory), internal character generator, 256x200 pixel display. The operating supply current can be reduced by approximately 1mA by setting both CLO and the display OFF. 5. VD0 to VD7 and D0 to D7 have internal feedback circuits so that if the inputs become highimpedance, the input state immediately prior to that is held. Because of the feedback circuit, input current flow occurs when the inputs are in an intermediate state. 6. Because the oscillator circuit input bias current is in the order of uA, design the printed circuit board so as to reduce leakage currents. RAiO TECHNOLOGY INC. 79/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller VDD = 2.7 to 4.5V, VSS = 0V, Ta = –20 to 75℃ Parameter Symbol Rating Condition Unit Min. Typ. Max. V Supply voltage Register data retention voltage Input leakage current VDD 2.7 3.3 4.5 V VOH 2.0 — 6.0 V ILI VI = VDD. See note 5. — 0.05 2.0 μA Output leakage current ILO — 0.10 5.0 μA Operating supply current Iopr VI = VSS. See note 5. VDD = 3.5 V. See note 4. See note 4. Sleep mode, VOSC1= V( CS )= V( RD )= VDD — 3.5 — — — 7.0 — 0.05 20.0 μA 1.0 — 16.0 MHz 1.0 — 16.0 MHz 0.7 — 3.0 MΩ Quiescent supply current IQ mA Oscillator frequency fOSC External clock frequency Oscillator feedback resistance Input fCL HIGH-level input voltage VIHC See note 1, 2 0.5 VDD — VDD V LOW-level input voltage VILC See note 1, 2 VSS — 0.2 VDD V VDD – 0.4 — — V — — VSS + 0.4 V Rf Measured at crystal, 47.5% duty cycle. See note 6. Output IOH= 4.0 mA. See note 1, 2 IOL= -2 mA. See note 1, 2 HIGH-level output voltage VOHC LOW-level output voltage VOLC Schmitt-trigger Rising-edge threshold voltage Falling-edge threshold voltage VT+ See note 3. 0.5 VDD 0.7 VDD 0.8 VDD V VT– See note 3. 0.2 VDD 0.3 VDD 0.5 VDD V Notes 1. CS , RD , WR , A0, SEL1, SEL2 and TEST are inputs. VA0 to VA15, ( VRD ), ( VWR ), ( VCE ), YD, XD0 to XD3, XSCL, LP, WF, YDIS are outputs. 2. D0 to D7, VD0 to VD7 are Bi-direction pins. 3. The RES are Schmitt-trigger inputs. The pulse width on ( RES ) must be at least 10*tc. Note that pulses of more than a few seconds will cause DC voltages to be applied to the LCD panel. 4. fOSC = 10 MHz, no load (no display memory), internal character generator, 256x200 pixel display. The operating supply current can be reduced by approximately 1mA by setting both CLO and the display OFF. 5. VD0 to VD7 and D0 to D7 have internal feedback circuits so that if the inputs become highimpedance, the input state immediately prior to that is held. Because of the feedback circuit, input current flow occurs when the inputs are in an intermediate state. 6. Because the oscillator circuit input bias current is in the order of μA, design the printed circuit board so as to reduce leakage currents. RAiO TECHNOLOGY INC. 80/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 10-3 Timing Diagrams 10-3-1 8080 Family Interface Timing Ta = –20 to 75°C Signal Symbol A0, CS tAH8 VDD = 4.5 to 5.5V Parameter Address hold time VDD = 2.7 to 4.5V Min. Max. Min. Max. 10 — 10 — Unit ns tAW8 Address setup time 0 — 0 — ns WR , tCYC8 System cycle time note. — note. — ns RD tCC Strobe pulse width 120 — 150 — ns tDS8 Data setup time 120 — 120 — ns tDH8 Data hold time 5 RD access time Output disable time — 50 5 — — — 80 ns 10 50 10 55 ns D0 to D7 tACC8 tOH8 Condition CL = 100pF ns Note: For memory control and system control commands: tCYC8 = 2tC + tCC + tCEA + 75 > tACV + 245 For all other commands: tCYC8 = 4tC + tCC + 30 RAiO TECHNOLOGY INC. 81/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 10-3-2 6800 Family Interface Timing E tCYC6 tAW6 tEW R/W tAH6 A0, CS tDH6 tDS6 D0 to D7 (write) tACC6 tOH6 D0 to D7 (Read) Ta = –20 to 75°C Signal Symbol A0, CS , R/( W ) D0 to D7 E VDD = 4.5 to 5.5V Parameter VDD = 2.7 to 4.5V Unit Min. Max. Min. Max. System cycle time note. — note. — ns tAW6 Address setup time 0 — 10 — ns tAH6 Address hold time 0 — 0 — ns tDS6 Data setup time 100 — 120 — ns tCYC6 tDH6 Data hold time 0 — 0 — ns tOH6 Output disable time 10 50 10 75 ns tACC6 Access time — 85 — 130 ns 120 — 150 — ns tEW Enable pulse width Condition CL = 100 pF Note: For memory control and system control commands: tCYC6 = 2tC + tEW + tCEA + 75 > tACV + 245 For all other commands: tCYC6 = 4tC + tEW + 30 RAiO TECHNOLOGY INC. 82/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 10-3-3 Display Memory Read Timing EXT¢0 tC tCE tW tW VCE VA0 to VA15 tCYR tASC tAHC VR / W tRCH tCEA tRCS tCE3 tOH2 tACV VD0 to VD7 Ta = –20 to 75℃ Signal Symbol EXT Φ0 tC tW VCE tCE tCYR VA0 to VA15 tASC VDD = 4.5 to 5.5V Parameter Clock period VCE HIGH-level pulse width VCE LOW-level pulse width Read cycle time Address setup time to falling edge of VDD = 2.7 to 4.5V Unit Min. Max. Min. Max. 55.5 — 62.5 — ns tC – 50 — tC – 50 — ns 2tC – 30 — 2 tC – 30 — ns 3tC — 3tC — ns tC – 70 — tC – 100 — ns 2 tC – 30 — 2tC – 40 — ns Condition VCE tAHC Address hold time from falling edge of VCE tRCS VRD tRCH Read cycle setup time to falling edge of VCE Read cycle hold time from rising edge of CL = 100 pF tC – 45 — tC – 60 — ns 0.5tC — 0.5tC — ns — — 3tC – 115 2tC – 90 Ns Ns VCE tACV tCEA VD0 to VD7 tOH2 tCE3 RAiO TECHNOLOGY INC. Address access time VCE access time Output data hold time VCE to data off time 83/88 — — 3tC – 100 2tC – 80 0 — 0 — ns 0 — 0 — ns www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 10.3-4 Display Memory Write Timing tC EXT¢ O VA0 to VA15 tW VCE t CE t ASC t CA t AHC t AS t W SC tW HC t AH2 VR/W t DSC t DH2 t DHC VD0 to VD7 Ta = –20 to 75℃ Signal Symbol EXT Φ0 tC Clock period tW VCE HIGH-level pulse width VCE tCE tCYW tAHC tASC VA0 to VA15 tCA tAS tAH2 Parameter VCE LOW-level pulse width Write cycle time Address hold time from falling edge of VCE VDD = 4.5 to 5.5V Min. Max. 55.5 — VDD = 2.7 to 4.5V Min. Max. 62.5 — tC – 50 — tC – 50 — ns 2tC – 30 — 2tC – 30 — ns 3tC — 3tC — ns 2tC – 30 — 2tC – 40 — ns tC – 70 — tC – 110 — ns 0 — 0 — ns 0 — 0 — ns 10 — 10 — ns tC – 80 — tC – 115 — ns 2tC – 20 — 2tC – 20 — ns tC – 85 — tC – 125 — ns 2tC – 30 — 2tC – 30 — ns 5 50 5 50 ns Address setup time to falling edge of VCE Address hold time from rising edge of Unit Condition ns VCE Address setup time to falling edge of VWR Address hold time from rising edge of CL = 100 pF VWR tWSC VWR tWHC VD0 to VD7 Write setup time to falling edge of VCE Write hold time from tDSC falling edge of VCE Data input setup time to falling edge of tDHC Data input hold time from falling edge of tDH2 VCE VCE Data hold time from rising edge of VWR Note: VD0 to VD7 are latching input/outputs. While the bus is high impedance, VD0 to VD7 retain the write data until the data read from the memory is placed on the bus. RAiO TECHNOLOGY INC. 84/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 10-3-5 Sleep In Command Timing VCE WR (Command input) SYSTEM SET write SLEEP IN write tWRL tWRD YDIS Ta = –20 to 75°C Signal Symbol Parameter VDD = 4.5 to 5.5V Min. Max. VDD = 2.7 to 4.5V Min. Max. Unit tWRD VCE falling-edge delay time note 1. — note 1. — ns tWRL YDIS falling-edge delay time — note 2. — note 2. ns WR Condition CL = 100 pF Notes: 1. tWRD = 18tC + tOSS + 40 (tOSS is the time delay from the sleep state until stable operation) 2. tWRL = 36tC x [TC/R] x [L/F] + 70 RAiO TECHNOLOGY INC. 85/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 10-3-6 External Oscillator Signal Timing tRCL tFCL tWH EXT¢0 tWL tC Ta = –20 to 75℃ Signal Symbol tRCL tFCL EXT Φ0 tWH tWL tC VDD = 4.5 to 5.5V Min. Max. Parameter External clock rise time External clock fall time External clock HIGH-level pulse width External clock LOW-level pulse width VDD = 2.7 to 4.5V Min. Max. Unit — 10 — 10 ns — 10 — 10 ns note 1. note 2. note 1. note 2. ns note 1. note 2. note 1. note 2. ns 55.5 — 62.5 — ns External clock period Condition Notes: 475 < t WH , t WL 1000 525 − t FCL ) × > t WH , t WL 1000 1. ( t C − t RCL − t FCL ) × 2. ( t C − t RCL RAiO TECHNOLOGY INC. 86/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller 10-3-7 LCD Output Timing The following characteristics are for a 1/64 duty cycle. 62 Row LP 63 64 1 2 3 4 60 61 62 63 64 1frame time YD WF WF 1lime time ROW 64 Row 1 Row 2 LP XSCL XD0 to XD3 (14)(15)(16) (1) (15)(16)(1)(2)(3) (15) (16) (1) tcx twx tr XSCL tf tDS tDH tLS XD0 to XD3 tLD tWL LP tDHY tDF WF(B) YD RAiO TECHNOLOGY INC. 87/88 www.raio.com.tw RA8835A Version 1.3 Dot Matrix LCD Controller Ta = –20 to 75℃ Signal Symbol XSCL VDD = 2.7 to 4.5V Min. Max. Unit Rise time — 30 — 40 ns Fall time — 30 — 40 ns Shift clock cycle time 2tC — 2tC — ns tC – 20 — ns tCX tC – 20 — tDH XSCL clock pulse width X data hold time 2tC – 50 — 2tC – 50 — ns tDS X data setup time 2tC – 100 — 2tC – 105 — ns tC – 20 — tC – 20 — ns 2tC – 10 — 2tC – 10 — ns tC – 20 — ns tWL Latch data setup time LP pulse width WF tDF LP delay time from XSCL Permitted WF delay YD tDHY Y data hold time tLD RAiO TECHNOLOGY INC. Max. tf tLS LP Min. tr tWX XD0 to XD3 VDD = 4.5 to 5.5V Parameter tC – 20 — tC – 20 tc+30 tC – 20 tc+30 ns 2tC – 20 — 2tC – 20 — ns 88/88 Condition CL = 100 pF www.raio.com.tw