ETC SED1335F

SED1330F/1335F/1336F
LCD Controller ICs
Technical Manual
S-MOS Systems, Inc.
September, 1995
Version 0.4
268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238
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Table of Contents
SED1330F/1335F/1336F
CONTENTS
1.0 Overview ............................................................................................................. 9
1.1 Description .................................................................................................................................. 11
1.2 Features ...................................................................................................................................... 11
1.3 Block Diagram ............................................................................................................................. 12
1.4 Pinouts ........................................................................................................................................ 14
1.4.1 SED1330FBA, 1335FBB and SED1336F0A Pinouts ............................................. 14
1.4.2 SED1330FBA and SED1335F0A Pinouts .............................................................. 14
1.5 Package Dimensions ................................................................................................................... 15
2.0 Pin Description ................................................................................................. 17
2.1 SED1330FBA/BB Pin Summary .................................................................................................. 18
2.2 SED1330F/1335F0A/0B Pin Summary ....................................................................................... 19
2.3 SED1336F0A Pin Summary ........................................................................................................ 20
2.4 Pin Functions ............................................................................................................................... 21
2.4.1 Power Supply .......................................................................................................... 21
2.4.2 Oscillator ................................................................................................................. 21
2.4.3 Microprocessor Interface ........................................................................................ 21
2.4.4 Display Memory Control ......................................................................................... 23
2.4.5 LCD Drive Signals .................................................................................................. 23
3.0 Command Description ..................................................................................... 25
3.1 The Command Set ...................................................................................................................... 27
3.2 System Control Commands ........................................................................................................ 28
3.2.1 SYSTEM SET ......................................................................................................... 28
3.2.1.1 C ........................................................................................................ 29
3.2.1.2 M0 ...................................................................................................... 29
3.2.1.3 M1 ...................................................................................................... 29
3.2.1.4 M2 ...................................................................................................... 29
3.2.1.5 W/S .................................................................................................... 29
3.2.1.6 IV ........................................................................................................ 32
3.2.1.7 T/L ...................................................................................................... 32
3.2.1.8 DR ...................................................................................................... 32
3.2.1.9 FX ...................................................................................................... 32
3.2.1.10 WF ................................................................................................... 33
3.2.1.11 FY ..................................................................................................... 33
3.2.1.12 C/R .................................................................................................... 34
3.2.1.13 TC/R ................................................................................................. 34
3.2.1.14 L/F .................................................................................................... 35
3.2.1.15 AP .................................................................................................... 35
3.2.2 SLEEP IN................................................................................................................ 36
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SED1330F/1335F/1336F
Table of Contents
3.3 Display Control Commands ......................................................................................................... 36
3.3.1 DISP ON/OFF ......................................................................................................... 36
3.3.1.1 D ........................................................................................................ 37
3.3.1.2 FC ...................................................................................................... 37
3.3.1.3 FP ...................................................................................................... 37
3.3.2 SCROLL ................................................................................................................. 37
3.3.2.1 C ........................................................................................................ 37
3.3.2.2 SL1, SL2 ............................................................................................ 38
3.3.3 CSRFORM.............................................................................................................. 42
3.3.3.1 CRX ................................................................................................... 42
3.3.3.2 CRY .................................................................................................... 42
3.3.3.3 CM ..................................................................................................... 43
3.3.4 CSRDIR .................................................................................................................. 43
3.3.5 OVLAY .................................................................................................................... 43
3.3.5.1 MX0, MX1 .......................................................................................... 43
3.3.5.2 DM1, DM2 .......................................................................................... 45
3.3.5.3 OV ...................................................................................................... 45
3.3.6 CGRAM ADR .......................................................................................................... 45
3.3.7 HDOT SCR ............................................................................................................. 45
3.3.7.1 D0 to D2 ............................................................................................. 45
3.4 Drawing Control Commands ....................................................................................................... 46
3.4.1 CSRW ..................................................................................................................... 46
3.4.2 CSRR ...................................................................................................................... 46
3.5 Memory Control Commands ....................................................................................................... 47
3.5.1 MWRITE ................................................................................................................. 47
3.5.2 MREAD ................................................................................................................... 47
4.0 Specifications ................................................................................................... 49
4.1 Absolute Maximum Ratings ......................................................................................................... 51
4.1.1 SED1330 ................................................................................................................ 51
4.1.2 SED1335/SED1336 ................................................................................................ 51
4.2 SED 1330 Electrical Characteristics............................................................................................ 52
4.3 SED1335/1336 Electrical Characteristics.................................................................................... 53
4.4 SED1330 Timing Diagrams ......................................................................................................... 54
4.4.1 System bus READ/WRITE timing I (8080) ............................................................. 54
4.4.1.1 SED1330F ......................................................................................... 54
4.4.2 System bus READ/WRITE timing II (6800) ............................................................ 55
4.4.2.1 SED1330F ......................................................................................... 55
4.4.3 Display memory READ timing ................................................................................ 56
4.4.3.1 SED1330F ......................................................................................... 56
4.4.4 Display memory WRITE timing ............................................................................... 57
4.4.4.1 SED1330F ......................................................................................... 57
4.4.5 LCD control timing .................................................................................................. 58
4.4.5.1 SED1330F ......................................................................................... 59
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Table of Contents
SED1330F/1335F/1336F
4.4.6 Oscillator timing ...................................................................................................... 60
4.4.6.1 SED1330F ......................................................................................... 60
4.4.7 Measurement circuit ............................................................................................... 61
4.5 SED1335/SED1336 AC Timing Diagrams ................................................................................... 62
4.5.1 8080 family Interface Timing ................................................................................... 62
4.5.1.1 SED1335F ......................................................................................... 62
4.5.1.2 SED1336F ......................................................................................... 63
4.5.2 6800 family Interface Timing ................................................................................... 64
4.5.2.1 SED1335F ......................................................................................... 65
4.5.2.2 SED1336F ......................................................................................... 65
4.5.3 Display Memory Read Timing ................................................................................. 66
4.5.3.1 SED1335F ......................................................................................... 66
4.5.3.2 SED1336F ......................................................................................... 67
4.5.4 Display Memory Write Timing ................................................................................. 68
4.5.4.1 SED1335F ......................................................................................... 69
4.5.4.2 SED1336F ......................................................................................... 70
4.5.5 SLEEP IN Command Timing .................................................................................. 71
4.5.5.1 SED1335F ......................................................................................... 71
4.5.5.2 SED1336F ......................................................................................... 71
4.5.6 External Oscillator Signal Timing ............................................................................ 72
4.5.6.1 SED1335F ......................................................................................... 72
4.5.6.2 SED1336F ......................................................................................... 72
4.5.7 E-1330 LCD Controller IC ........................................................................................................ 73
4.5.7.1 SED1335F ......................................................................................... 75
4.5.7.2 SED1336F ......................................................................................... 75
5.0 Display Control Functions .............................................................................. 77
5.1 Character Configuration .............................................................................................................. 79
5.2 Screen Configuration ................................................................................................................... 81
5.2.1 Screen Configuration .............................................................................................. 81
5.2.2 Display Address Scanning ...................................................................................... 81
5.2.3 Display Scan Timing ............................................................................................... 84
5.3 Cursor Control ............................................................................................................................. 85
5.3.1 Cursor Register Function ........................................................................................ 85
5.3.2 Cursor Movement ................................................................................................... 85
5.3.3 Cursor Display Layers ............................................................................................ 85
5.4 Memory to Display Relationship .................................................................................................. 87
5.5 Scrolling ....................................................................................................................................... 90
5.5.1 On-page Scrolling ................................................................................................... 90
5.5.2 Inter-page Scrolling ................................................................................................. 91
5.5.3 Horizontal Scrolling ................................................................................................. 92
5.5.4 Bidirectional Scrolling ............................................................................................. 93
5.5.5 Scroll Units.............................................................................................................. 93
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SED1330F/1335F/1336F
Table of Contents
6.0 Character Generator ........................................................................................ 95
6.1 CG Characteristics ...................................................................................................................... 97
6.1.1 Internal Character Generator .................................................................................. 97
6.1.2 External Character Generator ROM ....................................................................... 97
6.1.3 Character Generator RAM ...................................................................................... 97
6.2 CG Memory Allocation................................................................................................................. 98
6.3 Setting the Character Generator Address ................................................................................... 99
6.3.1 M1 = 1 ................................................................................................................... 100
6.3.2 CG RAM Addressing Example .............................................................................. 100
6.4 Character Codes ....................................................................................................................... 101
7.0 TV Mode (SED1336F only) ............................................................................. 103
7.1 Sync Generator Circuit Timing .................................................................................................. 105
8.0 Description of Circuit Blocks ........................................................................ 109
8.1 Microprocessor Interface ........................................................................................................... 111
8.1.1 System Bus Interface............................................................................................ 111
8.1.1.1 8080 series ...................................................................................... 111
8.1.1.2 6800 series ...................................................................................... 111
8.1.2 Microprocessor Synchronization........................................................................... 111
8.1.2.1 Display Status Indication Output For SED1336F only...................... 111
8.1.2.2 Internal Register Access .................................................................. 111
8.1.2.3 Display Memory Access ................................................................... 111
8.1.3 Interface Examples ............................................................................................... 113
8.1.3.1 Z80® to SED1330F/1335F/1336F Interface .................................... 113
8.1.3.2 6802 to SED1330F/1335F/1336F Interface ..................................... 114
8.2 Display Memory Interface .......................................................................................................... 115
8.2.1 Static RAM ............................................................................................................ 115
8.2.2 Supply Current during Display Memory Access .................................................... 115
8.3 Oscillator Circuit ........................................................................................................................ 116
8.4 Status Flag ................................................................................................................................ 116
8.5 Reset ......................................................................................................................................... 117
9.0 Application Notes ........................................................................................... 119
9.1 Initialization Parameters ............................................................................................................ 121
9.1.1 SYSTEM SET Instruction and Parameters ........................................................... 121
9.1.2 Initialization Example ............................................................................................ 122
9.1.3 Display Mode Setting Example 1: Combining Text and Graphics ......................... 128
9.1.4 Display Mode Setting Example 2: Combining Graphics and Graphics ................. 129
9.1.5 Display Mode Setting Example 3: Combining Three Graphics Layers ................. 130
9.2 System Overview ...................................................................................................................... 132
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Table of Contents
SED1330F/1335F/1336F
9.3 System Interconnection ............................................................................................................. 133
9.3.1 SED1330F/1335F ................................................................................................. 133
9.3.2 SED1336F ............................................................................................................ 134
9.4 Smooth Horizontal Scrolling ...................................................................................................... 135
9.5 Layered Display Attributes ......................................................................................................... 137
9.5.1 Inverse Display ..................................................................................................... 137
9.5.2 Half-tone Display .................................................................................................. 137
9.5.2.1 Menu Pad Display ............................................................................ 137
9.5.2.2 Graph Display .................................................................................. 138
9.5.3 Flashing Areas ...................................................................................................... 138
9.5.3.1 Small Area ........................................................................................ 138
9.5.3.2 Large Area ....................................................................................... 138
9.6 16 × 16-dot Graphic Display ...................................................................................................... 139
9.6.1 Command Usage .................................................................................................. 139
9.6.2 Kanji Character Display ........................................................................................ 139
10.0 Internal Character Generator Font ............................................................. 141
11.0 Glossary of Terms ........................................................................................ 145
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SED1330F/1335F/1336F
Table of Contents
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1.0
Overview
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1.0 – 1.2
1.0 Overview
1.0 Overview
1.1 Description
The SED1330/1335F/1336F is a family of versatile
LCD controller ICs that can display text and graphics
on a medium size LCD panel. The software is
compatible among all three chips. S-MOS recommends new designs use the SED1335 since the
SED1330 will gradually be replaced by the SED1335.
The SED1336F incorporates a TV sync generator
circuit that is compatible with both NTSC and PAL
systems. The 256 × 200 pixel TV display comprises
three superimposed layers, and is identical to the
simultaneous LCD panel display. When driving an
LCD only, up to 3 overlapping layers can be displayed
on LCD panels up to 640 × 256 pixels in size. The
SED1330/1335F does not incorporate a TV controller.
The SED1330/1335F/1336F can display layered text
and graphics, scroll the display in any direction and
partition the display into multiple screens.
The SED1330/1335F/1336F stores text, character
codes and bit-mapped graphics data in external frame
buffer memory. Display controller functions include
transferring data from the controlling microprocessor
to the buffer memory, reading memory data, converting data to display pixels and generating timing signals for the buffer memory, TV monitor and LCD
panel.
The SED1330/1335F/1336F has an internal character generator with 160, 5 × 7 pixel characters in
internal mask ROM. The character generators support up to 64, 8 × 16 pixel characters in external
character generator RAM and up to 256, 8 × 16 pixel
characters in external character generator ROM.
1.2 Features
• Text, graphics and combined text/graphics display modes
• Three overlapping screens in graphics mode
• 640 × 256 pixel LCD panel display resolution
• Programmable cursor control
• Smooth horizontal and vertical scrolling of all or
part of the display
• 1/2-duty to 1/256-duty LCD drive
• Up to 64 Kbytes of external static RAM frame
buffer memory
• Internal character generator
• 160, 5 × 7 pixel characters in internal maskprogrammed character generator ROM
• Up to 64, 8 × 16 pixel characters in external
character generator RAM
• Up to 256, 8 × 16 pixel characters in external
character generator ROM
• 6800 and 8080 family microprocessor interfaces
• NTSC and PAL systems compatible
(SED1336F only)
• 256 × 200 pixel TV monitor display resolution
(SED1336F only)
• Low power consumption—3.5 mA operating
current (VDD = 3.5V), 0.05 µA standby current
• 4.5 to 5.5V (SED1330F)
• 2.7 to 5.5V (SED1330F/1335F)
• 3.0 to 5.5V (SED1336F)
• Available in 60-pin QFPs
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1.0 Overview
1.3
1.3 Block Diagram
Character
Generator ROM
Display
Address
Controller
Refresh
Counter
Dot Counter
Character
Generator
ROM
Layered
Controller
Oscillator
D0 to D7
A0, CS
RD, WR
RES
XD0 to XD3
LCD Controller
Microprocessor Interface
SEL1
SEL0
XSCL, XECL
YSCL,YD,YDIS
Input/Output
Register
Video RAM Interface
Cursor
Address
Controller
LCD
VD0 to VD7
VR/W
VCE
VA0 to VA15
Character
Generator RAM
LP, WF
Video RAM
OSC1
OSC2
Figure 1. SED1330F block diagram
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1.3
1.0 Overview
1.3 Block Diagram
Cursor
Address
Controller
Display
Address
Controller
Refresh
Counter
Dot Counter
TV
Controller*
Character
Generator
ROM
Layered
Controller
Oscillator
D0 to D7
A0, CS
RD, WR
RES
XD0 to XD3
LCD Controller
Microprocessor Interface
SEL1
SEL0
XSCL, XECL
LCD
YSCL, YD, YDIS
VSD
VD0 to VD7
VRD
VCE,
VRD,
VWR
VA0 to VA15
VWR
Input/Output
Register
Video RAM Interface
TV
LP, WF
Character
Generator ROM
Character
Generator RAM
SNC
Video RAM
XG
XD
*SED1336F only
Figure 2. SED1335F/1336F block diagram
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1.0 Overview
1.4 – 1.4.2
50
60
1
Index
5
6
45
40
SED1330FBA
10
30
29
15
20
VA8
VA9
VA10
VA11
VA12
VA13
NC
VA14
VA15
VD0
VD1
VD2
VD3
VD2
VD1
VD0
VA15
VA14
VA13
VA12
VA11
VA10
VA9
VA8
VA7
VA6
NC
50
60
1
Index
5
6
45
40
SED1335FOA
10
30
29
15
20
D7
XD3
XD2
XD1
XD0
XECL
XSCL
VSS
LP
WF
YDIS
YD
YSCL
VD7
VD6
VD5
VD4
VD3
D2
D3
D4
D5
D6
55
31
30
SED1330FBB
Index
16
15
60
1
XD3
D7
D6
D5
D4
D3
D2
D1
D0
VDD
A0
CS
OSC2
OSC1
SEL 1
VD4
VD5
VD6
VD7
YSCL(SNC)
YD
YDIS
WF
LP
VSS
XSCL
XECL(VSD)
XD0
XD1
XD2
XG
SEL1
SEL2
WR
RD
NC
NC
RES
VRD
VCE
VWR
VA0
VA1
VA2
VA3
VA4
VA5
VA6
VA7
XD
CS
A0
VDD
D0
D1
45
46
VA5
VA4
VA3
VA2
VA1
VA0
VR/W
VCE
NC
RES
NC
NC
RD
WR
SEL 2
D7
XD3
XD2
XD1
XD0
XECL
XSCL
VSS
LP
WF
YDIS
YD
YSCL
VD7
VD6
VD5
VD4
VD3
D2
D3
D4
D5
D6
55
VA8
VA9
VA10
VA11
VA12
VA13
NC
VA14
VA15
VD0
VD1
VD2
VD3
VD2
VD1
VD0
VA15
VA14
VA13
VA12
VA11
VA10
VA9
VA8
VA7
VA6
NC
45
46
31
30
SED1335F0B
(SED1336F0A)
Index
60
1
16
15
XD3
D7
D6
D5
D4
D3
D2
D1
D0
VDD
A0
CS
XD
XG
SEL1
VA5
VA4
VA3
VA2
VA1
VA0
VWR
VCE
VRD
RES
NC
NC(CLO)
RD
WR
SEL 2(NT/PL)
XD
CS
A0
VDD
D0
D1
VD4
VD5
VD6
VD7
YSCL
YD
YDIS
WF
LP
VSS
XSCL
XECL
XD0
XD1
XD2
XG
SEL1
SEL2
WR
RD
NC
NC
RES
NC
VCE
VWR
VA0
VA1
VA2
VA3
VA4
VA5
VA6
VA7
1.4 Pinouts
Figure 3. SED1330F and SED1335F pinouts
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1.4 – 1.4.2
1.0 Overview
1.5 Package Dimensions
QFP5
Unit: mm
25.6 ± 0.4
20.0 ± 0.1
54
36
55
30
Index
29
5
24
6
1.0 ± 0.1
2.7 ± 0.1
0.15 ± 0.05
19.6 ± 0.4
60
1
14.0 ± 0.1
35
0.35 ± 0.1
23
0 ~ 12°
1.5 ± 0.3
2.8
Figure 4. SED1330FBA and 1335F0A package dimensions
17.6 ± 0.4
QFP6
Unit: mm
14.0 ± 0.2
45
31
46
Index
16
60
2.7 ± 0.1
1
0.15 ± 0.05
17.6 ± 0.4
14.0 ± 0.2
30
15
0.8 ± 0.15
0.35 ± 0.15
0 ~ 12°
0.8 ± 0.3
1.8
Figure 5. SED1330FBB , 1335F0B and SED1336F0A
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2.0
Pin Description
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2.0 Pin Description
2.0 – 2.1
2.0 Pin Description
2.1 SED1330FBA/BB Pin Summary
Name
Number
Type
Description
SED1330F0A
SED1330FBB
27 to 28
30 to 43
44
45
47
29, 46, 48, 49
50 to 59
1 to 6
7
8
10
9, 11, 12, 60
RD
50
13
Input
WR
51
14
Input
SEL2
52
15
Input
SEL1
53
16
Input
OSC1
OSC2
CS
A0
VDD
54
55
56
57
58
59 to 60
1 to 6
10 to 7
11
12
17
18
19
20
21
Input
Output
Input
Input
Supply
22 to 29
Input/output
33 to 30
34
35
Output
Output
Output
X-driver data
X-driver enable chain clock
X-driver data shift clock
LP
WF
13
14
15
36
37
38
Supply
Output
Output
YDIS
16
39
Output
17
18
26 to 19
40
41
49 to 42
Output
Output
Input/output
Ground
Latch pulse
Frame signal
Power-down signal when display is
blanked
Scan start pulse
Y-driver shift clock
VRAM data bus
VA0 to VA15
VR/W
VCE
RES
NC
D0 to D7
XD0 to XD3
XECL
XSCL
VSS
YD
YSCL
VD0 to VD7
18
Output
VRAM address bus
Output
Output
Input
—
VRAM write signal
Memory control signal
Reset
No connection
8080 family: Read signal
6800 family: Enable clock (E)
8080 family: Write signal
6800 family: R/W signal
8080 or 6800 family interface
select
8080 or 6800 family interface
select
Oscillator connection
Oscillator connection
Chip select
Data type select
4.5 to 5.5V supply
Data bus
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2.0 – 2.2
2.0 Pin Description
2.0 Pin Description
2.2 SED1330F/1335F0A/0B Pin Summary
Name
VA0 to VA15
VWR
VCE
VRD
RES
NC
Number
SED1335F0B
SED1335F0A
27 to 28
50 to 59
30 to 43
1 to 6
44
7
45
8
46
9
47
10
29, 48, 49
11, 12, 60
Type
Description
Output
VRAM address bus
Output
Output
Output
Input
—
RD
50
13
Input
WR
51
14
Input
SEL2
52
15
Input
SEL1
53
16
Input
XG
XD
CS
A0
VDD
54
55
56
57
17
18
19
20
Input
Output
Input
Input
VRAM write signal
Memory control signal
VRAM read signal
Reset
No connection
8080 family: Read signal
6800 family: Enable clock (E)
8080 family: Write signal
6800 family: R/W signal
8080 or 6800 family interface
select
8080 or 6800 family interface
select
Oscillator connection
Oscillator connection
Chip select
Data type select
58
59 to 60
1 to 6
10 to 7
11
12
13
14
15
21
Supply
2.7 to 5.5V supply
22 to 29
Input/output
33 to 30
34
35
36
37
38
Output
Output
Output
Supply
Output
Output
16
39
Output
17
18
26 to 19
40
41
49 to 42
Output
Output
Input/output
D0 to D7
XD0 to XD3
XECL
XSCL
VSS
LP
WF
YDIS
YD
YSCL
VD0 to VD7
Data bus
X-driver data
X-driver enable chain clock
X-driver data shift clock
Ground
Latch pulse
Frame signal
Power-down signal when display is
blanked
Scan start pulse
Y-driver shift clock
VRAM data bus
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2.0 Pin Description
2.3
2.3 SED1336F0A Pin Summary
Name
VA0 to VA15
VWR
VCE
VRD
RES
NC
CLO
Number
1 to 6
50 to 59
7
8
9
10
11, 60
12
Type
Output
VRAM address bus
Output
Output
Output
Input
—
Output
VRAM write signal
Memory control signal
VRAM read signal
Reset
No connection
Clock output
8080 family: Read signal
6800 family: Enable clock (E)
8080 family: Write signal
6800 family: R/W signal
NTSC or PAL TV mode select
8080 or 6800 family interface select
Oscillator connection
Oscillator connection
RD
13
Input
WR
14
Input
NT/PL
SEL1
OSC1
OSC2
15
16
17
18
Input
Input
Input
Output
19
20
21
22 to 29
30 to 33
34
35
36
37
38
Input
Input
Supply
Input/output
Output
Output
Output
Supply
Output
Output
39
Output
40
41
42 to 49
Output
Output
Input/output
CS
A0
VDD
D0 to D7
XD0 to XD3
VSD
XSCL
VSS
LP
WF
YDIS
YD
SNC
VD0 to VD7
20
Description
Chip select
Data type select
3.0 to 5.5V supply
Data bus
X-driver data
Video data
Data shift clock
Ground
Latch pulse
Frame signal
Power-down signal when display is
blanked
Scan start pulse
TV sync signal
VRAM data bus
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2.4 – 2.4.3
2.0 Pin Description
2.4 Pin Functions
2.4.1 Power Supply
Pin Name
VDD
VSS
Function
4.5 to 5.5V (SED1330F), 3.0 to 5.5V (SED1336F) or 2.7 to 5.5V (SED1330F/1335F) supply.
This may be the same supply as the controlling microprocessor.
Ground
Note: The peak supply current drawn by the SED1330F/1335F/1336F may be up to ten times the average supply current. The power
supply impedance must be kept as low as possible by ensuring that supply lines are sufficiently wide and by placing 0.47 µF
decoupling capacitors that have good high-frequency response near the device’s supply pins.
2.4.2 Oscillator
Pin Name
(OSC) XG
(OSC2) XD
CLO
Function
Crystal connection for internal oscillator (see Section 8.3). This pin can be driven by an external
clock source that satisfies the timing specifications of the EXT φ0 signal (see Section 4.3.6).
Crystal connection for internal oscillator. Leave this pin open when using an external clock
source.
Clock output (SED1336F only). Same phase as XG. Clock is output when system command
P1 is executed. Output stops during system reset.
2.4.3 Microprocessor Interface
Pin Name
D0 to D7
SEL1, SEL2
Function
Tristate input/output pins. Connect these pins to an 8- or 16-bit microprocessor bus.
Microprocessor interface select pin. The SED1336F supports both 8080 family processors
(such as the 8085 and Z80®) and 6800 family processors (such as the 6802 and 6809).
SEL1*
0
SEL2
0
Interface
8080 family
A0
A0
RD
RD
WR
WR
CS
CS
1
0
6800 family
A0
E
R/W
CS
* SED1330F and SED1335F only
Note: SEL1 should be tied directly to VDD or V SS to prevent noise. If noise does appear on SEL1, decouple it to ground using a
capacitor placed as close to the pin as possible.
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2.0 Pin Description
Pin Name
A0
2.4.3
Function
A0, in conjunction with the RD and WR or R/W and E signals, controls the type of access to
the SED1336F, as shown below.
8080 family interface
A0
RD
WR
0
1
0
0
1
1
Status flag read
Display data and cursor address read
Function
0
1
0
Display data and parameter write
1
1
0
Command write
6800 family interface
RD or E
WR or R/W
CS
RES
22
A0
R/W
E
Function
0
1
1
1
1
1
Status flag read
Display data and cursor address read
0
0
1
Display data and parameter write
1
0
1
Command write
When the 8080 family interface is selected, this signal acts as the active-LOW read strobe. The
SED1330F/1335F/1336F’s output buffers are enabled when this signal is active.
When the 6800 family interface is selected, this signal acts as the active-HIGH enable clock.
Data is read from or written to the SED1330F/1335F/1336F when this clock goes HIGH.
When the 8080 family interface is selected, this signal acts as the active-LOW write strobe. The
bus data is latched on the rising edge of this signal.
When the 6800 family interface is selected, this signal acts as the read/write control signal. Data
is read from the SED1330F/1335F/1336F if this signal is HIGH, and written to the SED1330F/
1335F/1336F if it is LOW.
Chip select. This active-LOW input enables the SED1330F/1335F/1336F. It is usually
connected to the output of an address decoder device that maps the SED1330F/1335F/1336F
into the memory space of the controlling microprocessor.
This active-LOW input performs a hardware reset on the SED1330F/1335F/1336F. It is a
Schmitt-trigger input for enhanced noise immunity; however, care should be taken to ensure
that it is not triggered if the supply voltage is lowered.
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2.4.4 – 2.4.5
2.0 Pin Description
2.4.4 Display Memory Control
The SED1330F/1335F/1336F can directly access static
RAM and PROM. The designer may use a mixture of
these two types of memory to achieve an optimum
trade-off between low cost and low power consumption.
Pin Name
Function
16-bit display memory address. When accessing character generator RAM or ROM, VA0 to
VA0 to VA15
VA3, reflect the lower 4 bits of the row counter.
VD0 to VD7 8-bit tristate display memory data bus. These pins are enabled when VR/W is LOW.
VR/W
Active-LOW display memory write control output (SED1330).
VRD
Active-LOW display memory read control output (SED1335/6).
VCE
Active-LOW static memory standby control signal. VCE can be used with CS.
VWR
Active-LOW display memory write control output (SED1335/6).
2.4.5 LCD Drive Signals
In order to provide effective low-power drive for LCD
matrixes, the SED1330F/1335F/1336F can directly
control both the X- and Y-drivers using an enable
chain.
Pin Name
XD0 to XD3
XSCL
XECL
LP
WF
YSCL
YD
YDIS
Function
4-bit X-driver (column drive) data outputs. Connect these outputs to the inputs of the X-driver
chips.
The falling edge of XSCL latches the data on XD0 to XD3 into the input shift registers of the
X-drivers. To conserve power, this clock halts between LP and the start of the following display
line (see Section 4.3.7).
The falling edge of XECL (SED1330F/1335F only) triggers the enable chain cascade for the
X-drivers (SED1600/SED1180). Every 16th clock pulse is output to the next X-driver.
LP latches the signal in the X-driver shift registers into the output data latches. LP is a fallingedge triggered signal, and pulses once every display line.
Connect LP to the Y-driver shift clock on modules that use the SED1600 and SED1610 drivers.
LCD panel AC drive output. The WF period is selected to be one of two values with SYSTEM
SET command.
The falling edge of YSCL (SED1330F/1335F only) latches the data on YD into the input shift
registers of the Y-drivers. YSCL is not used with the SED1600, SED1610 or other driver ICs
which use LP as the Y-driver shift clock.
YD is the data pulse output for the Y drivers. It is active during the last line of each frame, and
is shifted through the Y drivers one by one (by YSCL), to scan the display’s common
connections.
Power-down output signal. YDIS is HIGH while the display drive outputs are active.
YDIS goes LOW one or two frames after the sleep command is written to the SED1330F/
1335F/1336F. All Y-driver outputs are forced to an intermediate level (de-selecting the display
segments) to blank the display. In order to implement power-down operation in the LCD unit,
the LCD power drive supplies must also be disabled when the display is disabled by YDIS.
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1.0 Overview
1.3
THIS PAGE INTENTIONALLY BLANK
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1.3 – 1.4
1.0 Overview
3.0
Command Description
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THIS PAGE INTENTIONALLY BLANK
26
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3.0 – 3.1
3.0 Command Description
3.0 Command Description
3.1 The Command Set
Table 1. The Command Set
Command
Read
Hex Command Description Parameters
No. of SecRD WR A0 D7 D6 D5 D4 D3 D2 D1 D0
Bytes tion
Code
Class
System
control
Display
control
Drawing
control
Memory
control
Command
Initialize device and display
SYSTEM SET
1
0
1
0
1
0
0
0
0
0
0
40
SLEEP IN
1
0
1
0
1
0
1
0
0
1
1
DISP ON/OFF
1
0
1
0
1
0
1
1
0
0
D
53 Enter standby mode
58, Enable and disable dis59 play and display flashing
SCROLL
1
0
1
0
1
0
0
0
1
0
0
CSRFORM
1
0
1
0
1
0
1
1
1
0
1
0
0
Set display start address
and display regions
5D Set cursor type
44
Set start address of char5C
acter generator RAM
8
3.2.1
0
3.2.2
1
3.3.1
10
3.3.2
2
3.3.3
2
3.3.6
0
3.3.4
1
3.3.7
1
3.3.5
2
3.4.1
CGRAM ADR
1
0
1
0
1
0
1
1
1
CSRDIR
1
0
1
0
1
0
0
1
1
HDOT SCR
1
0
1
0
1
0
1
1
OVLAY
1
0
1
0
1
0
1
1
0
1
1
CSRW
1
0
1
0
1
0
0
0
1
1
0
Set display overlay format
46 Set cursor address
CSRR
1
0
1
0
1
0
0
0
1
1
1
47 Read cursor address
2
3.4.2
MWRITE
1
0
1
0
1
0
0
0
0
1
0
—
3.5.1
MREAD
1
0
1
0
1
0
0
0
0
1
1
42 Write to display memory
Read from display mem43
ory
—
3.5.2
4C
CD CD
Set direction of cursor
to
1 0
movement
4F
Set horizontal scroll pos0 1 0 5A
ition
5B
Notes:
1. In general, the internal registers of the SED1330F/1335F/1336F are modified as each command parameter is input. However,
the microprocessor does not have to set all the parameters of a command and may send a new command before all parameters
have been input. The internal registers for the parameters that have been input will have been changed but the remaining
parameter registers are unchanged.
2-byte parameters (where two bytes are treated as one data item) are handled as follows:
a. CSRW, CSRR: Each byte is processed individually. The microprocessor may read or write just the low byte of the cursor
address.
b. SYSTEM SET, SCROLL, CGRAM ADR: Both parameter bytes are processed together. If the command is changed after
half of the parameter has been input, the single byte is ignored.
2. APL and APH are 2-byte parameters, but are treated as two 1-byte parameters.
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3.0 Command Description
3.2 – 3.2.1
3.2 System Control Commands
3.2.1 SYSTEM SET
Initializes the device, sets the window sizes, and
selects the LCD interface format. Since the command
sets the basic operating parameters of the SED1330F/
1335F/1336F, an incorrect SYSTEM SET command
may cause other commands to operate incorrectly.
MSB
LSB
D7
D6
D5
D4
D3
D2
D1
D0
A0
WR
RD
C
0
1
0
0
0
0
0
0
1
0
1
P1
DR
T/L
IV
1
W/S
M2
M1
M0
0
0
1
P2
WF
0
0
0
0
0
0
1
P3
0
0
0
0
0
0
1
FX
FY
P4
C/R
0
0
1
P5
TC/R
0
0
1
P6
L/F
0
0
1
P7
APL
0
0
1
P8
APH
0
0
1
Figure 7. SYSTEM SET instruction
28
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3.2.1.1 – 3.2.1.5
3.2.1.1 C
3.0 Command Description
as character generator RAM, and the CG RAM2
address space is treated as character generator ROM.
This control byte performs the following:
M1 = 1: 64 char CG RAM + CG RAM2
1. Resets the internal timing generator
2. Disables the display
3. Cancels sleep mode
The CG RAM1 and CG RAM2 address spaces are
contiguous and are both treated as character generator RAM.
Parameters following P1 are not needed if only canceling sleep mode.
3.2.1.4 M2
3.2.1.2 M0
Selects the internal or external character generator
ROM. The internal character generator ROM contains 160, 5 × 7 pixel characters. These characters are
fixed at fabrication by the metalization mask. The
external character generator ROM can contain up to
256 user-defined characters.
M0 = 0: Internal CG ROM
M0 = 1: External CG ROM
Note that if the CG ROM address space overlaps the
display memory address space, that portion of the
display memory cannot be written to.
Selects the height of the character defined in external
CG ROM and CG RAM. Characters more than 16 pixels high can be displayed by creating a bitmap for
each portion of each character and using the
SED1330F/1335F/1336F’s graphics mode to reposition them.
M2 = 0: 8-pixel character height (2716 or
equivalent ROM)
M2 = 1: 16-pixel character height (2732
or equivalent ROM)
3.2.1.5 W/S
Selects the LCD drive method.
3.2.1.3 M1
W/S = 0: Single-panel drive
W/S = 1: Dual-panel drive
Selects the CG RAM area for user-definable characters. The CG RAM codes are selected from the 64
codes shown in Figure 59.
M1 = 0: CG RAM1; 32 char
The CG RAM1 and CG RAM2 address spaces are not
contiguous, the CG RAM1 address space is treated
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3.0 Command Description
EI
3.2.1.5
X driver
X driver
YD
Y driver
LCD
Figure 8. Single-panel display
EI
X driver
X driver
YD
Upper Panel
Y driver
Lower Panel
X driver
X driver
Figure 9. Dual-panel display
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3.2.1.5
3.0 Command Description
EI
X driver
X driver
X driver
X driver
YD
Y driver
Left Panel
Right Panel
Note: There are no Seiko-Epson LCD units in the configuration shown in Figure 10.
Figure 10. Left-and-right two-panel display
Table 3. LCD parameters
Parameter
C/R
TC/R
L/F
SL1
SL2
SAD1
SAD2
SAD3
SAD4
Cursor movement range
W/S = 0
W/S = 1
IV = 1
C/R
TC/R
L/F
IV = 0
IV = 1
IV = 0
C/R
C/R
C/R
TC/R (see note 1)
TC/R
TC/R
L/F
L/F
L/F
00H to L/F + 1
00H to L/F
(L/F) / 2
(L/F) / 2
(see note 2)
00H to L/F + 1
00H to L/F
(L/F) / 2
(L/F) / 2
(see note 2)
First screen block
First screen block
First screen block
First screen block
Second screen block Second screen block Second screen block Second screen block
Third screen block
Third screen block
Third screen block
Third screen block
Invalid
Invalid
Fourth screen block Fourth screen block
Above-and-below configuration:
Continuous movement over whole screen
continuousmovement over whole screen
Notes:
1. See table 31 (page 105) for further details on setting the C/R and TC/R parameters when using the HDOT SCR command.
2. The value of SL when IV = 0 is equal to the value of SL when IV = 1, plus one.
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3.0 Command Description
3.2.1.6 – 3.2.1.9
3.2.1.6 IV
3.2.1.7 T/L
Screen origin compensation for inverse display. IV is
usually set to 1.
Selects TV or LCD mode. When TV mode is selected,
the TV sync generator circuit is ON.
The best way of displaying inverted characters is to
Exclusive-OR the text layer with the graphics background layer. However, inverted characters at the top
or left of the screen are difficult to read as the character origin is at the top-left of its bitmap and there are no
background pixels either above or to the left of these
characters.
The IV flag causes the SED1330F/1335F/1336F to
offset the text screen against the graphics back layer
by one vertical pixel. Use the horizontal pixel scroll
function (HDOT SCR) to shift the text screen 1 to 7
pixels to the right. All characters will then have the
necessary surrounding background pixels that ensure easy reading of the inverted characters.
See Section 5.5 for information on scrolling.
IV = 0:
IV = 1:
Back layer
3.2.1.8 DR
Selects output of an additional shift-clock cycle for
every 64 pixels. The extra cycles are required for
correct operation of the enable chain when using a
two-panel display.
DR = 0: Normal operation
DR = 1: Additional shift-clock cycles
3.2.1.9 FX
Screen top-line correction
No screen top-line correction (no
offset)
Display start point
T/L = 0: LCD mode
T/L = 1: TV mode
IV
Sets the width, in pixels, of the character field. The
character width in pixels is equal to FX + 1, where FX
can range from 00 to 07H inclusive. If data bit 3 is set
(FX is in the range 08 to 0FH) and an 8-pixel font is
used, a space is inserted between characters. Note
that the maximum character width in TV mode is eight
pixels.
1 dot
Table 4. Horizontal character size selection
HDOT SCR
Character
Dots 1 to 7
HEX
00
01
↓
07
D3
0
0
↓
0
FX
D2 D1 D0
0
0
0
0
0
1
↓
↓
↓
1
1
1
[FX] character width
(pixels)
1
2
↓
8
Figure 11. IV and HDOT SCR adjustment
Since the SED1330F/1335F/1336F handles display
data in 8-bit units, characters larger than 8 pixels wide
must be formed from 8-pixel segments. As Figure 12
shows, the remainder of the second eight bits are not
displayed. This also applies to the second screen layer.
In graphics mode, the normal character field is also
eight pixels. If a wider character field is used, any
remainder in the second eight bits is not displayed.
32
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3.2.1.10 – 3.2.1.11
3.0 Command Description
FX
FX
FY
8 bits
8 bits
FY
8 bits
Address A
8 bits
Address B
Non-display area
Figure 12. FX and FY display addresses
3.2.1.10 WF
3.2.1.11 FY
Selects the AC frame drive waveform period. WF is
usually set to 1.
Sets the height, in pixels, of the character. The height
in pixels is equal to FY + 1.
WF = 0: 16-line AC drive
WF = 1: two-frame AC drive
In two-frame AC drive, the WF period is twice the
frame period.
FY can range from 00 to 0FH inclusive.
Set FY to zero (vertical size equals one) when in
graphics mode.
Table 5. Vertical character size selection
In 16-line AC drive, WF inverts every 16 lines.
Although 16-line AC drive gives a more readable
display, horizontal lines may appear when using high
LCD drive voltages or at high viewing angles.
HEX
00
01
↓
07
↓
0E
0F
D3
0
0
↓
0
↓
1
1
FY
D2 D1 D0
0
0
0
0
0
1
↓
↓
↓
1
1
1
↓
↓
↓
1
1
0
1
1
1
[FY] character
height (pixels)
1
2
↓
8
↓
15
16
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3.0 Command Description
3.2.1.12 – 3.2.1.13
3.2.1.12 C/R
Sets the address range covered by one display line,
that is, the number of characters less one, multiplied
by the number of horizontal bytes per character.
C/R can range from 0 to 239.
For example, if the character width is 10 pixels, then
the address range is equal to twice the number of
characters, less 2. See Section 9.1.1 for the calculation of C/R.
[C/R] cannot be set to a value greater than the
address range. It can, however, be set smaller than
the address range, in which case the excess display
area is blank. The number of excess pixels must not
exceed 64.
Table 6. Display line address range
HEX
00
01
↓
4F
↓
EE
EF
D7
0
0
↓
0
↓
1
1
D6
0
0
↓
1
↓
1
1
D5
0
0
↓
0
↓
1
1
C/R
D4
0
0
↓
0
↓
0
0
D3
0
0
↓
1
↓
1
1
D2
0
0
↓
1
↓
1
1
D1
0
0
↓
1
↓
1
1
D0
0
1
↓
1
↓
0
1
[C/R] bytes per display line
1
2
↓
80
↓
239
240
3.2.1.13 TC/R
Sets the length, including horizontal blanking, of one
line. The line length is equal to TC/R + 1, where TC/
R can range from 0 to 255.
according to the equation given in section 9.1.1 in
order to hold the frame period constant and minimize
jitter for any given main oscillator frequency, fOSC.
TC/R must be greater than or equal to C/R + 4.
Provided this condition is satisfied, [TC/R] can be set
Table 7. Line length selection
HEX
00
01
↓
52
↓
FE
FF
34
D7
0
0
↓
0
↓
1
1
D6
0
0
↓
1
↓
1
1
TC/R
D5
D4
0
0
0
0
↓
↓
0
1
↓
↓
1
1
1
1
D3
0
0
↓
0
↓
1
1
D2
0
0
↓
0
↓
1
1
D1
0
0
↓
1
↓
1
1
D0
0
1
↓
0
↓
0
1
[TC/R] line length (bytes)
1
2
↓
83
↓
255
256
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3.2.1.14 – 3.2.1.15
3.0 Command Description
3.2.1.14 L/F
Sets the height, in lines, of a frame. The height in lines
is equal to L/F + 1, where L/F can range from 0 to 255.
If W/S is set to 1, selecting two-screen display, the
number of lines must be even and L/F must, therefore,
be an odd number.
Table 8. Frame height selection
HEX
00
01
↓
7F
↓
FE
FF
D7
0
0
↓
0
↓
1
1
D6
0
0
↓
1
↓
1
1
D5
0
0
↓
1
↓
1
1
L/F
D4
0
0
↓
1
↓
1
1
D3
0
0
↓
1
↓
1
1
D2
0
0
↓
1
↓
1
1
Table 9. Frame heights and compatible LCD units
Number of lines [LF]
Panel Duty Cycle
64
1/64
128
1/64
D1
0
0
↓
1
↓
1
1
[L/F] lines per frame
D0
0
1
↓
1
↓
0
1
1
2
↓
128
↓
255
256
Table 10. Horizontal address range
Hex code
APH
APL
0
0
0
0
0
0
↓
↓
↓
0
0
5
↓
↓
↓
F
F
F
F
F
F
3.2.1.15 AP
[AP] addresses
per line
0
1
↓
0
↓
E
F
0
1
↓
80
↓
16
2 –2
216 – 1
Defines the horizontal address range of the virtual
screen. APL is the least significant byte of the address.
APL
AP7
AP6
AP5
AP4
AP3
AP2
AP1
AP0
APH
AP15
AP14
AP13
AP12
AP11
AP10
AP9
AP8
Figure 13. AP parameters
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3.0 Command Description
3.2.1.15 – 3.3.1
1. The YDIS signal goes LOW between one
and two frames after the SLEEP IN command is received. Since YDIS forces all
display driver outputs to go to the deselected output voltage, YDIS can be used as
a power-down signal for the LCD unit. This
can be done by having YDIS turn off the
relatively high-power LCD drive supplies at
the same time as it blanks the display.
Display area
C/R
2. Since all internal clocks in the SED1330F/
1335F/1336F are halted while in the sleep
state, a DC voltage will be applied to the LCD
panel if the LCD drive supplies remain on.
Display memory limit
AP
If reliability is a prime consideration, turn off
the LCD drive supplies before issuing the
SLEEP IN command.
Figure 14. AP and C/R relationship
3.2.2 SLEEP IN
Places the system in standby mode. This command
has no parameter bytes. At least one blank frame after
receiving this command, the SED1330F/1335F/1336F
halts all internal operations, including the oscillator,
and enters the sleep mode. Blank data is sent to the
X-drivers, and the Y-drivers have their bias supplies
turned off by the YDIS signal. Using the YDIS signal
to disable the Y-drivers guards against any spurious
displays.
The internal registers of the SED1330F/1335/1336F
maintain their values during the sleep mode. The
display memory control pins maintain their logic levels
to ensure that the display memory is not corrupted.
The SED1330F/1335F/1336F can be removed from
the sleep state by sending the SYSTEM SET command with only the P1 parameter. The DISP ON
command should be sent next to enable the display.
3. Note that, although the bus lines become
high impedance in the sleep state, pull-up
or pull-down resistors on the bus line will
force these lines to a known state.
3.3 Display Control Commands
3.3.1 DISP ON/OFF
Turns the whole display on or off. The single-byte
parameter enables and disables the cursor and layered screens, and sets the cursor and screen flash
rates. The cursor can be set to flash over one character or over a whole line.
MSB
C
P1
MSB
C
0
LSB
1
0
1
1
0
0
0
FP5 FP4 FP3 FP2 FP1 FP0 FC1 FC0
LSB
0
1
0
1
0
0
1
1
Figure 16. DISP ON/OFF parameters
Figure 15. SLEEP IN instruction
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3.3.1.1 – 3.3.2.1
3.3.1.1 D
Turns the display ON or OFF. The D bit takes precedence over the FP bits in the parameter.
D = 0:
D = 1:
Display OFF
Display ON
3.0 Command Description
Note: If SAD4 is enabled by setting W/S to 1, FP3 and FP2
control both SAD2 and SAD4. The attributes of SAD2
and SAD4 cannot be set independently.
3.3.2 SCROLL
3.3.2.1 C
3.3.1.2 FC
Enables/disables the cursor and sets the flash rate.
The cursor flashes with a 70% duty cycle (ON/OFF).
Sets the scroll start address and the number of lines
per scroll block. Parameters P1 to P10 can be omitted
if not required. The parameters must be entered
sequentially as shown in Figure 17.
Table 11. Cursor flash rate selection
MSB
FC1
0
0
FC0
0
1
1
0
1
1
Cursor display
OFF (blank)
No flashing
Flash at fFR/32 Hz
ON
(approx. 2 Hz)
Flash at fFR/64 Hz
(approx. 1 Hz)
Note: As the MWRITE command always enables the cursor,
the cursor position can be checked even when performing consecutive writes to display memory while the
cursor is flashing.
3.3.1.3 FP
Each pair of bits in FP sets the attributes of one screen
block, as follows.
LSB
C
0
1
0
0
0
1
0
0
P1
A7
A6
A5
A4
A3
A2
A1
A0 (SAD 1L)
P2
A15 A14 A13 A12 A11 A10
A9
A8 (SAD 1H)
P3
L7
L6
L5
L4
L3
L2
L1
L0 (SL 1)
P4
A7
A6
A5
A4
A3
A2
A1
A0 (SAD 2 L)
P5
A15 A14 A13 A12 A11 A10
A9
A8 (SAD 2H)
P6
L7
L6
L5
L4
L3
L2
L1
L0 (SL 2)
P7
A7
A6
A5
A4
A3
A2
A1
A0 (SAD 3L)
P8
A15 A14 A13 A12 A11 A10
A9
A8 (SAD 3H)
P9
A7
A2
A1
A0 (SAD 4L)
P10 A15 A14 A13 A12 A11 A10
A9
A8 (SAD 4H)
Table 12. Screen block attribute selection
FP1
FP0
FP3
FP2
FP5
0
0
FP4
0
1
1
0
1
1
First screen block (SAD1)
Second screen block (SAD2,
SAD4). See note.
Third screen block (SAD3)
OFF (blank)
No flashing
Flash at fFR/32 Hz
ON
(approx. 2 Hz)
Flash at fFR/4 Hz
(approx. 16 Hz)
A6
A5
A4
A3
Note: Set parameters P9 and P10 only if both two-screen
drive (W/S = 1) and two-layer configuration are selected. SAD4 is the fourth screen block display start
address.
Figure 17. SCROLL instruction parameters
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3.0 Command Description
3.3.2.1 – 3.3.2.2
Table 13. Screen block start address selection
HEX
00
01
↓
7F
↓
FE
FF
L7
0
0
↓
0
↓
1
1
L6
0
0
↓
1
↓
1
1
SL1, SL2
L5
L4
0
0
0
0
↓
↓
1
1
↓
↓
1
1
1
1
L3
0
0
↓
1
↓
1
1
L2
0
0
↓
1
↓
1
1
L1
0
0
↓
1
↓
1
1
[SL] screen lines
L0
0
1
↓
1
↓
0
1
1
2
↓
128
↓
255
256
3.3.2.2 SL1, SL2
SL1 and SL2 set the number of lines per scrolling
screen. The number of lines is SL1 or SL2 plus one.
The relationship between SAD, SL and the display
mode is described below.
Table 14. Text display mode
W/S
Screen
First screen block
Second screen block
First Layer
Second Layer
SAD1
SAD2
SL1
SL2
SAD3 (see note 1)
Set both SL1 and SL2 to L/F + 1
if not using a partitioned screen.
Third screen block (partitioned screen)
Screen configuration example:
SAD2
SAD1
SL2
0
SL1
Character display page 1
Graphics display page 2
SAD3
Character display page 3
Layer 2
Layer 1
(continued)
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3.3.2.2
3.0 Command Description
Table 14. Text display mode (continued)
W/S
Screen
First Layer
SAD1
Upper screen
SL1
SAD3
Lower screen
(see note 2)
Set both SL1 and SL2 to ((L/F) / 2 + 1)
Screen configuration example:
Second Layer
SAD2
SL2
SAD4
(see note 2)
SAD2
SAD1
1
SL1
Graphics display page 2
Character display page 1
SAD3
Graphics display page 4
(SAD4)
Character display page 3
Layer 1
Layer 2
Notes:
1. SAD3 has the same value as either SAD1 or SAD2, whichever has the least number of lines (set by SL1 and SL2).
2. Since the parameters corresponding to SL3 and SL4 are fixed by L/F, they do not have to be set in this mode.
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3.0 Command Description
3.3.2.2
Table 15. Graphics display mode
W/S
Screen
First Layer
Second Layer
SAD1
SAD2
Two-layer composition
SL1
SL2
SAD3 (see note 3)
Set both SL1 and SL2 to
Upper screen
L/F + 1 if not using a
partitioned screen
Screen configuration example:
Third Layer
SAD2
SAD1
SL2
0
SL1
Graphics display page 2
Character display page 1
SAD3
Character display page 3
Layer 1
Layer 2
SAD1
SL1 = L/F + 1
Screen configuration example:
Three-layer configuration
SAD2
SL2 = L/F + 1
SAD3
SAD2
SAD1
SAD3
—
Graphics display page 3
SL2
0
SL1
Graphics display page 2
Graphics display page 1
Layer 1
40
Layer 3
Layer 2
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3.3.2.2
3.0 Command Description
Table 15. Graphics display mode (continued)
W/S
Screen
First Layer
Second Layer
SAD1
SAD2
Upper screen
SL1
SL2
SAD3
SAD4
Lower screen
(see note 2)
(see note 2)
Set both SL1 and SL2 to ((L/F) / 2 + 1)
Screen configuration example (see note 3):
Third Layer
—
—
SAD2
SAD1
1
SL1
Graphics display page 2
Graphics display page 1
SAD3
Graphics display page 4
Graphics display page 3
Layer 1
Layer 2
Notes:
1. SAD3 has the same value as either SAD1 or SAD2, whichever has the least number of lines (set by SL1 and SL2).
2. Since the parameters corresponding to SL3 and SL4 are fixed by L/F, they do not have to be set.
3. If, and only if, W/S = 1, the differences between SL1 and (L/F + 1) / 2, and between SL2 and (L/F + 1) / 2, are blanked.
SL1
Upper Panel
L
L/2
Lower Panel
Graphics
Figure 18. Two-panel display height
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3.0 Command Description
3.3.3 – 3.3.3.2
3.3.3 CSRFORM
3.3.3.2 CRY
Sets the cursor size and display mode. Although the
cursor is normally only used in text displays, it may
also be used in graphics displays when displaying
special characters.
Sets the location of an underscored cursor in lines,
from the character origin. When using a block cursor,
CRY sets the vertical size of the cursor from the
character origin. CRY is equal to the number of lines
less one.
MSB
C
0
LSB
1
0
1
1
1
0
Table 17. Cursor height selection
1
P1
0
0
0
0
X3
CRX
X2
X1 X0
P2
CM
0
0
0
Y3
CRY
Y2
Y1 Y0
Figure 19. CSRFORM parameter bytes
HEX
0
1
↓
8
↓
E
F
CRY
Y3 Y2 Y1 Y0
0
0
0
0
0
0
0
1
↓
↓
↓
↓
1
0
0
0
↓
↓
↓
↓
1
1
1
0
1
1
1
1
[CRY] cursor
height (lines)
illegal
2
↓
9
↓
15
16
3.3.3.1 CRX
Sets the horizontal size of the cursor from the character origin. CRX is equal to the cursor size less one.
CRX must be less than or equal to FX.
Table 16. Horizontal cursor size selection
Character start point
0
0 1 2 3 4 5 6 •
•
•
1
CRX
HEX X3 X2 X1 X0
0
0
0
0
0
1
0
0
0
1
↓
↓ ↓
↓
↓
8
1
0
0
0
↓
↓ ↓
↓
↓
E
1
1
1
0
F
1
1
1
1
[CRX] cursor width
(pixels)
1
2
↓
9
↓
15
16
2
3
4
5
6
7
8
9
CRX = 5 dots
CRY = 9 dots
CM = 0
Figure 20. Cursor size and position
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3.3.3.3 – 3.3.5.1
3.0 Command Description
3.3.3.3 CM
Table 18. Cursor shift direction
Sets the cursor display mode. Always set CM to 1
when in graphics mode.
CM = 0: Underline cursor
CM = 1: Block cursor
C
4CH
4DH
4EH
4FH
CD1
0
0
1
1
CD0
0
1
0
1
Shift direction
Right
Left
Up
Down
Note: Since the cursor moves in address units even if FX ≥ 9,
the cursor address increment must be preset for movement in character units. See Section 5.3.
3.3.4 CSRDIR
Sets the direction of automatic cursor increment. The
cursor can move left or right one character, or up or
down by the number of bytes specified by the address
pitch, AP.
When reading from and writing to display memory,
this automatic cursor increment controls the display
memory address increment on each read or write.
3.3.5 OVLAY
Selects layered screen composition and screen text/
graphics mode.
MSB
MSB
C
LSB
C
0
1
0
P1
0
0
0
1
1
0
1
1
LSB
0
1
0
0
1
1
CD1 CD2
Figure 21. CSRDIR parameters
OV DM2 DM1 MX1 MX0
Figure 23. OVLAY parameter
3.3.5.1 MX0, MX1
10
–AP
–1
+1
01
00
+AP
MX0 and MX1 set the layered screen composition
method, which can be either OR, AND, Exclusive-OR
or Priority-OR. Since the screen composition is organized in layers and not by screen blocks, when using
a layer divided into two screen blocks, different composition methods cannot be specified for the individual screen blocks.
The Priority-OR mode is the same as the OR mode
unless flashing of individual screens is used.
11
Figure 22. Cursor direction
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3.0 Command Description
3.3.5.1
Table 19. Composition method selection
MX1
0
MX0
0
Function
L1 ∪ L2 ∪ L3
Composition Method
OR
0
1
(L1 ⊕ L2) ∪ L3
Exclusive-OR
1
1
0
1
(L1 ∩ L2) ∪ L3
L1 > L2 > L3
AND
Priority-OR
Applications
Underlining, rules, mixed text and graphics
Inverted characters, flashing regions, underlining
Simple animation, three-dimensional appearance
Notes:
L1: First layer (text or graphics). If text is selected, layer L3 cannot be used.
L2: Second layer (graphics only)
L3: Third layer (graphics only)
Layer 1
Layer 2
Layer 3
Visible display
1
EPSON
EPSON OR
2
EPSON
EPSON Exclusive OR
3
EPSON
4
EPSON
SON AND
EPSON Prioritized OR
Notes:
L1: Not flashing
L2: Flashing at 1 Hz
L3: Flashing at 2 Hz
Figure 24. Combined layer display
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3.3.5.2 – 3.3.7.1
3.0 Command Description
3.3.5.2 DM1, DM2
3.3.7 HDOT SCR
DM1 and DM2 specify the display mode of screen
blocks 1 and 3, respectively.
While the scroll command only allows scrolling by
characters, HDOT SCR allows the screen to be scrolled
horizontally by pixels. HDOT SCR cannot be used on
individual layers.
DM1/2 = 0: Text mode
DM1/2 = 1: Graphics mode
Note 1: Screen blocks 2 and 4 can only display graphics.
Note 2: DM1 and DM2 must be the same, regardless of the
setting of W/S.
MSB
LSB
C
0
1
0
1
1
0
1
0
P1
0
0
0
0
0
D2
D1
D0
3.3.5.3 OV
Figure 26. HDOT SCR parameters
Specifies two- or three-layer composition in graphics
mode.
OV = 0: Two-layer composition
OV = 1: Three-layer composition
Set OV to 0 for mixed text and graphics mode.
3.3.6 CGRAM ADR
3.3.7.1 D0 to D2
Specifies the number of pixels to scroll. The C/R
parameter has to be set to one more than the number
of horizontal characters before using HDOT SCR.
Smooth scrolling can be simulated if the controlling
microprocessor repeatedly issues the HDOT SCR
command to the SED1330F/1335F/1336F. See Section 5.5 for more information on scrolling the display.
Specifies the CG RAM start address.
Table 20. Scroll step selection
MSB
LSB
C
0
1
0
1
1
1
0
0
P1
A7
A6
A5
A4
A3
A2
A1
A0 (SAGL)
P2
A15 A14 A13 A12 A11 A10
A9
A8 (SAGH)
Figure 25. CGRAM ADR parameters
HEX
00
01
02
↓
06
07
P1
D2 D1 D0
0
0
0
0
0
1
0
1
0
↓
↓
↓
1
1
0
1
1
1
Number of pixels
to scroll
0
1
2
↓
6
7
Note: See Section 6 for information on the SAG parameters.
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3.0 Command Description
3.4 – 3.4.2
Note that the microprocessor cannot directly access
the display memory.
M
B
A
Z
A
Z
X
B
A
The MREAD and MWRITE commands use the address in this register.
Y
X
M=0
Y
B
N=0
X
Display width
The cursor address register can only be modified by
the CSRW command, and by the automatic increment after an MREAD or MWRITE command. It is not
affected by display scrolling.
Y
N
M/N is the number of bits (dots) that parameter 1 (P1)
is incremented/decremented by.
If a new address is not set, display memory accesses
will be from the last set address or the address after
previous automatic increments.
Figure 27. Horizontal scrolling
3.4.2 CSRR
Reads from the cursor address register. After issuing
the command, the data read address is read twice, for
the low byte and then the high byte of the register.
3.4 Drawing Control Commands
3.4.1 CSRW
The 16-bit cursor address register contains the display memory of the data at the cursor position as
shown in Figure 28.
MSB
LSB
C
0
1
0
0
0
1
1
P1
A7
A6
A5
A4
A3
A2
A1
A0 (CSRL)
P2
A15 A14 A13 A12 A11 A10
A9
A8 (CSRH)
MSB
LSB
C
0
1
0
0
0
1
1
1
P1
A7
A6
A5
A4
A3
A2
A1
A0 (CSRL)
P2
A15 A14 A13 A12 A11 A10
A9
A8 (CSRH)
0
Figure 29. CSRR parameters
Figure 28. CSRW parameters
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3.5 – 3.5.2
3.0 Command Description
3.5 Memory Control Commands
3.5.2 MREAD
3.5.1 MWRITE
Puts the SED1330F/1335F/1336F into the data output state. On the MREAD command, the display
memory data at the cursor address is read into a
buffer in the SED1330F/1335F/1336F.
The microprocessor may write a sequence of data
bytes to display memory by issuing the MREAD
command and then writing the bytes to the SED1330F/
1335F/1336F. There is no need for further MWRITE
commands or for the microprocessor to update the
cursor address register after each byte as the cursor
address is automatically incremented by the amount set
with CSRDIR, in preparation for the next data write.
MSB
C
LSB
0
1
0
0
0
0
1
Each time the microprocessor reads the buffer, the
cursor address is incremented by the amount set by
CSRDIR and the next data byte fetched from memory,
so a sequence of data bytes may be read without
further MREAD commands or by updating the cursor
address register.
If the cursor is displayed, the read data will be from two
positions ahead of the cursor.
0
MSB
P1
C
0
LSB
1
0
0
0
0
1
1
P2
P1
n≥1
Pn
P2
Note:
P1, P2, ..., Pn: display data.
n≥1
Pn
Figure 30. MWRITE parameters
Figure 31. MREAD parameters
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1.0 Overview
1.3
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3.3.2.2
3.0 Command Description
4.0
Specifications
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4.0 – 4.1
4.0 Specifications
4.0 Specifications
4.1 Absolute Maximum Ratings
4.1.1 SED1330
Parameter
Supply voltage range
Input voltage range
Power dissipation
Operating temperature range
Storage temperature range
Soldering temperature (10 seconds). See note 1.
Symbol
VDD
VIN
PD
Topr
Tstg
Tsolder
Rating
–0.3 to 7.0
–0.5 to VDD + 0.5
300
–20 to 75
–65 to 150
260
Unit
V
V
mW
°C
°C
°C
Symbol
VDD
VIN
PD
Topr
Tstg
Tsolder
Rating
–0.3 to 7.0
–0.3 to VDD + 0.3
300
–20 to 75
–65 to 150
260
Unit
V
V
mW
°C
°C
°C
4.1.2 SED1335/SED1336
Parameter
Supply voltage range
Input voltage range
Power dissipation
Operating temperature range
Storage temperature range
Soldering temperature (10 seconds). See note 1.
Notes:
1. The humidity resistance of the flat package may be reduced if the package is immersed in solder. Use a soldering technique
that does not heatstress the package.
2. If the power supply has a high impedance, a large voltage differential can occur between the input and supply voltages. Take
appropriate care with the power supply and the layout of the supply lines. (See Section 2.3.)
3. All supply voltages are referenced to VSS = 0V.
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51
4.0 Specifications
4.2
4.2 SED 1330 Electrical Characteristics
Parameter
Supply voltage
Register data retention voltage
Input leakage current
Output leakage current
Operating supply current
Quiescent supply current
min
4.5
2.0
—
—
—
Rating
typ
5.0
—
0.05
0.10
8
max
5.5
5.5
2.0
5.0
12
VOSC1 = VCS = VRD = VDD
—
0.05
20.0
µA
Measured at OSC1
1.0
—
0.5
—
—
1.0
10.0
10.0
5.0
MHz
MHz
MΩ
2.2
–0.3
—
—
VDD + 0.3
0.8
V
V
2.4
—
—
V
—
—
0.4
V
—
—
—
—
—
0.2V DD
—
0.4
V
V
V
V
0.7V DD
0.3V DD
0.8V DD
0.5V DD
V
V
Symbol
VDD
VOH
ILI
ILO
Iopr
IQ
VDD = 5V ±10%, VSS = 0V, Ta = –20 to 75°C
Condition
VI = VDD.
VI = VSS.
See note 4.
Oscillator frequency
External clock frequency
Oscillator feedback resistance
TTL
HIGH-level input voltage
LOW-level input voltage
fOSC
fCL
Rf
HIGH-level output voltage
VOHT
LOW-level output voltage
VOLT
IOL = 5.0 mA. See note 1.
VIHC
VILC
VOHC
VOLC
See note 2.
0.8V DD
See note 2.
—
IOH = –1.6 mA. See note 2.VDD – 0.4
IOH = 1.6 mA. See note 2.
—
CMOS
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
Schmitt-trigger
Rising-edge threshold voltage
Falling-edge threshold voltage
VIHT
VILT
VT+
VT–
See note 1.
See note 1.
IOH = –5.0 mA.
See note 1.
See note 3.
See note 3.
0.5V DD
0.2V DD
Unit
V
V
µA
µA
mA
Notes:
1. D0 to D7, A0, CS, RD, WR, VD0 to VD7, VA0 to VA15,
VR/W and VCE are TTL-level inputs.
2. SEL1, SEL2 and OSC1 are CMOS-level inputs. YD,
XD0 to XD3, XSCL, YECL, LP, WF, YSCL, YDIS and
CLO are CMOS-level outputs.
3. RES is a Schmitt-trigger input. The pulsewidth on RES
must be at least 200 µs. Note that pulses of more than
a few seconds will cause DC voltages to be applied to
the LCD panel.
4. fOSC = 10 MHz, no load (no display memory), internal
character generator, 256 × 200 pixel display. The
operating supply current can be reduced by approximately 1 mA by setting both CLO and the display OFF.
52
S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
4.3
4.0 Specifications
4.3 SED1335/1336 Electrical Characteristics
VDD = 4.5 to 5.5V, VSS = 0V, Ta = –20 to 75°C
Parameter
Supply voltage
Register data retention voltage
Input leakage current
Output leakage current
Operating supply current
Quiescent supply current
Symbol
VDD
VOH
I LI
ILO
Iopr
IQ
Condition
VI = VDD. See note 6.
VI = VSS. See note 6.
See note 4.
Sleep mode,
VOSC1 = VCS = VRD = VDD
min
4.5
2.0
—
—
—
Rating
typ
5.0
—
0.05
0.10
11
max
5.5
6.0
2.0
5.0
15
—
0.05
20.0
µA
1.0
1.0
0.5
—
—
1.0
10.0
10.0
3.0
MHz
MHz
MΩ
0.5V DD
VSS
—
—
VDD
0.2V DD
V
V
2.4
—
—
V
—
—
VSS + 0.4
V
Unit
V
V
µA
µA
mA
Oscillator frequency
External clock frequency
Oscillator feedback resistance
TTL
HIGH-level input voltage
LOW-level input voltage
f OSC
f CL
Rf
HIGH-level output voltage
VOHT
LOW-level output voltage
VOLT
IOL = 5.0 mA. See note 1.
VIHC
VILC
VOHC
VOLC
See note 2.
0.8V DD
See note 2.
VSS
IOH = –2.0 mA. See note 2. VDD – 0.4
IOH = 1.6 mA. See note 2.
—
—
—
—
—
VDD
0.2V DD
—
VSS + 0.4
V
V
V
V
VOLN
IOL = 6.0 mA. See note 5.
—
—
VSS + 0.4
V
0.5V DD
0.2V DD
0.7V DD
0.3V DD
0.8V DD
0.5V DD
V
V
CMOS
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
Open-drain
LOW-level output voltage
Schmitt-trigger
Rising-edge threshold voltage
Falling-edge threshold voltage
VIHT
VILT
VT+
VT–
Measured at crystal,
47.5% duty cycle.
See note 7.
See note 1.
See note 1.
IOH = –5.0 mA.
See note 1.
See note 3.
See note 3.
Notes:
1. D0 to D7, A0, CS, RD, WR, VD0 to VD7, VA0 to VA15,
VRD, VWR and VCE are TTL-level inputs.
2. SEL1 and NT/PL are CMOS-level inputs. YD, XD0 to
XD3, XSCL, XECL, LP, WF, YSCL, YDIS and CLO are
CMOS-level outputs.
3. RES is a Schmitt-trigger input. The pulsewidth on RES
must be at least 200 µs. Note that pulses of more than
a few seconds will cause DC voltages to be applied to
the LCD panel.
4. fOSC = 10 MHz, no load (no display memory), internal
character generator, 256 × 200 pixel display. The
operating supply current can be reduced by approximately 1 mA by setting both CLO and the display OFF.
268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238
53
4.0 Specifications
4.4 – 4.4.1
4.4 SED1330 Timing Diagrams
4.4.1 System bus READ/WRITE timing I (8080)
tAH8
A0, CS
tAW8
tCYC
tCC
WR, RD
tDS8
tDH8
D0~D7
(WRITE)
tACC8
tOH8
D0~D7
(READ)
Figure 32. System bus READ/WRITE timing I (8080)
4.4.1.1 SED1330F
Signal
A0, CS
WR, RD
D0 to D7
Note: tCYC
Symbol
tAH8
tAW8
tCYC
tCC
tDS8
tDH8
tACC8
tOH8
Ta = –20 to 75°C
Parameter
Address hold time
Address setup time
System cycle time
Strobe pulsewidth
Data setup time
Data hold time
RD access time
Output disable time
Rating
min
10
30
(1)
220
120
10
—
10
max
—
—
—
—
—
—
120
50
Unit
Condition
ns
ns
ns
ns
ns
ns
ns
ns
CL = 100
pF
= 2tC + tCC + tCEA + 75 > tACV + 245:
memory control/movement control commands:
= 4tC + tCC + 30:
all other commands:
54
S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
4.4.2 – 4.4.2.1
4.0 Specifications
4.4 SED1330 Timing Diagrams
4.4.2 System bus READ/WRITE timing II (6800)
tCYC6
E
tAW6
tEW
R/W
tAH6
A0, CS
tDS6
tDH6
D0~D7
(WRITE)
tACC6
tOH6
D0~D7
(READ)
Figure 33. System bus READ/WRITE timing II (6800)
4.4.2.1 SED1330F
Signal
A0, CS
R/W
D0 to D7
E
Symbol
t AH6
t AW6
tCYC6
t DS6
tDH6
tACC6
t OH6
t EW
Ta = –20 to 75°C
Parameter
Address hold time
Address setup time
System cycle time
Data setup time
Data hold time
Access time
Output disable time
Enable pulse width
Rating
min
10
30
(1)
120
10
—
10
220
max
—
—
—
—
—
120
50
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Condition
CL=100pF+1TTL
pF
Note: (1) tCYC6 = 2tC + tEW + tCEA + 75 > tACV + 245:
memory control/movement control commands:
= 4tC + tEW + 30:
all other commands:
1.
tCYC6 means a cycle of (CS.E) not E alone.
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55
4.0 Specifications
4.4.3 – 4.4.3.1
4.4 SED1330 Timing Diagrams
4.4.3 Display memory READ timing
tC
EXTφO
tW
tCE
tW
VCE
tCYR
VA0~VA15
tASC
VR/W
tAHC
tRCS
tRCH
tCE3
tCEA
tOH2
tACY
VD0~VD7
Figure 34. Display memory READ timing
4.4.3.1 SED1330F
Signal
Symbol
EXT Ø0
tC
tW
tCE
tCYR
tASC
tAHC
VCE
VA0
to VA15
VR/W
VD0
to VD7
tRCS
tRCH
tACV
tCEA
tOH2
tCE2
Parameter
Clock cycle
VCE high level pulse width
VCE low level pulse width
Read cycle time
VCE address setup time (fall)
VCE address hold time (fall)
VCE read cycle setup time (fall)
VCE read cycle hold time (fall)
Address access time
VCE access time
Output data hold time
VCE data off time
Note: 1.
2.
tCYR
tACV
= 3tC
= 3tC –120
3.
tCEA
= 2tC –120
56
Ta = –20 to 75°C
Rating
min
max
100
tc–40
2tc–40
—
—
—
—
—
—
—
—
(2)
(3)
—
—
(1)
tc–45
2tc–40
tc–45
tc/2–35
—
—
0
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Condition
CL = 100pF
+1TTL
S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
4.4.4 – 4.4.4.1
4.0 Specifications
4.4 SED1330 Timing Diagrams
4.4.4 Display memory WRITE timing
tC
EXTφO
tW
tCE
VCE
tASC
tCA
tAHC
VA0~VA15
tCYW
tAS tWSC
tWHC
tAH2
VWR
tOSC
tOH2
tOHC
VD0~VD7
Figure 35. Display memory WRITE timing
4.4.4.1 SED1330F
Signal
Symbol
EXT Ø0
tC
tW
t CE
VCE
VA0
to VA15
VR/W
VD0
to VD7
tCYW
tAHC
t ASC
t CA
tAS
t AH2
tWSC
t WHC
tDSC
t DHC
tDH2
Ta = –20 to 75°C
Parameter
Clock cycle
VCE high level pulse width
VCE low level pulse width
Write cycle time
VCE address hold time (fall)
VCE address setup time (fall)
VCE address hold time (rise)
VR/W address setup time (fall)
VR/W address hold time (rise)
VCE write setup time (fall)
VCE write hold time (fall)
VCE data input setup time (fall)
VCE data input hold time (fall)
VR/W data hold time (rise)
Rating
min
max
100
tc–40
2tc–40
3tc
2tc–40
tc–55
5
0
15
tc–55
tc2–40
twsc–10
2tc–30
10*
—
—
—
—
—
—
—
—
—
—
—
—
—
50
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Condition
CL = 100pF
+1TTL
* Lines VD0 to VD7 are latched.
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57
4.0 Specifications
4.4.5
4.4 SED1330 Timing Diagrams
4.4.5 LCD control timing
ROW NO
LP
1 frame period
YD
WF
YSCL
1 line period
WF
YSCL
ROW64
ROW1
ROW2
LP
XSCL
XD0~XD3
XECL
tr
XSCL
tWX
tf
tCX
tDS
tDH
XD0~XD3
tWL
LP
tL1
tL2
tS2
XECL
tS1
tWXE
WF(B)
YD
tDf
YSCL
tLD
tDHY
tWY
Figure 36. LCD control timing
58
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4.4.5.1
4.0 Specifications
4.4 SED1330 Timing Diagrams
4.4.5.1 SED1330F
Ta = –20 to 75°C
Signal
Symbol
EXT Ø0
tC
tr
tf
t CX
t WX
tDH
XSCL
XD0
to XD3
LP
XECL
WF
YSCL
YD
t DS
tLS
t WL
tL1
tL2
tS1
tS1
t WXE
tDF
t LD
t WY
tDHY
Parameter
Clock cycle
VCE high level pulse width
VCE low level pulse width
Shift clock cycle time
XSCL clock pulse width
X-data hold time
X-data setup time
Latch data setup time
LP signal pulse width
XECL setup time
XECL data hold time
Enable setup time
Enable delay time
XECL clock pulse width
Time allowance of WF delay
LP delay time against YSCL
YSCL clock pulse width
Y-data hold time
Rating
min
100
—
—
4tc
t CX2–80
t CX2–100
t CX2–100
t CX2–100
t CX4–80
t CX3–100
t C–30
t C–30
t C–30
t CX3–80
—
t CX4–100
t CX4–80
t CX6–100
max
—
35
35
—
—
—
—
—
—
—
—
—
—
—
100
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Condition
VDD = 5.0V
±10%
CL=150F
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59
4.0 Specifications
4.4 .6– 4.4.6.1
4.4 SED1330 Timing Diagrams
4.4.6 Oscillator timing
VDD
tOSP
CLO
tOSS
YDIS
Power ON
Sleep period
tRCL
tFCL
EXT 0O
tWL
tWH
tCL
Figure 37. Oscillator timing
4.4.6.1 SED1330F
Signal
CLO
EXTø0
Ta = –20 to 75°C
Symbol
Parameter
tOSP
tOSS
tRCL
tFCL
tWH
tWL
tCL
Time to stable CLO output after power ON
Time to stable CLO output after sleep OFF
External clock rise time
External clock fall time
External clock high-pulse width
External clock low-pulse width
External clock cycle
Rating
min
max
—
3
—
1
—
15
—
15
Note 1
Note 2
Note 1
Note 2
100
—
Unit
Condition
ms
ms
ns
ns
ns
ns
ns
RES = H
20 pF
1. (tC – tRCL – tFCL) X 475/1000 < tWH, tWL
2. (tC – tRCL – tFCL) X 525/1000 > tWH, tWL
60
S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
4.4.7
4.0 Specifications
4.4 SED1330 Timing Diagrams
4.4.7 Measurement circuit
VDD
2.1 KΩ
Measurement
Terminal
C = 100 pF
24 KΩ
IN 916
COMPATABLE
VSS
* C includes probe capacitance.
Figure 38. Measurement circuit
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61
4.0 Specifications
4.5 – 4.5.1.1
4.5 SED1335/SED1336 AC Timing Diagrams
4.5.1 8080 family Interface Timing
AO, CS
tAW8
tAH8
tCYC
WR, RD
tCC
tDH8
tDS8
D0 to D7
(Write)
tACC8
tOH8
D0 to D7
(Read)
Figure 39. 8080 family interface timing
4.5.1.1 SED1335F
Signal
A0, CS
WR, RD
D0 to D7
Symbol
tAH8
tAW8
tCYC
tCC
tDS8
tDH8
tACC8
tOH8
Ta = –20 to 75°C
Parameter
Address hold time
Address setup time
System cycle time
Strobe pulsewidth
Data setup time
Data hold time
RD access time
Output disable time
VDD = 4.5 to 5.5V VDD = 2.7 to 4.5V
min
max
min
max
10
—
10
—
0
—
0
—
See note
See note
—
—
120
—
150
—
120
—
120
—
5
—
5
—
—
50
—
80
10
50
10
55
Unit
Condition
ns
ns
ns
ns
ns
ns
ns
ns
CL = 100
pF
Note: For memory control and system control commands:
tCYC8 = 2tC + tCC + tCEA + 75 > tACV + 245
For all other commands:
tCYC8 = 4tC + tCC + 30
62
S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
4.5.1.2
4.0 Specifications
4.5.1.2 SED1336F
Ta = –20 to 75°C
Signal
A0, CS
WR, RD
D0 to D7
Symbol
t AH8
t AW8
tCYC
tCC
t DS8
tDH8
tACC8
t OH8
Parameter
Address hold time
Address setup time
System cycle time
Strobe pulsewidth
Data setup time
Data hold time
RD access time
Output disable time
VDD = 4.5 to 5.5V VDD = 3.0 to 4.5V
min
max
min
max
10
—
10
—
0
—
0
—
See note
See note
—
—
120
—
140
—
120
—
120
—
5
—
5
—
—
50
—
70
10
50
10
50
Unit
Condition
ns
ns
ns
ns
ns
ns
ns
ns
CL = 100
pF
Note: For memory control and system control commands:
tCYC8 = 2tC + tCC + tCEA + 75 > tACV + 245
For all other commands:
tCYC8 = 4tC + tCC + 30
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63
4.0 Specifications
4.5.2
4.5.2 6800 family Interface Timing
E
tCYC
tAW6
tEW
R/W
tAH6
AO, CS
tDH6
tDS6
D0 to D7
(Write)
tACC6
tOH6
D0 to D7
(Read)
Note: tCYC6 indicates the interval during which CS is LOW and E is HIGH.
Figure 40. 6800 family interface timing
64
S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
4.5.2.1 – 4.5.2.2
4.0 Specifications
4.5.2.1 SED1335F
Signal
Symbol
A0,
CS,
R/W
tCYC6
t AW6
t AH6
t DS6
tDH6
t OH6
tACC6
t EW
D0 to D7
E
Ta = –20 to 75°C
Parameter
System cycle time
Address setup time
Address hold time
Data setup time
Data hold time
Output disable time
Access time
Enable pulsewidth
VDD = 4.5 to 5.5V VDD = 2.7 to 4.5V
min
max
min
max
See note
—
See note
—
0
—
10
—
0
—
0
—
100
—
120
—
0
—
0
—
10
50
10
75
—
85
—
130
120
—
150
—
Unit
Condition
ns
ns
ns
ns
ns
ns
ns
ns
CL =
100 pF
Note: For memory control and system control commands:
tCYC6 = 2tC + tEW + tCEA + 75 > tACV + 245
For all other commands:
tCYC6 = 4tC + tEW + 30
4.5.2.2 SED1336F
Signal
Symbol
A0,
CS,
R/W
tCYC6
t AW6
t AH6
t DS6
tDH6
t OH6
tACC6
t EW
D0 to D7
E
Ta = –20 to 75°C
Parameter
System cycle time
Address setup time
Address hold time
Data setup time
Data hold time
Output disable time
Access time
Enable pulsewidth
VDD = 4.5 to 5.5V VDD = 3.0 to 4.5V
min
max
min
max
See note
—
See note
—
0
—
10
—
0
—
0
—
100
—
120
—
0
—
0
—
10
50
10
70
—
85
—
120
120
—
140
—
Unit
Condition
ns
ns
ns
ns
ns
ns
ns
ns
CL =
100 pF
Note: For memory control and system control commands:
tCYC6 = 2tC + tEW + tCEA + 75 > tACV + 245
For all other commands:
tCYC6 = 4tC + tEW + 30
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65
4.0 Specifications
4.5.3 – 4.5.3.1
4.5.3 Display Memory Read Timing
EXTΦ0
tC
tW
tCE
tW
VCE
tCYR
VA0 to VA15
tASC
tAHC
tRCH
VRD
tRCS
tCEA
tCE3
tOH2
tACV
VD0 to VD7
(SED1335F)
Figure 41. Display memory read timing
4.5.3.1 SED1335F
Ta = –20 to 75°C
Signal
Symbol
EXT φ0
tC
tW
VCE
tCE
tCYR
VA0 to
VA15
tASC
tAHC
tRCS
VRD
tRCH
VD0 to
VD7
66
tACV
tCEA
tOH2
tCE3
Parameter
Clock period
VCE HIGH-level pulsewidth
VCE LOW-level pulsewidth
VDD = 4.5 to 5.5V VDD = 2.7 to 4.5V
min
max
min
max
100
—
125
—
Unit
ns
tC – 50
—
tC – 50
—
ns
2tC – 30
—
2tC – 30
—
ns
Read cycle time
3tC
—
3t C
—
Address setup time to
—
tC – 100
—
tC – 70
falling edge of VCE
Address hold time from
—
2tC – 40
—
2tC – 30
falling edge of VCE
Read cycle setup time to
tC – 45
—
tC – 60
—
falling edge of VCE
Read cycle hold time
—
0.5tC
—
0.5tC
from rising edge of VCE
Address access time
—
3tC – 100
—
3tC – 115
VCE access time
—
2tC – 80
—
2tC – 90
Output data hold time
0
—
0
—
VCE to data off time
0
—
0
—
Condition
ns
ns
ns
CL = 100
pF
ns
ns
ns
ns
ns
ns
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4.5.3.2
4.0 Specifications
4.5.3.2 SED1336F
Ta = –20 to 75°C
Signal
Symbol
EXT φ0
tC
tW
VCE
t CE
tCYR
VA0 to
VA15
t ASC
tAHC
tRCS
VRD
t RCH
VD0 to
VD7
t ACV
t CEA
t OH2
t CE3
Parameter
Clock period
VCE HIGH-level pulsewidth
VCE LOW-level pulsewidth
Read cycle time
Address setup time to
falling edge of VCE
Address hold time from
falling edge of VCE
Read cycle setup time to
falling edge of VCE
Read cycle hold time
from rising egde of VCE
Address access time
VCE access time
Output data hold time
VCE to data off time
VDD = 4.5 to 5.5V VDD = 3.0 to 4.5V
min
max
min
max
100
—
125
—
Unit
Condition
ns
tC – 50
—
tC – 50
—
ns
2tC – 30
—
2tC – 30
—
ns
3tC
—
3t C
—
ns
tC – 70
—
tC – 100
—
ns
2tC – 30
—
2tC – 40
—
ns
tC – 45
—
tC – 55
—
ns
0.5tC
—
0.5tC
—
ns
—
—
0
0
3tC – 100
2tC – 80
—
—
—
—
0
0
3tC – 110
2tC – 85
—
—
ns
ns
ns
ns
CL = 100
pF
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67
4.0 Specifications
4.5.4
4.5.4 Display Memory Write Timing
tC
EXTφO
tW
tCE
VCE
tASC
tCA
tAHC
VA0~VA15
tCYW
tAS tWSC
tWHC
tAH2
VWR
tOSC
tOH2
tOHC
VD0~VD7
Figure 42. Display memory write timing
68
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4.5.4.1
4.0 Specifications
4.5.4.1 SED1335F
Ta = –20 to 75°C
Signal
Symbol
EXT φ0
tC
tW
VCE
t CE
tCYW
tAHC
t ASC
VA0 to
VA15
t CA
tAS
t AH2
tWSC
VWR
t WHC
tDSC
VD0 to
VD7
t DHC
tDH2
Parameter
Clock period
VCE HIGH-level pulsewidth
VCE LOW-level pulsewidth
Write cycle time
Address hold time from
falling edge of VCE
Address setup time to
falling edge of VCE
Address hold time from
rising edge of VCE
Address setup time to
falling edge of VWR
Address hold time from
rising edge of VWR
VDD = 4.5 to 5.5V VDD = 2.7 to 4.5V
min
max
min
max
100
—
125
—
Unit
ns
tC – 50
—
tC – 50
—
ns
2tC – 30
—
2tC – 30
—
ns
3tC
—
3t C
—
ns
2tC – 30
—
2tC – 40
—
ns
tC – 70
—
tC – 110
—
ns
0
—
0
—
ns
0
—
0
—
ns
10
—
10
—
ns
—
tC – 115
—
ns
—
2tC – 20
—
ns
—
tC – 125
—
ns
—
2tC – 30
—
ns
50
5
50
ns
Write setup time to falling
tC – 80
edge of VCE
Write hold time from fall2tC – 20
ing edge of VCE
Data input setup time to
tC – 85
falling edge of VCE
Data input hold time
2tC – 30
from falling edge of VCE
Data hold time from
5
rising edge of VWR
Condition
CL = 100
pF
Note: VD0 to VD7 are latching input/outputs. While the bus is high impedance, VD0 to VD7 retain the write data until the data read
from the memory is placed on the bus.
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69
4.0 Specifications
4.5.4.2
4.5.4.2 SED1336F
Ta = –20 to 75°C
Signal
Symbol
EXT φ0
tC
tW
VCE
tCE
tCYW
tAHC
tASC
VA0 to
VA15
tCA
tAS
tAH2
tWSC
VWR
tWHC
tDSC
VD0 to
VD7
tDHC
tDH2
Parameter
Clock period
VCE HIGH-level pulsewidth
VCE LOW-level pulsewidth
Write cycle time
Address hold time from
falling edge of VCE
Address setup time to
falling edge of VCE
Address hold time from
rising edge of VCE
Address setup time to
falling edge of VWR
Address hold time from
rising edge of VWR
VDD = 4.5 to 5.5V VDD = 3.0 to 4.5V
min
max
min
max
100
—
125
—
Unit
ns
tC – 50
—
tC – 50
—
ns
2tC – 30
—
2tC – 30
—
ns
3tC
—
3t C
—
ns
2tC – 30
—
2tC – 40
—
ns
tC – 70
—
tC – 100
—
ns
0
—
0
—
ns
0
—
0
—
ns
10
—
10
—
ns
—
tC – 110
—
ns
—
2tC – 20
—
ns
—
tC – 120
—
ns
—
2tC – 30
—
ns
50
5
50
ns
Write setup time to falling
tC – 80
edge of VCE
Write hold time from fall2tC – 20
ing edge of VCE
Data input setup time to
tC – 85
falling edge of VCE
Data input hold time
2tC – 30
from falling edge of VCE
Data hold time from
5
rising edge of VWR
Condition
CL = 100
pF
Note: VD0 to VD7 are latching input/outputs. While the bus is high impedance, VD0 to VD7 retain the write data until the data read
from the memory is placed on the bus.
70
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4.5.5 – 4.5.5.2
4.0 Specifications
4.5.5 SLEEP IN Command Timing
VCE
SLEEP IN write
SYSTEM SET write
tWRL
tWRD
WR
(command input)
YDIS
Figure 43. SLEEP IN command timing
4.5.5.1 SED1335F
Ta = –20 to 75°C
Signal
Symbol
t WRD
WR
tWRL
Parameter
VCE falling-edge delay
time
YDIS falling-edge delay
time
VDD = 4.5 to 5.5V VDD = 2.7 to 4.5V
min
max
min
max
Unit
See note 1
—
See note 1
—
ns
—
See note 2
—
See note 2
ns
Condition
CL = 100
pF
Notes:
1. tWRD = 18tC + tOSS + 40 (tOSS is the time delay from the sleep state until stable operation)
2. tWRL = 36tC × [TC/R] × [L/F] + 70
4.5.5.2 SED1336F
Ta = –20 to 75°C
Signal
Symbol
t WRD
WR
tWRL
Parameter
VCE falling-edge delay
time
YDIS falling-edge delay
time
VDD = 4.5 to 5.5V VDD = 3.0 to 4.5V
min
max
min
max
Unit
See note 1
—
See note 1
—
ns
—
See note 2
—
See note 2
ns
Condition
CL = 100
pF
Notes:
1. tWRD = 18tC + tOSS + 40 (tOSS is the time delay from the sleep state until stable operation)
2. tWRL = 36tC × [TC/R] × [L/F] + 70
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71
4.0 Specifications
4.5.6 – 4.5.6.2
4.5.6 External Oscillator Signal Timing
tRCL
tFCL
EXTφ0
tWL
tWH
tCL
Figure 44. External oscillator signal timing
4.5.6.1 SED1335F
Ta = –20 to 75°C
Signal
Symbol
tRCL
tFCL
EXT φ0
tWH
tWL
tC
Parameter
External clock rise time
External clock fall time
External clock
HIGH-level pulsewidth
External clock
LOW-level pulsewidth
External clock period
VDD = 4.5 to 5.5V VDD = 2.7 to 4.5V
min
max
min
max
—
15
—
15
—
15
—
15
Unit
ns
ns
See note 1 See note 2 See note 1 See note 2
ns
See note 1 See note 2 See note 1 See note 2
ns
100
—
125
—
Condition
ns
Notes:
1.
(tC – tRCL – tFCL) ×
475
< tWH, tWL
1000
2.
(tC – tRCL – tFCL) ×
525
> tWH, tWL
1000
4.5.6.2 SED1336F
Ta = –20 to 75°C
Signal
Symbol
tRCL
tFCL
EXT φ0
tWH
tWL
tC
Parameter
External clock rise time
External clock fall time
External clock
HIGH-level pulsewidth
External clock
LOW-level pulsewidth
External clock period
VDD = 4.5 to 5.5V VDD = 3.0 to 4.5V
min
max
min
max
—
15
—
15
—
15
—
15
Unit
ns
ns
See note 1 See note 2 See note 1 See note 2
ns
See note 1 See note 2 See note 1 See note 2
ns
100
—
125
—
Condition
ns
Notes:
72
1.
(tC – tRCL – tFCL) ×
475
< tWH, tWL
1000
2.
(tC – tRCL – tFCL) ×
525
> tWH, tWL
1000
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4.5.7
4.0 Specifications
4.5.7 LCD Output Timing
The following characteristics are for a 1/64 duty cycle.
ROW
62
63
64
1
2
3
4
60
61
62
63
64
LP
1 frame period
YD
WF
YSCL
WF
1 line period
YSCL
ROW64
ROW1
ROW2
LP
XSCL
XD0~XD3
XECL
tr
tWX
tf
tCX
XSCL
tDS
tDH
XD0~XD3
tWL
LP
tL2
tL1
tS2
tS1
XECL
tWXE
tDf
WF(B)
tLD
YD
tDHY
YSCL
tWY
Figure 45. LCD output timing
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73
4.0 Specifications
4.5.7
4.5.7.1 SED1330F
Signal
Symbol
tr
tf
XSCL
XD0
to XD3
LP
XECL
WF
YSCL
YD
tCX
tWX
tDH
tDS
tLS
tWL
tL1
tL2
tS1
tS1
tWXE
tDF
tLD
tWY
tDHY
Ta = –20 to 75°C
Rating
Parameter
VCE high level pulse width
VCE low level pulse width
Shift clock cycle time
XSCL clock pulse width
X-data hold time
X-data setup time
Latch data setup time
LP signal pulse width
XECL setup time
XECL data hold time
Enable setup time
Enable delay time
XECL clock pulse width
Time allowance of WF delay
LP delay time against YSCL
YSCL clock pulse width
Y-data hold time
min
—
—
4tc–70
2t C–80
2t C–100
2t C–100
2tC–100
4t C–80
3tC–100
tC–30
tC–30
tC–30
3t C–80
—
4tC–100
4t C–80
6t C–100
max
35
35
—
—
—
—
—
—
—
—
—
—
—
100
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Condition
VDD = 5.0V
±10%
CL=150F
Notes:
1. The E-1330 reads display memory data from the address of the top left corner of the display screen, then scans horizontally until
it reaches the address for the bottom right corner of the display screen. Therefore, each line of X-driver data is sent starting from
the left side of the display line.
2. The E-1330 uses nine cycles of ø0 as the basic cycle (tc). The XSCL waveform is shown in the following figure.
ø0
4 tC
5 tC
XSCL
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4.5.7.2 – 4.5.7.3
4.0 Specifications
4.5.7.2 SED1335F
Ta = –20 to 75°C
Signal
Symbol
tr
tf
XSCL
XD0 to
XD3
LP
WF
YD
t CX
t WX
tDH
t DS
tLS
t WL
t LD
tDF
tDHY
VDD = 4.5 to 5.5V
min
max
Rise time
—
30
Fall time
—
30
Shift clock cycle time
4tC
—
XSCL clock pulsewidth
2tC – 60
—
X data hold time
2tC – 50
—
X data setup time
2tC – 100
—
Latch data setup time
2tC – 50
—
LP pulsewidth
4tC – 80
—
LP delay time from XSCL
0
—
Permitted WF delay
—
50
Y data hold time
2tC – 20
—
Parameter
VDD = 2.7 to 4.5V
min
max
—
40
—
40
4t C
—
2tC – 60
—
2tC – 50
—
2tC – 105
—
2tC – 50
—
4tC – 120
—
0
—
—
50
2tC – 20
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Condition
CL =
100 pF
4.5.7.3 SED1336F
Ta = –20 to 75°C
Signal
Symbol
tr
tf
XSCL
XD0 to
XD3
LP
WF
YD
t CX
t WX
tDH
t DS
tLS
t WL
t LD
tDF
tDHY
VDD = 4.5 to 5.5V VDD = 3.0 to 4.5V
min
max
min
max
Rise time
—
30
—
35
Fall time
—
30
—
35
Shift clock cycle time
4tC
—
4t C
—
XSCL clock pulsewidth
2tC – 60
—
2tC – 60
—
X data hold time
2tC – 50
—
2tC – 50
—
X data setup time
2tC – 100
—
2tC – 100
—
Latch data setup time
2tC – 50
—
2tC – 50
—
LP pulsewidth
4tC – 80
—
4tC – 100
—
LP delay time from XSCL
0
—
0
—
Permitted WF delay
—
50
—
50
Y data hold time
2tC – 20
—
2tC – 20
—
Parameter
Unit
Condition
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CL =
100 pF
Note: The SED1335F/1336F reads display memory data from the address of the top left corner of the display screen, then scans
horizontally until it reaches the address for the bottom right corner of the display screen. Therefore, each line of X-driver data
is sent starting from the left side of the display line.
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75
THIS PAGE INTENTIONALLY BLANK
76
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5.0
Display Control Functions
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77
THIS PAGE INTENTIONALLY BLANK
78
S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
5.0 – 5.1
5.0 Display Control Functions
5.0 Display Control Functions
5.1 Character Configuration
The origin of each character bitmap is in the top left
corner as shown in Figure 38. Adjacent bits in each
byte are horizontally adjacent in the corresponding
character image.
Although the size of the bitmap is fixed by the character generator, the actual displayed size of the character field can be varied in both dimensions.
If the area outside the character bitmap contains only
zeros, the displayed character size can easily be
increased by increasing FX and FY, as the zeros
ensure that the extra space between displayed characters is blank.
The displayed character width can be set to any value
up to 16 even if each horizontal row of the bitmap is
two bytes wide.
Character starting point
FX
D7
Character
height
FY
Space
Character width
Space
to
D0
R0
0
1
1
1
0
0
0
0
R1
1
0
0
0
1
0
0
0
R2
1
0
0
0
1
0
0
0
R3
1
0
0
0
1
0
0
0
R4
1
1
1
1
1
0
0
0
R5
1
0
0
0
1
0
0
0
R6
1
0
0
0
1
0
0
0
R7
0
0
0
0
0
0
0
0
R8
0
0
0
0
0
0
0
0
R9
0
0
0
0
0
0
0
0
R10
0
0
0
0
0
0
0
0
R11
0
0
0
0
0
0
0
0
R12
0
0
0
0
0
0
0
0
R13
0
0
0
0
0
0
0
0
R14
0
0
0
0
0
0
0
0
R15
0
0
0
0
0
0
0
0
Space
data
Space
data
Figure 46. Example of character display ([FX] ≤ 8) and generator bitmap
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79
5.0 Display Control Functions
5.1
Horizontal
non-display
area
FX
Character
Height
FY
16 dots
Space
Vertical
non-display
area
8 dots
Character width
8 dots
Space
Note: The SED1330F/1335F/1336F does not automatically insert spaces between characters. If the displayed character size is
8 pixels or less and the space between character origins is nine pixels or more, the bitmap must use two bytes per row,
even though the character image requires only one.
Figure 47. Character width greater than one byte wide ([FX] = 9)
80
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5.2 – 5.2.2
5.0 Display Control Functions
5.2 Screen Configuration
5.2.1 Screen Configuration
The basic screen configuration of the SED1330F/
1335F/1336F is as a single text screen or as overlapping text and graphics screens. The graphics screen
uses eight times as much display memory as the text
screen.
Figure 40 shows the relationship between the virtual
screens and the physical screen.
A/P
C/R
0000H
Character
memory area
0800H
07FFH
Display
memory
window
Graphics
memory area
47FFH
(0,YM)
(XW,YM)
(XM,YM)
Y
(0,0)
X
(XM,0)
Figure 48. Virtual and physical screen relationship
5.2.2 Display Address Scanning
The SED1330F/1335F/1336F scans the display memory
in the same way as a raster scan CRT screen. Each row
is scanned from left to right until the address range
equals C/R. Rows are scanned from top to bottom.
In graphics mode, at the start of each line, the address
counter is set to the address at the start of the previous
line plus the address pitch, AP.
In text mode, the address counter is set to the same
start address, and the same character data is read, for
each row in the character bitmap. However, a new row
of the character generator output is used each time.
Once all the rows in the character bitmap have been
displayed, the address counter is set to the start
address plus AP and the next line of text is displayed.
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81
5.0 Display Control Functions
1
•
•
•
8
9
•
•
•
16
17
•
•
•
24
•
•
•
•
5.2.2
SAD
SAD + 1
SAD + 2
SAD + C/R
SAD + AP
SAD + AP
+1
SAD + AP
+2
SAD + AP
+ C/R
SAD + 2AP
C/R
W/S = 0, FX = 8, FY = 8
Note: One byte of display memory corresponds to one character.
Figure 49. Character position parameters
1
SAD
SAD +1
SAD + 2
SAD + C/R
2
SAD + AP
SAD + AP
+1
SAD + AP
+2
SAD + AP
+ C/R
3
SAD + 2AP
Line 1
SAD
SAD +1
SAD + 2
AP
•
•
•
•
•
•
•
•
SAD + C/R
Line 2
SAD + AP
SAD + AP + 1
AP
SAD + AP + C/R
SAD + 2AP
Line 3
C/R
W/S = 0, FX = 8
Note: One bit of display memory corresponds to one pixel.
Figure 50. Character parameters vs. memory
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5.2.2
5.0 Display Control Functions
1
SAD1
SAD1 + 1
SAD1 + 2
SAD1 + C/R
SAD1 + AP
SAD1 + AP
+1
SAD1 + AP
+2
SAD1 + AP
+ C/R
SAD3 + 2
SAD3 + C/R
SAD3 + AP
+2
SAD3 + AP
+ C/R
•
•
•
8
9
•
•
•
16
17
SAD1 + 2AP
•
•
•
24
25
•
•
•
(L/F)/2 = β
β+1
SAD3 + 1
•
•
•
β+8
β+9
SAD3 + AP
SAD3 + AP
+1
•
•
•
β + 16
β + 17
SAD3 + 2AP
•
•
•
β + 24
β + 25
•
•
•
•
(L/F)
C/R
W/S = 1, FX = 8, FY = 8
Note: In two-panel drive, the SED1330F/1335F/1336F reads line 1 and line β + 1 as one cycle. The upper and lower panels are
thus read alternately, one line at a time.
Figure 51. Two-panel display address indexing
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83
5.0 Display Control Functions
5.2.3
5.2.3 Display Scan Timing
Figure 44 shows the basic timing of the SED1330F/
1335F/1336F. One display memory read cycle takes
nine periods of the system clock, φ0 (f OSC). This cycle
repeats (C/R + 1) times per display line.
When reading, the display memory pauses at the end
of each line for (TC/R – C/R) display memory read
cycles, though the LCD drive signals are still generated. TC/R may be set to any value within the constraints imposed by C/R, fOSC, fFR, and the size of the
LCD panel, and it may be used to fine tune the frame
frequency. The microprocessor may also use this
pause to access the display memory data.
φ0
T0
T1
Display read cycle interval
T2
VCE
Character read interval
Graphics generator
read interval
Graphics read interval
VA
Figure 52. Display memory basic read cycle
Display period
TC/R
Divider frequency
period
C/R
Frame
period
Line 1
O
R
2
O
R
3
O
R
•
•
•
•
•
(L/F)
O
R
LP
Note: The divider adjustment interval (R) applies to both the upper and lower screens even if W/S = 1. In this case, LP is active
only at the end of the lower screen’s display interval.
Figure 53. Relationship between TC/R and C/R
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5.3 – 5.3.3
5.0 Display Control Functions
5.3 Cursor Control
5.3.1 Cursor Register Function
The SED1330F/1335F/1336F cursor address register functions as both the displayed cursor position
address register and the display memory access
address register. When accessing display memory
outside the actual screen memory, the address register must be saved before accessing the memory and
restored after memory access is complete.
the cursor layer moved within the display memory if it
is necessary to display the cursor on a layer other than
the present cursor layer.
Although the cursor is normally displayed for character data, the SED1330F/1335F/1336F may also display a dummy cursor for graphical characters. This is
only possible if the graphics screen is displayed, the
text screen is turned off and the microprocessor
generates the cursor control address.
Cursor display
address register
Cursor register
D=1
Address pointer
FC1 = 0
Figure 54. Cursor addressing
Cursor ON
FC0 = 1
Note that the cursor may disappear from the display
if the cursor address remains outside the displayed
screen memory for more than a few hundred milliseconds.
FP1 = 0
5.3.2 Cursor Movement
FP3 = 0
On each memory access, the cursor address register
changes by the amount previously specified with
CSRDIR, automatically moving the cursor to the desired location.
FP2 = 1
FP0 = 0
Block screen 1 (character
screen) OFF
Block screen 2 (graphics
screen) ON
Figure 55. Cursor display layers
5.3.3 Cursor Display Layers
Although the SED1330F/1335F/1336F can display
up to three layers, the cursor is displayed in only one
of these layers:
Two-layer configuration: First layer (L1)
Three-layer configuration: Third layer (L3)
The cursor will not be displayed if it is moved outside
the memory for its layer. Layers may be swapped or
Consider the example of displaying Chinese characters on a graphics screen. To write the display data,
the cursor address is set to the second screen block,
but the cursor is not displayed. To display the cursor,
the cursor address is set to an address within the
blank text screen block.
Since the automatic cursor increment is in address
units, not character units, the controlling microprocessor must set the cursor address register when moving
the cursor over the graphical characters.
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85
5.0 Display Control Functions
8 dots 8 dots
5.3.3
8 dots 8 dots
Block cursor
18 dots
Auto shift
Auto shift
Auto shift
Cursor address preset
Figure 56. Cursor movement
If no text screen is displayed, only a bar cursor can be
displayed at the cursor address.
If the first layer is a mixed text and graphics screen
and the cursor shape is set to a block cursor, the
86
SED1330F/1335F/1336F automatically decides which
cursor shape to display. On the text screen it displays
a block cursor, and on the graphics screen, a bar
cursor.
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5.4
5.0 Display Control Functions
5.4 Memory to Display Relationship
The SED1330F/1335F/1336F supports virtual
screens that are larger than the physical size of the
LCD panel address range, C/R. A layer of the
SED1330F/1335F/1336F can be considered as a
window in the larger virtual screen held in display
memory. This window can be divided into two
blocks, with each block able to display a different
portion of the virtual screen.
This enables, for example, one block to dynamically
scroll through a data area while the other acts as a
status message display area. See Figure 49 and 50.
AP
C/R
SAD1
W/S = 0
SAD3
Character page 1
SAD1
Character page 3
SAD3
Display page 1
W/S = 1
Display page 1
Display page 3
SAD2
Layer 1
SAD4
Character page 2
SAD2
Layer 1
Character page 2
SAD4
Display page 2
Display page 2
Display page 4
C/R
Layer 2
Layer 2
CG RAM
SAD1
C/R
Character page 1
SAD1
Display page 1
SAD3
Display page 3
C/R
SAD3 Character page 3
Layer 1
SAD2
C/R
SAD2
Display page 2
Graphics page 2
Layer 2
SAD3
C/R
Graphics page 3
C/R
SAD3
SAD2
SAD1
Display page 3
SAD2
Graphics page 2
Display page 2
Display page 1
C/R
SAD1
Layer 1
Graphics page 1
Layer 2
Layer 3
Figure 57. Display layers of memory
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87
5.0 Display Control Functions
5.4
AP
0000H
SAD1
FX
CRY
FY
CSRA
CRX
Display
window
L/F
Virtual display
memory limit
CRX
FX = Horizontal character field ≤ 16 dots
FY = Vertical character field ≤ 16 dots
CRX = Horizontal cursor size ≤ 16 dots
CRY = Vertical cursor size ≤ 16 dots
C/R = Characters per row ≤ 240 bytes
L/F = Lines per frame ≤ 256 bytes
AP = Address pitch ≤ 64 Kbytes
FFFFH
Figure 58. Display window and memory
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Back layer
Character
code
SAG
SAD2
SAD1
F000
4A00
4800
4440
2800
2000
SL2
0800
0300
0400
SL1
0000
D7
Character generator
ROM
Not used
Character generator
RAM
Page 2
Page 1
Page 2
Page 1
to
D0
to
01110000
10001000
10001000
10001000
11111000
10001000
10001000
00000000
D0
1FFF
0080
02FF
0000
#4800
1
2
3
4
5
6
#4807
D0
Example of character A
70
88
88
88
F8
88
88
00
HEX D7
χ
γ
β
α
Y
X
C
B
A (Code)
D7
(MSB)
D7
ABC
α
Magnified image
(LSB)(MSB)
D0 D7
Display
XY
β
(LSB)
D0
5.4
5.0 Display Control Functions
Figure 59. Memory map and magnified characters
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5.0 Display Control Functions
5.5 – 5.5.1
5.5 Scrolling
5.5.1 On-page Scrolling
The controlling microprocessor can set the SED1330F/
1335F/1336F scrolling modes by overwriting the scroll
address registers SAD1 to SAD4, and by directly
setting the scrolling mode and scrolling rate.
The normal method of scrolling within a page is to
move the whole display up one line and erase the
bottom line. Since the SED1330F/1335F/1336F does
not automatically erase the bottom line, it must be
erased with blanking data when changing the scroll
address register.
Display memory
AP
C/R
Before scrolling
ABC
WXYZ
SAD1
789
ABC
WXYZ
789
SAD3
After scrolling
WXYZ
789
Blank
SAD1
WXYZ
789
Blank
Figure 60. On-page scrolling
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5.5.2
5.0 Display Control Functions
5.5.2 Inter-page Scrolling
Scrolling between pages and page switching can be
performed only if the display memory capacity is
greater than one screen.
Display memory
AP
C/R
Before scrolling
After scrolling
ABC
SAD1
WXYZ
789
WXYZ
789
ABC
WXYZ
SAD1
789
ABC
WXYZ
789
Figure 61. Inter-page scrolling
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91
5.0 Display Control Functions
5.5.3
5.5.3 Horizontal Scrolling
The display can be scrolled horizontally in onecharacter units, regardless of the display memory
capacity.
Display memory
Display
Before scrolling
ABC
123
XYZ
SAD1
ABC
123
XYZ
AP
C/R
After scrolling
BC
23
XYZ1
SAD1
ABC
123
XYZ
Figure 62. Horizontal wraparound scrolling
Refer to Section 9.4 for application notes.
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5.5.4 – 5.5.5
5.0 Display Control Functions
5.5.4 Bidirectional Scrolling
Bidirectional scrolling can be performed only if the
display memory is larger than the physical screen
both horizontally and vertically. Although scrolling is
normally done in single-character units, the HDOT
SCR command can be used to scroll horizontally in
pixel units. Single-pixel scrolling both horizontally and
vertically can be performed by using the SCROLL and
HDOT SCR commands. See Section 9.4
Display memory
Before scrolling
BC
EFG
TUV
AP
12
A BC
EFG
TUV
C/R
After scrolling
12 34
567
89
ABC
E FG
TUV
FG
TUV
1234
56
1234
56 7
89
Figure 63. Bidirectional scrolling
5.5.5 Scroll Units
Table 21. Scroll units
Mode
Vertical
Text
Characters
Graphics
Pixels
Horizontal
Pixels or
characters
Pixels
Note that in a divided screen, each block cannot be independently scrolled horizontally in pixel units.
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6.0
Character Generator
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96
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6.0 – 6.1.3
6.0 Character Generator
6.0 Character Generator
6.1 CG Characteristics
6.1.1 Internal Character Generator
The internal character generator is recommended for
minimum system configurations containing a
SEDSED1330F/1335F/1336F, display RAM, LCD
panel, single-chip microprocessor and power supply.
Since the internal character generator uses a CMOS
mask ROM, it is also recommended for low-power
applications.
• 5 × 7-pixel font (See Section 10)
• 160 JIS standard characters
• Can be mixed with character generator RAM
(maximum of 64 CG RAM characters)
• Can be automatically spaced out up to 8 × 16
pixels
6.1.2 External Character Generator ROM
The external CG ROM can be used when fonts other
than those in the internal ROM are needed. Data is
stored in the external ROM in the same format used
in the internal ROM. (See Section 6.3.)
• Up to 8 × 8-pixel characters (M2 = 0) or 8 × 16pixel characters (M2 = 1)
• Up to 256 characters (192 if used together with
the internal ROM)
• Mapped into the display memory address space
at F000H to F7FFH (M2 = 0) or F000H to
FFFFH (M2 = 1)
• Characters can be up to 8 × 16-pixels; however, excess bits must be set to zero.
6.1.3 Character Generator RAM
The user can freely use the character generator RAM
for storing graphics characters. The character generator RAM can be mapped by the microprocessor
anywhere in display memory, allowing effective use of
unused address space.
• Up to 8 × 8-pixel characters (M2 = 0) or 8 × 16
characters (M2 = 1)
• Up to 256 characters if mapped at F000H to
FFFFH (64 if used together with character
generator ROM)
• Can be mapped anywhere in display memory
address space if used with the character generator ROM
• Mapped into the display memory address space
at F000H to F7FFH if not used with the character generator ROM (more than 64 characters
are in the CG RAM). Set SAG0 to F000H and
M1 to zero when defining characters number
193 upwards.
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6.0 Character Generator
6.2
6.2 CG Memory Allocation
Since the SED1335F/1336F uses 8-bit character
codes, it can handle no more than 256 characters at
a time. However, if a wider range of characters is
required, character generator memory can be bankswitched using the CGRAM ADR command.
Built–in CG ROM
(160 characters,
5 × 7 pixels max.)
M0 = 1
CG RAM
CG RAM n
CG RAM 2
SAG
CG RAM 1
(64 characters max, 8 × 16 pixels max)
Basic CG space
(256 characters,
8 × 16 pixels max.)
256 characters max.
M1 = 0
CG RAM
CG ROM
M0 = 1
256 characters max.
M1 = 0
Built-in CG ROM
(160 characters,
5 × 7 pixels max.)
CG ROM
CG RAM n
CG RAM 2
CG RAM
ADR
CG RAM 1
(64 characters max, 8 × 16 pixels max)
Note that there can be no more than 64 characters per bank.
Figure 64. Internal and external character mapping
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6.2 – 6.3
6.0 Character Generator
Table 22. Character mapping
Item
Parameter
Remarks
Internal/external character generator selection
1 to 8 pixels
M0
M2 = 0
Character field height
M2 = 1
Graphics mode (8 bits × 1 line)
9 to 16 pixels
Greater than 16 pixels
Internal CG ROM/RAM select
External CG ROM/RAM select
CG RAM bit 6 correction
M1
Specified with CG RAM ADR
Can be moved anywhere in the
command
display memory address space
Other than the area of Figure 58
CG RAM data storage address
External CG ROM
address
Determined by the
character code
Automatic
192 characters or less
More than 192 characters
Set SAG to F000H and overly
SAG and the CG ROM table.
6.3 Setting the Character Generator Address
The CG RAM addresses in the VRAM address space
are not mapped directly from the address in the SAG
register. The data to be displayed is at a CG RAM
address calculated from SAG + character code +
ROW select address. This mapping is shown in Tables
23 and 24.
Table 23. Character fonts, number of lines ≤ 8 (M2 = 0, M1 = 0)
SAG
Character code
+ROW select address
CG RAM address
A15 A14 A13 A12 A11 A10
0
0
0
0
0
0
0
0
0
0
D7
0
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
0
R2
0
R1
0
R0
VA15 VA14 VA13 VA12 VA11 VA10 VA9 VA8 VA7 VA6 VA5 VA4 VA3 VA2 VA1 VA0
Table 24. Character fonts, 9 ≤ number of lines ≤ 16 (M2 = 1, M1 = 0)
SAG
Character code
+ROW select address
CG RAM address
0
0
0
0
D7
D6
A9
D5
A8
D4
A7
D3
A6
D2
A5
D1
A4
D0
A3
0
A2
0
A1
0
A0
0
0
0
0
0
0
0
0
0
0
0
0
0
R3
R2
R1
R0
A15 A14 A13 A12 A11 A10
VA15 VA14 VA13 VA12 VA11 VA10 VA9 VA8 VA7 VA6 VA5 VA4 VA3 VA2 VA1 VA0
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99
6.0 Character Generator
Row
R3
R2
R1
R0
Row 0
0
0
0
0
Row 1
0
0
0
1
Row 2
0
0
1
0
6.3 – 6.3.2
As the character code table in Figure 58 shows, codes
80H to 9FH and E0H to FFH are allocated to the CG
RAM and can be used as desired. 80H is thus the first
code for CG RAM. As characters cannot be used if
only using graphics mode, there is no need to set the
CG RAM data.
Line 1
Line 2
Row 7
0
1
1
1
Row 8
1
0
0
0
Row 14
1
1
1
0
Row 15
1
1
1
1
Note: Lines = 1: lines in the character bitmap ≤ 8
Lines = 2: lines in the character bitmap ≥ 9
Figure 65. Row select address
6.3.1 M1 = 1
The SED1335F/1336F automatically converts all bits
set in bit 6 of character code for CG RAM 2 to zero.
Because of this, the CG RAM data areas become
contiguous in display memory.
Table 25. Character data example
CGRAM ADR
P1
P2
5CH
00H
40H
Reverse the CG RAM address calculation to calculate SAG
CSRDIR
4CH
Set cursor shift direction
to right
CSRW
P1
P2
MWRITE
P
P2
P3
P4
P5
P6
P7
P8
P8
↓
P16
46H
00H
48H
42H
70H
88H
88H
88H
F8H
88H
88H
00H
00H
↓
00H
CG RAM start address is
4800H
Write ROW 0 data
Write ROW 1 data
Write ROW 2 data
Write ROW 3 data
Write ROW 4 data
Write ROW 5 data
Write ROW 6 data
Write ROW 7 data
Write ROW 8 data
↓
Write ROW 15 data
When writing data to CG RAM:
• Calculate the address as for M1 = 0.
• Change bit 6 of the character code from “1” to
“0”.
6.3.2 CG RAM Addressing Example
• Define a pattern for the “A” in Figure 38.
• The CG RAM table start address is 4800H.
• The character code for the defined pattern is
80H (the first character code in the CG RAM
area).
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6.4
6.0 Character Generator
6.4 Character Codes
The following figure shows the character codes and
the codes allocated to CG RAM. All codes can be
used by the CG RAM if not using the internal ROM.
Upper 4 bits
Lower 4 bits
0
1
2
0
3
4
5
6
7
0 @ P
'
p
1
!
1
A Q
a
q
2
"
2
B
R
b
r
3
#
3
C
S
c
s
4
$
4
D
T
d
t
5
%
5
E
U
e
u
6
&
6
F
V
f
v
7
'
7
G W g
w
8
(
8
H
X
h
x
9
)
9
I
Y
i
y
A
*
:
J
Z
j
z
B
+
;
K
[
k
{
C
,
<
L
¥
l
|
D
.
+
M
]
m
}
E
-
\> N
^
n →
F
/
?
_
o ←
O
8
8
A
B
C
D
E
F
Figure 66. On-chip character codes
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7.0
TV Mode
(SED1336F only)
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7.0 – 7.1
7.0 TV Mode (SED1336F only)
7.0 TV Mode (SED1336F only)
When used with an external video mixer circuit, the
SED1336F can show the same display on a television
as on the LCD panel. In addition, the changeover from
LCD-only to TV-and-LCD display is instantaneous
with the changing of the T/L register using the System
Set instruction.
The TV and LCD display register parameters which
are determined by hardware constraints are shown in
Table 26.
Table 26. Register parameters
System
TC/R (Hex)
C/R (Hex)
L/F (Hex)
Clock Cycles
per
Horizontal Line
NTSC
PAL
2A
2A
1F
1F
C7
C7
388
388
LCD
≥ 2A
1F
C7
≥ 388
Oscillator
Frequency,
fO (MHz)
6.1050
6.0625
6.0625 or
6.1050
T/L
1
1
0
7.1 Sync Generator Circuit Timing
The NTSC and PAL vertical sync signal waveforms
are shown in Figure 59 and 60, respectively. The
21H
Color field I vertical blanking interval
1.5 ± 0.1µs
Pre-blanking
interval
2
Start of
field I
3H
3
4
H
H
Horizontal
sync interval
Display
interval
21H
TI
3H
1
H
vertical sync timing parameters and VSD output states
are shown in Table 27.
Interval before
equalizing pulses
5
3H
6
7
8
11H
9
10
19
20
H
Equalizing
pulse interval
Vertical Sync
pulse interval
Vertical serration
pulse interval
0.5H
Interval after
equalizing pulses
Reference
subcarrier phase
color field I
Postblanking
interval
Display
interval
9-line vertical interval
Figure 67. NTSC vertical sync waveform
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7.0 TV Mode (SED1336 only)
7.1
Field blanking (25H + a) (a = 11-line blanking interval)
42H
2.5H
311
Display
period
Pre-blanking
interval
2.5H
312
Interval before
equalizing pulses
313
314
2.5H
315
Vertical sync
pulse interval
316
317
17.5H
318
319
45H
320
335
Reference
subcarrier phase
color field I
Interval after
equalizing pulses
Postblanking
interval
Display
interval
Figure 68. PAL vertical sync waveform
Table 27. Vertical sync timing characteristics
Interval
Interval
Reference
Vertical
Postbefore
after
Subcarrier
Sync Pulse
blanking
Equalizing
Equalizing Phase Color
Interval
Interval
Pulse
Pulse
Field I
Display
Interval
Equalizing
Pulse
Interval
Vertical
Serration
Pulse
Interval
Parameter
Preblanking
Interval
NTSC
system
timing
21H
3H
3H
3H
11H
21H
200H
15CK
27CK
PAL
system
timing
42H
2.5H
2.5H
2.5H
17.5H
45H
200H
15CK
27CK
VSD
output
level
High
impedance
LOW
LOW
LOW
LOW
High
impedance
LOW or
high
impedance
—
—
Notes:
1. The NTSC system uses 262 lines per screen, and the PAL system, 312.
2. H = Horizontal line period
CK = Oscillator period
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7.1
7.0 TV Mode (SED1336 only)
The horizontal sync signal waveforms are shown in
Figure 61, and the timing parameters and VSD output
SNC
High
impedance
VSD
High
impedance
Display
interval
Preblanking
interval
states, in Table 28. Note that SNC and VSD are both
high-impedance when in LCD mode.
High
impedance
Low or high
impedance
Front
porch
Horizontal
sync
pulse
Back porch
Postblanking
interval
Display
interval
Figure 69. Horizontal sync waveforms
Table 28. Horizontal sync characteristics
Parameter
NTSC
system timing
PAL
system timing
VSD
output level
Pre-blanking
Front Porch
Interval
Horizontal
Sync Pulse
Back Porch
Post-blanking
Interval
Display
Interval
29CK
10CK
29CK
28CK
36CK
256CK
29CK
10CK
29CK
34CK
30CK
256CK
High
impedance
LOW
LOW
LOW
High
impedance
LOW or High
impedance
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8.0
Description of Circuit Blocks
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110 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
8.0 – 8.1.2.3
8.0 Description of Circuit Blocks
8.0 Description of Circuit Blocks
8.1 Microprocessor Interface
8.1.1 System Bus Interface
8.1.2 Microprocessor Synchronization
SEL1, SEL2 (SED1330F and SED1335F only), A0,
RD, WR and CS are used as control signals for the
microprocessor data bus. A0 is normally connected to
the lowest bit of the system address bus. SEL1 and
SEL2 change the operation of the RD and WR pins to
enable interfacing to either an 8080 or 6800 family
bus, and should have either a pull-up or a pull-down
resistor.
The SED1330F/1335F/1336F interface operates at
full bus speed, completing the execution of each
command within the cycle time, tCYC. The controlling
micro-processor’s performance is thus not hampered
by polling or handshaking when accessing the
SED1330F/1335F/1336F.
With microprocessors using an 8080 family interface,
the SED1330F/1335F/1336F is normally mapped into
the I/O address space.
Display flicker may occur if there is more than one
consecutive access that cannot be ignored within a
frame. The microprocessor can minimize this either
by performing these accesses intermittently, or by
continuously checking the status flag (D6) and waiting
for it to become HIGH.
8.1.1.1 8080 series
Table 29. 8080 series interface signals
A0 RD WR
Function
0
0
1 Status flag read
Display data and cursor address
1
0
1
read
0
1
0 Display data and parameter write
1
1
0 Command write
8.1.2.1 Display Status Indication Output
(For SED1336 only)
When CS, A0 and RD are LOW, D6 functions as the
display status indication output. It is HIGH during the
TV-mode vertical retrace period or the LCD-mode
horizontal retrace period, and LOW, during the period
the controller is writing to the display. By monitoring
D6 and writing to the data memory only during retrace
periods, the display can be updated without causing
screen flicker.
8.1.1.2 6800 series
Table 30. 6800 series interface signals
A0 RD WR
Function
0
1
1 Status flag read
Display data and cursor address
1
1
1
read
0
0
1 Display data and parameter write
1
0
1 Command write
8.1.2.2 Internal Register Access
The SYSTEM SET and SLEEP IN commands can be
used to perform input/output to the SED1330F/1335F/
1336F independently of the system clock frequency.
These are the only commands that can be used while
the SED1330F/1335F/1336F is in sleep mode.
8.1.2.3 Display Memory Access
The SED1330F/1335F/1336F supports a form of
pipelined processing, in which the microprocessor
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8.0 Description of Circuit Blocks
8.1.2.3
synchronizes its processing to the SED1330F/1335F/
1336F’s timing. When writing, the microprocessor
first issues the MWRITE command. It then repeatedly
writes display data to the SED1336F using the system bus timing. This ensures that the microprocessor
is not slowed down even if the display memory
access times are slower than the system bus access
times. See Figure 70.
When reading, the microprocessor first issues the
MREAD command, which causes the SED1330F/
1335F/1336F to load the first read data into its output
buffer. The microprocessor then reads data from the
SED1330F/1335F/1336F using the system bus timing. With each read, the SED1330F/1335F/1336F
reads the next data item from the display memory
ready for the next read access. See Figure 71.
tCYC
WR
Microprocessor
Command write
Data write
Data write
D0 to D7
WR/W
Display memory
VD0 to VD7
Figure 70. Display memory write cycle
WR
tCYC
Command write
Microprocessor
RD
Data read
Data read
D0 to D7
WR/W
Display memory
VD0 to VD7
Figure 71. Display memory read cycle
Note: A possible problem with the display memory read cycle is that the system bus access time, tACC, does not depend on the display
memory access time, tACV. The microprocessor may only make repeated reads if the read loop time exceeds the SED1330F/
1335F/1336F cycle time, tCYC. If it does not, NOP instructions may be inserted in the program loop. tACC, tACV and tCYC limits
are given in Section 4.3.
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8.1.3 – 8.1.3.1
8.0 Description of Circuit Blocks
8.1.3 Interface Examples
8.1.3.1 Z80® to SED1330F/1335F/1336F Interface
IORQ
A0
A1
to
A15
Z80®
A0
Decoder
CS
SED1335F/
D0
to
D7
D0
to
D7
RD
RD
SEL 1
WR
WR
SEL 2
1336F
RES
RESET
RESET
Note: Z80® is a registered trademark of Zilog Corporation.
Figure 72. Z80® to SED1330F/1335F/1336F* interface
Note: *For SED1336F: SEL 2 is open..
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8.0 Description of Circuit Blocks
8.1.3.2
8.1.3.2 6802 to SED1330F/1335F/1336F Interface
VMA
A0
A1
to
A15
A0
Decoder
CS
SED1335F/
6802
D0
to
D7
D0
to
D7
E
RD
SEL 1
R/W
WR
SEL 2
RESET
1336F
VDD
RES
RESET
Figure 73. 6802 to SED1330F/1335F/1336F interface
Note: *For SED1336F: SEL 2 is open..
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8.2 – 8.2.2
8.0 Description of Circuit Blocks
8.2 Display Memory Interface
8.2.1 Static RAM
The figure below shows the interface between an 8K
× 8 static RAM and the SED1330F/1335F/1336F.
Note that bus buffers are required if the bus is heavily
loaded.
VA0 to VA12
A0 to A12
HC138
VA13 to VA15
VCE
A
to
C
Y
CE1
VDD
CE2
6264 SRAM
SED1335F/
1336F
OE
VR/W
I/O1 to I/O8
R/W
I/O1 to I/O8
Figure 74. Static RAM interface
8.2.2 Supply Current during Display Memory Access
The 24 address and data lines of the SED1330F/
1335F/1336F cycle at one-third of the oscillator frequency, fOSC. The charge and discharge current on
these pins, IVOP, is given by the equation below.
When IVOP exceeds I OPR, it can be estimated by:
IVOP ∝ C V f
where C is the capacitance of the display memory
bus, V is the operating voltage, and f is the operating
frequency.
If VOPR = 5.0V, f = 1.0 MHz, and the display memory
bus capacitance is 1.0 pF per line:
IVOP ≤ 120 µA / MHz × pF
To reduce current flow during display memory accesses, it is important to use low-power memory, and
to minimize both the number of devices and the
parasitic capacitance.
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8.0 Description of Circuit Blocks
8.3 – 8.4
8.3 Oscillator Circuit
8.4 Status Flag
The SED1330F/1335F/1336F incorporates an oscillator circuit. A stable oscillator can be constructed
simply by connecting an AT-cut crystal and two capacitors to OSC1 and OSC2, as shown in the figure
below. If the oscillator frequency is increased, CD and
CG should be decreased proportionally.
The SED1330F/1335F/1336F has a single bit status
flag.
D6: X line standby
D7
Note that the circuit board lines to OSC1 and OSC2
must be as short as possible to prevent wiring capacitance from changing the oscillator frequency or increasing the power consumption.
OSC2
CD = 3 to 20 pF
CG
CD
D6
X
X
X
X
X
X
X: Don’t care
Figure 76. Status flag
The D6 status flag is LOW (0) for the TC/R - C/R cycles
at the end of each line where the SED1330F/1335F/
1336F is not reading the display memory. The microprocessor may use this period to update display
memory without affecting the display; however, it is
recommended that the display be turned off when
refreshing the whole display.
SED1335F/1336F
OSC1
X
D0
CG = 2 to 18 pF
Load impedance = 700 Ω (max)
Figure 75. Crystal oscillator
LP
tTC/R
tm
tC/R
XSCL
Figure 77. C/R to TC/R time difference
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8.4 – 8.5
8.0 Description of Circuit Blocks
8.5 Reset
The SED1330F requires a reset pulse at least 1 ms
long after power-on in order to re-initialize its internal
state. The SED1335F/1336F requires a minimum
reset pulse of 200µs.
Read Status Flag
No
During reset, the LCD drive signals XD, LP and FR are
halted.
D6 = 1?
For maximum reliability, it is not recommended to
apply a DC voltage to the LCD panel while the
SED1330F/1335F/1336F is reset. Turn off the LCD
power supplies for at least one frame period after the
start of the reset pulse.
Yes
Data Input
No
The SED1330F/1335F/1336F cannot receive commands while it is reset. Commands to initialize the
internal registers should be issued soon after a reset.
Data Input ?
Yes
A delay of 3 ms (maximum) is required following the
rising edges of both RES and VDD to allow for system
stabilization.
Figure 78. Flowchart for busy flag checking
VDD
200µs reset pulse
RES
0.7 VDD
0.3 VDD
Figure 79. Reset timing
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118 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
9.0
Application Notes
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9.0 – 9.1.1
9.0 Application Notes
9.0 Application Notes
9.1 Initialization Parameters
The parameters for the initialization commands must
be determined first. Square brackets around a parameter name indicate the number represented by the
parameter, rather than the value written to the parameter register. For example, [FX] = FX + 1.
9.1.1
• TC/R
TC/R must satisfy the condition [TC/R] ≥ [C/R]
+ 4.
• fOSC and fFR
Once TC/R has been set, the frame frequency,
fFR, and lines per frame [L/F] will also have
been set. The lower limit on the oscillator
frequency fOSC is given by:
SYSTEM SET Instruction and Parameters
fOSC ≥ ([TC/R] × 9 + 1) × [L/F] × fFR
• FX
The horizontal character field size is determined from the horizontal display size in pixels
[VD] and the number of characters per line
[VC].
[VD] / [VC] ≤ [FX]
VD: # of X-directional dots
VC: # of X-directional characters
• If no standard crystal close to the calculated
value of fOSC exists, a higher frequency crystal
can be used and the value of TC/R revised
using the above equation.
• Symptoms of an incorrect TC/R setting are
listed below. If any of these appears, check the
value of TC/R and modify it if necessary.
• Vertical scanning halts and a high-contrast horizontal line appears.
• All pixels are on or off.
• The LP output signal is absent or corrupted.
• The display is unstable.
• C/R
C/R can be determined from VC and FX.
[C/R] = RND([FX] / 8) × [VC]
where RND(x) denotes x rounded up to the
next highest integer. [C/R] is the number of
bytes per line, not the number of characters.
Table 31. Epson LCD unit example parameters (SED1335F only)
Resolution (X × Y)
[FX]
[FY]
[C/R]
TC/R
fOSC (MHz)
See Note 2
256 × 64
[FX] = 6 pixels:
256 / 6 = 42 remainder 4
= 4 blank pixels
8 or 16, depending
on the screen
[C/R] = 42 = 2AH bytes:
C/R = 29H. When using HDOT
SCR, [C/R] = 43 bytes
2DH
1.85
512 × 64
[FX] = 6 pixels:
512 / 6 = 85 remainder 2
= 2 blank pixels
8 or 16, depending
on the screen
[C/R] = 85 = 55H bytes:
C/R = 54H. When using HDOT
SCR, [C/R] = 86 bytes
58H
3.59
256 × 128
[FX] = 8 pixels:
256 / 8 = 32 remainder 0
= no blank pixels
8 or 16, depending
on the screen
[C/R] = 32 = 20H bytes:
C/R = 19H. When using HDOT
SCR, [C/R] = 33 bytes
22H
2.90
512 × 128
[FX] = 10 pixels:
512 / 10 = 51 remainder
2 = 2 blank pixels
8 or 16, depending
on the screen
[C/R] = 102 = 66H bytes:
C/R = 65H. When using HDOT
SCR, [C/R] = 103 bytes
69H
8.55
Notes:
1. The remainder pixels on the right-hand side of the display are automatically blanked by the SED1335F. There is no need to
zero the display memory corresponding to these pixels.
2. Assuming a frame frequency of 60 Hz.
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9.0 Application Notes
9.1.2
9.1.2 Initialization Example
The initialization example shown in Figure 80 is for a
SED1330F/1335F/1336F with an 8-bit microproces-
sor interface bus display unit (512 × 128 pixels).
Start
Clear first
memory layer
Supply on
Clear second
memory layer
SYSTEM SET
CSRW
SCROLL
CSR FORM
HDOT SCR
DISP ON
OVLAY
Output display
data
DISP OFF
Note: Set the cursor address to the start of each screen’s layer memory, and use MWRITE to fill the memory with space
characters, 20H (text screen only) or 00H (graphics screen only). Determining which memory to clear is explained in section
9.1.3.
Figure 80. Initialization procedure
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9.1.2
9.0 Application Notes
Table 32. Initialization procedure
No.
1
2
3
Command
Power-up
Supply
SYSTEM SET
C = 40H
P1 = 38H
P2 = 87H
P3 = 07H
P4 = 3FH
P5 = 49H
4
P6 = 7FH
P7 = 80H
P8 = 00H
SCROLL
C = 44H
P1 = 00H
P2 = 00H
P3 = 40H
P4 = 00H
P5 = 10H
P6 = 40H
P7 = 00H
P8 = 04H
Operation
Wait for at least 3 ms after reset with VDD ≥ 4.5V
initialization.
M0: Internal CG ROM
M1: CG RAM is 32 characters maximum
M2: 8 lines per character
W/S: Two-panel drive
IV: No top-line compensation
FX: Horizontal character size = 8 pixels
WF: Two-frame AC drive
FY: Vertical character size = 8 pixels
C/R: 64 display addresses per line
TC/R: Total address range per line = 90
fOSC = 6.0 MHz, fFR = 70 Hz
L/F: 128 display lines
AP: Virtual screen horizontal size is 128 addresses
First screen block start address
Set to 0000H
Display lines in first screen block = 64
Second screen block start address
Set to 1000H
Display lines in second screen block = 64
Third screen block start address
Set to 0400H
(continued)
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9.0 Application Notes
9.1.2
Table 32. Initialization procedure (continued)
No.
Command
P9 = 00H
P10 = 30H
Operation
Fourth screen block start address
Set to 3000H
Display memory
(SAD1) 0000H
(SAD3) 0400H
1st display memory page
2nd display memory page
0800H
(SAD2) 1000H
3rd display memory page
(SAD4) 3000H
4th display memory page
5000H
5
6
7
8
HDOT SCR
C = 5AH
P1 = 00H
OVLAY
C = 5BH
P1 = 01H
DISP ON/OFF
C = 58H
P1 = 56H
Clear data in first layer
Set horizontal pixel shift to zero
MX 1, MX 0: Inverse video superposition
DM 1: First screen block is text mode
DM 2: Third screen block is text mode
D: Display OFF
FC1, FC0: Flash cursor at 2 Hz
FP1, FP0: First screen block ON
FP3, FP2: Second and fourth screen blocks ON
FP5, FP4: Third screen block ON
Fill first screen layer memory with 20H (space character)
(continued)
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9.1.2
9.0 Application Notes
Table 32. Initialization procedure (continued)
No.
9
Command
Clear data in second layer
Operation
Fill second screen layer memory with 00H (blank data)
Display
Character code in every position
1st layer
Blank code in every position
2nd layer
10
11
12
CSRW
C = 46H
P1 = 00H
P2 = 00H
CSR FORM
C = 5DH
P1 = 04H
P2 = 86H
DISP ON/OFF
C = 59H
Set cursor to start of first screen block
CRX: Horizontal cursor size = 5 pixels
CRY: Vertical cursor size = 7 pixels
CM: Block cursor
Display ON
Display
13
CSR DIR
C = 4CH
Set cursor shift direction to right
(continued)
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9.0 Application Notes
9.1.2
Table 32. Initialization procedure (continued)
No.
14
Command
MWRITE
C = 42H
P1 = 20H
P2 = 45H
P3 = 50H
P4 = 53H
P5 = 4FH
P6 = 4EH
Operation
‘’
‘E’
‘P’
‘S’
‘O’
‘N’
EPSON
15
16
17
18
19
CSRW
C = 46H
P1 = 00H
P2 = 10H
CSR DIR
C = 4FH
MWRITE
C = 42H
P1 = FFH
↓
P9 = FFH
CSRW
C = 46H
P1 = 01H
P2 = 10H
MWRITE
C = 42H
Set cursor to start of second screen block
Set cursor shift direction to down
Fill in a square to the left of the ‘E’
EPSON
Set cursor address to 1001H
(continued)
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9.1.2
9.0 Application Notes
Table 32. Initialization procedure (continued)
No.
20
Command
P1 = FFH
↓
P9 = FFH
CSRW
Operation
Fill in the second screen block in the second column of line
1
Repeat operations 18 and 19 to fill in the background under
‘EPSON’
↓
Inverse display
29
MWRITE
EPSON
30
31
32
CSRW
C = 46H
P1 = 00H
P2 = 01H
CSR DIR
C = 4CH
MWRITE
C = 42H
P1 = 44H
P2 = 6FH
P3 = 74H
P4 = 20H
P5 = 4DH
P6 = 61H
P7 = 74H
P8 = 72H
P9 = 69H
P10 = 78H
P11 = 20H
P12 = 4CH
P13 = 43H
P14 = 44H
Set cursor to line three of the first screen block
Set cursor shift direction to right
‘D’
‘o’
‘t’
‘’
‘M’
‘a’
‘t’
‘r’
‘i’
‘x’
‘’
‘L’
‘C’
‘D’
Inverse display
EPSON
Dot matrix LCD
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9.0 Application Notes
9.1.3
9.1.3 Display Mode Setting Example 1: Combining Text and Graphics
• Conditions
• 320 × 200 pixels, single-panel drive (1/
200 duty cycle)
• First layer: text display
• Second layer: graphics display
• 8 × 8-pixel character font
• CG RAM not required
• Display memory allocation
• First layer (text): 320/8 = 40 characters
per line, 200/8 = 25 lines. Required
memory size = 40 × 25 = 1000 bytes.
• Second layer (graphics): 320/8 = 40 characters per line, 200/1 = 200 lines. Required memory size = 40 × 200 = 8000
bytes.
03E8H
2nd graphics layer
(8000 bytes)
0000H
1st character layer
(1000 bytes)
2327H
03E7H
Figure 81. Character over graphics layers
• Register setup procedure
SYSTEM SET
TC/R calculation
SCROLL
C=
44H
fOSC = 6 MHz
P1 =
00H
fFR = 70 Hz
P2 =
00H
P3 =
C8H
P4 =
E8H
P5 =
03H
C7H
P6 =
C8H
P7 =
28H
P7 =
XH
P8 =
00H
P8 =
XH
P9 =
XH
P10 =
XH
C=
40H
P1 =
30H
P2 =
87H
P3 =
07H
P4 =
27H
P5 =
2FH
P6 =
(1/6) × 9 × [TC/R] × 200 = 1/70
[TC/R] = 48, so TC/R = 2FH
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9.1.3 – 9.1.4
9.0 Application Notes
CSR FORM
OVLAY
C=
5DH
C=
5BH
P1 =
04H
P1 =
00H
P2 =
86H
DISP ON/OFF
HDOT SCR
C=
59H
C=
5AH
P1 =
16H
P1 =
00H
X = Don’t care
9.1.4 Display Mode Setting Example 2: Combining Graphics and Graphics
• Conditions
• 320 × 200 pixels, single-panel drive (1/
200 duty cycle)
• First layer: graphics display
• Second layer: graphics display
• Display memory allocation
• First layer (graphics): 320/8 = 40 characters per line, 200/1 = 200 lines. Required
memory size = 40 × 200 = 8000 bytes.
• Second layer (graphics): 320/8 = 40 characters per line, 200/1 = 200 lines. Required memory size = 8000 bytes.
1F40H
2nd graphics layer
(8000 bytes)
0000H
1st graphics layer
(8000 bytes)
3E7FH
1F3FH
Figure 82. Two-layer graphics
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9.0 Application Notes
• Register setup procedure
SYSTEM SET
TC/R calculation
9.1.4 –9.1.5
CSR FORM
C=
5DH
P1 =
07H
P2 =
87H
C=
40H
P1 =
30H
fOSC = 6 MHz
P2 =
87H
fFR = 70 Hz
P3 =
07H
P4 =
27H
P5 =
2FH
P6 =
C7H
P7 =
28H
OVLAY
P8 =
00H
C=
5BH
P1 =
0CH
HDOT SCR
(1/6) × 9 × [TC/R] × 200 = 1/70
[TC/R] = 48, so TC/R = 2FH
C=
5AH
P1 =
00H
SCROLL
C=
44H
DISP ON/OFF
P1 =
00H
C=
59H
P2 =
00H
P1 =
16H
P3 =
C8H
P4 =
40H
P5 =
1FH
P6 =
C8H
P7 =
XH
P8 =
XH
P9 =
XH
P10 =
XH
X = Don’t care
9.1.5 Display Mode Setting Example 3: Combining Three Graphics Layers
• Conditions
• 320 × 200 pixels, single-panel drive (1/
200 duty cycle)
• First layer: graphics display
• Second layer: graphics display
• Third layer: graphics display
• Display memory allocation
• All layers (graphics): 320/8 = 40 characters per line, 200/1 = 200 lines. Required
memory size = 40 × 200 = 8000 bytes.
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9.1.5
9.0 Application Notes
3E80H
3rd graphics layer
(8000 bytes)
1F40H
2nd graphics layer
(8000 bytes)
0000H
1st graphics layer
(8000 bytes)
5DBFH
3E7FH
1F3FH
Figure 83. Three-layer graphics
• Register setup procedure
SYSTEM SET
TC/R calculation
SCROLL
C=
44H
fOSC = 6 MHz
P1 =
00H
fFR = 70 Hz
P2 =
00H
P3 =
C8H
P4 =
40H
P5 =
1FH
C7H
P6 =
C8H
P7 =
28H
P7 =
80H
P8 =
00H
P8 =
3EH
P9 =
XH
P10 =
XH
C=
40H
P1 =
30H
P2 =
87H
P3 =
07H
P4 =
27H
P5 =
2FH
P6 =
(1/6) × 9 × [TC/R] × 200 = 1/70
[TC/R] = 48, so TC/R = 2FH
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9.0 Application Notes
9.1.5 – 9.2
CSR FORM
OVLAY
C=
5DH
C=
5BH
P1 =
07H
P1 =
1CH
P2 =
87H
DISP ON/OFF
HDOT SCR
C=
59H
C=
5AH
P1 =
16H
P1 =
00H
X = Don’t care
9.2 System Overview
Figure 84 shows the SED1330F/1335F/1336F in a
typical system. The microprocessor issues instructions to the 1330F/SED1335F/1336F, and the
SED1330F/1335F/1336F drives the LCD panel and
may have up to 64Kbytes of display memory.
Since all of the LCD control circuits are integrated
onto the SED1330F/1335F/1336F, few external components are required to construct a complete medium-resolution liquid crystal display.
SED1335F/1336F
Microprocessor
Character
generator
External character
generator memory
Display memory
address bus
Display memory
Display
address
control
Display memory
data bus
LCD unit
Driver
control
Main
memory
Data bus
Address bus
Control bus
Driver bus
TV
control*
X driver
Composite
signal
X driver
X driver
LCD panel
Y driver
TV
* SED1336F only
Figure 84. System block diagram
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9.3 – 9.3.1
9.0 Application Notes
9.3 System Interconnection
9.3.1 SED1330F/1335F
10MHz crystal
HC138
OSC1 OSC2
A0
A1
to
A7
A0
Decoder
CS
IORQ
Microprocessor
D0
to
D7
D0
to
D7
RD
WR
RES
SED1335F
A
B
C
Y7
Y6
to
Y0
CS7
CS6
to
CS0
VA12
A0 to A12 WE
A0 to A12 WE
A0 to A11
SRM2064 CS1
(RAM1) CS2
SRM2064 CS1
(RAM2) CS2
OE
2732
(CGROM)
D0 to D7
OE
D0 to D7
OE
D0 to D7
CE
VD0
to
VD7
XECL
XSCL
LP
WF
YDIS
YD
YSCL
RESET
RD
WR
RES
XD0
to
XD3
VA13
to
VA15
VCE
VR/W
VA0
to
VA12
LAT
DI
INH
FR
YSCL
SED1630F
V3
V4
VREG
SED1600F
FR
EI
E0
SED1600F
FR
EI
E0
SED1600F
FR
EI
E1
E0
LP
XSCL
ECL
DO
to
D3
V2
LP
XSCL
ECL
DO
to
D3
V1
LP
XSCL
ECL
DO
to
D3
POFF
Power
supply
converter
LCD
V5
LCD UNIT
Notes:
1. The recommended common drivers are the SED1743, SED1635.
2. The recommended segment drivers are the SED1742 and SED1606.
Figure 85. System interconnection diagram
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9.0 Application Notes
9.3.2
9.3.2 SED1336F
10MHz crystal
HC138
OSC1 OSC2
A0
A1
to
A7
A0
Decoder
CS
IORQ
Microprocessor
D0
to
D7
D0
to
D7
RD
WR
RES
SED1336F
RD
WR
RES
XD0
to
XD3
A
B
C
Y7
Y6
to
Y0
CS7
CS6
to
CS0
VA12
A0 to A12 WE
A0 to A12 WE
A0 to A11
SRM2064 CS1
(RAM1) CS2
SRM2064 CS1
(RAM2) CS2
OE
2732
(CGROM)
D0 to D7
OE
D0 to D7
OE
D0 to D7
CE
VD0
to
VD7
XSCL
LP
WF
YDIS
YD
RESET
VA13
to
VA15
VCE
VR/W
VA0
to
VA12
DI
INH
FR
YSCL
SED1600F
FR
EI
E1
E0
LP
XSCL
ECL
DO
to
D3
SED1600F
FR
EI
E0
DO
to
D3
V3
V4
VREG
SED1600F
FR
EI
E0
LP
XSCL
V2
LP
XSCL
V1
DO
to
D3
SED1630F
POFF
Power
supply
converter
LCD
V5
LCD UNIT
Notes:
1. The recommended common drivers are the SED1743, SED1635.
2. The recommended segment drivers are the SED1742 and SED1606.
Figure 86. System interconnection diagram
The SED1330F/1335F/1336F’s layered screens and
flexible scrolling facilities support a range of display
functions and reduces the load on the controlling
microprocessor when displaying underlining, inverse
display, text overlaid on graphics or simple animation.
• Character code table
• Contains character codes for text display
• Each character requires 8 bits
• Table mapping can be changed by using
the scroll start function
These facilities are supported by the SED1330F/
1335F/1336F’s ability to divide display memory into
up to four different areas.
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9.3.2 – 9.4
• Graphics data table
• Contains graphics bitmaps
• Word length is 8 bits
• Table mapping can be changed
• CG RAM table
• Character generator memory can be
modified by the external microprocessor
• Character sizes up to 8 × 16 pixels (16
bytes per character)
• Maximum of 64 characters
• Table mapping can be changed
• CG ROM table
• Used when the internal character generator is not adequate
• Can be used in conjunction with the internal character generator and external character generator RAM
• Character sizes up to 8 × 16-pixels (16
bytes per character)
• Maximum of 256 characters
• Fixed mapping at F000H to FFFFH
9.0 Application Notes
9.4 Smooth Horizontal Scrolling
Figure 87 illustrates smooth display scrolling to the
left. When scrolling left, the screen is effectively
moving to the right, over the larger virtual screen.
Instead of changing the display start address SAD
and shifting the display by eight pixels, smooth scrolling is achieved by repeatedly changing the pixel-shift
parameter of the HDOT SCR command. When the
display has been scrolled seven pixels, the HDOT
SCR pixel-shift parameter is reset to zero and SAD
incremented by one. Repeating this operation at a
suitable rate gives the appearance of smooth scrolling.
To scroll the display to the right, the reverse procedure is followed.
When the edge of the virtual screen is reached, the
microprocessor must take appropriate steps so that
the display is not corrupted. The scroll must be stopped
or the display modified.
Note that the HDOT SCR command cannot be used
to scroll individual layers.
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9.0 Application Notes
HDOT SCR
parameter
9.4
SAD
SAD + 1
P1 = 00H
SAD + 2
Magnified
AP
P1 = 01H
SAD = SAD
P1 = 02H
Display
C/R
P1 = 03H
Virtual screen
P1 = 07H
P1 = 00H
SAD = SAD + 1
Not visible
Visible
Note: The response time of LCD panels changes considerably at low temperatures. Smooth scrolling under these conditions may
make the display difficult to read.
Figure 87. HDOT SCR example
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9.5 – 9.5.2.1
9.0 Application Notes
9.5 Layered Display Attributes
SED1330F/1335F/1336F incorporates a number of
functions for enhanced displays using monochrome
LCD panels. It allows the display of inverse characters, half-intensity menu pads and flashing of selected
screen areas. These functions are controlled by the
OVLAY and DISP ON/OFF commands.
Attribute
MX1
MX0
0
1
1
0
0
1
1
0
0
0
1
0
0
0
1
1
1
Half-tone
Ruled line
Combined layer display
1st layer display
2ndt layer display
1
Reverse
Local flashing
A number of means can be used to achieve these
effects, depending on the display configuration. These
are listed below. Note, however, that not all of these
can be used in the one layer at the same time.
IV
EPSON
IV
EPSON
ME
Yes, No
ME
Yes, No
BL
Error
BL
RL
LINE
RL
LINE
Error
LINE
LINE
Figure 88. Layer synthesis
9.5.1 Inverse Display
9.5.2 Half-tone Display
The first layer is text, the second layer is graphics.
The FP parameter can be used to generate halfintensity display by flashing the display at 17 Hz. Note
that this mode of operation may cause flicker problems with certain LCD panels.
1. CSRW, CSDIR, MWRITE
Write 1s into the graphics screen at the area to
be inverted.
2. OVLAY: MX0 = 1, MX1 = 0
Set the combination of the two
Exclusive-OR.
layers to
3. DISP ON/OFF: FP0 = FP1 = 1, FP1 = FP3 =
0.
Turn on layers 1 and 2.
9.5.2.1 Menu Pad Display
Turn flashing off for the first layer, on at 17 Hz for the
second layer, and combine the screens using the OR
function.
1. OVLAY: P1 = 00H
2. DISP ON/OFF: P1 = 34H
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9.0 Application Notes
9.5.2.1 – 9.5.3.2
SAD1
SAD2
Half-tone
AB
AB
+
1st layer
2nd layer
Combined layer display
Figure 89. Half-tone character and graphics
9.5.2.2 Graph Display
9.5.3 Flashing Areas
To present two overlaid graphs on the screen, configure the display as for the menu bar display and put one
graph on each screen layer. The difference in contrast
between the half- and full-intensity displays will make
it easy to distinguish between the two graphs and help
create an attractive display.
9.5.3.1 Small Area
1. OVLAY: P1 = 00H
2. DISP ON/OFF: P1 = 34H
To flash selected characters, the MPU can alternately
write the characters as character codes and blank
characters at intervals of 0.5 to 1.0 seconds.
9.5.3.2 Large Area
Divide both layer 1 and layer 2 into two screen blocks
each, layer 2 being divided into the area to be flashed
and the remainder of the screen. Flash the layer 2
screen block at 2 Hz for the area to be flashed and
combine the layers using the OR function.
ABC
ABC
XYZ
XYZ
Figure 90. Localized flashing
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9.6 – 9.6.2
9.0 Application Notes
9.6 16 × 16-dot Graphic Display
9.6.1 Command Usage
9.6.2 Kanji Character Display
This example shows how to display 16 × 16-pixel
characters. The command sequence is as follows:
The program for writing large characters operates as
follows:
CSRW
Set the cursor address.
CSRDIR Set the cursor auto-increment direction.
MWRITE Write to the display memory.
1. The microprocessor reads the character data
from its ROM.
2. The microprocessor sets the display address
and writes to the VRAM. The flowchart is
shown in Figure 91.
A0 = 0
A0 = 1
O8 O7 O6 O5 O4 O3 O2 O1
O8 O7 O6 O5 O4 O3 O2 O1
0H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
(1)
(3)
(5)
(7)
(9)
(11)
(13)
(15)
(17)
(19)
(21)
(23)
(25)
(27)
(29)
(31)
(2)
(4)
(6)
(8)
(10)
(12)
(14)
(16)
(18)
(20)
(22)
(24)
(26)
(28)
(30)
(32)
1st column
2nd column
CG ROM output
(n) shows the CG ROM data
readout order
(Kanji ROM pattern)
Scan address A1 to A4
(6)
(4)
(2)
(19)
(17)
(15)
(13)
(11)
(9)
(7)
(5)
(3)
(1)
Data held in the microprocessor memory
2nd column
memory area
(4)
(2)
1st column
memory area
(3)
(1)
Data written into the SED1330 display memory
Figure 91. Graphics address indexing
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9.0 Application Notes
9.6 – 9.6.2
320 dots
Direction of cursor movement
(2)
(4)
(6)
(8)
(10)
(12)
(14)
(16)
(18)
(20)
(22)
(24)
(26)
(28)
(30)
(32)
(1)
(3)
(5)
(7)
(9)
(11)
(13)
(15)
(17)
(19)
(21)
(23)
(25)
(27)
(29)
(31)
240 dots
Figure 92. Graphics bit map
Start
Enable cursor downwards movement
Set column 1 cursor address
Using an external character generator ROM, and 8 ×
16-pixel font can be used, allowing a 16 × 16-pixel
character to be displayed in two segments. The external CG ROM EPROM data format is described in
Section 5.1. This will allow the display of up to 128, 16
× 16-pixel characters. If CG RAM is also used, 96 fixed
characters and 32 bank-switchable characters can
also be supported.
Write data
Set column 2 cursor address
Write data
End
Figure 93. 16 × 16-dot display flowchart
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10.0
Internal Character
Generator Font
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THIS PAGE INTENTIONALLY BLANK
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10.0
10.0 Internal Character Generator Font
10.0 Internal Character Generator Font
0
1
2
3
4
Character code bits 0 to 3
5
6
7
8
9 A
B
C
D
E
F
2
3
Character code bits 4 to 7
4
5
6
7
A
B
C
D
1
Figure 94. On-chip character set
Note: The shaded positions indicate characters that have the whole 6 × 8 bitmap blackened.
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THIS PAGE INTENTIONALLY BLANK
144 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
11.0
Glossary of Terms
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11.0
11.0 Glossary of Terms
11.0 Glossary of Terms
A
Address
AP
Address pitch parameter
C
Character display mode
CD
Cursor direction of movement parameter
CG
Character generator
CGRAM ADR Character generator memory address
CM
Cursor display shape parameter
C/R
Characters per row parameter
CRX
Horizontal cursor size parameter
CRY
Vertical cursor size parameter
CSR DIR
Cursor direction of movement instruction
CSR FORM
Cursor size, position and type instruction
CSRR
Read cursor address register instruction
CSRW
Write cursor address register instruction
DM
Display mode parameter
FC
Flashing cursor parameter
fFR
Frame frequency
fOSC
Oscillator frequency
FP
Screen flashing parameter
FX
Horizontal character size parameter
FY
Vertical character size parameter
G
Graphics display mode
GLC
Graphic line control unit
HDOT SCR
Horizontal scrolling by pixels instruction
IV
Screen origin compensation for inverse display
L/F
Lines per frame instruction
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11.0 Glossary of Terms
11.0
MREAD
Display memory read instruction
MWRITE
Display memory write instruction
MX
Screen composition mode
OV
Graphics layer select parameter
OVLAY
Screen layer mode instruction
P
Parameter
R
Row
RAM
Random access memory
ROM
Read only memory
SAD
Display scrolling start address parameter
SL
Display scrolling length parameter
TC/R
Length, including horizontal blanking, of one screen line
VRAM
Display memory
WF
Display drive waveform parameter
W/S
Windows per screen parameter
S-MOS assumes no responsibility or liability for (1) any errors or inaccuracies contained in the
information herein and (2) the use of the information or a portion thereof in any application,
including any claim for (a) copyright or patent infringement or (b) direct, indirect, special or
consequential damages. There are no warranties extended or granted by this document. The
information herein is subject to change without notice from S-MOS.
September 1995
© Copyright 1995 S-MOS Systems, Inc.
Printed in U.S.A.
268-0.4
148 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4