WMC: Challenges in Model-Based HPA Design Application of Non-Linear Models in a range of challenging GaN HEMT Power Amplifier Designs Ray Pengelly, Brad Millon, Don Farrell, Bill Pribble and Simon Wood Cree Inc., Research Triangle Park, NC 27709 Outline • Attributes of GaN HEMTs • Cree GaN HEMT Models • Design Examples – Broadband CW Amplifiers – Linear WiMAX Amplifier • Future Model Improvements • Conclusions Attributes of GaN HEMTs • High Voltage Operation • High power densities – 4 to 8 watts/mm at 28 and 50 volt operation respectively • High Frequency Performance – present Cree process has fT of 25 GHz p a g d n • High Efficiency a B e • Low Quiescent Current Wid • High Native Linearity • Low capacitance per peak watt (12% of LDMOS and 21% of GaAs MESFET) – supports broad bandwidths • Enable new amplifier architectures • Highly correctable under DPD • Almost constant CDS as a function of VDS – great for Drain Modulation Models for GaN HEMTs • Equivalent-circuit based approach – Relatively simple extraction – Process sensitive based on individual elements – Simple implementation using commercial harmonic balance simulators • Significant historical information for model basis and validation • Non-linearity introduced as required by element – Drain current source is dominant non-linearity – Gate current formulation includes breakdown and forward conduction – Voltage variations of parasitic capacitances derived from charge formulations • Model data fit extends over drive, frequency, bias, and temperature • Many hundreds of successful hybrid and MMIC designs Model Schematic pncap3 X15 sc=sc scf=scf cg1=cgd pF cg2=0.6 cg3=0.1 vgg0=-21 V R R3 R=0.01 Ohm SDD6P SDD6P1 I[1,0]=(vg)/5e8 I[2,0]=id1 I[3,0]=(_v3)*gdsc I[4,0]=(_v4)*gmc I[5,0]=-vd*idt I[6,0]=(vdf)/5e4 C[1]= Cport[1]= vg1 SRL SRL1 R=(rg/sc+rg1/(sc*scf)) Ohm L=(lg/sc+lg1/(scf*sc)) nH Port P1 Num=1 R R5 R=1e6 Ohm pncap3 X12 sc=sc scf=scf cg1=cgs pF cg2=cg2 cg3=cg3 vgg0=vgg0 V R R1 R=(ri/(sc*scf)) Ohm Drain current SRL SRL4 R=(rd/(sc*scf)) Ohm L=(ld/sc+ld1/(sc*scf)) nH C C7 C=1.0 uF Port P2 Num=2 C C9 C=(cds*sc*scf) pF VCVS SRC1 G=1 Port P4 Num=4 Port P5 Num=5 SRL SRL3 R=(rs/(sc*scf)) Ohm L=(ls/sc) nH R R6 R=1e6 Ohm Thermal resistance vd1g R R2 R=rth Ohm C C8 C=30.0 nF Port P8 Num=8 • Based on 13-element MESFET model (H. Kondoh – 1986 MTT-S) • ADS version shown using non-linear equation-based elements – Easily changed during design process – Speed comparable to C-coded version • AWR version uses C code with “model wizard” More details on GaN HEMT Model • Most FET models implement a gate current-control characteristic that transitions from the sub-threshold Quad Linear Compression region to the linear gate control Sub region directly, without treating the Threshold intermediate region, called the Ids, mA gm and Ids Gm, mS 500 quadratic region. Fager et al. implemented an equation and new parameters to fit the quadratic region. This leads to better 250 agreement with measured IMD and other nonlinear characteristics. • Gate charge is partitioned into gate- 0 -4 -3 -2 -1 0 0.5 Gate voltage, volts source and gate-drain charge. Each charge expression is a function of Blue is DC transconductance both VDS and VGS. Using charge Red is drain current partitioning, it is possible to fit most GaN HEMT capacitance functions and observed charge conservation. 30 4000 25 3333 20 2667 15 2000 10 1333 |S(2,1)|[1,X] (L) Schematic 1 5 666.7 IDC(I_METER.AMP1) (R, mA) Schematic 1 p1: Freq = 0.05 GHz p1 0 -15 -10 -5 Voltage (V) 0 5 8 0 More details on GaN HEMT Model • • • The model includes new capacitance functions as well as modeling of the drain-source breakdown and self heating. The model has four ports, with the extra port providing a measure of the temperature rise. The voltage between the external thermal circuit port and the source node is numerically equal to the junction temperature rise in degrees C. This occurs because the current source in the thermal circuit is numerically equal to the instantaneous power dissipated in the FET and the resistance, R_TH is numerically equal to the thermal resistance. The RC product of the thermal circuit is the thermal time constant. The model addresses the sharp turn-on knee in GaN HEMTs leading to the accurate prediction of IMD sweet spots in Class A/B operation. Drain Current Model 0.15 0.5 gm permute(Is_high.i) 0.10 0.05 0.00 -4 -3 -2 -1 Vlow 0 1 2 0.4 0.3 0.2 0.1 0.0 0 5 10 15 20 25 30 35 40 Vhigh • • • • • Transconductance curve fit to Gm from small-signal model fits over bias range Output conductance dispersion model Peak current and knee voltage fit from load-pull - includes trap effects Pinch-off fit from DC IV-characteristics – gives model of drain current IV function similar to Fager-Statz formulation – good model of pinch-off needed to accurately predict intermodulation distortion 45 Temperature Dependence – Self-heating output power 36.5 36 35.5 35 34.5 34 0 1mm gate width 50 100 150 200 chuck temp • Drain current is only temperature dependent model element • Drain current scales to provide -0.1 dB/10oC reduction in power for current-limited load-line • Self-heating included using a thermal resistance – calculated from finite element analysis of die and package. • Thermal performance due to package needs to be included where appropriate Feedback Capacitance Cgd (pF) Feedback Capacitance - CGD 0.4 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 0 10 20 30 40 50 60 Drain Voltage • Feedback capacitance is a strong function of drain voltage • Inclusion of this effect necessary to fit small-signal data • Non-linearity changes harmonic generation from the model – effects efficiency and linearity predictions • Output Capacitance CDS is linear – no voltage dependence (weak anyway) Input Capacitance Cgs (pF) Input Capacitance - CGS 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 0 Gate Voltage (V) • Input capacitance is a strong function of gate voltage • CGS is also a function of drain voltage, but this non-linearity is not included at present • The gate-voltage non-linearity also effects model’s harmonic generation GaN HEMT Model - Small-Signal measured 30 model 20 a(2,2) b(2,2) b(1,1) a(1,1) bg ag Measured Gmax Model Gmax 25 15 10 1E9 1E10 2E10 freq, Hz freq (1.000GHz to 14.00GHz) • • • • On-wafer S-parameters of 0.5 mm HEMT – 25OC baseplate Major challenge of modeling for high power circuits – scaling from reasonable test cell to large periphery output stages – successfully implemented for scaling factors >100:1 Non-linear model fits small-signal parameters over a range of bias voltages All measurements performed using 1% duty cycle, 20µs pulsed bias to control thermal effects GaN HEMT Model - Large-Signal Power Contour Levels: 36 dBm 35 dBm 34 dBm measured model • • • On-wafer load-pull of 0.5 mm HEMT Measured at 3.5 GHz, VDS=48V, Id~25%IDSS, 25OC chuck temperature PAE contours not used for modeling due to sensitivity to harmonic loading – PAE verified using hybrid amplifier measurements Basic Thermal Features of High Voltage GaN • 240 Watts CW RF from a 28.8mm HEMT operating at 50 volts drain voltage • Assume 60% DC to RF conversion efficiency • 160 watts dissipated heat • Active chip area is 2.5 sq. mm so heat density is > 40 kilowatts per square inch ! • Much emphasis on new amplifier architectures to improve drain efficiencies Broadband Amplifier Performance Trade-Off Analysis - Background • Broadband (0.8 to 2.2 GHz) push-pull amplifier to provide 100 watts peak power • Two GaN HEMT die in “Gemini” package – HEMTs attached to composite material shims within Cu-Mo-Cu package • Study drain efficiencies over the band and impact on thermal management – Comparison of different matching approaches and termination impedances Theta-jc is 1.1 deg C/watt Basic Amplifier • • Different matching topologies – Drain-to-Gate Feedback – Lossy Match – Multi-section reactive – Lossy Match with Feedback PORT P=1 Z=50 Ohm TLIN ID=TL6 Z0=43.09 Ohm EL=195.3 Deg F0=1.5 GHz TLIN ID=TL7 Z0=28.29 Ohm EL=57.64 Deg F0=1.5 GHz TLIN ID=TL8 Z0=9.149 Ohm EL=42.65 Deg F0=1.5 GHz PORT P=3 Z=50 Ohm 3 DC RF 2 CAP ID=C7 C=1.243 pF DC & RF BIASTEE CAP ID=X1 ID=C1 C=2.271 pF CAP ID=C8 C=2.414 pF 1 PORT P=2 Z=50 Ohm Concentrate on Lossy Match case Input Match Schematic DCVS ID=V1 V=28 V SWPVAR ID=SWP4 VarName="Power" Values=stepped(10,40,.1) UnitType=None Xo . . . Xn I_METER ID=AMP1 ATTEN ID=U1 R=50 Ohm LOSS=3 dB 2 TLIN ID=TL3 Z0=10.16 Ohm EL=70.63 Deg F0=1.5 GHz TLIN ID=TL4 CAP Z0=18.75 Ohm ID=C4 C=1.006 pFEL=86.31 Deg F0=1.5 GHz TLIN ID=TL5 CAP Z0=35.25 Ohm ID=C5 C=0.6011 pF EL=93.57 Deg F0=1.5 GHz RF 2 PORT P=2 Z=50 Ohm BIASTEE ID=X1 SUBCKT ID=S1 NET="IMN Lossy Match" 1 3 DC DC & 1 RF Power=10 PORT1 P=1 Z=50 Ohm Pwr=Power dBm PORT P=3 Z=50 Ohm PORT P=1 Z=50 Ohm 3 1 2 1 3 SUBCKT ID=S3 NET="GaN HEMT Die Model G3" 2 PORT P=2 Z=50 Ohm SUBCKT ID=S2 NET="OMN Lossy Match" DCVS ID=V2 V=2.2 V Output Match Schematic Overall Schematic Simulated Amplifier Performance Output Power at P3dB and Drain Efficiency Efficiency Small Signal Gain Gain = 13.2 dB ± 0.8 dB POUT = 46 to 59 watts Drain Efficiency = 49 to 66% Worst Case Dissipated Heat is 54 watts (per transistor) POUT Thermal Performance • 3.75 W/mm dissipated 54 watts per transistor Assuming TJ limit of 200OC, maximum dissipated heat of 108 watts and theta-jc of 1.1 deg C/Watt leads to a maximum case temperature of 81 deg C The thermal characteristics of the die and the package are very important – The design requires a composite material shim such as silver-diamond (theta jc =550 W/mK) mounted on a Super-CMC package flange (theta jc = 370 W/mK) Pdiss 4 3.5 3 2.5 Pdiss (W/mm) • Pdiss Lossy Match 2 1.5 1 0.5 • Before full electrical design is completed broadband amplifiers require thermal design even with GaN HEMTs! 0 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 Frequency (GHz) Dissipated Power as a function of frequency Comparison of Dissipated Power vs. Frequency for 4 Amplifier Approaches Lossy match with feedback Pdiss 4.5 Multi-section reactive 4 3.5 Pdiss Multisection Pdiss(W/mm) 3 Pdiss Lossy Match 2.5 Pdiss LM w Feedback 2 Pdiss MS w Feedback 1.5 1 Feedback Lossy Match 0.5 0 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 Frequency (GHz) • Large-Signal Modeling of Broadband Amplifiers invaluable in selecting optimum topology for both electrical and thermal performance Measured 0.5 to 2.5 GHz Push-Pull Amplifier Performance 25 to 50 ohm coupler Drain Efficiency at Device Sat 70.00 60.00 Drain Efficiency (%) 50.00 Power out at Device Sat (W) 120.00 40.00 30.00 20.00 100.00 10.00 80.00 Psat (W) 0.00 0.000 0.500 1.000 1.500 2.000 Frequency (GHz) 60.00 40.00 20.00 0.00 0.000 0.500 1.000 1.500 Frequency (GHz) 2.000 2.500 3.000 Full amplifier with coupler insertion losses Average Gain = 15 dB Psat > 80 watts and Drain Efficiencies > 45% 2.500 3.000 500 to 2700 MHz Amplifier using Cree CGH40010F DCVS ID=V2 V=28 V I_METER ID=AMP1 DCVS ID=V1 V=2.05 V Lossy Match IND ID=L2 L=200 nH IND ID=L1 L=200 nH PORT_PS1 P=1 Z=50 Ohm PStart=-8 dBm PStop=32 dBm PStep=5 dB CAP ID=C5 C=8.513 pF TLIN ID=TL3 Z0=53.79 Ohm EL=26.09 Deg F0=3 GHz TLIN ID=TL2 Z0=12.22 Ohm EL=21.88 Deg F0=3 GHz TLIN ID=TL1 Z0=70.11 Ohm EL=32.91 Deg F0=3 GHz RES ID=R1 R=51 Ohm RES ID=R2 R=0 Ohm 2 CAP ID=C3 C=0.9191 pF 1 PIPAD ID=P1 Z1=50 Ohm Z2=50 Ohm DB=2 dB CAP ID=C4 C=1.096 pF CAP ID=C2 C=1.187 pF CAP ID=C1 C=15.55 pF 3 CGH40010F_r2 ID=40010F1 TNOM=105 PORT P=2 Z=50 Ohm Simulated Performance of 500 to 2700 MHz GaN HEMT PA Small Signal S21 S11 and S22 30 POUT and Efficiency Vs Input Power 80 DCRF(PORT _ 2 )[ *, X] Re a l Ci rc u i t DB(PT (PORT _2 ))[ *,X] (d Bm ) 5 0 0 to 2 70 0 M Hz Sta g e 20 DCRF(PORT _ 2 )[ *, X] 5 0 0 to 2 70 0 M Hz Sta g e DB(PT (PORT _2 ))[ *,X] Re a l Ci rc u i t p2 60 0 p3 p1 -10 DB(|S(1,1)|)[X,2] 500 to 2700 MHz Stage DB(|S(2,1)|)[X,2] 500 to 2700 MHz Stage -20 DB(|S(2,2)|)[X,2] 500 to 2700 MHz Stage dBm and % dB 10 40 20 p1: Pwr = -3 dBm p2: Pwr = -3 dBm p3: Pwr = -3 dBm -30 0.5 1 1.5 Frequency (GHz) 2 2.5 2.7 0 -8 2 12 Input Power (dBm) • Worst Case Heat Dissipation is 9 watts • Theta-jc of packaged transistor is 5 deg C/watt • Max. channel temperature at 85 deg C case is 130 deg C. 22 32 Measured Performance of 500 to 2700 MHz GaN HEMT PA • Excellent agreement between simulations and measurements • Measured efficiencies between 50 and 78% over the band Output Power Output Power vs. Frequency 44 0.25 GHz 40 0.50 GHz 0.75 GHz 38 1.00 GHz P OUT (dBm) 36 Simulated andVs measured Simulated Actual 20 42 1.25 GHz 34 1.50 GHz 32 1.75 GHz 30 2.00 GHz 28 2.25 GHz 26 2.50 GHz 24 2.70 GHz 22 3.00 GHz 20 10 15 14 16 18 20 22 24 26 28 30 32 34 PIN (dBm) 10 Saturated Output Power and Drain Efficiency Saturated Output Power and Efficiency 5 0 -5 p1 p4 p3 p6 -10 0.5 1 1.5 Frequency (GHz) 2 2.5 2.7 p1: Pwr = -3 dBm p2: Pwr = -3 dBm p3: Pwr = -3 dBm p4: Pwr = -3 dBm p5: Pwr = -3 dBm p6: Pwr = -3 dBm P OUT (dBm) / Efficiency (%) dB 12 p5 p2 82 80 78 76 74 72 70 68 66 64 62 60 58 56 54 52 50 48 46 44 42 40 38 36 Efficiency Power 0 0.25 0.5 0.75 1 1.25 1.5 1.75 Frequency (GHz) 2 2.25 2.5 2.75 3 3.25 PSAT EFFICIENCY @PSAT Linear WiMAX Amplifier Simulation versus Measured Data • 60 Watt, 2.3 to 2.8 GHz linear amplifier design • Developed an accurate packaged transistor model using the Cree GaN HEMT scale-able die model • Circuit developed to address Fixed and Mobile Access WiMAX applications such as – 802.16-2004 – 802.16e – WiBro • The design targets were as follows: – Average Output Power > 8W – EVM < 2.5% – Drain Efficiency > 25% (under WiMAX stimulus) CGH27060F Packaged Device Model CG H40045F_r1 ID=CGH27060 ID=CG H27030 TNOM=25 TNOM=25 2 1 CAP ID=C5 C=0.03 pF 3 MLIN ID=TL1 W=250 mil L=60mil GaNg28v2_r3 ID=GaNv2sc1 TNOM=25 SC=20 SCF=1.44 RTH=2.7 VDD=50 SRL ID=RLD1 R=0.007Ohm L=0.285 nH SRL ID=RLD2 R=0.007 Ohm L=Lbond nH 2 V_METER ID=VM1 1 PORT P=5 Z=50 Ohm CAP ID=C2 C=0.06pF MSUB Er=9.6 H=20 mil T=1.4 mil Rho=1 Tand=0 ErNom=9.6 Name=Alum_pkg1 CAP ID=C3 C=0.06 pF CAP I D=CDpad1 C=0. 48 pF MLIN ID=TL2 W=250 mil L=60 mil CAP ID=C1 C=0.06pF CAP ID=CDpad2 C=0.48 pF 3 SRL ID=RL1 R=0.001Ohm L=0.015nH CAP ID=C4 C=0.06pF PORT P=6 Z=50Ohm Input Circuit Model ML IN ID=T L1 W =3 5 m il L=2 3 m il SU BCK T ID=S 3 NE T="Re sis to r_ 10 0 _ Oh m Ce nt e r1" M LI N I D=TL2 W =3 5 mil L =2 3 mil MD L X 1 P O RT P =1 Z =50 Oh m MLIN ID=TL 5 W =4 4 mil L=2 5 m il ML IN ID=T L3 W=1 0 m il L=4 0 m il M ST EP $ I D=TL 8 2 1 1 S UB CK T ID=S 2 NE T=" In du c tive Lin e _ 2p 5 _ Ne w1 " 3 3 2 2 MS UB E r=3 .6 6 H =20 mil T =1. 4 mil R ho =1 T an d =0 .0 0 4 E rNo m=3 .6 6 N am e=R og e rs 1 1 MD L X SU BC KT ID=S 1 NE T="In d u ct ive L in e_ 2p 5_ Ne w1" ML IN ID=TL 4 W =1 0 mil L =4 0 mil P OR T P =2 Z=5 0 O h m SU BC KT ID =S 2 N ET ="Gate B ias F eed w ith T rans Line_02 _06_06" 2 MO Dca tc 06 0 3 0 01 ID=A TC _60 0 S_ C1 C=2.2 p F MS UB = Sim _m od e =0 To lera n ce =1 PA DW =3 5 mil MLE F ID= Open W = 30 m il L=9 3 m il M OD catc 06 03001 ID =AT C_6 00S _C 1 C =0.85 pF M SU B= Sim _m ode= 0 Tol era nc e=1 PAD W =35 m il SU BCK T ID= S4 NE T="Input La unc h_AS T UN ED " 1 3 1 2 1 2 3 1 2 1 MD LX 2 1 PO R T P= 1 Z =5 0 O hm PO R T P= 1 Z=5 0 O hm M LIN I D=T L1 3 W =7 0 mil L =200 m il MSTE P$ ID =TL14 MLIN ID =TL12 W =20 mi l L= 130 m il M LIN I D=T L11 W =7 0 mil L =200 mi l MSTE P$ ID =TL10 M STEP $ I D=T L9 M STEP $ I D= TL1 5 MSU B Er= 3.66 H= 20 m il T= 1.4 mil Rh o=1 Ta nd= 0.004 ErN om =3.66 Na me= Roge rs 1 SU BC KT ID =S1 NE T= "S ta bil ity C irc uit_N ew" M LIN ID =T L2 W =1 0 mil L =120 mi l MLI N ID =TL1 W =44 mi l L= 25 m il M STE P$ ID =TL8 MLIN ID =T L4 W =44 mil L= 565 m il P O RT P =2 Z= 50 O hm M SU B Er =3.66 H =20 m il T =1.4 m il R ho=1 T a nd=0.004 Er N om =3.48 N am e=R oge rs 1 4 2 POR T P=2 Z= 50 Ohm S UB CKT ID = S5 N ET ="Input T ank J unctio n_EM 1 " S UB CK T I D= S3 N ET ="G ate Pad 3 Por t" M LIN ID =TL_S H W =20 m il L=2 30 m il 2 1 3 SU BC KT ID =S8 N ET= "Input_S hunt_GN D _03_21_ 071" 1 Output Circuit Model 3 1 4 2 ML I N ID = Db i as L 2 W=Wba i s mi l L= L b i as m li M B END 90 X I D= M S 4 W = W o u t mi l M =0 . 5 S UB C K T I D= S 5 NET = "D rai n B i as T e rm n i a to i n" M B E ND 90 X I D= M S 3 W = W o u t mi l M = 0. 5 1 M B E N D9 0 X ID = MS 1 W =Wba i s mi l M = 0 .5 M L EF I D= O S t u b1 W = 1 1 0 mi l L =3 0 m il ML I N ID = Db i as L 1 W=Wba i s mi l L= 2 4 0 m i l P O RT P=1 Z = 5 0 O hm L st u b _ A = 50 W o u t = 34 L o ut = 6 1 L st u b _ M= 7 0 Wd ln i e = 1 00 W b i as = 4 0 Lb a i s = 25 5 ML E F ID = OS t u b 2 W = 11 0 m li L= 3 0 mi l M L IN I D = T L3 W = W o ut m i l L = L o ut m i l S UB C K T I D= S 3 NE T = "D rai n B l o ck Ca p P a d_ 2 p 5 " 3 M DL X 1 S U BCK T I D =S 2 N E T = "Dra i n P ad 4 P o rt _2 p 5 " 2 4 1 M L IN I D =T L 1 6 W =1 6 0 mi l L =2 6 5 m il MS TE P $ I D= T L 19 M LI N I D= T L 2 0 W =1 1 0 m il L =2 m il ML I N I D= Db i a sL W = W b i as m li L =2 4 0 mi l M B E N D9 0 X ID = MS 6 W =Wba i s mi l M = 0 .5 2 1 2 M OD ca t c 10 0 B0 0 1 I D= A T C _1 0 0 B_ C1 C= 8 . 2 pF M S UB = Si m _m o d e= 0 T o l era n c e= 1 PA D W = 1 10 m li ML I N I D= T L 2 W = W o u t mi l L =5 0 m li 1 SU B CK T I D= S 1 NE T= " Dra n i Bi a s T e rm i na ti o n" M B E ND 90 X I D= M S 2 W = W o u t mi l M = 0. 5 M L EF I D =O S t u b 4 M L IN I D= T L 7 W = W o u t m li L = L ou t m li M L EF I D= O S t u b6 W = 7 2 mi l L =2 6 m il W =4 0 m li L =1 7 4 m il 1 M CR OS S$ I D =T L 9 M LI N I D= T L 6 W = 3 4 mi l L = 60 m li 2 R ho = 1 T a n d =0 . 0 0 4 E rN o m= 3 . 4 8 N am e = Ro g ers 4 3 50 M STEP$ I D= T L 1 3 M LI N I D= T L 1 W = 4 4 mi l L = 1 44 m li 2 3 1 S U B CKT I D= S 7 NE T= " 3p o rt _ co rn e r" 1 ML I N ID = T L1 5 W = 70 m i l L= 2 0 0 m i l M LI N I D= T L 1 0 W = 2 0 mi l L = 1 30 m li M STEP$ I D =T L 4 ML I N ID = T L1 1 W = 70 m i l L= 2 0 0 m i l 3 3 2 1 M LI N I D= T L 8 W = W o u t mi l L = 45 m i l M L IN I D = TL 1 7 W = 48 m li L = 1 2 mi l 4 M L EF I D =O S t u b 3 W =4 0 m li L =1 7 4 m il M SUB E r= 3 . 6 6 H =2 0 m li T =1 .4 m i l M LI N ID= Db i a sL 3 W = W b i a s m il L = Lb i a s m i l M LI N I D= T L 5 W = W o u t mi l L = 44 m li S U B CK T I D= S 6 NE T =" Ha rmo n i c A s s s i t _ A S T UN ED" M CR OS S $ 4 I D =T L 1 8 M L EF I D= O S t u b5 W = 7 2 mi l L=2 6 m il M STEP$ I D =T L 1 2 M STEP$ I D= T L 1 4 P ORT P =2 Z = 5 0 Oh m Fully Modeled Layout of Amplifier 1 J 9 8 7 6 5 4 3 2 1 L C 3 J 2 J Actual Printed Circuit Board Simulated and Measured Amplifier 5 14 3 13 1 12 -1 11 -3 10 -5 DB(|S(1,1)|) (R) Amp_SS_AsTuned 9 DB(|S(2,1)|) (L) Amp_SS_AsTuned 8 DB(|S(2,1)|) (L) fixt20_G28V2144L1w3__5 7 DB(|S(1,1)|) (R) fixt20_G28V2144L1w3__5 6 DB(|S(2,2)|) (R) Amp_SS_AsTuned 5 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 Frequency (GHz) 3 3.1 3.2 -7 -9 -11 -13 -15 Return Loss (dB) Small Signal Gain (dB) Small Signal Frequency Response 15 Simulated Linearity of Amplifier 2-Tone IMD vs Average Ouput Power 60 IM3L_Pave (L) IM3U_Pave (L) -10 50 IM5L_Pave (L) IM5U_Pave (L) -20 40 DE_Pave (R) -30 30 -40 20 -50 10 -60 0 26 28 30 32 34 36 38 40 42 2 Tone Average Output Power (dBm) 44 46 Drain Efficiency (%) 3rd & 5th Order IMD (dBc) 0 Measured Linearity of Amplifier EVM and Efficiency vs. Average Output Power EVM (%) 3.50 40.0% EVM 2.5GHz DE 2.5GHz 35.0% 3.00 30.0% 2.50 25.0% 2.00 20.0% 1.50 15.0% 1.00 10.0% 0.50 5.0% 0.00 22.0 24.0 26.0 28.0 30.0 32.0 34.0 36.0 Average Output Power (dBm) 38.0 40.0 0.0% 42.0 Drain Efficiency (%) 4.00 Measured Linearity of Amplifier EVM and Efficiency vs Frequency 4.00 40.0% EVM @ 26dBm 3.50 35.0% EVM @ 39dBm 3.00 30.0% 2.50 25.0% 2.00 20.0% 1.50 15.0% 1.00 10.0% 0.50 5.0% 0.00 2.300 2.400 2.500 Frequency (GHz) 2.600 0.0% 2.700 Drain Efficiency (%) EVM (%) Efficiency @ 2.5% EVM Future GaN HEMT Model Improvements • Behavioral models to allow direct simulation of various digital waveforms • Improved active and passive switch models • Improved models for switch mode PA’s • Additional noise models • Support for simulators other than ADS and MWO Conclusions • Successful development of GaN HEMT large-signal models • Models are scale-able over > 100:1 gate width ratio • Models – Are broadband – Accurately predict DC, s-parameters, dynamic load lines, non-linearities – Include self-heating – Can be used in a range of amplifier types • Demonstrated a variety of hybrid circuit applications • Equally useful for MMIC amplifier designs • Future extensions to include other features such as noise