Renesas LSIs M5M5V5A36GP-75,85 Preliminary Notice: This is not final specification. Some parametric limits are subject to change. 18874368-BIT(524288-WORD BY 36-BIT) Flow-Through NETWORK SRAM FEATURES FUNCTION • Flow-Through Read mode, Single Late Write mode • Fast access time: 7.5 ns and 8.5 ns • Single 3.3V -5% and +5% power supply VDD • Separate VDDQ for 3.3V or 2.5V I/O • Individual byte write (BWa# - BWd#) controls may be tied LOW • Single Read/Write control pin (W#) • CKE# pin to enable clock and suspend operations • Internally self-timed, registers outputs eliminate the need to control G# • Snooze mode (ZZ) for power down • Three chip enables for simple depth expansion Synchronous circuitry allows for precise cycle control triggered by a positive edge clock transition. Synchronous signals include : all Addresses, all Data Inputs, all Chip Enables (E1#, E2, E3#), Address Advance/Load (ADV), Clock Enable (CKE#), Byte Write Enables (BWa#, BWb#, BWc#, BWd#) and Read/Write (W#). Write operations are controlled by the four Byte Write Enables (BWa# - BWd#) and Read/Write(W#) inputs. All writes are conducted with on-chip synchronous self-timed write circuitry. Asynchronous inputs include Output Enable (G#), Clock (CLK) and Snooze Enable (ZZ). The HIGH input of ZZ pin puts the SRAM in the power-down state. All read, write and deselect cycles are initiated by the ADV LOW input. Subsequent burst address can be internally generated as controlled by the ADV HIGH input. Package 100pin TQFP APPLICATION High-end networking products that require high bandwidth, such as switches and routers. PART NAME TABLE Access Cycle Active Current (max.) Standby Current (max.) M5M5V5A36GP-75 7.5ns 8.5ns 280mA 30mA M5M5V5A36GP-85 8.5ns 10ns 260mA 30mA Part Name 1/19 Preliminary M5M5V5A36GP-75,85 REV.1.0 Renesas LSIs M5M5V5A36GP-75,85 18874368-BIT(524288-WORD BY 36-BIT) Flow-Through NETWORK SRAM PIN CONFIGURATION(TOP VIEW) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQPb DQb DQb VDDQ VSSQ DQb DQb DQb DQb VSSQ VDDQ DQb DQb VSS MCL VDD ZZ DQa DQa VDDQ VSSQ DQa DQa DQa DQa VSSQ VDDQ DQa DQa DQPa 100pin TQFP M5M5V5A36GP 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 A10 A11 A12 A13 A14 A15 A16 NC NC VDD VSS NC NC A0 A1 A2 A3 A4 A5 LBO# DQPc DQc DQc VDDQ VSSQ DQc DQc DQc DQc VSSQ VDDQ DQc DQc MCL VDD MCH VSS DQd DQd VDDQ VSSQ DQd DQd DQd DQd VSSQ VDDQ DQd DQd DQPd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 A9 81 A8 82 A17 83 A18 84 ADV 85 G# 86 CKE# 87 W# 88 CLK 89 VSS 90 VDD 91 E3# 92 BWa# 93 BWb# 94 BWc# 95 BWd# 96 E2 97 E1# 98 A7 99 A6 100 Note1. MCH means "Must Connect High". MCH should be connected to HIGH. Note2. MCL means "Must Connect Low". MCL should be connected to LOW. 2/19 Preliminary M5M5V5A36GP-75,85 REV.1.0 Renesas LSIs M5M5V5A36GP-75,85 18874368-BIT(524288-WORD BY 36-BIT) Flow-Through NETWORK SRAM BLOCK DIAGRAM VDD A0 A1 A2~18 19 19 17 ADDRESS REGISTER A1' A1 D1 LINEAR/ Q1 D0 INTERLEAVED BURST COUNTER Q0 A0 CLK CKE# VDDQ A0' 19 WRITE ADDRESS REGISTER 19 ZZ ADV AND DATA COHERENCY CONTROL LOGIC BYTE2 WRITE DRIVERS BYTE3 WRITE DRIVERS 256Kx36 MEMORY ARRAY BYTE4 WRITE DRIVERS W# OUTPUT BUFFERS WRITE REGISTRY OUTPUT SELECT BWa# BWb# BWc# BWd# BYTE1 WRITE DRIVERS DQa DQPa DQb DQPb DQc DQPc DQd DQPd INPUT 36 G# REGISTER READ LOGIC E1# E2 E3# VSS Note3. The BLOCK DIAGRAM illustrates simplified device operation. See TRUTH TABLE, PIN FUNCTION and timing diagrams for detailed information. 3/19 Preliminary M5M5V5A36GP-75,85 REV.1.0 Renesas LSIs M5M5V5A36GP-75,85 18874368-BIT(524288-WORD BY 36-BIT) Flow-Through NETWORK SRAM PIN FUNCTION Pin Function Name A0~A18 Synchronous Address Inputs These inputs are registered and must meet the setup and hold times around the rising edge of CLK. A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. BWa#, BWb#, BWc#, BWd# Synchronous Byte Write Enables These active LOW inputs allow individual bytes to be written when a WRITE cycle is active and must meet the setup and hold times around the rising edge of CLK. BYTE WRITEs need to be asserted on the same cycle as the address. BWs are associated with addresses and apply to subsequent data. BWa# controls DQa, DQPa pins; BWb# controls DQb, DQPb pins; BWc# controls DQc, DQPc pins; BWd# controls DQd, DQPd pins. CLK Clock Input This signal registers the address, data, chip enables, byte write enables and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock's rising edge. E1# Synchronous Chip Enable This active LOW input is used to enable the device and is sampled only when a new external address is loaded (ADV is LOW). E2 Synchronous Chip Enable This active High input is used to enable the device and is sampled only when a new external address is loaded (ADV is LOW). This input can be used for memory depth expansion. E3# Synchronous Chip Enable This active Low input is used to enable the device and is sampled only when a new external address is loaded (ADV is LOW). This input can be used for memory depth expansion. G# Output Enable This active LOW asynchronous input enable the data I/O output drivers. ADV Synchronous Address Advance/Load CKE# Synchronous Clock Enable LBO# Burst Mode Control When HIGH, this input is used to advance the internal burst counter, controlling burst access after the external address is loaded. When HIGH, W# is ignored. A LOW on this pin permits a new address to be loaded at CLK rising edge. This active LOW input permits CLK to propagate throughout the device. When HIGH, the device ignores the CLK input and effectively internally extends the previous CLK cycle. This input must meet setup and hold times around the rising edge of CLK. This DC operated pin allows the choice of either an interleaved burst or a linear burst. If this pin is HIGH or NC, an interleaved burst occurs. When this pin is LOW, a linear burst occurs, and input leak current to this pin. This active HIGH asynchronous input causes the device to enter a low-power standby mode in which all data in the memory array is retained. When active, all other inputs are ignored. When this pin is LOW or NC, the SRAM normally operates. ZZ Snooze Enable W# Synchronous Read/Write This active input determines the cycle type when ADV is LOW. This is the only means for determining READs and WRITEs. READ cycles may not be converted into WRITEs (and vice versa) other than by loading a new address. A LOW on the pin permits BYTE WRITE operations and must meet the setup and hold times around the rising edge of CLK. Full bus width WRITEs occur if all byte write enables are LOW. DQa,DQPa,DQb,DQPb DQc,DQPc,DQd,DQPd Synchronous Data I/O Byte “a” is DQa , DQPa pins; Byte “b” is DQb, DQPb pins; Byte “c” is DQc, DQPc pins; Byte “d” is DQd,DQPd pins. Input data must meet setup and hold times around CLK rising edge. VDD VDD Core Power Supply VSS VSS Core Ground VDDQ VDDQ I/O buffer Power supply VSSQ VSSQ I/O buffer Ground MCH Must Connect High These pins should be connected to HIGH MCL Must Connect Low These pins should be connected to LOW No Connect These pins are not internally connected and may be connected to ground. NC 4/19 Preliminary M5M5V5A36GP-75,85 REV.1.0 Renesas LSIs M5M5V5A36GP-75,85 18874368-BIT(524288-WORD BY 36-BIT) Read Operations Flow-Through NETWORK SRAM Flow-Through Read Read operation is initiated when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1#, E2 and E3#) are active, the write enable input signal (W#) is deasserted high, and ADV is asserted low. #0 #1 #2 #3 #4 CLK E1# ADV W# BWx# ADD A C Read A Deselect D Q(B) Q(A) DQ Write Operation B Read B Read C E Q(C) Read D Q(D) Read E Single Late Write Write operation occurs when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1#, E2 and E3#) are active, the write enable input signal (W#) is asserted low, and ADV is asserted low. In Single Late Write the RAM requires Data in one rising clock edge later than the edge used to load Address and Control. #0 #1 #2 #3 #4 CLK E1# ADV W# BWx# ADD A B D(A) DQ Write A Deselect C D D(B) Write B Write C E D(C) Write D D(D) Write E 5/19 Preliminary M5M5V5A36GP-75,85 REV.1.0 Renesas LSIs M5M5V5A36GP-75,85 18874368-BIT(524288-WORD BY 36-BIT) Flow-Through NETWORK SRAM Single Late Write with Flow-Through Read #0 #1 #2 #3 #4 #5 #6 CLK E1# ADV W# BWx# ADD A DQ Write A B C D(A) Q(B) Read B Deselect D D(C) Write C Read D E Q(D Write E F D(E Read F 6/19 Preliminary M5M5V5A36GP-75,85 REV.1.0 Renesas LSIs M5M5V5A36GP-75,85 18874368-BIT(524288-WORD BY 36-BIT) Flow-Through NETWORK SRAM DC OPERATED TRUTH TABLE Name Input Status LBO# HIGH or NC LOW Operation Interleaved Burst Sequence Linear Burst Sequence Note4. LBO# is DC operated pin. Note5. NC means No Connection. Note6. See BURST SEQUENCE TABLE about interleaved and Linear Burst Sequence. BURST SEQUENCE TABLE Interleaved Burst Sequence (when LBO# = HIGH or NC) Operation A18~A2 First access, latch external address Second access(first burst address) Third access(second burst address) Fourth access(third burst address) A1,A0 A18~A2 latched A18~A2 latched A18~A2 latched A18~A2 0,1 0,0 1,1 1,0 0,0 0,1 1,0 1,1 1,0 1,1 0,0 0,1 1,1 1,0 0,1 0,0 Linear Burst Sequence Operation A18~A2 A1,A0 First access, latch external address A18~A2 0,0 0,1 1,0 1,1 Second access(first burst address) latched A18~A2 0,1 1,0 1,1 0,0 Third access(second burst address) latched A18~A2 1,0 1,1 0,0 0,1 Fourth access(third burst address) latched A18~A2 1,1 0,0 0,1 1,0 Note7. The burst sequence wraps around to its initial state upon completion. TRUTH TABLE Address E1# E2 E3# ZZ ADV W# BWx# G# CKE# CLK DQ H X X X L X X X H L L L L L L X X X X X X X X X L L L L->H High-Z None L->H High-Z None L->H High-Z None Deselect Cycle Deselect Cycle Deselect Cycle X X X L H X X X L L->H High-Z None Continue Deselect Cycle L X L X H X H X L X L X L L L L L H L H H X H X X X X X L L H H L L L L L->H Q External L X L X H X H X L X L X L L L L L H L H L X L X L L H H X X X X L L L L X X X L X X X X H used L->H Q Next L->H High-Z External L->H High-Z Next L->H D External L->H D Next L->H High-Z None L->H High-Z Next L->H - Current Operation Read Cycle, Begin Burst Read Cycle, Continue Burst NOP/Dummy Read, Begin Burst Dummy Read, Continue Burst Write Cycle, Begin Burst Write Cycle, Continue Burst NOP/Write Abort, Begin Burst Write Abort, Continue Burst Ignore Clock edge, Stall X X X H X X X X X Snooze Mode X High-Z None Note8. “H” = input VIH; “L” = input VIL; “X” = input VIH or VIL. Note9. BWx#=H means all Synchronous Byte Write Enables (BWa#,BWb#,BWc#,BWd#) are HIGH. BWx#=L means one or more Synchronous Byte Write Enables are LOW. Note10. All inputs except G# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 7/19 Preliminary M5M5V5A36GP-75,85 REV.1.0 Renesas LSIs M5M5V5A36GP-75,85 18874368-BIT(524288-WORD BY 36-BIT) Flow-Through NETWORK SRAM STATE DIAGRAM F,L,X Deselect F,L,X T,L,H T,L,L X,H,X Read Begin Burst T,L,H X,H,X T,L,H Write Begin Burst T,L,L T,L,H X,H,X X,H,X Read Continue Burst T,L,L Key F,L,X T,L,H T,L,L T,L,L Write Continue Burst X,H,X Input Command Code f Current State Transition Next State Note11. The notation "x , x , x" controlling the state transitions above indicate the state of inputs E, ADV and W# respectively. Note12. If (E1# = L and E2 = H and E3# = L) then E="T" else E="F". Note13. "H" = input VIH; "L" = input VIL; "X" = input VIH or VIL; "T" = input "true"; "F" = input "false". 8/19 Preliminary M5M5V5A36GP-75,85 REV.1.0 Renesas LSIs M5M5V5A36GP-75,85 18874368-BIT(524288-WORD BY 36-BIT) Flow-Through NETWORK SRAM WRITE TRUTH TABLE W# BWa# BWb# BWc# BWd# H X X X X L L H H H L H L H H L H H L H L H H H L L L L L L Function Read Write Byte a Write Byte b Write Byte c Write Byte d Write All Bytes Write Abort/NOP L H H H H Note14. “H” = input VIH; “L” = input VIL; “X” = input VIH or VIL. Note15. All inputs except G# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. ABSOLUTE MAXIMUM RATINGS Symbol VDD VDDQ VI VO PD TOPR TSTG(bias) TSTG Parameter Conditions Power Supply Voltage I/O Buffer Power Supply Voltage Input Voltage With respect to VSS Output Voltage Maximum Power Dissipation (VDD) Operating Temperature Storage Temperature(bias) Ratings Unit -1.0*~4.6 -1.0*~4.6 -1.0~VDDQ+1.0** -1.0~VDDQ+1.0** 1180 0~70 -10~85 -65~150 V V V V mW °C °C Storage Temperature Note16.* This is –1.0V when pulse width≤2ns, and –0.5V in case of DC. ** This is –1.0V~VDDQ+1.0V when pulse width≤2ns, and –0.5V~VDDQ+0.5V in case of DC. °C CAPACITANCE Symbol CI CO Parameter Input Capacitance Input / Output(DQ) Capacitance Note19.This parameter is sampled. Conditions Limits Min Typ Max 6 8 VI=GND, VI=25mVrms, f=1MHz VO=GND, VO=25mVrms, f=1MHz Unit pF pF THERMAL RESISTANCE 4-Layer PC board mounted (70x70x1.6mmT) Symbol θJA Parameter Thermal Resistance Junction Ambient Conditions Air velocity=0m/sec Air velocity=2m/sec θJC Thermal Resistance Junction to Case Note20.This parameter is sampled. Limits Min Typ 28 20 6.6 Max Unit °C/W °C/W °C/W 9/19 Preliminary M5M5V5A36GP-75,85 REV.1.0 Renesas LSIs M5M5V5A36GP-75,85 18874368-BIT(524288-WORD BY 36-BIT) Flow-Through NETWORK SRAM DC ELECTRICAL CHARACTERISTICS (Ta=0~70°C, VDD=3.135~3.465V, unless otherwise noted) Limits Symbol Parameter VDD Power Supply Voltage VDDQ I/O Buffer Power Supply Voltage VIH VIL Condition Unit Min Max 3.135 3.465 VDDQ = 3.3V 3.135 3.465 VDDQ = 2.5V 2.375 2.625 VDDQ = 3.135~3.465V 2.0 VDDQ = 2.375~2.625V 1.7 High-level Input Voltage VDDQ = 3.135~3.465V Low-level Input Voltage -0.3* VDDQ = 2.375~2.625V VDDQ+0.3* 0.8 0.7 VOH High-level Output Voltage IOH = -2.0mA VOL Low-level Output Voltage IOL = 2.0mA 0.4 Input Current except ZZ and LBO# VI = 0V ~ VDDQ 10 Input Current of LBO# VI = 0V ~ VDDQ 100 Input Current of ZZ VI = 0V ~ VDDQ 100 Off-state Output Current VI (G#) ≥ VIH, VO = 0V ~ VDDQ -75(Cycle time=8.5ns) 280 Power Supply Current : Operating Device selected; Output Open VI≤VIL or VI≥VIH ZZ≤VIL -85(Cycle time=10ns) 260 Device deselected VI≤VIL or VI≥VIH ZZ≤VIL -75(Cycle time=8.5ns) 90 -85(Cycle time=10ns) 80 ILI ILO ICC1 ICC2 Power Supply Current : Deselected VDDQ-0.4 CMOS Standby Current (CLK stopped standby mode) V V V V 10 V µA µA mA Device deselected; Output Open VI≤VSS+0.2V or VI≥VDDQ-0.2V CLK frequency=0Hz, All inputs static Snooze mode Snooze Mode Standby Current ICC4 ZZ≥VDDQ-0.2V Device selected; -75(Cycle time=8.5ns) Output Open Stall Current CKE#≥VIH ICC5 VI≤VSS+0.2V or -85(Cycle time=10ns) VI≥VDDQ-0.2V Note17.*VILmin is –1.0V and VIH max is VDDQ+1.0V in case of AC(Pulse width≤2ns). Note18."Device Deselected" means device is in power-down mode as defined in the truth table. ICC3 V mA 30 mA 30 mA 80 mA 70 10/19 Preliminary M5M5V5A36GP-75,85 REV.1.0 Renesas LSIs M5M5V5A36GP-75,85 18874368-BIT(524288-WORD BY 36-BIT) Flow-Through NETWORK SRAM AC ELECTRICAL CHARACTERISTICS (Ta=0~70°C, VDD=3.135~3.465V, unless otherwise noted) (1)MEASUREMENT CONDITION Input pulse levels ········································ VIH=VDDQ, VIL=0V Input rise and fall times ······························· faster than or equal to 1V/ns Input timing reference levels ······················· VIH=VIL=0.5*VDDQ Output reference levels ·······························VIH=VIL=0.5*VDDQ Output load ·················································· Fig.1 30pF (Including wiring and JIG) Q ZO=50Ω 50Ω VT=0.5*VDDQ Fig.1 Output load Input Waveform VDDQ / 2 toff tplh Output Waveform Input Waveform VDDQ / 2 VDDQ / 2 Fig.2 Tdly measurement tphl Vh Output Waveform (toff) Vl ton Vh-(0.2(Vh-Vz)) Vz+(0.2(Vh-Vz)) Vz 0.2(Vz-Vl) Vz-(0.2(Vz-Vl)) (ton) Fig.3 Tri-State measurement Note21.Valid Delay Measurement is made from the VDDQ/2 on the input waveform to the VDDQ/2 on the output waveform. Input waveform should have a slew rate of faster than or equal to 1V/ns. Note22.Tri-state toff measurement is made from the VDDQ/2 on the input waveform to the output waveform moving 20% from its initial to final Value VDDQ/2. Note:the initial value is not VOL or VOH as specified in DC ELECTRICAL CHARACTERISTICS table. Note23. Tri-state ton measurement is made from the VDDQ/2 on the input waveform to the output waveform moving 20% from its initial Value VDDQ/2 to its final Value. Note:the final value is not VOL or VOH as specified in DC ELECTRICAL CHARACTERISTICS table. Note24.Clocks,Data,Address and control signals will be tested with a minimum input slew rate of faster than or equal to 1V/ns. 11/19 Preliminary M5M5V5A36GP-75,85 REV.1.0 Renesas LSIs M5M5V5A36GP-75,85 18874368-BIT(524288-WORD BY 36-BIT) Flow-Through NETWORK SRAM (2)TIMING CHARACTERISTICS Limits Symbol Parameter -75 Min Unit -85 Max Min Max Clock tKHKH tKHKL tKLKH Clock Cycle time Clock HIGH time Clock LOW time 8.5 2.8 2.8 10 3.0 3.0 ns ns ns Output times tKHQV tKHQX tKHQX1 tKHQZ tGLQV tGLQX1 tGHQZ Clock HIGH to output valid Clock HIGH to output invalid Clock HIGH to output in LOW-Z Clock HIGH to output in High-Z G# to output valid G# to output in Low-Z G# to output in High-Z 7.5 2.5 2.5 8.5 2.5 2.5 4.0 3.5 0.0 5.0 4.0 0.0 3.5 4.0 ns ns ns ns ns ns ns Setup times tAVKH tckeVKH tadvVKH tWVKH tBVKH tEVKH tDVKH Address valid to clock HIGH CKE# valid to clock HIGH ADV valid to clock HIGH Write valid to clock HIGH Byte write valid to clock HIGH (BWa#~BWd#) Enable valid to clock HIGH (E1#,E2,E3#) Data In valid to clock HIGH 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 ns ns ns ns ns ns ns Clock HIGH to Address don’t care Clock HIGH to CKE# don’t care Clock HIGH to ADV don’t care Clock HIGH to Write don’t care Clock HIGH to Byte Write don’t care (BWa#~BWb#) Clock HIGH to Enable don’t care (E1#,E2,E3#) Clock HIGH to Data In don’t care 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns ns ns ns ns ns ns Hold times tKHAX tKHckeX tKHadvX tKHWX tKHBX tKHEX tKHDX ZZ tZZS tZZREC ZZ standby 2*tKHKH ZZ recovery 2*tKHKH Note25.All parameter except tZZS, tZZREC in this table are measured on condition that ZZ=LOW fix. Note26.Test conditions is specified with the output loading shown in Fig.1 unless otherwise noted. Note27. tKHQX1, tKHQZ, tGLQX1, tGHQZ are sampled. Note28.LBO# is static and must not change during normal operation. 2*tKHKH 2*tKHKH ns ns 12/19 Preliminary M5M5V5A36GP-75,85 REV.1.0 Renesas LSIs M5M5V5A36GP-75,85 18874368-BIT(524288-WORD BY 36-BIT) Flow-Through NETWORK SRAM (3)READ TIMING tKHKH CLK tKHKL tKLKH tckeVKH tKHckeX CKE# tEVKH tKHEX E# tadvVKH tKHadvX ADV tWVKH tKHWX W# BWx# tAVKH ADD tKHAX A1 A2 A3 tKHQX1 DQ tGLQV Q(A1) tKHQV Q(A2) Q(A2+1) Q(A2+2) Q(A2+3) tGHQZ tKHQX Q(A2) Q(A3) Q(A3+1) Q(A3+1) tKHQZ tGLQX1 G# Read A1 Read A2 Burst Read A2+1 Stall Burst Read Burst Read Burst Read A2+2 A2+3 A2 Deselect Continue Deselect Read A3 Burst Read Burst Read Burst Read A3+1 A3+2 A3+3 DON’T CARE UNDEFINED Note29.Q(An) refers to output from address An. Q(An+1) refers to output from the next internal burst address following An. Note30. E# represents three signals. When E# is LOW, it represents E1# is LOW, E2 is HIGH and E3# is LOW. Note31.ZZ is fixed LOW. 13/19 Preliminary M5M5V5A36GP-75,85 REV.1.0 Renesas LSIs M5M5V5A36GP-75,85 18874368-BIT(524288-WORD BY 36-BIT) Flow-Through NETWORK SRAM (4)WRITE TIMING tKHKH CLK tKHKL tKLKH tckeVKH tKHckeX CKE# tEVKH tKHEX E# tadvVKH tKHadvX ADV tWVKH tKHWX W# tBVKH tKHBX BWx# tAVKH ADD tKHAX A1 A2 A3 A4 tDVKH tKHDX DQ D(A1) D(A2) D(A2+1) Write A2 Burst Write A2+1 NOP D(A2+3) D(A2) D(A3) Write A2 Write A3 NOP D(A4) D(A4+1 D(A4+2) G# Write A1 Burst Write A2+3 Write A4 Burst Write A4+1 Stall DON'T CARE Burst Write Burst Write A4+2 A4+3 UNDEFINED Note32.Q(An) refers to output from address An. Q(An+1) refers to output from the next internal burst address following An. Note33. E# represents three signals. When E# is LOW, it represents E1# is LOW, E2 is HIGH and E3# is LOW. Note34.ZZ is fixed LOW. 14/19 Preliminary M5M5V5A36GP-75,85 REV.1.0 Renesas LSIs M5M5V5A36GP-75,85 18874368-BIT(524288-WORD BY 36-BIT) Flow-Through NETWORK SRAM (5)READ/WRITE TIMING tKHKH CLK tKHKL tKLKH tckeVKH tKHckeX CKE# tEVKH tKHEX E# tadvVKH tKHadvX ADV tWVKH tKHWX W# tBVKH tKHBX BWx# tAVKH ADD tKHAX A1 A2 tKHQX1 DQ A3 A4 A4 tDVKH tKHDX D(A1) tKHQV A3 Q(A2) D(A3) D(A3+1) Q(A3) Q(A3+1) Burst Read A3+1 Deselect D(A4) D(A4+1) Burst Write A4+1 Read A4 Q(A4) Q(A4+1) tKHQV G# Write A1 Read A2 Deselect Write A3 Burst Write A3+1 Read A3 Write A4 DON'T CARE Burst Read A4+1 Deselect UNDEFINED Note35.Q(An) refers to output from address An. Q(An+1) refers to output from the next internal burst address following An. Note36. E# represents three signals. When E# is LOW, it represents E1# is LOW, E2 is HIGH and E3# is LOW. Note37.ZZ is fixed LOW. 15/19 Preliminary M5M5V5A36GP-75,85 REV.1.0 Renesas LSIs M5M5V5A36GP-75,85 18874368-BIT(524288-WORD BY 36-BIT) Flow-Through NETWORK SRAM (6)SNOOZE MODE TIMING CLK tZZS tZZREC ZZ All Inputs (except ZZ) DESELECT or READ only Q Snooze Mode 16/19 Preliminary M5M5V5A36GP-75,85 REV.1.0 Renesas LSIs M5M5V5A36GP-75,85 18874368-BIT(524288-WORD BY 36-BIT) Flow-Through NETWORK SRAM PACKAGE OUTLINE Plastic 100pin 14x20 mm body 22±0.2 *2 20±0.1 80 0.125+0.05 -0.02 51 50 100 31 1 30 A *3 0.1 0.32+0.06 -0.07 0.13 M 0°~7° 0.125±0.075 0.65 Nom (1.4) 1.6 MAX *1 14±0.2 16±0.2 81 0.5±0.15 Detail A Note38. Dimensions *1 and *2 don't include mold flash. Note39 Dimension *3 doesn't include trim off set. Note40.All dimensions in millimeters. 17/19 Preliminary M5M5V5A36GP-75,85 REV.1.0 Renesas LSIs M5M5V5A36GP-75,85 18874368-BIT(524288-WORD BY 36-BIT) Flow-Through NETWORK SRAM REVISION HISTORY Rev. No. 0.0 0.1 1.0 History First revision DC ELECTRICAL CHARACTERISTICS Changed ILI limit from 10uA to 100uA (Input Leakage Current of ZZ and LBO#) Changed Icc3 and Icc4 limit from 20mA to 30mA (Standby Current) The semiconductor operations of HITACHI and MITSUBISHI Electric were transferred to RENESAS Technology Corporation on April 1st 2003. Date November 20, 2002 Preliminary January 31, 2003 Preliminary August 1, 2003 Preliminary 18/19 Preliminary M5M5V5A36GP-75,85 REV.1.0 Renesas LSIs M5M5V5A36GP-75,85 18874368-BIT(524288-WORD BY 36-BIT) Flow-Through NETWORK SRAM Nippon Bldg.,6-2,Oteamchi 2-chome,Chiyoda-ku,Tokyo,100-0004 Japan Keep safety first in your circuit designs! • Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. 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New publication, effective August 2003. Specifications subject to change without notice.