PowerPoint Template

Accurate Prediction of
Thermal Resistance of FET
by Detailed Modeling of Heat
Generation and Backend Stackup
Qun Wan, Don Willis, and Daniel Jin
September 12, 2012
2012, 45th International Symposium on Microelectronics
San Diego, CA, USA
Content
• Joule Heating and FET structure
• Heat Distribution and Averaging Schemes
• Backend Topology Modeling
• FET3 FEA Model
• Results and Discussion
• Effect of Various Heat Averaging Schemes
• Effect of Backend Stackup Layers
• Estimate Tj based on T_surf
• Conclusions
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Joule Heating in Differential Form
Integral form
Differential form
i
V, l
dV, dx
P = i V
P =  idV =  pdx
No current, No heat
(common sense)
No voltage drop, No heat
(superconductor)
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i
idV = pdx, p=idV/dx
pavg = P/l
Heat density p(x): W/m
Average heat density pavg: W/m
FET (field effect transistor) Structure
• Constant current
• Varying electrical potential density
• Varying heat density
Total Heat:
Average Heat density
under the gate:
Heat Distribution:
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P  iVd  Vs 
pavg
P

Lg
dV x 
px   i
dx
Distribution of Electrical Potential V(x) and Heat p(x)
Electrical Potential Field
Large
Gradie
nt
From RFMD electrical simulation group
• V(x) drops drastically around
the gate edge at drain side
Vg=0.35V
• p(x) heavily concentrates at
the same location
• Commonly assumed average
heat density under the gate
may be overly simplified in
both magnitude and location
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More Realistic Approaches to Average Heat Density
Heat Area Density:
qx  
px 
tc
• Heat Averaging Schemes
− GateAvg1:
• Commonly assumed average heat
density under the gate
− EdgeAvg2:
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qavg(W/m2)
Heat Avg
Width(m)
GateAvg1
0.55
8.08
EdgeAvg2
0.132
33.67
EdgeAvg3
0.17
26.14
• Use peak value as average
• A little overestimated at conservative
side
− EdgeAvg3:
• Consider both pulse peak and width
Backend Topology (SEM and model)
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Importance of Backend Layers in Heat Spreading
Backend Layer Removed
• Single Gate:
• Rth_die: 359C/W (Full Detail) vs. 604 C/W (no Backend Layer)
• Rth_die increase (no Backend Layer) : 68% from full detailed model
• Tj increase: 10C from full detailed model
• Multiple Gates:
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• Same Tj increase as single gate due to local phenomena of near source heat
spreading (pitch >> heat source size)
FET3 Die Assembly on Substrate and Eval board
(a) isometric view
of assembly
(b) zoom-in isometric view
(c) isometric view of die
with 24X4 fingers;
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(d) cross section view
Top Down Material Set for FEA Full Assembly Model
Material
Die
Passivation
Top Metal
Field Metal
Ohm Contact
Source/Drain
Gate
Schottky1
Channel
Silicon Nitride
Metal Composite
Metal Composite
Metal Composite
Doped GaAs
Metal Composite
InGaAs
Schottky2
Substrate
Back plating
Die Attach
GaAs
Au
Ag epoxy
Laminate
Dielectric
Pad
Solid Vias
CX50
Cu
Cu
Solder
Eval Board
Dielectric
Pad
Filled Vias
Thermal Grease
10
K(W/mK)
35
304/193
269/140
301/258
Varies
234/71
20
5
20
Varies
318
2.74
0.8
388
388
Micron scale
Nanometer scale
Micron scale
Millimeter scale
50.6
Rogers/FR4
Cu
Cu
0.64/0.3
388
0.54
1.1
Inch scale
Effect of Various Average Heat Schemes (Single Finger)
Tsurf=94.6C
Tj=97.5C
Tsurf=94.7C
Tj=100.5
C
Tsurf=95.9C
Tj=99.9C
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Single Finger: 250umX0.5um, 40mW
Effect of Various Average Heat Schemes (Single Finger)
• Scheme GateAvg1 predicts
much lower thermal
resistance (21% less from
EdgeAvg2) and junction
temperature (3C cooler from
EdgeAvg2)
 
Rth T j 
RthTs  
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T j  Tref
P
Ts  Tref
P
Definition of Thermal
resistance
Thermal resistance
defined by surface
temperature
(typically available from
thermal measurement)
• Use of surface temperature
as junction temperature
could lead to much lower die
thermal resistance Rth(Ts)
• Tjs is independent of
number of fingers
Effect of Backend Stackup Layers
• Heat spreading:
• Near heat source: all
directions
0.7C
• Substrate: pass thru and
spreading
5.3C
• Backend layers: lateral
spreading and go back into
substrate at distance.
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Estimate Tj based on T_surf
• Numerical Method
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y = 139.25x
• Backend layer detail specific
 
Rth T j 
T j  Tref
P
 RthTs   
Tj- Tsurf (C)
T j  Ts  P
5
4
Tsurf
3
2
Tj
1
0
 = 0.139C/mW
0
0.01
varies with FET device Technology
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0.02
0.03
Finger Power (W)
0.04
0.05
Conclusions
• Heat distribution within the FET channel
is heavily localized at the gate edge
towards drain side.
• Heat spreading can be accurately
predicted by detailed modeling of
backend topology.
• Junction temperature and thermal
resistance of FET device can be
accurately obtained both experimentally
and numerically with the estimation
based on surface temperature.
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Vg=0.35V
Qun Wan, Don Willis, and Daniel Jin
RF Micro Devices
7628 Thorndike Road
Greensboro, NC 27409-9421
Ph: 336-678-8557
Fax: 336-931-6706
Email: [email protected]
Thank you!
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