EVALUATION KIT AVAILABLE MAX16930/MAX16931 2MHz, 36V, Dual Buck with Preboost and 20µA Quiescent Current General Description The MAX16930/MAX16931 offer two high-voltage, synchronous step-down controllers and a step-up preboost controller. They operate with an input voltage supply from 2V to 42V with preboost active and can operate in drop-out condition by running at 95% duty cycle. The devices are intended for applications with mid- to high-power requirements that operate at a wide input voltage range such as during automotive cold-crank or engine stop-start conditions. The MAX16930/MAX16931 step-down controllers operate 180N out-of-phase at frequencies up to 2.2MHz to allow small external components, reduced output ripple, and to guarantee no AM band interference. The switching frequency is resistor adjustable. The FSYNC input programmability enables three frequency modes for optimized performance: forced fixed-frequency operation, skip mode with ultra-low quiescent current (20FA), and synchronization to an external clock. The devices also provide a spread-spectrum option to minimize EMI interference. Features S Dual, 2MHz Step-Down Controllers S Preboost for Operation to 2V S 180° Out-of-Phase Operation S 50ns Minimum On-Time Allows 3.3V Output from Car Battery at 2.2MHz S 20µA Operating Current S Wide Input Supply Range from 3.5V to 36V (without Preboost) S Resistor Programmable Frequency Between 200kHz and 2.2MHz S Q1% Output-Voltage Accuracy: 5.0V/3.3V Fixed or Adjustable Between 1V and 10V S Current-Mode Controllers with Forced Continuous and Skip Modes S Frequency Synchronization Input S Supply Overvoltage and Undervoltage Lockout S Overtemperature and Short-Circuit Protection The MAX16930/MAX16931 are offered with an asynchronous step-up controller. This preboost circuitry turns on during low input voltage conditions. It is designed to provide power to step-down controller channels with input voltages as low as 2V. S Thermally Enhanced 40-Pin TQFN-EP Package The devices also feature a power-OK monitor and overvoltage and undervoltage lockout. Protection features include cycle-by-cycle current limit and thermal shutdown. POL Applications for Automotive Power The devices are available in a 40-pin TQFN-EP package and are specified for operation over the -40NC to +125NC automotive temperature range. S -40NC to +125NC Operating Temperature Applications Distributed DC Power Systems Navigation and Radio Head Units Ordering Information and Selector Guide appear at end of data sheet. For related parts and recommended products to use with this part, refer to: www.maximintegrated.com/MAX16930.related For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com. 19-6631; Rev 1; 7/13 MAX16930/MAX16931 2MHz, 36V, Dual Buck with Preboost and 20µA Quiescent Current ABSOLUTE MAXIMUM RATINGS IN, INS, CS3P, CS3N, FB3, EN1, EN2, EN3, TERM to PGND_........................................-0.3V to +42V CS1, CS2, OUT1, OUT2 to AGND.........................-0.3V to +11V CS1 to OUT1.........................................................-0.2V to +0.2V CS2 to OUT2.........................................................-0.2V to +0.2V CS3P to CS3N.......................................................-0.2V to +0.2V BIAS, FSYNC, FOSC to AGND..............................-0.3V to +6.0V COMP1, COMP2, BSTON to AGND......................-0.3V to +6.0V FB1, FB2, FSELBST, EXTVCC to AGND...............-0.3V to +6.0V DL_ to PGND_ ......................................................-0.3V to +6.0V BST_ to LX_ .........................................................-0.3V to + 6.0V DH_ to LX_...........................................................-0.3V to + 6.0V LX_ to PGND_........................................................-0.3V to +42V PGND_ to AGND...................................................-0.3V to +0.3V PGOOD1, PGOOD2 to AGND..............................-0.3V to +6.0V Continuous Power Dissipation (TA = +70NC) TQFN (derate 35.7mW/NC above +70NC)..................2857mW Operating Temperature Range......................... -40NC to +125NC Junction Temperature Range...........................................+150NC Storage Temperature Range............................. -65NC to +150NC Lead Temperature (soldering, 10s).................................+300NC Soldering Temperature (reflow).......................................+260NC Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PACKAGE THERMAL CHARACTERISTICS (Note 1) TQFN Junction-to-Ambient Thermal Resistance (qJA)...........28°C/W Junction-to-Case Thermal Resistance (qJC)...............1.7°C/W Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. ELECTRICAL CHARACTERISTICS (VIN = 14V, VBIAS = 5V, CBIAS = 6.8μF, TA = TJ = -40NC to +125NC, unless otherwise noted.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT SYNCHRONOUS STEP-DOWN DC-DC CONVERTERS Normal operation Supply Voltage Range Supply Current VIN IIN Buck 1 Fixed Output Voltage VOUT1 Buck 2 Fixed Output Voltage VOUT2 Output Voltage Adjustable Range Maxim Integrated 3.5 36 t < 1s With preboost after initial startup condition is satisfied 42 2.0 36 VEN1 = VEN2 = VEN3 = 0V 8 20 VEN1 = 5V, VOUT1 = 5V, VEN2 = VEN3 = 0V, VEXTVCC = 5V, no switching 30 40 VEN2 = 5V, VOUT2 = 3.3V, VEN1 = VEN3 = 0V, VEXTVCC = 3.3V, no switching 20 30 VEN1 = VEN2 = 5V, VOUT1 = 5V, VOUT2 = 3.3V, VEN3 = 0V, VEXTVCC = 3.3V, no switching 25 40 VFB1 = VBIAS, PWM mode 4.95 5 5.05 VFB1 = VBIAS, skip mode 4.95 5 5.075 VFB2 = VBIAS, PWM mode 3.234 3.3 3.366 VFB2 = VBIAS, skip mode 3.234 3.3 3.4 Buck 1, buck 2 1 V 10 FA V V V 2 MAX16930/MAX16931 2MHz, 36V, Dual Buck with Preboost and 20µA Quiescent Current ELECTRICAL CHARACTERISTICS (continued) (VIN = 14V, VBIAS = 5V, CBIAS = 6.8μF, TA = TJ = -40NC to +125NC, unless otherwise noted.) (Note 2) PARAMETER Regulated Feedback Voltage SYMBOL IFB1,2 Feedback Line Regulation Error Transconductance (from FB_ to COMP_) gm Dead Time Maximum Duty-Cycle Minimum On-Time TYP MAX UNIT 0.99 1.0 1.01 V FB rising +10 +15 +20 FB falling (Note 3) +5 +10 +15 TA = +25NC 0.01 1 VIN = 3.5V to 36V, VFB = 1V 0.00 VFB = 1V, VBIAS = 5V (Note 4) 1200 MAX16930, DL_ low to DH_ high 35 MAX16930, DH_ low to DL_ high 60 MAX16931, DL_ low to DH_ high 60 MAX16931, DH_ low to DL_ high 100 Buck 1, buck 2 tON(MIN) PWM Switching Frequency Range fSW Spread-Spectrum Range % FA %/V 2400 FS ns 95 Buck 1, buck 2 50 % ns Programmable, high frequency, MAX16930 1 2.2 Programmable, low frequency, MAX16931 0.2 1 MHz MAX16930ATLT/V+, MAX16930ATLU/V+ only Buck 2 Switching Frequency Switching Frequency Accuracy MIN VFB1,2 Output Overvoltage Threshold Feedback Leakage Current CONDITIONS 1/2fSW MHz MAX16930, RFOSC = 13.7kI, VBIAS = 5V 1.98 2.2 2.42 MHz MAX16931, RFOSC = 80.6kI, VBIAS = 5V 360 400 440 kHz Spread spectrum enabled ±6 % FSYNC INPUT FSYNC Frequency Range FSYNC Switching Thresholds CS Current-Limit Voltage Threshold Minimum sync pulse of 100ns, MAX16930 1.2 2.4 MHz Minimum sync pulse of 100ns, MAX16931 240 1200 kHz High threshold 1.5 Low threshold VLIMIT1,2 VCS - VOUT, VBIAS = 5V, VOUT R 2.5V Skip Mode Threshold Current sense = 80mV Soft-Start Ramp Time Buck 1 and buck 2, fixed soft-start time regardless of frequency Phase Shift Between Buck1 and Buck 2 0.6 64 80 96 15 2 6 V mV mV 10 180 ms ° LX1, LX2 Leakage Current VIN = 6V, VLX_ = VIN, TA = +25NC 0.01 1 FA DH1, DH2 Pullup Resistance VBIAS = 5V, IDH_ = -100mA 10 20 I DH1, DH2 Pulldown Resistance VBIAS = 5V, IDH_ = +100mA 2 4 I Maxim Integrated 3 MAX16930/MAX16931 2MHz, 36V, Dual Buck with Preboost and 20µA Quiescent Current ELECTRICAL CHARACTERISTICS (continued) (VIN = 14V, VBIAS = 5V, CBIAS = 6.8μF, TA = TJ = -40NC to +125NC, unless otherwise noted.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT DL1, DL2 Pullup Resistance VBIAS = 5V, IDL_ = -100mA 4 8 I DL1, DL2 Pulldown Resistance VBIAS = 5V, IDL_ = +100mA 1.5 3 I PGOOD1, PGOOD2 Threshold PGOOD_H % of VOUT_, rising 85 90 95 PGOOD_F % of VOUT_, falling 80 85 90 0.01 1 PGOOD1, PGOOD2 Leakage Current VPGOOD1,2 = 5V, TA = +25NC PGOOD1, PGOOD2 Startup Delay Time Buck 1 and buck 2 after soft-start is complete PGOOD1, PGOOD2 Debounce Time Fault detection 64 8 % FA Cycles 20 40 Fs 5 5.25 V 3.1 3.4 INTERNAL LDO: BIAS Internal BIAS Voltage VIN > 6V 4.75 VBIAS rising BIAS UVLO Threshold VBIAS falling 2.7 Hysteresis External VCC Threshold 2.9 0.2 VTH,EXTVCC EXTVCC rising, HYST = 110mV 3 V V 3.2 V THERMAL OVERLOAD Thermal Shutdown Temperature (Note 4) 170 NC Thermal Shutdown Hysteresis (Note 4) 20 NC EN LOGIC INPUT High Threshold 1.8 V Low Threshold Input Current 0.01 EN1, EN2 logic inputs only, TA = +25NC 0.8 V 1 FA PREBOOST Minimum On Time TONBST Minimum Off Time TOFFBST 60 ns 60 ns VFSELBST = 0V, RFOSC = 13.7kI 1.98 2.2 2.42 VFSELBST = VBIAS, RFOSC = 13.7kI 0.4 0.44 0.48 108 120 132 mV 1 1.05 1.1 V Switching Frequency fBOOST Current Limit ILIMBST CS3P - CS3N INS Unlock Threshold VINS,UV One-time latch during startup; preboost is disabled until the VINS rises above this threshold INS Off Threshold VINS,OFF Battery rising and EN3 high, preboost turns off if VINS is above this threshold 1.2 1.25 1.3 INS On Threshold VINS,ON,SW Battery falling and EN3 high, preboost turns back on when VINS falls below this threshold 1.1 1.15 1.2 Maxim Integrated MHz V 4 MAX16930/MAX16931 2MHz, 36V, Dual Buck with Preboost and 20µA Quiescent Current ELECTRICAL CHARACTERISTICS (continued) (VIN = 14V, VBIAS = 5V, CBIAS = 6.8μF, TA = TJ = -40NC to +125NC, unless otherwise noted.) (Note 2) PARAMETER INS Threshold Undervoltage Lockout SYMBOL VINS,UV CONDITIONS MIN TYP MAX Battery rising and EN3 high 0.325 0.35 0.375 Battery falling and EN3 high, preboost turns off when VINS falls below this threshold 0.275 0.3 0.325 0.01 1 BSTON Leakage Current VBSTON = 5V, TA = +25NC BSTON Debounce Time Fault detection 10 DL3 Pullup Resistance VBIAS = 5V, IDL3 = -100mA 4 DL3 Pulldown resistance Feedback Voltage Boost Load Regulation Error EN3 Threshold VBIAS = 5V, IDL3 = +100mA VFB3 No load on boost output 1.1875 0mV < VCS3P - VCS3N < 120mV, error proportional to input current High threshold UNIT V FA Fs 8 I 1 2 I 1.25 1.3125 V 0.7 %/A 3.5 Low threshold 2 V EN3 Input Current VEN3 = 5.5V 7 14 FA TERM Resistance ITERM = 10mA 70 150 I TERM Leakage Current VTERM = 14V, VEN3 = 0V, TA = +25NC 0.01 1 FA INS and FB3 Leakage Current TA = +25NC 0.01 1 FA Note 2: Limits are 100% production tested at TA = +25°C. Limits over the operating temperature range and relevant supply voltage are guaranteed by design and characterization. Typical values are at TA = +25°C. Note 3: Overvoltage protection is detected at the FB1/FB2 pins. If the feedback voltage reaches overvoltage threshold of FB1/FB2 + 15% (typ), the corresponding controllers stop switching. The controllers resume switching once the output drops below FB1/FB2 + 10% (typ). Note 4: Guaranteed by design; not production tested. Maxim Integrated 5 MAX16930/MAX16931 2MHz, 36V, Dual Buck with Preboost and 20µA Quiescent Current Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) NO-LOAD STARTUP SEQUENCE (VFSYNC = 0V) MAX16930 toc01 FULL-LOAD STARTUP SEQUENCE (VFSYNC = 0V) MAX16930 toc02 VBAT 5V/div VOUT1 2V/div IOUT1 2A/div VPGOOD1 5V/div VOUT2 2V/div IOUT2 2A/div VPGOOD2 5V/div VOUT1 2V/div VOUT2 2V/div VPGOOD1 5V/div VPGOOD2 5V/div 4ms/div VEN1 = 0V VEN2 = VBAT EXTVCC = VOUT2 10 70 60 MAX16930 toc04 BUCK 1 EXTVCC = VOUT2 40 30 20 0 20 40 60 80 100 120 140 80 5 10 15 70 60 EXTVCC = GND SKIP MODE 50 30 PWM MODE 10 20 25 30 35 EXTVCC = GND EXTVCC = VOUT1 40 20 BUCK 2 EXTVCC = VOUT2 0 fSW = 2.2MHz EXTVCC = VOUT1 L = 2.2µH VBAT = 14V VOUT1 = 5V 90 0 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E+00 1.0E+01 40 SUPPLY VOLTAGE (V) IOUT1 (A) BUCK 2 EFFICIENCY SWITCHING FREQUENCY vs. LOAD CURRENT SWITCHING FREQUENCY vs. RFOSC (MAX16930) fSW = 2.2MHz EXTVCC = VOUT2 L = 2.2µH VBAT = 14V VOUT2 = 3.3V SKIP MODE 50 40 30 EXTVCC = GND EXTVCC = VOUT2 20 EXTVCC = GND PWM MODE 10 0 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E+00 1.0E+01 IOUT1 (A) Maxim Integrated 2.30 2.28 BUCK 2 2.26 2.24 2.22 BUCK 1 2.20 2.18 2.16 2.14 2.12 2.10 0 1 2 3 4 LOAD CURRENT (A) 5 6 MAX16930 toc08 TEMPERATURE (°C) 2.4 SWITCHING FREQUENCY (MHz) 80 50 MAX16930 toc07 90 0 60 10 SWITCHING FREQUENCY (MHz) 100 -60 -40 -20 70 BUCK 1 EFFICIENCY 100 EFFICIENCY (%) 20 80 QUIESCENT CURRENT (µA) 30 MAX16930 toc06 QUIESCENT CURRENT (µA) 40 0 EFFICIENCY (%) VEN1 = VBAT VEN2 = 0V EXTVCC = VOUT1 50 QUIESCENT CURRENT vs. SUPPLY VOLTAGE MAX16930 toc03 QUIESCENT CURRENT vs. TEMPERATURE MAX16930 toc05 2ms/div 60 VBAT 5V/div 2.2 2.0 VBIAS = 5V 1.8 1.6 VBIAS = 3.3V 1.4 1.2 1.0 10 15 20 25 30 RFOSC (kΩ) 6 MAX16930/MAX16931 2MHz, 36V, Dual Buck with Preboost and 20µA Quiescent Current Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) 2.40 1.0 0.9 SWITCHING FREQUENCY (MHz) MAX16930 toc09 SWITCHING FREQUENCY (MHz) 1.1 0.8 0.7 VBIAS = 5V 0.6 0.5 0.4 0.3 0.2 2.35 SWITCHING FREQUENCY vs. TEMPERATURE MAX16930 toc10 SWITCHING FREQUENCY vs. RFOSC (MAX16931) RFOSC = 13.7kΩ 2.30 2.25 2.20 2.15 2.10 2.05 VBIAS = 3.3V 2.00 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 -60 -40 -20 0 RFOSC (kΩ) LOAD TRANSIENT RESPONSE DIPS AND DROPS EXTERNAL FSYNC TRANSITION MAX16930 toc12 MAX16930 toc11 20 40 60 80 100 120 140 TEMPERATURE (ºC) MAX16930 toc13 VBAT 10V/div VLX1 10V/div VOUT1 100mV/div VLX2 10V/div IOUT1 1A/div 400µs/div LOAD DUMP SLOW VIN RAMP VOUT2 1V/div SHORT-CIRCUIT RESPONSE MAX16930 toc15 MAX16930 toc16 IOUT1 2A/div VOUT1 2V/div VPGOOD1 5V/div VOUT2 2V/div VPGOOD2 5V/div VPGOOD2 5V/div Maxim Integrated 40ms/div VBAT 5V/div VBAT 10V/div LOAD DUMP, PWM 100ms/div VOUT1 5V/div VFSYNC 2V/div 400ns/div MAX16930 toc14 VPGOOD1 5V/div 10s/div 200µs/div VOUT1 1V/div VPGOOD1 2V/div 7 MAX16930/MAX16931 2MHz, 36V, Dual Buck with Preboost and 20µA Quiescent Current Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) MAX16930 toc17 BUCK 1 LOAD REGULATION 4.998 VFSYNC = VBIAS 4.997 VOUT1 1V/div VPGOOD1 2V/div MAX16930 toc18 OUTPUT OVERVOLTAGE RESPONSE 4.996 VOUT_ (V) 4.995 4.994 4.993 4.992 4.991 4.990 4.989 1s/div 0 1 2 3 4 5 6 IOUT_ (A) 3.294 3.293 3.292 99.90 99.85 99.80 3.290 99.75 0 1 2 3 4 99.70 6 5 1.005 1.000 -60 -40 -20 0 20 40 60 80 100 120 140 0.990 0 10 15 20 25 30 35 40 VSUP (V) MINIMUM ON-TIME (BUCK 1) FB2 LINE REGULATION MAX16930 toc22 MAX16930 toc23 VOUT1 = 1.8V IOUT1 = 300mA VBAT 5V/div 1.000 0.995 0.990 5 TEMPERATURE (ºC) 1.005 VOUT_ (V) VOUT1 =1.8V 0.995 IOUT_ (A) 1.010 FB1 LINE REGULATION 1.010 VOUT1 99.95 3.291 3.289 EXTVCC = VGND VFSYNC = VBIAS IOUT_ =0A VOUT2 MAX16930 toc21 100.00 VOUT_ (%nominal) VOUT_ (V) 3.295 100.05 VOUT_ vs. TEMPERATURE VOUT_ (V) 3.296 100.10 MAX16930 toc19 VFSYNC = VBIAS MAX16930 toc20 BUCK 2 LOAD REGULATION 3.297 VOUT1 1V/div 0 5 10 15 20 25 30 35 40 200ns/div VSUP (V) Maxim Integrated 8 MAX16930/MAX16931 2MHz, 36V, Dual Buck with Preboost and 20µA Quiescent Current Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) MINIMUM ON-TIME (BUCK 2) COLD CRANK (PREBOOST ON) MAX16930 toc24 BOOST ENABLE MAX16930 toc25 MAX16930 toc26 IOUT2 = 300mA VBAT 10V/div VIN 5V/div VBSTON 5V/div VOUT1 5V/div VPGOOD1 5V/div VOUT2 5V/div VPGOOD2 5V/div VBAT 5V/div VOUT1 1V/div VIN 5V/div VSNS 1V/div VBSTON 5V/div 400ms/div LX WAVEFORMS MAX16930 toc27 2s/div IOUT1 = IOUT2 = 1A 9.95 VLX1 5V/div 9.90 PREBOOST LOAD REGULATION MAX16930 toc28 200ns/div VBAT 5V/div VBAT = 7V 9.85 VOUT_ (V) 9.80 VLX2 5V/div 9.75 9.70 9.65 9.60 VLXBST 5V/div 9.55 9.50 200ns/div 0 1 2 3 4 5 6 IOUT_ (A) 20 10 0 -10 300 320 340 360 380 400 320 440 460 480 500 FREQUENCY (kHz) Maxim Integrated 25 20 15 10 5 0 35 25 20 15 10 5 0 -5 -5 -10 960k 1.0M FREQUENCY (Hz) 1.1M 1.2M MEASURED ON THE MAX16930ATLS/V+ 30 -10 800k SPECTRAL ENERGY DENSITY vs. FREQUENCY MAX16930 toc31 30 MEASURED AT VOUT2 ON THE MAX16930ATLU/V+ OUTPUT SPECTRUM (dBµV) 30 35 SPECTRAL ENERGY DENSITY vs. FREQUENCY MAX16930 toc30 40 40 OUTPUT SPECTRUM (dBµV) MEASURED ON THE MAX16931ATLS/V+ MAX16930 toc29 OUTPUT SPECTRUM (dBµV) 50 SPECTRAL ENERGY DENSITY vs. FREQUENCY 1.8 2.0 2.2 2.4 2.6 FREQUENCY (MHz) 9 MAX16930/MAX16931 2MHz, 36V, Dual Buck with Preboost and 20µA Quiescent Current N.C. FSYNC FOSC COMP2 FB2 CS2 OUT2 PGND2 LX2 TOP VIEW DL2 Pin Configuration 30 29 28 27 26 25 24 23 22 21 DH2 31 20 PGOOD2 BST2 32 19 PGND3 18 DL3 FSELBST 33 17 TERM BSTON 34 MAX16930 MAX16931 EN2 35 EN1 36 16 CS3N 15 CS3P EN3 37 14 INS N.C. 38 13 FB3 BST1 39 12 PGOOD1 + 7 8 9 10 EXTVCC CS1 6 AGND PGND1 5 BIAS 4 FB1 3 COMP1 2 OUT1 1 LX1 11 IN DL1 DH1 40 TQFN Pin Description PIN NAME DESCRIPTION 1 LX1 Inductor Connection for Buck 1. Connect LX1 to the switched side of the inductor. LX1 serves as the lower supply rail for the DH1 high-side gate drive. 2 DL1 Low-Side Gate Drive Output for Buck 1. DL1 output voltage swings from VPGND1 to VBIAS. 3 PGND1 4 CS1 Positive Current-Sense Input for Buck 1. Connect CS1 to the positive terminal of the current-sense resistor. See the Current Limiting and Current-Sense Inputs and Current-Sense Measurement sections. 5 OUT1 Output Sense and Negative Current-Sense Input for Buck 1. When using the internal preset 5V feedback divider (FB1 = BIAS), the buck uses OUT1 to sense the output voltage. Connect OUT1 to the negative terminal of the current-sense resistor. See the Current Limiting and Current-Sense Inputs and Current-Sense Measurement sections. 6 FB1 7 COMP1 8 BIAS 9 AGND Maxim Integrated Power Ground for Buck 1 Feedback Input for Buck 1. Connect FB1 to BIAS for the 5V fixed output or to a resistive divider between OUT1 and GND to adjust the output voltage between 1V and 10V. In adjustable mode, FB1 regulates to 1V (typ). See the Setting the Output Voltage in Buck Converters section. Buck 1 Error-Amplifier Output. Connect an RC network to COMP1 to compensate buck 1. 5V Internal Linear Regulator Output. Bypass BIAS to GND with a low-ESR ceramic capacitor of 6.8FF minimum value. BIAS provides the power to the internal circuitry and external loads. See the Fixed 5V Linear Regulator (BIAS) section. Signal Ground for IC 10 MAX16930/MAX16931 2MHz, 36V, Dual Buck with Preboost and 20µA Quiescent Current Pin Description (continued) PIN NAME 10 EXTVCC 11 IN DESCRIPTION 3.1V to 5.2V Input to the Switchover Comparator Supply Input. Connect IN to the output of the preboost. Bypass IN with sufficient capacitance to supply the two out-of-phase buck converters. 12 PGOOD1 Open-Drain Power-Good Output for Buck 1. PGOOD1 is low if OUT1 is more than 15% (typ) below the normal regulation point. PGOOD1 asserts low during soft-start and in shutdown. PGOOD1 becomes high impedance when OUT1 is in regulation. To obtain a logic signal, pullup PGOOD1 with an external resistor connected to a positive voltage lower than 5.5V. 13 FB3 Preboost Feedback Input. Connect FB3 to the center tap of a resistive-divider between the boost regulator output and TERM to adjust the output voltage. FB3 regulates to 1.25V (typ). See the Setting the Output Voltage in Boost Converter section. 14 INS Input Voltage Sense for Preboost. The voltage at INS is compared to internal comparator reference. Program the preboost threshold by using resistor-divider from BAT to INS to TERM pin. 15 CS3P Positive Current-Sense Input for Preboost. Connect CS3P to the positive terminal of the currentsense resistor. See the Current Limit in Boost Controller and Shunt Resistor Selection in Boost Converter sections. 16 CS3N Negative Current-Sense Input for Preboost. Connect CS3N to the negative terminal of the currentsense resistor. See the Current Limit in Boost Controller and Shunt Resistor Selection in Boost Converter sections. 17 TERM Ground Switch. TERM opens when the voltage at EN3 is logic-low. Use TERM to terminate the preboost feedback and INS resistive divider. 18 DL3 19 PGND3 Preboost n-Channel MOSFET Gate-Drive Output Power Ground for Preboost. All the high-current paths for the preboost should terminate to this ground. Open-Drain Power-Good Output for Buck 2. PGOOD2 is low if OUT2 is more than 90% (typ) below the normal regulation point. PGOOD2 asserts low during soft-start and in shutdown. PGOOD2 becomes high impedance when OUT2 is in regulation. To obtain a logic signal, pullup PGOOD2 with an external resistor connected to a positive voltage lower than 5.5V. 20 PGOOD2 21, 38 N.C. 22 FSYNC External Clock Synchronization Input. Synchronization to the controller operating frequency ratio is 1. Keep fSYNC a minimum of 10% greater than the maximum internal switching frequency for stable operation. See the Switching Frequency/External Synchronization section. 23 FOSC Frequency Setting Input. Connect a resistor from FOSC to AGND to set the switching frequency of the DC-DC converters. 24 COMP2 25 FB2 Maxim Integrated No Connection Buck 2 Error Amplifier Output. Connect an RC network to COMP2 to compensate buck 2. Feedback Input for Buck 2. Connect FB2 to BIAS for the 3.3V fixed output or to a resistive divider between OUT2 and GND to adjust the output voltage between 1V and 10V. In adjustable mode, FB2 regulates to 1V (typ). See the Setting the Output Voltage in Buck Converters section. 11 MAX16930/MAX16931 2MHz, 36V, Dual Buck with Preboost and 20µA Quiescent Current Pin Description (continued) PIN NAME DESCRIPTION 26 OUT2 Output Sense and Negative Current-Sense Input for Buck 2. When using the internal preset 3.3V feedback-divider (FB2 = BIAS), the buck uses OUT2 to sense the output voltage. Connect OUT2 to the negative terminal of the current-sense resistor. See the Current Limiting and Current-Sense Inputs and Current-Sense Measurement sections. 27 CS2 Positive Current-Sense Input for Buck 2. Connect CS2 to the positive terminal of the current-sense resistor. See the Current Limiting and Current-Sense Inputs and Current-Sense Measurement sections. 28 PGND2 29 DL2 Low-Side Gate Drive Output for Buck 2. DL2 output voltage swings from VPGND2 to VBIAS. 30 LX2 Inductor Connection for Buck 2. Connect LX2 to the switched side of the inductor. LX2 serves as the lower supply rail for the DH2 high-side gate drive. 31 DH2 High-Side Gate Drive Output for Buck 2. DH2 output voltage swings from VLX2 to VBST2. 32 BST2 Boost Capacitor Connection for High-Side Gate Voltage of Buck 2. Connect a high-voltage diode between BIAS and BST2. Connect a ceramic capacitor between BST2 and LX2. See the High-Side Gate-Driver Supply (BST_) section. 33 FSELBST Frequency Select Pin for the Preboost. When pulled low, the preboost will have the same switching frequency as buck 1. When pulled high, the preboost will have a switching frequency that is 1/5th that of buck 1. FSELBST is only active for the MAX16930. FSELBST should be connected to ground for the MAX16931. 34 BSTON 35 EN2 High-Voltage Tolerant, Active-High Digital Enable Input for Buck 2. Driving EN2 high enables buck 2. 36 EN1 High-Voltage Tolerant, Active-High Digital Enable Input for Buck 1. Driving EN1 high enables buck 1. 37 EN3 High-Voltage Tolerant, Active-High Digital Enable Input for Preboost. When EN3 is high, the external preboost is enabled and begins switching if VINS drops below VINS,OLV and required conditions are met (see the Preboost section). 39 BST1 Boost Capacitor Connection for High-Side Gate Voltage of Buck 1. Connect a high-voltage diode between BIAS and BST1. Connect a ceramic capacitor between BST1 and LX1. See the High-Side Gate-Driver Supply (BST_) section. 40 DH1 High-Side Gate-Drive Output for Buck 1. DH1 output voltage swings from VLX1 to VBST1. — Maxim Integrated EP Power Ground for Buck 2 Preboost On-Indicator Output. To obtain a logic signal, pull up BSTON with an external resistor connected to a positive voltage lower than 5.5V. BSTON goes high to indicate that the preboost is on. Exposed Pad. Connect the exposed pad to ground. Connecting the exposed pad to ground does not remove the requirement for proper ground connections to PGND1, PGND2, PGND3, and AGND. The exposed pad is attached with epoxy to the substrate of the die, making it an excellent path to remove heat from the IC. 12 MAX16930/MAX16931 2MHz, 36V, Dual Buck with Preboost and 20µA Quiescent Current Detailed Description The MAX16930/MAX16931 are automotive-rated tripleoutput switching power supplies. These devices integrate two synchronous step-down controllers and an asynchronous step-up controller and can provide up to three independently controlled power rails as follows: • A preboost with adjustable output voltage. • A buck controller with a fixed 5V output voltage or an adjustable 1V to 10V output voltage. • A buck controller with a fixed 3.3V output voltage or an adjustable 1V to 10V output voltage. The buck controllers and the preboost can each provide up to 10A output current and ar independently controllable. Buck 1, buck 2, and the preboost are enabled and disabled by the EN1, EN2, and EN3 control inputs, respectively. These are active-high inputs and can be connected directly to car battery. • EN1 and EN2 enable the respective buck controllers. Connect EN1 and EN2 directly to VBAT or to powersupply sequencing logic. • EN3 controls the boost controller In standby mode (only buck 2 is active), the total supply current is reduced to 30µA (typ). When all three controllers are disabled, the total current drawn is further reduced to 6.8µA. Fixed 5V Linear Regulator (BIAS) The internal circuitry of the MAX16930/MAX16931 requires a 5V bias supply. An internal 5V linear regulator (BIAS) generates this bias supply. Bypass BIAS with a 6.8µF or greater ceramic capacitor to guarantee stability under the full-load condition. EXTVCC Switchover The internal linear regulator can be bypassed by connecting an external supply (3V to 5.2V) or the output of one of the buck converters to EXTVCC. BIAS internally switches to EXTVCC and the internal linear regulator turns off. This configuration has several advantages: • It reduces the internal power dissipation of the MAX16930/MAX16931. • The low-load efficiency improves as the internal supply current gets scaled down proportionally to the duty cycle. If VEXTVCC drops below VTH,EXTVCC = 3.0V (min), the internal regulator enables and switches back to BIAS. Undervoltage Lockout (UVLO) The BIAS input undervoltage lockout (UVLO) circuitry inhibits switching if the 5V bias supply (BIAS) is below its 2.9V (typ) UVLO falling threshold. Once the 5V bias supply (BIAS) rises above its UVLO rising threshold and EN1 and EN2 enable the buck controllers, the controllers start switching and the output voltages begin to ramp up using soft-start. Buck Controllers The MAX16930/MAX16931 provide two buck controllers with synchronous rectification. The step-down controllers use a PWM, current-mode control scheme. External logic-level MOSFETs allow for optimized load-current design. Fixed-frequency operation with optimal interleaving minimizes input ripple current from the minimum to the maximum input voltages. Output-current sensing provides an accurate current limit with a sense resistor or power dissipation can be reduced using lossless current sensing across the inductor. Soft-Start The internal linear regulator can source up to 100mA (150mA under EXTVCC switchover, see the EXTVCC Switchover section). Use the following equation to estimate the internal current requirements for the MAX16930/ MAX16931: Once a buck converter is enabled by driving the corresponding EN_ high, the soft-start circuitry gradually ramps up the reference voltage during soft-start time (tSSTART = 6ms (typ)) to reduce the input surge currents during startup. Before the device can begin the soft-start, the following conditions must be met: IBIAS = ICC + fSW(QG_DL3 + QG_DH1 + QG_DL1 + QG_DH2 + QG_DL2) = 10mA to 50mA (typ) 1)VBIAS exceeds the 3.4V (max) undervoltage lockout threshold. where ICC is the internal supply current, 5mA (typ), fSW is the switching frequency, and QG_ is the MOSFET’s total gate charge (specification limits at VGS = 5V). To minimize the internal power dissipation, bypass BIAS to an external 5V rail. Maxim Integrated 2)VEN_ is logic-high. 13 MAX16930/MAX16931 2MHz, 36V, Dual Buck with Preboost and 20µA Quiescent Current Switching Frequency/External Synchronization The MAX16930 provides an internal oscillator adjustable from 1MHz to 2.2MHz. The MAX16931 provides an internal oscillator adjustable from 200kHz to 1MHz. High-frequency operation optimizes the application for the smallest component size, trading off efficiency to higher switching losses. Low-frequency operation offers the best overall efficiency at the expense of component size and board space. To set the switching frequency, connect a resistor RFOSC from FOSC to AGND. See TOCs 8 and 9 in the Typical Operating Characteristics section to determine the relationship between switching frequency and RFOSC. Buck 1 and the boost converter are synchronized with the internal clock-signal rising edge, while buck 2 is synchronized with the clock-signal falling edge. The preboost enables the low-side switch (DL3) with the rising edge of the cycle while buck 1 turns on its high-side n-channel MOSFET (DH1). The devices can be synchronized to an external clock by connecting the external clock signal to FSYNC. A rising edge on FSYNC resets the internal clock. Keep the FSYNC frequency between 110% and 125% of the internal frequency. The FSYNC signal should have a 50% duty cycle. Light-Load Efficiency Skip Mode (VFSYNC = 0V) Drive FSYNC low to enable skip mode. In skip mode, the devices stop switching until the FB voltage drops below the reference voltage. Once the FB voltage has dropped below the reference voltage, the devices begin switching until the inductor current reaches 30% (skip threshold) of the maximum current defined by the inductor DCR or output shunt resistor. Forced-PWM Mode (VFSYNC) Driving FSYNC high prevents the devices from entering skip mode by disabling the zero-crossing detection of the inductor current. This forces the low-side gatedriver waveform to constantly be the complement of the high-side gate-drive waveform, so the inductor current reverses at light loads and discharges the output capacitor. The benefit of forced PWM mode is to keep the switching frequency constant under all load conditions. However, forced-frequency operation diverts a considerable amount of the output current to PGND, reducing the efficiency under light-load conditions. Maxim Integrated Forced-PWM mode is useful for improving load-transient response and eliminating unknown frequency harmonics that can interfere with AM radio bands. Spread Spectrum The MAX16930AGLS/MAX16930AGLU/MAX16931AGLS feature enhanced EMI performance. They perform Q6% dithering of the switching frequency to reduce peak emission noise at the clock frequency and its harmonics, making it easier to meet stringent emission limits. When using an external clock source (i.e., driving the FSYNC input with an external clock), spread spectrum is disabled. Buck 2 Switching Frequency For the MAX16930ATLT and MAX16930ATLU, the switching frequency of buck 2 is set to 1/2 of fSW (buck 1 switching frequency). When using these devices, the external components of buck 2 should be sized to account for the reduced switching frequencies (see the Design Procedure section). MOSFET Gate Drivers (DH_ and DL_) The DH_ high-side n-channel MOSFET drivers are powered from capacitors at BST_ while the low-side drivers (DL_) are powered by the 5V linear regulator (BIAS). On each channel, a shoot-through protection circuit monitors the gate-to-source voltage of the external MOSFETs to prevent a MOSFET from turning on until the complementary switch is fully off. There must be a low-resistance, low-inductance path from the DL_ and DH_ drivers to the MOSFET gates for the protection circuits to work properly. Follow the instructions listed to provide the necessary lowresistance and low-inductance path: • Use very short, wide traces (50 mils to 100 mils wide if the MOSFET is 1in from the driver). It may be necessary to decrease the slew rate for the gate drivers to reduce switching noise or to compensate for low-gate charge capacitors. For the low-side drivers, use gate capacitors in the range of 1nF to 5nF from DL_ to GND. For the high-side drivers, connect a small 5I to 10I resistor between BST_ and the bootstrap capacitor. Note: Gate drivers must be protected during shutdown, at the absence of the supply voltage (VBIAS = 0V) when the gate is pulled high either capacitively or by the leakage path on the PCB. Therefore, external gate pulldown resistors are needed, especially at DL3 to prevent making a direct path from VBAT to GND. 14 MAX16930/MAX16931 2MHz, 36V, Dual Buck with Preboost and 20µA Quiescent Current High-Side Gate-Driver Supply (BST_) The high-side MOSFET is turned on by closing an internal switch between BST_ and DH_ and transferring the bootstrap capacitor’s (at BST_) charge to the gate of the high-side MOSFET. This charge refreshes when the high-side MOSFET turns off and the LX_ voltage drops down to ground potential, taking the negative terminal of the capacitor to the same potential. At this time the bootstrap diode recharges the positive terminal of the bootstrap capacitor. The selected n-channel high-side MOSFET determines the appropriate boost capacitance values (CBST_ in the Typical Operating Circuit) according to the following equation: C BST_ = QG ∆VBST_ where QG is the total gate charge of the high-side MOSFET and DVBST_ is the voltage variation allowed on the high-side MOSFET driver after turn-on. Choose DVBST_ such that the available gate-drive voltage is not significantly degraded (e.g., DVBST_ = 100mV to 300mV) when determining CBST_. The boost capacitor should be a low-ESR ceramic capacitor. A minimum value of 100nF works in most cases. Current Limiting and Current-Sense Inputs (OUT_ and CS_) The current-limit circuit uses differential current-sense inputs (OUT_ and CS_) to limit the peak inductor current. If the magnitude of the current-sense signal exceeds the current-limit threshold (VLIMIT1,2 = 80mV (typ)), the PWM controller turns off the high-side MOSFET. The actual maximum load current is less than the peak currentlimit threshold by an amount equal to half of the inductor ripple current. Therefore, the maximum load capability is a function of the current-sense resistance, inductor value, switching frequency, and duty cycle (VOUT_/VIN). For the most accurate current sensing, use a currentsense shunt resistor (RSH) between the inductor and the output capacitor. Connect CS_ to the inductor side of RSH and OUT_ to the capacitor side. Dimension RSH such that the maximum inductor current (IL,MAX = ILOAD,MAX+1/2 IRIPPLE,PP) induces a voltage of VLIMIT1,2 across RSH including all tolerances. For higher efficiency, the current can also be measured directly across the inductor. This method could cause up to 30% error over the entire temperature range and Maxim Integrated requires a filter network in the current-sense circuit. See the Current-Sense Measurement section. Voltage Monitoring (PGOOD_) The MAX16930/MAX16931 include several power monitoring signals to facilitate power-supply sequencing and supervision. PGOOD_ can be used to enable circuits that are supplied by the corresponding voltage rail, or to turn on subsequent supplies. Each PGOOD_ goes high (high impedance) when the corresponding regulator output voltage is in regulation. Each PGOOD_ goes low when the corresponding regulator output voltage drops below 15% (typ) or rises above 15% (typ) of its nominal regulated voltage. Connect a 10kI (typ) pullup resistor from PGOOD_ to the relevant logic rail to level-shift the signal. PGOOD_ asserts low during soft-start, soft-discharge, and when either buck converter is disabled (either EN1 or EN2 is low). Supply Monitoring (INS) The supply voltage in automotive systems can vary significantly and indicate potentially dangerous situations for the application. Undervoltage transients can indicate impending loss of power (for example during engine-start with a weak battery), while overvoltage conditions can quickly exceed the thermal budget of the application. The devices include a dedicated battery voltage sensor at INS to quickly detect overvoltage and undervoltage for the boost converter. Connect INS to the center tap of a resistive divider from the input voltage (battery) to TERM to set the threshold voltage for VINS,OFF, VINS,ON,SW, and VINS,UV. For example, with a 153kI/±1% resistor between INS and VBAT and a 20kI/±1% resistor between INS and TERM, the following typical automotive VBAT levels can be sensed, allowing for proper turn-on/turn-off of the preboost. If this setting is not sufficient, optimize the divider for the most critical level. SIGNAL VBAT(MIN) (V) VBAT(TYP) (V) VBAT(MAX) (V) VINS,OFF 10.38 10.81 11.25 VINS,ON,SW 9.515 9.95 10.38 VINS,UV Rising 2.81 3.0275 3.24 VINS,UV Falling 2.38 2.6 2.81 15 MAX16930/MAX16931 2MHz, 36V, Dual Buck with Preboost and 20µA Quiescent Current Preboost The MAX16930/MAX16931 include an asynchronous current-mode preboost with adjustable output. This preboost can be used independently, but is ideally suited for applications that need to stay fully functional during input voltage dropouts typical for automotive cold-crank or start-stop. The preboost is turned on by bringing EN3 high. EN3 can be used for power-supply sequencing and implementing a boost timeout to prevent overheating the components used for the boost converter. While the boost circuit is essential to maintain functionality during undervoltage events, it reduces system efficiency. During normal operation, the boost diode dissipates power and the resistive dividers at INS and FB3 sink significant amounts of quiescent current. Increasing the Efficiency of the Boost Circuit (TERM) The MAX16930/MAX16931 provide a feature to improve the efficiency of the boost circuit when it is not active: • TERM provides a switch to GND for the INS and FB3 voltage-dividers. This switch opens during standby mode and shutdown mode to reduce the quiescent current by 240µA, assuming that resistors used in the voltage-divider network are in the range of 100kI. Preboost n-Channel MOSFET Driver (DL3) DL3 drives the gate of an external n-channel MOSFET. The driver is powered by the 5V (typ) internal regulator (BIAS) or the external bypass supply (EVTVCC). DL3 asserts low during standby mode. Switching Frequency in Boost Controller The preboost switching frequency (fBOOST) is derived from the buck controllers switching frequency (fSW) by setting FOSC. See the Electrical Characteristics table. On the MAX16930, fBOOST can be set equal to fSW by connecting FBSTSEL to ground or to 1/5fsu by connecting FBSTSEL Maxim Integrated to BIAS. The gate driver of the preboost turns on simultaneously with the high-side driver of buck 1. FSELBST should be connected to ground on the MAX16931. Current Limit in Boost Controller A current-sense resistor (RCS), connected CS3P and CS3N, sets the current limit of the boost converter. The CS input has a voltage trip level (VCS) of 120mV (typ). The low 120mV current-limit threshold reduces the power dissipation in the current-sense resistor. Use a currentsense filter to reduce capacitive coupling during turn on. See the Shunt Resistor Selection in Boost Converter section. Thermal-Overload, Overcurrent, and Overvoltage and Undervoltage Behavior Thermal-Overload Protection Thermal-overload protection limits total power dissipation in the devices. When the junction temperature exceeds +170NC, an internal thermal sensor shuts down the devices, allowing them to cool. The thermal sensor turns on the devices again after the junction temperature cools by 20NC. Overcurrent Protection If the inductor current on the MAX16930 and MAX16931 exceed the maximum current limit programmed at CS_ and OUT_, the respective driver turns off. In an overcurrent mode, this results in shorter and shorter highside pulses. A hard short results in a minimum on-time pulse every clock cycle. Choose the components so they can withstand the shortcircuit current if required. Overvoltage Protection The devices limit the output voltage of the buck converters by turning off the high-side gate driver at approximately 115% of the regulated output voltage. The output voltage needs to come back in regulation before the high-side gate driver starts switching again. 16 MAX16930/MAX16931 2MHz, 36V, Dual Buck with Preboost and 20µA Quiescent Current Design Procedure Buck Converter Design Procedure Effective Input Voltage Range in Buck Converters Although the MAX16930/MAX16931 can operate from input supplies up to 36V (42V transients) and regulate down to 1V, the minimum voltage conversion ratio (VOUT/ VIN) might be limited by the minimum controllable on-time. For proper fixed-frequency PWM operation and optimal efficiency, buck 1 and buck 2 should operate in continuous conduction during normal operating conditions. For continuous conduction, set the voltage conversion ratio as follows: VOUT VIN > t ON(MIN) × fSW DC output accuracy specifications in the Electrical Characteristics table refer to the error comparator’s threshold, VFB_ = 1V (typ). When the inductor conducts continuously, the devices regulate the peak of the output ripple, so the actual DC output voltage is lower than the slope-compensated trip level by 50% of the output ripple voltage. In discontinuous conduction mode (skip or STDBY active and IOUT < ILOAD(SKIP)), the devices regulate the valley of the output ripple, so the output voltage has a DC regulation level higher than the error-comparator threshold. Inductor Selection in Buck Converters Three key inductor parameters must be specified for operation with the MAX16930/MAX16931: inductance value (L), inductor saturation current (ISAT), and DC resistance (RDCR). To determine the optimum inductance, knowing the typical duty cycle (D) is important. where tON(MIN) is 50ns (typ) and fSW is the switching frequency in Hz. If the desired voltage conversion does VOUT VOUT not meet the above condition, pulse skipping occurs to= D = OR D decrease the effective duty cycle. Decrease the switching VIN VIN − IOUT (R DS(ON) + R DCR ) frequency if constant switching frequency is required. The if the RDCR of the inductor and RDS(ON) of the MOSFET same is true for the maximum voltage conversion ratio. are available with VIN = (VBAT - VDIODE). All values The maximum voltage conversion ratio is limited by the should be typical to optimize the design for normal maximum duty cycle (95%). operation. VOUT Inductance < 0.95 VIN − VDROP The exact inductor value is not critical and can be adjusted in order to make trade-offs among size, cost, where VDROP = IOUT (RON,HS + RDCR) is the sum of the efficiency, and transient response requirements. parasitic voltage drops in the high-side path and fSW is • Lower inductor values increase LIR, which minimizes the programmed switching frequency. During low drop size and cost and improves transient response at the operation, the devices reduce fSW to 25% (max) of the cost of reduced efficiency due to higher peak currents. programmed frequency. In practice, the above condition should be met with adequate margin for good load-tran• Higher inductance values decrease LIR, which sient response. increases efficiency by reducing the RMS current at the cost of requiring larger output capacitors to meet Setting the Output Voltage load-transient specifications. in Buck Converters Connect FB1 and FB2 to BIAS to enable the fixed buck The ratio of the inductor peak-to-peak AC current to DC controller output voltages (5V and 3.3V) set by a preset average current (LIR) must be selected first. A good internal resistive voltage-divider connected between the initial value is a 30% peak-to-peak ripple current to averoutput (OUT_) and AGND. To externally adjust the output age-current ratio (LIR = 0.3). The switching frequency, voltage between 1V and 10V, connect a resistive divider input voltage, output voltage, and selected LIR then from the output (OUT_) to FB_ to AGND (see the Typical determine the inductor value as follows: Operating Circuit. Calculate RFB_1 and RFB_2 with the fol(VIN − VOUT )x D lowing equation: L[µH] = fSW [MHz]x IOUT x LIR VOUT_ R FB_1 R FB_2 = − 1 VFB_ where VIN, VOUT, and IOUT are typical values (so that efficiency is optimum for typical conditions). where V = 1V (typ) (see the Electrical Characteristics table). FB_ Maxim Integrated 17 MAX16930/MAX16931 2MHz, 36V, Dual Buck with Preboost and 20µA Quiescent Current Peak Inductor Current Inductors are rated for maximum saturation current. The maximum inductor current equals the maximum load current in addition to half of the peak-to-peak ripple current: = IPEAK ILOAD(MAX) + ∆IINDUCTOR 2 For the selected inductance value, the actual peak-to-peak inductor ripple current (DIINDUCTOR) is calculated as: VOUT (VIN − VOUT ) ∆IINDUCTOR = VIN x fSW x L where DIINDUCTOR is in mA, L is in µH, and fSW is in kHz. Once the peak current and the inductance are known, the inductor can be selected. The saturation current should be larger than IPEAK or at least in a range where the inductance does not degrade significantly. The MOSFETs are required to handle the same range of current without dissipating too much power. MOSFET Selection in Buck Converters Each step-down controller drives two external logic-level n-channel MOSFETs as the circuit switch elements. The key selection parameters to choose these MOSFETs include the items in the following sections. Threshold Voltage All four n-channel MOSFETs must be a logic-level type with guaranteed on-resistance specifications at VGS = 4.5V. If the internal regulator is bypassed (for example: VEXTVCC = 3.3V), then the n-channel MOSFETS should be chosen to have guaranteed on-resistance at that gate-to-source voltage. Maximum Drain-to-Source Voltage (VDS(MAX)) All MOSFETs must be chosen with an appropriate VDS rating to handle all VIN voltage conditions. Current Capability The n-channel MOSFETs must deliver the average current to the load and the peak current during switching. Choose MOSFETs with the appropriate average current at VGS = 4.5V or VGS = VEXTVCC when the internal linear regulator is bypassed. For load currents below approximately 3A, dual MOSFETs in a single package can be an economical solution. To reduce switching noise for Maxim Integrated smaller MOSFETs, use a series resistor in the BST_ path and additional gate capacitance. Contact the factory for guidance using gate resistors. Current-Sense Measurement For the best current-sense accuracy and overcurrent protection, use a ±1% tolerance current-sense resistor between the inductor and output as shown in Figure 1A. This configuration constantly monitors the inductor current, allowing accurate current-limit protection. Use low-inductance current-sense resistors for accurate measurement. Alternatively, high-power applications that do not require highly accurate current-limit protection can reduce the overall power dissipation by connecting a series RC circuit across the inductor (Figure 1B) with an equivalent time constant: R2 R CSHL = R DCR R1 + R 2 and: R DCR = L C EQ 1 1 + R R2 1 where RCSHL is the required current-sense resistor and RDCR is the inductor’s series DC resistor. Use the inductance and RDCR values provided by the inductor manufacturer. Carefully observe the PCB layout guidelines to ensure the noise and DC errors do no corrupt the differential current-sense signals seen by CS_ and OUT_. Place the sense resistor close to the devices with short, direct traces, making a Kelvin-sense connection to the currentsense resistor. Input Capacitor in Buck Converters The discontinuous input current of the buck converter causes large input ripple currents and therefore the input capacitor must be carefully chosen to withstand the input ripple current and keep the input voltage ripple within design requirements. The 180° ripple phase operation increases the frequency of the input capacitor ripple current to twice the individual converter switching frequency. When using ripple phasing, the worst-case input capacitor ripple current is when the converter with the highest output current is on. 18 MAX16930/MAX16931 2MHz, 36V, Dual Buck with Preboost and 20µA Quiescent Current The input voltage ripple is composed of DVQ (caused by the capacitor discharge) and DVESR (caused by the ESR of the input capacitor). The total voltage ripple is the sum of DVQ and DVESR that peaks at the end of an on-cycle. Calculate the input capacitance and ESR required for a specific ripple using the following equation: ∆VESR ESR[ Ω ] = ∆IP − P ILOAD(MAX) + 2 V ILOAD(MAX) x OUT VIN CIN [µF] = (∆VQ x fSW ) where: (VIN − VOUT ) x VOUT ∆IP −P = VIN x fSW x L ILOAD(MAX) is the maximum output current in A, DIP-P is the peak-to-peak inductor current in A, fSW is the switching frequency in MHz, and L is the inductor value in µH. The internal 5V linear regulator (BIAS) includes an output UVLO with hysteresis to avoid unintentional chattering during turn-on. Use additional bulk capacitance if the input source impedance is high. At lower input voltage, additional input capacitance helps avoid possible undershoot below the undervoltage lockout threshold during transient loading. INPUT (VIN) CIN MAX16930/ MAX16931 DH_ NH RSENSE L LX_ DL_ COUT NL GND CS_ OUT_ A) OUTPUT SERIES RESISTOR SENSING INPUT (VIN) CIN MAX16930/ MAX16931 DH_ NH INDUCTOR L DCR R1 R2 LX_ DL_ NL GND CS_ OUT_ CEQ COUT RCSHL = RDCR = ( ) [ ] R2 R R1 + R2 DCR L 1 + 1 CEQ R1 R2 B) LOSSLESS INDUCTOR SENSING Figure 1. Current-Sense Configurartions Maxim Integrated 19 MAX16930/MAX16931 2MHz, 36V, Dual Buck with Preboost and 20µA Quiescent Current Output Capacitor in Buck Converters The actual capacitance value required relates to the physical size needed to achieve low ESR, as well as to the chemistry of the capacitor technology. The capacitor is usually selected by ESR and the voltage rating rather than by capacitance value. When using low-capacity filter capacitors, such as ceramic capacitors, size is usually determined by the capacity needed to prevent VSAG and VSOAR from causing problems during load transients. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the Transient Considerations section). However, low-capacity filter capacitors typically have high-ESR zeros that can affect the overall stability. The total voltage sag (VSAG) can be calculated as follows: VSAG = L( ∆ILOAD(MAX) ) 2 2C OUT ((VIN × D MAX ) − VOUT ) + ∆ILOAD(MAX) (t − ∆t) C OUT The amount of overshoot (VSOAR) during a full-load to no-load transient due to stored inductor energy can be calculated as: ( ∆ILOAD(MAX) ) 2 L VSOAR ≈ 2C OUT VOUT ESR Considerations The output filter capacitor must have low enough equivalent series resistance (ESR) to meet output ripple and load-transient requirements, yet have high enough ESR to satisfy stability requirements. When using high-capacitance, low-ESR capacitors, the filter capacitor’s ESR dominates the output-voltage ripple. So the output capacitor’s size depends on the maximum ESR required to meet the output-voltage ripple (VRIPPLE(P-P)) specifications: VRIPPLE(P −P) = ESR x ILOAD(MAX) x LIR Maxim Integrated In standby mode, the inductor current becomes discontinuous, with peak currents set by the idle-mode currentsense threshold (VCS,SKIP = 26mV (typ)). Transient Considerations The output capacitor must be large enough to absorb the inductor energy while transitioning from no-load to full-load condition without tripping the overvoltage fault protection. The total output-voltage sag is the sum of the voltage sag while the inductor is ramping up and the voltage sag before the next pulse can occur. Therefore: ( ) 2 L ∆ILOAD(MAX) C OUT = 2VSAG (VIN x D MAX − VOUT ) + ∆ILOAD(MAX) (t − ∆t) VSAG where DMAX is the maximum duty factor (approximately 95%), L is the inductor value in µH, COUT is the output capacitor value in µF, t is the switching period (1/fSW) in µs, and Dt equals (VOUT/VIN) x t. The MAX16930/MAX16931 use a current-mode control scheme that regulates the output voltage by forcing the required current through the external inductor, so the controller uses the voltage drop across the DC resistance of the inductor or the alternate series currentsense resistor to measure the inductor current. Currentmode control eliminates the double pole in the feedback loop caused by the inductor and output capacitor resulting in a smaller phase shift and requiring less elaborate error-amplifier compensation than voltage-mode control. A single series resistor (RC) and capacitor (CC) is all that is required to have a stable, high-bandwidth loop in applications where ceramic capacitors are used for output filtering (see Figure 2). For other types of capacitors, due to the higher capacitance and ESR, the frequency of the zero created by the capacitance and ESR is lower than the desired closed-loop crossover frequency. To stabilize a non-ceramic output capacitor loop, add another compensation capacitor (CF) from COMP to AGND to cancel this ESR zero. 20 MAX16930/MAX16931 2MHz, 36V, Dual Buck with Preboost and 20µA Quiescent Current The output capacitor and its ESR also introduce a zero at: gmc = 1/(AVCS x RDC) fzMOD = CS_ CURRENT MODE POWER MODULATION OUT_ R1 RESR COUT When COUT is composed of “n” identical capacitors in parallel, the resulting COUT = nxCOUT(EACH), and ESR = ESR(EACH) /n. Note that the capacitor zero for a parallel combination of alike capacitors is the same as for an individual capacitor. gmea = 1200µS FB_ COMP_ ERROR AMP R2 VREF 30MI RC CF CC Figure 2. Compensation Network The basic regulator loop is modeled as a power modulator, output feedback divider, and an error amplifier as shown in Figure 2. The power modulator has a DC gain set by gmc x RLOAD, with a pole and zero pair set by RLOAD, the output capacitor (COUT), and its ESR. The loop response is set by the following equations: GAINMOD(dc) = g mc × R LOAD where RLOAD = VOUT/ILOUT(MAX) in I and gmc =1/(AV_ CS x RDC) in S. AV_CS is the voltage gain of the currentsense amplifier and is typically 11V/V. RDC is the DC resistance of the inductor or the current-sense resistor in I. In a current-mode step-down converter, the output capacitor and the load resistance introduce a pole at the following frequency: fpMOD = 1 2π × C OUT × R LOAD The unity gain frequency of the power stage is set by COUT and gmc: fUGAINpMOD = Maxim Integrated g mc 2π × C OUT 1 2π × ESR × C OUT The feedback voltage-divider has a gain of GAINFB = VFB / VOUT, where VFB is 1V (typ). The transconductance error amplifier has a DC gain of GAINEA(DC) = gm,EA x ROUT,EA, where gm,EA is the error amplifier transconductance, which is 1200µS (typ), and ROUT,EA is the output resistance of the error amplifier, which is 30MI (typ) (see the Electrical Characteristics table.) A dominant pole (fdpEA) is set by the compensation capacitor (CC) and the amplifier output resistance (ROUT,EA). A zero (fZEA) is set by the compensation resistor (RC) and the compensation capacitor (CC). There is an optional pole (fPEA) set by CF and RC to cancel the output capacitor ESR zero if it occurs near the crossover frequency (fC, where the loop gain equals 1 (0dB)). Thus: fdpEA = 1 2π × C C × (R OUT,EA + R C ) fzEA = 1 2π × C C × R C fpEA = 1 2π × C F × R C The loop-gain crossover frequency (fC) should be set below 1/5th of the switching frequency and much higher than the power-modulator pole (fpMOD). Select a value for fC in the range: f fpMOD << fC ≤ SW 5 21 MAX16930/MAX16931 2MHz, 36V, Dual Buck with Preboost and 20µA Quiescent Current At the crossover frequency, the total loop gain must be equal to 1. So: GAINMOD(f ) × C VFB × GAINEA(f ) = 1 C VOUT fSW = 26.4/65.5kI = 0.403MHz GAINMOD(dc) = 6.06 × 0.9375 = 5.68 = fpMOD GAINEA(f = ) g m,EA × R C fpMOD f fpMOD << fC ≤ SW 5 fC 1.8kHz << fC ≤ 80.6kHz C GAIN = MOD(fC ) GAINMOD(dc) × 1 ≈ 1.8kHz 2π × 94µF × 0.9375 Therefore: select fC = 40kHz GAINMOD(f ) × C VFB VOUT × g m,EA × R C = 1 Solving for RC: RC = VOUT g m,EA × VFB × GAINMOD(f ) C Set the error-amplifier compensation zero formed by RC and CC at the fpMOD. Calculate the value of CC as follows: CC = 1 2π × fpMOD × R C If fzMOD is less than 5 x fC, add a second capacitor CF from COMP to AGND. The value of CF is: CF = 1 2π × fzMOD × R C As the load current decreases, the modulator pole also decreases; however, the modulator gain increases accordingly and the crossover frequency remains the same. Below is a numerical example to calculate the compensation network component values of Figure 2: AV_CS = 11V/V RDCR = 15mI = fzMOD 1 ≈ 376kHz 2π × 4.5mΩ × 94µF since fzMOD>fC: RC ≈ 16kI CC ≈ 5.6nF CF ≈ 27pF Boost Converter Design Procedure Setting the Output Voltage in Boost Converter Adjust the boost converter output voltage by connecting a resistive divider from the output of the boost converter to FBBST to TERM (Figure 3) and RB2 (FB3 to TERM resistor). Calculate RB1 (VOUT(BOOST) to FBBST resistor) using the following equation: VOUT(BOOST ) R B1 R B2 = − 1 VFB3 where VFB3 = 1.2V (typ) (see the Electrical Characteristics table). VOUT(BOOST) RB1 MAX16930/ MAX16931 FB3 gmc = 1/(AV_CS x RDC) = 1/(11 x 0.015) = 6.06 RB2 VOUT = 5V IOUT(MAX) = 5.33A RLOAD = VOUT /IOUT(MAX) = 5V/5.33A = 0.9375I COUT = 2x47µF = 94µF ESR = 9mI/2 = 4.5mI Maxim Integrated TERM Figure 3. Boost Converter Adjustable Output Voltage 22 MAX16930/MAX16931 2MHz, 36V, Dual Buck with Preboost and 20µA Quiescent Current Inductor Selection in Boost Converter Duty cycle and frequency are important to calculate the inductor size, as the inductor current ramps up during the on-time of the switch and ramps down during its offtime. A higher switching frequency generally improves transient response and reduces component size. However, if the boost components are to be used as the input filter components during nonboost operation, a low frequency is advantageous. The boost frequency is selected as a multiple of the buck frequency by setting the input voltage of FSELBST. • If VFSELBST =VGND, then fBOOST = fSW • If VFSELBST = VBIAS, then fBOOST = 1/5fSW The duty-cycle range of the boost converter depends on the effective input to output-voltage ratio. In the following calculations, the duty cycle refers to the on-time of the boost MOSFET: D MAX = VOUT(MAX) − VBAT(MIN) VOUT(MAX) or including the voltage drops across the inductor, MOSFET (VON,FET), and the boost diode (VD): D MAX = VOUT(MAX) − VBAT(MIN) + VD + (IOUT xR DC ) VOUT(MAX) In some applications, it may be beneficial to maintain discontinuous conduction (DCM) in the boost converter under all conditions. This formula defines the maximum size of the inductor for DCM mode: LMAX < VIN(MIN) x DMAX /(2 x (IOUT(MAX)/1 - DMAX)) x fSW(MIN) The ratio of the inductor peak-to-peak AC current to DC average current (LIR) must be selected first. A good initial value is a 30% peak-to-peak ripple current to average-current ratio (LIR = 0.3). The switching frequency, input voltage, output voltage, and selected LIR determine the inductor value as follows: L[µH] = VIN × D fSW [MHz] × LIR where: VIN = Typical input voltage VOUT = Typical output voltage LIR = 0.3 x IOUT/1 - D. Maxim Integrated Select the inductor with a saturation current rating higher than the peak switch current limit of the converter: IL,PEAK > IL,MAX + ∆IL,RIP,MAX 2 Running a boost converter in continuous conduction mode introduces a right-half plane zero into the transfer function, which can only be compensated by reducing bandwidth in the voltage feedback loop by adding a capacitor across the low-side feedback resistor. This results in a system that is slow to respond to load and line changes. If the boost converter response is too slow, increase the ripple current. A smaller inductor and higher frequency generally improves the preboost, especially for high input to output ratios. MOSFET Selection in Boost Converter The key selection parameters to choose the n-channel MOSFET used in the boost converter are as follows. Threshold Voltage The boost n-channel MOSFETs must be a logic-level type with guaranteed on-resistance specifications at VGS = 4.5V. Maximum Drain-to-Source Voltage (VDS(MAX)) The MOSFET must be chosen with an appropriate VDS rating to handle all VIN voltage conditions. Current Capability The n-channel MOSFET must deliver the input current (IIN(MAX)): IIN(MAX) = ILOAD(MAX) x D MAX 1 − D MAX Choose MOSFETs with the appropriate average current at VGS = 4.5V. Diode Selection in Boost Converter The diode must deliver the average output current (IOUT) plus the peak inductor current (ILPEAK). The boost diode current can be higher during nonboost operation when it supplies current to both buck converters under full-load conditions. Use a boost diode with a power dissipation of P = IOUT x VDIODE or higher. To reduce the power dissipation, use a Schottky diode. 23 MAX16930/MAX16931 2MHz, 36V, Dual Buck with Preboost and 20µA Quiescent Current Input Capacitor Selection in Boost Converter The input current for the boost converter is continuous and the RMS ripple current at the input capacitor is low. Calculate the minimum input capacitor value and maximum ESR using the following equations: C BAT = ∆IL x D 4 x fSW x ∆VQ ESR = ∆VESR ∆IL where: (V − VDS ) x D ∆IL = BAT L x fSW VDS is the total voltage drop across the external MOSFET plus the voltage drop across the inductor ESR. DIL is peak-to-peak inductor ripple current as calculated above. DVQ is the portion of input ripple due to the capacitor discharge and DVESR is the contribution due to ESR of the capacitor. Assume the input capacitor ripple contribution due to ESR (DVESR) and capacitor discharge (DVQ) are equal when using a combination of ceramic and aluminum capacitors. During the converter turn-on, a large current is drawn from the input source especially at high output-to-input differential. Output Capacitor Selection in Boost Converter In a boost converter, the output capacitor supplies the load current when the boost MOSFET is on. The required output capacitance is high, especially at higher duty cycles. Also, the output capacitor ESR needs to be low enough to minimize the voltage drop while supporting the load current. Use the following equations to calculate the output capacitor for a specified output ripple. All ripple values are peak-to-peak. Maxim Integrated ESR = ∆VESR IOUT I x D MAX C OUT = OUT ∆VQ x fSW IOUT is the load current in A, fSW is in MHz, COUT is µF, DVQ is the portion of the ripple due to the capacitor discharge, and DVESR is the contribution due to the ESR of the capacitor. DMAX is the maximum duty cycle at the minimum input voltage. Use a combination of low-ESR ceramic and high-value, low-cost aluminum capacitors for lower output ripple and noise. Shunt Resistor Selection in Boost Converter The current-sense resistor (RCS), connected between the battery and the inductor, sets the current limit. The CS input has a voltage trip level (VCS) of 120mV (typ). Set the current-limit threshold high enough to accommodate the component variations. Use the following equation to calculate the value of RCS: R CS = VCS IIN(MAX) where IIN(MAX) is the peak current that flows through the MOSFET at full load and minimum VIN. IIN(MAX) = ILOAD(MAX) /(1 - DMAX) When the voltage produced by this current (through the current-sense resistor) exceeds the current-limit comparator threshold, the MOSFET driver (DL3) quickly terminates the on-cycle. 24 MAX16930/MAX16931 2MHz, 36V, Dual Buck with Preboost and 20µA Quiescent Current Applications Information Layout Recommendations Careful PCB layout is critical to achieve low switching losses and clean, stable operation. The switching power stage requires particular attention (Figure 4). If possible, mount all the power components on the top side of the board, with their ground terminals flush against one another. Follow these guidelines for good PCB layout: • Keep the high-current paths short, especially at the ground terminals. This practice is essential for stable, jitter-free operation. • Keep the power traces and load connections short. This practice is essential for high efficiency. Using thick copper PCBs (2oz vs. 1oz) can enhance full load efficiency by 1% or more. • Minimize current-sensing errors by connecting CS_ and OUT_. Use kelvin sensing directly across the current-sense resistor (RSENSE_). • Route high-speed switching nodes (BST_, LX_, DH_, and DL_) away from sensitive analog areas (FB_, CS_, and OUT_). Layout Procedure 1)Place the power components first, with ground terminals adjacent (low-side FET, CIN, COUT_, and schottky). If possible, make all these connections on the top layer with wide, copper-filled areas. 2)Mount the controller IC adjacent to the low-side MOSFET, preferably on the back side opposite NL_ and NH_ to keep LX_, GND, DH_, and the DL_ gate drive lines short and wide. The DL_ and DH_ gate traces must be short and wide (50 mils to 100 mils wide if the MOSFET is 1in from the controller IC) to keep the driver impedance low and for proper adaptive dead-time sensing. 3)Group the gate-drive components (BST_ diode and capacitor and LDO bypass capacitor BIAS) together near the controller IC. Be aware that gate currents of up to 1A flow from the bootstrap capacitor to BST_, from DH_ to the gate of the external HS switch and from the LX_ pin to the inductor. Up to 100mA of current flow from the BIAS capacitor through the bootstrap diode to the bootstrap capacitor. Dimension those traces accordingly. 4)Make the DC-DC controller ground connections as shown in Figure 4. This diagram can be viewed as having two separate ground planes: power ground, where all the high-power components go; and an analog ground plane for sensitive analog components. The analog ground plane and power ground plane must meet only at a single point directly under the IC. 5) Connect the output power planes directly to the output filter capacitor positive and negative terminals with multiple vias. Place the entire DC-DC converter circuit as close to the load as is practical. KELVIN-SENSE VIAS UNDER THE SENSE RESISTOR (REFER TO THE EVALUATION KIT) INDUCTOR LOW-SIDE n-CHANNEL MOSFET (NH) COUT CIN COUT HIGH-SIDE n-CHANNEL MOSFET (NL) INPUT OUTPUT GROUND Figure 4. Layout Example Maxim Integrated 25 MAX16930/MAX16931 2MHz, 36V, Dual Buck with Preboost and 20µA Quiescent Current Block Diagram PGOOD1 COMP1 DC-DC1 CONTROL LOGIC PGOOD LOW LEVEL PGOOD HIGH LEVEL PGOOD COMP FB1 FEEDBACK SELECT LOGIC EAMP1 INTERNAL SOFT START MAX16930 EN1 REF = 1V OUT1 PWM1 80 mV(TYP) MAX DIFFERENTIAL INPUT CSA1 CLK1 CS1 ZX1 CL SLOPE COMP LOGIC EN1 GATE DRIVE LOGIC DL1 PGND1 LX1 VIN SPREAD SPECTRUM OPTION AVAILABLE WITH INTERNAL CLOCK ONLY EXTERNAL CLOCK INPUT BIAS INTERNAL LINEAR REGULATOR TIED HIGH (PWM MODE) FSYNC SELECT LOGIC LX1 CLK1 OSCILLATOR FSYNC DH1 STEP-DOWN DC-DC1 ZERO CROSS COMP CURRENT LIMIT THRESHOLD LX1 FOSC BST1 PWM1 TIED LOW (SKIP MODE) SWITCHOVER AGND BIAS IF 3.1V < VEXTVCC < 5.2V EXTVCC CLK 180° OUT OF PHASE CLK2 EN2 COMP2 BST2 PWM2 FB2 CLK2 OUT2 DC-DC2 CONTROL LOGIC SAME AS DC-DC1 ABOVE CS2 EN2 DH2 STEP-DOWN DC-DC2 ZX2 GATE DRIVE LOGIC PGOOD2 LX2 LX2 DL2 PGND2 LX2 CLK1 FSELBST TIED LOW FSELBST INPUT IF LOW, CLK3 = CLK1 TIED HIGH IF HIGH, CLK3 = CLK1/5 BOOST ENABLED INS START-UP TURN ON THRESHOLD BOOST ON-OFF THRESHOLDS VIN PRE-BST SNS THRESHOLD COMPARATOR PWM3 CLK3 EN GOES HIGH BSTON BOOST EN FLAG CHECK FOR INS THRESHOLDS GATE DRIVE LOGIC DL3 BOOST ENABLED IN SLOPE COMP LOGIC CS3P CS3N STEP-UP DC-DC3 CLK3 UVLO THRESHOLD EN3 PGND3 BIAS 50 mV(TYP) MAX DIFFERENT INPUT CSA3 CURRENT LIMIT THRESHOLD FB3 REF3 = 1.25V EAMP3 CL3 PWM3 LOW GAIN EAMP, NO COMP PIN REQUIRED DC-DC3 CONTROL LOGIC TERM EN3 EP Maxim Integrated 26 MAX16930/MAX16931 2MHz, 36V, Dual Buck with Preboost and 20µA Quiescent Current Typical Operating Circuit BIAS OUT1 BIAS PGOOD2 EXTVCC FB2 CS2 OUT2 COMP2 N.C. FSYNC FOSC AGND BIAS OUT1 EN2 CS1 DH2 FB1 LX2 COMP1 IN OUT1 OUT2 BST2 MAX16930 MAX16931 PGOOD1 DL2 DH1 PGND2 LX1 N.C. BST1 BSTON DL1 FSELBST VBAT IN EN3 PGND3 FB3 CS3N CS3P TERM INS IN PGND1 DL3 BIAS EN1 IN TERM Maxim Integrated IN TERM 27 MAX16930/MAX16931 2MHz, 36V, Dual Buck with Preboost and 20µA Quiescent Current Selector Guide BUCK 1 SWITCHING FREQUENCY (fSW1) BUCK 2 SWITCHING FREQUENCY (fSW2) SPREAD SPECTRUM (%) MAX16930ATLR/V+ 1MHz to 2.2MHz fSW1 — MAX16930ATLS/V+ 1MHz to 2.2MHz fSW1 6 MAX16930ATLT/V+ 1MHz to 2.2MHz 1/2fSW1 — MAX16930ATLU/V+ 1MHz to 2.2MHz 1/2fSW1 6 MAX16931ATLR/V+ 200kHz to 1MHz fSW1 — MAX16931ATLS/V+ 200kHz to 1MHz fSW1 6 PART Ordering Information PART TEMP RANGE PIN-PACKAGE MAX16930ATL_/V+ -40°C to +125°C 40 TQFN-EP** MAX16931ATL_/V+* -40°C to +125°C 40 TQFN-EP** Note: Insert the desired suffix letter (from Selector Guide) into the blank to indicate buck 2 switching frequency and spread spectrum. /V denotes an automotive qualified part. +Denotes a lead(Pb)-free/RoHS-compliant package. *Future product. **Exposed pad side-wettable flanked package. Package Information For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 40 TQFN-EP T4066+5 21-0141 90-0055 Chip Information PROCESS: BiCMOS Maxim Integrated 28 MAX16930/MAX16931 2MHz, 36V, Dual Buck with Preboost and 20µA Quiescent Current Revision History REVISION NUMBER REVISION DATE 0 7/13 DESCRIPTION Initial release PAGES CHANGED — Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 © 2013 Maxim Integrated Products, Inc. 29 Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.