MAXIM MAX8716ETG

19-3569; Rev 1; 6/05
KIT
ATION
EVALU
E
L
B
AVAILA
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
Applications
2 to 4 Li+ Cell Battery-Powered Devices
Notebook and Subnotebook Computers
PDAs and Mobile Communicators
Main or I/O Power Supplies
Features
♦ Fixed 200kHz, 300kHz, or 500kHz Switching
Frequency
♦
♦
♦
♦
No Current-Sense Resistor Required
40/60 Optimal Interleaving
Reduced Input-Capacitor Requirement
3.3V and 5V fixed or 1.0V to 5.5V Adjustable
Outputs (Dual Mode™)
♦ 4V to 26V Input Range
♦ Independently Selectable PWM, Skip, and LowNoise Mode Operation
♦ Soft-Start and Soft-Stop
♦ 2V Precision Reference with 0.75% Accuracy
♦ Independent Power-Good Outputs
Ordering Information
TEMP RANGE
PIN-PACKAGE
MAX8716ETG
PART
-40°C to +85°C
24 Thin QFN 4mm x 4mm
MAX8716ETG+
-40°C to +85°C
24 Thin QFN 4mm x 4mm
MAX8717ETI
-40°C to +85°C
28 Thin QFN 5mm x 5mm
MAX8717ETI+
-40°C to +85°C
28 Thin QFN 5mm x 5mm
MAX8757ETI+
-40°C to +85°C
28 Thin QFN 5mm x 5mm
+Denotes lead-free package.
Dual Mode is a trademark of Maxim Integrated Products, Inc.
TOP VIEW
LX1
DL1
GND
VDD
DL2
LX2
LX1
DL1
AGND
PGND
VDD
DL2
LX2
TOP VIEW
18
17
16
15
14
13
21
20
19
18
17
16
15
19
BST1
20
CSH1
21
CSL1
22
FB1
PGOOD1
12
11
DH1
22
14
DH2
BST1
23
13
BST2
DH2
BST2
10
CSH2
CSH1
24
12
CSH2
9
CSL2
CSL1
25
11
CSL2
23
8
FB2
FB1
26
10
FB2
24
7
PGOOD2
PGOOD1
27
9
PGOOD2
ILIM1
28
8
ILIM2
SKIP2
ON1
ON2
2
3
4
5
6
7
ON2
REF
TQFN
1
ON1
6
FSEL
5
REF
4
SKIP2
3
VCC
2
MAX8717ETI
MAX8757ETI+
SKIP1
1
VCC
MAX8716ETG
SKIP1
DH1
Pin Configurations
TQFN
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX8716/MAX8717/MAX8757
General Description
The MAX8716/MAX8717/MAX8757 are dual, stepdown, interleaved, fixed-frequency, switch-mode
power-supply (SMPS) controllers with synchronous rectification. They are intended for main (5V/3.3V) and I/O
power generation in battery-powered systems.
Fixed-frequency operation with optimal interleaving
minimizes input ripple current from the lowest input voltages up to the 26V maximum input. Optimal 40/60 interleaving allows the input voltage to go down to 8.3V
before duty-cycle overlap occurs, compared to 180°
out-of-phase regulators where the duty-cycle overlap
occurs when the input drops below 10V.
Accurate output current limit is achieved using a sense
resistor. Alternatively, power dissipation can be
reduced using lossless inductor current sensing.
Independent ON/OFF controls and power-good signals
allow flexible power sequencing. Soft-start reduces
inrush current, while soft-stop gradually ramps the output voltage down preventing negative voltage dips.
A low-noise mode maintains high light-load efficiency
while keeping the switching frequency out of the audible range.
The MAX8716 is available in a 24-pin thin QFN package, and the MAX8717/MAX8757 are available in a 28pin thin QFN package.
MAX8716/MAX8717/MAX8757
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
ABSOLUTE MAXIMUM RATINGS (Note 1)
VDD, VCC, CSL1, CSH1, CSL2, CSH2 to AGND ......-0.3V to +6V
ON1, ON2, SKIP1, SKIP2, PGOOD1,
PGOOD2 to AGND ...............................................-0.3V to +6V
FB1, FB2, ILIM1, ILIM2, FSEL to AGND ...................-0.3V to +6V
REF to AGND..............................................-0.3V to (VCC + 0.3V)
BST1, BST2 to AGND .............................................-0.3V to +36V
LX1 to BST1..............................................................-6V to +0.3V
LX2 to BST2..............................................................-6V to +0.3V
DH1 to LX1 ..............................................-0.3V to (VBST1 + 0.3V)
DH2 to LX2 ..............................................-0.3V to (VBST2 + 0.3V)
DL1, DL2 to PGND .....................................-0.3V to (VDD + 0.3V)
AGND to PGND .....................................................-0.3V to +0.3V
REF Short Circuit to AGND.........................................Continuous
REF Current ......................................................................+10mA
Continuous Power Dissipation (TA = +70°C)
24-Pin Thin QFN 4mm x 4mm (derate 20.8mW/°C
above +70°C)..........................................................1666.7mW
28-Pin Thin QFN 5mm x 5mm (derate 21.3mW/°C
above +70°C)..........................................................1702.1mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Note 1: For the 24-pin TQFN version, AGND and PGND refer to a single pin designated GND.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VIN = 12V, FSEL = REF, SKIP_ = 0, VON_ = VILIM_ = VCC = VDD = 5V, TA = 0°C to +85°C, unless otherwise noted.
Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
INPUT SUPPLIES
Input Voltage Range
VIN
26
VCC, VDD
4.5
3.9
3.7
Shutdown Supply Current (VCC)
VCC rising
200mV typical
hysteresis
VCC falling
CSL_ and FB_ forced above their regulation
points
CSL_ and FB_ forced above their regulation
points
ON1 = ON2 = GND
Shutdown Supply Current (VDD)
ON1 = ON2 = GND
VCC Undervoltage-Lockout
Threshold
VBIAS
VUVLO
Quiescent Supply Current (VCC)
ICC
Quiescent Supply Current (VDD)
IDD
5.5
V
4.15
3.95
4.4
4.2
V
0.8
1.3
mA
<1
5
µA
<1
5
µA
<1
5
µA
3.265
3.30
3.365
V
4.94
5.00
5.09
V
0.990
1.005
1.020
0.995
1.005
1.015
MAIN SMPS CONTROLLERS
PWM1 Output Voltage in Fixed
Mode
PWM2 Output Voltage in Fixed
Mode
Feedback Voltage in Adjustable
Mode (Note 2)
Output-Voltage Adjust Range
VOUT1
VOUT2
VFB_
VIN = 6V to 26V, SKIP1 = VCC,
zero to full load (Note 2)
VIN = 6V to 26V, SKIP2 = VCC,
zero to full load (Note 2)
VIN = 6V to 26V, FB1 or FB2,
duty factor = 20% to 80%
VIN = 6V to 26V, FB1 or FB2,
duty factor = 50%
Either SMPS
V
1.0
5.5
V
2.1
V
+0.1
µA
FB1, FB2 Fixed-Mode Threshold
Voltage
Dual-mode comparator
1.9
Feedback Input Leakage Current
FB1 = 1.1V, FB2 = 1.1V
-0.1
DC Load Regulation
Either SMPS, SKIP_ = VCC, zero to full load
2
-0.1
_______________________________________________________________________________________
%
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
(Circuit of Figure 1, VIN = 12V, FSEL = REF, SKIP_ = 0, VON_ = VILIM_ = VCC = VDD = 5V, TA = 0°C to +85°C, unless otherwise noted.
Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
Line-Regulation Error
IFB_
Operating Frequency
fOSC
Minimum On-Time
MIN
Either SMPS, 4V < VIN < 26V
FB_ Input Bias Current
Maximum Duty Factor
CONDITIONS
DMAX
tON(MIN)
SMPS1 to SMPS2 Phase Shift
TYP
MAX
0.03
%/V
VFB_ = 0 to 5.5V
-0.1
+0.1
FSEL = GND
170
200
230
FSEL = REF (Note 3)
270
300
330
FSEL = VCC
425
500
575
FSEL = GND
97.5
99
FSEL = REF (Note 3)
97.5
99
FSEL = VCC
97.5
99
(Note 4)
µA
kHz
%
200
SMPS2 starts after SMPS1
UNITS
ns
40
%
144
Degrees
Soft-Start Ramp Time
tSSTART
Measured from the rising edge of ON_ to full
scale, REF = 2V
2
ms
Soft-Stop Ramp Time
tSSTOP
Measured from the falling edge of ON_ to full
scale
4
ms
CURRENT LIMIT
ILIM_ Adjustment Range
Current-Limit Threshold (Fixed)
Current-Limit Threshold
(Adjustable)
Current-Limit Threshold
(Negative)
Current-Limit Threshold (Zero
Crossing)
0.5
VLIMIT_
VLIMIT_
VCSH_ - VCSL _, ILIM_ = VCC (Note 3)
VCSH_ - VCSL _
VZX
50
55
200
210
VILIM_ = 1.00V
94
100
106
-67
-60
-53
VCSH_ - VCSL _, SKIP_ = GND or REF
ILIM_ = VCC (Note 3)
Idle Mode™ Threshold
VIDLE
VLN
VCSH_ - VCSL_
SKIP_ = REF
6
With respect to
current-limit
threshold
ILIM_ = VCC (Note 3)
Low-Noise Mode Threshold
mV
45
190
VCSH_ - VCSL _, SKIP_ = VCC, adjustable
mode, percent of current limit
VCSH_ - VCSL _,
SKIP_ = GND
V
VILIM_ = 2.00V
VCSH_ - VCSL _, SKIP_ = ILIM_ = VCC
(Note 3)
VNEG
VREF
2.5
mV
-120
%
3
mV
10
14
20
With respect to
current-limit
threshold
mV
5
%
7.5
10
ILIM_ Leakage Current
mV
mV
%
0.1
µA
REFERENCE (REF)
Reference Voltage
VREF
VCC = 4.5V to 5.5V,
IREF = 0
TA = +25°C to
+85°C
1.985
2.00
2.015
TA = 0°C to +85°C
1.98
2.00
2.02
V
Idle Mode is a trademark of Maxim Integrated Products, Inc.
_______________________________________________________________________________________
3
MAX8716/MAX8717/MAX8757
ELECTRICAL CHARACTERISTICS (continued)
MAX8716/MAX8717/MAX8757
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 12V, FSEL = REF, SKIP_ = 0, VON_ = VILIM_ = VCC = VDD = 5V, TA = 0°C to +85°C, unless otherwise noted.
Typical values are at TA = +25°C.)
PARAMETER
Reference Load Regulation
SYMBOL
∆VREF
CONDITIONS
TYP
IREF = 0µA to 50µA
Reference Sink Current
REF Lockout Voltage
MIN
MAX
UNITS
10
mV
10
VREF(UVLO) Rising edge, hysteresis = 50mV
µA
1.8
V
FAULT DETECTION
Output Overvoltage Trip
Threshold
Output Overvoltage FaultPropagation Delay
Output Undervoltage-Protection
Trip Threshold
Output Undervoltage FaultPropagation Delay
Output Undervoltage-Protection
Blanking Time
MAX8716/MAX8717 only
tOVP
tBLANK
tPGOOD_
PGOOD_ Output Low Voltage
PGOOD_ Leakage Current
Thermal-Shutdown Threshold
15
65
From rising edge of ON_
-12.5
Falling edge, 50mV overdrive
70
TSHDN
µs
75
%
µs
6144
1/fOSC
-10
-8.0
10
High state, PGOOD_ forced to 5.5V
Hysteresis = 15°C
%
10
ISINK = 4mA
IPGOOD_
19
10
50mV overdrive
With respect to error-comparator threshold,
hysteresis = 1%
PGOOD_ Lower Trip Threshold
PGOOD_ Propagation Delay
50mV overdrive, MAX8716/MAX8717 only
With respect to error-comparator threshold
tUVP
11
%
µs
0.4
V
1
µA
+160
°C
GATE DRIVERS
DH_ Gate-Driver On-Resistance
RDH
DL_ Gate-Driver On-Resistance
RDL
DH_ Gate-Driver Source/Sink
Current
IDH
DL_ Gate-Driver Source Current
IDL
BST_ - LX_ forced to 5V (Note 5)
1.5
5
DL_, high state (Note 5)
1.7
5
DL_, low state (Note 5)
0.6
3
DH_ forced to 2.5V, BST_ - LX_ forced to
5V
Ω
Ω
2
A
DL_ forced to 2.5V
1.7
A
DL_ forced to 2.5V
3.3
A
DL_ rising
35
DH_ rising
26
VBST_ = VLX_ = 26V
<2
20
µA
+1
µA
1.7
2.2
V
2.3
V
(SOURCE)
DL_ Gate-Driver Sink Current
Dead Time
LX_, BST_ Leakage Current
IDL (SINK)
tDEAD
ns
INPUTS AND OUTPUTS
Logic Input Current
ON1, ON2
-1
ON_ Input Voltage
Rising edge, hysteresis = 225mV
1.2
High
Tri-Level Input Logic
SKIP1, SKIP2, FSEL
REF
VCC 0.2
1.7
GND
4
_______________________________________________________________________________________
0.5
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
(Circuit of Figure 1, VIN = 12V, FSEL = REF, SKIP_ = 0, VON_ = VILIM_ = VCC = VDD = 5V, TA = 0°C to +85°C, unless otherwise noted.
Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Leakage Current
SKIP1, SKIP2, FSEL, 0V, or VCC
-3
+3
µA
Input Leakage Current
ILIM1, ILIM2, 0V, or VCC
-0.1
+0.1
µA
Input Leakage Current
CSH_, 0V, or VDD
-0.1
+0.1
µA
Input Bias Current
CSL_, 0V, or VDD
50
µA
25
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VIN = 12V, FSEL = REF, SKIP_ = 0, VON_ = VILIM_ = VCC = VDD = 5V, TA = -40°C to +85°C, unless otherwise
noted.) (Note 6)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
INPUT SUPPLIES
Input Voltage Range
VIN
VBIAS
26
VCC, VDD
4.5
5.5
V
Quiescent Supply Current (VCC)
ICC
CSL_ and FB_ forced above their regulation
points
1.3
mA
Quiescent Supply Current (VDD)
IDD
CSL_ and FB_ forced above their regulation
points
5
µA
Shutdown Supply Current (VCC)
ON1 = ON2 = GND
5
µA
Shutdown Supply Current (VDD)
ON1 = ON2 = GND
5
µA
MAIN SMPS CONTROLLERS
PWM1 Output Voltage in Fixed
Mode
VOUT1
VIN = 6V to 26V, SKIP1 = VCC,
zero to full load (Note 1)
3.255
3.375
V
PWM2 Output Voltage in Fixed
Mode
VOUT2
VIN = 6V to 26V, SKIP2 = VCC,
zero to full load (Note 1)
4.925
5.105
V
VIN = 6V to 26V, FB1 or FB2,
duty factor = 20% to 80% (Note 1)
0.987
1.023
V
Feedback Voltage in Adjustable
Mode
VFB_
Output Voltage Adjust Range
Either SMPS
1.0
5.5
V
FB1, FB2 Fixed-Mode Threshold
Voltage
Dual-mode comparator
1.9
2.1
V
FSEL = GND
170
230
FSEL = REF (Note 3)
270
330
FSEL = VCC
425
575
FSEL = GND
97.5
FSEL = REF (Note 3)
97.5
FSEL = VCC
97.5
Operating Frequency
Maximum Duty Factor
Minimum On-Time
fOSC
DMAX
tON(MIN)
(Note 4)
kHz
%
200
ns
VREF
V
CURRENT LIMIT
ILIM_ Adjustment Range
0.5
_______________________________________________________________________________________
5
MAX8716/MAX8717/MAX8757
ELECTRICAL CHARACTERISTICS (continued)
MAX8716/MAX8717/MAX8757
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 12V, FSEL = REF, SKIP_ = 0, VON_ = VILIM_ = VCC = VDD = 5V, TA = -40°C to +85°C, unless otherwise
noted.) (Note 6)
PARAMETER
SYMBOL
CONDITIONS
Current-Limit Threshold (Fixed)
VLIMIT_
VCSH_ - VCSL _, ILIM_ = VCC (Note 3)
Current-Limit Threshold
(Adjustable)
VLIMIT_
VCSH_ - VCSL _
MIN
TYP
44
MAX
UNITS
56
mV
VILIM_ = 2.00V
188
212
VILIM_ = 1.00V
93
107
1.98
2.02
V
mV
REFERENCE (REF)
Reference Voltage
VREF
VCC = 4.5V to 5.5V, IREF = 0
FAULT DETECTION
Output Overvoltage Trip
Threshold
MAX8716/MAX8717 only
11
19
%
Output Undervoltage-Protection
Trip Threshold
With respect to error-comparator threshold
65
75
%
PGOOD_ Lower Trip Threshold
With respect to error-comparator threshold,
hysteresis = 1%
-12.5
-8.0
%
PGOOD_ Output Low Voltage
ISINK = 4mA
0.4
V
BST_ - LX_ forced to 5V (Note 5)
5
Ω
DL_, high state (Note 5)
5
DL_, low state (Note 5)
3
GATE DRIVERS
DH_ Gate-Driver On-Resistance
DL_ Gate Driver On-Resistance
RDH
RDL
Ω
INPUTS AND OUTPUTS
ON_ Input Voltage
Rising edge, hysteresis = 225mV
Three-Level Input Logic
SKIP1, SKIP2, FSEL
High
REF
1.2
VCC 0.2
1.7
GND
2.2
2.3
V
V
0.5
Note 2: When the inductor is in continuous conduction, the output voltage will have a DC regulation level lower than the error-comparator threshold by 50% of the ripple. In discontinuous conduction, the output voltage will have a DC regulation level higher than the error-comparator threshold by 50% of the ripple.
Note 3: Default setting for the MAX8716.
Note 4: Specifications are guaranteed by design, not production tested.
Note 5: Production testing limitations due to package handling require relaxed maximum on-resistance specifications for the thin QFN
package.
Note 6: Specifications from 0°C to -40°C are guaranteed by design, not production tested.
6
_______________________________________________________________________________________
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
(Circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, SKIP_ = GND, FSEL = REF, TA = +25°C, unless otherwise noted.)
3.3V OUTPUT EFFICIENCY
vs. LOAD CURRENT
60
80
70
PWM
MODE
LOWNOISE
MODE
60
1
10
0.001
0.01
3.3V OUTPUT VOLTAGE
vs. LOAD CURRENT
SKIP
MODE
3.30
1
10
PWM
MODE
SKIP
MODE
90
3
4
0.001
5
0.01
0.1
1
10
0.001
0.01
PWM
MODE
LOWNOISE
MODE
5.05
SKIP
MODE
5.00
VIN = 20V
50
4.95
0.1
LOAD CURRENT (A)
1
10
100
VIN = 12V
L = 4.3µH
90
SKIP
MODE
0
1
10
80
70
PWM
MODE
LOW-NOISE
MODE
60
PWM
MODE
1
2.5V OUTPUT EFFICIENCY
vs. LOAD CURRENT
LOWNOISE
MODE
5.10
0.1
LOAD CURRENT (A)
EFFICIENCY (%)
80
0.01
PWM
MODE
VIN = 12V
5.15
OUTPUT VOLTAGE (V)
SKIP
MODE
0.001
70
5V OUTPUT VOLTAGE
vs. LOAD CURRENT
MAX8716/17/57 toc07
100
60
LOWNOISE
MODE
LOAD CURRENT (A)
5V OUTPUT EFFICIENCY
vs. LOAD CURRENT
70
80
50
LOAD CURRENT (A)
90
SKIP
MODE
VIN = 6V
MAX8716/17/57 toc08
2
10
100
50
1
1
60
VIN = 12V
3.25
0
0.1
5V OUTPUT EFFICIENCY
vs. LOAD CURRENT
60
PWM
MODE
0.01
5V OUTPUT EFFICIENCY
vs. LOAD CURRENT
80
70
0.001
LOAD CURRENT (A)
LOWNOISE
MODE
90
EFFICIENCY (%)
LOWNOISE
MODE
3.35
100
MAX8716/17/57 toc04
OUTPUT VOLTAGE (V)
3.40
0.1
LOAD CURRENT (A)
MAX8716/17/57 toc05
LOAD CURRENT (A)
EFFICIENCY (%)
VIN = 20V
50
EFFICIENCY (%)
0.1
PWM
MODE
LOWNOISE
MODE
VIN = 12V
50
0.01
70
60
VIN = 6V
50
0.001
80
MAX8716/17/57 toc06
70
PWM
MODE
MAX8716/17/57 toc09
LOWNOISE
MODE
SKIP
MODE
90
EFFICIENCY (%)
80
SKIP
MODE
90
EFFICIENCY (%)
90
100
MAX8716/17/57 toc02
SKIP
MODE
EFFICIENCY (%)
100
MAX8716/17/57 toc01
100
3.3V OUTPUT EFFICIENCY
vs. LOAD CURRENT
MAX8716/17/57 toc03
3.3V OUTPUT EFFICIENCY
vs. LOAD CURRENT
VIN = 12V
2
3
LOAD CURRENT (A)
4
5
50
0.001
0.01
0.1
1
10
LOAD CURRENT (A)
_______________________________________________________________________________________
7
MAX8716/MAX8717/MAX8757
Typical Operating Characteristics
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, SKIP_ = GND, FSEL = REF, TA = +25°C, unless otherwise noted.)
SKIP
MODE
24
80
70
PWM
MODE
50
0.001
16
12
10
SKIP1 = SKIP2 = GND OR REF
ON1 = ON2 = VCC
0.1
10
1
1
IBIAS
IIN
0.1
SKIP1 = SKIP2 = VCC
ON1 = ON2 = VCC
0
0.01
0.01
0
4
8
12
16
24
20
0
4
8
12
16
LOAD CURRENT (A)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
OUT2 IDLE-MODE CURRENT
vs. INPUT VOLTAGE
OUT2 SWITCHING FREQUENCY
vs. LOAD CURRENT
5V OUTPUT VOLTAGE
vs. INPUT VOLTAGE
1.2
1.0
0.8
SKIP2 = REF
0.6
0.4
SKIP2 = REF
100
SKIP2 = GND
10
5.05
24
5.00
4.95
SKIP2 = VCC
0.2
0
0
4
8
12
16
20
4.90
1
0.001
24
0.01
INPUT VOLTAGE (V)
0.1
1
10
4
8
12
16
INPUT VOLTAGE (V)
OUT2 DROPOUT VOLTAGE
vs. LOAD CURRENT
3.35
3.30
MAX8716/17/57 toc17
0.4
DROPOUT VOLTAGE (V)
MAX8716/17/57 toc16
3.40
OUTPUT VOLTAGE (V)
0
LOAD CURRENT (A)
3.3V OUTPUT VOLTAGE
vs. INPUT VOLTAGE
0.3
0.2
0.1
VOUT2 = 4.8V
SKIP1 = VCC
3.25
0
0
4
8
12
16
INPUT VOLTAGE (V)
8
20
MAX8716/17/57 toc15
SKIP2 = VCC
OUTPUT VOLTAGE (V)
SKIP2 = GND
MAX8716/17/57 toc14
1.6
1.4
1000
SWITCHING FREQUENCY (kHz)
MAXIMUM DUTYCYCLE LIMITED
1.8
IIN
8
4
MAX8716/17/57 toc13
2.0
IBIAS
20
LOW-NOISE
MODE
60
MAX8716/17/57 toc11
90
SUPPLY CURRENT (mA)
VIN = 12V
L = 3.2µH
EFFICIENCY (%)
28
MAX8716/17/57 toc10
100
NO-LOAD SUPPLY CURRENT vs. INPUT
VOLTAGE (IDLE MODE)
MAX8716/17/57 toc12
NO-LOAD SUPPLY CURRENT vs. INPUT
VOLTAGE (FORCED-PWM MODE)
SUPPLY CURRENT (mA)
1.8V OUTPUT EFFICIENCY
vs. LOAD CURRENT
IDLE-MODE CURRENT (A)
MAX8716/MAX8717/MAX8757
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
20
24
0
1
2
3
4
LOAD CURRENT (A)
_______________________________________________________________________________________
5
20
24
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
(Circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, SKIP_ = GND, FSEL = REF, TA = +25°C, unless otherwise noted.)
STARTUP WAVEFORMS
SHUTDOWN WAVEFORMS
MAX8716/17/57 toc18
5V
0
5V
A
12V
B
C
0
0
2V
STARTUP WAVEFORMS
MAX8716/17/57 toc19
5V
2V
5V
D
E
0
0
MAX8716/17/57 toc20
A
3.3V
0
A
B
0
B
C
0
5V
C
D
E
0
D
F
0
E
F
0
0
0
0
400µs/div
A. LX2, 20V/div
D. REF, 2V/div
B. ON2, 10V/div
E. OUT2, 2V/div
C. PGOOD2, 10V/div
F. ILX2, 2.5AV/div
1ms/div
A. DL2, 10V/div
D. REF, 2V/div
B. ON2, 10V/div
E. OUT2, 2V/div
C. PGOOD2, 10V/div
F. ILX2, 2.5AV/div
1.0Ω LOAD ON OUT2
1.0kΩ LOAD ON OUT2
SKIP2 = GND
VCC UVLO WAVEFORMS
1ms/div
A. ON1/ON2, 5V/div
D. OUT2, 2V/div
B. PGOOD1, 10V/div
E. OUT1, 2V/div
C. PGOOD2, 10V/div
STEADY-STATE WAVEFORMS
MAX8716/17/57 toc21
MAX8716/17/57 toc22
5V
A
5V
5V
A
12V
0
5V
B
B
C
C
5V
D
0
3.3V
D
12V
0
E
E
0
4ms/div
A. VCC, 2V/div
D. DL2, 5V/div
B. OUT2, 2V/div
E. ILX2, 2.5AV/div
C. PGOOD2, 5V/div
2µs/div
A. OUT2, 50mV/div
D. OUT1, 50mV/div
B. LX2, 10V/div
E. LX1, 10V/div
C. VIN, 50mV/div
100Ω LOAD ON OUT2
SKIP2 = VCC
1.0A LOAD ON OUT1, 1.0A LOAD ON OUT2
SKIP1 = VCC, SKIP2 = VCC
_______________________________________________________________________________________
9
MAX8716/MAX8717/MAX8757
Typical Operating Characteristics (continued)
MAX8716/MAX8717/MAX8757
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, SKIP_ = GND, FSEL = REF, TA = +25°C, unless otherwise noted.)
OUT1 LOAD TRANSIENT
DROPOUT WAVEFORMS
SKIP1 TRANSITION
MAX8716/17/57 toc24
MAX8716/17/57 toc23
4.9V
A
5V
B
C
3.3V
D
0
A
3.3V
B
0
A
12V
0
5V
MAX8716/17/57 toc25
B
0
3A
C
0
3.3V
C
2.5A
12V
5V
E
D
0
D
0
0
2µs/div
A. OUT2, 50mV/div
D. OUT1, 50mV/div
B. LX2, 10V/div
E. LX1, 10V/div
C. VIN, 50mV/div
1.0A LOAD ON OUT1, 1.0A LOAD ON OUT2
SKIP1 = VCC, SKIP2 = VCC
20µs/div
A. CONTROL, 5V/div
C. ILX1, 3A/div
B. OUT1, 50mV/div
D. LX1, 10V/div
A. SKIP1, 5V/div
B. LX1, 10V/div
SKIP1 = VCC
30mA LOAD ON OUT1
20µs/div
SKIP1 TRANSITION
SKIP1 TRANSITION
MAX8716/17/57 toc27
MAX8716/17/57 toc26
0
A
A
0
12V
12V
B
0
3.3V
C
B
0
3.3V
C
2.5A
2.5A
D
0
D
0
20µs/div
20µs/div
A. SKIP1, 5V/div
B. LX1, 10V/div
30mA LOAD ON OUT1
10
C. OUT1, 50mV/div
D. ILX1, 2.5A/div
C. OUT1, 50mV/div
D. ILX1, 2.5A/div
A. SKIP1, 5V/div
B. LX1, 10V/div
C. OUT1, 50mV/div
D. ILX1, 2.5A/div
30mA LOAD ON OUT1
______________________________________________________________________________________
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
PIN
MAX8716
MAX8717/
MAX8757
NAME
FUNCTION
1
1
VCC
Analog Supply Input. Connect to the system supply voltage (+4.5V to +5.5V) through a
series 20Ω resistor. Bypass VCC to AGND with a 1µF or greater ceramic capacitor.
2
2
SKIP1
Low-Noise Mode Control for SMPS1. Connect SKIP1 to GND for normal idle-mode
(pulse-skipping) operation or to VCC for PWM mode (fixed frequency). Connect to REF
for low-noise mode.
3
3
REF
2.0V Reference Voltage Output. Bypass REF to AGND with a 0.1µF or greater ceramic
capacitor. The reference can source up to 50µA. Loading REF degrades output voltage
accuracy according to the REF load-regulation error (see the Typical Operating
Characteristics). The reference shuts down when both ON1 and ON2 are low.
4
4
SKIP2
Low-Noise Mode Control for SMPS2. Connect SKIP2 to GND for normal idle-mode
(pulse-skipping) operation or to VCC for PWM mode (fixed frequency). Connect to REF
for low-noise mode.
—
5
FSEL
Frequency Select Input. This four-level logic input sets the controller’s switching
frequency. Connect FSEL to VCC for 500kHz, to REF for 300kHz, and to GND for 200kHz
operation.
5
6
ON1
SMPS1 Enable Input. Drive ON1 high to enable SMPS1. Drive ON1 low to shut down
SMPS1.
6
7
ON2
SMPS2 Enable Input. Drive ON2 high to enable SMPS2. Drive ON2 low to shut down
SMPS2.
SMPS2 Peak Current-Limit Threshold Adjustment. Connect ILIM2 to VCC to enable the
default 50mV current-limit threshold. In adjustable mode, the current-limit threshold
across CSH2 and CSL2 is precisely 1/10th the voltage seen at ILIM2 over a 500mV to
2.0V range. The logic threshold for switchover to the 50mV default value is
approximately VCC - 1V.
—
8
ILIM2
7
9
PGOOD2
8
10
FB2
9
11
CSL2
Negative Current-Sense Input for SMPS2. Connect to the negative terminal of the
current-sense element. Figure 8 describes two different current-sensing options.
10
12
CSH2
Positive Current-Sense Input for SMPS2. Connect to the positive terminal of the currentsense element. Figure 8 describes two different current-sensing options.
11
13
BST2
Boost Flying Capacitor Connection for SMPS2. Connect to an external capacitor and
diode as shown in Figure 1. An optional resistor in series with BST2 allows the DH2 turnon current to be adjusted.
12
14
DH2
High-Side Gate-Driver Output for SMPS2. DH2 swings from LX2 to BST2.
13
15
LX2
Inductor Connection for SMPS2. Connect LX2 to the switched side of the inductor. LX2
is the lower supply rail for the DH2 high-side gate driver.
SMPS2 Open-Drain Power-Good Output. PGOOD2 is low when SMPS2 is more than
10% below its regulation threshold, during soft-start, and in shutdown.
Feedback Input for SMPS2. Connect FB2 to VCC for fixed 5V output. In adjustable mode,
FB2 regulates to 1V.
______________________________________________________________________________________
11
MAX8716/MAX8717/MAX8757
Pin Description
MAX8716/MAX8717/MAX8757
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
Pin Description (continued)
PIN
MAX8716
MAX8717/
MAX8757
NAME
14
16
DL2
Low-Side Gate-Driver Output for SMPS2. DL2 swings from PGND to VDD.
15
17
VDD
Supply Voltage Input for the DL_ Gate Drivers. Connect to a 5V supply.
16
—
GND
Power and Analog Ground. Connect backside pad to GND.
—
18
PGND
—
19
AGND
17
20
DL1
Low-Side Gate-Driver Output for SMPS1. DL1 swings from PGND to VDD.
18
21
LX1
Inductor Connection for SMPS1. Connect LX1 to the switched side of the inductor. LX1
is the lower supply rail for the DH1 high-side gate driver.
19
22
DH1
High-Side Gate-Driver Output for SMPS1. DH1 swings from LX1 to BST1.
20
23
BST1
Boost Flying Capacitor Connection for SMPS1. Connect to an external capacitor and
diode as shown in Figure 1. An optional resistor in series with BST1 allows the DH1 turnon current to be adjusted.
21
24
CSH1
Positive Current-Sense Input for SMPS1. Connect to the positive terminal of the currentsense element. Figure 8 describes two different current-sensing options.
22
25
CSL1
Negative Current-Sense Input for SMPS1. Connect to the negative terminal of the
current-sense element. Figure 8 describes two different current-sensing options.
23
26
FB1
Feedback Input for SMPS1. Connect FB1 to VCC for fixed 3.3V output. In adjustable
mode, FB1 regulates to 1V.
24
27
PGOOD1
SMPS1 Open-Drain Power-Good Output. PGOOD1 is low when SMPS1 is more than
10% below its regulation threshold, during soft-start, and in shutdown.
—
28
ILIM1
EP
EP
EP
FUNCTION
Power Ground
Analog Ground. Connect backside pad to AGND.
SMPS1 Peak Current-Limit Threshold Adjustment. Connect ILIM1 to VCC to enable the
default 50mV current-limit threshold. In adjustable mode, the current-limit threshold
across CSH1 and CSL1 is precisely 1/10th the voltage seen at ILIM1 over a 500mV to
2.0V range. The logic threshold for switchover to the 50mV default value is
approximately VCC - 1V.
Exposed Pad. Connect exposed backside pad to analog ground.
Detailed Description
The MAX8716/MAX8717/MAX8757 Standard Application
Circuit (Figure 1) generates the 5V/5A and 3.3V/5A typical of the main supplies in notebook computers. The
input supply range is 6V to 24V. See Table 1 for component selections, while Table 2 lists the component manufacturers.
The MAX8716/MAX8717/MAX8757 contain two interleaved fixed-frequency, step-down controllers
designed for low-voltage power supplies. The optimal
interleaved architecture guarantees out-of-phase operation, which reduces the input capacitor ripple.
12
SMPS 5V Bias Supply (VCC and VDD)
The MAX8716/MAX8717/MAX8757 switch-mode power
supplies (SMPS) require a 5V bias supply in addition to
the high-power input supply (battery or AC adapter).
VDD is the power rail for the MOSFET gate drive, and
VCC is the power rail for the IC. Connect the external
4.5V to 5.5V supply directly to VDD and connect VDD to
VCC through an RC filter, as shown in Figure 1. The
maximum supply current required is:
IBIAS = ICC + fSW (QG(NL1) + QG1(NH1) +QG2(NL2) +
QG2(NH2)) = 1.3mA to 40mA
where ICC is 1.3mA, fSW is the switching frequency,
and Q G_ are the MOSFET data sheet’s total gatecharge specification limits at VGS = 5V.
______________________________________________________________________________________
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
MAX8716/MAX8717/MAX8757
INPUT (VIN)
+5V BIAS
C1
1µF
CIN
(2) 10µF
VDD
DBST1
NH1
DH1
CBST1
0.1µF
L1
5.7µH
DBST2
DL1
BST1
MAX8716
MAX8717
MAX8757
NH2
DH2
BST2
CBST2
0.1µF
LX1
LX2
DL1
DL2
DL2
L2
5.7µH
NL2
NL1
*PGND
*AGND
RCS1
7mΩ
3.3V PWM
OUTPUT
COUT1
220µF
VCC
CSH1
CSH2
CSL1
CSL2
FB1
RCS2
7mΩ
FB2
5V PWM
OUTPUT
COUT2
150µF
VCC
R1
20Ω
+5V BIAS
VCC
PULSESKIPPING
CONTROL
C2
1µF
SKIP1
SKIP2
ON1
R2
100kΩ
R3
100kΩ
POWER-GOOD 1
PGOOD1
POWER-GOOD 2
PGOOD2
CREF
0.22µF
ON OFF
ON2
REF
DEFAULT
CURRENT
LIMIT
VCC
ILIM1
VCC
ILIM2
FSEL
REF (300kHz)
*FOR THE MAX8716 AGND AND PGND,
REFER TO A SINGLE
PIN DESIGNATED GND.
MAX8717 AND MAX8757 ONLY
POWER GROUND
SEE TABLE 1 FOR COMPONENT SPECIFICATIONS.
ANALOG GROUND
Figure 1. Standard Application Circuit
______________________________________________________________________________________
13
MAX8716/MAX8717/MAX8757
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
Table 1. Component Selection for Standard Applications
COMPONENT
5A/300kHz
5A/500kHz
Input Voltage
VIN = 7V to 24V
VIN = 7V to 24V
(2) 10µF, 25V
Taiyo Yuden TMK432BJ106KM
(2) 10µF, 25V
Taiyo Yuden TMK432BJ106KM
220µF, 4V, 25mΩ low-ESR capacitor
Sanyo 4TPE220M
150µF, 4V, 25mΩ low-ESR capacitor
Sanyo 4TPE150M
150µF, 6.3V, 25mΩ low-ESR capacitor
Sanyo 6TPE150M
100µF, 6.3V, 25mΩ low-ESR capacitor
Sanyo 6TPE100M
NH_ High-Side MOSFET
Fairchild Semiconductor FDS6612A,
International Rectifier IRF7807V
Fairchild Semiconductor FDS6612A,
International Rectifier IRF7807V
NL_ Low-Side MOSFET
Fairchild Semiconductor FDS6670S,
International Rectifier IRF7807VD1
Fairchild Semiconductor FDS6670S,
International Rectifier IRF7807VD1
Nihon EC21QS03L
2A, 30V, 0.45Vf
Nihon EC21QS03L
2A, 30V, 0.45Vf
L_ Inductor
5.7µH
Sumida CDEP105-5R7NC
3.9µH
Sumida CDRH124-3R9NC
RSENSE_
7mΩ ±1%, 0.5W resistor
IRC LR2010-01-R007F or
Dale WSL-2010-R007F
7mΩ ±1%, 0.5W resistor
IRC LR2010-01-R007F or
Dale WSL-2010-R007F
CIN Input Capacitor
COUT1, Output Capacitor for 3.3V Output
COUT2, Output Capacitor for 5V Output
DL_ Schottky Rectifier
(If Needed)
Reference (REF)
The 2V reference is accurate to ±1.5% over temperature and load, making REF useful as a precision system
reference. Bypass REF to GND with a 0.1µF or greater
ceramic capacitor. The reference sources up to 50µA
and sinks 10µA to support external loads.
SMPS Detailed Description
Power-on reset (POR) occurs when VCC rises above
approximately 2V, resetting the undervoltage, overvoltage, and thermal-shutdown fault latches. The POR circuit also ensures that the low-side drivers are driven
high until the SMPS controllers are activated. The VCC
input undervoltage-lockout (UVLO) circuitry inhibits
switching if VCC is below the VCC UVLO threshold.
An internal soft-start gradually increases the regulation
voltage during startup to reduce the input surge currents (see the startup waveforms in the Typical
Operating Characteristics).
SMPS Enable Controls (ON1, ON2)
Table 2. Component Suppliers
SUPPLIER
WEBSITE
AVX
www.avx.com
Central Semiconductor
www.centralsemi.com
Coilcraft
www.coilcraft.com
Coiltronics
www.coiltronics.com
Fairchild Semiconductor
www.fairchildsemi.com
International Rectifier
www.irf.com
Kemet
www.kemet.com
Panasonic
www.panasonic.com/industrial
Sanyo
www.secc.co.jp
Sumida
www.sumida.com
Taiyo Yuden
www.t-yuden.com
TDK
www.component.tdk.com
TOKO
www.tokoam.com
Vishay (Dale, Siliconix)
www.vishay.com
ON1 and ON2 provide independent control of output
soft-start and soft-shutdown. This allows flexible control
of startup and shutdown sequencing. The outputs can
be started simultaneously, sequentially, or independently. To provide sequential startup, connect
14
______________________________________________________________________________________
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
MAX8716/MAX8717/MAX8757
REF
R
MAX8717/MAX8757
2.0V
REF
OSC
FSEL
R
SKIP1
VCC
GND
SKIP2
ON1
ON2
ILIM1
ILIM2
CSH1
CSH2
CSL1
BST1
DH1
CSL2
BST2
PWM2
CONTROLLER
(FIGURE 3)
PWM1
CONTROLLER
(FIGURE 3)
DH2
LX2
LX1
VDD
VDD
DL1
DL2
PGND
FB
DECODE
(FIGURE 5)
POWER-GOOD AND
FAULT PROTECTION
(FIGURE 7)
PGOOD1
FB2
INTERNAL FB
FAULT
INTERNAL FB
FAULT
FB
DECODE
(FIGURE 5)
FB1
POWER-GOOD AND
FAULT PROTECTION
(FIGURE 7)
PGOOD2
Figure 2. Functional Diagram
ON_ of one regulator to PGOOD_ of the other. For
example, with ON1 connected to PGOOD2, OUT1 softstarts after OUT2 is in regulation. Drive ON_ low to
clear the overvoltage, undervoltage, and thermal fault
latches.
Soft-Start and Soft-Shutdown
Soft-start begins when ON_ is driven high and REF is in
regulation. During soft-start, the output is ramped up
from 0V to the final set voltage in 2ms. This reduces
inrush current and provides a predictable ramp-up time
for power sequencing.
Soft-shutdown begins after ON_ goes low, an output
undervoltage fault occurs, or a thermal fault occurs.
______________________________________________________________________________________
15
MAX8716/MAX8717/MAX8757
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
The two outputs are independent. A fault at one output
does not trigger shutdown of the other. During softshutdown the output is ramped down to 0V in 4ms,
reducing negative inductor currents that can cause
negative voltages on the output. At the end of soft-shutdown, DL_ is driven high until startup is again triggered
by a rising edge of ON_. The reference is turned off
when both outputs have been shut down.
Fixed-Frequency, Current-Mode PWM
Controller
The heart of each current-mode PWM controller is a
multi-input, open-loop comparator that sums two signals: the output-voltage error signal with respect to the
reference voltage and the slope-compensation
ramp (Figure 3). The MAX8716/MAX8717/MAX8757 use
a direct-summing configuration, approaching ideal
cycle-to-cycle control over the output voltage without a
traditional error amplifier and the phase shift associated
with it. The MAX8716/MAX8717/MAX8757 use a relatively low loop gain, allowing the use of low-cost output
capacitors. The low loop gain results in the 0.1% typical
load-regulation error and helps reduce the output
capacitor size and cost by shifting the unity-gain
crossover frequency to a lower level.
Frequency Selection (FSEL)
The FSEL input selects the PWM mode switching frequency. Table 3 shows the switching frequency based
on the FSEL connection. High-frequency (500kHz)
operation optimizes the application for the smallest
component size, trading off efficiency due to higher
switching losses. This may be acceptable in ultraportable devices where the load currents are lower.
Low-frequency (200kHz) operation offers the best overall efficiency at the expense of component size and
board space.
Forced-PWM Mode
To maintain low-noise fixed-frequency operation, drive
SKIP_ high to put the output into forced-PWM mode.
This disables the zero-crossing comparator and allows
negative inductor current. During forced-PWM mode,
the switching frequency remains constant and the noload supply current is typically between 8mA and
20mA per phase, depending on external MOSFETs and
switching frequency.
Light-Load Operation Control (SKIP_)
The MAX8716/MAX8717/MAX8757 include SKIP_
inputs that enable the corresponding outputs to operate in discontinuous mode. Connect SKIP_ to GND or
REF as shown in Table 4 to enable or disable the zerocrossing comparators of either controller. When the
16
zero-crossing comparator is enabled, the controller
forces DL_ low when the current-sense inputs detect
zero inductor current. This keeps the inductor from discharging the output capacitors and forces the controller to skip pulses under light-load conditions to
avoid overcharging the output. During skip mode, the
VDD current consumption is reduced and efficiency is
improved. During low-noise skip mode, the no-load ripple amplitude is two times smaller and the no-load
switching frequency is four times higher, although the
light-load efficiency is somewhat lower.
Table 3. FSEL Configuration Table
FSEL
SWITCHING FREQUENCY (kHz)
VCC
500
REF
300
GND
200
Idle-Mode Current-Sense Threshold
When pulse-skipping mode is enabled, the on-time of
the step-down controller terminates when the output
voltage exceeds the feedback threshold and when the
current-sense voltage exceeds the idle-mode currentsense threshold. Under light-load conditions, the ontime duration depends solely on the idle-mode
current-sense threshold, which is 20% (SKIP_ = GND)
of the full-load current-limit threshold set by ILIM_, or
the low-noise current-sense threshold, which is 10%
(SKIP_ = REF) of the full-load current-limit threshold set
by ILIM_. This forces the controller to source a minimum amount of power with each cycle. To avoid overcharging the output, another on-time cannot begin until
output voltage drops below the feedback threshold.
Since the zero-crossing comparator prevents the
switching regulator from sinking current, the controller
must skip pulses. Therefore, the controller regulates the
valley of the output ripple under light-load conditions.
Automatic Pulse-Skipping Crossover
In skip mode, an inherent automatic switchover to PFM
takes place at light loads (Figure 4). This switchover is
affected by a comparator that truncates the low-side
switch on-time at the inductor current’s zero crossing.
The zero-crossing comparator senses the inductor current across CSH_ and CSL_. Once VCSH - VCSL _ drops
below the 3mV zero-crossing, current-sense threshold,
the comparator forces DL_ low (Figure 3). This mechanism causes the threshold between pulse-skipping
PFM and nonskipping PWM operation to coincide with
the boundary between continuous and discontinuous
inductor-current operation (also known as the “critical
______________________________________________________________________________________
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
MAX8716/MAX8717/MAX8757
FB
CSH
REF / 2
0.05 x VLIMIT
SLOPE COMP
0.1 x VLIMIT
SOFT-START
SOFT-STOP
CSL
ON
AGND
R
Q
SKIP
DECODE
S
DH DRIVER
SKIP
VLIMIT
OSC
-1.2 x VLIMIT
S
R
Q
DL DRIVER
3mV
Figure 3. PWM-Controller Functional Diagram
conduction” point). The load-current level at which
PFM/PWM crossover occurs, I LOAD(SKIP) , is determined by:
ILOAD(SKIP) =
(VIN − VOUT )VOUT
2LVIN ƒ OSC
The switching waveforms may appear noisy and asynchronous when light loading causes pulse-skipping
operation, but this is a normal operating condition that
results in high light-load efficiency. Trade-offs in PFM
noise vs. light-load efficiency are made by varying the
inductance. Generally, low inductance produces a
broader efficiency vs. load curve, while higher values
result in higher full-load efficiency (assuming that the
______________________________________________________________________________________
17
Table 4. SKIP_ Configuration Table
SKIP_
VCC
MODE
Forced-PWM mode
GND
REF
COMMENTS
Skip mode
Low-noise skip mode
Fixed-frequency operation.
Constant output ripple
voltage.
Able to source and sink
current.
High efficiency at light
loads.
Source-only applications.
Good efficiency at light
loads.
Two times smaller no-load
ripple and 4 times higher
frequency compared with
skip mode.
Source-only applications.
tON(SKIP) =
INDUCTOR CURRENT
MAX8716/MAX8717/MAX8757
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
VOUT
VIN x fOSC
ILOAD(SKIP)
I
ILOAD = LOAD(SKIP)
2
0
ON-TIME
TIME
Figure 4. Pulse-Skipping/Discontinuous Crossover Point
Table 5. Operating Modes Truth Table
MODE
CONDITION
Power-Up
VCC UVLO
Run
ON1 or ON2 enabled
COMMENT
DL_ tracks VCC as VCC rises from 0V to +5V.
When ON_ is low, DL_ tracks VCC as VCC falls.
When ON_ is high, DL_ is forced low as VCC falls below the
3.95V (typ) falling UVLO threshold. DL_ is forced high when
VCC falls below 1V (typ).
Normal operation.
Output Overvoltage (OVP)
Protection
Either output > 115% of nominal level
When the overvoltage (OV) comparator trips, the faulted side
sets the OV latch, forcing PGOOD_ low and DL_ high. The
other controller is not affected.
The OV latch is cleared by cycling VCC below 1V or cycling
the respective ON_ pin.
Output Undervoltage
Protection (UVP)
Either output < 70% of nominal level,
UVP is enabled 6144 clock cycles
(1/fOSC) after the output is enabled
(ON_ going high)
When the undervoltage (UV) comparator trips, the faulted
side sets the UV latch, forcing PGOOD_ low and initiating the
soft-shutdown sequence by pulsing only DL_. DL_ goes high
after soft-shutdown. The other controller is not affected.
The UV latch is cleared by cycling VCC below 1V or cycling
the respective ON_ pin.
Shutdown
ON1 and ON2 are driven low
Thermal Shutdown
TJ > +160°C
coil resistance remains fixed) and less output voltage
ripple. Penalties for using higher inductor values
include larger physical size and degraded load-transient response (especially at low input-voltage levels).
18
DL_ stays high after soft-shutdown is completed.
All circuitry is shut down.
Exited by POR or cycling ON1 and ON2.
DL1 and DL2 remain high.
Output Voltage
DC output accuracy specifications in the Electrical
Characteristics refer to the error comparator’s threshold. When the inductor continuously conducts, the
______________________________________________________________________________________
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
⎛ A
(V − V
)⎞ ⎛ V
⎞
VOUT(PWM) = VNOM ⎜1− SLOPE IN NOM ⎟ − ⎜ RIPPLE ⎟
⎠
VIN
2
⎝
⎠ ⎝
where VNOM is the nominal output voltage, ASLOPE
equals 1%, and VRIPPLE is the output ripple voltage
(VRIPPLE = R ESR x ∆IINDUCTOR as described in the
Output Capacitor Selection section).
In discontinuous conduction (IOUT < ILOAD(SKIP)), the
MAX8716/MAX8717/MAX8757 regulate the valley of the
output ripple, so the output voltage has a DC regulation
level higher than the error-comparator threshold. For PFM
operation (discontinuous conduction), the output voltage
is approximately defined by the following equation:
VOUT(PFM) = VNOM +
1 ⎛ ƒ SW ⎞
IIDLE RESR
2 ⎜⎝ ƒ OSC ⎟⎠
where VNOM is the nominal output voltage, fOSC is the
maximum switching frequency set by the internal oscillator, fSW is the actual switching frequency, and IIDLE is
the idle-mode inductor current when pulse skipping.
Adjustable/Fixed Output Voltages
(Dual-Mode Feedback)
Connect FB1 and FB2 to VCC to enable the fixed SMPS
output voltages (3.3V and 5V, respectively), set by a
preset, internal resistive voltage-divider connected
between CSL_ and analog ground. See Figure 5.
Connect a resistive voltage-divider at FB_ between
CSL_ and GND to adjust the respective output voltage
between 1V and 5.5V. Choose R2 (resistance from FB
to AGND) to be approximately 10kΩ and solve for R1
(resistance from OUT to FB) using the equation:
⎛ VOUT _ ⎞
R1 = R2⎜
− 1⎟
⎝ VFB _
⎠
where VFB_ = 1V nominal.
Current-Limit Protection (ILIM_)
The current-limit circuit uses differential current-sense
inputs (CSH_ and CSL_) to limit the peak inductor current. If the magnitude of the current-sense signal
exceeds the current-limit threshold, the PWM controller
turns off the high-side MOSFET (Figure 3). At the next
rising edge of the internal oscillator, the PWM controller
does not initiate a new cycle unless the current-sense
signal drops below the current-limit threshold. The
actual maximum load current is less than the peak current-limit threshold by an amount equal to half of the
inductor ripple current. Therefore, the maximum load
capability is a function of the current-sense resistance,
inductor value, switching frequency, and duty cycle
(VOUT / VIN).
In forced-PWM mode, the MAX8716/MAX8717/
MAX8757 also implement a negative current limit to
prevent excessive reverse inductor currents when
V OUT is sinking current. The negative current-limit
threshold is set to approximately -120% of the positive
current limit and tracks the positive current limit when
ILIM is adjusted.
Connect ILIM_ to VCC for the 50mV default threshold, or
adjust the current-limit threshold with an external resistor-divider at ILIM_. Use a 2µA to 20µA divider current
for accuracy and noise immunity. The current-limit
threshold adjustment range is from 50mV to 200mV. In
the adjustable mode, the current-limit threshold voltage
equals precisely 1/10 the voltage seen at ILIM_. The
logic threshold for switchover to the 50mV default value
is approximately VCC - 1V.
Carefully observe the PC board layout guidelines to
ensure that noise and DC errors do not corrupt the differential current-sense signals seen by CSH_ and
CSL_. Place the IC close to the sense resistor with
short, direct traces, making a Kelvin-sense connection
to the current-sense resistor.
MOSFET Gate Drivers (DH_, DL_)
The DH_ and DL_ drivers are optimized for driving
moderate-sized high-side, and larger low-side power
MOSFETs. This is consistent with the low duty factor
seen in notebook applications, where a large V IN V OUT differential exists. The high-side gate drivers
(DH_) source and sink 2A, and the low-side gate drivers (DL_) source 1.7A and sink 3.3A. This ensures
robust gate drive for high-current applications. The
DH_ floating high-side MOSFET drivers are powered by
diode-capacitor charge pumps at BST_ (Figure 6) while
the DL_ synchronous-rectifier drivers are powered
directly by the external 5V supply (VDD).
Adaptive dead-time circuits monitor the DL_ and DH_
drivers and prevent either FET from turning on until the
other is fully off. The adaptive driver dead-time allows
operation without shoot-through with a wide range of
MOSFETs, minimizing delays and maintaining efficiency. There must be a low-resistance, low-inductance
path from the DL_ and DH_ drivers to the MOSFET
______________________________________________________________________________________
19
MAX8716/MAX8717/MAX8757
MAX8716/MAX8717/MAX8757 regulate the peak of the
output ripple, so the actual DC output voltage is lower
than the slope-compensated trip level by 50% of the
output ripple voltage. For PWM operation (continuous
conduction), the output voltage is accurately defined
by the following equation:
MAX8716/MAX8717/MAX8757
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
TO ERROR
AMPLIFIER
CBYP
ADJUSTABLE
OUTPUT
FB
MAX8716
MAX8717
MAX8757
VDD
BST
(RBST)*
DBST
INPUT (VIN)
CBST
DH
2V
NH
L
LX
VDD
FIXED OUTPUT
FB = VCC
DL
CSL
NL
(CNL)*
PGND
Figure 5. Dual-Mode Feedback Decoder
gates for the adaptive dead-time circuits to work properly; otherwise, the sense circuitry in the MAX8716/
MAX8717/MAX8757 interprets the MOSFET gates as
“off” while charge actually remains. Use very short,
wide traces (50 mils to 100 mils wide if the MOSFET is
1in from the driver).
The internal pulldown transistor that drives DL_ low is
robust, with a 0.6Ω (typ) on-resistance. This helps prevent DL_ from being pulled up due to capacitive coupling from the drain to the gate of the low-side MOSFETs
when the inductor node (LX_) quickly switches from
ground to VIN. Applications with high input voltages and
long inductive driver traces may require additional gateto-source capacitance to ensure fast-rising LX_ edges
do not pull up the low-side MOSFETs gate, causing
shoot-through currents. The capacitive coupling
between LX_ and DL_ created by the MOSFET’s gate-todrain capacitance (CRSS), gate-to-source capacitance
(CISS - CRSS), and additional board parasitics should not
exceed the following minimum threshold:
⎛C
⎞
VGS(TH) > VIN ⎜ RSS ⎟
C
⎝ ISS ⎠
Variation of the threshold voltage may cause problems
in marginal designs. Alternatively, adding a resistor
less than 10Ω in series with BST_ may remedy the
problem by increasing the turn-on time of the high-side
MOSFET without degrading the turn-off time (Figure 6).
20
(RBST)* OPTIONAL—THE RESISTOR LOWERS EMI BY DECREASING
THE SWITCHING-NODE RISE TIME.
(CNL)* OPTIONAL—THE CAPACITOR REDUCES LX TO DL CAPACITIVE
COUPLING THAT CAN CAUSE SHOOT-THROUGH CURRENTS.
Figure 6. Optional Gate-Driver Circuitry
Power-Good Output (PGOOD_)
PGOOD_ is the open-drain output of a comparator that
continuously monitors each SMPS output voltage for
overvoltage and undervoltage conditions. PGOOD_ is
actively held low in shutdown (ON_ = GND), soft-start,
and soft-shutdown. Once the analog soft-start terminates, PGOOD_ becomes high impedance as long as
the output is above 90% of the nominal regulation voltage set by FB_. PGOOD_ goes low once the output
drops 10% below its nominal regulation point, an output
overvoltage fault occurs, or ON_ is pulled low. For a
logic-level PGOOD_ output voltage, connect an external pullup resistor between PGOOD_ and +5V or +3.3V.
A 100kΩ pullup resistor works well in most applications.
Fault Protection
Output Overvoltage Protection
(MAX8716/MAX8717 Only)
If the output voltage of either SMPS rises above 115%
of its nominal regulation voltage, the corresponding
controller sets its overvoltage fault latch, pulls PGOOD_
low, and forces DL_ high for the corresponding SMPS
controller. The other controller is not affected. If the
condition that caused the overvoltage persists (such as
a shorted high-side MOSFET), the battery fuse will
blow. Cycle VCC below 1V or toggle ON_ to clear the
overvoltage fault latch and restart the SMPS controller.
______________________________________________________________________________________
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
VCC POR and UVLO
Power-on reset (POR) occurs when VCC rises above
approximately 2V, resetting the fault latch and preparing the PWM for operation. VCC undervoltage-lockout
(UVLO) circuitry inhibits switching, forces PGOOD_
low, and forces the DL_ gate drivers low.
If VCC drops low enough to trip the UVLO comparator
while ON_ is high, the MAX8716/MAX8717/MAX8757
immediately force DH_ and DL_ low on both controllers.
The output discharges to 0V at a rate dependent on the
load and the total output capacitance. This prevents
negative output voltages, eliminating the need for a
Schottky diode to GND at the output.
Thermal Fault Protection
The MAX8716/MAX8717/MAX8757 feature a thermal
fault-protection circuit. When the junction temperature
rises above +160°C, a thermal sensor sets the fault
latches, pulls PGOOD low, and shuts down both SMPS
controllers using the soft-shutdown sequence (see the
Sort-Start and Soft-Shutdown section). Cycle V CC
below 1V or toggle ON1 and ON2 to clear the fault
latches and restart the controllers after the junction
temperature cools by 15°C.
0.9 x
INT REF_
1.15 x
INT REF_
0.7 x
INT REF_
INTERNAL FB
POR
TIMER
FAULT
LATCH
FAULT
POWERGOOD
Figure 7. Power-Good and Fault Protection
•
Maximum Load Current. There are two values to
consider. The peak load current (ILOAD(MAX)) determines the instantaneous component stresses and filtering requirements and thus drives output capacitor
selection, inductor saturation rating, and the design
of the current-limit circuit. The continuous load current (ILOAD) determines the thermal stresses and
thus drives the selection of input capacitors,
MOSFETs, and other critical heat-contributing components.
•
Switching Frequency. This choice determines the
basic trade-off between size and efficiency. The
optimal frequency is largely a function of maximum
input voltage, due to MOSFET switching losses that
are proportional to frequency and VIN2. The optimum frequency is also a moving target, due to rapid
improvements in MOSFET technology that are making higher frequencies more practical.
Inductor Operating Point. This choice provides
trade-offs between size vs. efficiency and transient
response vs. output ripple. Low inductor values provide better transient response and smaller physical
size, but also result in lower efficiency and higher
output ripple due to increased ripple currents. The
minimum practical inductor value is one that causes
the circuit to operate at the edge of critical conduction (where the inductor current just touches zero
with every cycle at maximum load). Inductor values
Design Procedure
Firmly establish the input voltage range and maximum
load current before choosing a switching frequency
and inductor operating point (ripple-current ratio). The
primary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design:
• Input Voltage Range. The maximum value (VIN(MAX))
must accommodate the worst-case, high AC-adapter
voltage. The minimum value (VIN(MIN)) must account
for the lowest battery voltage after drops due to connectors, fuses, and battery selector switches. If there
is a choice at all, lower input voltages result in better
efficiency.
FAULT
PROTECTION
POWER-GOOD
•
______________________________________________________________________________________
21
MAX8716/MAX8717/MAX8757
Output Undervoltage Protection
If the output voltage of either SMPS falls below 70% of
its regulation voltage, the corresponding controller sets
its undervoltage fault latch, pulls PGOOD_ low, and
begins soft-shutdown for the corresponding SMPS controller by pulsing DL_. DH_ remains off during the softshutdown sequence initiated by an unvervoltage fault.
The other controller is not affected. After soft-shutdown
has completed, the MAX8716/MAX8717/MAX8757
force DL_ high and DH_ low. Cycle VCC below 1V or
toggle ON_ to clear the undervoltage fault latch and
restart the SMPS controller.
MAX8716/MAX8717/MAX8757
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
lower than this grant no further size-reduction benefit. The optimum operating point is usually found
between 20% and 50% ripple current. When pulseskipping (SKIP low and light loads), the inductor
value also determines the load-current value at
which PFM/PWM switchover occurs.
Inductor Selection
The switching frequency and inductor operating point
determine the inductor value as follows:
L=
VOUT (VIN − VOUT )
VIN ƒ OSCILOAD(MAX)LIR
For example: ILOAD(MAX) = 5A, VIN = 12V, VOUT = 5V,
fOSC = 300kHz, 30% ripple current or LIR = 0.3:
L=
5V × (12V − 5V)
= 6.50µH
12V × 300kHz × 5A × 0.3
Find a low-loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. Most
inductor manufacturers provide inductors in standard
values, such as 1.0µH, 1.5µH, 2.2µH, 3.3µH, etc. Also
look for nonstandard values, which can provide a better
compromise in LIR across the input voltage range. If
using a swinging inductor (where the no-load inductance decreases linearly with increasing current), evaluate the LIR with properly scaled inductance values. For
the selected inductance value, the actual peak-to-peak
inductor ripple current (∆IINDUCTOR) is defined by:
V
(V − V
)
∆IINDUCTOR = OUT IN OUT
VIN ƒ OSCL
Ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200kHz.
The core must be large enough not to saturate at the
peak inductor current (IPEAK):
IPEAK = ILOAD(MAX) +
∆IINDUCTOR
2
Transient Response
The inductor ripple current also impacts transientresponse performance, especially at low VIN - VOUT differentials. Low inductor values allow the inductor
current to slew faster, replenishing charge removed
from the output filter capacitors by a sudden load step.
The total output voltage sag is the sum of the voltage
sag while the inductor is ramping up and the voltage
sag before the next pulse can occur:
22
VSAG =
L(∆ILOAD(MAX) )2
2COUT (VIN × DMAX − VOUT )
+
∆ILOAD(MAX) (T − ∆T)
COUT
where DMAX is maximum duty factor (see the Electrical
Characteristics), T is the switching period (1 / fOSC), and
∆T equals VOUT / VIN x T when in PWM mode, or L x 0.2
x IMAX / (VIN - VOUT) when in skip mode. The amount of
overshoot during a full-load to no-load transient due to
stored inductor energy can be calculated as:
VSOAR ≈
(∆ILOAD(MAX) )2L
2COUT VOUT
Setting the Current Limit
The minimum current-limit threshold must be great
enough to support the maximum load current when the
current limit is at the minimum tolerance value. The
peak inductor current occurs at ILOAD(MAX) plus half
the ripple current; therefore:
⎛ ∆I
⎞
ILIMIT > ILOAD(MAX) + ⎜ INDUCTOR ⎟
⎝
⎠
2
where ILIMIT_ equals the minimum current-limit threshold voltage divided by the current-sense resistance
(RSENSE). For the 50mV default setting, the minimum
current-limit threshold is 50mV.
Connect ILIM_ to VCC for a default 50mV current-limit
threshold. In adjustable mode, the current-limit threshold is precisely 1/10 the voltage seen at ILIM_. For an
adjustable threshold, connect a resistive divider from
REF to analog ground (GND) with ILIM_ connected to
the center tap. The external 500mV to 2V adjustment
range corresponds to a 50mV to 200mV current-limit
threshold. When adjusting the current limit, use 1% tolerance resistors and a divider current of approximately
10µA to prevent significant inaccuracy in the currentlimit tolerance.
The current-sense method (Figure 8) and magnitude
determines the achievable current-limit accuracy and
power loss. Typically, higher current-sense limits provide tighter accuracy, but also dissipate more power.
Most applications employ a current-limit threshold
(VLIM) of 50mV to 100mV, so the sense resistor can be
determined by:
RSENSE_ = VLIM_ / ILIM_
For the best current-sense accuracy and overcurrent
protection, use a 1% tolerance current-sense resistor
between the inductor and output as shown in Figure 8a.
______________________________________________________________________________________
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
MAX8716/MAX8717/MAX8757
INPUT (VIN)
DH_
CIN
NH
RSENSE
L
LX_
MAX8716 DL_
MAX8717
MAX8757 PGND
COUT
DL
NL
CSH_
CSL_
a) OUTPUT SERIES RESISTOR SENSING
INPUT (VIN)
DH_
NH
CIN
NL
DL
INDUCTOR
LX_
MAX8716 DL_
MAX8717
MAX8757 PGND
COUT
REQ
CEQ
CSH_
CSL_
b) LOSSLESS INDUCTOR SENSING
RBIAS = REQ
Figure 8. Current-Sense Configurations
This configuration constantly monitors the inductor current, allowing accurate current-limit protection.
Alternatively, high-power applications that do not
require highly accurate current-limit protection may
reduce the overall power dissipation by connecting a
series RC circuit across the inductor (Figure 8b) with an
equivalent time constant:
L
= CEQ × REQ
RL
where RL is the inductor’s series DC resistance. In this
configuration, the current-sense resistance equals the
inductor’s DC resistance (RSENSE = RL). Use the worstcase inductance and RL values provided by the inductor manufacturer, adding some margin for the
inductance drop over temperature and load.
Output Capacitor Selection
The output filter capacitor must have low enough equivalent series resistance (ESR) to meet output ripple and
load-transient requirements, yet have high enough ESR
to satisfy stability requirements. The output capacitance must be high enough to absorb the inductor
energy while transitioning from full-load to no-load conditions without tripping the overvoltage fault protection.
When using high-capacitance, low-ESR capacitors (see
the Output-Capacitor Stability Considerations section),
the filter capacitor’s ESR dominates the output voltage
ripple. So the output capacitor’s size depends on the
maximum ESR required to meet the output-voltage-ripple (VRIPPLE(P-P)) specifications:
VRIPPLE(P-P) = RESRILOAD(MAX)LIR
In idle mode, the inductor current becomes discontinuous, with peak currents set by the idle-mode current-
______________________________________________________________________________________
23
MAX8716/MAX8717/MAX8757
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
sense threshold (VIDLE = 0.2VLIMIT). In idle mode, the
no-load output ripple can be determined as follows:
V
R
VRIPPLE(P−P) = IDLE ESR
RSENSE
The actual capacitance value required relates to the
physical size needed to achieve low ESR, as well as to
the chemistry of the capacitor technology. Thus, the
capacitor is usually selected by ESR and voltage rating
rather than by capacitance value (this is true of tantalums, OS-CONs, polymers, and other electrolytics).
When using low-capacity filter capacitors, such as
ceramic capacitors, size is usually determined by the
capacity needed to prevent V SAG and V SOAR from
causing problems during load transients. Generally,
once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge
is no longer a problem (see the VSAG and VSOAR equations in the Transient Response section). However, lowcapacity filter capacitors typically have high-ESR zeros
that may effect the overall stability (see the OutputCapacitor Stability Considerations section).
Output-Capacitor Stability Considerations
Stability is determined by the value of the ESR zero relative to the switching frequency. The boundary of instability is given by the following equation:
ƒ
ƒ ESR ≤ SW
π
where:
ƒ ESR =
1
2πRESR COUT
For a typical 300kHz application, the ESR zero frequency must be well below 95kHz, preferably below 50kHz.
Tantalum and OS-CON capacitors in widespread use
at the time of publication have typical ESR zero frequencies of 25kHz. In the design example used for
inductor selection, the ESR needed to support 25mVP-P
ripple is 25mV/1.5A = 16.7mΩ. One 220µF/4V Sanyo
polymer (TPE) capacitor provides 15mΩ (max) ESR.
This results in a zero at 48kHz, well within the bounds
of stability.
For low input-voltage applications where the duty cycle
exceeds 50% (VOUT / VIN ≥ 50%), the output ripple
voltage should not be greater than twice the internal
slope-compensation voltage:
VRIPPLE ≤ 0.02 x VOUT
where VRIPPLE equals ∆IINDUCTOR x RESR. The worstcase ESR limit occurs when VIN = 2 x VOUT, so the
24
above equation can be simplified to provide the following boundary condition:
RESR ≤ 0.04 x L x ƒOSC
Do not put high-value ceramic capacitors directly
across the feedback sense point without taking precautions to ensure stability. Large ceramic capacitors can
have a high-ESR zero frequency and cause erratic,
unstable operation. However, it is easy to add enough
series resistance by placing the capacitors a couple of
inches downstream from the feedback sense point,
which should be as close as possible to the inductor.
Unstable operation manifests itself in two related but
distinctly different ways: short/long pulses or cycle
skipping resulting in a lower switching frequency.
Instability occurs due to noise on the output or because
the ESR is so low that there is not enough voltage ramp
in the output voltage signal. This “fools” the error comparator into triggering too early or skipping a cycle.
Cycle skipping is more annoying than harmful, resulting
in nothing worse than increased output ripple.
However, it can indicate the possible presence of loop
instability due to insufficient ESR. Loop instability can
result in oscillations at the output after line or load
steps. Such perturbations are usually damped, but can
cause the output voltage to rise above or fall below the
tolerance limits.
The easiest method for checking stability is to apply a
very fast zero-to-max load transient and carefully
observe the output-voltage-ripple envelope for overshoot and ringing. It can help to simultaneously monitor
the inductor current with an AC current probe. Do not
allow more than one cycle of ringing after the initial
step-response under/overshoot.
Input Capacitor Selection
The input capacitor must meet the ripple-current
requirement (IRMS) imposed by the switching currents.
For an out-of-phase regulator, the total RMS current in
the input capacitor is a function of the load currents,
the input currents, the duty cycles, and the amount of
overlap as defined in Figure 9.
The 40/60 optimal interleaved architecture of the
MAX8716/MAX8717/MAX8757 allows the input voltage
to go as low as 8.3V before the duty cycles begin to
overlap. This offers improved efficiency over a regular
180° out-of-phase architecture where the duty cycles
begin to overlap below 10V. Figure 9 shows the inputcapacitor RMS current vs. input voltage for an application that requires 5V/5A and 3.3V/5A. This shows the
improvement of the 40/60 optimal interleaving over
50/50 interleaving and in-phase operation.
______________________________________________________________________________________
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
Power MOSFET Dissipation
Worst-case conduction losses occur at the duty-factor
extremes. For the high-side MOSFET (NH), the worstcase power dissipation due to resistance occurs at
minimum input voltage:
V
PD (NH RESISTIVE) = OUT (ILOAD )2RDS(ON)
VIN
Generally, use a small high-side MOSFET to reduce
switching losses at high input voltages. However, the
RDS(ON) required to stay within package power-dissipation limits often limits how small the MOSFET can be.
The optimum occurs when the switching losses equal
the conduction (RDS(ON)) losses. High-side switching
INPUT CAPACITOR RMS CURRENT
vs. INPUT VOLTAGE
5.0
4.5
4.0
IN PHASE
IRMS (A)
3.5
Power MOSFET Selection
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability
when using high-voltage (>20V) AC adapters. Low-current applications usually require less attention.
The high-side MOSFET (NH) must be able to dissipate
the resistive losses plus the switching losses at both
VIN(MIN) and VIN(MAX). Ideally, the losses at VIN(MIN)
should be roughly equal to the losses at VIN(MAX), with
lower losses in between. If the losses at VIN(MIN) are
significantly higher, consider increasing the size of NH.
Conversely, if the losses at VIN(MAX) are significantly
higher, consider reducing the size of NH. If VIN does
not vary over a wide range, optimum efficiency is
achieved by selecting a high-side MOSFET (N H) that
has conduction losses equal to the switching losses.
Choose a low-side MOSFET (NL) that has the lowest
possible on-resistance (RDS(ON)), comes in a moderate-sized package (i.e., 8-pin SO, DPAK, or D 2PAK),
and is reasonably priced. Ensure that the
MAX8716/MAX8717/MAX8757 DL_ gate driver can supply sufficient current to support the gate charge and the
current injected into the parasitic drain-to-gate capacitor caused by the high-side MOSFET turning on; otherwise, cross-conduction problems may occur. Switching
losses are not an issue for the low-side MOSFET since
it is a zero-voltage switched device when used in the
step-down topology.
MAX8716/MAX8717/MAX8757
For most applications, nontantalum chemistries (ceramic, aluminum, or OS-CON) are preferred due to their
resistance to power-up surge currents typical of systems with a mechanical switch or connector in series
with the input. Choose a capacitor that has less than
10°C temperature rise at the RMS input current for optimal reliability and lifetime.
50/50 INTERLEAVING
3.0
2.5
2.0
1.5
40/60 OPTIMAL
INTERLEAVING
1.0
0.5
5V/5A AND 3.3V/5A
0
8
6
10
12
14
16
18
20
VIN (V)
INPUT RMS CURRENT FOR INTERLEAVED OPERATION
IRMS =
(IOUT1 - IIN)2 (DLX1 - DOL) + (IOUT2 - IIN)2 (DLX2 - DOL) +
(IOUT1 + IOUT2 - IIN)2 DOL + IIN2 (1 - DLX1 - DLX2 + DOL)
V
DLX1 = OUT1
VIN
V
DLX2 = OUT2
VIN
DOL = DUTY-CYCLE OVERLAP FRACTION
V
I
+V
I
IIN = OUT1 OUT1 OUT2 OUT2
VIN
INPUT RMS CURRENT FOR SINGLE-PHASE OPERATION
(
IRMS = ILOAD VOUT (VIN - VOUT)
VIN
)
Figure 9. Input RMS Current
losses do not become an issue until the input is greater
than approximately 15V.
Calculating the power dissipation in high-side
MOSFETs (NH) due to switching losses is difficult, since
it must allow for difficult-to-quantify factors that influence the turn-on and turn-off times. These factors
include the internal gate resistance, gate charge,
threshold voltage, source inductance, and PC board
layout characteristics. The following switching-loss calculation provides only a very rough estimate and is no
substitute for breadboard evaluation, preferably including verification using a thermocouple mounted on NH:
PD (NH SWITCHING) =
⎛ VIN(MAX)ILOADfSW ⎞ ⎛ QG(SW) ⎞ COSS VIN2 fSW
⎜
⎟⎜ I
⎟ +
η TOTAL
2
⎝
⎠ ⎝ GATE ⎠
where COSS is the NH, MOSFET's output capacitance,
Q G(SW) 2 , is the change needed to turn on the
N H MOSFET, and I GATE is the peak gate-drive
source/sink current (1A typ).
______________________________________________________________________________________
25
MAX8716/MAX8717/MAX8757
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
Switching losses in the high-side MOSFET can become
a heat problem when maximum AC adapter voltages
are applied, due to the squared term in the switchingloss equation (C x VIN2 x fSW). If the high-side MOSFET
chosen for adequate RDS(ON) at low battery voltages
becomes extraordinarily hot when subjected to
V IN(MAX) , consider choosing another MOSFET with
lower parasitic capacitance.
For the low-side MOSFET (NL), the worst-case power
dissipation always occurs at maximum battery voltage:
⎡ ⎛ V
⎞⎤
PD (NL RESISTIVE) = ⎢1 − ⎜ OUT ⎟ ⎥(ILOAD )2 RDS(ON)
⎢ ⎝ VIN(MAX) ⎠ ⎥
⎣
⎦
The absolute worst case for MOSFET power dissipation
occurs under heavy-overload conditions that are
greater than ILOAD(MAX) but are not high enough to
exceed the current limit and cause the fault latch to trip.
To protect against this possibility, “overdesign” the circuit to tolerate:
⎛ ∆I
⎞
ILOAD = ILIMIT − ⎜ INDUCTOR ⎟
⎝
⎠
2
where ILIMIT is the peak current allowed by the currentlimit circuit, including threshold tolerance and senseresistance variation. The MOSFETs must have a
relatively large heatsink to handle the overload power
dissipation.
Choose a Schottky diode (DL) with a forward-voltage
drop low enough to prevent the low-side MOSFET’s
body diode from turning on during the dead time. As a
general rule, select a diode with a DC current rating
equal to 1/3rd of the load current. This diode is optional
and can be removed if efficiency is not critical.
Boost Capacitors
The boost capacitors (CBST) must be selected large
enough to handle the gate-charging requirements of
the high-side MOSFETs. Typically, 0.1µF ceramic
capacitors work well for low-power applications driving
medium-sized MOSFETs. However, high-current applications driving large, high-side MOSFETs require boost
capacitors larger than 0.1µF. For these applications,
select the boost capacitors to avoid discharging the
capacitor more than 200mV while charging the highside MOSFETs’ gates:
CBST =
26
QGATE
200mV
where QGATE is the total gate charge specified in the
high-side MOSFET’s data sheet. For example, assume
the FDS6612A n-channel MOSFET is used on the high
side. According to the manufacturer’s data sheet, a single FDS6612A has a maximum gate charge of 13nC
(VGS = 5V). Using the above equation, the required
boost capacitance would be:
CBST =
13nC
= 0.065µF
100mV
Selecting the closest standard value, this example
requires a 0.1µF ceramic capacitor.
Applications Information
Duty-Cycle Limits
Minimum Input Voltage
The minimum input operating voltage (dropout voltage)
is restricted by the maximum duty-cycle specification
(see the Electrical Characteristics table). For the best
dropout performance, use the slowest switching-frequency setting (200kHz, FSEL = GND). However, keep
in mind that the transient performance gets worse as
the step-down regulators approach the dropout voltage, so bulk output capacitance must be added (see
the voltage sag and soar equations in the Design
Procedure section). The absolute point of dropout
occurs when the inductor current ramps down during
the off-time (∆IDOWN) as much as it ramps up during
the on-time (∆IUP). This results in a minimum operating
voltage defined by the following equation:
⎛ 1
⎞
VIN(MIN) = VOUT + VCHG + h ⎜
− 1⎟ (VOUT + VDIS )
⎝ DMAX ⎠
where VCHG and VDIS are the parasitic voltage drops in
the charge and discharge paths, respectively. A reasonable minimum value for h is 1.5, while the absolute
minimum input voltage is calculated with h = 1.
Maximum Input Voltage
The MAX8716/MAX8717/MAX8757 controller includes a
minimum on-time specification, which determines the
maximum input operating voltage that maintains the
selected switching frequency (see the Electrical
Characteristics table). Operation above this maximum
input voltage results in pulse-skipping operation,
regardless of the operating mode selected by SKIP. At
the beginning of each cycle, if the output voltage is still
above the feedback threshold voltage, the controller
does not trigger an on-time pulse, effectively skipping a
cycle. This allows the controller to maintain regulation
______________________________________________________________________________________
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
• Route high-speed switching nodes (BST_, LX_, DH_,
and DL_) away from sensitive analog areas (REF,
FB_, CSH_, CSL_).
⎛
⎞
1
VIN(SKIP) = VOUT ⎜
⎟
⎝ ƒ OSC t ON(MIN) ⎠
1) Place the power components first, with ground terminals adjacent (NL_ source, CIN, COUT_, and DL_
anode). If possible, make all these connections on
the top layer with wide, copper-filled areas.
2) Mount the controller IC adjacent to the low-side
MOSFET, preferably on the back side opposite NL_
and NH_ to keep LX_, GND, DH_, and the DL_ gatedrive lines short and wide. The DL_ and DH_ gate
traces must be short and wide (50 mils to 100 mils
wide if the MOSFET is 1in from the controller IC) to
keep the driver impedance low and for proper adaptive dead-time sensing.
3) Group the gate-drive components (BST_ diode and
capacitor and LDO5 bypass capacitor) together
near the controller IC.
4) Make the DC-DC controller ground connections as
shown in Figures 1 and 10. This diagram can be
viewed as having two separate ground planes:
power ground, where all the high-power components go; and an analog ground plane for sensitive
analog components. The analog ground plane and
power ground plane must meet only at a single point
directly at the IC.
5) Connect the output power planes directly to the output filter capacitor positive and negative terminals
with multiple vias. Place the entire DC-DC converter
circuit as close to the load as is practical.
where fOSC is the switching frequency selected by FSEL.
PC Board Layout Guidelines
Careful PC board layout is critical to achieving low
switching losses and clean, stable operation. The
switching power stage requires particular attention
(Figure 10). If possible, mount all the power components on the top side of the board, with their ground
terminals flush against one another. Follow these guidelines for good PC board layout:
• Keep the high-current paths short, especially at the
ground terminals. This practice is essential for stable, jitter-free operation.
• Keep the power traces and load connections short.
This practice is essential for high efficiency. Using
thick copper PC boards (2oz vs. 1oz) can enhance
full-load efficiency by 1% or more. Correctly routing
PC board traces is a difficult task that must be
approached in terms of fractions of centimeters,
where a single mΩ of excess trace resistance causes a measurable efficiency penalty.
• Minimize current-sensing errors by connecting
CSH_ and CSL_ directly across the current-sense
resistor (RSENSE_).
• When trade-offs in trace lengths must be made, it is
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the lowside MOSFET or between the inductor and the output filter capacitor.
Layout Procedure
Chip Information
TRANSISTOR COUNT: 5879
PROCESS: BiCMOS
______________________________________________________________________________________
27
MAX8716/MAX8717/MAX8757
above the maximum input voltage, but forces the controller to effectively operate with a lower switching frequency. This results in an input threshold voltage at
which the controller begins to skip pulses (VIN(SKIP)):
MAX8716/MAX8717/MAX8757
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
CONNECT GND AND PGND TO THE
CONTROLLER AT ONE POINT
ONLY AS SHOWN
VIA TO POWER
GROUND
CONNECT THE
EXPOSED PAD TO
ANALOG GND
VIA TO VCC
BYPASS CAPACITOR
VIA TO REF
BYPASS CAPACITOR
VIA TO VCC PIN
VIA TO REF PIN
MAX8717/MAX8757
BOTTOM LAYER
MAX8717/MAX8757
TOP LAYER
KELVIN-SENSE VIAS
UNDER THE SENSE
RESISTOR
(REFER TO THE EVALUATION KIT)
INDUCTOR
SINGLE
n-CHANNEL
MOSFETS
INDUCTOR
DH
LX
DL
COUT
CIN
COUT
CIN
INPUT
HIGH-POWER LAYOUT
INPUT
OUTPUT
COUT
OUTPUT
GROUND
GROUND
LOW-POWER LAYOUT
Figure 10. PC Board Layout Example
28
DUAL
n-CHANNEL
MOSFET
______________________________________________________________________________________
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
24L QFN THIN.EPS
PACKAGE OUTLINE,
12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
21-0139
E
1
2
PACKAGE OUTLINE,
12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
21-0139
E
2
2
______________________________________________________________________________________
29
MAX8716/MAX8717/MAX8757
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Package Information (continued)
QFN THIN.EPS
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
30 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2005 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
MAX8716/MAX8717/MAX8757
MAX8716/MAX8717/MAX8757
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers