Application Note
PCIE-TH Series
Final Inch® Designs in
PCI Express Applications
Generation 2 – 5.0 Gbps
Revision Date: July 20, 2009
Copyrights and Trademarks
Copyright © 2009 Samtec, Inc.
Developed in conjunction with
Teraspeed Consulting Group LLC
Application Note
Series: PCIE-TH (thru-hole)
Standard: PCI Express, Generation 2
COPYRIGHTS, TRADEMARKS, and PATENTS
Final Inch® is a trademark of Samtec, Inc. Other product names used herein are
trademarks of their respective owners. All information and material in this
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Inc. does not authorize customers to make copies of the content for any use.
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Revision Date: 07/20/2009
1
Copyright 2009
Samtec/Teraspeed
Application Note
Series: PCIE-TH (thru-hole)
Standard: PCI Express, Generation 2
Abstract
PCI Express (PCIe) is primarily intended as a high performance serial interface targeted
for use in desktop, mobile, workstation, server, communications platforms, and
embedded devices. As with any modern high speed PCB design, the performance of an
actual PCI Express interconnect is highly dependent on the implementation. This paper
describes a measurement method applied to proven Samtec Final Inch® designs and this
industry standard to help engineers deploy systems of two PCB cards mated through
Samtec’s family of high speed electrical connectors. To demonstrate the feasibility of
using Samtec PCI Express connectors with standard FR4 epoxy PCBs, informative
interconnect loss and jitter values will be measured through Spice simulation and
presented in spreadsheet format. Also, trace lengths on the motherboard side of the PCIe
connector will be gradually increased to show the limits of compliance.
In order to ensure interoperability between PCI Express Generation 2 transmitter and
receiver devices, we will stress a typical interconnect design by stimulating their Spice
model components and devices with worst case data patterns as described in Section
4.3.6.2.4 of PCI Express Base Specification, Rev 2.0. This paper will cover techniques to
stress the system with reduced driver amplitude as well as max transmit jitter and noise
injection.
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Samtec/Teraspeed
Application Note
Series: PCIE-TH (thru-hole)
Standard: PCI Express, Generation 2
Introduction
Samtec has developed a full line of connector products that are designed to support serial
speeds greater than 5.0 Gbps, the “Baud rate” of each PCI Express Generation 2 data
lane. Working with Teraspeed Consulting, they have developed a complete breakout and
routing solution for each member of Samtec’s line of high speed connectors, called Final
Inch®. To demonstrate the feasibility of using Samtec PCIe connectors in PCI Express
applications with standard FR4 epoxy PCBs, informative interconnect loss and jitter
values will be measured through Spice simulation and presented in a user-friendly
spreadsheet format. Trace lengths will be varied to show the limits of compliance.
Analysis will consist of stimulating a typical trace-connector-trace circuit path with a
worst case signal and then observing the corresponding eye closure related to reflections
due to impedance discontinuities, loss, and stubs. Next, utility software will be used to
extract, analyze, and format Spice-measured voltage amplitudes and differential signal
crossing times. Mask violations (see Figure 2) will be recorded in pass/fail format.
Definitions
Interconnect Budget – The amount of loss and jitter that is allowed in the interconnect
and still meet the target specification.
Loss – The differential voltage swing attenuation from transmitter to receiver on the
trace. The trace is subject to resistive, dielectric, and skin effect loss. Loss increases as
trace length and and/or signal frequency increases. Vias and connectors also exhibit
losses which must be included in the interconnect budget. Total loss allowed in the
interconnect is 13.2 dB.
Jitter – The variation in the time between differential crossings from the ideal crossing
time. Jitter includes both data dependent and random contributions on the interconnect.
Total jitter allowed is 0.4UI, or 80 ps when UI = 200 ps.
PRBS – Pseudo Random Bit Sequence.
Tj – Total jitter, which is the convolution of the probability density functions for all the
jitter sources, Random jitter (Rj) and Deterministic jitter (Dj). The UI allocation is given
as the allowable Tj. The PCI Express specification does not specify allocation of Rj and
Dj.
UI – Unit Interval. The time interval required for transmission of one data symbol. For a
binary lane operating at 5.0 Gbps, the UI is 200 ps.
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Application Note
Series: PCIE-TH (thru-hole)
Standard: PCI Express, Generation 2
VDIFF – Differential voltage, defined as the difference of the positive conductor voltage
and the negative conductor voltage (VD+ - VD- ).
VDIFFp-p – Differential peak-to-peak voltage, defined by the following equations:
VDIFFp-p = (2*max | VD+ - VD- |) (Applies to a symmetric differential swing)
VDIFFp-p = (max | VD+ - VD- | { VD+ > VD-} + max | VD+ - VD- | { VD+ < VD-})
(Applies to a asymmetric differential swing)
The PCI Express Specification
PCI Express links are based on recent advances in point-to-point interconnect technology.
A PCI Express link is comprised of a dual-simplex communications channel between two
components physically consisting of two low-voltage, differential signal pairs. The PCI
Express Base Specification defines one half of a link (one transmitter and receiver) an
electrical sub-block. The design model used for this paper is of three electrical sub-blocks
operating in tandem, the victim surrounded by multiple aggressors, with all bit streams
heading in the same direction.
Detailed specifications for an electrical sub-block can be found in the PCI Express 2.0
Base Specification and will be referred to throughout the rest of this paper1. Measurement
techniques specified in this section have been rigidly adhered to including the
requirement for finding the median within the jitter for use in jitter measurements.
1
The PCI Express Base 2.0 specification is available for purchase though the PCI Sig organization
(http://www.pcisig.com/specifications/ordering_information).
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Samtec/Teraspeed
Application Note
Series: PCIE-TH (thru-hole)
Standard: PCI Express, Generation 2
Setup and Measurement
Input Stimulus Setup
A PRBS 27-1 pattern was used for victim stimulus pair and a repeating 1010… pattern
used for the aggressor pairs surrounding the victim pair. Teraspeed has developed its own
stimulus conversion tool that has the capability to selectively de-emphasize and/or add
jitter to the HSPICE stimulus output, such as a vector file. This was used to add enough
jitter and de-emphasis to just meet worst case PCI Express Generation 2 transmit jitter
specifications.
The Test Circuit Model
The test circuit modeled is shown in Figure 1. It consists of the following:
•
•
•
•
One set of Teraspeed behavioral driver models with programmable edge rate,
amplitude, and de-emphasis.
One set of six AC coupling capacitors, value = 100 nF
1 PCI Express Final Inch™ design, comprised of the PCIe connector model
surrounded by the Samtec’s BOR models, lossy trace models and SMA
connector models on both sides of the connector.
50 Ohm termination resistors to Ground (as required per Section 4.3.4 of the PCI
Express Base Specification, Rev 2.0.
Edge
Card
PCIe Receiver SMAs
Termination
Uncoupled Lossy Traces
AC PCIe Driver SMAs
Caps
PCIe
Connector
Uncoupled Lossy Traces
Motherboard
Figure 1 - PCI Express Test Circuit
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Samtec/Teraspeed
Application Note
Series: PCIE-TH (thru-hole)
Standard: PCI Express, Generation 2
Figure 2a – X-Ray image of PCIe thru-hole connector section with edge card installed
A
A
V
V
A
A
Card edge
Figure 2b – PCIe edge card connector pad pattern. V = Victim, A = Aggressor
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Application Note
Series: PCIE-TH (thru-hole)
Standard: PCI Express, Generation 2
Procedure
Interconnect Budget
The interconnect budget can be best illustrated by the mask shown in Figure 3. In order to
pass the PCI Express constraints for loss and jitter, the simulated eye waveform must not
touch any location within the grey areas shown. Calculated interconnect budget values
are shown in Table 1.
Figure 3 - Example eye mask template
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Samtec/Teraspeed
Application Note
Series: PCIE-TH (thru-hole)
Standard: PCI Express, Generation 2
Driver at Package
Pin
Receiver at
Package Pin
Interconnect
budget:
Low Power Differential
Maximum Loss,
A1 to –A1
(See example mask
template) (VDIFFp-p)
Normal Power Differential
Maximum Loss,
A1 to –A1
(See example mask
template) (VDIFFp-p)
Minimum Eye
Width,
X1 to 1-X1
(See example mask
template) (UIp-p)
0.400
0.800
0.75
0.120
0.120
0.602
10.5 dB loss
16.5 dB loss1
0.15 UI
(30ps when UI =
200 ps)
Table 1 - PCI Express Gen 2 interconnect budgets: max loss and min eye width calculated values
1
The worst case operational loss budget at 2.5 GHz Nyquist frequency is calculated by
taking the minimum driver output voltage (VTX-DIFFp-p = 800 mV) divided by the
minimum input voltage to the receiver (VRX-DIFFp-p = 175 mV). 175/800 = .219, which
after conversion results in a maximum loss budget of 13.2 dB.
2
Minimum width pulse at Rx after accounting for worst Tj at 10-12 BER. See Table 4-12
in the PCI Express Base Specification, Revision 2.0.
Transmitter Compliance Measurements
Setup for Tj for UI Measurements
Before the PCI Express circuit model can be simulated and measured, we must first set
up the driver stimulus to provide minimum TX eye width (maximum jitter) and minimum
amplitude for both low power and regular power driver models. As mentioned in the
previous section, the driver stimulus’ jitter can be adjusted until it just reaches the
maximum total jitter allowed under the compliance load shown in the figure below. The
AC coupling capacitor CTX can be set anywhere between 75pF and 200pF. We set CTX to
100nF for all simulations because it is a popular value in the industry. Table 2 shows the
resulting output measurements. The eye pattern generated in the PCI Express driver
compliance test simulation can be found in Appendix A, Picture 1, of this paper.
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Samtec/Teraspeed
Application Note
Series: PCIE-TH (thru-hole)
Standard: PCI Express, Generation 2
D+ Package
Pin
C = 100 nF
TX
Driver
C = 100 nF
D- Package
Pin
R = 50 Ω
R = 50 Ω
Figure 4 - PCI Express Compliance Test/Measurement load
Vdiffp-p
Deemphasis
0dB (Low Specification
Power) Measured
Specification
-3 dB
Measured
Specification
-4 dB
Measured
Specification
-5.5 dB
Measured
Specification
-6.5 dB
Measured
Transition
Bit
≥400 mV
1
401 mV
≥800 mV
1
800 mV
≥800 mV
1
800 mV
≥800 mV
1
800 mV
≥800 mV
1
800 mV
De-emphasized
Bit
None
≥566 mV
566 mV
≤505 mV
505 mV
≥425 mV
425 mV
≤378 mV
378 mV
Total Jitter Edge Rate
≤0.25 UI,
≥0.15 UI,
measured at measured
crossings 20% to 80%
≥30ps
≤50 ps
34ps
46 ps
≥30ps
≤50 ps
30ps
49 ps
≥30ps
≤50 ps
30ps
49 ps
≥30ps
≤50 ps
30ps
49 ps
≥30ps
≤50 ps
30 ps
49 ps
Table 2 - PCI Express TX Silicon + Package Measurements at Package Pin
1
The PCI Express Base Specification defines X2 to 1-X2 = 0. The minimum TX height
measurements were taken at mid bit.
Revision Date: 07/20/2009
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Samtec/Teraspeed
Application Note
Series: PCIE-TH (thru-hole)
Standard: PCI Express, Generation 2
Measurements at the Receiver
Notes:
1.) The total trace length specified is the sum of the mother board and daughter card
differential traces as shown in Figure 1. Both trace lengths are equal in each
simulation.
2.) For each of the following tables, the eye patterns generated in the PCI Express
circuit simulation with the maximum allowable total trace length in each of the
following table can be found in Appendix A of this paper.
PCIE-TH
Connector with
Final Inch
Design
Specification
5.0" total trace
10.0" total trace
15.0" total trace
20.0" total trace
25.0" total trace
27.0" total trace
29.0" total trace
30.0" total trace
Min RX Differential
Voltage, A1 to –A11
(See example mask
template)
≥120 mVDIFFp-p
296 mV
250 mV
207 mV
171 mV
143 mV
135 mV
121 mV
117 mV
Min RX Eye Width,
X1 to 1-X1 (See
example mask
template)
≥120 ps
151 ps
148 ps
143 ps
138 ps
129 ps
125 ps
120 ps
118 mV
Pass/Fail
Pass
Pass
Pass
Pass
Pass
Pass
Pass
Fail
Table 3 - PCI Express Connector Far-end Measurements, Low Power Driver.
PCIE-TH
Connector with
Final Inch
Design
Specification
10.0" total trace
20.0" total trace
30.0" total trace
40.0" total trace
41.0" total trace
42.0" total trace
43.0" total trace
Min RX Differential
Voltage, A1 to –A11
(See example mask
template)
≥120 mVDIFFp-p
384 mV
321 mV
237 mV
168 mV
162 mV
157 mV
149 mV
Min RX Eye Width,
X1 to 1-X1 (See
example mask
template)
≥120 ps
151 ps
151 ps
139 ps
123 ps
122 ps
120 ps
119 ps
Pass/Fail
Pass
Pass
Pass
Pass
Pass
Pass
Fail
Table 4 - PCI Express Connector Far-end Measurements, Normal Driver with -3dB de-emphasis.
Revision Date: 07/20/2009
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Samtec/Teraspeed
Application Note
Series: PCIE-TH (thru-hole)
Standard: PCI Express, Generation 2
PCIE-TH
Connector with
Final Inch
Design
Specification
10.0" total trace
20.0" total trace
30.0" total trace
40.0" total trace
45.0" total trace
47.0" total trace
48.0" total trace
49.0" total trace
Min RX Differential
Voltage, A1 to –A11
(See example mask
template)
≥120 mVDIFFp-p
344 mV
320 mV
244 mV
181 mV
154 mV
142 mV
136 mV
132 mV
Min RX Eye Width,
X1 to 1-X1 (See
example mask
template)
≥120 ps
149 ps
149 ps
144 ps
133 ps
126 ps
122 ps
121 ps
119 ps
Pass/Fail
Pass
Pass
Pass
Pass
Pass
Pass
Pass
Fail
Table 5 - PCI Express Connector Far-end Measurements, Normal Driver with -4dB de-emphasis.
PCIE-TH
Connector with
Final Inch
Design
Specification
10.0" total trace
20.0" total trace
30.0" total trace
40.0" total trace
50.0" total trace
55.0" total trace
56.0" total trace
57.0" total trace
Min RX Differential
Voltage, A1 to –A11
(See example mask
template)
≥120 mVDIFFp-p
292 mV
282 mV
259 mV
198 mV
147 mV
125 mV
122 mV
117 mV
Min RX Eye Width,
X1 to 1-X1 (See
example mask
template)
≥120 ps
146 ps
146 ps
146 ps
143 ps
134 ps
126 ps
124 ps
121 ps
Pass/Fail
Pass
Pass
Pass
Pass
Pass
Pass
Pass
Fail
Table 6 - PCI Express Connector Far-end Measurements, Normal Driver with -5.5dB de-emphasis.
Revision Date: 07/20/2009
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Samtec/Teraspeed
Application Note
Series: PCIE-TH (thru-hole)
Standard: PCI Express, Generation 2
PCIE-TH
Connector with
Final Inch
Design
Specification
10.0" total trace
20.0" total trace
30.0" total trace
40.0" total trace
50.0" total trace
55.0" total trace
57.0" total trace
59.0" total trace
60.0" total trace
Min RX Differential
Voltage, A1 to –A11
(See example mask
template)
≥120 mVDIFFp-p
263 mV
261 mV
243 mV
204 mV
158 mV
137 mV
130 mV
121 mV
119 mV
Min RX Eye Width,
X1 to 1-X1 (See
example mask
template)
≥120 ps
144 ps
144 ps
144 ps
142 ps
138 ps
136 ps
133 ps
129 ps
128 ps
Pass/Fail
Pass
Pass
Pass
Pass
Pass
Pass
Pass
Pass
Fail
Table 7 - PCI Express Connector Far-end Measurements, Normal Driver with -6.5dB de-emphasis.
Conclusions
When used with Samtec’s Final Inch® differential routing, breakout, and trace width
solution, a single Samtec PCIe connector in a motherboard to daughter card configuration
can be used to transfer PCI Express lanes with total trace lengths up to:
•
•
•
•
•
29 inches in low power driver mode.
42 inches when using a normal driver with -3 dB de-emphasis.
48 inches when using a normal driver with -4 dB de-emphasis.
56 inches when using a normal driver with -5.5 dB de-emphasis.
59 inches when using a normal driver with -6.5 dB de-emphasis.
Recommendations
Designers should be aware that using smaller trace widths, laminates with higher loss
tangent, and sub optimal routing solutions with higher pair-to-pair coupling and
additional via stubs will decrease overall performance and the maximum allowable trace
length. It is advisable, when designing systems that approach the maximum trace length
limits, to perform detailed modeling, simulation, and measurement of the target design
including the effects of material properties, traces, vias, and additional components.
Revision Date: 07/20/2009
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Samtec/Teraspeed
Application Note
Series: PCIE-TH (thru-hole)
Standard: PCI Express, Generation 2
Appendix A – Waveform images
Picture A1 – Example of worst case stimulus eye waveform, probed at Teraspeed driver behavioral
model nodes connected to PCIe compliance test/measurement load. Low power setting.
Picture A2 – Example of worst case stimulus measurement, probed at Teraspeed driver behavioral
model nodes connected to PCIe compliance test/measurement load. Low power setting.
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Samtec/Teraspeed
Application Note
Series: PCIE-TH (thru-hole)
Standard: PCI Express, Generation 2
Picture A3 – Receiver eye measurement, probed at far end termination. Low power driver setting
with 0 dB de-emphasis. Total trace length = 29 inches.
Picture A4 – Receiver eye measurement, probed at far end termination. Normal power driver setting
with -3 dB de-emphasis. Total trace length = 42 inches.
Revision Date: 07/20/2009
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Application Note
Series: PCIE-TH (thru-hole)
Standard: PCI Express, Generation 2
Picture A5 – Receiver eye measurement, probed at far end termination. Normal power driver setting
with -4 dB de-emphasis. Total trace length = 48 inches.
Picture A6 – Receiver eye measurement, probed at far end termination. Normal power driver setting
with -5.5 dB de-emphasis. Total trace length = 56 inches
Revision Date: 07/20/2009
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Application Note
Series: PCIE-TH (thru-hole)
Standard: PCI Express, Generation 2
Picture A7 – Receiver eye measurement, probed at far end termination. Standard driver setting with
-6.5 dB de-emphasis. Total trace length = 59 inches.
Revision Date: 07/20/2009
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