Application Note
DP Array™ DPAM/DPAF Final Inch®
Designs in XAUI Applications
10mm Stack Height
REVISION DATE: January 11, 2005
Copyrights and Trademarks
Copyright © 2005 Samtec, Inc.
Developed in conjunction with
Teraspeed Consulting Group LLC
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Abstract
The 10 Gigabit Attachment Unit Interface (XAUI ) is primarily intended as a point-topoint interface of up to approximately 50 cm (19.685 inches) between integrated circuits
using controlled impedance traces on low-cost printed circuit boards (PCBs). As with any
modern high speed PCB design, the performance of an actual XAUI interconnect is
highly dependent on the implementation. This paper describes a measurement method
applied to proven Samtec Final Inch® designs and this industry standard to help
engineers deploy systems of two PCB cards mated through Samtec’s family of high
speed electrical connectors. To demonstrate the feasibility of using Samtec DP Array™
connectors with standard FR4 epoxy PCBs, informative interconnect loss and jitter values
will be measured through Spice simulation and presented in spreadsheet format. Also,
trace lengths on each side of the DPAM/DPAF Series connector will be gradually
increased to show the limits of compliance.
In order to ensure interoperability between XAUI transmitter and receiver devices, we
will stress a typical interconnect design by stimulating their Spice model components and
devices with stressed data patterns. This paper will cover techniques to stress the system
with reduced driver amplitude as well as jitter injection.
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Introduction
Samtec has developed a full line of connector products that are designed to support serial
speeds up to and greater than 3.125 Gb/ps, the “Baud rate” of each XAUI data lane.
Working with Teraspeed Consulting, they have developed a complete breakout and
routing solution for each member of Samtec’s line of high speed connectors, called Final
Inch®. To demonstrate the feasibility of using Samtec DP Array™ series connectors in
XAUI applications with standard FR4 epoxy PCBs, informative interconnect loss and
jitter values will be measured through Spice simulation and presented in a user-friendly
spreadsheet format. Trace lengths will be varied to show the limits of compliance.
Analysis will consist of stimulating a typical trace-connector-trace circuit path with a
worst case signal and then observing the corresponding eye closure related to reflections
due to impedance discontinuities, loss, and stubs. Next, utility software will be used to
extract, analyze, and format Spice-measured voltage amplitudes and differential signal
crossing times. Mask violations (see Figure 3) will be recorded in pass/fail format.
Definitions
Interconnect Budget – The amount of loss and jitter that is allowed in the interconnect
and still meet the target specification.
Loss – The differential voltage swing attenuation from transmitter to receiver on the
trace. The trace is subject to resistive, dielectric, and skin effect loss. Loss increases as
trace length and and/or signal frequency increases. Vias and connectors also exhibit
losses which must be included in the interconnect budget. Total loss allowed in the XAUI
interconnect is -12.0dB.
Jitter – The variation in the time between differential crossings from the ideal crossing
time. Jitter includes both data dependent and random contributions on the interconnect.
Total jitter allowed in the XAUI interconnect is +/-0.275UI, or +/-88 ps when UI = 320
ps.
PRBS – Pseudo Random Bit Sequence.
Tj – Total jitter, which is the convolution of the probability density functions for all the
jitter sources, Random jitter (Rj) and Deterministic jitter (Dj). The UI allocation is given
as the allowable Tj.
UI – Unit Interval. The time interval required for transmission of one data symbol. For a
binary lane operating at 3.125 Gbps, the UI is 320 ps.
VDIFF – Differential voltage, defined as the difference of the positive conductor voltage
and the negative conductor voltage (VD+ - VD- ).
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VDIFFp-p – Differential peak-to-peak voltage, defined by the following equations:
VDIFFp-p = (2*max | VD+ - VD- |) (Applies to a symmetric differential swing)
VDIFFp-p = (max | VD+ - VD- | { VD+ > VD-} + max | VD+ - VD- | { VD+ < VD-})
(Applies to a asymmetric differential swing)
The XAUI Specification
XAUI links are based on recent advances in point-to-point interconnect technology. A
XAUI lane is comprised of a dual-simplex communications channel between two
components physically consisting of two low-voltage, differential signal pairs. Four of
these lanes are used to convey 32-bit self-clocking data and control, each at a nominal
rate of 3.125 GBaud resulting in a 10 Gb/ps effective data rate.
The XAUI specification uses the name “byte stream” to describe one half of a data lane.
The design model used for this paper is of three byte streams operating in tandem, one
the victim surrounded by 2 aggressors, with all bit streams heading in the same direction
and passing through the connector on adjacent pin pairs.
Detailed specifications for the XAUI electrical sub-block can be found starting in Section
47 of IEEE 802.3ae™ Specification. Relevant timing and voltage constraints from this
section of the specification will be referred to throughout the rest of this paper.
Setup and Measurement
Input Stimulus Setup
A PRBS 27-1 pattern was used for victim stimulus and a repeating 1010… pattern used
for the aggressor differential pairs on each side of the victim differential pair. Xilinx
supplies a stimulus generator tool kit within their VirtexII Pro™ design kit giving
customers complete control over the amount of jitter in the transmitter’s data output.
Using their stimulus system with their RocketIO™ multi-gigabit serial transceiver model,
enough total jitter was added to the driver output to just meet worst case XAUI transmit
jitter specifications. The slow-slow corner silicon model was used to come as close as
possible to the minimum differential VDIFF output specification.
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The Test Circuit Model
The test circuit modeled is shown in Figure 1. It consists of the following:
•
•
•
•
•
One set of three of Xilinx Virtex-II Pro™ serial transceiver models configured as
XAUI drivers.
Xilinx FPGA flip-chip package model.
1 Samtec DP Array™ Final Inch® design comprised of DPAM-23-10-H-8-1 and
DPAF-23-01-H-8-1 10mm stack height connector models surrounded by the
Samtec’s BOR models, lossy trace models, and SMA connector models on both
sides of the connector.
One set of six AC coupling capacitors, value = 100 nF.
100 Ohm termination resistors.
Xilinx Drivers
/w Package
Stimulus
SMAs
Side 2
Differential Trace Pairs Vias
DPAM
Side 1
Side 1
Differential Traces Pairs
DPAF
Vias
Side 2
AC coupling
Caps
SMAs
Termination
Figure 1 - XAUI Test Circuit
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DP Array(TM) 168 pin differential pair connector routing assignment for DPAM
DPAF connector flips routing
pattern.
Across connectors:
Layer 3 connects to Layer 10
Layer 5 connects to Layer 8
Layer 8 connects to Layer 5
Differential Routed
and modeled area.
A
Ground Pins
A
A
A
A
A
A
A
A
A
Layer 8 (driven by Layer 1 SMA)
A
Layer 5 (Driven by layer 12 SMA)
Layer 3 (Driven by Layer 12 SMA)
V
Victim net
A
Aggressor net
A
A
A
V
A
A
A
V
A
A
A
A
A
A
A
A
A
Edge of Card
One pattern with 21 differential pairs instrumented
42 Total SMA's per card
Figure 2 - DPAM/DPAF Series Differential Connector Pin Pattern
Procedure
Interconnect Budget
The interconnect budget can be best illustrated by the mask shown in Figure 3. In order to
pass the XAUI constraints for loss and jitter, the simulated eye waveform must not touch
any location within the grey areas shown. Calculated interconnect budget values are
shown in Table 1.
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Figure 3—Example mask template
Symbol
X1
X2
A1
A2
Near-end value
+/-56
124.8
400
800
Far-end value
+/-88
128
100
800
Units
psec
psec
mV
mV
Table 1 – Driver template intervals at 3.125 Gb/ps
Driver at Package Pin
Receiver at Package Pin
Interconnect budget:
Maximum Loss,
A1 to –A1
(See example
mask template)
(mVDIFFp-p)
800
200
12.04 dB loss1
Minimum Eye Width,
X1 to 1-X1
(See example mask template)
(UIp-p)
0.65
0.45
0.2 UIp-p (64ps when UI=320 ps)
Table 2 – XAUI interconnect budget max loss and min eye width calculated values
1
The worst case operational loss budget at 1.5625 GHz Nyquist frequency is
calculated by taking the minimum driver output voltage (VTX-DIFF = 800 mV)
divided by the minimum input voltage to the receiver (VRX-DIFF = 200 mV).
200/800 = .25, which after conversion results in a maximum loss budget of 12.04
dB.
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Transmitter Compliance Measurements
Setup for Tj for UI Measurements
As mentioned in the previous section, the driver stimulus’ jitter was adjusted until the
transmitter exhibited the maximum total jitter allowed by the XAUI specification at the
driver package pins under the compliance load shown in Figure 4 below. The XAUI
specification does not specify the range of capacitor values allowed for the AC coupling
capacitors. We set C to 100nF for all simulations because it is a popular value in the
industry. Table 3 shows the resulting output measurements.
D+ Package
Pin
C = 100 nF
TX
Silicon +
Package
C = 100 nF
D- Package
Pin
R = 100 Ω
Figure 4 – XAUI Compliance Test/Measurement load
1
Specification
Measured
Vp-p
Total Jitter
≥800 mV ≤ ±56 psec
800.2 mV ±55.9 psec
Table 3 – XAUI TX Silicon + Package Measurements at Package Pin
1
X2 to 1-X2, the TX mid bit sample time, is 70.4 psec when UI = 320 psec.
The eye pattern generated in the XAUI driver compliance test simulation can be found in
Appendix A of this paper, picture #1.
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Full Circuit Compliance Measurements
Differential Voltage and Eye Width Measurements at Receiver End
Specification
≤ ±88 psec
≥112 psec
Min Rx Differential
Voltage, A1 to –A12
(See example mask
template)
≥200mVDIFFp-p
10" total trace3
20" total trace
30" total trace
40" total trace
41" total trace
42" total trace
43" total trace
44" total trace
±61.8
±58.9
±61.0
±70.9
±71.6
±71.2
±72.3
±73.3
308.4
305.6
292.4
263.6
261.5
259.4
256.3
253.3
667.4
488.2
372.6
237.6
228.6
216.4
201.8
187.0
DPAM/DPAF
Connector, 10
mm Stack
Max Jitter1 at
UI = 320 psec
Height
Min RX Eye Width,
X1 to 1-X1 (See
example mask
template)
Pass/Fail
Pass
Pass
Pass
Pass
Pass
Pass
Pass
Fail
Table 4 – XAUI Measurements at Receiver End, 10mm stack height
1
XAUI jitter requirements are specified as peak from the mean. These value
assume symmetrical jitter distributions from the mean.
2
X2 to 1-X2, the RX mid bit sample time, is 64 psec when UI = 320 psec.
3
The total trace length specified is the sum of the two differential trace lengths in
the DPAM/DPAF test fixture model, as shown in Figure 1. These traces are
always kept equal in length in each simulation.
The eye pattern generated in the XAUI circuit simulation with 43 inches total trace length
can be found in Appendix A of this paper, picture #2.
Conclusions
A single Samtec DP Array™ DPAM/DPAF Series 10mm stack height connector in a
board-to-board configuration can be used in XAUI systems with total trace lengths not to
exceed 43 inches when used with Samtec’s Final Inch® routing, breakout, and trace
width solutions. Because loss is the dominant contributor to system degradation,
designers should be aware that using smaller trace widths, laminates with higher loss
tangent, and sub optimal routing solutions with higher pair-to-pair coupling and
additional via stubs will decrease overall performance and the maximum allowable trace
length. It is advisable when designing systems that approach the maximum jitter limits to
perform detailed modeling, simulation, and measurement of the target design including
the effects of material properties, traces, vias, and additional components.
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Appendix A – Waveform images
Picture 1 – Worst case stimulus differential eye waveform, probed at Xilinx driver package pins,
connected to compliance test/measurement load. Driver set for 33% de-emphasis.
Picture 2 – XAUI circuit differential eye waveform, probed at terminator pins, 43 inches total trace
length, 3.125 Gbps data rate
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