Application Note Q Strip® QTE/QSE Series 16mm Stack Height Final Inch® Designs in XAUI Applications Revision Date: July 29, 2005 Copyrights and Trademarks Copyright © 2005 Samtec, Inc. Developed in conjunction with Teraspeed Consulting Group LLC Application Note Series: QTE/QSE Series, 16mm Stack Height Standard: XAUI COPYRIGHTS, TRADEMARKS, and PATENTS Q Strip® and Final Inch® are trademarks of Samtec, Inc. Other product names used herein are trademarks of their respective owners. All information and material in this publication are property of Samtec, Inc. All related rights are reserved. Samtec, Inc. does not authorize customers to make copies of the content for any use. Terms of Use Use of this publication is limited to viewing the pages for evaluation or purchase. No permission is granted to the user to copy, print, distribute, transmit, display in public, or modify the contents of this document in any way. Disclaimer The information in this publication may change without notice. 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Revision Date: 7/29/2005 1 Copyright 2005 Samtec/Teraspeed Application Note Series: QTE/QSE Series, 16mm Stack Height Standard: XAUI Abstract The 10 Gigabit Attachment Unit Interface (XAUI ) is primarily intended as a point-topoint interface of up to approximately 50 cm (19.685 inches) between integrated circuits using controlled impedance traces on low-cost printed circuit boards (PCBs). As with any modern high speed PCB design, the performance of an actual XAUI interconnect is highly dependent on the implementation. This paper describes a measurement method applied to proven Samtec Final Inch® designs and this industry standard to help engineers deploy systems of two PCB cards mated through Samtec’s family of high speed electrical connectors. To demonstrate the feasibility of using Samtec QTE/QSE series connectors with standard FR4 epoxy PCBs, informative interconnect loss and jitter values will be measured through SPICE simulation and presented in spreadsheet format. Also, trace lengths leading to each of the QTE/QSE series connectors will be gradually increased to show the limits of compliance. In order to ensure interoperability between XAUI transmitter and receiver devices, we will stress a typical interconnect design by stimulating their SPICE model components and devices with stressed data patterns. This paper will cover techniques to stress the system with reduced driver amplitude as well as jitter injection. Introduction Samtec has developed a full line of connector products that are designed to support serial speeds up to and greater than 3.125 Gb/ps, the “Baud rate” of each XAUI data lane. Working with Teraspeed Consulting, they have developed a complete breakout and routing solution for each member of Samtec’s line of high speed connectors, called Final Inch®. To demonstrate the feasibility of using Samtec QTE/QSE series connectors in XAUI applications with standard FR4 epoxy PCBs, informative interconnect loss and jitter values will be measured through SPICE simulation and presented in a user-friendly spreadsheet format. Trace lengths will be varied to show the limits of compliance. Analysis will consist of stimulating a typical trace-connector-trace circuit path with a worst case signal and then observing the corresponding eye closure related to reflections due to impedance discontinuities, loss, and stubs. Next, utility software will be used to extract, analyze, and format SPICE-measured voltage amplitudes and single-endedsignal crossing times. Mask violations (see Figure 3) will be recorded in pass/fail format. Revision Date: 7/29/2005 2 Copyright 2005 Samtec/Teraspeed Application Note Series: QTE/QSE Series, 16mm Stack Height Standard: XAUI Definitions Interconnect Budget – The amount of loss and jitter that is allowed in the interconnect and still meet the target specification. Loss – The single-endedvoltage swing attenuation from transmitter to receiver on the trace. The trace is subject to resistive, dielectric, and skin effect loss. Loss increases as trace length and and/or signal frequency increases. Vias and connectors also exhibit losses which must be included in the interconnect budget. Total loss allowed in the XAUI interconnect is -12.0dB. Jitter – The variation in the time between single-endedcrossings from the ideal crossing time. Jitter includes both data dependent and random contributions on the interconnect. Total jitter allowed in the XAUI interconnect is +/-0.275UI, or +/-88 ps when UI = 320 ps. PRBS – Pseudo Random Bit Sequence. Tj – Total jitter, which is the convolution of the probability density functions for all the jitter sources, Random jitter (Rj) and Deterministic jitter (Dj). The UI allocation is given as the allowable Tj. UI – Unit Interval. The time interval required for transmission of one data symbol. For a binary lane operating at 3.125 Gbps, the UI is 320 ps. VDIFF – Differential voltage, defined as the difference of the positive conductor voltage and the negative conductor voltage (VD+ - VD- ). VDIFFp-p – Differential peak-to-peak voltage, defined by the following equations: VDIFFp-p = (2*max | VD+ - VD- |) (Applies to a symmetric differential swing) VDIFFp-p = (max | VD+ - VD- | { VD+ > VD-} + max | VD+ - VD- | { VD+ < VD-}) (Applies to a asymmetric differential swing) Revision Date: 7/29/2005 3 Copyright 2005 Samtec/Teraspeed Application Note Series: QTE/QSE Series, 16mm Stack Height Standard: XAUI The XAUI Specification XAUI links are based on recent advances in point-to-point interconnect technology. A XAUI lane is comprised of a dual-simplex communications channel between two components physically consisting of two low-voltage, differential signal pairs. Four of these lanes are used to convey 32-bit self-clocking data and control, each at a nominal rate of 3.125 GBaud resulting in a 10 Gb/ps effective data rate. The XAUI specification uses the name “byte stream” to describe one half of a data lane. The design model used for this paper is of three byte streams operating in tandem, one the victim surrounded by 2 aggressors, with all bit streams heading in the same direction and passing through the connector on adjacent pin pairs. Detailed specifications for the XAUI electrical sub-block can be found starting in Section 47 of IEEE 802.3ae™ Specification. Relevant timing and voltage constraints from this section of the specification will be referred to throughout the rest of this paper. Setup and Measurement Input Stimulus Setup A PRBS 27-1 pattern was used for victim stimulus and a repeating 1010… pattern used for the aggressor stimulus for the differential pairs on each side of the victim differential pair. Xilinx supplies a stimulus generator tool kit within their VirtexII Pro™ design kit giving customers complete control over the amount of jitter in the transmitter’s data output. Using their stimulus generator system along with their RocketIO™ multi-gigabit serial transceiver model, just the right amount of total jitter was added to the driver output to barely meet worst case XAUI transmit jitter specifications. The slow-slow corner silicon SPICE model was used to come as close as possible to the minimum single-ended VDIFF output specification. The Test Circuit Model The test circuit modeled is shown in Figure 1. It consists of the following: • One set of three of Xilinx Virtex-II Pro™ serial transceiver models configured as XAUI drivers. • Xilinx FPGA flip-chip package model. • 1 Samtec Q Strip® QTE/QSE Series Final Inch® design, comprised of the QTE020-04-L-D-A/QSE-020-01-L-D-A 16mm stack height connector models surrounded by the Samtec’s BOR models, lossy trace models, and SMA connector models on both sides of the connector. • One set of six AC coupling capacitors, value = 100 nF. • 100 Ohm termination resistors. Revision Date: 7/29/2005 4 Copyright 2005 Samtec/Teraspeed Application Note Series: QTE/QSE Series, 16mm Stack Height Standard: XAUI Xilinx Drivers /w Package Stimulus SMAs Side 2 Differential Trace Pairs Vias QTE Side 1 Side 1 Differential Traces Pairs QSE Vias Side 2 AC coupling Caps SMAs Termination Figure 1 - XAUI Test Circuit A A V V A A Figure 2 – QTE/QSE single-ended connector pin pattern. A = Aggressor pair. V = Victim pair. Black = Grounded pin. Revision Date: 7/29/2005 5 Copyright 2005 Samtec/Teraspeed Application Note Series: QTE/QSE Series, 16mm Stack Height Standard: XAUI Procedure Interconnect Budget The interconnect budget can be best illustrated by the mask shown in Figure 2. In order to pass the XAUI constraints for loss and jitter, the simulated eye waveform must not touch any location within the grey areas shown. Calculated interconnect budget values are shown in Table 1. Figure 3 – Example mask template Symbol X1 X2 A1 A2 Near-end value 56 124.8 400 800 Far-end value 88 128 100 800 Units psec psec mV mV Table 1—Driver template intervals at 3.125 Gbps Driver at Package Pin Receiver at Package Pin Interconnect budget: Maximum Loss, A1 to –A1 (See example mask template) (VDIFFp-p) 0.800 0.200 12.04 dB loss1 Minimum Eye Width, X1 to 1-X1 (See example mask template) (UIp-p) 0.65 0.45 0.2 UIp-p (64ps when UI=320 ps) Table 2—XAUI interconnect budget max loss and min eye width calculated values 1 The worst case operational loss budget at 1.5625 GHz Nyquist frequency is calculated by taking the minimum driver output voltage (VTX-DIFF = 800 mV) divided by the minimum input voltage to the receiver (VRX-DIFF = 200 mV). 200/800 = .25, which after conversion results in a maximum loss budget of 12.04 dB. Revision Date: 7/29/2005 6 Copyright 2005 Samtec/Teraspeed Application Note Series: QTE/QSE Series, 16mm Stack Height Standard: XAUI Transmitter Compliance Measurements Setup for Tj for UI Measurements As mentioned in the previous section, the driver stimulus’ jitter was adjusted until the transmitter exhibited the maximum total jitter allowed by the XAUI specification at the driver package pins under the compliance load shown in Figure 4 below. The XAUI specification does not specify the range of capacitor values allowed for the AC coupling capacitors. We set C to 100nF for all simulations because it is a popular value in the industry. Table 3 shows the resulting output measurements. D+ Package Pin C = 100 nF TX Silicon + Package D- Package Pin C = 100 nF R = 100 Ω Figure 4 – XAUI Compliance Test/Measurement load VDIFFp-p1 Total Jitter Specification ≥800 mV ≤ ±56 psec Measured 800.2 mV ±55.9 psec Table 3 – XAUI TX Silicon + Package Measurements at Package Pin 1 X2 to 1-X2, the TX mid bit sample time, is 70.4 psec when UI = 320 psec. The eye pattern generated in the XAUI driver compliance test simulation can be found in Appendix A of this paper, picture #1. Revision Date: 7/29/2005 7 Copyright 2005 Samtec/Teraspeed Application Note Series: QTE/QSE Series, 16mm Stack Height Standard: XAUI Full Circuit Compliance Measurements Differential Voltage and Eye Width Measurements at Receiver End QTE/QSE 16 mm Stack Height Specification Min RX Eye Width, X1 to 1-X1 (See 1 Max Jitter at example mask UI = 320 psec template) ≤ ±88 psec ≥112 psec Min Rx Differential 2 Voltage, A1 to –A1 (See example mask template) ≥200mVDIFFp-p Pass/Fail - 3 ± 298.6 680.8 Pass 5" total trace 10" total trace ±58.5 292.1 288.1 Pass 15" total trace ±57.6 291.7 484.8 Pass 20" total trace ±59.2 293.0 386.8 Pass 25" total trace ±61.5 293.3 240.4 Pass 30" total trace ±54.3 283.0 269.0 Pass 35" total trace ±61.9 281.7 232.0 Pass 37" total trace ±64.5 279.4 216.6 Pass 38" total trace ±67.2 276.6 204.8 Pass 39" total trace ±68.7 272.6 191.6 Fail Table 4 – XAUI Measurements at Receiver End – RiseUp™ RU8 Series 25 mm stack height, differential pair configuration. 1 XAUI jitter requirements are specified as peak from the mean. These value assume symmetrical jitter distributions from the mean. 2 X2 to 1-X2, the RX mid bit sample time, is 64 psec when UI = 320 psec. 3 The total trace length specified is the sum of the two differential trace lengths in the QTE/QSE series test fixture model, as shown in Figure 1. These traces are always kept equal in length in each simulation. The eye pattern generated in the XAUI circuit simulation with 38 inches total trace length can be found in Appendix A of this paper, picture #2. Revision Date: 7/29/2005 8 Copyright 2005 Samtec/Teraspeed Application Note Series: QTE/QSE Series, 16mm Stack Height Standard: XAUI Conclusions A single Samtec QTE/QSE Series 16 mm used in a differential board-to-board configuration can be used in XAUI systems with total trace lengths not to exceed 38 inches when used with Samtec’s Final Inch® routing, breakout, and trace width solutions. Because loss is the dominant contributor to system degradation, designers should be aware that using smaller trace widths, laminates with higher loss tangent, and sub optimal routing solutions with higher pair-to-pair coupling and additional via stubs will decrease overall performance and the maximum allowable trace length. It is advisable when designing systems that approach the maximum jitter limits to perform detailed modeling, simulation, and measurement of the target design including the effects of material properties, traces, vias, and additional components. Revision Date: 7/29/2005 9 Copyright 2005 Samtec/Teraspeed Application Note Series: QTE/QSE Series, 16mm Stack Height Standard: XAUI Appendix A – Waveform images Picture 1 – Worst case stimulus differential eye waveform, probed at Xilinx driver package pins, connected to compliance test/measurement load. Picture 2 – QTE/QSE Series 16mm XAUI circuit eye waveform, probed at terminator pins, 38 inches total trace length. Revision Date: 7/29/2005 10 Copyright 2005 Samtec/Teraspeed