Communication ICs
DTMF receiver for telephones
BU8874 / BU8874F
The BU8874 and BU8874F are DTMF receiver ICs developed for use in telephone answering machines, and convert
16 different types of DTMF signals into 4-bit binary serial data. In addition to a compact 8-pin DIP (BU8874) package,
these receivers feature a wide dynamic range, eliminating the need for an external input amplifier. Expertise from a number of companies has been incorporated into these products to enable guard time control through a host microcontroller.
Telephone answering machines
1) Dynamic range of 45dB. (internal AGC)
2) Power down mode.
3) 4-bit binary serial data output.
4) Guard time can be controlled through host microcontroller.
5) Input pins equipped with hysteresis. (ACK pin)
Block diagram
6) 4.19MHz crystal resonator can be used.
7) 8-pin DIP package. (BU8874)
Communication ICs
BU8874 / BU8874F
FAbsolute maximum ratings (Ta=25_C)
FRecommended operating conditions (Ta=25_C)
FPin descriptions
Communication ICs
BU8874 / BU8874F
Input / output circuits
Communication ICs
BU8874 / BU8874F
FElectrical characteristics (unless otherwise noted, Ta=25_C, VDD=5.0V)
Communication ICs
Circuit operation
(1) An overview of operation
A DTMF signal is supplied to the INPUT pin and applied
to a pair of 6th-order bandpass filters, which separate the
DTMF signal into its high (COL) and low (ROW) frequencies. The separated tonesre converted into square
waves and fed to a DIGITAL DETECTOR. The DIGITAL
DETECTOR checks the two tones to see if they are within the valid DTMF frequency bands. If they are, it sends
a DETECT signal to the STEERING CIRCUIT, and sends
the appropriate COLUMN and ROW address signals to
The CODE CONVERTER encodes the received and detected DTMF signal, and outputs an ENABLE signal to
Based on the DETECT and ENABLE signals, the
STEERING CIRCUIT outputs an Early Steering (ESt)
signal, which sets the ESt pin to HIGH, indicating that a
valid DTMF signal has been detected.
If a series of pulses is input at the ACK pin while ESt is
HIGH, a decoded DTMF signal is output to the SD pin as
a binary code. (See Figure 4 for the overall timing.)
If a pulse sequence is input at the ACK pin, the data is
latched at the rising edge of the first pulse by a PARALLELSERIAL CONVERTER, and at the same time,
the LSB is output from the SD pin. Following this, three
bits of data are output from the SD pin for each bit of each
pulse in the pulse sequence input from the ACK pin. As
a result, a total of four bits of data are output for the four
pulses. (See Figure 5 for the ACK and SD timing.)
If the pulse sequence input to the ACK pin consists of
three or fewer pulses, the next DTMF input cannot be decoded properly. Any ACK pulses in excess of four are ignored until ESt goes HIGH again. Table 1 shows the format of serial data output from the SD pin.
BU8874 / BU8874F
(2) Power down interface
The power down mode is activated by applying a rising
edge at the PWDN pin when the ACK pin is LOW. The
ACK pin may be taken from LOW to HIGH and back to
LOW again while the circuit is in the power down mode.
To return to the normal operation mode, set PWDN to
LOW. After returning from the power down mode to the
normal operation mode, if a valid DTMF signal is still being held (from prior to entering the power down mode),
a second reading of the data can be performed (the first
reading following recovery to the normal operation
mode) by inputting the ACK pulse sequence. Figure 3
shows this status.
If the circuit enters the power down mode n times, data
can be read (n1) times (while ESt is HIGH), as long as
input of the DTMF signal continues.
Communication ICs
BU8874 / BU8874F
(3) Overall timing chart
(5) ACK and SD timing
(4) Serial data correspondence table
(6) Operation mode input logic
Communication ICs
BU8874 / BU8874F
Application example
Selecting attachment components
(1) Power supply components
C502 : This is the VDD bypass capacitor, and is normally
JP501 : This is normally shorted. To test the current consumption of the IC (at the point where the power
down mode is entered), insert a DC ammeter in
place of JP501.
(2) Oscillation components
X501 : Use a crystal or ceramic resonator with an oscillation frequency of 4.194304MHz. If using a
ceramic resonator, there may be problems with
the precision of the oscillation frequency, so we
recommend using one of the ceramic resonators listed below.
C591 : If you are using a dedicated resonator X501designed for DTMF receivers, capacitor C591
should be left open. If you are injecting an external clock, X501 should be omitted and DC
blocking capacitor C591 used in its place. Typically, this capacitor should be 47µnF.
Communication ICs
BU8874 / BU8874F
(3) DTMF input
C501 : This is the DC blocking capacitor. Select a capacitor that will pass DTMF signals (greater
than 697Hz) without significantly attenuating
the signals.
JP592 : If DTMF signals are being input directly, both
ends should be shorted.
Use these to increase the sensitivity of
R591 X R595
the DTMF receiver.
C592, C593
(4) ESt output
The ESt guard time is determined by the CPU of the host
computer, but to reduce the load on the host computer,
the guard time can be set using an external circuit, as
shown in Figure 10.
The relation between a momentary falter in the ESt guard
time (tGL), a momentary HIGH level in the ESt guard time
(tGH), and the time constant is shown below. Figure 12
shows a timing diagram for guard times.
Communication ICs
Operation notes
(1) Power down
When ACK is LOW, the power down mode can be entered by applying a rising edge to the PWDN pin. Current
consumption drops from several seconds to several tens
of seconds after the power down mode has been specified.
Operation with SD multiple reading is recommended.
BU8874 / BU8874F
(2) Oscillation
Oscillation frequency precision can be a problem with ceramic resonators. Before including a ceramic resonator
in your design, please consult the resonator manufacturer to make sure this will not be a problem.
Also, if an external clock is being injected, a DC blocking
capacitor must be inserted. Select a capacitor that will
neither attenuate the frequency components or put an
excessive load on the drive side.
This LSI is not equipped with the power-on reset function. Also, since the internal circuit (flip-flop circuit) becomes unstable at the rising edge of the power supply, the internal circuit is initialized as shown below by the first DTMF sequence
received after the rising edge of the power supply. Therefore, input four dummy ACK pulses before the DTMF reception.
Electrical characteristic curves
Communication ICs
BU8874 / BU8874F
External dimensions (Units: mm)