Quality Assurance System

No.Q2200101EG
LOT ASSURANCE INSPECTION
LOT ASSURANCE INSPECTION is executed to verify the quality every wafer process fabrication lot.
It is the key to the assured delivery initial reliability.
<For Real-Time Clock ICs>
No.
1
2
TEST ITEMS
High Temperature Operating Life Test
uHAST
TEST CONDITION
SAMPLE
LTPD
Ta=125C, 48h
22
10%
Pre-condition(*)
Ta=125C, RH=85%、20h
22
10%
< Test Period >
The test period will be change to
the periodical monitoring when it is
confirmed the good quality level.
Temperature (C)
uHAST: Unbiased Highly Accelerated temperature and humidity Stress Test.
(*)Pre-condition [SMD Package]
Reflow 2times (IR/ Max.260: Following profile.)
260C max.
2555C
220C
190C
150C
101s
120s max.
Heating condition of infrared-ray reflow.
90s max.
Time (s)
No.Q2200102EG
QUALITY ASSURANCE TEST INSPECTION
QUALITY ASSURANCE TEST is done for quality assurance of shipped products by using sampling
inspection.
<For Real-Time Clock ICs>
No.
DIVISION
TEST ITEMS
CRITERIA
Major Defect
1
2
QAT Specification
Electrical
AQL **
0.065% *
Minor Defect
0.15%
Major Defect
0.25%
Appearance
Visual Inspection Criteria
Minor Defect
* ) Major Defect (short, open or functionally inoperative) AQL 0.065%
**)
AQL
: ANSI/ASQC Z1.4-1993
Sampling Plans : Table Ⅱ-C-Single sampling plans for reduced inspection
0.15%