TSS463B PPAP TSS463B Serial VAN Data Link Controller ATMEL P/N : TSS463B-TERA PPAP Submission Date: Supplier: 2003 October Atmel Nantes SA Address: La Chantrerie BP 70602 44306 NANTES Cedex 3 France Tel : 33(0) 2 40 18 18 18 Fax : 33(0) 2 40 18 19 20 1 Rev. 3 : Initial Submission – 2003 October TSS463B PPAP Table of Contents 1 DESIGN RECORDS .............................................................................................................................................................................. 6 1.1 1.2 2 PRODUCT S PECIFICATION.............................................................................................................................................................6 PACKAGE OUTLINE ........................................................................................................................................................................6 ENGINEERING CHANGE DOCUMENTS ................................................................................................................................... 7 2.1 CDC CERTIFICATE OF DESIGN, CONSTRUCTION AND QUALIFICATION............................................................................7 2.1.1 General Product Information................................................................................................................................................... 7 2.1.2 Process Technology Information............................................................................................................................................. 7 2.2 PRODUCT DESIGN ...........................................................................................................................................................................8 2.2.1 Product Design Information..................................................................................................................................................... 8 2.2.2 Product Design Validation....................................................................................................................................................... 8 2.2.3 Package Technology Information ........................................................................................................................................... 9 2.2.4 Packing Delivery Information................................................................................................................................................10 2.2.5 Final Test Information ............................................................................................................................................................10 2.2.6 Device Cross Section...............................................................................................................................................................10 2.3 QUALIFICATION AND CHANGE PROCEDURE...........................................................................................................................11 2.3.1 Qualification methodology.....................................................................................................................................................11 2.3.2 Change Procedure...................................................................................................................................................................12 2.3.3 Qualification test methods......................................................................................................................................................13 3 ENGINEERING APPROVAL..........................................................................................................................................................14 4 DESIGN FMEA ....................................................................................................................................................................................14 5 PROCESS FLOW DIAGRAMS .......................................................................................................................................................14 5.1 5.2 5.3 WAFER PROCESSING ....................................................................................................................................................................14 ASSEMBLY ......................................................................................................................................................................................15 TEST AND PACKING......................................................................................................................................................................15 6 PROCESS FMEA .................................................................................................................................................................................15 7 DIMENTIONAL RESULTS .............................................................................................................................................................15 8 PERFORMANCE TEST RES ULTS ...............................................................................................................................................16 8.1 QUALIFICATION RESULTS ...........................................................................................................................................................16 8.1.1 Wafer Process Qualification..................................................................................................................................................16 8.1.2 Package Qualification.............................................................................................................................................................16 8.1.3 Device Qualification................................................................................................................................................................17 8.1.4 Failure Mechanisms and Corrective Actions......................................................................................................................17 8.1.5 Electrical Distribution in Operating Life-Test....................................................................................................................18 8.1.6 Reliability Calculation............................................................................................................................................................19 8.1.7 ESD Results (HBM) - MIL-STD 883 method 3015.7.........................................................................................................19 8.1.8 Latch-up Results.......................................................................................................................................................................19 8.2 PRODUCT CHARACTERIZATION.................................................................................................................................................19 8.2.1 Characterization environment...............................................................................................................................................19 8.2.2 Corner lot’s splits.....................................................................................................................................................................19 8.2.3 Results / Parameter capability...............................................................................................................................................20 9 2 INITIAL PROCESS STUDY ............................................................................................................................................................21 Rev. 3 : Initial Submission – 2003 October TSS463B PPAP 9.1 SCMOS3 PROCESS (Z92G) ........................................................................................................................................................21 10 MEASUREMENT SYSTEM ANALYSIS STUDY................................................................................................................21 11 QUALIFIED LABORATORY DOCUMENTATION ..........................................................................................................22 12 CONTROL PLAN...........................................................................................................................................................................22 13 PART SUBMISSION WARRANT .............................................................................................................................................23 14 APPEARANCE APPROVAL REPORT...................................................................................................................................24 15 BULK MATERIAL REQUIREMENTS ...................................................................................................................................24 16 SAMPLE PRODUCTION PARTS .............................................................................................................................................24 17 MASTER SAMPLE........................................................................................................................................................................24 18 CHECKING AIDS ..........................................................................................................................................................................24 19 CUSTOMER-SPECIFIC REQUIREMENTS .........................................................................................................................24 3 Rev. 3 : Initial Submission – 2003 October TSS463B PPAP Revision history 4 Rev 0 1 2 Issue 2003 March 2003 June 2003 October 3 2003 October Modification Notice Initial release (preliminary document) Initial release (revised document) Initial release (revised document) - Add of TSS463B rev 4 reliability assessment Initial release (revised document) - Add of reliability calculation Applicable from 2003 April 2003 June 2003 October 2003 October Rev. 3 : Initial Submission – 2003 October TSS463B PPAP PPAP Checklist Requirements Table of contents PPAP Checklist 1. Design Records 2. Engineering Change Documents 3. Engineering Approval 4. Design FMEA 5. Process Flow Diagrams 6. Process FMEA 7. Dimensional Results 8. Records of Material / Performance Test Results 8.1 Material Test Records 8.2 Performance Test Records 9. Initial Process Study 10. Measurement System Analysis Study 11. Qualified Laboratory Documentation 12. Control Plan 13. Part Submission Warrant (PSW) 14. Appearance Approval Report 15. Bulk Material Requirements Checklist 16. Sample Production Parts 17. Master Sample 18. Checking Aids 19. Customer Specific Requirements 5 Included yes yes yes yes yes Project risk analysis yes yes Not Applicable Not applicable to IC Yes Yes Yes Yes Yes Yes Not applicable to IC Not applicable to IC To be ordered separately Not attached Not Applicable Not attached Rev. 3 : Initial Submission – 2003 October TSS463B PPAP 1 Design Records 1.1 Product Specification Please refer to ATMEL’s Data Sheet: TSS463B VAN Data Link Controller with serial interface http://www.atmel.com/ 1.2 6 Package Outline Rev. 3 : Initial Submission – 2003 October TSS463B PPAP 2 Engineering Change Documents 2.1 CDC Certificate of Design, Construction and Qualification 2.1.1 General Product Information Product Name: TSS463B Function: VAN Data Link Controller Wafer Process: CMOS 0.5um Package Type: SO-L.300 16 leads Locations: Process Development Product Development Wafer Plant QC Responsibility Probe Test Assembly Final Test Lot Release Shipment Control Quality Assurance Reliability Testing Failure Analysis Atmel Nantes , France Atmel Nantes , France Atmel Nantes , France Atmel Nantes, France Atmel Nantes , France ASE Chung Li, Taiwan CHIPPAC, China AMKOR, Korea TSTI Philippines Atmel Nantes, France Global Logistic Center, Philippines Atmel Nantes, France Atmel Nantes, France Atmel Nantes, France 2.1.2 Process Technology Information Process Type (Name): Z92 (SCMOS3 : 0.5um Logic CMOS technology) Base Material: Wafer Thickness (final) Wafer Diameter Bulk silicon 475µm 150 mm Number Of Masks 14 Gate Oxide (Logic transistors) Material Thickness Silicon Dioxide 110 A 7 Rev. 3 : Initial Submission – 2003 October TSS463B PPAP Polysilicon Number of Layers Thickness 1 2000A Metal Number of Layers Material Layer 1 Thickness Layer 2 Thickness Layer 3 Thickness Passivation Material Thickness 2.2 3 AlCu 5150A 5150A 7650A SiO2 / Nitride 2600A / 6400A Product Design 2.2.1 Product Design Information Die Size Pad Size Opening Logic Effective Channel Length Gate Poly Width (min.) Gate Poly Spacing (min.) Metal 1 Width Metal 1 Spacing Metal 2 Width Metal 2 Spacing Metal 3 Width Metal 3 Spacing Contact size Via 1 size Via 2 size 2 2200µm * 2790 µm (6.14mm ) 100µm * 100µm 0.5µm 0.50µm 0.60µm 0.60µm 0.70µm 0.80µm 0.70µm 0.80µm 0.70µm 0.60µm 0.60µm 0.60µm 2.2.2 Product Design Validation Design validation done according to Atmel Nantes development procedure and documented in the following documents: VAN protocol assessment DASSAULT Test Plan Results TSS463B Rev4 ATD-TS-GU-R001 – October 2002 Laurentiu BIRSAN Third Party Application assessment VAN Device TSS463B NSI Test Report DCL-MUX-0077 /V1.0 Jacques TELLIER EMC Evaluation TSS463B Dynamic Current Analysis APP/LAB/JLL/01/67-0.2 Jean Luc LEVANT 8 Rev. 3 : Initial Submission – 2003 October TSS463B PPAP 2.2.3 Package Technology Information Package weight Chip separation method Lead frame Material Thickness Size Lead plating Die attach Material Type Wire bonding Material Diameter Method Molding Material Flammability rating Marking Method Drawing example 0.43 g Sawing Cu 10 mils 2 270*270 mils Electroplated Sn/Pb 85/15 Silver epoxy Ablestick 84-1 LMISR4 Au 1.0 mil Thermosonic NITTO MP8000AN UL94V-0 Printed ink (top) and Laser (back) Atmel TSS463B-TERA YYMM Zxxxxxxx Bonding Diagram 9 Rev. 3 : Initial Submission – 2003 October TSS463B PPAP 2.2.4 Packing Delivery Information Dry packing Tube packed Primary Material Number per unit Secondary Material Number per unit Labeling (minimum) Bar coding Reel packed Primary Material Carrier tape Cover tape Number per unit Secondary Number per unit Labeling (minimum) No Tube Antistatic PVC 36 Box Cardboard 1692 Device type, quantity, Date code, Production code Code 39 to EIA-556-A Reel Conductive black polystyrene Antistatic film 1500 Box 1 Device type, quantity, Date code, Production code 2.2.5 Final Test Information Probe equipment Probe temperature Test equipment Test temperature NEXTEST Maverick o 125 C NEXTEST Maverick o o 25 C, 125 C 2.2.6 Device Cross Section 10 Rev. 3 : Initial Submission – 2003 October TSS463B PPAP 2.3 Qualification and Change Procedure 2.3.1 Qualification methodology All product qualifications are split into three distinct steps as shown below. Before a product is released for use, successful qualification testing are required at wafer, device and package level. Wafer Level Reliability consists in testing individually basic process modules regarding their well known potential limitations (Electromigration, Hot Carriers Injection, Oxide Breakdown, NVM Data Retention). Each test is performed using a dedicated wafer process structure. Device reliability is covering either dice design and processing aspects. The tests are performed on device under qualification, and generic data may also be considered for reliability calculation. For each package type proposed in the Datasheet, it is verified that qualification data are available. If not qualification tests are carried out for the new package types. At least one package type is selected to verify packaging reliability of the devi ce under qualification. Product Qualification Wafer Level Device Packaging (Design / Process) Reliability 11 Reliability Reliability Rev. 3 : Initial Submission – 2003 October TSS463B PPAP 2.3.2 Change Procedure All changes are controlled by ECN (Engineering Change Notice). Major changes are notified to customers using products affected by the change. Major changes are defined as changes which may affect the electrical and/or mechanical product specification. The following checklist provides the minimum list of items to be considered. 1 1-1 1-2 1-3 1-4 1-5 1-6 General Changes Manufacturing line Sequence of fabrication process cycle Material type Electrical parameter External physical dimension Die size 2 2-1 2-2 2-3 2-4 2-5 Changes Specific to Wafer Fabrication Doping method Gate oxide formation method Equipment change Layer Thickness Module dimensions 3 3-1 3-2 3-3 3-4 3-5 Changes Specific to Asse mbly Sawing method Die attach method Wiring method Molding process Lead finish / MSL classification 4 4-1 4-2 4-2 4-3 Changes Specific to Test Specification limit Test coverage reduction Product identification Final conditioning 12 Rev. 3 : Initial Submission – 2003 October TSS463B PPAP 2.3.3 Qualification test methods General Requirements for Plastic Encapsulated CMOS Ics. 13 Standard Test Description Acceptance MIL-STD 883 Method 1005 Electrical Life Test (Early Failure Rate) 48 hours 140°C 0/800 - 48h MIL-STD 883 Method 1005 Electrical Life Test (Latent Failure Rate) 1000 hours 140°C Dynamic or Static 0/77 - 1000h MIL-STD 883 Method 3015.7 Electrostatic Discharge HBM +/-2000v 1.5kOhm/100pF/3 pulses 0/3 per level JEDEC 78 Latch up 50mW power injection, 50% overvoltage @125°C 0/5 per stress AEC Q100 Method 005 NVM Endurance Program Erase Cycles 125°C 0/77 - 100kc AEC Q100 Method 005 NVM Data Retention High Temperature Storage 165°C 0/77 - 1000h MIL-STD 883 Method 1010 Temperature Cycling 1000 cycles –65°C/150°C air/air 0/77 - 500c EIA JESD22-A110 Autoclave 96 hours 130°C/85%RH 0/77 – 96h EIA JESD22-A101 85/85 Humidity Test 1000 hours 85°C/85%RH 0/77 - 1000h EIA JESD22-A110 HAST 96 hours 130°C/85%RH/biased 0/50 - 96h EIA JESD20 Preconditioning Soldering Stress 220°C/235°c/3 times 0/11 per class MIL-STD 883 Method 2003 Solderability 0/3 MIL-STD 883 Method 2015 Marking Permanency 0/5 Rev. 3 : Initial Submission – 2003 October TSS463B PPAP 3 Engineering Approval TSS463B is qualified since 2003 March Released to production review was done in 2003 May Release to Production is approved by: Ø Ø Ø Ø Ø Ø Ø Ø Head of Technical Center Project Leader Product Engineering Operation Back-end Operation Front-end Quality Management Marketing Business Planning 4 Design FMEA Project Risk Analysis has been initiated at Feasibility stage and followed under Project Leader responsibility, all over project development stages. Project Risk Analysis report may be consulted in Atmel Nantes upon request. 5 Process Flow Diagrams 5.1 Wafer Processing 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 14 Incoming inspection of silicon wafers Locos (Z92) Isolation MOS N-Well implants and N Well diffusion MOS P-Well Implants MOS Gate oxidation Polysilicon deposition and MOS gate definition MOS Implants with Spacer definition Salicide Hard mask definition Salicide module ILD deposition and SOG planarization Contact etching and Plug1 filling Metal 1 deposition and etching IMD1 and REB planarization Via1 etching and Plug2 filling Metal 2 deposition and etching IMD2 and REB planarization Via2 etching and Plug3 filling Rev. 3 : Initial Submission – 2003 October TSS463B PPAP 18. 19. 20. 21. 22. 5.2 Metal 3 deposition and etching Passivation deposition and Pad etching E-Test Back grinding Wafer sort Assembly 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 5.3 Wafer mount Wafer saw First optical Die bonding Wire bonding Molding Solder plating Top marking Trim and form Final visual inspection Test and Packing 1. 2. 3. Room temperature initial test Final quality checks Packing 6 Process FMEA Process FMEA for 0.5um Z92 may be consulted in Atmel Nantes upon request. 7 Dimentional Results SO-L.300 16 leads package comply with JEDEC standard outline. Package dimensions were checked during Package Qualification. 15 Rev. 3 : Initial Submission – 2003 October TSS463B PPAP 8 Performance Test Results 8.1 Qualification Results 8.1.1 Wafer Process Qualification ATMEL 0.5µm SCMOS3 wafer process is qualified since 1997, September. 8.1.2 Package Qualification Package qualification measurements carried out on VAN DLC devices are detailed in the table below: Lots Device Type Test Description Z40807C TSS463B SO-L.300 16 AMKOR K 85/85 Humidity Z41393J Z45925A (Note 1) TSS461E SO-L.300 24 AMKOR K TSS463B rev4 SO-L.300 16 ASE CL Thermal Cycles HAST after Thermal Shocks High Temperature Storage 165°C Moisture sensitivity JESD20 – level1 85/85 Humidity Thermal Cycles HAST after Thermal Shocks High Temperature Storage 165°C Moisture sensitivity JESD20 – level1 85/85 Humidity Thermal Cycles HAST after Thermal Shocks Moisture sensitivity JESD20 – level1 High Temperature Storage 165°C 16 Step 500h 1000h 500c Result Comment 1000c 96h 0/77 0/77 0/77 0/5 0/5 0/72 0/77 Post preconditioning level1 500h 1000h CSAM Elect 500h 1000h 500c 1000c 96h 0/77 0/77 0/11 0/231 0/50 0/50 0/50 0/72 0/77 Post preconditioning level1 500h 1000h CSAM Elect 500h 1000h 500c 1000c 96h 0/50 0/50 0/11 0/231 0/77 0/77 0/77 0/77 0/77 Post preconditioning level1 CSAM Elect 500h 1000h 0/11 0/231 0/77 0/77 Post preconditioning level1 Ball shear cpk:1.70 (30 pads) Wire pull cpk:2.35 (30 wires) Post preconditioning level1 Post preconditioning level1 Post preconditioning level1 Post preconditioning level1 WP-Cpk= 1.67, BS-Cpk=1.89 Post preconditioning level1 Rev. 3 : Initial Submission – 2003 October TSS463B PPAP Additional assembly qualification reports are available under the following references: ASE Chung Li : QR0813 (2002/09/23) CHIPPAC China : QR0726 (2002/05/13) 8.1.3 Device Qualification Device qualification is based upon HTOL results of 3 lots as detailed in the table below: Lot Device Type Test Description Z40807C TSS463B SO-L.300 16 AMKOR K EFR Dynamic Life Test 140°c/5.75v LFR Life Test 140°c/5.75v EFR Dynamic Life Test 140°c/5.75v LFR Life Test 140°c/5.75v EFR Dynamic Life Test 140°c/5.75v LFR Life Test 140°c/5.75v Z41393J Z45925A (Note 1) TSS461E SO-L.300 24 AMKOR K TSS463B rev4 SO-L.300 16 ASE CL Step Result 48h 0/774 500h 1000h 48h 0/77 0/77 0/795 500h 1000h 48h 0/77 0/77 0/800 500h 1000h 0/100 0/100 Comment Note 1: In this revision of the TSS463B PPAP, are reported the reliability results of the final production version of the circuit (Rev 4 design). The measurements have been carried out on lot Z45925A DC0327. 8.1.4 Failure Mechanisms and Corrective Actions No failure mechanism reported in this document. The table here below presents additional Reliability Monitor Data performed during the first quarter of 2003. Lot Device Type Test Description Z44574F TSSIO16E SO-L.300 28 AMKOR K EFR Dynamic Life Test 140°c/5.75v LFR Life Test 140°c/5.75v Moisture sensitivity JESD20 – level1 85/85 Humidity Thermal Cycles Autoclave post Thermal Shocks 17 Step Result 48h 0/300 500h 1000h CSAM Elect 500h 1000h 500c 1000c 96h 0/77 0/77 0/11 0/150 0/50 0/50 0/50 0/50 Comment Post preconditioning level1 (Test in progress) Post preconditioning level1 Post preconditioning level1 Rev. 3 : Initial Submission – 2003 October TSS463B PPAP 8.1.5 Electrical Distribution in Operating Life-Test In order to assess the drift of product performance under HTOL stress 30 parts have been submitted to 1000 hours 140°c/5.75v aging. All specified AC and DC Parameters have been recorded prior (initial) and post stress (final) for the lot Z41521. The table below summarizes the results with total drift ratio and final Cpk. No significant drift noticed after HTOL aging. Final Cpk values are higher than 1.33. HTOL performance records for the rev 4 design (lot Z45925A) have been included in the table as well. The records do not indicate any change in the performance of the circuit. Symbol Parameter Typical Initial Final Drift (%) Cpk Z45925A ICCSB Static Consumption 50uA max 5.5V 0.050 0.049 0.046 -6.1 >20 0.051 ICCOP Active Consumption 9 mA max 5.5V 2.20 2.23 2.25 0.9 >20 2.24 VIL CMOS Input Low Level 1.5V min 4.5V 1.51 1.51 1.54 2.0 1.6 1.63 VIL1 XTAL 1 Low Level 1.5V min 4.5V 1.66 1.70 1.69 0.6 3.4 1.70 VIH CMOS Input High Level 3.5V max 5.5V 3.16 3.12 3.23 3.5 1.5 3.11 VIH1 XTAL 1 In High Level 3.5V max 5.5V 3.15 3.11 3.21 3.2 1.6 3.10 VOL TXD TXD Out Low Level 0.4V max 4.5V 0.22 0.21 0.23 9.5 10.2 0.23 VOL INTB INTB Out Low Level 0.4V max 4.5V 0.22 0.21 0.23 9.5 9.3 0.24 VOH TXD TXD Out High Level 2.4V min 4.5V 4.1 4.0 4.0 0.0 3.7 4.0 IIL RESET RESET Low Leakage 78.5uA max 5.5V 20.6 21.3 22.6 6.1 >20 20.8 TCYC Cycle Time SPI 250ns max 4.5V 9.3 9.3 9.4 1.1 >20 9.3 TW SCKH Clock High Time 100ns max 4.5V 3.41 3.41 3.47 1.8 >20 3.41 TW SCKL Clock Low Time 100ns max 4.5V 5.9 5.9 5.9 0.0 >20 5.9 TSU Data Setup Time 40ns max 4.5V 0.80 0.80 0.86 7.5 >20 0.79 TH Data Hold Time 40ns max 5.5V -0.52 -0.52 .052 0.0 >20 -0.52 TV Enable to Data Valid 60ns max 4.5V 30.1 32.6 31.5 -3.4 7.5 31.6 18 Specification Vcc (*) Rev. 3 : Initial Submission – 2003 October TSS463B PPAP 8.1.6 Reliability Calculation Reliability calculation requires a large base of measurement data in prospect of targeting the objectives of Automotive Market. Therefore the data source is enlarged to 2003 records of digital 0.5um Nantes products. Sample size Failures Failure Rate Projected Failure Rate Unit 1.9E6 7 4 3 PPM 2880E3 0 2 1 FIT Early Life Failures Latent Failures 8.1.7 ESD Results (HBM) - MIL-STD 883 method 3015.7 Lot Device Type Test Description Z40807C TSS463B SO-L.300 16 AMKOR K ESD HBM Step 2000v 3000v 4000v Result 0/3 0/3 0/3 Comment Class 3 of MIL STD 883 Method 3015 (ESD0113) 8.1.8 Latch-up Results Lot Device Type Test Description Step Z40807C TSS463B SO-L.300 16 AMKOR K LATCH-UP Power Injection Over voltage 50mw 10v 8.2 Result 0/5 0/5 Comment Latch-up free (min value: 180mW at 125°c) Product Characterization 8.2.1 Characterization environment Tester: Sentry 15 Lot: Z43525 Process: Z92 Perso Code: 0RD7 (design Rev 4) Assy package: TE (SO-L.300 16 leads) 8.2.2 Corner lot’s splits In order to characterize the product with the maximum excursion of the process, corner run splits have been manufactured using : 19 Rev. 3 : Initial Submission – 2003 October TSS463B PPAP - Variations on LeffP and LeffN Variations on VTP and VTN The sample size is 3 parts per corner plus 6 parts in the group of typical values (Total 21 parts). 8.2.3 Results / Parameter capability All specified AC and DC Parameters have been characterized for Rev 4 design version. They present Cpk values higher than 1.6. The comparison of Rev 1 and Rev 4 characteristics does not point out any difference. Characterization results have been submitted to a detailed customer review (TSS463B Test Review) held in Nantes on 27/11/2001. The next table provides the main product characteristics based upon Mask 6046 Rev 4 evaluation results. All TSS463B AC parameters are reported in this table. Symbol Parameter Specification (1) Vcc (*) Temp (*) Average Cpk ICCSB Static Consumption 50uA max 5.5V 125 2.9uA 9.6 ICCOP Active Consumption 9 mA max 5.5V -40 2.7mA > 20 VIL CMOS Input Low Level 1.5V min 4.5V -40 1,6V 1.61 VIL1 XTAL 1 Low Level 1.5V min 4.5V -40 1,7V 4.0 VIH CMOS Input High Level 3.5V max 5.5V -40 3.2V 5.7 VIH1 XTAL 1 In High Level 3.5V max 5.5V -40 3.2V 4.7 VOL TXD TXD Out Low Level 0.4V max 4.5V 125 0.22V 18.0 VOL INTB INTB Out Low Level 0.4V max 4.5V 125 0.23V 12.3 VOH TXD TXD Out High Level 2.4V min 4.5V 125 3.9V > 20 IIL RESET RESET Low Leakage 78.5uA max 5.5V -40 26.5uA > 20 TCYC Cycle Time SPI 250ns max 4.5V 125 10ns > 20 TW SCKH Clock High Time 100ns max 4.5V 125 5.5ns 14.7 TW SCKL Clock Low Time 100ns max 4.5V 125 5.9ns >20 TSU Data Setup Time 40ns max 4.5V 125 0.8ns >20 TH Data Hold Time 40ns max 5.5V -40 -0.5ns >20 TV Enable to Data Valid 60ns max 4.5V 125 36.7ns 14.1 (*) worst case condition 20 Rev. 3 : Initial Submission – 2003 October TSS463B PPAP 9 Initial Process Study 9.1 SCMOS3 process (Z92G) Parameters controlled during Electrical Test : NMOS/PMOS :junction Breakdown Voltage, Threshold voltage, electrical width & length, Thin oxide Breakdown Voltage, Sub-threshold current. Sheet Resistance : N+, P+, WELL, PolyN, PolyP, Unsalicided Poly Metal continuity / isolation: metal1, metal2, metal3 Contacts/ Vias1 & Vias2 resistance Contacts Breakdown Voltage Salicide isolation Cpk history (Last update 23/01/2003) : Z92G Cpk distribution 120% 100% Répartition (%) 80% 60% 40% 20% 0% 02/01 02/02 02/03 02/04 02/05 02/06 02/07 02/08 02/09 02/10 02/11 02/12 03/01 Cpk<1.33 (%) 5% 3% 5% 8% 5% 5% 8% 0% 8% 14% 0% 3% 3% Cpk>=1.33 & <1.66 (%) 5% 5% 3% 5% 19% 5% 11% 3% 5% 0% 3% 5% 3% 89% 92% 92% 86% 76% 89% 81% 97% 86% 86% 97% 92% 95% Cpk>=1.66 (%) Mois Cpk<1.33 (%) Cpk>=1.33 & <1.66 (%) Cpk>=1.66 (%) Linéaire (Cpk<1.33 (%)) Linéaire (Cpk>=1.66 (%)) 10 Measurement System Analysis Study Repeatability and Reproducibility tests are performed on all the manufacturing equipments. Critical parameters and equipments are followed under SPC system. In addition Equipment performance is assessed by GRR and through regular maintenance activity. 21 Rev. 3 : Initial Submission – 2003 October TSS463B PPAP 11 Qualified Laboratory Documentation Internal Lab – COMPLIANT QS-9000 3rd edition Application Lab Calibration Lab Characterization Lab Chemical Lab Environmental Lab Technology Analysis Lab Scope Check the functionality of products to customer applications Standard Gage Calibration Product and process characterization before completing industrialization Incoming inspection on chemical products and process monitoring on DI water , gases Product Reliability Testing Failure Analysis and Yield enhancement 12 Control Plan Control plan is composed of the following: - Wafer fab Control Plan for Z92G process Assembly Control Plan Test Control Plan Front-end and Back-end operation control plans may be consulted in Atmel Nantes upon request. Test Control Plan: 22 Rev. 3 : Initial Submission – 2003 October TSS463B PPAP 13 Part Submission Warrant 23 Rev. 3 : Initial Submission – 2003 October TSS463B PPAP 14 Appearance Approval Report Not Applicable for IC 15 Bulk Material Requirements Not Applicable for IC 16 Sample Production Parts Not attached, delivered previously 17 Master Sample Not attached. 18 Checking Aids Not applicable 19 Customer-Specific Requirements Not attached. 24 Rev. 3 : Initial Submission – 2003 October