KSZ8091RNA

KSZ8091RNA/KSZ8091RND
10Base-T/100Base-TX
Physical Layer Transceiver
Revision 1.2
General Description
Features
The KSZ8091RNA is a single-supply 10Base-T/100BaseTX Ethernet physical-layer transceiver for transmission
and reception of data over standard CAT-5 unshielded
twisted pair (UTP) cable.
• Single-chip 10Base-T/100Base-TX IEEE 802.3
compliant Ethernet transceiver
• RMII v1.2 interface support with a 50MHz reference
clock output to MAC, and an option to input a 50MHz
reference clock
• RMII back-to-back mode support for a 100Mbps copper
repeater
• MDC/MDIO management interface for PHY register
configuration
• Programmable interrupt output
• LED outputs for link and activity status indication
• On-chip termination resistors for the differential pairs
• Baseline wander correction
• HP Auto MDI/MDI-X to reliably detect and correct
straight-through and crossover cable connections with
disable and enable option
• Auto-Negotiation to automatically select the highest linkup speed (10/100Mbps) and duplex (half/full)
• Energy Efficient Ethernet (EEE) support with low-power
idle (LPI) mode for 100Base TX and transmit amplitude
reduction with 10Base-Te option
• Wake-On-LAN (WOL) support with either magic packet,
link status change, or robust custom-packet detection
®
• LinkMD TDR-based cable diagnostics to identify faulty
copper cabling
• HBM ESD rating (6kV)
The KSZ8091RNA is a highly-integrated PHY solution. It
reduces board cost and simplifies board layout by using
on-chip termination resistors for the differential pairs and
by integrating a low-noise regulator to supply the 1.2V
core, and by offering a flexible 1.8/2.5/3.3V digital I/O
interface.
The KSZ8091RNA offers the Reduced Media Independent
Interface (RMII) for direct connection with RMII-compliant
Ethernet MAC processors and switches.
As the power-up default, the KSZ8091RNA uses a 25MHz
crystal to generate all required clocks, including the
50MHz RMII reference clock output for the MAC. The
KSZ8091RND takes in the 50MHz RMII reference clock as
the power-up default.
Energy Efficient Ethernet (EEE) provides further power
saving during idle traffic periods and Wake-On-LAN (WOL)
provides a mechanism for the KSZ8091RNA to wake up a
system that is in standby power mode.
The KSZ8091RNA and KSZ8091RND are available in 24pin, lead-free QFN packages (see Ordering Information).
Datasheets and support documentation are available on
website at: www.micrel.com.
Functional Diagram
LinkMD is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
August 31, 2015
Revision 1.2
Micrel, Inc.
KSZ8091RNA/KSZ8091RND
Features (Continued)
Applications
• Parametric NAND Tree support for fault detection
between chip I/Os and the board
• Loopback modes for diagnostics
• Power-down and power-saving modes
• Single 3.3V power supply with VDD I/O options for 1.8V,
2.5V, or 3.3V
• Built-in 1.2V regulator for core
• Available in 24-pin (4mm × 4mm) QFN package
•
•
•
•
•
•
Game console
IP phone
IP set-top box
IP TV
LOM
Printer
Ordering Information
Temperature
Range
Package
Lead
Finish
0°C to 70°C
24-Pin QFN
Pb-Free
RMII with 25MHz crystal/clock input and 50MHz
RMII REF_CLK output, EEE and WoL Support,
Commercial Temperature.
KSZ8091RNAIA
−40°C to 85°C
24-Pin QFN
Pb-Free
RMII with 25MHz crystal/clock input and 50MHz
RMII REF_CLK output, EEE and WoL Support,
Industrial Temperature.
KSZ8091RNDCA
0°C to 70°C
24-Pin QFN
Pb-Free
RMII normal mode with 50MHz clock input, EEE
and WoL Support, Commercial Temperature.
−40°C to 85°C
24-Pin QFN
Pb-Free
RMII normal mode with 50MHz clock input, EEE
and WoL Support, Industrial Temperature.
Ordering Part Number
KSZ8091RNACA
(1)
(1)
KSZ8091RNDIA
Description
KSZ8091RNA-EVAL
KSZ8091RNA Evaluation Board
(Mounted with KSZ8081RNA device in
commercial temperature)
KSZ8091RND-EVAL
KSZ8091RND Evaluation Board
(Mounted with KSZ8091RND device in
commercial temperature)
Note:
1. Contact factory for lead time.
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2
Revision 1.2
Micrel, Inc.
KSZ8091RNA/KSZ8091RND
Revision History
Date
Change Description/Edits by:
Rev.
9/24/13
New datasheet.
1.0
12/2/14
Added silver wire bonding part numbers to Ordering Information.
Updated Ordering Information to include Ordering Part Number and Device Marking.
1.1
Add Max frequency for MDC in MII Management (MIIM) Interface section.
Updated ordering information Table.
Updated descriptions for Figure 19.
Add a note for Figure 20.
Updated descriptions in local loopback section for data loopback path.
Updated Table 16.
Add a note for Table 18.
Updated description and add an equation in LinkMD section.
Add HBM ESD rating in Features.
1.2
8/31/15
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KSZ8091RNA/KSZ8091RND
Contents
List of Figures .......................................................................................................................................................................... 6
List of Tables ........................................................................................................................................................................... 7
Pin Configuration ..................................................................................................................................................................... 8
Pin Description ........................................................................................................................................................................ 9
Strapping Options ................................................................................................................................................................. 12
Functional Description: 10Base-T/100Base-TX Transceiver ................................................................................................ 13
100Base-TX Transmit........................................................................................................................................................ 13
100Base-TX Receive ......................................................................................................................................................... 13
Scrambler/De-Scrambler (100Base-TX Only) ................................................................................................................... 13
10Base-T Transmit ............................................................................................................................................................ 14
10Base-T Receive ............................................................................................................................................................. 14
PLL Clock Synthesizer ...................................................................................................................................................... 14
Auto-Negotiation ................................................................................................................................................................ 14
RMII Data Interface ............................................................................................................................................................... 16
RMII Signal Definition ........................................................................................................................................................ 16
Reference Clock (REF_CLK) ......................................................................................................................................... 16
Transmit Enable (TXEN) ................................................................................................................................................ 16
Transmit Data[1:0] (TXD[1:0]) ........................................................................................................................................ 16
Carrier Sense/Receive Data Valid (CRS_DV) ............................................................................................................... 17
Receive Data[1:0] (RXD[1:0]) ........................................................................................................................................ 17
Receive Error (RXER).................................................................................................................................................... 17
Collision Detection (COL) .............................................................................................................................................. 17
RMII Signal Diagram – 25/50MHz Clock Mode ................................................................................................................. 17
RMII – 25MHz Clock Mode ............................................................................................................................................ 17
RMII – 50MHz Clock Mode ............................................................................................................................................ 18
Back-to-Back Mode – 100Mbps Copper Repeater ............................................................................................................... 19
RMII Back-to-Back Mode................................................................................................................................................... 19
MII Management (MIIM) Interface ......................................................................................................................................... 20
Interrupt (INTRP) ................................................................................................................................................................... 20
HP Auto MDI/MDI-X .............................................................................................................................................................. 21
Straight Cable .................................................................................................................................................................... 21
Crossover Cable ................................................................................................................................................................ 22
Loopback Mode ..................................................................................................................................................................... 22
Local (Digital) Loopback .................................................................................................................................................... 22
Remote (Analog) Loopback ............................................................................................................................................... 23
®
LinkMD Cable Diagnostic .................................................................................................................................................... 25
NAND Tree Support .............................................................................................................................................................. 26
NAND Tree I/O Testing ..................................................................................................................................................... 27
Power Management .............................................................................................................................................................. 28
Power-Saving Mode .......................................................................................................................................................... 28
Energy-Detect Power-Down Mode .................................................................................................................................... 28
Power-Down Mode ............................................................................................................................................................ 28
Slow-Oscillator Mode ......................................................................................................................................................... 28
Energy Efficient Ethernet (EEE) ............................................................................................................................................ 29
Transmit Direction Control (MAC-to-PHY) ........................................................................................................................ 30
Receive Direction Control (PHY-to-MAC) ......................................................................................................................... 30
Registers Associated with EEE ......................................................................................................................................... 30
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KSZ8091RNA/KSZ8091RND
Wake-On-LAN ....................................................................................................................................................................... 31
Magic-Packet Detection..................................................................................................................................................... 31
Customized-Packet Detection ........................................................................................................................................... 32
Link Status Change Detection ........................................................................................................................................... 32
Reference Circuit for Power and Ground Connections ......................................................................................................... 33
Typical Current/Power Consumption .................................................................................................................................... 34
Register Map ......................................................................................................................................................................... 36
Standard Registers ............................................................................................................................................................... 38
IEEE-Defined Registers – Descriptions ............................................................................................................................. 38
Vendor-Specific Registers – Descriptions ......................................................................................................................... 43
MMD Registers...................................................................................................................................................................... 48
MMD Register Write .......................................................................................................................................................... 49
MMD Register Read .......................................................................................................................................................... 49
MMD Registers – Descriptions .......................................................................................................................................... 50
Absolute Maximum Ratings .................................................................................................................................................. 55
Operating Ratings ................................................................................................................................................................. 55
Electrical Characteristics ....................................................................................................................................................... 55
Timing Diagrams ................................................................................................................................................................... 57
RMII Timing ....................................................................................................................................................................... 57
Auto-Negotiation Timing .................................................................................................................................................... 58
MDC/MDIO Timing ............................................................................................................................................................ 59
Power-Up/Reset Timing .................................................................................................................................................... 60
Reset Circuit .......................................................................................................................................................................... 61
Reference Circuits – LED Strap-In Pin ................................................................................................................................. 62
Reference Clock – Connection and Selection ...................................................................................................................... 63
Magnetic – Connection and Selection .................................................................................................................................. 64
Package Information and Recommended Land Pattern ....................................................................................................... 66
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KSZ8091RNA/KSZ8091RND
List of Figures
Figure 1. Auto-Negotiation Flow Chart ................................................................................................................................ 15
Figure 2. KSZ8091RNA/RND RMII Interface (RMII – 25MHz Clock Mode) ....................................................................... 18
Figure 3. KSZ8091RNA/RND RMII Interface (RMII – 50MHz Clock Mode) ....................................................................... 18
Figure 4. KSZ8091RNA/RND to KSZ8091RNA/RND Back-to-Back Copper Repeater ...................................................... 19
Figure 5. Typical Straight Cable Connection ...................................................................................................................... 21
Figure 6. Typical Crossover Cable Connection .................................................................................................................. 22
Figure 7. Local (Digital) Loopback ...................................................................................................................................... 23
Figure 8. Remote (Analog) Loopback ................................................................................................................................. 24
Figure 9. LPI Mode (Refresh Transmissions and Quiet Periods) ....................................................................................... 29
Figure 10. LPI Transition – RMII (100Mbps) Transmit .......................................................................................................... 30
Figure 11. LPI Transition – RMII (100Mbps) Receive ........................................................................................................... 30
Figure 12. KSZ8091RNA/RND Power and Ground Connections ......................................................................................... 33
Figure 13. RMII Timing – Data Received from RMII ............................................................................................................. 57
Figure 14. RMII Timing – Data Input to RMII ........................................................................................................................ 57
Figure 15. Auto-Negotiation Fast Link Pulse (FLP) Timing .................................................................................................. 58
Figure 16. MDC/MDIO Timing............................................................................................................................................... 59
Figure 17. Power-Up/Reset Timing ....................................................................................................................................... 60
Figure 18. Recommended Reset Circuit ............................................................................................................................... 61
Figure 19. Recommended Reset Circuit for Interfacing with CPU/FPGA Reset Output ...................................................... 61
Figure 20. Reference Circuits for LED Strapping Pin ........................................................................................................... 62
Figure 21. 25MHz Crystal/Oscillator Reference Clock Connection ...................................................................................... 63
Figure 22. 50MHz Oscillator/Reference Clock Connection .................................................................................................. 63
Figure 23. Typical Magnetic Interface Circuit ........................................................................................................................ 64
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KSZ8091RNA/KSZ8091RND
List of Tables
Table 1. RMII Signal Definition............................................................................................................................................ 16
Table 2. RMII Signal Connection for RMII Back-to-Back Mode (100Base-TX Copper Repeater) ..................................... 19
Table 3. MII Management Frame Format for the KSZ8091RNA/RND ............................................................................... 20
Table 4. MDI/MDI-X Pin Definition ...................................................................................................................................... 21
Table 5. NAND Tree Test Pin Order for KSZ8091RNA/RND ............................................................................................. 26
Table 6. KSZ8091RNA/RND Power Pin Description .......................................................................................................... 33
Table 7. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 3.3V) ........................................................... 34
Table 8. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 2.5V) ........................................................... 34
Table 9. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 1.8V) ........................................................... 35
Table 10. Standard Registers Supported by KSZ8091RNA/RND ........................................................................................ 36
Table 11. MMD Registers Supported by KSZ8091RNA/RND .............................................................................................. 37
Table 12. Portal Registers (Access to Indirect MMD Registers)........................................................................................... 48
Table 13. RMII Timing Parameters – KSZ8091RNA/RND (25MHz input to XI pin, 50MHz output from REF_CLK pin) ..... 57
Table 14. RMII Timing Parameters – KSZ8091RNA/RND (50MHz input to XI pin) ............................................................. 57
Table 15. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters ................................................................................ 58
Table 16. MDC/MDIO Timing Parameters ............................................................................................................................ 59
Table 17. Power-Up/Reset Timing Parameters .................................................................................................................... 60
Table 18. 25MHz Crystal/Reference Clock Selection Criteria .............................................................................................. 63
Table 19. 50MHz Oscillator/Reference Clock Selection Criteria .......................................................................................... 63
Table 20. Magnetics Selection Criteria ................................................................................................................................. 65
Table 21. Compatible Single-Port 10/100 Magnetics ........................................................................................................... 65
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Micrel, Inc.
KSZ8091RNA/KSZ8091RND
Pin Configuration
24-Pin (4mm × 4mm) QFN
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Revision 1.2
Micrel, Inc.
KSZ8091RNA/KSZ8091RND
Pin Description
Type
(2)
Pin Number
Pin Name
Pin Function
1
VDD_1.2
P
1.2V Core VDD (power supplied by KSZ8091RNA/KSZ8091RND). Decouple with
2.2µF and 0.1µF capacitors to ground.
2
VDDA_3.3
P
3.3V analog VDD.
3
RXM
I/O
Physical receive or transmit signal (– differential).
4
RXP
I/O
Physical receive or transmit signal (+ differential).
5
TXM
I/O
Physical transmit or receive signal (– differential).
6
TXP
I/O
Physical transmit or receive signal (+ differential).
7
XO
O
Crystal Feedback for 25MHz Crystal. This pin is a no connect if an oscillator or
external clock source is used.
RMII – 25MHz Mode: 25MHz ±50ppm Crystal/Oscillator/External Clock Input
RMII – 50MHz Mode: 50MHz ±50ppm Oscillator/External Clock Input
For unmanaged mode (power-up default setting),
•
KSZ8091RNA takes in the 25MHz crystal/clock on this pin.
8
XI
I
•
KSZ8091RND takes in the 50MHz clock on this pin.
After power-up, both the KSZ8091RNA and KSZ8091RND can be programmed to
either the 25MHz mode or 50MHz mode using PHY Register 1Fh, Bit [7].
See also REF_CLK (Pin 16).
Set PHY Transmit Output Current
Connect a 6.49kΩ resistor to ground on this pin.
9
REXT
I
10
MDIO
Ipu/Opu
11
MDC
Ipu
12
RXD1
Ipd/O
RMII Receive Data Output[1] .
13
RXD0
Ipu/O
RMII Receive Data Output[0] .
14
VDDIO
P
3.3V, 2.5V, or 1.8V digital VDD.
Management Interface (MII) Data I/O. This pin has a weak pull-up, is open-drain, and
requires an external 1.0kΩ pull-up resistor.
Management Interface (MII) Clock Input. This clock pin is synchronous to the MDIO
data pin.
(3)
(3)
Notes:
2. P = Power supply.
GND = Ground.
I = Input.
O = Output.
I/O = Bi-directional.
Ipu = Input with internal pull-up (see Electrical Characteristics for value).
Ipu/O = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset; output pin otherwise.
Ipu/Opu = Input with internal pull-up (see Electrical Characteristics for value) and output with internal pull-up (see Electrical Characteristics for
value).
3. RMII RX Mode: The RXD[1:0] bits are synchronous with the 50MHz RMII Reference Clock. For each clock period in which CRS_DV is asserted, two
bits of recovered data are sent by the PHY to the MAC.
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KSZ8091RNA/KSZ8091RND
Pin Description (Continued)
Pin Number
Pin Name
15
CRS_DV /
PHYAD[1:0]
16
REF_CLK
Type
(2)
Ipd/O
Ipd/O
Pin Function
RMII Mode: Carrier Sense/Receive Data Valid output
Config Mode: The pull-up/pull-down value is latched as PHYAD[1:0] at the de-assertion
of reset.
See the Strapping Options section for details.
RMII – 25MHz Mode: This pin provides the 50MHz RMII reference clock output to the
MAC.
RMII – 50MHz Mode: This pin is a no connect.
For unmanaged mode (power-up default setting),
•
KSZ8091RNA is in RMII – 25MHz mode and outputs the 50MHz RMII reference
clock on this pin.
•
KSZ8091RND is in RMII – 50MHz mode and does not use this pin.
After power-up, both KSZ8091RNA and KSZ8091RND can be programmed to either
25MHz mode or 50MHz mode using PHY Register 1Fh, Bit [7].
See also XI (Pin 8).
17
RXER /
PME_EN
Ipd/O
RMII Mode: RMII Receive Error Output
Config Mode: The pull-up/pull-down value is latched as PME_EN at the de-assertion of
reset. See the Strapping Options section for details.
Interrupt Output: Programmable interrupt output, with Register 1Bh as the Interrupt
Control/Status register, for programming the interrupt conditions and reading the
interrupt status. Register 1Fh, Bit [9] sets the interrupt output to active low (default) or
active high.
PME_N Output: Programmable PME_N output (pin option 2). When asserted low, this
pin signals that a WOL event has occurred.
This pin has a weak pull-up and is an open-drain.
For Interrupt (when active low) and PME functions, this pin requires an external 1.0kΩ
pull-up resistor to VDDIO (digital VDD).
18
INTRP/
PME_N2
Ipu/Opu
19
TXEN
I
RMII Transmit Enable Input
20
TXD0
I
RMII Transmit Data Input[0]
21
TXD1
I/O
22
GND
GND
(4)
(4)
RMII Mode: RMII Transmit Data Input[1]
NAND Tree Mode: NAND Tree Output
Ground
Note:
4. RMII TX Mode: The TXD[1:0] bits are synchronous with the 50MHz RMII Reference Clock. For each clock period in which TXEN is asserted, two bits
of data are received by the PHY from the MAC.
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KSZ8091RNA/KSZ8091RND
Pin Description (Continued)
Pin Number
Pin Name
Type
(2)
Pin Function
LED Output: Programmable LED0 output
PME_N Output: Programmable PME_N Output (pin option 1). When asserted low, this
pin signals that a WOL event has occurred. In this mode, this pin has a weak pull-up, is
an open-drain, and requires an external 1.0kΩ pull-up resistor to VDDIO (digital VDD).
Config Mode: Latched as Auto-Negotiation enable (Register 0h, Bit [12]) and Speed
(Register 0h, Bit [13]) at the de-assertion of reset. See the Strapping Options section for
details.
The LED0 pin is programmable using Register 1Fh, Bits [5:4], and is defined as follows.
LED Mode = [00]
23
LED0/
PME_N1/
ANEN_SPEED
Ipu/O
Link/Activity
Pin State
LED Definition
No link
High
OFF
Link
Low
ON
Activity
Toggle
Blinking
Link
Pin State
LED Definition
No link
High
OFF
Link
Low
ON
LED Mode = [01]
LED Mode = [10], [11]
24
RST#
Ipu
PADDLE
GND
GND
August 31, 2015
Reserved
Chip Reset (active low)
Ground
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Revision 1.2
Micrel, Inc.
KSZ8091RNA/KSZ8091RND
Strapping Options
Pin Number
Pin Name
15
PHYAD[1:0]
Type
(5 )
Ipd/O
Pin Function
The PHY Address is latched at the de-assertion of reset and is configurable to either one
of the following two values:
Pull-up = PHY Address is set to 00011b (3h)
Pull-down (default) = PHY Address is set to 00000b (0h)
PHY Address 0 is assigned by default as the broadcast PHY address, but it can be
assigned as a unique PHY address after writing a ‘1’ to Register 16h, Bit [9].
PHY Address bits [4:2] are set to 000 by default.
17
PME_EN
Ipd/O
PME Output for Wake-On-LAN
Pull-up = Enable
Pull-down (default) = Disable
At the de-assertion of reset, this pin value is latched into Register 16h, Bit [15].
Auto-Negotiation Enable and Speed Mode
Pull-up (default) = Enable Auto-Negotiation and set 100Mbps Speed
Pull-down = Disable Auto-Negotiation and set 10Mbps Speed
23
ANEN_SPEED
Ipu/O
At the de-assertion of reset, this pin value is latched into Register 0h, Bit [12] for AutoNegotiation enable/disable, Register 0h, Bit [13] for the Speed select, and Register 4h
(Auto-Negotiation Advertisement) for the Speed capability support.
Note:
5. Ipu/O = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset; output pin otherwise.
The PHYAD[1:0] and PME_EN strap-in pins are latched at the de-assertion of reset. In some systems, the RMII MAC
receive input pins may drive high/low during power-up or reset, and consequently cause the PHYAD[1:0] and PME_EN
strap-in pins, shared pin with the RMII CRS_DV and RXER signals respectively, to be latched to the unintended high/low
state. In this case an external pull-up (4.7kΩ) or pull-down (1.0kΩ) should be added on the PHYAD[1:0] and PME_EN
strap-in pins to ensure that the intended value is strapped-in correctly.
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KSZ8091RNA/KSZ8091RND
Functional Description: 10Base-T/100Base-TX Transceiver
The KSZ8091RNA is an integrated single 3.3V supply Fast Ethernet transceiver. It is fully compliant with the IEEE 802.3
Specification, and reduces board cost and simplifies board layout by using on-chip termination resistors for the two
differential pairs and by integrating the regulator to supply the 1.2V core.
On the copper media side, the KSZ8091RNA supports 10Base-T and 100Base-TX for transmission and reception of data
over a standard CAT-5 unshielded twisted pair (UTP) cable, and HP Auto MDI/MDI-X for reliable detection of and
correction for straight-through and crossover cables.
On the MAC processor side, the KSZ8091RNA offers the Reduced Media Independent Interface (RMII) for direct
connection with RMII-compliant Ethernet MAC processors and switches
The MII management bus option gives the MAC processor complete access to the KSZ8091RNA control and status
registers. Additionally, an interrupt pin eliminates the need for the processor to poll for PHY status change.
As the power-up default, the KSZ8091RNA uses a 25MHz crystal to generate all required clocks, including the 50MHz
RMII reference clock output for the MAC. The KSZ8091RND version uses the 50MHz RMII reference clock as the powerup default.
The KSZ8091RNA/RND is used to refer to both KSZ8091RNA and KSZ8091RND versions in this datasheet.
100Base-TX Transmit
The 100Base-TX transmit function performs parallel-to-serial conversion, 4B/5B encoding, scrambling, NRZ-to-NRZI
conversion, and MLT3 encoding and transmission.
The circuitry starts with a parallel-to-serial conversion, which converts the RMII data from the MAC into a 125MHz serial
bit stream. The data and control stream is then converted into 4B/5B coding and followed by a scrambler. The serialized
data is further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. The output current is set
by an external 6.49kΩ 1% resistor for the 1:1 transformer ratio.
The output signal has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude
balance, overshoot, and timing jitter. The wave-shaped 10Base-T output is also incorporated into the 100Base-TX
transmitter.
100Base-TX Receive
The 100Base-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and
clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion.
The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair
cable. Because the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust its
characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on
comparisons of incoming signal strength against some known cable characteristics, then tunes itself for optimization. This
is an ongoing process and self-adjusts against environmental changes such as temperature variations.
Next, the equalized signal goes through a DC-restoration and data-conversion block. The DC-restoration circuit
compensates for the effect of baseline wander and improves the dynamic range. The differential data-conversion circuit
converts MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock-recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used
to convert the NRZI signal to NRZ format. This signal is sent through the de-scrambler, then the 4B/5B decoder. Finally,
the NRZ serial data is converted to RMII format and provided as the input data to the MAC.
Scrambler/De-Scrambler (100Base-TX Only)
The scrambler spreads the power spectrum of the transmitted signal to reduce electromagnetic interference (EMI) and
baseline wander. The de-scrambler recovers the scrambled signal.
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KSZ8091RNA/KSZ8091RND
10Base-T Transmit
The 10Base-T drivers are incorporated with the 100Base-TX drivers to allow for transmission using the same magnetic.
The drivers perform internal wave-shaping and pre-emphasis, and output 10Base-T signals with a typical amplitude of
2.5V peak for standard 10Base-T mode and 1.75V peak for energy-efficient 10Base-Te mode. The 10Base-T/10Base-Te
signals have harmonic contents that are at least 27dB below the fundamental frequency when driven by an all-ones
Manchester-encoded signal.
10Base-T Receive
On the receive side, input buffer and level detecting squelch circuits are used. A differential input receiver circuit and a
phase-locked loop (PLL) performs the decoding function. The Manchester-encoded data stream is separated into clock
signal and NRZ data. A squelch circuit rejects signals with levels less than 400mV, or with short pulse widths, to prevent
noise at the differential line receive inputs from falsely triggering the decoder. When the input exceeds the squelch limit,
the PLL locks onto the incoming signal and the KSZ8091RNA/RND decodes a data frame. The receive clock is kept
active during idle periods between data receptions.
PLL Clock Synthesizer
The KSZ8091RNA/RND in RMII – 25MHz Clock mode generates all internal clocks and all external clocks for system
timing from an external 25MHz crystal, oscillator, or reference clock. For the KSZ8091RNA/RND in RMII – 50MHz clock
mode, these clocks are generated from an external 50MHz oscillator or system clock.
Auto-Negotiation
The KSZ8091RNA/RND conforms to the Auto-Negotiation protocol, defined in Clause 28 of the IEEE 802.3 Specification.
Auto-Negotiation allows unshielded twisted pair (UTP) link partners to select the highest common mode of operation.
During Auto-Negotiation, link partners advertise capabilities across the UTP link to each other and then compare their own
capabilities with those they received from their link partners. The highest speed and duplex setting that is common to the
two link partners is selected as the mode of operation.
The following list shows the speed and duplex operation mode from highest to lowest priority.
•
Priority 1:
100Base-TX, full-duplex
•
Priority 2:
100Base-TX, half-duplex
•
Priority 3:
10Base-T, full-duplex
•
Priority 4:
10Base-T, half-duplex
If Auto-Negotiation is not supported or the KSZ8091RNA/RND link partner is forced to bypass Auto-Negotiation, then the
KSZ8091RNA/RND sets its operating mode by observing the signal at its receiver. This is known as parallel detection,
which allows the KSZ8091RNA/RND to establish a link by listening for a fixed signal protocol in the absence of the AutoNegotiation advertisement protocol.
Auto-Negotiation is enabled by either hardware pin strapping (ANEN_SPEED, Pin 23) or software (Register 0h, Bit [12]).
By default, Auto-Negotiation is enabled after power-up or hardware reset. After that, Auto-Negotiation can be enabled or
disabled by Register 0h, Bit [12]. If Auto-Negotiation is disabled, the speed is set by Register 0h, Bit [13], and the duplex
is set by Register 0h, Bit [8].
The Auto-Negotiation link-up process is shown in Figure 1.
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Figure 1. Auto-Negotiation Flow Chart
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RMII Data Interface
The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII). It provides
a common interface between physical layer and MAC layer devices, and has the following key characteristics:
•
Pin count is 8 pins (3 pins for data transmission, 4 pins for data reception, and 1 pin for the 50MHz reference clock).
•
10Mbps and 100Mbps data rates are supported at both half- and full-duplex.
•
Data transmission and reception are independent and belong to separate signal groups.
•
Transmit data and receive data are each 2 bits wide, a dibit.
RMII Signal Definition
Table 1 describes the RMII signals. Refer to RMII Specification v1.2 for detailed information.
Table 1. RMII Signal Definition
Direction
(with respect to PHY,
KSZ8091RNA/RND signal)
Direction
(with respect to MAC)
Description
Output (25MHz clock mode)/
<no connect> (50MHz clock mode)
Input/
Input or <no connect>
Synchronous 50MHz reference clock for receive,
transmit, and control interface
TXEN
Input
Output
Transmit Enable
TXD[1:0]
Input
Output
Transmit Data[1:0]
CRS_DV
Output
Input
Carrier Sense/Receive Data Valid
RXD[1:0]
Output
Input
Receive Data[1:0]
RXER
Output
Input, or (not required)
RMII Signal
Name
REF_CLK
Receive Error
Reference Clock (REF_CLK)
REF_CLK is a continuous 50MHz clock that provides the timing reference for TXEN, TXD[1:0], CRS_DV, RXD[1:0], and
RX_ER.
For RMII – 25MHz Clock Mode, the KSZ8091RNA/RND generates and outputs the 50MHz RMII REF_CLK to the MAC at
REF_CLK (Pin 16).
For RMII – 50MHz Clock Mode, the KSZ8091RNA/RND takes in the 50MHz RMII REF_CLK from the MAC or system
board at XI (Pin 8) and leaves the REF_CLK (Pin 16) as no connect.
Transmit Enable (TXEN)
TXEN indicates that the MAC is presenting dibits on TXD[1:0] for transmission. It is asserted synchronously with the first
dibit of the preamble and remains asserted while all dibits to be transmitted are presented on the RMII. It is negated
before the first REF_CLK following the final dibit of a frame.
TXEN transitions synchronously with respect to REF_CLK.
Transmit Data[1:0] (TXD[1:0])
When TXEN is asserted, TXD[1:0] are the data dibits presented by the MAC and accepted by the PHY for transmission.
When TXEN is de-asserted, the MAC drives TXD[1:0] to either 00 for the idle state (non-EEE mode) or 01 for the LPI
state (EEE mode).
TXD[1:0] transitions synchronously with respect to REF_CLK.
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Carrier Sense/Receive Data Valid (CRS_DV)
The PHY asserts CRS_DV when the receive medium is non-idle. It is asserted asynchronously when a carrier is detected.
This happens when squelch is passed in 10Mbps mode, and when two non-contiguous 0s in 10 bits are detected in
100Mbps mode. Loss of carrier results in the de-assertion of CRS_DV.
While carrier detection criteria are met, CRS_DV remains asserted continuously from the first recovered dibit of the frame
through the final recovered dibit. It is negated before the first REF_CLK that follows the final dibit. The data on RXD[1:0] is
considered valid after CRS_DV is asserted. However, because the assertion of CRS_DV is asynchronous relative to
REF_CLK, the data on RXD[1:0] is 00 until receive signals are properly decoded.
Receive Data[1:0] (RXD[1:0])
For each clock period in which CRS_DV is asserted, RXD[1:0] transfers a dibit of recovered data from the PHY.
When CRS_DV is de-asserted, the PHY drives RXD[1:0] to either 00 for the idle state (non-EEE mode) or 01 for the LPI
state (EEE mode).
RXD[1:0] transitions synchronously with respect to REF_CLK.
Receive Error (RXER)
When CRS_DV is asserted, RXER is asserted for one or more REF_CLK periods to indicate that a symbol error (for
example, a coding error that a PHY can detect that may otherwise be undetectable by the MAC sub-layer) is detected
somewhere in the frame that is being transferred from the PHY to the MAC.
RXER transitions synchronously with respect to REF_CLK.
Collision Detection (COL)
The MAC regenerates the COL signal of the MII from TXEN and CRS_DV.
RMII Signal Diagram – 25/50MHz Clock Mode
The KSZ8091RNA/RND RMII pin connections to the MAC for 25MHz clock mode are shown in Figure 2. The connections
for 50MHz clock mode are shown in Figure 3.
RMII – 25MHz Clock Mode
The KSZ8091RNA is configured to RMII – 25MHz clock mode after it is powered up or hardware reset with the following:
•
A 25MHz crystal connected to XI, XO (Pins 8, 7), or an external 25MHz clock source (oscillator) connected to XI
The KSZ8091RND can optionally be configured to RMII – 25MHz clock mode after it is powered up or hardware reset and
software programmed with the following:
•
A 25MHz crystal connected to XI, XO (Pins 8, 7), or an external 25MHz clock source (oscillator) connected to XI
•
Register 1Fh, Bit [7] programmed to ‘1’ to select RMII – 25MHz clock mode
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Figure 2. KSZ8091RNA/RND RMII Interface (RMII – 25MHz Clock Mode)
RMII – 50MHz Clock Mode
The KSZ8091RND is configured to RMII – 50MHz clock mode after it is powered up or hardware reset with the following:
•
An external 50MHz clock source (oscillator) connected to XI (Pin 8)
The KSZ8091RNA can optionally be configured to RMII – 50MHz clock mode after it is powered up or hardware reset and
software programmed with the following:
•
An external 50MHz clock source (oscillator) connected to XI (Pin 8)
•
Register 1Fh, Bit [7] programmed to ‘1’ to select RMII – 50MHz clock mode
Figure 3. KSZ8091RNA/RND RMII Interface (RMII – 50MHz Clock Mode)
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Back-to-Back Mode – 100Mbps Copper Repeater
Two KSZ8091RNA/RND devices can be connected back-to-back to form a managed 100Base-TX copper repeater.
Figure 4. KSZ8091RNA/RND to KSZ8091RNA/RND Back-to-Back Copper Repeater
RMII Back-to-Back Mode
In RMII back-to-back mode, a KSZ8091RNA/RND interfaces with another KSZ8091RNA/RND to provide a 100Mbps
copper repeater solution.
The KSZ8091RNA/RND devices are configured to RMII back-to-back mode after power-up or reset, and software
programming, with the following:
•
A common 50MHz reference clock connected to XI (Pin 8) of both KSZ8091RNA/RND devices.
•
Register 1Fh, Bit [7] programmed to ‘1’ to select RMII – 50MHz clock mode for KSZ8091RNA.
(KSZ8091RND is set to RMII – 50MHz clock mode as the default after power up or hardware reset).
•
Register 16h, Bits [6] and [1] programmed to ‘1’ and ‘1’, respectively, to enable RMII back-to-back mode.
•
RMII signals connected as shown in Table 2.
Table 2. RMII Signal Connection for RMII Back-to-Back Mode (100Base-TX Copper Repeater)
KSZ8091RNA/RND (100Base-TX copper)
[Device 1]
KSZ8091RNA/RND (100Base-TX copper)
[Device 2]
Pin Name
Pin Number
Pin Type
Pin Name
Pin Number
Pin Type
CRSDV
15
Output
TXEN
19
Input
RXD1
12
Output
TXD1
21
Input
RXD0
13
Output
TXD0
20
Input
TXEN
19
Input
CRSDV
15
Output
TXD1
21
Input
RXD1
12
Output
TXD0
20
Input
RXD0
13
Output
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MII Management (MIIM) Interface
The KSZ8091RNA/RND supports the IEEE 802.3 MII management interface, also known as the Management Data
Input/Output (MDIO) interface. This interface allows an upper-layer device, such as a MAC processor, to monitor and
control the state of the KSZ8091RNA/RND. An external device with MIIM capability is used to read the PHY status and/or
configure the PHY settings. More details about the MIIM interface can be found in Clause 22.2.4 of the IEEE 802.3
Specification.
The MIIM interface consists of the following:
•
A physical connection that incorporates the clock line (MDC) and the data line (MDIO).
•
A specific protocol that operates across the physical connection mentioned earlier, which allows the external controller
to communicate with one or more PHY devices.
•
A 32-register address space for direct access to IEEE-defined registers and vendor-specific registers, and for indirect
access to MMD addresses and registers. See the Register Map section.
The KSZ8091RNA/RND supports only two unique PHY addresses. The PHYAD[1:0] strapping pin is used to select either
0h or 3h as the unique PHY address for the KSZ8091RNA/RND device.
PHY Address 0h is defined as the broadcast PHY address according to the IEEE 802.3 Specification, and can be used to
read/write to a single PHY device, or write to multiple PHY devices simultaneously. For the KSZ8091RNA/RND, PHY
Address 0h defaults to the broadcast PHY address after power-up, but PHY Address 0h can be disabled as the broadcast
PHY address using software to assign it as a unique PHY address.
For applications that require two KSZ8091RNA/RND PHYs to share the same MDIO interface with one PHY set to
Address 0h and the other PHY set to Address 3h, use PHY Address 0h (defaults to broadcast after power-up) to set both
PHYs’ Register 16h, Bit [9] to ‘1’ to assign PHY Address 0h as a unique (non-broadcast) PHY address.
The MIIM interface can operates up to a maximum clock speed of 10MHz MAC clock.
Table 3 shows the MII management frame format for the KSZ8091RNA/RND.
Table 3. MII Management Frame Format for the KSZ8091RNA/RND
Preamble
Start of
Frame
Read/Write
OP Code
PHY Address
Bits [4:0]
REG Address
Bits [4:0]
TA
Data
Bits [15:0]
Read
32 1’s
01
10
000AA
RRRRR
Z0
DDDDDDDD_DDDDDDDD
Z
Write
32 1’s
01
01
000AA
RRRRR
10
DDDDDDDD_DDDDDDDD
Z
Idle
Interrupt (INTRP)
INTRP (Pin 18) is an optional interrupt signal that is used to inform the external controller that there has been a status
update to the KSZ8091RNA/RND PHY register. Bits [15:8] of Register 1Bh are the interrupt control bits to enable and
disable the conditions for asserting the INTRP signal. Bits [7:0] of Register 1Bh are the interrupt status bits to indicate
which interrupt conditions have occurred. The interrupt status bits are cleared after reading Register 1Bh.
Bit [9] of Register 1Fh sets the interrupt level to active high or active low. The default is active low.
The MII management bus option gives the MAC processor complete access to the KSZ8091RNA/RND control and status
registers. Additionally, an interrupt pin eliminates the need for the processor to poll the PHY for status change.
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HP Auto MDI/MDI-X
HP Auto MDI/MDI-X configuration eliminates the need to decide whether to use a straight cable or a crossover cable
between the KSZ8091RNA/RND and its link partner. This feature allows the KSZ8091RNA/RND to use either type of
cable to connect with a link partner that is in either MDI or MDI-X mode. The auto-sense function detects transmit and
receive pairs from the link partner and assigns transmit and receive pairs to the KSZ8091RNA/RND accordingly.
HP Auto MDI/MDI-X is enabled by default. It is disabled by writing a ‘1’ to Register 1Fh, Bit [13]. MDI and MDI-X mode is
selected by Register 1Fh, Bit [14] if HP Auto MDI/MDI-X is disabled.
An isolation transformer with symmetrical transmit and receive data paths is recommended to support Auto MDI/MDI-X.
Table 4 shows how the IEEE 802.3 Standard defines MDI and MDI-X.
Table 4. MDI/MDI-X Pin Definition
MDI
MDI-X
RJ-45 Pin
Signal
RJ-45 Pin
Signal
1
TX+
1
RX+
2
TX−
2
RX−
3
RX+
3
TX+
6
RX−
6
TX−
Straight Cable
A straight cable connects an MDI device to an MDI-X device, or an MDI-X device to an MDI device. Figure 5 shows a
typical straight cable connection between a NIC card (MDI device) and a switch or hub (MDI-X device).
Figure 5. Typical Straight Cable Connection
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Crossover Cable
A crossover cable connects an MDI device to another MDI device, or an MDI-X device to another MDI-X device. Figure 6
shows a typical crossover cable connection between two switches or hubs (two MDI-X devices).
Figure 6. Typical Crossover Cable Connection
Loopback Mode
The KSZ8091RNA/RND supports the following loopback operations to verify analog and/or digital data paths.
•
Local (digital) loopback
•
Remote (analog) loopback
Local (Digital) Loopback
This loopback mode checks the RMII transmit and receive data paths between the KSZ8091RNA/RND and the external
MAC, and is supported for both speeds (10/100Mbps) at full-duplex.
The loopback data path is shown in Figure 7.
1. The RMII MAC transmits frames to the KSZ8091RNA/RND.
2. Frames are wrapped around inside the KSZ8091RNA/RND.
3. The KSZ8091RNA/RND transmits frames back to the RMII MAC.
4. Except the frames back to the RMII MAC, the transmit frames also go out from the copper port.
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Figure 7. Local (Digital) Loopback
The following programming action and register settings are used for local loopback mode.
For 10/100Mbps loopback,
Set Register 0h,
Bit [14] = 1
Bit [13] = 0/1
Bit [12] = 0
Bit [8] = 1
// Enable local loopback mode
// Select 10Mbps/100Mbps speed
// Disable Auto-Negotiation
// Select full-duplex mode
Remote (Analog) Loopback
This loopback mode checks the line (differential pairs, transformer, RJ-45 connector, Ethernet cable) transmit and receive
data paths between the KSZ8091RNA/RND and its link partner, and is supported for 100Base-TX full-duplex mode only.
The loopback data path is shown in Figure 8.
1. The Fast Ethernet (100Base-TX) PHY link partner transmits frames to the KSZ8091RNA/RND.
2. Frames are wrapped around inside the KSZ8091RNA/RND.
3. The KSZ8091RNA/RND transmits frames back to the Fast Ethernet (100Base-TX) PHY link partner.
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Figure 8. Remote (Analog) Loopback
The following programming steps and register settings are used for remote loopback mode.
1. Set Register 0h,
Bit [13] = 1
Bit [12] = 0
Bit [8] = 1
// Select 100Mbps speed
// Disable Auto-Negotiation
// Select full-duplex mode
Or just auto-negotiate and link up with the link partner at 100Base-TX full-duplex mode.
2. Set Register 1Fh,
Bit [2] = 1
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LinkMD® Cable Diagnostic
The LinkMD function uses time-domain reflectometry (TDR) to analyze the cabling plant for common cabling problems.
These include open circuits, short circuits, and impedance mismatches.
LinkMD works by sending a pulse of known amplitude and duration down the MDI or MDI-X pair, then analyzing the shape
of the reflected signal to determine the type of fault. The time duration for the reflected signal to return provides the
approximate distance to the cabling fault. The LinkMD function processes this TDR information and presents it as a
numerical value that can be translated to a cable distance.
LinkMD is initiated by accessing Register 1Dh, the LinkMD Cable Diagnostic Register, in conjunction with Register 1Fh,
the PHY Control 2 Register. The latter register is used to disable Auto MDI/MDI-X and to select either MDI or MDI-X as
the cable differential pair for testing.
Usage
The following is a sample procedure for using LinkMD with Registers 1Dh and 1Fh:
3. Disable auto MDI/MDI-X by writing a ‘1’ to Register 1Fh, bit [13].
4. Start cable diagnostic test by writing a ‘1’ to Register 1Dh, bit [15]. This enable bit is self-clearing.
5. Wait (poll) for Register 1Dh, bit [15] to return a ‘0’, and indicating cable diagnostic test is completed.
6. Read cable diagnostic test results in Register 1Dh, bits [14:13]. The results are as follows:
00 = normal condition (valid test)
01 = open condition detected in cable (valid test)
10 = short condition detected in cable (valid test)
11 = cable diagnostic test failed (invalid test)
The ‘11’ case, invalid test, occurs when the device is unable to shut down the link partner. In this instance, the test is
not run, since it would be impossible for the device to determine if the detected signal is a reflection of the signal
generated or a signal from another source.
7. Get distance to fault by concatenating Register 1Dh, bits [8:0] and multiplying the result by a constant of 0.38. The
distance to the cable fault can be determined by the following formula:
D (distance to cable fault) = 0.38 x (Register 1Dh, bits [8:0])
D (distance to cable fault) is expressed in meters.
Concatenated value of Registers 1Dh bits [8:0] should be converted to decimal before multiplying by 0.38.
The constant (0.38) may be calibrated for different cabling conditions, including cables with a velocity of propagation
that varies significantly from the norm.
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NAND Tree Support
The KSZ8091RNA/RND provides parametric NAND tree support for fault detection between chip I/Os and board. The
NAND tree is a chain of nested NAND gates in which each KSZ8091RNA/RND digital I/O (NAND tree input) pin is an
input to one NAND gate along the chain. At the end of the chain, the TXD1 pin provides the output for the nested NAND
gates.
The NAND tree test process includes:
•
Enabling NAND tree mode
•
Pulling all NAND tree input pins high
•
Driving each NAND tree input pin low, sequentially, according to the NAND tree pin order
•
Checking the NAND tree output to make sure there is a toggle high-to-low or low-to-high for each NAND tree input
driven low
Table 5 lists the NAND tree pin order
Table 5. NAND Tree Test Pin Order for KSZ8091RNA/RND
Pin Number
Pin Name
NAND Tree Description
10
MDIO
Input
11
MDC
Input
12
RXD1
Input
13
RXD0
Input
15
CRS_DV
Input
16
REF_CLK
Input
18
INTRP
Input
19
TXEN
Input
23
LED0
Input
20
TXD0
Input
21
TXD1
Output
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NAND Tree I/O Testing
Use the following procedure to check for faults on the KSZ8091RNA/RND digital I/O pin connections to the board:
1. Enable NAND tree mode by setting Register 16h, Bit [5] to ‘1’.
2. Use board logic to drive all KSZ8091RNA/RND NAND tree input pins high.
3. Use board logic to drive each NAND tree input pin, in KSZ8091RNA/RND NAND tree pin order, as follows:
a. Toggle the first pin (MDIO) from high to low, and verify that the TXD1 pin switches from high to low to indicate that
the first pin is connected properly.
b. Leave the first pin (MDIO) low.
c.
Toggle the second pin (MDC) from high to low, and verify that the TXD1 pin switches from low to high to indicate
that the second pin is connected properly.
d. Leave the first pin (MDIO) and the second pin (MDC) low.
e. Toggle the third pin (RXD1) from high to low, and verify that the TXD1 pin switches from high to low to indicate
that the third pin is connected properly.
f.
Continue with this sequence until all KSZ8091RNA/RND NAND tree input pins have been toggled.
Each KSZ8091RNA/RND NAND tree input pin must cause the TXD1 output pin to toggle high-to-low or low-to-high to
indicate a good connection. If the TXD1 pin fails to toggle when the KSZ8091RNA/RND input pin toggles from high to low,
the input pin has a fault.
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Power Management
The KSZ8091RNA/RND incorporates a number of power-management modes and features that provide methods to
consume less energy. These are discussed in the following sections.
Power-Saving Mode
Power-saving mode is used to reduce the transceiver power consumption when the cable is unplugged. It is enabled by
writing a ‘1’ to Register 1Fh, Bit [10], and is in effect when Auto-Negotiation mode is enabled and the cable is
disconnected (no link).
In this mode, the KSZ8091RNA/RND shuts down all transceiver blocks, except for the transmitter, energy detect, and PLL
circuits.
By default, power-saving mode is disabled after power-up.
Energy-Detect Power-Down Mode
Energy-detect power-down (EDPD) mode is used to further reduce transceiver power consumption when the cable is
unplugged. It is enabled by writing a ‘0’ to Register 18h, Bit [11], and is in effect when Auto-Negotiation mode is enabled
and the cable is disconnected (no link).
EDPD mode works with the PLL off (set by writing a ‘1’ to Register 10h, Bit [4] to automatically turn the PLL off in EDPD
mode) to turn off all KSZ8091RNA/RND transceiver blocks except the transmitter and energy-detect circuits.
Power can be reduced further by extending the time interval between transmissions of link pulses to check for the
presence of a link partner. The periodic transmission of link pulses is needed to ensure the KSZ8091RNA/RND and its
link partner, when operating in the same low-power state and with Auto MDI/MDI-X disabled, can wake up when the cable
is connected between them.
By default, EDPD mode is disabled after power-up.
Power-Down Mode
Power-down mode is used to power down the KSZ8091RNA/RND device when it is not in use after power-up. It is
enabled by writing a ‘1’ to Register 0h, Bit [11].
In this mode, the KSZ8091RNA/RND disables all internal functions except the MII management interface. The
KSZ8091RNA/RND exits (disables) power-down mode after Register 0h, Bit [11] is set back to ‘0’.
Slow-Oscillator Mode
Slow-oscillator mode is used to disconnect the input reference crystal/clock on XI (Pin 8) and select the on-chip slow
oscillator when the KSZ8091RNA/RND device is not in use after power-up. It is enabled by writing a ‘1’ to Register 11h,
Bit [5].
Slow-oscillator mode works in conjunction with power-down mode to put the KSZ8091RNA/RND device in the lowest
power state, with all internal functions disabled except the MII management interface. To properly exit this mode and
return to normal PHY operation, use the following programming sequence:
1. Disable slow-oscillator mode by writing a ‘0’ to Register 11h, Bit [5].
2. Disable power-down mode by writing a ‘0’ to Register 0h, Bit [11].
3. Initiate software reset by writing a ‘1’ to Register 0h, Bit [15].
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Energy Efficient Ethernet (EEE)
The KSZ8091RNA/RND implements Energy Efficient Ethernet (EEE) as described in the IEEE Standard 802.3az for
100Base-TX copper signaling by the two differential pairs (analog side) and according to the multisource agreement
(MSA) of collaborating Fast Ethernet chip vendors for the RMII (digital side). The MSA agreement is based on the IEEE
Standard’s EEE implementation for the 100Mbps Media Independent Interface (MII). The IEEE Standard is defined
around an EEE-compliant MAC on the host side and an EEE-compliant link partner on the line side that support special
signaling associated with EEE. EEE saves power by keeping the AC signal on the copper Ethernet cable at approximately
0V peak-to-peak as often as possible during periods of no traffic activity, while maintaining the link-up status. This is
referred to as low-power idle (LPI) mode or state.
During LPI mode, the copper link responds automatically when it receives traffic and resumes normal PHY operation
immediately, without blockage of traffic or loss of packet. This involves exiting LPI mode and returning to normal 100Mbps
operating mode. Wake-up time is <30µs for 100Base-TX.
The LPI state is controlled independently for transmit and receive paths, allowing the LPI state to be active (enabled) for:
•
Transmit cable path only
•
Receive cable path only
•
Both transmit and receive cable paths
The KSZ8091RNA/RND has the EEE function disabled as the power-up default setting. To enable the EEE function for
100Mbps mode, use the following programming sequence:
1. Enable 100Mbps EEE mode advertisement by writing a ‘1’ to MMD Address 7h, Register 3Ch, Bit [1].
2. Restart Auto-Negotiation by writing a ‘1’ to standard Register 0h, Bit [9].
For standard (non-EEE) 10Base-T mode, normal link pulses (NLPs) with long periods of no AC signal transmission are
used to maintain the link during the idle period when there is no traffic activity. To save more power, the
KSZ8091RNA/RND provides the option to enable 10Base-Te mode, which saves additional power by reducing the
transmitted signal amplitude from 2.5V to 1.75V. To enable 10Base-Te mode, write a ‘1’ to standard Register 13h, Bit [4]
and write a ‘0’ to MMD Address 1Ch, Register 4h, Bit [13].
During LPI mode, refresh transmissions are used to maintain the link; power savings occur in quiet periods. Approximately
every 20ms to 22ms, a refresh transmission of 200µs to 220µs is sent to the link partner. The refresh transmissions and
quiet periods are shown in Figure 9.
Figure 9. LPI Mode (Refresh Transmissions and Quiet Periods)
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KSZ8091RNA/KSZ8091RND
Transmit Direction Control (MAC-to-PHY)
The KSZ8091RNA/RND enters LPI mode for the transmit direction when its attached EEE-compliant RMII MAC deasserts TXEN and sets TXD[1:0] to 01. The KSZ8091RNA/RND remains in the LPI transmit state while the RMII MAC
maintains the states of these signals. When the RMII MAC changes any of the TXEN or TX data signals from their LPI
state values, the KSZ8091RNA/RND exits the LPI transmit state.
Figure 10 shows the LPI transition for RMII (100Mbps) transmit.
Figure 10. LPI Transition – RMII (100Mbps) Transmit
Receive Direction Control (PHY-to-MAC)
The KSZ8091RNA/RND enters LPI mode for the receive direction when it receives the /P/ code bit pattern
(Sleep/Refresh) from its EEE-compliant link partner. It then de-asserts CRS_DV and drives RXD[1:0] to 01. The
KSZ8091RNA/RND remains in the LPI receive state while it continues to receive the refresh from its link partner, so it will
continue to maintain and drive the LPI output states for the RMII receive signals to inform the attached EEE-compliant
RMII MAC that it is in the LPI receive state. When the KSZ8091RNA/RND receives a non /P/ code bit pattern (nonrefresh), it exits the LPI receive state and sets the CRS_DV and RX data signals to set a normal frame or normal idle.
Figure 11 shows the LPI transition for RMII (100Mbps) receive.
Figure 11. LPI Transition – RMII (100Mbps) Receive
Registers Associated with EEE
The following registers are provided for EEE configuration and management:
•
Standard Register 13h – AFE Control 4 (to enable 10Base-Te mode)
•
MMD Address 1h, Register 0h – PMA/PMD Control 1 (to enable LPI)
•
MMD Address 1h, Register 1h – PMA/PMD Status 1 (for LPI status)
•
MMD Address 7h, Register 3Ch – EEE Advertisement
•
MMD Address 7h, Register 3Dh – EEE Link Partner Advertisement
•
MMD Address 1Ch, Register 4h – DSP 10Base-T/10Base-Te Control
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KSZ8091RNA/KSZ8091RND
Wake-On-LAN
Wake-On-LAN (WOL) is normally a MAC-based function to wake up a host system (for example, an Ethernet end device,
such as a PC) that is in standby power mode. Wake-up is triggered by receiving and detecting a special packet
(commonly referred to as the “magic packet”) that is sent by the remote link partner. The KSZ8091RNA/RND can perform
the same WOL function if the MAC address of its associated MAC device is entered into the KSZ8091RNA/RND PHY
Registers for magic-packet detection. When the KSZ8091RNA/RND detects the magic packet, it wakes up the host by
driving its power management event (PME) output pin low.
By default, the WOL function is disabled. It is enabled by setting the enabling bit and configuring the associated registers
for the selected PME wake-up detection method.
The KSZ8091RNA/RND provides three methods to trigger a PME wake-up:
•
Magic-packet detection
•
Customized-packet detection
•
Link status change detection
Magic-Packet Detection
The magic packet’s frame format starts with 6 bytes of 0xFFh and is followed by 16 repetitions of the MAC address of its
associated MAC device (local MAC device).
When the magic packet is detected from its link partner, the KSZ8091RNA/RND asserts its PME output pin low.
The following MMD Address 1Fh registers are provided for magic-packet detection:
•
Magic-packet detection is enabled by writing a ‘1’ to MMD Address 1Fh, Register 0h, Bit [6]
•
The MAC address (for the local MAC device) is written to and stored in MMD Address 1Fh, Registers 19h – 1Bh
The KSZ8091RNA/RND does not generate the magic packet. The magic packet must be provided by the external system.
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Customized-Packet Detection
The customized packet has associated register/bit masks to select which byte, or bytes, of the first 64 bytes of the packet
to use in the CRC calculation. After the KSZ8091RNA/RND receives the packet from its link partner, the selected bytes for
the received packet are used to calculate the CRC. The calculated CRC is compared to the expected CRC value that was
previously written to and stored in the KSZ8091RNA/RND PHY Registers. If there is a match, the KSZ8091RNA/RND
asserts its PME output pin low.
Four customized packets are provided to support four types of wake-up scenarios. A dedicated set of registers is used to
configure and enable each customized packet.
The following MMD Registers are provided for customized-packet detection:
•
Each of the four customized packets is enabled via MMD Address 1Fh, Register 0h,
Bit [2]
Bit [3]
Bit [4]
Bit [5]
•
// For customized packets, type 0
// For customized packets, type 1
// For customized packets, type 2
// For customized packets, type 3
Masks to indicate which of the first 64-bytes to use in the CRC calculation are set in:
MMD Address 1Fh, Registers 1h – 4h
MMD Address 1Fh, Registers 7h – Ah
MMD Address 1Fh, Registers Dh – 10h
MMD Address 1Fh, Registers 13h – 16h
•
// For customized packets, type 0
// For customized packets, type 1
// For customized packets, type 2
// For customized packets, type 3
32-bit expected CRCs are written to and stored in:
MMD Address 1Fh, Registers 5h – 6h
MMD Address 1Fh, Registers Bh – Ch
MMD Address 1Fh, Registers 11h – 12h
MMD Address 1Fh, Registers 17h – 18h
// For customized packets, type 0
// For customized packets, type 1
// For customized packets, type 2
// For customized packets, type 3
Link Status Change Detection
If link status change detection is enabled, the KSZ8091RNA/RND asserts its PME output pin low whenever there is a link
status change, using the following MMD Address 1Fh register bits and their enabled (1) or disabled (0) settings:
•
MMD Address 1Fh, Register 0h, Bit [0]
// For link-up detection
•
MMD Address 1Fh, Register 0h, Bit [1]
// For link-down detection
The PME output signal is available on either INTRP/PME_N2 (Pin 18) or LED0/PME_N1 (pin 23), and is enabled using
standard Register 16h, Bit [15]. MMD Address 1Fh, Register 0h, Bits [15:14] defines and selects the output functions for
Pins 18 and 23.
The PME output is active low and requires a 1kΩ pull-up to the VDDIO supply. When asserted, the PME output is cleared
by disabling the register bit that enabled the PME trigger source (magic packet, customized packet, link status change).
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KSZ8091RNA/KSZ8091RND
Reference Circuit for Power and Ground Connections
The KSZ8091RNA/RND is a single 3.3V supply device with a built-in regulator to supply the 1.2V core. The power and
ground connections are shown in Figure 12 and Table 6 for 3.3V VDDIO.
Figure 12. KSZ8091RNA/RND Power and Ground Connections
Table 6. KSZ8091RNA/RND Power Pin Description
Power Pin
Pin Number
Description
VDD_1.2
1
Decouple with 2.2µF and 0.1µF capacitors to ground.
VDDA_3.3
2
Connect to board’s 3.3V supply through a ferrite bead.
Decouple with 22µF and 0.1µF capacitors to ground.
VDDIO
14
Connect to board’s 3.3V supply for 3.3V VDDIO.
Decouple with 22µF and 0.1µF capacitors to ground.
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KSZ8091RNA/KSZ8091RND
Typical Current/Power Consumption
Table 7, Table 8, and Table 9 show typical values for current consumption by the transceiver (VDDA_3.3) and digital I/O
(VDDIO) power pins, and typical values for power consumption by the KSZ8091RNA/RND device for the indicated
nominal operating voltages. These current and power consumption values include the transmit driver current and on-chip
regulator current for the 1.2V core.
Table 7. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 3.3V)
Transceiver (3.3V), Digital I/Os (3.3V)
3.3V Transceiver
(VDDA_3.3)
3.3V Digital I/Os
(VDDIO)
Total Chip Power
mA
mA
mW
100Base-TX Link-up (no traffic)
34
12
152
100Base-TX Full-duplex @ 100% utilization
34
13
155
10Base-T Link-up (no traffic)
14
11
82.5
10Base-T Full-duplex @ 100% utilization
30
11
135
EEE 100Mbps Link-up mode
(transmit and receive in LPI state with no traffic)
13
10
75.9
Power-saving mode (Reg. 1Fh, Bit [10] = 1)
13
10
75.9
EDPD mode (Reg. 18h, Bit [11] = 0)
10
10
66.0
EDPD mode (Reg. 18h, Bit [11] = 0) and
PLL off (Reg. 10h, Bit [4] = 1)
3.77
1.54
17.5
Software power-down mode (Reg. 0h, Bit [11] =1)
2.59
1.51
13.5
Software power-down mode (Reg. 0h, Bit [11] =1) and
slow-oscillator mode (Reg. 11h, Bit [5] =1)
1.36
0.45
5.97
3.3V Transceiver
(VDDA_3.3)
2.5V Digital I/Os
(VDDIO)
Total Chip Power
mA
mA
mW
100Base-TX Link-up (no traffic)
34
11
140
100Base-TX Full-duplex @ 100% utilization
34
12
142
10Base-T Link-up (no traffic)
15
10
74.5
10Base-T Full-duplex @ 100% utilization
27
10
114
EEE 100Mbps Link-up mode
(transmit and receive in LPI state with no traffic)
13
10
67.9
Power-saving mode (Reg. 1Fh, Bit [10] = 1)
13
10
67.9
EDPD mode (Reg. 18h, Bit [11] = 0)
11
10
61.3
EDPD mode (Reg. 18h, Bit [11] = 0) and
PLL off (Reg. 10h, Bit [4] = 1)
3.55
1.35
15.1
Software power-down mode (Reg. 0h, Bit [11] =1)
2.29
1.34
10.9
Software power-down mode (Reg. 0h, Bit [11] =1) and
slow-oscillator mode (Reg. 11h, Bit [5] =1)
1.15
0.29
4.52
Condition
Table 8. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 2.5V)
Transceiver (3.3V), Digital I/Os (2.5V)
Condition
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KSZ8091RNA/KSZ8091RND
Table 9. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 1.8V)
Transceiver (3.3V), Digital I/Os (1.8V)
3.3V Transceiver
(VDDA_3.3)
1.8V Digital I/Os
(VDDIO)
Total Chip Power
mA
mA
mW
100Base-TX Link-up (no traffic)
34
11
132
100Base-TX Full-duplex @ 100% utilization
34
12
134
10Base-T Link-up (no traffic)
15
9.0
65.7
10Base-T Full-duplex @ 100% utilization
27
9.0
105
EEE 100Mbps Link-up mode
(transmit and receive in LPI state with no traffic)
13
9.0
59.1
Power-saving mode (Reg. 1Fh, Bit [10] = 1)
13
9.0
59.1
EDPD mode (Reg. 18h, Bit [11] = 0)
11
9.0
52.5
EDPD mode (Reg. 18h, Bit [11] = 0) and
PLL off (Reg. 10h, Bit [4] = 1)
4.05
1.21
15.5
Software power-down mode (Reg. 0h, Bit [11] =1)
2.79
1.21
11.4
Software power-down mode (Reg. 0h, Bit [11] =1) and
slow-oscillator mode (Reg. 11h, Bit [5] =1)
1.65
0.19
5.79
Condition
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KSZ8091RNA/KSZ8091RND
Register Map
The register space within the KSZ8091RNA/RND consists of two distinct areas.
•
Standard registers: // Direct register access
•
MDIO manageable device (MMD) registers: // Indirect register access
The KSZ8091RNA/RND supports the following standard registers:
Table 10. Standard Registers Supported by KSZ8091RNA/RND
Register Number (Hex)
Description
IEEE-Defined Registers
0h
Basic Control
1h
Basic Status
2h
PHY Identifier 1
3h
PHY Identifier 2
4h
Auto-Negotiation Advertisement
5h
Auto-Negotiation Link Partner Ability
6h
Auto-Negotiation Expansion
7h
Auto-Negotiation Next Page
8h
Auto-Negotiation Link Partner Next Page Ability
9h – Ch
Reserved
Dh
MMD Access – Control
Eh
MMD Access – Register/Data
Fh
Reserved
Vendor-Specific Registers
10h
Digital Reserved Control
11h
AFE Control 1
12h
Reserved
13h
AFE Control 4
14h
Reserved
15h
RXER Counter
16h
Operation Mode Strap Override
17h
Operation Mode Strap Status
18h
Expanded Control
19h – 1Ah
Reserved
1Bh
Interrupt Control/Status
1Ch
Reserved
1Dh
LinkMD Cable Diagnostic
1Eh
PHY Control 1
1Fh
PHY Control 2
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KSZ8091RNA/KSZ8091RND
The KSZ8091RNA/RND supports the following MMD device addresses and their associated register addresses, which
make up the indirect MMD registers:
Table 11. MMD Registers Supported by KSZ8091RNA/RND
Device Address (Hex)
1h
7h
1Ch
1Fh
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Register Address (Hex)
Description
0h
PMA/PMD Control 1
1h
PMA/PMD Status 1
3Ch
EEE Advertisement
3Dh
EEE Link Partner Advertisement
4h
DSP 10Base-T/10Base-Te Control
0h
Wake-On-LAN – Control
1h
Wake-On-LAN – Customized Packet, Type 0, Mask 0
2h
Wake-On-LAN – Customized Packet, Type 0, Mask 1
3h
Wake-On-LAN – Customized Packet, Type 0, Mask 2
4h
Wake-On-LAN – Customized Packet, Type 0, Mask 3
5h
Wake-On-LAN – Customized Packet, Type 0, Expected CRC 0
6h
Wake-On-LAN – Customized Packet, Type 0, Expected CRC 1
7h
Wake-On-LAN – Customized Packet, Type 1, Mask 0
8h
Wake-On-LAN – Customized Packet, Type 1, Mask 1
9h
Wake-On-LAN – Customized Packet, Type 1, Mask 2
Ah
Wake-On-LAN – Customized Packet, Type 1, Mask 3
Bh
Wake-On-LAN – Customized Packet, Type 1, Expected CRC 0
Ch
Wake-On-LAN – Customized Packet, Type 1, Expected CRC 1
Dh
Wake-On-LAN – Customized Packet, Type 2, Mask 0
Eh
Wake-On-LAN – Customized Packet, Type 2, Mask 1
Fh
Wake-On-LAN – Customized Packet, Type 2, Mask 2
10h
Wake-On-LAN – Customized Packet, Type 2, Mask 3
11h
Wake-On-LAN – Customized Packet, Type 2, Expected CRC 0
12h
Wake-On-LAN – Customized Packet, Type 2, Expected CRC 1
13h
Wake-On-LAN – Customized Packet, Type 3, Mask 0
14h
Wake-On-LAN – Customized Packet, Type 3, Mask 1
15h
Wake-On-LAN – Customized Packet, Type 3, Mask 2
16h
Wake-On-LAN – Customized Packet, Type 3, Mask 3
17h
Wake-On-LAN – Customized Packet, Type 3, Expected CRC 0
18h
Wake-On-LAN – Customized Packet, Type 3, Expected CRC 1
19h
Wake-On-LAN – Magic Packet, MAC-DA-0
1Ah
Wake-On-LAN – Magic Packet, MAC-DA-1
1Bh
Wake-On-LAN – Magic Packet, MAC-DA-2
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KSZ8091RNA/KSZ8091RND
Standard Registers
Standard registers provide direct read/write access to a 32-register address space, as defined in Clause 22 of the IEEE
802.3 Specification. Within this address space, the first 16 registers (Registers 0h to Fh) are defined according to the
IEEE specification, while the remaining 16 registers (Registers 10h to 1Fh) are defined specific to the PHY vendor.
IEEE-Defined Registers – Descriptions
Address
Name
(6)
Description
Mode
Default
Register 0h – Basic Control
0.15
Reset
1 = Software reset
0 = Normal operation
This bit is self-cleared after a ‘1’ is written to it.
RW/SC
0
0.14
Loopback
1 = Loopback mode
0 = Normal operation
RW
0
0.13
Speed Select
1 = 100Mbps
0 = 10Mbps
This bit is ignored if Auto-Negotiation is enabled
(Register 0.12 = 1).
RW
Set by the ANEN_SPEED
strapping pin.
See the Strapping Options section
for details.
0.12
AutoNegotiation
Enable
1 = Enable Auto-Negotiation process
0 = Disable Auto-Negotiation process
If enabled, the Auto-Negotiation result overrides
the settings in Registers 0.13 and 0.8.
RW
Set by the ANEN_SPEED
strapping pin.
See the Strapping Options section
for details.
0.11
Power-Down
1 = Power-down mode
0 = Normal operation
If software reset (Register 0.15) is used to exit
power-down mode (Register 0.11 = 1), two
software reset writes (Register 0.15 = 1) are
required. The first write clears power-down
mode; the second write resets the chip and relatches the pin strapping pin values.
RW
0
0.10
Isolate
1 = Electrical isolation of PHY from RMII
0 = Normal operation
RW
0
0.9
Restart AutoNegotiation
1 = Restart Auto-Negotiation process
0 = Normal operation.
This bit is self-cleared after a ‘1’ is written to it.
RW/SC
0
0.8
Duplex Mode
1 = Full-duplex
0 = Half-duplex
RW
1
0.7
Collision Test
1 = Enable COL test
0 = Disable COL test
RW
0
0.6:0
Reserved
Reserved
RO
000_0000
Note:
6. RW = Read/Write.
RO = Read only.
SC = Self-cleared.
LH = Latch high.
LL = Latch low.
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KSZ8091RNA/KSZ8091RND
IEEE-Defined Registers – Descriptions (Continued)
Address
Name
(6)
Description
Mode
Default
Register 1h – Basic Status
1.15
100Base-T4
1 = T4 capable
0 = Not T4 capable
RO
0
1.14
100Base-TX
Full-Duplex
1 = Capable of 100Mbps full-duplex
0 = Not capable of 100Mbps full-duplex
RO
1
1.13
100Base-TX
Half-Duplex
1 = Capable of 100Mbps half-duplex
0 = Not capable of 100Mbps half-duplex
RO
1
1.12
10Base-T
Full-Duplex
1 = Capable of 10Mbps full-duplex
0 = Not capable of 10Mbps full-duplex
RO
1
1.11
10Base-T
Half-Duplex
1 = Capable of 10Mbps half-duplex
0 = Not capable of 10Mbps half-duplex
RO
1
1.10:7
Reserved
Reserved
RO
000_0
1.6
No Preamble
1 = Preamble suppression
0 = Normal preamble
RO
1
1.5
AutoNegotiation
Complete
1 = Auto-Negotiation process completed
0 = Auto-Negotiation process not completed
RO
0
1.4
Remote Fault
1 = Remote fault
0 = No remote fault
RO/LH
0
1.3
AutoNegotiation
Ability
1 = Can perform Auto-Negotiation
0 = Cannot perform Auto-Negotiation
RO
1
1.2
Link Status
1 = Link is up
0 = Link is down
RO/LL
0
1.1
Jabber Detect
1 = Jabber detected
0 = Jabber not detected (default is low)
RO/LH
0
1.0
Extended
Capability
1 = Supports extended capability registers
RO
1
Assigned to the 3rd through 18th bits of the
Organizationally Unique Identifier (OUI).
KENDIN Communication’s OUI is 0010A1
(hex).
RO
0022h
3.15:10
PHY ID
Number
Assigned to the 19th through 24th bits of the
Organizationally Unique Identifier (OUI).
KENDIN Communication’s OUI is 0010A1
(hex).
RO
0001_01
3.9:4
Model Number
Six-bit manufacturer’s model number
RO
01_0110
3.3:0
Revision
Number
Four-bit manufacturer’s revision number
RO
Indicates silicon revision
Register 2h – PHY Identifier 1
2.15:0
PHY ID
Number
Register 3h – PHY Identifier 2
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KSZ8091RNA/KSZ8091RND
IEEE-Defined Registers – Descriptions (Continued)
Address
Name
(6)
Description
Mode
Default
Register 4h – Auto-Negotiation Advertisement
4.15
Next Page
1 = Next page capable
0 = No next page capability
RW
0
4.14
Reserved
Reserved
RO
0
4.13
Remote Fault
1 = Remote fault supported
0 = No remote fault
RW
0
4.12
Reserved
Reserved
RO
0
4.11:10
Pause
[00] = No pause
[10] = Asymmetric pause
[01] = Symmetric pause
[11] = Asymmetric and symmetric pause
RW
00
4.9
100Base-T4
1 = T4 capable
0 = No T4 capability
RO
0
4.8
100Base-TX
Full-Duplex
1 = 100Mbps full-duplex capable
0 = No 100Mbps full-duplex capability
RW
Set by the ANEN_SPEED
strapping pin.
See the Strapping Options section
for details.
4.7
100Base-TX
Half-Duplex
1 = 100Mbps half-duplex capable
0 = No 100Mbps half-duplex capability
RW
Set by the ANEN_SPEED
strapping pin.
See the Strapping Options section
for details.
4.6
10Base-T
Full-Duplex
1 = 10Mbps full-duplex capable
0 = No 10Mbps full-duplex capability
RW
1
4.5
10Base-T
Half-Duplex
1 = 10Mbps half-duplex capable
0 = No 10Mbps half-duplex capability
RW
1
4.4:0
Selector Field
[00001] = IEEE 802.3
RW
0_0001
Register 5h – Auto-Negotiation Link Partner Ability
5.15
Next Page
1 = Next page capable
0 = No next page capability
RO
0
5.14
Acknowledge
1 = Link code word received from partner
0 = Link code word not yet received
RO
0
5.13
Remote Fault
1 = Remote fault detected
0 = No remote fault
RO
0
5.12
Reserved
Reserved
RO
0
5.11:10
Pause
[00] = No pause
[10] = Asymmetric pause
[01] = Symmetric pause
[11] = Asymmetric and symmetric pause
RO
00
5.9
100Base-T4
1 = T4 capable
0 = No T4 capability
RO
0
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KSZ8091RNA/KSZ8091RND
IEEE-Defined Registers – Descriptions (Continued)
(6)
Address
Name
Description
Mode
5.8
100Base-TX
Full-Duplex
1 = 100Mbps full-duplex capable
0 = No 100Mbps full-duplex capability
RO
0
5.7
100Base-TX
Half-Duplex
1 = 100Mbps half-duplex capable
0 = No 100Mbps half-duplex capability
RO
0
5.6
10Base-T
Full-Duplex
1 = 10Mbps full-duplex capable
0 = No 10Mbps full-duplex capability
RO
0
5.5
10Base-T
Half-Duplex
1 = 10Mbps half-duplex capable
0 = No 10Mbps half-duplex capability
RO
0
5.4:0
Selector Field
[00001] = IEEE 802.3
RO
0_0001
Default
Register 6h – Auto-Negotiation Expansion
6.15:5
Reserved
Reserved
RO
0000_0000_000
6.4
Parallel
Detection Fault
1 = Fault detected by parallel detection
0 = No fault detected by parallel detection
RO/LH
0
6.3
Link Partner
Next Page
Able
1 = Link partner has next page capability
0 = Link partner does not have next page
capability
RO
0
6.2
Next Page
Able
1 = Local device has next page capability
0 = Local device does not have next page
capability
RO
1
6.1
Page Received
1 = New page received
0 = New page not received yet
RO/LH
0
6.0
Link Partner
AutoNegotiation
Able
1 = Link partner has Auto-Negotiation capability
0 = Link partner does not have AutoNegotiation capability
RO
0
Register 7h – Auto-Negotiation Next Page
7.15
Next Page
1 = Additional next pages will follow
0 = Last page
RW
0
7.14
Reserved
Reserved
RO
0
7.13
Message Page
1 = Message page
0 = Unformatted page
RW
1
7.12
Acknowledge2
1 = Will comply with message
0 = Cannot comply with message
RW
0
7.11
Toggle
1 = Previous value of transmitted link code
word equal to logic 0
0 = Previous value of transmitted link code
word equal to logic 1
RO
0
7.10:0
Message Field
11-bit wide field to encode 2048 messages
RW
000_0000_0001
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KSZ8091RNA/KSZ8091RND
IEEE-Defined Registers – Descriptions (Continued)
Address
Name
Description
Mode
(6)
Default
Register 8h – Auto-Negotiation Link Partner Next Page Ability
8.15
Next Page
1 = Additional next pages will follow
0 = Last page
RO
0
8.14
Acknowledge
1 = Successful receipt of link word
0 = No successful receipt of link word
RO
0
8.13
Message Page
1 = Message page
0 = Unformatted page
RO
0
8.12
Acknowledge2
1 = Can act on the information
0 = Cannot act on the information
RO
0
8.11
Toggle
1 = Previous value of transmitted link code
word equal to logic 0
0 = Previous value of transmitted link code
word equal to logic 1
RO
0
8.10:0
Message Field
11-bit wide field to encode 2048 messages
RO
000_0000_0000
RW
00
Register Dh – MMD Access – Control
D.15:14
MMD –
Operation
Mode
For the selected MMD Device Address (Bits
[4:0] of this register), these two bits select one
of the following register or data operations and
the usage for MMD Access – Register/Data
(Reg. Eh).
00 = Register
01 = Data, no post increment
10 = Data, post increment on reads and writes
11 = Data, post increment on writes only
D.13:5
Reserved
Reserved
RW
00_0000_000
D.4:0
MMD –
Device
Address
These five bits set the MMD device address.
RW
0_0000
RW
0000_0000_0000_0000
Register Eh – MMD Access – Register/Data
E.15:0
August 31, 2015
MMD –
Register/Data
For the selected MMD Device Address (Reg.
Dh, Bits [4:0]),
When Reg. Dh, Bits [15:14] = 00, this register
contains the read/write register address for the
MMD Device Address.
Otherwise, this register contains the read/write
data value for the MMD Device Address and its
selected register address.
See also Reg. Dh, Bits [15:14], for descriptions
of post increment reads and writes of this
register for data operation.
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KSZ8091RNA/KSZ8091RND
Vendor-Specific Registers – Descriptions
Address
Name
Description
Mode
(7)
Default
Register 10h – Digital Reserved Control
10.15:5
Reserved
Reserved
RW
0000_0000_000
10.4
PLL Off
1 = Turn PLL off automatically in EDPD mode
0 = Keep PLL on in EDPD mode.
See also Register 18h, Bit [11] for EDPD mode
RW
0
10.3:0
Reserved
Reserved
RW
0000
Reserved
Reserved
RW
0000_0000_00
11.5
Slow-Oscillator
Mode Enable
Slow-oscillator mode is used to disconnect the
input reference crystal/clock on the XI pin and
select the on-chip slow oscillator when the
KSZ8091RNA/RND device is not in use after
power-up.
1 = Enable
0 = Disable
This bit automatically sets software power-down
to the analog side when enabled.
RW
0
11.4:0
Reserved
Reserved
RW
0_0000
Reserved
Reserved
RW
0000_0000_000
13.4
10Base-Te
Mode
1 = EEE 10Base-Te (1.75V TX amplitude) and
also set MMD Address 1Ch, Register 4h, Bit
[13] to ‘0’.
0 = Standard 10Base-T (2.5V TX amplitude)
and also set MMD Address 1Ch, Register 4h,
Bit [13] to ‘1’.
RW
0
13.3:0
Reserved
Reserved
RW
0000
Receive error counter for symbol error frames
RO/SC
0000h
RW
Set by the PME_EN strapping pin.
See the Strapping Options section
for details.
Register 11h – AFE Control 1
11.15:6
Register 13h – AFE Control 4
13.15:5
Register 15h – RXER Counter
15.15:0
RXER Counter
Register 16h – Operation Mode Strap Override
16.15
PME Enable
PME for Wake-On-LAN
1 = Enable
0 = Disable
This bit works in conjunction with MMD Address
1Fh, Reg. 0h, Bits [15:14] to define the output
for Pins 18 and 23.
16.14:11
Reserved
Reserved
RW
000_0
16.10
Reserved
Reserved
RO
0
16.9
B-CAST_OFF
Override
1 = Override to disable broadcast (default
setting) for PHY Address 0
If bit is ‘1’, PHY Address 0 is non-broadcast.
RW
0
16.8:7
Reserved
Reserved
RW
0_0
Note:
7. RW = Read/Write.
RO = Read only.
SC = Self-cleared.
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KSZ8091RNA/KSZ8091RND
Vendor-Specific Registers – Descriptions (Continued)
(7)
Address
Name
Description
Mode
Default
16.6
RMII B-to-B
Override
1 = Override to enable RMII Back-to-Back
mode (also set Bit 1 of this register to ‘1’)
RW
0
16.5
NAND Tree
Override
1 = Override to enable NAND Tree mode
RW
0
16.4:2
Reserved
Reserved
RW
0_00
16.1
RMII Override
1 = Override to enable RMII mode
RW
1
16.0
Reserved
Reserved
RW
0
Register 17h – Operation Mode Strap Status
17.15
Reserved
Reserved
17.14:13
PHYAD[1:0]
Strap-In Status
[00] = Strap to PHY Address 00000b (0h)
[11] = Strap to PHY Address 00011b (3h)
The KSZ8091RNA/RND supports PHY
addresses 0h and 3h only.
RO
RO
17.12:2
Reserved
Reserved
RO
17.1
RMII Strap-In
Status
1 = Strap to RMII mode
RO
17.0
Reserved
Reserved
RO
Set by the PHYAD[1:0] strapping
pin.
See the Strapping Options section
for details.
Register 18h – Expanded Control
18.15:12
Reserved
Reserved
RW
0000
18.11
EDPD
Disabled
Energy-detect power-down mode
1 = Disable
0 = Enable
See also Register 10h, Bit [4] for PLL off.
RW
1
18.10:0
Reserved
Reserved
RW
000_0000_0001
Register 1Bh – Interrupt Control/Status
1B.15
Jabber
Interrupt
Enable
1 = Enable jabber interrupt
0 = Disable jabber interrupt
RW
0
1B.14
Receive Error
Interrupt
Enable
1 = Enable receive error interrupt
0 = Disable receive error interrupt
RW
0
1B.13
Page Received
Interrupt
Enable
1 = Enable page received interrupt
0 = Disable page received interrupt
RW
0
1B.12
Parallel Detect
Fault Interrupt
Enable
1 = Enable parallel detect fault interrupt
0 = Disable parallel detect fault interrupt
RW
0
1B.11
Link Partner
Acknowledge
Interrupt
Enable
1 = Enable link partner acknowledge interrupt
0 = Disable link partner acknowledge interrupt
RW
0
1B.10
Link-Down
Interrupt
Enable
1= Enable link-down interrupt
0 = Disable link-down interrupt
RW
0
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KSZ8091RNA/KSZ8091RND
Vendor-Specific Registers – Descriptions (Continued)
(7)
Address
Name
Description
Mode
Default
1B.9
Remote Fault
Interrupt
Enable
1 = Enable remote fault interrupt
0 = Disable remote fault interrupt
RW
0
1B.8
Link-Up
Interrupt
Enable
1 = Enable link-up interrupt
0 = Disable link-up interrupt
RW
0
1B.7
Jabber
Interrupt
1 = Jabber occurred
0 = Jabber did not occur
RO/SC
0
1B.6
Receive Error
Interrupt
1 = Receive error occurred
0 = Receive error did not occur
RO/SC
0
1B.5
Page Receive
Interrupt
1 = Page receive occurred
0 = Page receive did not occur
RO/SC
0
1B.4
Parallel Detect
Fault Interrupt
1 = Parallel detect fault occurred
0 = Parallel detect fault did not occur
RO/SC
0
1B.3
Link Partner
Acknowledge
Interrupt
1 = Link partner acknowledge occurred
0 = Link partner acknowledge did not occur
RO/SC
0
1B.2
Link-Down
Interrupt
1 = Link-down occurred
0 = Link-down did not occur
RO/SC
0
1B.1
Remote Fault
Interrupt
1 = Remote fault occurred
0 = Remote fault did not occur
RO/SC
0
1B.0
Link-Up
Interrupt
1 = Link-up occurred
0 = Link-up did not occur
RO/SC
0
Register 1Dh – LinkMD Cable Diagnostic
Cable
Diagnostic
Test Enable
1 = Enable cable diagnostic test. After test has
completed, this bit is self-cleared.
0 = Indicates cable diagnostic test (if enabled)
has completed and the status information is
valid for read.
RW/SC
0
1D.14:13
Cable
Diagnostic
Test Result
[00] = Normal condition
[01] = Open condition has been detected in
cable
[10] = Short condition has been detected in
cable
[11] = Cable diagnostic test has failed
RO
00
1D.12
Short Cable
Short Indicator
1 = A short cable (<10 meter) short condition
has been detected by LinkMD
RO
0
1D.11:9
Reserved
Reserved
RW
000
1D.8:0
Cable Fault
Counter
Distance to fault
RO
0_0000_0000
1D.15
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Micrel, Inc.
KSZ8091RNA/KSZ8091RND
Vendor-Specific Registers – Descriptions (Continued)
Address
Name
Description
Mode
(7)
Default
Register 1Eh – PHY Control 1
1E.15:10
Reserved
Reserved
RO
0000_00
1E.9
Enable Pause
(Flow Control)
1 = Flow control capable
0 = No flow control capability
RO
0
1E.8
Link Status
1 = Link is up
0 = Link is down
RO
0
1E.7
Polarity Status
1 = Polarity is reversed
0 = Polarity is not reversed
RO
1E.6
Reserved
Reserved
RO
1E.5
MDI/MDI-X
State
1 = MDI-X
0 = MDI
RO
1E.4
Energy Detect
1 = Signal present on receive differential pair
0=
No signal detected on receive
differential pair
RO
0
1E.3
PHY Isolate
1 = PHY in isolate mode
0 = PHY in normal operation
RW
0
Operation
Mode
Indication
[000] = Still in Auto-Negotiation
[001] = 10Base-T half-duplex
[010] = 100Base-TX half-duplex
[011] = Reserved
[100] = Reserved
[101] = 10Base-T full-duplex
[110] = 100Base-TX full-duplex
[111] = Reserved
RO
000
HP_MDIX
1 = HP Auto MDI/MDI-X mode
0 = Micrel Auto MDI/MDI-X mode
RW
1
1F.14
MDI/MDI-X
Select
When Auto MDI/MDI-X is disabled,
1 = MDI-X mode
Transmit on RXP,RXM (pins 4, 3) and Receive
on TXP,TXM (pins 6, 5)
0 = MDI mode
Transmit on TXP,TXM (pins 6, 5) and Receive
on RXP,RXM (pins 4, 3)
RW
0
1F.13
Pair Swap
Disable
1 = Disable Auto MDI/MDI-X
0 = Enable Auto MDI/MDI-X
RW
0
1F.12
Reserved
Reserved
RW
0
1E.2:0
0
Register 1Fh – PHY Control 2
1F.15
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KSZ8091RNA/KSZ8091RND
Vendor-Specific Registers – Descriptions (Continued)
Address
(7)
Name
Description
Mode
1F.11
Force Link
1 = Force link pass
0 = Normal link operation
This bit bypasses the control logic and allows
the transmitter to send a pattern even if there is
no link.
RW
0
1F.10
Power Saving
1 = Enable power saving
0 = Disable power saving
RW
0
1F.9
Interrupt Level
1 = Interrupt pin active high
0 = Interrupt pin active low
RW
0
1F.8
Enable Jabber
1 = Enable jabber counter
0 = Disable jabber counter
RW
1
RW
0
1F.7
1F.6
RMII
Reference
Clock Select
Default
1 = For KSZ8091RNA, clock input to XI (Pin 8)
is 50MHz for RMII – 50MHz Clock Mode.
For KSZ8091RND, clock input to XI (Pin 8) is
25MHz for RMII – 25MHz Clock Mode.
0 = For KSZ8091RNA, clock input to XI (Pin 8)
is 25MHz for RMII – 25MHz Clock Mode.
For KSZ8091RND, clock input to XI (Pin 8) is
50MHz for RMII – 50MHz Clock Mode.
Reserved
Reserved
RW
0
1F.5:4
LED Mode
[00] = LED0: Link/Activity
[01] = LED0: Link
[10], [11] = Reserved
RW
00
1F.3
Disable
Transmitter
1 = Disable transmitter
0 = Enable transmitter
RW
0
1F.2
Remote
Loopback
1 = Remote (analog) loopback is enabled
0 = Normal mode
RW
0
1F.1
Reserved
Reserved
RW
0
1F.0
Disable Data
Scrambling
1 = Disable scrambler
0 = Enable scrambler
RW
0
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KSZ8091RNA/KSZ8091RND
MMD Registers
MMD registers provide indirect read/write access to up to 32 MMD Device Addresses with each device supporting up to
65,536 16-bit registers, as defined in Clause 22 of the IEEE 802.3 Specification. The KSZ8091RNA/RND, however, uses
only a small fraction of the available registers. See the Register Map section for a list of supported MMD device addresses
and their associated register addresses.
The following two standard registers serve as the portal registers to access the indirect MMD registers.
•
Standard Register Dh – MMD Access – Control
•
Standard Register Eh – MMD Access – Register/Data
Table 12. Portal Registers (Access to Indirect MMD Registers)
Address
Name
Description
Mode
Default
RW
00
Register Dh – MMD Access – Control
D.15:14
MMD –
Operation
Mode
For the selected MMD Device Address (Bits
[4:0] of this register), these two bits select one
of the following register or data operations and
the usage for MMD Access – Register/Data
(Reg. Eh).
00 = Register
01 = Data, no post increment
10 = Data, post increment on reads and writes
11 = Data, post increment on writes only
D.13:5
Reserved
Reserved
RW
00_0000_000
D.4:0
MMD –
Device
Address
These five bits set the MMD device address.
RW
0_0000
RW
0000_0000_0000_0000
Register Eh – MMD Access – Register/Data
E.15:0
August 31, 2015
MMD –
Register/Data
For the selected MMD Device Address (Reg.
Dh, Bits [4:0]),
When Reg. Dh, Bits [15:14] = 00, this register
contains the read/write register address for
the MMD Device Address.
Otherwise, this register contains the
read/write data value for the MMD Device
Address and its selected register address.
See also Register Dh, Bits [15:14] descriptions
for post increment reads and writes of this
register for data operation.
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Micrel, Inc.
KSZ8091RNA/KSZ8091RND
Examples:
MMD Register Write
Write MMD – Device Address 1Fh, Register 0h = 0001h to enable link-up detection to trigger PME for WoL.
1. Write Register Dh with 001Fh
// Set up register address for MMD – Device Address 1Fh.
2. Write Register Eh with 0000h
// Select Register 0h of MMD – Device Address 1Fh.
3. Write Register Dh with 401Fh
// Select register data for MMD – Device Address 1Fh, Register 0h.
4. Write Register Eh with 0001h
// Write value 0001h to MMD – Device Address 1Fh, Register 0h.
MMD Register Read
Read MMD – Device Address 1Fh, Register 19h – 1Bh for the magic packet’s MAC address
1. Write Register Dh with 001Fh
// Set up register address for MMD – Device Address 1Fh.
2. Write Register Eh with 0019h
// Select Register 19h of MMD – Device Address 1Fh.
3. Write Register Dh with 801Fh
// Select register data for MMD – Device Address 1Fh, Register 19h
// with post increments
4. Read Register Eh
// Read data in MMD – Device Address 1Fh, Register 19h.
5. Read Register Eh
// Read data in MMD – Device Address 1Fh, Register 1Ah.
6. Read Register Eh
// Read data in MMD – Device Address 1Fh, Register 1Bh.
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Revision 1.2
Micrel, Inc.
KSZ8091RNA/KSZ8091RND
MMD Registers – Descriptions
Address
Name
Description
Mode
(8)
Default
MMD Address 1h, Register 0h – PMA/PMD Control 1
1.0.15:13
Reserved
Reserved
RW
000
1.0.12
LPI enable
Lower Power Idle enable
RW
0
1.0.11:0
Reserved
Reserved
RW
0000_0000_0000
MMD Address 1h, Register 1h – PMA/PMD Status 1
1.1.15:9
Reserved
Reserved
RO
0000_000
1.1.8
LPI State
Entered
1 = PMA/PMD has entered LPI state
0 = PMA/PMD has not entered LPI state
RO/LH
0
1.1.7:4
Reserved
Reserved
RO
0000
1.1.3
LPI State
Indication
1 = PMA/PMD is currently in LPI state
0 = PMA/PMD is currently not in LPI state
RO
0
1.1.2:0
Reserved
Reserved
RO
000
MMD Address 7h, Register 3Ch – EEE Advertisement
7.3C.15:3
Reserved
Reserved
RO
0000_0000_0000_0
7.3C.2
1000Base-T
EEE Capable
0 = 1000Mbps EEE is not supported
RO
0
7.3C.1
100Base-TX
EEE Capable
1 = 100Mbps EEE capable
0 = No 100Mbps EEE capability
This bit is set to ‘0’ as the default after power-up
or reset. Set this bit to ‘1’ to enable 100Mbps
EEE mode.
RW
0
7.3C.0
Reserved
Reserved
RO
0
MMD Address 7h, Register 3Dh – EEE Link Partner Advertisement
7.3D.15:3
Reserved
Reserved
RO
0000_0000_0000_0
7.3D.2
1000Base-T
EEE Capable
1 = 1000Mbps EEE capable
0 = No 1000Mbps EEE capability
RO
0
7.3D.1
100Base-TX
EEE Capable
1 = 100Mbps EEE capable
0 = No 100Mbps EEE capability
RO
0
7.3D.0
Reserved
Reserved
RO
0
MMD Address 1Ch, Register 4h – DSP 10Base-T/10Base-Te Control
1C.4.15
Reserved
Reserved
RW
0
1C.4.14
Reserved
Reserved
RO
0
1C.4.13
DSP 10BaseT/10Base-Te
Mode Select
1 = Standard 10Base-T (2.5V TX amplitude)
and also set Standard Register 13h, Bit [4] to
‘0’.
0 = EEE 10Base-Te (1.75V TX amplitude) and
also set Standard Register 13h, Bit [4] to ‘1’.
RW
1
1C.4.12
Reserved
Reserved
RW
0
1C.4.11:0
Reserved
Reserved
RO
0000_0000_0000
Note:
8. RW = Read/Write.
RO = Read only.
LH = Latch high.
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Revision 1.2
Micrel, Inc.
KSZ8091RNA/KSZ8091RND
MMD Registers – Descriptions (Continued)
Address
Name
Description
Mode
(8)
Default
MMD Address 1Fh, Register 0h – Wake-On-LAN – Control
1F.0.15:14
PME Output
Select
These two bits work in conjunction with Reg.
16h, Bit [15] for PME enable to define the
output for Pins 18 and 23.
INTRP/PME_N2 (Pin 18)
00 = INTRP output
01 = PME_N2 output
10 = INTRP and PME_N2 output
11 = Reserved
LED0/PME_N1 (Pin 23)
00 = PME_N1 output
01 = LED0 output
10 = LED0 output
11 = PME_N1 output
1F.0.13:7
Reserved
Reserved
RO
00_0000_0
1F.0.6
Magic Packet
Detect Enable
1 = Enable magic-packet detection
0 = Disable magic-packet detection
RW
0
1F.0.5
CustomPacket Type 3
Detect Enable
1 = Enable custom-packet, Type 3 detection
0 = Disable custom-packet, Type 3 detection
RW
0
1F.0.4
CustomPacket Type 2
Detect Enable
1 = Enable custom-packet, Type 2 detection
0 = Disable custom-packet, Type 2 detection
RW
0
1F.0.3
CustomPacket Type 1
Detect Enable
1 = Enable custom-packet, Type 1 detection
0 = Disable custom-packet, Type 1 detection
RW
0
1F.0.2
CustomPacket Type 0
Detect Enable
1 = Enable custom-packet, Type 0 detection
0 = Disable custom-packet, Type 0 detection
RW
0
1F.0.1
Link-Down
Detect Enable
1 = Enable link-down detection
0 = Disable link-down detection
RW
0
1F.0.0
Link-Up Detect
Enable
1 = Enable link-up detection
0 = Disable link-up detection
RW
0
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51
RW
00
Revision 1.2
Micrel, Inc.
KSZ8091RNA/KSZ8091RND
MMD Registers – Descriptions (Continued)
Address
Name
Description
Mode
(8)
Default
MMD Address 1Fh, Register 1h – Wake-On-LAN – Customized Packet, Type 0, Mask 0
MMD Address 1Fh, Register 7h – Wake-On-LAN – Customized Packet, Type 1, Mask 0
MMD Address 1Fh, Register Dh – Wake-On-LAN – Customized Packet, Type 2, Mask 0
MMD Address 1Fh, Register 13h – Wake-On-LAN – Customized Packet, Type 3, Mask 0
1F.1.15:0
1F.7.15:0
1F.D.15:0
1F.13.15:0
Custom Packet
Type X Mask 0
This register selects the bytes in the first 16
bytes of the packet (bytes 1 thru 16) that will be
used for CRC calculation.
For each bit in this register,
1 = Byte is selected for CRC calculation
0 = Byte is not selected for CRC calculation
The register-bit to packet-byte mapping is as
follows:
Bit [15] :
byte-16
…
:
…
Bit [1] :
byte-2
Bit [0] :
byte-1
RW
0000_0000_0000_0000
MMD Address 1Fh, Register 2h – Wake-On-LAN – Customized Packet, Type 0, Mask 1
MMD Address 1Fh, Register 8h – Wake-On-LAN – Customized Packet, Type 1, Mask 1
MMD Address 1Fh, Register Eh – Wake-On-LAN – Customized Packet, Type 2, Mask 1
MMD Address 1Fh, Register 14h – Wake-On-LAN – Customized Packet, Type 3, Mask 1
1F.2.15:0
1F.8.15:0
1F.E.15:0
1F.14.15:0
August 31, 2015
Custom Packet
Type X
Mask 1
This register selects the bytes in the second 16
bytes of the packet (bytes 17 thru 32) that will
be used for CRC calculation.
For each bit in this register,
1 = Byte is selected for CRC calculation
0 = Byte is not selected for CRC calculation
The register-bit to packet-byte mapping is as
follows:
Bit [15] :
byte-32
…
:
…
Bit [1] :
byte-18
Bit [0] :
byte-17
52
RW
0000_0000_0000_0000
Revision 1.2
Micrel, Inc.
KSZ8091RNA/KSZ8091RND
MMD Registers – Descriptions (Continued)
Address
Name
Description
Mode
(8 )
Default
MMD Address 1Fh, Register 3h – Wake-On-LAN – Customized Packet, Type 0, Mask 2
MMD Address 1Fh, Register 9h – Wake-On-LAN – Customized Packet, Type 1, Mask 2
MMD Address 1Fh, Register Fh – Wake-On-LAN – Customized Packet, Type 2, Mask 2
MMD Address 1Fh, Register 15h – Wake-On-LAN – Customized Packet, Type 3, Mask 2
1F.3.15:0
1F.9.15:0
1F.F.15:0
1F.15.15:0
Custom Packet
Type X
Mask 2
This register selects the bytes in the third 16
bytes of the packet (bytes 33 thru 48) that will
be used for CRC calculation.
For each bit in this register,
1 = Byte is selected for CRC calculation
0 = Byte is not selected for CRC calculation
The register-bit to packet-byte mapping is as
follows:
Bit [15] :
byte-48
…
:
…
Bit [1] :
byte-34
Bit [0] :
byte-33
RW
0000_0000_0000_0000
MMD Address 1Fh, Register 4h – Wake-On-LAN – Customized Packet, Type 0, Mask 3
MMD Address 1Fh, Register Ah – Wake-On-LAN – Customized Packet, Type 1, Mask 3
MMD Address 1Fh, Register 10h – Wake-On-LAN – Customized Packet, Type 2, Mask 3
MMD Address 1Fh, Register 16h – Wake-On-LAN – Customized Packet, Type 3, Mask 3
1F.4.15:0
1F.A.15:0
1F.10.15:0
1F.16.15:0
Custom Packet
Type X
Mask 3
This register selects the bytes in the fourth 16
bytes of the packet (bytes 49 thru 64) that will
be used for CRC calculation.
For each bit in this register,
1 = Byte is selected for CRC calculation
0 = Byte is not selected for CRC calculation
The register-bit to packet-byte mapping is as
follows:
Bit [15] :
byte-64
…
:
…
Bit [1] :
byte-50
Bit [0] :
byte-49
RW
0000_0000_0000_0000
MMD Address 1Fh, Register 5h – Wake-On-LAN – Customized Packet, Type 0, Expected CRC 0
MMD Address 1Fh, Register Bh – Wake-On-LAN – Customized Packet, Type 1, Expected CRC 0
MMD Address 1Fh, Register 11h – Wake-On-LAN – Customized Packet, Type 2, Expected CRC 0
MMD Address 1Fh, Register 17h – Wake-On-LAN – Customized Packet, Type 3, Expected CRC 0
1F.5.15:0
1F.B.15:0
1F.11.15:0
1F.17.15:0
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Custom Packet
Type X CRC 0
This register stores the lower two bytes for the
expected CRC.
Bit [15:8] = Byte 2 (CRC [15:8])
Bit [7:0] = Byte 1 (CRC [7:0])
The upper two bytes for the expected CRC are
stored in the following register.
53
RW
0000_0000_0000_0000
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KSZ8091RNA/KSZ8091RND
MMD Registers – Descriptions (Continued)
Address
Name
Description
Mode
(8)
Default
MMD Address 1Fh, Register 6h – Wake-On-LAN – Customized Packet, Type 0, Expected CRC 1
MMD Address 1Fh, Register Ch – Wake-On-LAN – Customized Packet, Type 1, Expected CRC 1
MMD Address 1Fh, Register 12h – Wake-On-LAN – Customized Packet, Type 2, Expected CRC 1
MMD Address 1Fh, Register 18h – Wake-On-LAN – Customized Packet, Type 3, Expected CRC 1
1F.6.15:0
1F.C.15:0
1F.12.15:0
1F.18.15:0
Custom Packet
Type X
CRC 1
This register stores the upper two bytes for the
expected CRC.
Bit [15:8] = Byte 4 (CRC [31:24])
Bit [7:0] = Byte 3 (CRC [23:16])
The lower two bytes for the expected CRC are
stored in the previous register.
RW
0000_0000_0000_0000
RW
0000_0000_0000_0000
RW
0000_0000_0000_0000
RW
0000_0000_0000_0000
MMD Address 1Fh, Register 19h – Wake-On-LAN – Magic Packet, MAC-DA-0
1F.19.15:0
Magic Packet
MAC-DA-0
This register stores the lower two bytes of the
destination MAC address for the magic packet.
Bit [15:8] = Byte 2 (MAC Address [15:8])
Bit [7:0] = Byte 1 (MAC Address [7:0])
The upper four bytes of the destination MAC
address are stored in the following two
registers.
MMD Address 1Fh, Register 1Ah – Wake-On-LAN – Magic Packet, MAC-DA-1
1F.1A.15:0
Magic Packet
MAC-DA-1
This register stores the middle two bytes of the
destination MAC address for the magic packet.
Bit [15:8] = Byte 4 (MAC Address [31:24])
Bit [7:0] = Byte 3 (MAC Address [23:16])
The lower two bytes and upper two bytes of the
destination MAC address are stored in the
previous and following registers, respectively.
MMD Address 1Fh, Register 1Bh – Wake-On-LAN – Magic Packet, MAC-DA-2
1F.1B.15:0
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Magic Packet
MAC-DA-2
This register stores the upper two bytes of the
destination MAC address for the magic packet.
Bit [15:8] = Byte 6 (MAC Address [47:40])
Bit [7:0] = Byte 5 (MAC Address [39:32])
The lower four bytes of the destination MAC
address are stored in the previous two
registers.
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KSZ8091RNA/KSZ8091RND
Absolute Maximum Ratings(9)
Operating Ratings(10)
Supply Voltage (VIN)
(VDD_1.2) .................................................. –0.5V to +1.8V
(VDDIO, VDDA_3.3) ...................................... –0.5V to +5.0V
Input Voltage (all inputs) .............................. –0.5V to +5.0V
Output Voltage (all outputs) ......................... –0.5V to +5.0V
Lead Temperature (soldering, 10s) ............................ 260°C
Storage Temperature (TS) ......................... –55°C to +150°C
Supply Voltage
(VDDIO_3.3, VDDA_3.3).......................... +3.135V to +3.465V
(VDDIO_2.5)........................................ +2.375V to +2.625V
(VDDIO_1.8)........................................ +1.710V to +1.890V
Ambient Temperature
(TA, Commercial) ...................................... 0°C to +70°C
(TA, Industrial) ....................................... –40°C to +85°C
Maximum Junction Temperature (TJ max.) ................ 125°C
Thermal Resistance (θJA) .................................... 49.22°C/W
Thermal Resistance (θJC) .................................... 25.65°C/W
Electrical Characteristics(11)
Symbol
Parameter
Supply Current (VDDIO, VDDA_3.3 = 3.3V)
Condition
Min.
Typ.
Max.
Units
(12)
IDD1_3.3V
10Base-T
Full-duplex traffic @ 100% utilization
41
mA
IDD2_3.3V
100Base-TX
Full-duplex traffic @ 100% utilization
47
mA
IDD3_3.3V
EEE (100Mbps) Mode
TX and RX paths in LPI state with no traffic
23
mA
IDD4_3.3V
EDPD Mode
Ethernet cable disconnected (Reg. 18h.11 = 0)
20
mA
IDD5_3.3V
Power-Down Mode
Software power-down (Reg. 0h.11 = 1)
4
mA
CMOS Level Inputs
VIH
VIL
|IIN|
Input High Voltage
Input Low Voltage
Input Current
VDDIO = 3.3V
2.0
VDDIO = 2.5V
1.8
VDDIO = 1.8V
1.3
V
VDDIO = 3.3V
0.8
VDDIO = 2.5V
0.7
VDDIO = 1.8V
0.5
VIN = GND ~ VDDIO
10
V
µA
CMOS Level Outputs
VOH
VOL
|Ioz|
Output High Voltage
Output Low Voltage
VDDIO = 3.3V
2.4
VDDIO = 2.5V
2.0
VDDIO = 1.8V
1.5
V
VDDIO = 3.3V
0.4
VDDIO = 2.5V
0.4
VDDIO = 1.8V
0.3
Output Tri-State Leakage
10
V
µA
LED Output
ILED
Output Drive Current
LED0 pin
8
mA
Notes:
9. Exceeding the absolute maximum ratings may damage the device. Stresses greater than the absolute maximum rating can cause permanent
damage to the device. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is
not implied. Maximum conditions for extended periods may affect reliability.
10. The device is not guaranteed to function outside its operating ratings.
11. TA = 25°C. Specification for packaged product only.
12. Current consumption is for the single 3.3V supply KSZ8091RNA/RND device only, and includes the transmit driver current and the 1.2V supply
voltage (VDD_1.2) that are supplied by the KSZ8091RNA/RND
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KSZ8091RNA/KSZ8091RND
Electrical Characteristics(11) (Continued)
Symbol
Parameter
Condition
Min.
Typ.
Max.
VDDIO = 3.3V
30
45
73
VDDIO = 2.5V
39
61
102
VDDIO = 1.8V
48
99
178
VDDIO = 3.3V
26
43
79
VDDIO = 2.5V
34
59
113
VDDIO = 1.8V
53
99
200
Units
All Pull-Up/Pull-Down Pins (including Strapping Pins)
pu
pd
Internal Pull-Up Resistance
Internal Pull-Down Resistance
kΩ
kΩ
100Base-TX Transmit (measured differentially after 1:1 transformer)
VO
Peak Differential Output Voltage
100Ω termination across differential output
VIMB
Output Voltage Imbalance
100Ω termination across differential output
tr , tf
Rise/Fall Time
Rise/Fall Time Imbalance
0.95
1.05
V
2
%
3
5
ns
0
0.5
ns
±0.25
ns
5
%
Duty Cycle Distortion
Overshoot
Output Jitter
Peak-to-peak
0.7
ns
10Base-T Transmit (measured differentially after 1:1 transformer)
VP
tr , tf
Peak Differential Output Voltage
100Ω termination across differential output
Jitter Added
Peak-to-peak
Rise/Fall Time
2.2
2.8
V
3.5
ns
25
ns
5MHz square wave
400
mV
R(ISET) = 6.49kΩ
0.65
V
Peak-to-peak
(Applies only to RMII – 25MHz clock mode)
300
ps
4.4
µs
10Base-T Receive
VSQ
Squelch Threshold
Transmitter – Drive Setting
VSET
Reference Voltage of ISET
REF_CLK Output
50MHz RMII Clock Output Jitter
100Mbps Mode – Industrial Applications Parameters
tllr
Link Loss Reaction (Indication)
Time
August 31, 2015
Link loss detected at receive differential inputs to
PHY signal indication time for each of the
following:
1. For LED mode 01, Link LED output changes
from low (link-up) to high (link-down).
2. INTRP pin asserts for link-down status change.
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KSZ8091RNA/KSZ8091RND
Timing Diagrams
RMII Timing
Figure 13. RMII Timing – Data Received from RMII
Figure 14. RMII Timing – Data Input to RMII
Table 13. RMII Timing Parameters – KSZ8091RNA/RND (25MHz input to XI pin, 50MHz output from REF_CLK pin)
Timing Parameter
Description
Min.
Typ.
Max.
tCYC
Clock cycle
t1
Setup time
4
ns
t2
Hold time
2
ns
tOD
Output delay
7
10
13
ns
Min.
Typ.
Max.
Unit
20
Unit
ns
Table 14. RMII Timing Parameters – KSZ8091RNA/RND (50MHz input to XI pin)
Timing Parameter
Description
tCYC
Clock cycle
t1
Setup time
4
ns
t2
Hold time
2
ns
tOD
Output delay
8
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20
57
11
ns
13
ns
Revision 1.2
Micrel, Inc.
KSZ8091RNA/KSZ8091RND
Auto-Negotiation Timing
Figure 15. Auto-Negotiation Fast Link Pulse (FLP) Timing
Table 15. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters
Timing Parameter
Description
tBTB
FLP burst to FLP burst
tFLPW
FLP burst width
tPW
Clock/Data pulse width
tCTD
Clock pulse to data pulse
55.5
64
69.5
µs
tCTC
Clock pulse to clock pulse
111
128
139
µs
Number of clock/data pulses per FLP burst
17
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58
Min.
Typ.
Max.
Unit
8
16
24
ms
2
ms
100
ns
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KSZ8091RNA/KSZ8091RND
MDC/MDIO Timing
Figure 16. MDC/MDIO Timing
Table 16. MDC/MDIO Timing Parameters
Timing Parameter
Description
fc
Typ.
Max.
Unit
MDC Clock Frequency
2.5
10
MHz
tP
MDC period
400
tMD1
MDIO (PHY input) setup to rising edge of MDC
10
ns
tMD2
MDIO (PHY input) hold from rising edge of MDC
4
ns
tMD3
MDIO (PHY output) delay from rising edge of MDC
5
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Min.
59
222
ns
ns
Revision 1.2
Micrel, Inc.
KSZ8091RNA/KSZ8091RND
Power-Up/Reset Timing
The KSZ8091RNA/RND reset timing requirement is summarized in Figure 17 and Table 17.
Figure 17. Power-Up/Reset Timing
Table 17. Power-Up/Reset Timing Parameters
Timing Parameter
Description
Min.
Typ.
Max.
Unit
tVR
Supply voltage (VDDIO, VDDA_3.3) rise time
300
µs
tSR
Stable supply voltage (VDDIO, VDDA_3.3) to reset high
10
ms
tCS
Configuration setup time
5
ns
tCH
Configuration hold time
5
ns
tRC
Reset to strap-in pin output
6
ns
The supply voltage (VDDIO and VDDA_3.3) power-up waveform should be monotonic. The 300µs minimum rise time is from
10% to 90%.
For warm reset, the reset (RST#) pin should be asserted low for a minimum of 500µs. The strap-in pin values are read
and updated at the de-assertion of reset.
After the de-assertion of reset, wait a minimum of 100µs before starting programming on the MIIM (MDC/MDIO) interface.
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KSZ8091RNA/KSZ8091RND
Reset Circuit
Figure 18 shows a reset circuit recommended for powering up the KSZ8091RNA/RND if reset is triggered by the power
supply.
Figure 18. Recommended Reset Circuit
Figure 19 Shows a reset circuit recommended for applications where reset is driven by another device (for example, the
CPU or an FPGA). The reset out RST_OUT_n from CPU/FPGA provides the warm reset after power up reset. D2 is used
if using different VDDIO between the switch and CPU/FPGA, otherwise, the different VDDIO will fight each other. If
different VDDIO have to use in a special case, a low VF (<0.3V) diode is required (For example, VISHAY’s BAT54,
MSS1P2L and so on), or a level shifter device can be used too. If Ethernet device and CPU/FPGA use same VDDIO
voltage, D2 can be removed to connect both devices directly. Usually, Ethernet device and CPU/FPGA should use same
VDDIO voltage.
Figure 19. Recommended Reset Circuit for Interfacing with CPU/FPGA Reset Output
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KSZ8091RNA/KSZ8091RND
Reference Circuits – LED Strap-In Pin
The pull-up, float, and pull-down reference circuits for the LED0/ANEN_SPEED strapping pin are shown in Figure 20 for
3.3V and 2.5V VDDIO.
Figure 20. Reference Circuits for LED Strapping Pin
For 1.8V VDDIO, LED indication support is not recommended due to the low voltage. Without the LED indicator, the
ANEN_SPEED strapping pin is functional with a 4.7kΩ pull-up to 1.8V VDDIO or float for a value of ‘1’, and with a 1.0kΩ
pull-down to ground for a value of ‘0’.
Note: If using RJ45 jacks with integrated LEDs and 1.8V VDDIO, a level shifting is required from LED 3.3V to 1.8V. For
example, use a bipolar transistor or a level shift device.
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KSZ8091RNA/KSZ8091RND
Reference Clock – Connection and Selection
A crystal or external clock source, such as an oscillator, is used to provide the reference clock for the KSZ8091RNA/RND.
For the KSZ8091RNA/RND in RMII – 25MHz clock mode, the reference clock is 25MHz. The crystal/reference clock
connections to XI (Pin 8) and XO (Pin 7), and the crystal / reference clock selection criteria, are provided in Figure 21 and
Table 18.
Figure 21. 25MHz Crystal/Oscillator Reference Clock Connection
Table 18. 25MHz Crystal/Reference Clock Selection Criteria
Characteristics
Value
Units
Frequency
25
MHz
Frequency tolerance (max.)()
±50
ppm
Crystal series resistance (typ.)
40
Ω
Crystal load capacitance (typ.)
22
pF
Note:
13. ±60ppm for overtemperature crystal.
For the KSZ8091RNA/RND in RMII – 50MHz clock mode, the reference clock is 50MHz. The reference clock connection
to XI (Pin 8) and the reference clock selection criteria are provided in Figure 22 and Table 19.
Figure 22. 50MHz Oscillator/Reference Clock Connection
Table 19. 50MHz Oscillator/Reference Clock Selection Criteria
Characteristics
Value
Units
Frequency
50
MHz
Frequency tolerance (max.)
±50
ppm
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KSZ8091RNA/KSZ8091RND
Magnetic – Connection and Selection
A 1:1 isolation transformer is required at the line interface. Use one with integrated common-mode chokes for designs
exceeding FCC requirements.
The KSZ8091RNA/RND design incorporates voltage-mode transmit drivers and on-chip terminations.
With the voltage-mode implementation, the transmit drivers supply the common-mode voltages to the two differential
pairs. Therefore, the two transformer center tap pins on the KSZ8091RNA/RND side should not be connected to any
power supply source on the board; instead, the center tap pins should be separated from one another and connected
through separate 0.1µF common-mode capacitors to ground. Separation is required because the common-mode voltage
is different between transmitting and receiving differential pairs.
Figure 23 shows the typical magnetic interface circuit for the KSZ8091RNA/RND.
Figure 23. Typical Magnetic Interface Circuit
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KSZ8091RNA/KSZ8091RND
Table 20 lists recommended magnetic characteristics.
Table 20. Magnetics Selection Criteria
Parameter
Value
Test Condition
Turns ratio
1 CT : 1 CT
Open-circuit inductance (min.)
350µH
100mV, 100kHz, 8mA
Insertion loss (typ.)
–1.1dB
100kHz to 100MHz
HIPOT (min.)
1500Vrms
Table 21 is a list of compatible single-port magnetics with separated transformer center tap pins on the PHY chip side that
can be used with the KSZ8091RNA/RND.
Table 21. Compatible Single-Port 10/100 Magnetics
Manufacturer
Part Number
Temperature
Range
Bel Fuse
S558-5999-U7
0°C to 70°C
No
Bel Fuse
SI-46001-F
0°C to 70°C
Yes
Bel Fuse
SI-50170-F
0°C to 70°C
Yes
Delta
LF8505
0°C to 70°C
No
HALO
HFJ11-2450E
0°C to 70°C
Yes
HALO
TG110-E055N5
–40°C to 85°C
No
LANKom
LF-H41S-1
0°C to 70°C
No
Pulse
H1102
0°C to 70°C
No
Pulse
H1260
0°C to 70°C
No
Pulse
HX1188
–40°C to 85°C
No
Pulse
J00-0014
0°C to 70°C
Yes
Pulse
JX0011D21NL
–40°C to 85°C
Yes
TDK
TLA-6T718A
0°C to 70°C
Yes
Transpower
HB726
0°C to 70°C
No
Wurth/Midcom
000-7090-37R-LF1
–40°C to 85°C
No
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Magnetic + RJ-45
Revision 1.2
Micrel, Inc.
KSZ8091RNA/KSZ8091RND
Package Information and Recommended Land Pattern(14)
24-Pin (4mm × 4mm) QFN
Note:
14. Package information is correct as of the publication date. For updates and most current information, go to www.micrel.com.
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KSZ8091RNA/KSZ8091RND
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
Micrel, Inc. is a leading global manufacturer of IC solutions for the worldwide high performance linear and power, LAN, and timing & communications
markets. The Company’s products include advanced mixed-signal, analog & power semiconductors; high-performance communication, clock
management, MEMs-based clock oscillators & crystal-less clock generators, Ethernet switches, and physical layer transceiver ICs. Company
customers include leading manufacturers of enterprise, consumer, industrial, mobile, telecommunications, automotive, and computer products.
Corporation headquarters and state-of-the-art wafer fabrication facilities are located in San Jose, CA, with regional sales and support offices and
advanced technology design centers situated throughout the Americas, Europe, and Asia. Additionally, the Company maintains an extensive network
of distributors and reps worldwide.
Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this datasheet. This
information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry,
specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability
whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties
relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product
can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical
implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A
Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully
indemnify Micrel for any damages resulting from such use or sale.
© 2013 Micrel, Incorporated.
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