MICREL KSZ8041MNLU

KSZ8041NL/RNL
10Base-T/100Base-TX
Physical Layer Transceiver
Data Sheet Rev. 1.4
General Description
The KSZ8041NL is a single supply 10Base-T/100Base-TX
Physical Layer Transceiver, which provides MII/RMII
interfaces to transmit and receive data. A unique mixed
signal design extends signaling distance while reducing
power consumption.
HP Auto MDI/MDI-X provides the most robust solution for
eliminating the need to differentiate between crossover
and straight-through cables.
The KSZ8041NL represents a new level of features and
performance and is an ideal choice of physical layer
transceiver for 10Base-T/100Base-TX applications.
The KSZ8041RNL is an enhanced RMII version of the
KSZ8041NL that does not require a 50MHz system clock.
It uses a 25MHz crystal for its input reference clock and
outputs a 50MHz RMII reference clock to the MAC.
The KSZ8041NL and KSZ8041RNL are available in 32pin, lead-free MLF® (QFN per JDEC) packages (See
Ordering Information).
Data sheets and support documentation can be found on
Micrel’s web site at: www.micrel.com.
Functional Diagram
KSZ8041NL
KSZ8041RNL
MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
September 2010
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Micrel, Inc.
KSZ8041NL/RNL
Features
Applications
• Single-chip 10Base-T/100Base-TX physical layer
solution
• Fully compliant to IEEE 802.3u Standard
• Low power CMOS design, power consumption of
<180mW
• HP auto MDI/MDI-X for reliable detection and
correction for straight-through and crossover cables
with disable and enable option
• Robust operation over standard cables
• Power down and power saving modes
• MII interface support (KSZ8041NL only)
• RMII interface support with external 50MHz system
clock (KSZ8041NL only)
• RMII interface support with 25MHz crystal/clock input
and 50MHz reference clock output to MAC
(KSZ8041RNL only)
• MIIM (MDC/MDIO) management bus to 6.25MHz for
rapid PHY register configuration
• Interrupt pin option
• Programmable LED outputs for link, activity and
speed
• ESD rating (6kV)
• Single power supply (3.3V)
• Built-in 1.8V regulator for core
• Available in 32-pin (5mm x 5mm) MLF® package
•
•
•
•
•
•
Printer
LOM
Game Console
IPTV
IP Phone
IP Set-top Box
Ordering Information
Part Number
Temperature Range
Package
Lead Finish
KSZ8041NL
0°C to 70°C
32-Pin MLF®
Pb-Free
MII / RMII, Commercial Temperature
KSZ8041NLI (1)
−40°C to 85°C
32-Pin MLF®
Pb-Free
MII / RMII, Industrial Temperature
KSZ8041NL AM(1)
−40°C to 85°C
32-Pin MLF®
Pb-Free
MII / RMII, Automotive Qualified Device
KSZ8041MNLU
−40°C to 85°C
32-Pin MLF®
Pb-Free
KSZ8041NL AM with MII support only.
KSZ8041RNLU
−40°C to 85°C
32-Pin MLF®
Pb-Free
KSZ8041NL AM with RMII support only.
0°C to 70°C
32-Pin MLF®
Pb-Free
RMII with 50MHz clock output, Commercial
Temperature
−40°C to 85°C
32-Pin MLF®
Pb-Free
RMII with 50MHz clock output, Industrial
Temperature
KSZ8041RNL
KSZ8041RNLI (1)
Description
Note:
1.
Contact factory for lead time.
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KSZ8041NL/RNL
Revision History
Revision
Date
Summary of Changes
1.0
10/13/06
Data sheet created.
1.1
4/27/07
Added maximum MDC clock speed.
Added 40K +/-30% to note 1 of Pin Description and Strapping Options tables for internal pull-ups/pulldowns.
Changed Model Number in Register 3h – PHY Identifier 2.
Changed polarity (swapped definition) of DUPLEX strapping pin.
Removed DUPLEX strapping pin update to Register 4h – Auto-Negotiation Advertisement bits [8, 6].
Set “Disable power saving” as the default for Register 1Fh bit [10].
Corrected LED1 (pin 31) definition for Activity in LED mode 01.
Added Symbol Error to MII/RMII Receive Error description and Register 15h – RXER Counter.
Added a 100pF capacitor on REXT (pin 10) in Pin Description table.
1.2
7/18/08
Added Automotive Qualified part number to Ordering Information.
Added maximum case temperature.
Added thermal resistance (θJC).
Added chip maximum current consumption.
1.3
12/11/09
Added Automotive Qualified part number, KSZ8041NL EAM, to Ordering Information.
Changed MDIO hold time (min) from 10ns to 4ns.
Added LED drive current.
Renamed Register 3h bits [3:0] to “manufacturer’s revision number” and changed default value to
“Indicates silicon revision.”
Updated RMII output delay for CRSDV and RXD[1:0] output pins.
Added support for Asymmetric PAUSE in register 4h bit [11].
Added control bits for 100Base-TX preamble restore (register 14h bit [7]) and 10Base-T preamble
restore (register 14h bit [6]).
Changed strapping pin definition for CONFIG[2:0] = 100 from “PCS Loopback” to “MII 100Mbps
Preamble Restore.”
Corrected MII timing for tRLAT, tCRS1, tCRS2.
Added KSZ8041RNL device and updated entire data sheet accordingly.
1.4
01/19/10
Removed part number (KSZ8041NL EAM) from Ordering Information.
Removed chip maximum current consumption.
September 2010
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Contents
General Description .............................................................................................................................................................. 1
Functional Diagram............................................................................................................................................................... 1
Features ................................................................................................................................................................................. 2
Applications........................................................................................................................................................................... 2
Ordering Information ............................................................................................................................................................ 2
Revision History.................................................................................................................................................................... 3
List of Figures........................................................................................................................................................................ 7
List of Tables ......................................................................................................................................................................... 8
Pin Configuration – KSZ8041NL .......................................................................................................................................... 9
Pin Description – KSZ8041NL............................................................................................................................................ 10
Pin Description – KSZ8041NL (continued) ....................................................................................................................... 11
Pin Description – KSZ8041NL (continued) ....................................................................................................................... 12
Pin Description – KSZ8041NL (continued) ....................................................................................................................... 13
Strapping Options – KSZ8041NL....................................................................................................................................... 14
Pin Configuration – KSZ8041RNL ..................................................................................................................................... 15
Pin Description – KSZ8041RNL ......................................................................................................................................... 16
Pin Description – KSZ8041RNL (continued) .................................................................................................................... 17
Pin Description – KSZ8041RNL (continued) .................................................................................................................... 18
Strapping Options – KSZ8041RNL .................................................................................................................................... 19
Functional Description ....................................................................................................................................................... 20
100Base-TX Transmit....................................................................................................................................................... 20
100Base-TX Receive........................................................................................................................................................ 20
PLL Clock Synthesizer...................................................................................................................................................... 20
Scrambler/De-scrambler (100Base-TX only).................................................................................................................... 20
10Base-T Transmit ........................................................................................................................................................... 20
10Base-T Receive ............................................................................................................................................................ 21
SQE and Jabber Function (10Base-T only)...................................................................................................................... 21
Auto-Negotiation ............................................................................................................................................................... 21
MII Management (MIIM) Interface .................................................................................................................................... 23
Interrupt (INTRP) .............................................................................................................................................................. 23
MII Data Interface (KSZ8041NL only) .............................................................................................................................. 23
MII Signal Definition (KSZ8041NL only) ........................................................................................................................... 24
Transmit Clock (TXC) ................................................................................................................................................... 24
Transmit Enable (TXEN) .............................................................................................................................................. 24
Transmit Data [3:0] (TXD[3:0]) ..................................................................................................................................... 24
Receive Clock (RXC).................................................................................................................................................... 24
Receive Data Valid (RXDV).......................................................................................................................................... 25
Receive Data [3:0] (RXD[3:0]) ...................................................................................................................................... 25
Receive Error (RXER) .................................................................................................................................................. 25
Carrier Sense (CRS) .................................................................................................................................................... 25
Collision (COL) ............................................................................................................................................................. 25
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Reduced MII (RMII) Data Interface................................................................................................................................... 25
RMII Signal Definition ....................................................................................................................................................... 26
Reference Clock (REF_CLK) ....................................................................................................................................... 26
Transmit Enable (TX_EN) ............................................................................................................................................ 26
Transmit Data [1:0] (TXD[1:0]) ..................................................................................................................................... 26
Carrier Sense/Receive Data Valid (CRS_DV).............................................................................................................. 27
Receive Data [1:0] (RXD[1:0]) ...................................................................................................................................... 27
Receive Error (RX_ER) ................................................................................................................................................ 27
Collision Detection........................................................................................................................................................ 27
RMII Signal Diagram......................................................................................................................................................... 27
HP Auto MDI/MDI-X.......................................................................................................................................................... 28
Straight Cable ............................................................................................................................................................... 29
Crossover Cable........................................................................................................................................................... 29
Power Management.......................................................................................................................................................... 30
Power Saving Mode ..................................................................................................................................................... 30
Power Down Mode ....................................................................................................................................................... 30
Reference Clock Connection Options .............................................................................................................................. 30
Reference Circuit for Power and Ground Connections .................................................................................................... 31
Register Map........................................................................................................................................................................ 32
Register Description ........................................................................................................................................................... 32
Register Description (continued) ...................................................................................................................................... 33
Register Description (continued) ...................................................................................................................................... 34
Register Description (continued) ...................................................................................................................................... 35
Register Description (continued) ...................................................................................................................................... 36
Register Description (continued) ...................................................................................................................................... 37
Register Description (continued) ...................................................................................................................................... 38
Register Description (continued) ...................................................................................................................................... 39
Absolute Maximum Ratings(1) ............................................................................................................................................ 40
Operating Ratings(2) ............................................................................................................................................................ 40
Electrical Characteristics(4) ................................................................................................................................................ 40
Electrical Characteristics(4) (continued)............................................................................................................................ 41
Timing Diagrams ................................................................................................................................................................. 42
MII SQE Timing (10Base-T) ............................................................................................................................................. 42
MII Transmit Timing (10Base-T) ....................................................................................................................................... 43
MII Receive Timing (10Base-T) ........................................................................................................................................ 44
MII Transmit Timing (100Base-TX) .................................................................................................................................. 45
MII Receive Timing (100Base-TX) ................................................................................................................................... 46
RMII Timing....................................................................................................................................................................... 47
Auto-Negotiation Timing ................................................................................................................................................... 48
MDC/MDIO Timing ........................................................................................................................................................... 49
Reset Timing..................................................................................................................................................................... 50
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KSZ8041NL/RNL
Reset Circuit ........................................................................................................................................................................ 51
Reference Circuits for LED Strapping Pins...................................................................................................................... 52
Selection of Isolation Transformer.................................................................................................................................... 53
213H
Selection of Reference Crystal .......................................................................................................................................... 53
87H
214H
Package Information........................................................................................................................................................... 54
8H
215H
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KSZ8041NL/RNL
List of Figures
Figure 1. Auto-Negotiation Flow Chart................................................................................................................................. 22
Figure 2. KSZ8041NL RMII Interface................................................................................................................................... 27
Figure 3. KSZ8041RNL RMII Interface ................................................................................................................................ 28
Figure 4. Typical Straight Cable Connection ....................................................................................................................... 29
Figure 5. Typical Crossover Cable Connection ................................................................................................................... 29
Figure 6. 25MHz Crystal / Oscillator Reference Clock ........................................................................................................ 30
Figure 7. 50MHz Oscillator Reference Clock for KSZ8041NL RMII Mode .......................................................................... 30
Figure 8. KSZ8041NL/RNL Power and Ground Connections.............................................................................................. 31
Figure 9. MII SQE Timing (10Base-T) ................................................................................................................................. 42
Figure 10. MII Transmit Timing (10Base-T) ......................................................................................................................... 43
Figure 11. MII Receive Timing (10Base-T) .......................................................................................................................... 44
Figure 12. MII Transmit Timing (100Base-TX)..................................................................................................................... 45
Figure 13. MII Receive Timing (100Base-TX)...................................................................................................................... 46
Figure 14. RMII Timing – Data Received from RMII ............................................................................................................ 47
Figure 15. RMII Timing – Data Input to RMII ....................................................................................................................... 47
Figure 16. Auto-Negotiation Fast Link Pulse (FLP) Timing ................................................................................................. 48
Figure 17. MDC/MDIO Timing.............................................................................................................................................. 49
Figure 18. Reset Timing....................................................................................................................................................... 50
Figure 19. Recommended Reset Circuit.............................................................................................................................. 51
Figure 20. Recommended Reset Circuit for interfacing with CPU/FPGA Reset Output...................................................... 51
Figure 21. Reference Circuits for LED Strapping Pins......................................................................................................... 52
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List of Tables
Table 1. MII Management Frame Format ............................................................................................................................ 23
Table 2. MII Signal Definition ............................................................................................................................................... 24
Table 3. RMII Signal Description – KSZ8041NL.................................................................................................................. 26
Table 4. RMII Signal Description – KSZ8041RNL ............................................................................................................... 26
Table 5. MDI/MDI-X Pin Definition ....................................................................................................................................... 28
Table 6. KSZ8041NL/RNL Power Pin Description............................................................................................................... 31
Table 7. MII SQE Timing (10Base-T) Parameters ............................................................................................................... 42
Table 8. MII Transmit Timing (10Base-T) Parameters ........................................................................................................ 43
Table 9. MII Receive Timing (10Base-T) Parameters ......................................................................................................... 44
Table 10. MII Transmit Timing (100Base-TX) Parameters .................................................................................................. 45
Table 11. MII Receive Timing (100Base-TX) Parameters ................................................................................................... 46
Table 12. RMII Timing Parameters – KSZ8041NL .............................................................................................................. 47
Table 13. RMII Timing Parameters – KSZ8041RNL............................................................................................................ 47
Table 14. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters ............................................................................... 48
Table 15. MDC/MDIO Timing Parameters ........................................................................................................................... 49
Table 16. Reset Timing Parameters .................................................................................................................................... 50
Table 17. Transformer Selection Criteria ............................................................................................................................. 53
Table 18. Qualified Single Port Magnetics........................................................................................................................... 53
Table 19. Typical Reference Crystal Characteristics ........................................................................................................... 53
253H
127H
254H
128H
25H
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Pin Configuration – KSZ8041NL
®
32-Pin (5mm x 5mm) MLF
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KSZ8041NL/RNL
Pin Description – KSZ8041NL
(1)
Pin Number
Pin Name
1
GND
2
VDDPLL_1.8
P
1.8V analog VDD
3
VDDA_3.3
P
3.3V analog VDD
4
RX-
I/O
Physical receive or transmit signal (- differential)
5
RX+
I/O
Physical receive or transmit signal (+ differential)
6
TX-
I/O
Physical transmit or receive signal (- differential)
7
TX+
I/O
Physical transmit or receive signal (+ differential)
8
XO
O
Crystal feedback
Type
Gnd
Pin Function
Ground
This pin is used only in MII mode when a 25 MHz crystal is used.
This pin is a no connect if oscillator or external clock source is used, or if RMII mode
is selected.
9
XI /
I
REFCLK
10
REXT
I/O
Crystal / Oscillator / External Clock Input
MII Mode:
25MHz +/-50ppm (crystal, oscillator, or external clock)
RMII Mode:
50MHz +/-50ppm (oscillator, or external clock only)
Set physical transmit output current
Connect a 6.49KΩ resistor in parallel with a 100pF capacitor to ground on this pin.
See KSZ8041NL reference schematics.
11
MDIO
I/O
Management Interface (MII) Data I/O
This pin requires an external 4.7KΩ pull-up resistor.
12
MDC
I
Management Interface (MII) Clock Input
This pin is synchronous to the MDIO data interface.
13
RXD3 /
Ipu/O
PHYAD0
14
RXD2 /
Ipd/O
PHYAD1
15
16
RXD1 /
Receive Data Output[3]
Config Mode:
The pull-up/pull-down value is latched as PHYADDR[0] during
power-up / reset. See “Strapping Options” section for details.
MII Mode:
Receive Data Output[2]
Config Mode:
The pull-up/pull-down value is latched as PHYADDR[1] during
power-up / reset. See “Strapping Options” section for details.
MII Mode:
Receive Data Output[1]
(2)
/
(3)
/
(2)
/
/
RXD[1] /
RMII Mode:
Receive Data Output[1]
PHYAD2
Config Mode:
The pull-up/pull-down value is latched as PHYADDR[2] during
power-up / reset. See “Strapping Options” section for details.
MII Mode:
Receive Data Output[0]
(2)
/
(3)
/
RXD0 /
Ipu/O
RXD[0] /
RMII Mode:
Receive Data Output[0]
DUPLEX
Config Mode:
Latched as DUPLEX (register 0h, bit 8) during power-up /
reset. See “Strapping Options” section for details.
17
VDDIO_3.3
18
RXDV /
19
Ipd/O
(2)
MII Mode:
P
Ipd/O
3.3V digital VDD
MII Mode:
Receive Data Valid Output /
CRSDV /
RMII Mode:
Carrier Sense/Receive Data Valid Output /
CONFIG2
Config Mode:
The pull-up/pull-down value is latched as CONFIG2 during
power-up / reset. See “Strapping Options” section for details.
MII Mode:
Receive Clock Output
RXC
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Pin Description – KSZ8041NL (Continued)
Pin Number
Pin Name
20
RXER /
21
(1)
Type
MII Mode:
Receive Error Output /
RX_ER /
RMII Mode:
Receive Error Output /
ISO
Config Mode:
The pull-up/pull-down value is latched as ISOLATE during
power-up / reset. See “Strapping Options” section for details.
INTRP
Ipd/O
Pin Function
Opu
Interrupt Output: Programmable Interrupt Output
Register 1Bh is the Interrupt Control/Status Register for programming the interrupt
conditions and reading the interrupt status. Register 1Fh bit 9 sets the interrupt
output to active low (default) or active high.
22
23
TXC
O
MII Mode:
TXEN /
I
MII Mode:
Transmit Enable Input /
RMII Mode:
Transmit Enable Input
MII Mode:
Transmit Data Input[0]
(4)
RMII Mode:
Transmit Data Input[0]
(5)
MII Mode:
Transmit Data Input[1]
(4)
RMII Mode:
Transmit Data Input[1]
(5)
MII Mode:
Transmit Data Input[2]
(4)
/
(4)
/
TX_EN
24
TXD0 /
I
TXD[0]
25
TXD1 /
I
TXD[1]
26
27
28
TXD2
I
/
/
TXD3
I
MII Mode:
Transmit Data Input[3]
COL /
Ipd/O
MII Mode:
Collision Detect Output /
Config Mode:
The pull-up/pull-down value is latched as CONFIG0 during
power-up / reset. See “Strapping Options” section for details.
MII Mode:
Carrier Sense Output /
Config Mode:
The pull-up/pull-down value is latched as CONFIG1 during
power-up / reset. See “Strapping Options” section for details.
CONFIG0
29
Transmit Clock Output
CRS /
CONFIG1
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Ipd/O
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KSZ8041NL/RNL
Pin Description – KSZ8041NL (Continued)
Pin Number
Pin Name
30
LED0 /
NWAYEN
(1)
Type
Ipu/O
Pin Function
LED Output:
Programmable LED0 Output /
Config Mode:
Latched as Auto-Negotiation Enable (register 0h, bit 12) during
power-up / reset. See “Strapping Options” section for details.
The LED0 pin is programmable via register 1Eh bits [15:14], and is defined as
follows.
LED mode = [00]
Link/Activity
Pin State
LED Definition
No Link
H
OFF
Link
L
ON
Activity
Toggle
Blinking
Link
Pin State
LED Definition
No Link
H
OFF
Link
L
ON
LED mode = [01]
LED mode = [10]
Reserved
LED mode = [11]
Reserved
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KSZ8041NL/RNL
Pin Description – KSZ8041NL (Continued)
Pin Number
Pin Name
31
LED1 /
(1)
Type
Ipu/O
SPEED
Pin Function
LED Output:
Programmable LED1 Output /
Config Mode:
Latched as SPEED (register 0h, bit 13) during power-up / reset.
See “Strapping Options” section for details.
The LED1 pin is programmable via register 1Eh bits [15:14], and is defined as
follows.
LED mode = [00]
Speed
Pin State
LED Definition
10BT
H
OFF
100BT
L
ON
Pin State
LED Definition
LED mode = [01]
Activity
No Activity
H
OFF
Activity
Toggle
Blinking
LED mode = [10]
Reserved
LED mode = [11]
Reserved
32
RST#
I
Chip Reset (active low)
PADDLE
GND
Gnd
Ground
Notes:
1. P = Power supply.
Gnd = Ground.
I = Input.
O = Output.
I/O = Bi-directional.
Ipd = Input with internal pull-down (40K +/-30%).
Ipu = Input with internal pull-up (40K +/-30%).
Opu = Output with internal pull-up (40K +/-30%).
Ipu/O = Input with internal pull-up (40K +/-30%) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (40K +/-30%) during power-up/reset; output pin otherwise.
2. MII Rx Mode: The RXD[3..0] bits are synchronous with RXCLK. When RXDV is asserted, RXD[3..0] presents valid data to MAC through the
MII. RXD[3..0] is invalid when RXDV is de-asserted.
3. RMII Rx Mode: The RXD[1:0] bits are synchronous with REF_CLK. For each clock period in which CRS_DV is asserted, two bits of
recovered data are sent from the PHY.
4. MII Tx Mode: The TXD[3..0] bits are synchronous with TXCLK. When TXEN is asserted, TXD[3..0] presents valid data from the MAC through
the MII. TXD[3..0] has no effect when TXEN is de-asserted.
5. RMII Tx Mode: The TXD[1:0] bits are synchronous with REF_CLK. For each clock period in which TX_EN is asserted, two bits of data are
received by the PHY from the MAC.
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KSZ8041NL/RNL
Strapping Options – KSZ8041NL
(1)
Pin Number
Pin Name
15
PHYAD2
Ipd/O
14
PHYAD1
Ipd/O
The PHY Address is latched at power-up / reset and is configurable to any value from
1 to 7.
13
PHYAD0
Ipu/O
The default PHY Address is 00001.
18
CONFIG2
Ipd/O
29
CONFIG1
Ipd/O
28
CONFIG0
Ipd/O
Type
Pin Function
PHY Address bits [4:3] are always set to ‘00’.
20
ISO
Ipd/O
The CONFIG[2:0] strap-in pins are latched at power-up / reset and are defined as
follows:
CONFIG[2:0]
Mode
000
MII (default)
001
RMII
010
Reserved – not used
011
Reserved – not used
100
MII 100Mbps Preamble Restore
101
Reserved – not used
110
Reserved – not used
111
Reserved – not used
ISOLATE mode
Pull-up = Enable
Pull-down (default) = Disable
During power-up / reset, this pin value is latched into register 0h bit 10.
31
SPEED
Ipu/O
SPEED mode
Pull-up (default) = 100Mbps
Pull-down = 10Mbps
During power-up / reset, this pin value is latched into register 0h bit 13 as the Speed
Select, and also is latched into register 4h (Auto-Negotiation Advertisement) as the
Speed capability support.
16
DUPLEX
Ipu/O
DUPLEX mode
Pull-up (default) = Half Duplex
Pull-down = Full Duplex
During power-up / reset, this pin value is latched into register 0h bit 8 as the Duplex
Mode.
30
NWAYEN
Ipu/O
Nway Auto-Negotiation Enable
Pull-up (default) = Enable Auto-Negotiation
Pull-down = Disable Auto-Negotiation
During power-up / reset, this pin value is latched into register 0h bit 12.
Note:
1.
Ipu/O = Input with internal pull-up (40K +/-30%) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (40K +/-30%) during power-up/reset; output pin otherwise.
Pin strap-ins are latched during power-up or reset. In some systems, the MAC receive input pins may drive high during
power-up or reset, and consequently cause the PHY strap-in pins on the MII/RMII signals to be latched high. In this
case, it is recommended to add 1K pull-downs on these PHY strap-in pins to ensure the PHY does not strap-in to
ISOLATE mode, or is not configured with an incorrect PHY Address.
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Pin Configuration – KSZ8041RNL
®
32-Pin (5mm x 5mm) MLF
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KSZ8041NL/RNL
Pin Description – KSZ8041RNL
(1)
Pin Number
Pin Name
1
GND
2
VDDPLL_1.8
P
1.8V analog VDD
3
VDDA_3.3
P
3.3V analog VDD
4
RX-
I/O
Physical receive or transmit signal (- differential)
5
RX+
I/O
Physical receive or transmit signal (+ differential)
6
TX-
I/O
Physical transmit or receive signal (- differential)
7
TX+
I/O
Physical transmit or receive signal (+ differential)
8
XO
O
Crystal feedback – for 25 MHz crystal
9
XI
I
Type
Gnd
Pin Function
Ground
This pin is a no connect if oscillator or external clock source is used.
Crystal / Oscillator / External Clock Input
25MHz +/-50ppm
10
REXT
I/O
Set physical transmit output current
Connect a 6.49KΩ resistor in parallel with a 100pF capacitor to ground on this
pin. See KSZ8041RNL reference schematics.
11
MDIO
I/O
Management Interface (MII) Data I/O
This pin requires an external 4.7KΩ pull-up resistor.
12
MDC
I
Management Interface (MII) Clock Input
13
PHYAD0
Ipu/O
The pull-up/pull-down value is latched as PHYADDR[0] during power-up / reset.
See “Strapping Options” section for details.
14
PHYAD1
Ipd/O
The pull-up/pull-down value is latched as PHYADDR[1] during power-up / reset.
See “Strapping Options” section for details.
15
RXD1 /
Ipd/O
RMII Mode:
RMII Receive Data Output[1]
Config Mode:
The pull-up/pull-down value is latched as PHYADDR[2] during
power-up / reset. See “Strapping Options” section for details.
RMII Mode:
RMII Receive Data Output[0]
Config Mode:
Latched as DUPLEX (register 0h, bit 8) during power-up /
reset. See “Strapping Options” section for details.
This pin is synchronous to the MDIO data interface.
PHYAD2
16
RXD0 /
Ipu/O
DUPLEX
17
VDDIO_3.3
P
18
CRS_DV /
Ipd/O
CONFIG2
19
REF_CLK
O
(2)
(2)
/
/
3.3V digital VDD
RMII Mode:
Carrier Sense/Receive Data Valid Output /
Config Mode:
The pull-up/pull-down value is latched as CONFIG2 during
power-up / reset. See “Strapping Options” section for details.
50MHz Clock Output
This pin provides the 50MHz RMII reference clock output to the MAC.
20
RX_ER /
Ipd/O
ISO
21
INTRP
Opu
RMII Mode:
RMII Receive Error Output /
Config Mode:
The pull-up/pull-down value is latched as ISOLATE during
power-up / reset. See “Strapping Options” section for details.
Interrupt Output: Programmable Interrupt Output
Register 1Bh is the Interrupt Control/Status Register for programming the
interrupt conditions and reading the interrupt status. Register 1Fh bit 9 sets the
interrupt output to active low (default) or active high.
22
NC
O
No connect
23
TX_EN
I
RMII Transmit Enable Input
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KSZ8041NL/RNL
Pin Description – KSZ8041RNL (Continued)
(1)
Pin Number
Pin Name
24
TXD0
I
RMII Transmit Data Input[0]
25
TXD1
I
RMII Transmit Data Input[1]
26
NC
I
No connect
27
NC
28
CONFIG0
Ipd/O
The pull-up/pull-down value is latched as CONFIG0 during power-up / reset.
See “Strapping Options” section for details.
29
CONFIG1
Ipd/O
The pull-up/pull-down value is latched as CONFIG1 during power-up / reset.
See “Strapping Options” section for details.
30
LED0 /
Ipu/O
LED Output:
Programmable LED0 Output /
Config Mode:
during
Latched as Auto-Negotiation Enable (register 0h, bit 12)
power-up / reset. See “Strapping Options” section for details.
NWAYEN
Type
I
Pin Function
(3)
(3)
No connect
The LED0 pin is programmable via register 1Eh bits [15:14], and is defined as
follows.
LED mode = [00]
Link/Activity
Pin State
LED Definition
No Link
H
OFF
Link
L
ON
Activity
Toggle
Blinking
Link
Pin State
LED Definition
No Link
H
OFF
Link
L
ON
LED mode = [01]
LED mode = [10] , [11]
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KSZ8041NL/RNL
Pin Description – KSZ8041RNL (Continued)
Pin Number
Pin Name
31
LED1 /
(1)
Type
Ipu/O
SPEED
Pin Function
LED Output:
Programmable LED1 Output /
Config Mode:
Latched as SPEED (register 0h, bit 13) during power-up / reset.
See “Strapping Options” section for details.
The LED1 pin is programmable via register 1Eh bits [15:14], and is defined as
follows.
LED mode = [00]
Speed
Pin State
LED Definition
10BT
H
OFF
100BT
L
ON
Pin State
LED Definition
LED mode = [01]
Activity
No Activity
H
OFF
Activity
Toggle
Blinking
LED mode = [10], [11]
32
RST#
I
PADDLE
GND
Gnd
Reserved
Chip Reset (active low)
Ground
Notes:
1.
P = Power supply.
Gnd = Ground.
I = Input.
O = Output.
I/O = Bi-directional.
Opu = Output with internal pull-up (40K +/-30%).
Ipu/O = Input with internal pull-up (40K +/-30%) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (40K +/-30%) during power-up/reset; output pin otherwise.
2.
RMII Rx Mode: The RXD[1:0] bits are synchronous with REF_CLK. For each clock period in which CRS_DV is asserted, two bits of
recovered data are sent from the PHY.
3.
RMII Tx Mode: The TXD[1:0] bits are synchronous with REF_CLK. For each clock period in which TX_EN is asserted, two bits of data are
received by the PHY from the MAC.
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KSZ8041NL/RNL
Strapping Options – KSZ8041RNL
(1)
Pin Number
Pin Name
15
PHYAD2
Ipd/O
14
PHYAD1
Ipd/O
The PHY Address is latched at power-up / reset and is configurable to any value from
1 to 7.
13
PHYAD0
Ipu/O
The default PHY Address is 00001.
18
CONFIG2
Ipd/O
29
CONFIG1
Ipd/O
28
CONFIG0
Ipd/O
Type
Pin Function
PHY Address bits [4:3] are always set to ‘00’.
20
ISO
Ipd/O
The CONFIG[2:0] strap-in pins are latched at power-up / reset and are defined as
follows:
CONFIG[2:0]
Mode
000
Reserved – not used
001
RMII
010
Reserved – not used
011
Reserved – not used
100
Reserved – not used
101
Reserved – not used
110
Reserved – not used
111
Reserved – not used
ISOLATE mode
Pull-up = Enable
Pull-down (default) = Disable
During power-up / reset, this pin value is latched into register 0h bit 10.
31
SPEED
Ipu/O
SPEED mode
Pull-up (default) = 100Mbps
Pull-down = 10Mbps
During power-up / reset, this pin value is latched into register 0h bit 13 as the Speed
Select, and also is latched into register 4h (Auto-Negotiation Advertisement) as the
Speed capability support.
16
DUPLEX
Ipu/O
DUPLEX mode
Pull-up (default) = Half Duplex
Pull-down = Full Duplex
During power-up / reset, this pin value is latched into register 0h bit 8 as the Duplex
Mode.
30
NWAYEN
Ipu/O
Nway Auto-Negotiation Enable
Pull-up (default) = Enable Auto-Negotiation
Pull-down = Disable Auto-Negotiation
During power-up / reset, this pin value is latched into register 0h bit 12.
Note:
1.
Ipu/O = Input with internal pull-up (40K +/-30%) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (40K +/-30%) during power-up/reset; output pin otherwise.
Pin strap-ins are latched during power-up or reset. In some systems, the MAC receive input pins may drive high during
power-up or reset, and consequently cause the PHY strap-in pins on the RMII signals to be latched high. In this case, it is
recommended to add 1K pull-downs on these PHY strap-in pins to ensure the PHY does not strap-in to ISOLATE mode,
or is not configured with an incorrect PHY Address.
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KSZ8041NL/RNL
Functional Description
The KSZ8041NL is a single 3.3V supply Fast Ethernet transceiver. It is fully compliant with the IEEE 802.3u Specification.
On the media side, the KSZ8041NL supports 10Base-T and 100Base-TX with HP auto MDI/MDI-X for reliable detection of
and correction for straight-through and crossover cables.
The KSZ8041NL offers a choice of MII or RMII data interface connection with the MAC processor. The MII management
bus option gives the MAC processor complete access to the KSZ8041NL control and status registers. Additionally, an
interrupt pin eliminates the need for the processor to poll for PHY status change.
Physical signal transmission and reception are enhanced through the use of patented analog circuitries that make the
design more efficient and allow for lower power consumption and smaller chip die size.
The KSZ8041RNL is an enhanced RMII version of the KSZ8041NL that does not require a 50MHz system clock. It uses a
25MHz crystal for its input reference clock and outputs a 50MHz RMII reference clock to the MAC.
100Base-TX Transmit
The 100Base-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI
conversion, and MLT3 encoding and transmission.
The circuitry starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125MHz serial bit
stream. The data and control stream is then converted into 4B/5B coding, followed by a scrambler. The serialized data is
further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output.
The output current is set by an external 6.49kΩ 1% resistor for the 1:1 transformer ratio. It has typical rise/fall times of 4
ns and complies with the ANSI TP-PMD standard regarding amplitude balance, overshoot and timing jitter. The waveshaped 10Base-T output drivers are also incorporated into the 100Base-TX drivers.
100Base-TX Receive
The 100Base-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and
clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion.
The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair
cable. Since the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust its
characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on
comparisons of incoming signal strength against some known cable characteristics, and then tunes itself for optimization.
This is an ongoing process and self-adjusts against environmental changes such as temperature variations.
Next, the equalized signal goes through a DC restoration and data conversion block. The DC restoration circuit is used to
compensate for the effect of baseline wander and to improve the dynamic range. The differential data conversion circuit
converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used
to convert the NRZI signal into the NRZ format. This signal is sent through the de-scrambler followed by the 4B/5B
decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to the MAC.
PLL Clock Synthesizer
The KSZ8041NL/RNL generates 125MΗz, 25MΗz and 20MΗz clocks for system timing. Internal clocks are generated
from an external 25MHz crystal or oscillator. For the KSZ8041NL in RMII mode, these internal clocks are generated from
an external 50MHz oscillator or system clock.
Scrambler/De-scrambler (100Base-TX only)
The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline wander.
10Base-T Transmit
The 10Base-T drivers are incorporated with the 100Base-TX drivers to allow for transmission using the same magnetic.
The drivers also perform internal wave-shaping and pre-emphasize, and output 10Base-T signals with a typical amplitude
of 2.5V peak. The 10Base-T signals have harmonic contents that are at least 27dB below the fundamental frequency
when driven by an all-ones Manchester-encoded signal.
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KSZ8041NL/RNL
10Base-T Receive
On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit and
a PLL performs the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data.
A squelch circuit rejects signals with levels less than 400 mV or with short pulse widths to prevent noise at the RX+ and
RX- inputs from falsely trigger the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming
signal and the KSZ8041NL/RNL decodes a data frame. The receive clock is kept active during idle periods in between
data reception.
SQE and Jabber Function (10Base-T only)
In 10Base-T operation, a short pulse is put out on the COL pin after each frame is transmitted. This SQE Test is required
as a test of the 10Base-T transmit/receive path. If transmit enable (TXEN) is high for more than 20 ms (jabbering), the
10Base-T transmitter is disabled and COL is asserted high. If TXEN is then driven low for more than 250 ms, the 10BaseT transmitter is re-enabled and COL is de-asserted (returns to low).
Auto-Negotiation
The KSZ8041NL/RNL conforms to the auto-negotiation protocol, defined in Clause 28 of the IEEE 802.3u specification.
Auto-negotiation is enabled by either hardware pin strapping (pin 30) or software (register 0h bit 12).
Auto-negotiation allows unshielded twisted pair (UTP) link partners to select the highest common mode of operation. Link
partners advertise their capabilities to each other, and then compare their own capabilities with those they received from
their link partners. The highest speed and duplex setting that is common to the two link partners is selected as the mode
of operation.
The following list shows the speed and duplex operation mode from highest to lowest.
•
Priority 1: 100Base-TX, full-duplex
•
Priority 2: 100Base-TX, half-duplex
•
Priority 3: 10Base-T, full-duplex
• Priority 4: 10Base-T, half-duplex
If auto-negotiation is not supported or the KSZ8041NL/RNL link partner is forced to bypass auto-negotiation, the
KSZ8041NL/RNL sets its operating mode by observing the signal at its receiver. This is known as parallel detection, and
allows the KSZ8041NL/RNL to establish link by listening for a fixed signal protocol in the absence of auto-negotiation
advertisement protocol.
The auto-negotiation link up process is shown in the flow chart illustrated as Figure 1.
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KSZ8041NL/RNL
Start Auto Negotiation
Force Link Setting
N
o
Parallel
Operation
Yes
Bypass Auto Negotiation
and Set Link Mode
Attempt Auto
Negotiation
Listen for 100BASE-TX
Idles
Listen for 10BASE-T
Link Pulses
No
Join
Flow
Link Mode Set ?
Yes
Link Mode Set
Figure 1. Auto-Negotiation Flow Chart
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KSZ8041NL/RNL
MII Management (MIIM) Interface
The KSZ8041NL/RNL supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input /
Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of the
KSZ8041NL/RNL. An external device with MIIM capability is used to read the PHY status and/or configure the PHY
settings. Further details on the MIIM interface can be found in Clause 22.2.4 of the IEEE 802.3 Specification.
The MIIM interface consists of the following:
•
A physical connection that incorporates the clock line (MDC) and the data line (MDIO).
•
A specific protocol that operates across the aforementioned physical connection that allows a external controller
to communicate with one or more PHY devices. Each KSZ8041NL/RNL device is assigned a unique PHY address
between 1 and 7 by its PHYAD[2:0] strapping pins. Also, every KSZ8041NL/RNL device supports the broadcast
PHY address 0, as defined per the IEEE 802.3 Specification, which can be used to read/write to a single
KSZ8041NL/RNL device, or write to multiple KSZ8041NL/RNL devices simultaneously.
•
A set of 16-bit MDIO registers. Register [0:6] are required, and their functions are defined per the IEEE 802.3
Specification. The additional registers are provided for expanded functionality.
The Table 1 shows the MII Management frame format for the KSZ8041NL/RNL.
Preamble
Start of
Frame
Read/Write
PHY
REG
OP Code
Address
Address
TA
Data
Idle
Bits [15:0]
Bits [4:0]
Bits [4:0]
Read
32 1’s
01
10
00AAA
RRRRR
Z0
DDDDDDDD_DDDDDDDD
Z
Write
32 1’s
01
01
00AAA
RRRRR
10
DDDDDDDD_DDDDDDDD
Z
Table 1. MII Management Frame Format
Interrupt (INTRP)
INTRP (pin 21) is an optional interrupt signal that is used to inform the external controller that there has been a status
update to the KSZ8041NL/RNL PHY register. Bits[15:8] of register 1Bh are the interrupt control bits, and are used to
enable and disable the conditions for asserting the INTRP signal. Bits[7:0] of register 1Bh are the interrupt status bits, and
are used to indicate which interrupt conditions have occurred. The interrupt status bits are cleared after reading register
1Bh.
Bit 9 of register 1Fh sets the interrupt level to active high or active low.
MII Data Interface (KSZ8041NL only)
The Media Independent Interface (MII) is specified in Clause 22 of the IEEE 802.3 Specification. It provides a common
interface between physical layer and MAC layer devices, and has the following key characteristics:
•
Supports 10Mbps and 100Mbps data rates.
•
Uses a 25MHz reference clock, sourced by the PHY.
•
Provides independent 4-bit wide (nibble) transmit and receive data paths.
•
Contains two distinct groups of signals: one for transmission and the other for reception.
By default, the KSZ8041NL is configured to MII mode after it is power-up or reset with the following:
•
A 25MHz crystal connected to XI, XO (pins 9, 8), or an external 25MHz clock source (oscillator) connected to XI.
•
CONFIG[2:0] (pins 18, 29, 28) set to ‘000’ (default setting).
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KSZ8041NL/RNL
MII Signal Definition (KSZ8041NL only)
The Table 2 describes the MII signals. Refer to Clause 22 of the IEEE 802.3 Specification for detailed information.
MII
Signal Name
Direction
(with respect to PHY,
KSZ8041NL signal)
Direction
(with respect to MAC)
TXC
Output
Input
Transmit Clock
(2.5MHz for 10Mbps; 25MHz for 100Mbps)
TXEN
Input
Output
Transmit Enable
TXD[3:0]
Input
Output
Transmit Data [3:0]
RXC
Output
Input
Receive Clock
RXDV
Output
Input
Receive Data Valid
RXD[3:0]
Output
Input
Receive Data [3:0]
Description
(2.5MHz for 10Mbps; 25MHz for 100Mbps)
RXER
Output
Input, or (not required)
Receive Error
CRS
Output
Input
Carrier Sense
COL
Output
Input
Collision Detection
Table 2. MII Signal Definition
Transmit Clock (TXC)
TXC is sourced by the PHY. It is a continuous clock that provides the timing reference for TXEN and TXD[3:0].
TXC is 2.5MHz for 10Mbps operation and 25MHz for 100Mbps operation.
Transmit Enable (TXEN)
TXEN indicates the MAC is presenting nibbles on TXD[3:0] for transmission. It is asserted synchronously with the first
nibble of the preamble and remains asserted while all nibbles to be transmitted are presented on the MII, and is negated
prior to the first TXC following the final nibble of a frame.
TXEN transitions synchronously with respect to TXC.
Transmit Data [3:0] (TXD[3:0])
TXD[3:0] transitions synchronously with respect to TXC. When TXEN is asserted, TXD[3:0] are accepted for transmission
by the PHY. TXD[3:0] is ”00” to indicate idle when TXEN is de-asserted. Values other than “00” on TXD[3:0] while TXEN
is de-asserted are ignored by the PHY.
Receive Clock (RXC)
RXC provides the timing reference for RXDV, RXD[3:0], and RXER.
•
In 10Mbps mode, RXC is recovered from the line while carrier is active. RXC is derived from the PHY’s reference
clock when the line is idle, or link is down.
•
In 100Mbps mode, RXC is continuously recovered from the line. If link is down, RXC is derived from the PHY’s
reference clock.
RXC is 2.5MHz for 10Mbps operation and 25MHz for 100Mbps operation.
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Receive Data Valid (RXDV)
RXDV is driven by the PHY to indicate that the PHY is presenting recovered and decoded nibbles on RXD[3:0].
•
In 10Mbps mode, RXDV is asserted with the first nibble of the SFD (Start of Frame Delimiter), “5D”, and remains
asserted until the end of the frame.
• In 100Mbps mode, RXDV is asserted from the first nibble of the preamble to the last nibble of the frame.
RXDV transitions synchronously with respect to RXC.
Receive Data [3:0] (RXD[3:0])
RXD[3:0] transitions synchronously with respect to RXC. For each clock period in which RXDV is asserted, RXD[3:0]
transfers a nibble of recovered data from the PHY.
Receive Error (RXER)
RXER is asserted for one or more RXC periods to indicate that a Symbol Error (e.g. a coding error that a PHY is capable
of detecting, and that may otherwise be undetectable by the MAC sub-layer) was detected somewhere in the frame
presently being transferred from the PHY.
RXER transitions synchronously with respect to RXC. While RXDV is de-asserted, RXER has no effect on the MAC.
Carrier Sense (CRS)
CRS is asserted and de-asserted as follows:
•
In 10Mbps mode, CRS assertion is based on the reception of valid preambles. CRS de-assertion is based on the
reception of an end-of-frame (EOF) marker.
•
In 100Mbps mode, CRS is asserted when a start-of-stream delimiter, or /J/K symbol pair is detected. CRS is deasserted when an end-of-stream delimiter, or /T/R symbol pair is detected. Additionally, the PMA layer de-asserts
CRS if IDLE symbols are received without /T/R.
Collision (COL)
COL is asserted in half-duplex mode whenever the transmitter and receiver are simultaneously active on the line. This is
used to inform the MAC that a collision has occurred during its transmission to the PHY.
COL transitions asynchronously with respect to TXC and RXC.
Reduced MII (RMII) Data Interface
The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII). It provides
a common interface between physical layer and MAC layer devices, and has the following key characteristics:
•
Supports 10Mbps and 100Mbps data rates.
•
Uses a 50MHz reference clock.
•
Provides independent 2-bit wide (di-bit) transmit and receive data paths.
•
Contains two distinct groups of signals: one for transmission and the other for reception.
The KSZ8041NL is configured in RMII mode after it is power-up or reset with the following:
•
A 50MHz reference clock connected to REFCLK (pin 9).
•
CONFIG[2:0] (pins 18, 29, 28) set to ‘001’.
The KSZ8041RNL is configured in RMII mode and outputs the 50MHz RMII reference clock to the MAC on REF_CLK (pin
19) after it is power-up or reset with the following:
•
A 25MHz crystal connected to XI (pin 9) and XO (pin 8), or a 25MHz reference clock connected to XI (pin 9).
•
CONFIG[2:0] (pins 18, 29, 28) set to ‘001’.
In RMII mode, unused MII signals, TXD[3:2] (pins 27, 26), are tied to ground.
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KSZ8041NL/RNL
RMII Signal Definition
The Tables 3 and 4 describe the RMII signals for KSZ8041NL and KSZ8041RNL. Refer to RMII Specification for detailed
information.
RMII
Signal Name
Direction
(with respect to PHY,
KSZ8041NL signal)
Direction
(with respect to MAC)
REF_CLK
Input
Input, or Output
Synchronous 50 MHz clock reference for
receive, transmit and control interface
TX_EN
Input
Output
Transmit Enable
TXD[1:0]
Input
Output
Transmit Data [1:0]
CRS_DV
Output
Input
Carrier Sense/Receive Data Valid
RXD[1:0]
Output
Input
Receive Data [1:0]
RX_ER
Output
Input, or (not required)
Receive Error
Description
Table 3. RMII Signal Description – KSZ8041NL
RMII
Signal Name
Direction
(with respect to PHY,
KSZ8041RNL signal)
Direction
(with respect to MAC)
REF_CLK
Output
Input
Synchronous 50 MHz clock reference for
receive, transmit and control interface
TX_EN
Input
Output
Transmit Enable
TXD[1:0]
Input
Output
Transmit Data [1:0]
CRS_DV
Output
Input
Carrier Sense/Receive Data Valid
RXD[1:0]
Output
Input
Receive Data [1:0]
RX_ER
Output
Input, or (not required)
Receive Error
Description
Table 4. RMII Signal Description – KSZ8041RNL
Reference Clock (REF_CLK)
REF_CLK is a continuous 50MHz clock that provides the timing reference for TX_EN, TXD[1:0], CRS_DV, RXD[1:0], and
RX_ER.
The KSZ8041NL inputs the 50MHz REF_CLK from the MAC or system board.
The KSZ8041RNL generates the 50MHz RMII REF_CLK and outputs it to the MAC.
Transmit Enable (TX_EN)
TX_EN indicates that the MAC is presenting di-bits on TXD[1:0] for transmission. It is asserted synchronously with the first
nibble of the preamble and remains asserted while all di-bits to be transmitted are presented on the RMII, and is negated
prior to the first REF_CLK following the final di-bit of a frame.
TX_EN transitions synchronously with respect to REF_CLK.
Transmit Data [1:0] (TXD[1:0])
TXD[1:0] transitions synchronously with respect to REF_CLK. When TX_EN is asserted, TXD[1:0] are accepted for
transmission by the PHY. TXD[1:0] is ”00” to indicate idle when TX_EN is de-asserted. Values other than “00” on TXD[1:0]
while TX_EN is de-asserted are ignored by the PHY.
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Carrier Sense/Receive Data Valid (CRS_DV)
CRS_DV is asserted by the PHY when the receive medium is non-idle. It is asserted asynchronously on detection of
carrier. This is when squelch is passed in 10Mbps mode, and when 2 non-contiguous zeroes in 10 bits are detected in
100Mbps mode. Loss of carrier results in the de-assertion of CRS_DV.
So long as carrier detection criteria are met, CRS_DV remains asserted continuously from the first recovered di-bit of the
frame through the final recovered di-bit, and it is negated prior to the first REF_CLK that follows the final di-bit. The data
on RXD[1:0] is considered valid once CRS_DV is asserted. However, since the assertion of CRS_DV is asynchronous
relative to REF_CLK, the data on RXD[1:0] is "00" until proper receive signal decoding takes place.
Receive Data [1:0] (RXD[1:0])
RXD[1:0] transitions synchronously to REF_CLK. For each clock period in which CRS_DV is asserted, RXD[1:0] transfers
two bits of recovered data from the PHY. RXD[1:0] is "00" to indicate idle when CRS_DV is de-asserted. Values other
than “00” on RXD[1:0] while CRS_DV is de-asserted are ignored by the MAC.
Receive Error (RX_ER)
RX_ER is asserted for one or more REF_CLK periods to indicate that a Symbol Error (e.g. a coding error that a PHY is
capable of detecting, and that may otherwise be undetectable by the MAC sub-layer) was detected somewhere in the
frame presently being transferred from the PHY.
RX_ER transitions synchronously with respect to REF_CLK. While CRS_DV is de-asserted, RX_ER has no effect on the
MAC.
Collision Detection
The MAC regenerates the COL signal of the MII from TX_EN and CRS_DV.
RMII Signal Diagram
The KSZ8041NL RMII pin connections to the MAC are shown in Figure 2.
Figure 2. KSZ8041NL RMII Interface
September 2010
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M9999-090910-1.4
Micrel, Inc.
KSZ8041NL/RNL
The KSZ8041RNL RMII pin connections to the MAC are shown in Figure 3.
Figure 3. KSZ8041RNL RMII Interface
HP Auto MDI/MDI-X
HP Auto MDI/MDI-X configuration eliminates the confusion of whether to use a straight cable or a crossover cable
between the KSZ8041NL/RNL and its link partner. This feature allows the KSZ8041NL/RNL to use either type of cable to
connect with a link partner that is in either MDI or MDI-X mode. The auto-sense function detects transmit and receive
pairs from the link partner, and then assigns transmit and receive pairs of the KSZ8041NL/RNL accordingly.
HP Auto MDI/MDI-X is enabled by default. It is disabled by writing a one to register 1F bit 13. MDI and MDI-X mode is
selected by register 1F bit 14 if HP Auto MDI/MDI-X is disabled.
An isolation transformer with symmetrical transmit and receive data paths is recommended to support auto MDI/MDI-X.
The IEEE 802.3 Standard defines MDI and MDI-X as follows:
MDI
MDI-X
RJ-45 Pin
Signal
RJ-45 Pin
Signal
1
2
TD+
1
RD+
TD-
2
RD-
3
RD+
3
TD+
6
RD-
6
TD-
Table 5. MDI/MDI-X Pin Definition
September 2010
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Micrel, Inc.
KSZ8041NL/RNL
Straight Cable
A straight cable connects a MDI device to a MDI-X device, or a MDI-X device to a MDI device. The Figure 4 depicts a
typical straight cable connection between a NIC card (MDI) and a switch, or hub (MDI-X).
10/100 Ethernet
Media Dependent Interface
10/100 Ethernet
Media Dependent Interface
1
1
2
2
Transmit Pair
Receive Pair
3
Straight
Cable
3
4
4
5
5
6
6
7
7
8
8
Receive Pair
Transmit Pair
Modular Connector
(RJ-45)
HUB
(Repeater or Switch)
Modular Connector
(RJ-45)
NIC
Figure 4. Typical Straight Cable Connection
Crossover Cable
A crossover cable connects a MDI device to another MDI device, or a MDI-X device to another MDI-X device. Figure 5
depicts a typical crossover cable connection between two switches or hubs (two MDI-X devices).
10/100 Ethernet
Media Dependent Interface
1
Receive Pair
10/100 Ethernet
Media Dependent Interface
Crossover
Cable
1
Receive Pair
2
2
3
3
4
4
5
5
6
6
7
7
8
8
Transmit Pair
Transmit Pair
Modular Connector (RJ-45)
HUB
(Repeater or Switch)
Modular Connector (RJ-45)
HUB
(Repeater or Switch)
Figure 5. Typical Crossover Cable Connection
September 2010
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Micrel, Inc.
KSZ8041NL/RNL
Power Management
The KSZ8041NL/RNL offers the following power management modes:
Power Saving Mode
This mode is used to reduce power consumption when the cable is unplugged. It is in effect when auto-negotiation mode
is enabled, cable is disconnected, and register 1F bit 10 is set to 1. Under power saving mode, the KSZ8041NL/RNL
shuts down all transceiver blocks, except for transmitter, energy detect and PLL circuits. Additionally, for the KSZ8041NL
in MII mode, the RXC clock output is disabled. RXC clock is enabled after the cable is connected and link is established.
Power saving mode is disabled by writing a zero to register 1F bit 10.
Power Down Mode
This mode is used to power down the entire KSZ8041NL/RNL device when it is not in use. Power down mode is enabled
by writing a one to register 0 bit 11. In the power down state, the KSZ8041NL/RNL disables all internal functions, except
for the MII management interface.
Reference Clock Connection Options
A crystal or clock source, such as an oscillator, is used to provide the reference clock for the KSZ8041NL/RNL.
The Figure 6 illustrates how to connect the 25MHz crystal and oscillator reference clock.
Figure 6. 25MHz Crystal / Oscillator Reference Clock
For the KSZ8041NL, Figure 7 illustrates how to connect the 50MHz oscillator reference clock for RMII mode.
Figure 7. 50MHz Oscillator Reference Clock for KSZ8041NL RMII Mode
September 2010
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Micrel, Inc.
KSZ8041NL/RNL
Reference Circuit for Power and Ground Connections
The KSZ8041NL/RNL is a single 3.3V supply device with a built-in 1.8V low noise regulator. The power and ground
connections are shown in Figure 8 and Table 6.
Ferrite
Bead
`
VIN
3
`
22uF
VDDA_3.3
VOUT
1.8V Low Noise
Regulator
(integrated)
0.1uF
10uF
0.1uF
VDDPLL_1.8
2
17
3.3V
VDDIO_3.3
`
22uF
KSZ8041NL/RNL
0.1uF
GND
1
Paddle
Figure 8. KSZ8041NL/RNL Power and Ground Connections
Power Pin
Pin Number
Description
VDDPLL_1.8
2
Decouple with 10uF and 0.1uF capacitors to ground.
VDDA_3.3
3
Connect to board’s 3.3V supply through ferrite bead.
VDDIO_3.3
17
Connect to board’s 3.3V supply.
Table 6. KSZ8041NL/RNL Power Pin Description
September 2010
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Micrel, Inc.
KSZ8041NL/RNL
Register Map
Register Number (Hex)
Description
0h
Basic Control
1h
Basic Status
2h
PHY Identifier 1
3h
PHY Identifier 2
4h
Auto-Negotiation Advertisement
5h
Auto-Negotiation Link Partner Ability
6h
Auto-Negotiation Expansion
7h
Auto-Negotiation Next Page
8h
Link Partner Next Page Ability
9h – 13h
Reserved
14h
MII Control
15h
RXER Counter
16h – 1Ah
Reserved
1Bh
Interrupt Control/Status
1Ch – 1Dh
Reserved
1Eh
PHY Control 1
1Fh
PHY Control 2
Register Description
Address
Name
(1)
Description
Mode
Default
1 = Software reset
RW/SC
0
RW
0
RW
Set by SPEED strapping pin.
Register 0h – Basic Control
0.15
Reset
0 = Normal operation
This bit is self-cleared after a ‘1’ is written to it.
0.14
Loop-back
1 = Loop-back mode
0 = Normal operation
0.13
Speed Select
(LSB)
1 = 100Mbps
See “Strapping Options” section
for details.
0 = 10Mbps
This bit is ignored if auto-negotiation is enabled
(register 0.12 = 1).
0.12
0.11
AutoNegotiation
Enable
1 = Enable auto-negotiation process
Power Down
1 = Power down mode
RW
Set by NWAYEN strapping pin.
See “Strapping Options” section
for details.
0 = Disable auto-negotiation process
If enabled, auto-negotiation result overrides
settings in register 0.13 and 0.8.
RW
0
0 = Normal operation
0.10
Isolate
1 = Electrical isolation of PHY from MII and
TX+/TX0 = Normal operation
September 2010
32
RW
Set by ISO strapping pin.
See “Strapping Options” section
for details.
M9999-090910-1.4
Micrel, Inc.
KSZ8041NL/RNL
Register Description (Continued)
Address
Name
(1)
Description
Mode
Default
1 = Restart auto-negotiation process
RW/SC
0
RW
Inverse of DUPLEX strapping pin
value.
Register 0h – Basic Control
0.9
Restart AutoNegotiation
0 = Normal operation.
This bit is self-cleared after a ‘1’ is written to it.
0.8
Duplex Mode
1 = Full-duplex
0 = Half-duplex
See “Strapping Options” section
for details.
0.7
Collision Test
1 = Enable COL test
0.6:1
Reserved
0.0
Disable
0 = Enable transmitter
Transmitter
1 = Disable transmitter
RW
0
RO
000_000
RW
0
RO
0
RO
1
RO
1
RO
1
RO
1
RO
0000
RO
1
RO
0
RO/LH
0
RO
1
RO/LL
0
RO/LH
0
RO
1
0 = Disable COL test
Register 1h – Basic Status
1.15
100Base-T4
1 = T4 capable
1.14
100Base-TX
Full Duplex
1 = Capable of 100Mbps full-duplex
100Base-TX
Half Duplex
1 = Capable of 100Mbps half-duplex
1.12
10Base-T Full
Duplex
1 = Capable of 10Mbps full-duplex
1.11
10Base-T Half
Duplex
1 = Capable of 10Mbps half-duplex
0 = Not T4 capable
1.13
1.10:7
Reserved
1.6
No Preamble
0 = Not capable of 100Mbps full-duplex
0 = Not capable of 100Mbps half-duplex
0 = Not capable of 10Mbps full-duplex
0 = Not capable of 10Mbps half-duplex
1 = Preamble suppression
0 = Normal preamble
1.5
1.4
AutoNegotiation
Complete
1 = Auto-negotiation process completed
Remote Fault
1 = Remote fault
0 = Auto-negotiation process not completed
0 = No remote fault
1.3
1.2
AutoNegotiation
Ability
1 = Capable to perform auto-negotiation
Link Status
1 = Link is up
0 = Not capable to perform auto-negotiation
0 = Link is down
1.1
Jabber Detect
1.0
Extended
Capability
1 = Jabber detected
0 = Jabber not detected (default is low)
September 2010
1 = Supports extended capabilities registers
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Micrel, Inc.
KSZ8041NL/RNL
Register Description (Continued)
Address
Name
(1)
Description
Mode
Default
Assigned to the 3rd through 18th bits of the
Organizationally Unique Identifier (OUI).
Kendin Communication’s OUI is 0010A1 (hex)
RO
0022h
Register 2h – PHY Identifier 1
2.15:0
PHY ID
Number
Register 3h – PHY Identifier 2
3.15:10
PHY ID
Number
Assigned to the 19th through 24th bits of the
Organizationally Unique Identifier (OUI).
Kendin Communication’s OUI is 0010A1 (hex)
RO
0001_01
3.9:4
Model Number
Six bit manufacturer’s model number
RO
01_0001
3.3:0
Revision
Number
Four bit manufacturer’s revision number
RO
Indicates silicon revision
RW
0
RO
0
RW
0
RO
0
RW
00
RO
0
RW
Set by SPEED strapping pin.
Register 4h – Auto-Negotiation Advertisement
4.15
Next Page
4.14
Reserved
4.13
Remote Fault
4.12
Reserved
4.11:10
Pause
1 = Next page capable
0 = No next page capability.
1 = Remote fault supported
0 = No remote fault
[00] = No PAUSE
[10] = Asymmetric PAUSE
[01] = Symmetric PAUSE
[11] = Asymmetric & Symmetric PAUSE
4.9
100Base-T4
1 = T4 capable
0 = No T4 capability
100Base-TX
Full-Duplex
1 = 100Mbps full-duplex capable
100Base-TX
Half-Duplex
1 = 100Mbps half-duplex capable
10Base-T
Full-Duplex
1 = 10Mbps full-duplex capable
4.5
10Base-T
Half-Duplex
1 = 10Mbps half-duplex capable
4.4:0
Selector Field
[00001] = IEEE 802.3
4.8
4.7
4.6
September 2010
See “Strapping Options” section
for details.
0 = No 100Mbps full-duplex capability
RW
Set by SPEED strapping pin.
See “Strapping Options” section
for details.
0 = No 100Mbps half-duplex capability
RW
1
RW
1
RW
0_0001
0 = No 10Mbps full-duplex capability
0 = No 10Mbps half-duplex capability
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Micrel, Inc.
KSZ8041NL/RNL
Register Description (Continued)
Address
Name
(1)
Description
Mode
Default
RO
0
RO
0
RO
0
RO
0
RO
00
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0_0001
RO
0000_0000_000
RO/LH
0
RO
0
RO
1
RO/LH
0
RO
0
Register 5h – Auto-Negotiation Link Partner Ability
5.15
Next Page
1 = Next page capable
0 = No next page capability
5.14
Acknowledge
5.13
Remote Fault
1 = Link code word received from partner
0 = Link code word not yet received
1 = Remote fault detected
0 = No remote fault
5.12
Reserved
5.11:10
Pause
[00] = No PAUSE
[10] = Asymmetric PAUSE
[01] = Symmetric PAUSE
[11] = Asymmetric & Symmetric PAUSE
5.9
100Base-T4
1 = T4 capable
5.8
100Base-TX
Full-Duplex
1 = 100Mbps full-duplex capable
100Base-TX
Half-Duplex
1 = 100Mbps half-duplex capable
5.6
10Base-T
Full-Duplex
1 = 10Mbps full-duplex capable
5.5
10Base-T
Half-Duplex
1 = 10Mbps half-duplex capable
Selector Field
[00001] = IEEE 802.3
0 = No T4 capability
5.7
5.4:0
0 = No 100Mbps full-duplex capability
0 = No 100Mbps half-duplex capability
0 = No 10Mbps full-duplex capability
0 = No 10Mbps half-duplex capability
Register 6h – Auto-Negotiation Expansion
6.15:5
Reserved
6.4
Parallel
Detection Fault
1 = Fault detected by parallel detection
Link Partner
Next Page
Able
1 = Link partner has next page capability
Next Page
Able
1 = Local device has next page capability
Page Received
1 = New page received
6.3
6.2
6.1
0 = No fault detected by parallel detection.
0 = Link partner does not have next page
capability
0 = Local device does not have next page
capability
0 = New page not received yet
6.0
Link Partner
AutoNegotiation
Able
September 2010
1 = Link partner has auto-negotiation capability
0 = Link partner does not have auto-negotiation
capability
35
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Micrel, Inc.
KSZ8041NL/RNL
Register Description (Continued)
Address
Name
(1)
Description
Mode
Default
RW
0
RO
0
RW
1
RW
0
RO
0
RW
000_0000_0001
RO
0
RO
0
RO
0
RO
0
RO
0
RO
000_0000_0000
RO
0000_0000
Register 7h – Auto-Negotiation Next Page
7.15
Next Page
1 = Additional next page(s) will follow
0 = Last page
7.14
Reserved
7.13
Message Page
1 = Message page
0 = Unformatted page
7.12
Acknowledge2
1 = Will comply with message
7.11
Toggle
1 = Previous value of the transmitted link code
word equaled logic one
7.10:0
Message Field
11-bit wide field to encode 2048 messages
0 = Cannot comply with message
0 = Logic zero
Register 8h – Link Partner Next Page Ability
8.15
Next Page
1 = Additional Next Page(s) will follow
0 = Last page
8.14
Acknowledge
1 = Successful receipt of link word
8.13
Message Page
1 = Message page
0 = No successful receipt of link word
0 = Unformatted page
8.12
Acknowledge2
1 = Able to act on the information
0 = Not able to act on the information
8.11
Toggle
1 = Previous value of transmitted link code
word equal to logic zero
0 = Previous value of transmitted link code
word equal to logic one
8.10:0
Message Field
Register 14h – MII Control
14.15:8
Reserved
14.7
100Base-TX
Preamble
Restore
1 = Restore received preamble to MII output
(random latency)
10Base-T
Preamble
Restore
1 = Restore received preamble to MII output
14.6
14.5:0
RW
0 or
1 (if CONFIG[2:0] = 100)
0 = Consume 1-byte preamble before sending
frame to MII output for fixed latency
See “Strapping Options” section
for details.
RW
0
RO
00_0001
RO/SC
0000h
0 = Remove all 7-bytes of preamble before
sending frame (starting with SFD) to MII
output
Reserved
Register 15h – RXER Counter
15.15:0
RXER Counter
September 2010
Receive error counter for Symbol Error frames
36
M9999-090910-1.4
Micrel, Inc.
KSZ8041NL/RNL
Register Description (Continued)
Address
Name
(1)
Description
Mode
Default
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RO/SC
0
RO/SC
0
RO/SC
0
RO/SC
0
RO/SC
0
RO/SC
0
RO/SC
0
RO/SC
0
Register 1Bh – Interrupt Control/Status
Jabber
Interrupt
Enable
1 = Enable Jabber Interrupt
Receive Error
Interrupt
Enable
1 = Enable Receive Error Interrupt
Page Received
Interrupt
Enable
1 = Enable Page Received Interrupt
Parallel Detect
Fault Interrupt
Enable
1 = Enable Parallel Detect Fault Interrupt
Link Partner
Acknowledge
Interrupt
Enable
1 = Enable Link Partner Acknowledge Interrupt
Link Down
Interrupt
Enable
1= Enable Link Down Interrupt
Remote Fault
Interrupt
Enable
1 = Enable Remote Fault Interrupt
Link Up
Interrupt
Enable
1 = Enable Link Up Interrupt
Jabber
Interrupt
1 = Jabber occurred
Receive Error
Interrupt
1 = Receive Error occurred
1b.5
Page Receive
Interrupt
1 = Page Receive occurred
1b.4
Parallel Detect
Fault Interrupt
1 = Parallel Detect Fault occurred
Link Partner
Acknowledge
Interrupt
1= Link Partner Acknowledge occurred
Link Down
Interrupt
1= Link Down occurred
Remote Fault
Interrupt
1= Remote Fault occurred
Link Up
Interrupt
1= Link Up occurred
1b.15
1b.14
1b.13
1b.12
1b.11
1b.10
1b.9
1b.8
1b.7
1b.6
1b.3
1b.2
1b.1
1b.0
September 2010
0 = Disable Jabber Interrupt
0 = Disable Receive Error Interrupt
0 = Disable Page Received Interrupt
0 = Disable Parallel Detect Fault Interrupt
0 = Disable Link Partner Acknowledge
Interrupt
0 = Disable Link Down Interrupt
0 = Disable Remote Fault Interrupt
0 = Disable Link Up Interrupt
0 = Jabber did not occurred
0 = Receive Error did not occurred
0 = Page Receive did not occurred
0 = Parallel Detect Fault did not occurred
0= Link Partner Acknowledge did not occurred
0= Link Down did not occurred
0= Remote Fault did not occurred
0= Link Up did not occurred
37
M9999-090910-1.4
Micrel, Inc.
KSZ8041NL/RNL
Register Description (Continued)
Address
Name
(1)
Description
Mode
Default
[00] =
RW
00
Register 1Eh – PHY Control 1
1e:15:14
LED mode
LED1 : Speed
LED0 : Link/Activity
[01] =
LED1 : Activity
LED0 : Link
[10], [11] = Reserved
1e.13
Polarity
0 = Polarity is not reversed
RO
1 = Polarity is reversed
1e.12
Reserved
1e.11
MDI/MDI-X
State
1e:10:8
Reserved
1e:7
Remote
loopback
1e:6:0
RO
0 = MDI
0
RO
1 = MDI-X
0 = Normal mode
RW
0
RW
1
RW
0
RW
0
RO
0
RW
0
1 = Remote (analog) loop back is enable
Reserved
Register 1Fh – PHY Control 2
1f:15
HP_MDIX
0 = Micrel Auto MDI/MDI-X mode
1 = HP Auto MDI/MDI-X mode
1f:14
MDI/MDI-X
Select
When Auto MDI/MDI-X is disabled,
0 = MDI Mode
Transmit on TX+/- (pins 7,6) and
Receive on RX+/- (pins 5,4)
1 = MDI-X Mode
Transmit on RX+/- (pins 5,4) and
Receive on TX+/- (pins 7,6)
1f:13
Pairswap
Disable
1 = Disable auto MDI/MDI-X
1f.12
Energy Detect
1 = Presence of signal on RX+/- analog wire
pair
0 = Enable auto MDI/MDI-X
0 = No signal detected on RX+/1f.11
Force Link
1 = Force link pass
0 = Normal link operation
This bit bypasses the control logic and allow
transmitter to send pattern even if there is no
link.
September 2010
38
M9999-090910-1.4
Micrel, Inc.
KSZ8041NL/RNL
Register Description (Continued)
(1)
Address
Name
Description
Mode
Default
1f.10
Power Saving
1 = Enable power saving
RW
0
RW
0
RW
1
RW
0
RO
0
RO
0
RO
000
RW
0
RW
0
0 = Disable power saving
If power saving mode is enabled and the cable
is disconnected, the RXC clock output (in MII
mode) is disabled. RXC clock is enabled after
the cable is connected and link is established.
1f.9
Interrupt Level
1 = Interrupt pin active high
0 = Interrupt pin active low
1f.8
Enable Jabber
1 = Enable jabber counter
0 = Disable jabber counter
AutoNegotiation
Complete
1 = Auto-negotiation process completed
1f.6
Enable Pause
(Flow Control)
1 = Flow control capable
1f.5
PHY Isolate
1 = PHY in isolate mode
1f.7
0 = Auto-negotiation process not completed
0 = No flow control capability
0 = PHY in normal operation
1f.4:2
Operation
Mode
Indication
[000] = still in auto-negotiation
[001] = 10Base-T half-duplex
[010] = 100Base-TX half-duplex
[011] = reserved
[101] = 10Base-T full-duplex
[110] = 100Base-TX full-duplex
[111] = reserved
1f.1
Enable SQE
test
1 = Enable SQE test
1f.0
Disable Data
Scrambling
1 = Disable scrambler
0 = Disable SQE test
0 = Enable scrambler
Note:
1.
RW = Read/Write.
RO = Read only.
SC = Self-cleared.
LH = Latch high.
LL = Latch low.
September 2010
39
M9999-090910-1.4
Micrel, Inc.
KSZ8041NL/RNL
Absolute Maximum Ratings(1)
Operating Ratings(2)
Supply Voltage
(VDDPLL_1.8) ............................................... -0.5V to +2.4V
(VDDIO_3.3, VDDA_3.3) ................................... -0.5V to +4.0V
Input Voltage (all inputs) ............................... -0.5V to +4.0V
Output Voltage (all outputs) .......................... -0.5V to +4.0V
Lead Temperature (soldering, 10sec.)....................... 260°C
Storage Temperature (Ts) ..........................-55°C to +150°C
ESD Rating(3) .................................................................. 6kV
Supply Voltage
(VDDIO_3.3, VDDA_3.3) .......................... +3.135V to +3.465V
Ambient Temperature
(TA , Commercial)...................................... 0°C to +70°C
(TA , Industrial) .......................................-40°C to +85°C
(TA , AM Automotive Qualified) .............-40°C to +85°C
Maximum Junction Temperature (TJ Max) ................. 125°C
Maximum Case Temperature (TC Max)...................... 150°C
Thermal Resistance (θJA) .........................................34°C/W
Thermal Resistance (θJC) ...........................................6°C/W
Electrical Characteristics(4)
Symbol
Parameter
Condition
Min
Typ
Max
Units
(5)
Supply Current
IDD1
100Base-TX
Chip only (no transformer);
53.0
mA
38.0
mA
Full-duplex traffic @ 100% utilization
IDD2
10Base-T
Chip only (no transformer);
IDD3
Power Saving Mode
Ethernet cable disconnected (reg. 1F.10 = 1)
32.0
mA
IDD4
Power Down Mode
Software power down (reg. 0.11 = 1)
4.0
mA
Full-duplex traffic @ 100% utilization
TTL Inputs
VIH
Input High Voltage
VIL
Input Low Voltage
IIN
Input Current
2.0
VIN = GND ~ VDDIO
V
-10
0.8
V
10
µA
TTL Outputs
VOH
Output High Voltage
IOH = -4mA
VOL
Output Low Voltage
IOL = 4mA
|Ioz|
Output Tri-State Leakage
2.4
V
0.4
V
10
µA
LED Outputs
ILED
Output Drive Current
Each LED pin (LED0, LED1)
8
mA
100Base-TX Transmit (measured differentially after 1:1 transformer)
VO
Peak Differential Output Voltage
100Ω termination across differential output
VIMB
Output Voltage Imbalance
100Ω termination across differential output
tr, tf
0.95
V
2
%
Rise/Fall Time
3
5
ns
Rise/Fall Time Imbalance
0
0.5
ns
+ 0.25
ns
5
%
Duty Cycle Distortion
Overshoot
VSET
1.05
0.65
Reference Voltage of ISET
Output Jitter
September 2010
0.7
Peak-to-peak
40
V
1.4
ns
M9999-090910-1.4
Micrel, Inc.
KSZ8041NL/RNL
Electrical Characteristics(4) (Continued)
Symbol
Parameter
Condition
Min
Typ
Max
Units
2.8
V
3.5
ns
10Base-T Transmit (measured differentially after 1:1 transformer)
VP
tr, tf
Peak Differential Output Voltage
100Ω termination across differential output
Jitter Added
Peak-to-peak
2.2
Rise/Fall Time
25
ns
400
mV
10Base-T Receive
VSQ
Squelch Threshold
5MHz square wave
Notes:
1. Exceeding the absolute maximum rating may damage the device. Stresses greater than the absolute maximum rating may cause permanent
damage to the device. Operation of the device at these or any other conditions above those specified in the operating sections of this specification
is not implied. Maximum conditions for extended periods may affect reliability.
2. The device is not guaranteed to function outside its operating rating.
3. Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5k in series with 100pF.
4. TA = 25°C. Specification for packaged product only.
5. Current consumption is for the single 3.3V supply KSZ8041NL/RNL device only, and includes the 1.8V supply voltage (VDDPLL_1.8) that is provided by
the KSZ8041NL/RNL. The PHY port’s transformer consumes an additional 45mA @ 3.3V for 100Base-TX and 70mA @ 3.3V for 10Base-T.
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KSZ8041NL/RNL
Timing Diagrams
MII SQE Timing (10Base-T)
Figure 9. MII SQE Timing (10Base-T)
Timing Parameter
Description
Min
Typ
Max
Unit
tP
TXC period
400
ns
tWL
TXC pulse width low
200
ns
tWH
TXC pulse width high
200
ns
tSQE
COL (SQE) delay after TXEN de-asserted
2.5
us
tSQEP
COL (SQE) pulse duration
1.0
us
Table 7. MII SQE Timing (10Base-T) Parameters
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MII Transmit Timing (10Base-T)
Figure 10. MII Transmit Timing (10Base-T)
Timing Parameter
Description
Min
Typ
Max
Unit
tP
TXC period
400
ns
tWL
TXC pulse width low
200
ns
tWH
TXC pulse width high
200
ns
tSU1
TXD[3:0] setup to rising edge of TXC
10
ns
tSU2
TXEN setup to rising edge of TXC
10
ns
tHD1
TXD[3:0] hold from rising edge of TXC
0
ns
tHD2
TXEN hold from rising edge of TXC
0
ns
tCRS1
TXEN high to CRS asserted latency
160
ns
tCRS2
TXEN low to CRS de-asserted latency
510
ns
Table 8. MII Transmit Timing (10Base-T) Parameters
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KSZ8041NL/RNL
MII Receive Timing (10Base-T)
Figure 11. MII Receive Timing (10Base-T)
Timing Parameter
Description
tP
RXC period
Min
Typ
Max
400
Unit
ns
tWL
RXC pulse width low
200
ns
tWH
RXC pulse width high
200
ns
tOD
(RXD[3:0], RXER, RXDV) output
delay from rising edge of RXC
tRLAT
CRS to (RXD[3:0], RXER, RXDV)
latency
182
225
6.5
ns
us
Table 9. MII Receive Timing (10Base-T) Parameters
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KSZ8041NL/RNL
MII Transmit Timing (100Base-TX)
Figure 12. MII Transmit Timing (100Base-TX)
Timing Parameter
Description
Min
Typ
Max
Unit
tP
TXC period
40
ns
tWL
TXC pulse width low
20
ns
tWH
TXC pulse width high
20
ns
tSU1
TXD[3:0] setup to rising edge of TXC
10
ns
tSU2
TXEN setup to rising edge of TXC
10
ns
tHD1
TXD[3:0] hold from rising edge of TXC
0
ns
tHD2
TXEN hold from rising edge of TXC
0
ns
tCRS1
TXEN high to CRS asserted latency
34
ns
tCRS2
TXEN low to CRS de-asserted latency
33
ns
Table 10. MII Transmit Timing (100Base-TX) Parameters
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KSZ8041NL/RNL
MII Receive Timing (100Base-TX)
Figure 13. MII Receive Timing (100Base-TX)
Timing Parameter
Description
tP
RXC period
Min
Typ
40
Max
ns
tWL
RXC pulse width low
20
ns
20
Unit
tWH
RXC pulse width high
tOD
(RXD[3:0], RXER, RXDV) output
delay from rising edge of RXC
tRLAT
CRS to RXDV latency
140
ns
CRS to RXD[3:0] latency
52
ns
CRS to RXER latency
60
ns
19
ns
25
ns
Table 11. MII Receive Timing (100Base-TX) Parameters
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KSZ8041NL/RNL
RMII Timing
Figure 14. RMII Timing – Data Received from RMII
Figure 15. RMII Timing – Data Input to RMII
Timing Parameter
Description
tcyc
Clock cycle
Min
Typ
Max
t1
Setup time
4
ns
t2
Hold time
2
ns
tod
Output delay
3
20
Unit
ns
9
ns
Table 12. RMII Timing Parameters – KSZ8041NL
Timing Parameter
Description
tcyc
Clock cycle
t1
Setup time
Min
Typ
Max
20
ns
4
t2
Hold time
1
tod
Output delay
9
Unit
ns
ns
11
13
ns
Table 13. RMII Timing Parameters – KSZ8041RNL
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KSZ8041NL/RNL
Auto-Negotiation Timing
Figure 16. Auto-Negotiation Fast Link Pulse (FLP) Timing
Timing Parameter
Description
Min
Typ
Max
Units
tBTB
FLP Burst to FLP Burst
8
16
24
ms
tFLPW
FLP Burst width
tPW
Clock/Data Pulse width
tCTD
Clock Pulse to Data Pulse
55.5
64
69.5
µs
tCTC
Clock Pulse to Clock Pulse
111
128
139
µs
Number of Clock/Data Pulse per
FLP Burst
17
2
ms
100
ns
33
Table 14. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters
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KSZ8041NL/RNL
MDC/MDIO Timing
Figure 17. MDC/MDIO Timing
Timing Parameter
Description
Min
tP
MDC period
t1MD1
MDIO (PHY input) setup to rising edge of MDC
10
tMD2
MDIO (PHY input) hold from rising edge of MDC
4
tMD3
MDIO (PHY output) delay from rising edge of MDC
Typ
400
Max
Unit
ns
ns
ns
222
ns
Table 15. MDC/MDIO Timing Parameters
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KSZ8041NL/RNL
Reset Timing
The KSZ8041NL/RNL reset timing requirement is summarized in the following figure and table.
Figure 18. Reset Timing
Parameter
Description
Min
Max
Units
tsr
Stable supply voltage to reset high
10
ms
tcs
Configuration setup time
5
ns
tch
Configuration hold time
5
ns
trc
Reset to strap-in pin output
6
ns
Table 16. Reset Timing Parameters
After the de-assertion of reset, it is recommended to wait a minimum of 100 us before starting programming on the MIIM
(MDC/MDIO) Interface.
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KSZ8041NL/RNL
Reset Circuit
The reset circuit in Figure 19 is recommended for powering up the KSZ8041NL/RNL if reset is triggered by the power
supply.
3.3V
D1: 1N4148
D1
KSZ8041NL/RNL
R 10K
RST#
C 10uF
Figure 19. Recommended Reset Circuit
The reset circuit in Figure 20 is recommended for applications where reset is driven by another device (e.g., CPU or
FPGA). At power-on-reset, R, C and D1 provide the necessary ramp rise time to reset the KSZ8041NL/RNL device. The
RST_OUT_n from CPU/FPGA provides the warm reset after power up.
3.3V
KSZ8041NL/RNL
D1
R 10K
CPU/FPGA
RST#
RST_OUT_n
D2
C 10uF
D1, D2: 1N4148
Figure 20. Recommended Reset Circuit for interfacing with CPU/FPGA Reset Output.
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KSZ8041NL/RNL
Reference Circuits for LED Strapping Pins
The Figure 21 shows the reference circuits for pull-up, float and pull-down on the LED1 and LED0 strapping pins.
3.3V
Pull-up
KSZ8041NL/RNL
LED pin
3.3V
Float
KSZ8041NL/RNL
LED pin
3.3V
Pull-down
KSZ8041NL/RNL
LED pin
Figure 21. Reference Circuits for LED Strapping Pins
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Selection of Isolation Transformer
A 1:1 isolation transformer is required at the line interface. An isolation transformer with integrated common-mode chokes
is recommended for exceeding FCC requirements.
The Table 17 gives recommended transformer characteristics.
Parameter
Value
Turns ratio
1 CT : 1 CT
Test Condition
Open-circuit inductance (min.)
350μH
100mV, 100kHz, 8mA
Leakage inductance (max.)
0.4μH
1MHz (min.)
Inter-winding capacitance (typ.)
12pF
D.C. resistance (typ.)
0.9Ω
Insertion loss (max.)
-1.0dB
HIPOT (min.)
1500Vrms
0MHz – 65MHz
Table 17. Transformer Selection Criteria
Magnetic Manufacturer
Part Number
Auto MDI-X
Number of Port
Bel Fuse
S558-5999-U7
Yes
1
Bel Fuse (Mag Jack)
SI-46001
Yes
1
Bel Fuse (Mag Jack)
SI-50170
Yes
1
Delta
LF8505
Yes
1
LanKom
LF-H41S
Yes
1
Pulse
H1102
Yes
1
Pulse (low cost)
H1260
Yes
1
Transpower
HB726
Yes
1
TDK (Mag Jack)
TLA-6T718
Yes
1
Table 18. Qualified Single Port Magnetics
Selection of Reference Crystal
Characteristics
Value
Units
Frequency
25
MHz
Frequency tolerance (max)
±50
ppm
Load capacitance
20
pF
Series resistance
40
Ω
Table 19. Typical Reference Crystal Characteristics
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Package Information
32-Pin (5mm x 5mm) MLF® Package
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its
use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product
can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical
implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user.
A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to
fully indemnify Micrel for any damages resulting from such use or sale.
© 2006 Micrel, Incorporated.
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