CMOS Latched 8-/16-Channel Analog Multiplexers ADG526A/ADG527A FEATURES FUNCTIONAL BLOCK DIAGRAMS 44 V supply maximum rating VSS to VDD analog signal range Single- or dual-supply specifications Wide supply ranges (10.8 V to 16.5 V) Microprocessor compatible (100 ns WR pulse) Extended plastic temperature range (−40°C to +85°C) Low leakage (20 pA typical) Low power dissipation (28 mW maximum) Available in PDIP, CERDIP, SOIC, and PLCC packages Superior alternative to DG526 and DG527 ADG526A S1 D S16 DECODER/ LATCHES 01532-001 WR A0 A1 A2 A3 EN RS Figure 1. ADG526A APPLICATIONS ADG527A Data acquisition systems Communication systems Automatic test equipment Microprocessor controlled systems S1A DA S8A S1B DB S8B The ADG526A and ADG527A are CMOS monolithic analog multiplexers with 16 single channels and dual 8 channels, respectively. On-chip latches facilitate microprocessor interfacing. WR The ADG526A switches one of 16 inputs to a common output, depending on the state of four binary addresses and an enable input. The ADG527A switches one of eight differential inputs to a common differential output, depending on the state of three binary addresses and an enable input. Both devices have TTL and 5 V CMOS logic-compatible digital inputs. The ADG526A and ADG527A are designed on an enhanced LC2MOS process that gives an increased signal capability of VSS to VDD and enables operation over a wide range of supply voltages. The devices can comfortably operate anywhere in the 10.8 V to 16.5 V single- or dual-supply range. These multiplexers also feature high switching speeds and low RON. DECODER/ LATCHES A0 A1 A2 EN RS 01532-002 GENERAL DESCRIPTION Figure 2. ADG527A PRODUCT HIGHLIGHTS 1. Single- or Dual-Supply Specifications with a Wide Tolerance. The devices are specified in the 10.8 V to 16.5 V range for both single and dual supplies. 2. Easily Interfaced. The ADG526A and ADG527A can be easily interfaced with microprocessors. The WR signal latches the state of the address control lines and the enable line. The RS signal clears both the address and enable data in the latches, resulting in no output (all switches off). RS can be tied to the microprocessor reset pin. 3. Extended Signal Range. The enhanced LC2MOS processing results in a high breakdown and an increased analog signal range from VSS to VDD. 4. Break-Before-Make Switching. Switches are guaranteed break-before-make so that input signals are protected against momentary shorting. 5. Low Leakage. Leakage currents in the range of 20 pA make these multiplexers suitable for high precision circuits. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved. ADG526A/ADG527A TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................7 Applications ....................................................................................... 1 Pin Configurations and Function Descriptions ............................8 General Description ......................................................................... 1 Typical Performance Characteristics ........................................... 11 Functional Block Diagrams ............................................................. 1 Terminology .................................................................................... 12 Product Highlights ........................................................................... 1 Timing .............................................................................................. 13 Revision History ............................................................................... 2 Test Circuits ..................................................................................... 14 Specifications..................................................................................... 3 Outline Dimensions ....................................................................... 17 Dual Supply ................................................................................... 3 Ordering Guide .......................................................................... 19 Single Supply ................................................................................. 5 Absolute Maximum Ratings............................................................ 7 REVISION HISTORY 6/08—Rev. B to Rev. C. 2/02—Rev. A to Rev. B. Updated Format .................................................................. Universal ADG526A LCCC Package Removed ............................... Universal Changes to Features.......................................................................... 1 Added Applications Section ............................................................ 1 Changes to Absolute Maximum Ratings ....................................... 7 Added Table 4, Renumbered Sequentially .................................... 8 Added Table 5.................................................................................... 9 Changes to Figure 7 and Figure 8 ................................................. 11 Updated Outline Dimensions ....................................................... 17 Changes to Ordering Guide .......................................................... 19 Edits to Specifications Table, Dual Supply .....................................2 Edits to Specifications Table, Single Supply ...................................3 Edits to Ordering Guide ...................................................................4 Removal of one Pin Configuration and Diagram .........................6 Rev. C | Page 2 of 20 ADG526A/ADG527A SPECIFICATIONS DUAL SUPPLY VDD = 10.8 V to 16.5 V, VSS = −10.8 V to −16.5 V, unless otherwise noted. Table 1. Parameter ANALOG SWITCH Analog Signal Range RON ADG526A/ADG527A K Version B Version 25°C −40°C to +85°C 25°C −40°C to +85°C ADG526A T Version 25°C −55°C to +125°C Unit VSS VDD 280 VSS VDD VSS VDD 280 VSS VDD 450 300 600 400 450 600 VSS VDD 280 VSS VDD 450 300 600 400 300 RON Drift RON Match IS (Off), Off Input Leakage ID (Off), Off Output Leakage ADG526A ADG527A ID (On), On Channel Leakage ADG526A ADG527A IDIFF, Differential Off Output Leakage (ADG527A Only) DIGITAL CONTROL VINH, Input High Voltage VINL, Input Low Voltage IINL or IINH CIN, Digital Input Capacitance DYNAMIC CHARACTERISTICS 1 tTRANSITION tOPEN tON (EN, WR) tOFF (EN, RS) tW , Write Pulse Width tS, Address Enable Setup Time tH, Address Enable Hold Time tRS, Reset Pulse Width 0.6 5 0.02 0.6 5 0.02 1 0.04 50 1 1 0.04 200 100 1 1 200 100 25 0.6 5 0.02 1 0.04 50 1 1 0.04 200 100 1 1 200 100 25 2.4 0.8 1 400 50 1 200 0.04 Ω max 200 nA max nA max nA typ nA max nA max nA max 8 8 8 200 200 200 ns typ 400 10 400 400 120 100 300 50 25 200 300 200 300 100 400 10 400 400 120 100 2.4 0.8 1 nA max nA typ V min V max μA max pF max 300 50 25 200 300 200 300 100 2.4 0.8 1 Ω max Ω max %/°C typ % typ nA typ 1 0.04 1 V min V max Ω typ 300 50 25 200 300 200 300 100 400 400 130 100 ns max ns typ ns min ns typ ns max ns typ ns max ns min ns min 10 400 Comments −10 V ≤ VS ≤ +10 V, IDS = 1 mA; see Figure 15 VDD = +15 V (±10%), VSS = −15 V (±10%) VDD = +15 V (±5%), VSS = −15 V (±5%) −10 V ≤ VS ≤ +10 V, IDS = 1 mA −10 V ≤ VS ≤ +10 V, IDS = 1 mA V1 = ±10 V, V2 = 10 V; see Figure 16 V1 = ±10 V, V2 = 10 V; see Figure 17 V1 = ±10 V, V2 = 10 V; see Figure 18 V1 = ±10 V, V2 = 10 V; see Figure 19 VIN = 0 to VDD V1 = ±10 V, V2 = 10 V; see Figure 20 See Figure 21 See Figure 22 and Figure 23 See Figure 22 and Figure 24 See Figure 13 See Figure 13 10 10 10 ns min See Figure 13 100 100 100 ns min See Figure 14 Rev. C | Page 3 of 20 ADG526A/ADG527A Parameter Off Isolation CS (Off) CD (Off) ADG526A ADG527A QINJ, Charge Injection POWER SUPPLY IDD ADG526A/ADG527A K Version B Version 25°C −40°C to +85°C 25°C −40°C to +85°C 68 68 ADG526A T Version 25°C −55°C to +125°C Unit 68 dB typ 50 5 50 5 50 5 dB min pF typ VS = 7 V rms, f = 100 kHz VEN = 0.8 V 44 22 4 44 22 4 44 pF typ pF typ pC typ VEN = 0.8 V 0.6 1.5 20 0.2 10 0.6 mA typ mA max μA typ mA max mW typ mW max VIN = VINL or VINH 0.6 1.5 ISS 20 0.2 Power Dissipation 10 28 1 4 1.5 20 0.2 10 28 28 Sample tested at 25°C to ensure compliance. Rev. C | Page 4 of 20 Comments VEN = 0.8 V, RL = 1 kΩ, CL = 15 pF,VS = 7 V rms, f = 100 kHz RS = 0 Ω, VS = 0 V; see Figure 25 VIN = VINL or VINH ADG526A/ADG527A SINGLE SUPPLY VDD = 10.8 V to 16.5 V, VSS = GND to 0 V, unless otherwise noted. Table 2. ADG526A/ADG527A K Version B Version 25°C −40°C to +85°C 25°C −40°C to +85°C 25°C VSS VDD VSS VDD 500 VSS VDD RON VSS VDD 500 700 0.6 1000 700 0.6 1000 RON Drift RON Match 5 5 5 % typ IS (Off), Off Input Leakage 0.02 0.02 0.02 nA typ Parameter ANALOG SWITCH Analog Signal Range ID (Off), Off Output Leakage ADG526A ADG527A ID (On), On Channel Leakage ADG526A ADG527A IDIFF, Differential Off Output Leakage (ADG527A Only) DIGITAL CONTROL VINH, Input High Voltage VINL, Input Low Voltage IINL or IINH CIN, Digital Input Capacitance DYNAMIC CHARACTERISTICS 1 tTRANSITION tOPEN tON (EN, WR) tOFF (EN, RS) tW Write Pulse Width tS Address Enable Setup Time tH Address Enable Hold Time tRS Reset Pulse Width Off Isolation 1 0.04 50 1 1 0.04 200 100 1 1 200 100 25 VSS VDD 500 VSS VDD 700 0.6 1000 1 0.04 50 1 1 0.04 200 100 1 1 200 100 25 2.4 0.8 1 ADG526A T Version −55°C to +125°C 1 0.04 50 1 200 0.04 1 Ω max %/°C typ nA max nA typ nA max nA max nA typ nA max nA max nA max 8 8 8 300 300 300 ns typ 600 10 600 600 120 100 450 50 25 250 450 250 450 100 10 600 10 600 600 120 100 2.4 0.8 1 V min V max Ω typ V min V max μA max pF max 450 50 25 250 450 250 450 100 2.4 0.8 1 200 Unit 450 50 25 250 450 250 450 100 10 100 100 600 0 V ≤ VS ≤ 10 V, IDS = 0.5 mA; see Figure 15 0 V ≤ VS ≤ 10 V, IDS = 0.5 mA 0 V ≤ VS ≤ 10 V, IDS = 0.5 mA V1 = 10 V/0 V, V2 = 0 V/ 10 V; see Figure 16 V1 = 10 V/0 V, V2 = 0 V/ 10 V; see Figure 17 V1 = 10 V/0 V, V2 = 0 V/ 10 V; see Figure 18 V1 = 10 V/0 V, V2 = 0 V/ 10 V; see Figure 19 VIN = 0 to VDD V1 = 10 V/0 V, V2 = 0 V/ 10 V; see Figure 20 600 130 100 ns max ns typ ns min ns typ ns max ns typ ns max ns min ns min 10 ns min See Figure 13 100 See Figure 14 VEN = 0.8 V, RL = 1 kΩ, CL = 15 pF VS = 3.5 V rms, f = 100 kHz 10 600 68 68 68 ns min dB typ 50 50 50 dB min Rev. C | Page 5 of 20 Comments See Figure 21 See Figure 22 and Figure 23 See Figure 22 and Figure 24 See Figure 13 See Figure 13 ADG526A/ADG527A ADG526A/ADG527A K Version B Version 25°C −40°C to +85°C 25°C −40°C to +85°C 5 5 Parameter CS (Off) CD (Off) ADG526A ADG527A QINJ, Charge Injection 44 22 4 POWER SUPPLY IDD 0.6 44 22 4 Power Dissipation 11 4 0.6 1.5 11 25 1 44 0.6 1.5 25°C 5 ADG526A T Version −55°C to +125°C 1.5 11 25 Sample tested at 25°C to ensure compliance. Rev. C | Page 6 of 20 25 Unit pF typ Comments VEN = 0.8 V pF typ pF typ pC typ VEN = 0.8 V mA typ mA max mW typ mW max RS = 0 Ω, VS = 0 V; see Figure 25 VIN = VINL or VINH ADG526A/ADG527A ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 3. Parameter VDD to VSS VDD to GND VSS to GND Analog Inputs1 Voltage at Sx or Dx Pins Continuous Current, Sx or Dx Pins Pulsed Current, Sx or Dx Pins 1 ms Duration, 10% Duty Cycle Digital Inputs1 Voltage at A, EN, WR, RS Power Dissipation (Any Package) Up to 75°C Derates Above 75°C Operating Temperature Range Commercial (K Version) Industrial (B Version) Storage Temperature Range Lead Temperature (Soldering, 10 sec) 1 Rating 44 V 25 V −25 V VSS − 2 V to VDD + 2 V or 20 mA, whichever occurs first 20 mA ESD CAUTION 40 mA VSS − 4 V to VDD + 4 V or 20 mA, whichever occurs first 470 mW 6 mW/°C −40°C to +85°C −40°C to +85°C −65°C to +150°C 300°C Overvoltage at A, EN, WR, RS, Sx, or Dx pins are clamped by diodes. Limit current to the maximum rating in Table 3. Rev. C | Page 7 of 20 ADG526A/ADG527A D VSS S8 27 26 PIN 1 IDENTFIER 25 S7 S14 6 24 S6 S13 7 23 S5 22 S4 ADG526A S12 8 TOP VIEW (Not to Scale) S11 9 S11 9 20 S2 S10 10 S10 10 19 S1 S09 11 S9 11 18 EN 12 GND 12 17 A0 WR 13 16 A1 GND 21 S3 A3 14 15 A2 14 15 16 17 18 NC = NO CONNECT S3 20 S2 19 S1 01532-005 NC = NO CONNECT 13 21 01532-007 VDD 28 S15 5 24 S6 TOP VIEW S14 6 (Not to Scale) 23 S5 S13 7 22 S4 S12 8 1 EN ADG526A 2 A0 S15 5 3 A1 25 S7 NC S16 4 4 A2 26 S8 A3 27 VSS RS 3 RS 28 D NC 2 WR VDD 1 S16 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 4. ADG526A PLCC Pin Configuration Figure 3. ADG526A PDIP, SOIC, and CERDIP Pin Configuration Table 4. ADG526A Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Mnemonic VDD NC RS S16 S15 S14 S13 S12 S11 S10 S9 GND WR A3 A2 A1 A0 EN S1 S2 S3 S4 S5 S6 S7 S8 VSS D Description Most Positive Power Supply Potential. No Connect. Reset. The RS signal clears both the address and enable data in the latches resulting in no output (all switches off ). Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Ground (0 V) Reference. Write. The WR signal latches the state of the address control lines and the enable line. Logic Control Inputs. Selects which source terminal is connected to the drain (D). Logic Control Inputs. Selects which source terminal is connected to the drain (D). Logic Control Inputs. Selects which source terminal is connected to the drain (D). Logic control inputs. Selects which source terminal is connected to the drain (D). Enable. Active high logic control input. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Most Negative Power Supply Potential. Drain Terminal. This pin can be an input or output. Rev. C | Page 8 of 20 28 DA RS DB VDD DA VSS S8A DB 2 27 VSS 4 3 2 1 28 27 26 RS 3 26 S8A S8B 4 25 S7A S7B 5 25 S7A S7B 5 24 S6A S6B 6 24 S6A 23 S5A S5B 7 23 S5A 22 S4A S6B 6 S5B 7 ADG527A TOP VIEW (Not to Scale) 22 S4A PIN 1 IDENTFIER ADG527A S4B 8 TOP VIEW (Not to Scale) 20 S2A S1B 11 18 EN S1B 11 19 S1A GND 12 17 A0 WR 13 16 A1 NC 14 15 A2 GND 01532-006 NC = NO CONNECT 12 13 14 15 16 17 18 EN S2B 10 A0 S3A 19 S1A A1 21 S2B 10 S3B 9 A2 20 S2A NC 21 S3A S3B 9 WR S4B 8 NC = NO CONNECT Figure 5. ADG527A PDIP, SOIC Pin Configuration 01532-008 VDD 1 S8B ADG526A/ADG527A Figure 6. ADG527A PLCC Pin Configuration Table 5. ADG527A Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Mnemonic VDD DB RS S8B S7B S6B S5B S4B S3B S2B S1B GND WR NC A2 A1 A0 EN S1A S2A S3A S4A S5A S6A S7A S8A VSS DA Description Most Positive Power Supply Potential. Drain Terminal. This pin can be an input or output. Reset. The RS signal clears both the address and enable data in the latches resulting in no output (all switches off). Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Ground (0 V) Reference. Write. The WR signal latches the state of the address control lines and the enable line. No Connect. Logic Control Inputs. Selects which source terminal is connected to the drain (D). Logic Control Inputs. Selects which source terminal is connected to the drain (D). Logic Control Inputs. Selects which source terminal is connected to the drain (D). Enable. Active high logic control input. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Most Negative Power Supply Potential. Drain Terminal. This pin can be an input or output. Rev. C | Page 9 of 20 ADG526A/ADG527A Table 6. ADG526A Truth Table1 A3 A2 A1 A0 EN X X X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 X X X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X X X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X X X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X X 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 WR RS ON SWITCH X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Retains previous switch condition None (address and enable latches cleared) None 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 X = don’t care. Table 7. ADG527A Truth Table1 A2 A1 A0 EN X X X 0 0 0 0 1 1 1 1 X X X 0 0 1 1 0 0 1 1 X X X 0 1 0 1 0 1 0 1 X X 0 1 1 1 1 1 1 1 1 1 WR RS ON SWITCH PAIR X 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 Retains previous switch condition None (address and enable latches cleared) None 1 2 3 4 5 6 7 8 X = don’t care. Rev. C | Page 10 of 20 ADG526A/ADG527A TYPICAL PERFORMANCE CHARACTERISTICS The multiplexers are guaranteed functional with reduced single or dual supplies down to 4.5 V. 700 1.9 600 VDD = 10.8V VSS = 0V 1.8 TRIGGER LEVEL (V) RON (Ω) 500 VDD = 15V VSS = 0V 400 300 200 1.7 1.6 1.5 –15 –10 –5 0 5 10 15 20 VD (VS) (V) 01532-009 0 –20 Figure 7. RON as a Function of VD (VS): Single-Supply Voltage, TA = 25°C 5 9 10 11 12 13 14 15 Figure 10. Trigger Levels vs. Power Supply Voltage, Dual or Single Supply, TA = 25°C 700 VDD = +5V VSS = –5V 500 600 tTRANSITION (ns) 400 300 VDD = +10.8V VSS = –10.8V 200 500 SINGLE SUPPLY 400 300 VDD = +15V VSS = –15V 0 –20 –15 –10 –5 0 DUAL SUPPLY 200 5 10 15 20 VD (VS) (V) 100 01532-010 100 Figure 8. RON as a Function of VD (VS): Dual-Supply Voltage, TA = 25°C 5 6 7 8 9 10 11 12 13 14 15 SUPPLY VOLTAGE (V) 01532-013 RON (Ω) 8 800 600 Figure 11. tTRANSITION vs. Supply Voltage: Dual and Single Supplies, TA = 25°C (Note: For VDD and VSS <10 V; V1 = VDD/VSS, V2 = VSS/VDD; See Figure 20) 1.0 VDD = +16.5V VSS = –16.5V 0.8 10 ID (ON) ID (OFF) IDD (mA) LEAKAGE CURRENT (nA) 7 SUPPLY VOLTAGE (V) 700 100 6 01532-012 100 1 0.6 0.4 IS (OFF) 0.1 25 35 45 55 65 75 85 TEMPERATURE (°C) 95 105 115 125 01532-011 0.01 Figure 9. Leakage Current as a Function of Temperature (Leakage Currents Reduce as the Supply Voltages Reduce) Rev. C | Page 11 of 20 0 5 6 7 8 9 10 11 12 13 14 15 16 17 SUPPLY VOLTAGE (V) Figure 12. IDD vs. Supply Voltage: Dual or Single Supply, TA = 25°C 01532-014 0.2 ADG526A/ADG527A TERMINOLOGY tOFF (EN) Delay time between the 50% and 10% points of the digital input and switch off condition. RON Ohmic resistance between Terminal D and Terminal S. RON Match Difference between the RON of any two channels. tTRANSITION Delay time between the 50% and 90% points of the digital inputs and switch on condition when switching from one address state to another. RON Drift Change in RON vs. temperature. IS (Off) Source terminal leakage current when the switch is off. tOPEN Off time measured between 50% points of both switches when switching from one address state to another. ID (Off) Drain terminal leakage current when the switch is off. ID (On) Leakage current that flows from the closed switch into the body. VS (VD) Analog voltage on Terminal S or Terminal D. VINL Maximum input voltage for Logic 0. VINH Minimum input voltage for Logic 1. IINL (IINH) Input current of the digital input. CS (Off) Channel input capacitance for off condition. VDD Most positive voltage supply. CD (Off) Channel output capacitance for off condition. VSS Most negative voltage supply. CIN Digital input capacitance. tON (EN) Delay time between the 50% and 90% points of the digital input and switch on condition. IDD Positive supply current. ISS Negative supply current. Rev. C | Page 12 of 20 ADG526A/ADG527A TIMING Figure 13 shows the timing sequence for latching the switch address and enable inputs. The latches are level sensitive; therefore, while WR is held low, the latches are transparent and the switches respond to the address and enable inputs. This input data is latched on the rising edge of WR. Figure 14 shows the reset pulse width, tRS, and reset turn-off time, tOFF (RS). Note that all digital input signal rise and fall times are measured from 10% to 90% of 3 V, tR = tF = 20 ns. 3V 3V 0V tW tS 3V EN, A0, A1, A2, (A3) 0V 1.5V tRS tOFF (RS) tH 2.0V 0.8V VO SWITCH OUTPUT 0V Figure 13. Timing Sequence 0.8V Figure 14. Reset Pulse Rev. C | Page 13 of 20 01532-004 0V 1.5V 01532-003 WR RS ADG526A/ADG527A TEST CIRCUITS IDS VDD VSS V1 VDD VSS D D V1 IDS V1 GND Figure 15. RON VDD 2.4V VDD VSS VDD VSS ADG527A EN 0.8V DA VSS D A EN GND V2 V1 VSS VDD VSS Figure 19. IDIFF D GND EN A ID (OFF) V2 01532-017 V1 0.8V A GND IDIFF = IDA (OFF) – IDB (OFF) Figure 16. IS (Off) VDD A V2 0.8V 01532-016 V1 ID (ON) V2 DB IS (OFF) A Figure 18. ID (On) VSS VDD EN 01532-018 RON = 01532-015 VS Figure 17. ID (Off) Rev. C | Page 14 of 20 01532-019 S ADG526A/ADG527A VDD VSS VDD VSS ADG526A* 3V 0V A3 ADDRESS DRIVE (VIN) 50% S1 A2 VIN 50Ω A1 A0 S16 90% D tTRANSITION EN RS GND WR V2 OUTPUT 1MΩ 35pF 01532-020 tTRANSITION 2.4V OUTPUT 90% V1 S2 TO S15 *SIMILAR CONNECTION FOR ADG527A. Figure 20. Switching Time of Multiplexer, tTRANSITION VDD VSS VDD VSS ADG526A* A3 ADDRESS DRIVE (VIN) 0V VIN 50Ω S2 TO S15 A1 A0 50% S16 D OUTPUT 2.4V 5V S1 A2 3V EN RS GND WR OUTPUT 1kΩ 35pF 01532-021 tOPEN *SIMILAR CONNECTION FOR ADG527A. Figure 21. Break-Before-Make Delay, tOPEN 3V 2.4V 50% ENABLE DRIVE (VIN) RS VDD VSS VDD VSS ADG526A* A3 A2 0V 5V S1 S2 TO S16 A1 A0 OUTPUT 10% EN VIN tON (EN) D OUTPUT 50Ω GND tOFF (EN) *SIMILAR CONNECTION FOR ADG527A. Figure 22. Enable Delay, tON (EN) tOFF (EN) Rev. C | Page 15 of 20 WR 1kΩ 35pF 01532-022 90% ADG526A/ADG527A EN 2.4V 50% VSS VDD VSS ADG526A* (WR) DRIVE (VIN) 5V S1 A3 A2 A1 A0 3V 0V VDD S2 TO S16 RS D WR OUTPUT VIN 20% 50Ω OUTPUT 1kΩ GND 35pF NOTE: DEVICE MUST BE RESET PRIOR TO APPLYING WR PULSE. 01532-023 tON (WR) *SIMILAR CONNECTION FOR ADG527A. Figure 23. Write Turn-On Time, tON (WR) EN 2.4V 3V 0V 50% VSS VDD VSS ADG526A* 5V S1 A3 A2 A1 A0 RS DRIVE (VIN) 80% VDD S2 TO S16 WR OUTPUT tOFF (RS) D RS VIN 50Ω OUTPUT 1kΩ GND 35pF 01532-024 NOTE: DEVICE WR MUST PULSE LOW PRIOR TO APPLYING RS PULSE. *SIMILAR CONNECTION FOR ADG527A. Figure 24. Reset Turn-Off, tOFF (RS) A3 A2 A1 A0 3V RS VO ΔVO VDD VSS ADG526A* D CL 1nF EN VIN 2.4V RS S1 VS 0V VSS VO 50Ω GND QINJ = CL × ΔVO WR *SIMILAR CONNECTION FOR ADG527A. Figure 25. Charge Injection Rev. C | Page 16 of 20 01532-025 VIN VDD ADG526A/ADG527A OUTLINE DIMENSIONS 0.005 (0.13) MIN 0.100 (2.54) MAX 28 15 0.610 (15.49) 0.500 (12.70) 1 14 PIN 1 0.620 (15.75) 0.590 (14.99) 0.015 (0.38) MIN 1.490 (37.85) MAX 0.150 (3.81) MIN 0.200 (5.08) 0.125 (3.18) 0.100 (2.54) BSC 0.026 (0.66) 0.014 (0.36) 0.070 (1.78) SEATING 0.030 (0.76) PLANE 0.018 (0.46) 0.008 (0.20) 15° 0° CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 030106-A 0.225(5.72) MAX Figure 26. 28-Lead Ceramic Dual In-Line Package [CERDIP] (Q-28) Dimensions shown in inches and (millimeters) 1.565 (39.75) 1.380 (35.05) 28 15 0.580 (14.73) 0.485 (12.31) 1 14 0.625 (15.88) 0.600 (15.24) 0.100 (2.54) BSC 0.250 (6.35) MAX 0.195 (4.95) 0.125 (3.17) 0.015 (0.38) GAUGE PLANE 0.015 (0.38) MIN 0.200 (5.08) 0.115 (2.92) SEATING PLANE 0.022 (0.56) 0.014 (0.36) 0.005 (0.13) MIN 0.700 (17.78) MAX 0.015 (0.38) 0.008 (0.20) COMPLIANT TO JEDEC STANDARDS MS-011 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE LEADS. Figure 27. 28-Lead Plastic Dual In-Line Package [PDIP] (N-28) Dimensions shown in inches and (millimeters) Rev. C | Page 17 of 20 071006-A 0.070 (1.78) 0.050 (1.27) ADG526A/ADG527A 0.180 (4.57) 0.165 (4.19) 0.048 (1.22) 0.042 (1.07) 0.048 (1.22) 0.042 (1.07) 0.056 (1.42) 0.042 (1.07) 4 5 PIN 1 IDENTIFIER 26 25 0.021 (0.53) 0.013 (0.33) 0.050 (1.27) BSC TOP VIEW (PINS DOWN) 11 12 0.020 (0.51) MIN 0.032 (0.81) 0.026 (0.66) 19 18 0.456 (11.582) SQ 0.450 (11.430) 0.495 (12.57) SQ 0.485 (12.32) BOTTOM VIEW (PINS UP) 0.430 (10.92) 0.390 (9.91) 0.045 (1.14) R 0.025 (0.64) 0.120 (3.04) 0.090 (2.29) 042508-A COMPLIANT TO JEDEC STANDARDS MO-047-AB CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 28. 28-Lead Plastic Leaded Chip Carrier [PLCC] (P-28A) Dimensions shown in inches and (millimeters) 18.10 (0.7126) 17.70 (0.6969) 15 28 7.60 (0.2992) 7.40 (0.2913) 14 2.65 (0.1043) 2.35 (0.0925) 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 10.65 (0.4193) 10.00 (0.3937) 1.27 (0.0500) BSC 0.51 (0.0201) 0.31 (0.0122) SEATING PLANE 0.75 (0.0295) 0.25 (0.0098) 8° 0° 0.33 (0.0130) 0.20 (0.0079) COMPLIANT TO JEDEC STANDARDS MS-013-AE CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 29. 28-Lead Standard Small Outline Package [SOIC] Wide Body (RW-28) Dimensions shown in millimeters and (inches) Rev. C | Page 18 of 20 45° 1.27 (0.0500) 0.40 (0.0157) 060706-A 1 ADG526A/ADG527A ORDERING GUIDE Model ADG526AKN ADG526AKNZ 1 ADG526AKR ADG526AKR-REEL ADG526AKRZ1 ADG526AKRZ-REEL1 ADG526AKP ADG526AKP-REEL ADG526AKPZ1 ADG526AKPZ-REEL1 ADG526ATQ ADG526ABQ ADG526ATCHIPS ADG527AKN ADG527AKNZ1 ADG527AKR ADG527AKR-REEL ADG527AKRZ1 ADG527AKP ADG527AKPZ1 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −55°C to +125°C −40°C to +85°C Package Description 28-Lead PDIP 28-Lead PDIP 28-Lead SOIC 28-Lead SOIC 28-Lead SOIC 28-Lead SOIC 28-Lead PLCC 28-Lead PLCC 28-Lead PLCC 28-Lead PLCC 28-Lead CERDIP 28-Lead CERDIP −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C 28-Lead PDIP 28-Lead PDIP 28-Lead SOIC 28-Lead SOIC 28-Lead SOIC 28-Lead PLCC 28-Lead PLCC Z = RoHS Compliant Part, # denotes RoHS complaint product, may be top or bottom marked. Rev. C | Page 19 of 20 Package Option N-28 N-28 RW-28 RW-28 RW-28 RW-28 P-28A P-28A P-28A P-28A Q-28 Q-28 DIE N-28 N-28 RW-28 RW-28 RW-28 P-28A P-28A ADG526A/ADG527A NOTES ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D01532-0-6/08(C) Rev. C | Page 20 of 20