High Voltage Latch-Up Proof, 4-/8-Channel Multiplexers ADG5408/ADG5409 FEATURES FUNCTIONAL BLOCK DIAGRAMS Latch-up proof 8 kV human body model (HBM) ESD rating Low on resistance (13.5 Ω) ±9 V to ±22 V dual-supply operation 9 V to 40 V single-supply operation 48 V supply maximum ratings Fully specified at ±15 V, ±20 V, +12 V, and +36 V VSS to VDD analog signal range ADG5408 ADG5409 S1 S1A DA S4A D S1B DB S8 1-OF-8 DECODER Relay replacement Automatic test equipment Data acquisition Instrumentation Avionics Audio and video switching Communication systems 1-OF-4 DECODER A0 A1 A2 EN A0 A1 EN 09206-001 APPLICATIONS S4B Figure 1. GENERAL DESCRIPTION The ADG5408/ADG5409 are monolithic CMOS analog multiplexers comprising eight single channels and four differential channels, respectively. The ADG5408 switches one of eight inputs to a common output, as determined by the 3-bit binary address lines, A0, A1, and A2. The ADG5409 switches one of four differential inputs to a common differential output, as determined by the 2-bit binary address lines, A0 and A1. The ADG5408/ADG5409 do not have VL pins; rather, the logic power supply is generated internally by an on-chip voltage generator. An EN input on both devices enables or disables the device. When EN is disabled, all channels switch off. The on-resistance profile is very flat over the full analog input range, which ensures good linearity and low distortion when switching audio signals. High switching speed also makes the parts suitable for video signal switching. 2. 3. Each switch conducts equally well in both directions when on, and each switch has an input signal range that extends to the power supplies. In the off condition, signal levels up to the supplies are blocked. PRODUCT HIGHLIGHTS 1. 4. 5. 6. Trench isolation guards against latch-up. A dielectric trench separates the P and N channel transistors thereby preventing latch-up even under severe overvoltage conditions. Low RON. Dual-supply operation. For applications where the analog signal is bipolar, the ADG5408/ADG5409 can be operated from dual supplies up to ±22 V. Single-supply operation. For applications where the analog signal is unipolar, the ADG5408/ADG5409 can be operated from a single rail power supply up to 40 V. 3 V logic compatible digital inputs: VINH = 2.0 V, VINL = 0.8 V. No VL logic power supply required. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved. ADG5408/ADG5409 TABLE OF CONTENTS Features .............................................................................................. 1 Absolute Maximum Ratings ............................................................9 Applications ....................................................................................... 1 ESD Caution...................................................................................9 Functional Block Diagrams ............................................................. 1 Pin Configurations and Function Descriptions ......................... 10 General Description ......................................................................... 1 Typical Performance Characteristics ........................................... 12 Product Highlights ........................................................................... 1 Test Circuits ..................................................................................... 16 Specifications..................................................................................... 3 Terminology .................................................................................... 18 ±15 V Dual Supply ....................................................................... 3 Trench Isolation .............................................................................. 19 ±20 V Dual Supply ....................................................................... 4 Applications Information .............................................................. 20 12 V Single Supply ........................................................................ 5 Outline Dimensions ....................................................................... 21 36 V Single Supply ........................................................................ 6 Ordering Guide .......................................................................... 21 Continuous Current per Channel, Sx or D ............................... 8 REVISION HISTORY 9/10—Revision 0: Initial Version Rev. 0 | Page 2 of 24 ADG5408/ADG5409 SPECIFICATIONS ±15 V DUAL SUPPLY VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted. Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, ∆RON On-Resistance Flatness, RFLAT (ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID (On), IS (On) 25°C 13.5 15 0.3 0.8 1.8 2.2 ±0.05 ±0.25 ±0.1 ±0.4 ±0.1 ±0.4 −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments VDD to VSS V Ω typ Ω max Ω typ VS = ±10 V, IS = −10 mA; see Figure 26 VDD = +13.5 V, VSS = −13.5 V VS = ±10 V, IS = −10 mA 18 22 1.3 1.4 2.6 3 ±1 ±7 ±4 ±30 ±4 ±30 Ω max Ω typ Ω max nA typ nA max nA typ nA max nA typ nA max VS = ±10 V, IS = −10 mA VDD = +16.5 V, VSS = −16.5 V VS = ±10 V, VD = m 10 V; see Figure 29 VS = ±10 V, VD = m 10 V; see Figure 29 VS = VD = ±10 V; see Figure 25 DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH 2.0 0.8 0.002 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION 3 V min V max μA typ μA max pF typ VIN = VGND or VDD Break-Before-Make Time Delay, tD 170 217 140 175 130 161 50 Charge Injection, QINJ 115 ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ Off Isolation −60 dB typ Channel-to-Channel Crosstalk −60 dB typ Total Harmonic Distortion + Noise 0.01 % typ −3 dB Bandwidth ADG5408 ADG5409 Insertion Loss 50 87 0.9 MHz typ MHz typ dB typ 15 pF typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 31 VS = 0 V, f = 1 MHz 102 50 pF typ pF typ VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz tON (EN) tOFF (EN) 258 292 213 242 183 198 16 CS (Off ) CD (Off ) ADG5408 ADG5409 Rev. 0 | Page 3 of 24 RL = 300 Ω, CL = 35 pF VS = 10 V; see Figure 32 RL = 300 Ω, CL = 35 pF VS = 10 V; see Figure 34 RL = 300 Ω, CL = 35 pF VS = 10 V; see Figure 34 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 10 V; see Figure 33 VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 35 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 27 RL = 1 kΩ, 15 V p-p, f = 20 Hz to 20 kHz; see Figure 30 RL = 50 Ω, CL = 5 pF; see Figure 31 ADG5408/ADG5409 Parameter CD (On), CS (On) ADG5408 ADG5409 POWER REQUIREMENTS IDD ISS 25°C −40°C to +85°C 133 81 45 55 0.001 Unit Test Conditions/Comments pF typ pF typ VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VDD = +16.5 V, VSS = −16.5 V Digital inputs = 0 V or VDD μA typ μA max μA typ μA max V min/V max Digital inputs = 0 V or VDD −40°C to +125°C Unit Test Conditions/Comments VDD to VSS V Ω typ Ω max Ω typ VS = ±15 V, IS = −10 mA; see Figure 26 VDD = +18 V, VSS = −18 V VS = ±15 V, IS = −10 mA 70 1 ±9/±22 VDD/VSS 1 −40°C to +125°C GND = 0 V Guaranteed by design; not subject to production test. ±20 V DUAL SUPPLY VDD = +20 V ± 10%, VSS = −20 V ± 10%, GND = 0 V, unless otherwise noted. Table 2. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, ∆RON On-Resistance Flatness, RFLAT (ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID (On), IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH 25°C 12.5 14 0.3 0.8 2.3 2.7 ±0.1 ±0.25 ±0.15 ±0.4 ±0.15 ±0.4 −40°C to +85°C 17 21 1.3 1.4 3.1 3.5 ±1 ±7 ±4 ±30 ±4 ±30 2.0 0.8 0.002 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION 3 nA typ nA max nA typ nA max nA typ nA max V min V max μA typ μA max pF typ Charge Injection, QINJ 155 ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ Off Isolation −60 dB typ Channel-to-Channel Crosstalk −60 dB typ tON (EN) tOFF (EN) Break-Before-Make Time Delay, tD 160 207 140 165 133 153 38 Ω max Ω typ Ω max 237 262 194 218 174 189 11 Rev. 0 | Page 4 of 24 VS = ±15 V, IS = −10 mA VDD = +22 V, VSS = −22 V VS = ±15 V, VD = m 15 V; see Figure 29 VS = ±15 V, VD = m 15 V; see Figure 29 VS = VD = ±15 V; see Figure 25 VIN = VGND or VDD RL = 300 Ω, CL = 35 pF VS = 10 V; see Figure 32 RL = 300 Ω, CL = 35 pF VS = 10 V; see Figure 34 RL = 300 Ω, CL = 35 pF VS = 10 V; see Figure 34 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 10 V; see Figure 33 VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 35 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 27 ADG5408/ADG5409 Parameter Total Harmonic Distortion + Noise −3 dB Bandwidth ADG5408 ADG5409 Insertion Loss CS (Off ) CD (Off ) ADG5408 ADG5409 CD (On), CS (On) ADG5408 ADG5409 POWER REQUIREMENTS IDD ISS VDD/VSS 1 25°C 0.012 −40°C to +85°C −40°C to +125°C Unit % typ Test Conditions/Comments RL = 1 kΩ, 20 V p-p, f = 20 Hz to 20 kHz; see Figure 30 RL = 50 Ω, CL = 5 pF; see Figure 31 50 88 0.8 MHz typ MHz typ dB typ 17 pF typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 31 VS = 0 V, f = 1 MHz 98 48 pF typ pF typ VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz 128 80 pF typ pF typ VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VDD = +22 V, VSS = −22 V Digital inputs = 0 V or VDD 50 70 0.001 μA typ μA max μA typ V min/V max Digital inputs = 0 V or VDD GND = 0 V −40°C to +125°C Unit Test Conditions/Comments 0 V to VDD V Ω typ 110 ±9/±22 Guaranteed by design; not subject to production test. 12 V SINGLE SUPPLY VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 3. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, ∆RON On-Resistance Flatness, RFLAT (ON) 25°C −40°C to +85°C 26 30 0.3 36 42 Ω max Ω typ 1 5.5 6.5 1.5 1.6 VS = 0 V to 10 V, IS = −10 mA 8 12 Ω max Ω typ Ω max nA typ VDD = 13.2 V, VSS = 0 V VS = 1 V/10 V, VD = 10 V/1 V; see Figure 29 LEAKAGE CURRENTS Source Off Leakage, IS (Off ) ±0.02 ±0.25 ±0.05 ±1 Drain Off Leakage, ID (Off ) ±0.4 ±0.05 ±0.4 ±4 ±30 ±4 ±30 Channel On Leakage, ID (On), IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH ±7 2.0 0.8 0.002 ±0.1 Digital Input Capacitance, CIN VS = 0 V to 10 V, IS = −10 mA; see Figure 26 VDD = 10.8 V, VSS = 0 V VS = 0 V to 10 V, IS = −10 mA 3 Rev. 0 | Page 5 of 24 nA max nA typ VS = 1 V/10 V, VD = 10 V/1 V; see Figure 29 nA max nA typ nA max VS = VD = 1 V/10 V; see Figure 25 V min V max μA typ μA max pF typ VIN = VGND or VDD ADG5408/ADG5409 Parameter DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION 25°C −40°C to +85°C −40°C to +125°C 388 430 345 397 187 209 Test Conditions/Comments RL = 300 Ω, CL = 35 pF VS = 8 V; see Figure 32 RL = 300 Ω, CL = 35 pF VS = 8 V; see Figure 34 RL = 300 Ω, CL = 35 pF VS = 8 V; see Figure 34 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 8 V; see Figure 33 VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 35 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 27 RL = 1 kΩ, 6 V p-p, f = 20 Hz to 20 kHz; see Figure 30 RL = 50 Ω, CL = 5 pF; see Figure 31 Break-Before-Make Time Delay, tD 230 321 215 276 134 161 118 Charge Injection, QINJ 45 ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ Off Isolation −60 dB typ Channel-to-Channel Crosstalk −60 dB typ Total Harmonic Distortion + Noise 0.1 % typ −3 dB Bandwidth ADG5408 ADG5409 Insertion Loss 35 74 −1.8 MHz typ MHz typ dB typ 22 pF typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 31 VS = 6 V, f = 1 MHz 119 59 pF typ pF typ VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz 146 86 pF typ pF typ VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz VDD = 13.2 V Digital inputs = 0 V or VDD tON (EN) tOFF (EN) 55 CS (Off ) CD (Off ) ADG5408 ADG5409 CD (On), CS (On) ADG5408 ADG5409 POWER REQUIREMENTS IDD 40 50 65 9/40 VDD 1 Unit μA typ μA max V min/V max GND = 0 V, VSS = 0 V Guaranteed by design; not subject to production test. 36 V SINGLE SUPPLY VDD = 36 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 4. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, ∆RON On-Resistance Flatness, RFLAT (ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) 25°C −40°C to +85°C −40°C to +125°C Unit 0 V to VDD V Ω typ 14.5 Test Conditions/Comments VS = 0 V to 30 V, IS = −10 mA; see Figure 26 VDD = 32.4 V, VSS = 0 V VS = 0 V to 30 V, IS = −10 mA 16 0.3 19 23 Ω max Ω typ 0.8 3.5 4.3 1.3 1.4 VS = 0 V to 30 V, IS = −10 mA 5.5 6.5 Ω max Ω typ Ω max nA typ VDD =39.6 V, VSS = 0 V VS = 1 V/30 V, VD = 30 V/1 V; see Figure 29 ±0.1 ±0.25 ±1 ±7 Rev. 0 | Page 6 of 24 nA max ADG5408/ADG5409 Parameter Drain Off Leakage, ID (Off ) Channel On Leakage, ID (On), IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH 25°C ±0.15 −40°C to +85°C −40°C to +125°C Unit nA typ ±0.4 ±0.15 ±0.4 ±4 ±30 VS = VD = 1 V/30 V; see Figure 25 ±4 ±30 nA max nA typ nA max V min V max μA typ μA max pF typ VIN = VGND or VDD 2.0 0.8 0.002 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION 3 Break-Before-Make Time Delay, tD 187 242 160 195 147 184 53 Charge Injection, QINJ 150 ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ Off Isolation −60 dB typ Channel-to-Channel Crosstalk −60 dB typ Total Harmonic Distortion + Noise 0.4 % typ −3 dB Bandwidth ADG5408 ADG5409 Insertion Loss 45 76 −1 MHz typ MHz typ dB typ 18 pF typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 31 VS = 18 V, f = 1 MHz 120 60 pF typ pF typ VS = 18 V, f = 1 MHz VS = 18 V, f = 1 MHz 137 80 pF typ pF typ VS = 18 V, f = 1 MHz VS = 18 V, f = 1 MHz VDD = 39.6 V Digital inputs = 0 V or VDD tON (EN) tOFF (EN) 257 281 219 237 184 190 17 CS (Off ) CD (Off ) ADG5408 ADG5409 CD (On), CS (On) ADG5408 ADG5409 POWER REQUIREMENTS IDD 80 100 VDD 1 Test Conditions/Comments VS = 1 V/30 V, VD = 30 V/1 V; see Figure 29 130 9/40 Guaranteed by design; not subject to production test. Rev. 0 | Page 7 of 24 μA typ μA max V min/V max RL = 300 Ω, CL = 35 pF VS = 18 V; see Figure 32 RL = 300 Ω, CL = 35 pF VS = 18 V; see Figure 34 RL = 300 Ω, CL = 35 pF VS = 18 V; see Figure 34 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 18 V; see Figure 33 VS = 18 V, RS = 0 Ω, CL = 1 nF; see Figure 35 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 27 RL = 1 kΩ, 18 V p-p, f = 20 Hz to 20 kHz; see Figure 30 RL = 50 Ω, CL = 5 pF; see Figure 31 GND = 0 V, VSS = 0 V ADG5408/ADG5409 CONTINUOUS CURRENT PER CHANNEL, Sx OR D Table 5. ADG5408 Parameter CONTINUOUS CURRENT, Sx OR D VDD = +15 V, VSS = −15 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 30.4°C/W) VDD = +20 V, VSS = −20 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 30.4°C/W) VDD = 12 V, VSS = 0 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 30.4°C/W) VDD = 36 V, VSS = 0 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 30.4°C/W) 25°C 85°C 125°C Unit 100 170 44 54 16 16 mA maximum mA maximum 106 178 45 55 16 16 mA maximum mA maximum 81 140 39 51 15 16 mA maximum mA maximum 104 175 44 55 16 16 mA maximum mA maximum 25°C 85°C 125°C Unit 75 130 37 49 15 16 mA maximum mA maximum 79 136 38 50 15 16 mA maximum mA maximum 60 105 32 44 14 16 mA maximum mA maximum 78 133 38 50 15 16 mA maximum mA maximum Table 6. ADG5409 Parameter CONTINUOUS CURRENT, Sx OR D VDD = +15 V, VSS = −15 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 30.4°C/W) VDD = +20 V, VSS = −20 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 30.4°C/W) VDD = 12 V, VSS = 0 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 30.4°C/W) VDD = 36 V, VSS = 0 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 30.4°C/W) Rev. 0 | Page 8 of 24 ADG5408/ADG5409 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 7. Parameter VDD to VSS VDD to GND VSS to GND Analog Inputs1 Digital Inputs1 Peak Current, Sx or D Pins ADG5408 ADG5409 Continuous Current, Sx or D2 Temperature Range Operating Storage Junction Temperature Thermal Impedance, θJA 16-Lead TSSOP (4-Layer Board) 16-Lead LFCSP (4-Layer Board) Reflow Soldering Peak Temperature, Pb Free Rating 48 V −0.3 V to +48 V +0.3 V to −48 V VSS − 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first VSS − 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first 370 mA (pulsed at 1 ms, 10% duty cycle maximum) 275 mA (pulsed at 1 ms, 10% duty cycle maximum) Data + 15% Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating can be applied at any one time. ESD CAUTION −40°C to +125°C −65°C to +150°C 150°C 112.6°C/W 30.4°C/W 260(+0/−5)°C 1 Overvoltages at the Ax, EN, Sx, and D pins are clamped by internal diodes. Limit current to the maximum ratings given. 2 See Table 5. Rev. 0 | Page 9 of 24 ADG5408/ADG5409 ADG5408 13 VDD S2 5 TOP VIEW (Not to Scale) 14 A1 VSS 1 PIN 1 INDICATOR S1 2 ADG5408 11 VDD TOP VIEW (Not to Scale) 10 S5 S5 S2 3 11 S6 S3 4 S4 7 10 S7 D 8 9 S8 S4 5 09206-002 12 S3 6 12 GND 9 S6 NOTES 1. THE EXPOSED PAD IS CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE SUBSTRATE, VSS. Figure 2. ADG5408 Pin Configuration (TSSOP) 09206-003 S1 4 13 A2 GND 3 S7 8 A2 14 VSS 15 A0 A1 S8 7 16 15 D 6 A0 1 EN 2 16 EN PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 3. ADG5408 Pin Configuration (LFCSP) Table 8. ADG5408 Pin Function Descriptions Pin No. TSSOP LFCSP 1 15 2 16 Mnemonic A0 EN 3 1 VSS 4 5 6 7 8 9 10 11 12 13 14 15 16 2 3 4 5 6 7 8 9 10 11 12 13 14 EP S1 S2 S3 S4 D S8 S7 S6 S5 VDD GND A2 A1 Exposed Pad Description Logic Control Input. Active High Digital Input. When low, the device is disabled and all switches are off. When high, Ax logic inputs determine on switches. Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to ground. Source Terminal 1. This pin can be an input or an output. Source Terminal 2. This pin can be an input or an output. Source Terminal 3. This pin can be an input or an output. Source Terminal 4. This pin can be an input or an output. Drain Terminal. This pin can be an input or an output. Source Terminal 8. This pin can be an input or an output. Source Terminal 7. This pin can be an input or an output. Source Terminal 6. This pin can be an input or an output. Source Terminal 5. This pin can be an input or an output. Most Positive Power Supply Potential. Ground (0 V) Reference. Logic Control Input. Logic Control Input. The exposed pad is connected internally. For increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS. Table 9. ADG5408 Truth Table A2 X 0 0 0 0 1 1 1 1 A1 X 0 0 1 1 0 0 1 1 A0 X 0 1 0 1 0 1 0 1 EN 0 1 1 1 1 1 1 1 1 Rev. 0 | Page 10 of 24 On Switch None 1 2 3 4 5 6 7 8 ADG5409 13 S1B S2A 5 TOP VIEW (Not to Scale) 12 S2B S3A 6 11 S3B S4A 7 10 S4B DA 8 9 DB 14 A1 13 GND VSS 1 PIN 1 INDICATOR S1A 2 ADG5409 11 S1B S2A 3 TOP VIEW (Not to Scale) 10 S2B S3A 4 12 VDD 9 S3B NOTES 1. THE EXPOSED PAD IS CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE SUBSTRATE, VSS. Figure 4. ADG5409 Pin Configuration (TSSOP) 09206-005 4 S4B 8 S1A 15 A0 VDD 3 DB 7 GND 14 VSS DA 6 A1 S4A 5 16 15 09206-004 A0 1 EN 2 16 EN ADG5408/ADG5409 Figure 5. ADG5409 Pin Configuration (LFCSP) Table 10. ADG5409 Pin Function Descriptions Pin No. TSSOP LFCSP 1 15 2 16 Mnemonic A0 EN 3 1 VSS 4 5 6 7 8 9 10 11 12 13 14 15 16 2 3 4 5 6 7 8 9 10 11 12 13 14 EP S1A S2A S3A S4A DA DB S4B S3B S2B S1B VDD GND A1 Exposed Pad Description Logic Control Input. Active High Digital Input. When low, the device is disabled and all switches are off. When high, Ax logic inputs determine on switches. Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to ground. Source Terminal 1A. This pin can be an input or an output. Source Terminal 2A. This pin can be an input or an output. Source Terminal 3A. This pin can be an input or an output. Source Terminal 4A. This pin can be an input or an output. Drain Terminal A. This pin can be an input or an output. Drain Terminal B. This pin can be an input or an output. Source Terminal 4B. This pin can be an input or an output. Source Terminal 3B. This pin can be an input or an output. Source Terminal 2B. This pin can be an input or an output. Source Terminal 1B. This pin can be an input or an output. Most Positive Power Supply Potential. Ground (0 V) Reference. Logic Control Input. The exposed pad is connected internally. For increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS. Table 11. ADG5409 Truth Table A1 X 0 0 1 1 A0 X 0 1 0 1 EN 0 1 1 1 1 On Switch Pair None 1 2 3 4 Rev. 0 | Page 11 of 24 ADG5408/ADG5409 TYPICAL PERFORMANCE CHARACTERISTICS 25 16 TA = 25°C TA = 25°C VDD = +10V VSS = –10V VDD = +9V VSS = –9V 14 12 VDD = +11V VSS = –11V ON RESISTANCE (Ω) ON RESISTANCE (Ω) 20 15 10 VDD = +13.5V VSS = –13.5V VDD = +15V VSS = –15V VDD = +16.5V VSS = –16.5V 10 VDD = 32.4V VSS = 0V 8 VDD = 39.6V VSS = 0V VDD = 36V VSS = 0V 6 4 5 –14 –10 –6 –2 2 6 10 14 18 VS, VD (V) 0 09206-028 0 –18 0 5 10 15 20 25 30 35 40 45 VS, VD (V) 09206-027 2 Figure 9. RON as a Function of VS, VD (Single Supply) Figure 6. RON as a Function of VS, VD (Dual Supply) 25 16 TA = 25°C 14 ON RESISTANCE (Ω) ON RESISTANCE (Ω) 20 VDD = +18V VSS = –18V 12 10 8 VDD = +22V VSS = –22V VDD = +20V VSS = –20V 6 TA = +125°C 15 TA = +85°C TA = +25°C 10 TA = –40°C 4 –20 –15 –10 –5 0 5 10 15 20 VS, VD (V) 25 VDD = +15V VSS = –15V 0 –15 –10 09206-029 0 –25 VDD = 10V VSS = 0V –30 VDD = 10.8V VSS = 0V 10 15 VDD = +20V VSS = –20V 20 ON RESISTANCE (Ω) –25 –20 –15 VDD = 13.2V VSS = 0V VDD = 12V VSS = 0V VDD = 11V VSS = 0V –10 TA = +125°C 15 TA = +85°C TA = +25°C 10 TA = –40°C 5 0 0 –2 –4 –6 –8 VS, VD (V) –10 –12 –14 Figure 8. RON as a Function of VS, VD (Single Supply) 0 –20 –15 –10 –5 0 5 10 15 20 VS, VD (V) Figure 11. RON as a Function of VS (VD) for Different Temperatures, ±20 V Dual Supply Rev. 0 | Page 12 of 24 09206-024 –5 09206-023 ON RESISTANCE (Ω) VDD = 9V VSS = 0V 5 Figure 10. RON as a Function of VS (VD) for Different Temperatures, ±15 V Dual Supply 25 TA = 25°C 0 VS, VD (V) Figure 7. RON as a Function of VS, VD (Dual Supply) –35 –5 09206-030 5 2 ADG5408/ADG5409 40 1 VDD = +20V VSS = –20V VBIAS = +15V/–15V 35 TA = +85°C 25 20 TA = +25°C 15 TA = –40°C 10 5 –1 ID, IS (ON) – – ID (OFF) + – –2 2 4 6 8 10 12 –3 0 50 75 100 125 TEMPERATURE (°C) Figure 12. RON as a Function of VS (VD) for Different Temperatures, 12 V Single Supply Figure 15. Leakage Currents vs. Temperature, ±20 V Dual Supply 0.5 25 25 09206-035 0 VS, VD (V) VDD = 12V VSS = 0V VBIAS = 1V/10V VDD = 36V VSS = 0V ID, IS (ON) + + IS (OFF) + – 0 LEAKAGE CURRENT (nA) 20 ON RESISTANCE (Ω) ID (OFF) – + IS (OFF) – + VDD = 12V VSS = 0V 09206-031 0 0 TA = +125°C 15 TA = +85°C TA = +25°C 10 TA = –40°C 5 ID (OFF) – + –0.5 IS (OFF) – + ID, IS (ON) – – –1.0 ID (OFF) + – –1.5 0 5 10 15 20 25 30 35 40 VS, VD (V) –2.0 09206-032 0 50 75 100 125 Figure 16. Leakage Currents vs. Temperature, 12 V Single Supply 1 VDD = +15V VSS = –15V VBIAS = +10V/–10V 25 TEMPERATURE (°C) Figure 13. RON as a Function of VD (VS) for Different Temperatures, 36 V Single Supply 0.5 0 09206-033 ON RESISTANCE (Ω) LEAKAGE CURRENT (nA) TA = +125°C 30 ID, IS (ON) + + IS (OFF) + – VDD = +36V VSS = 0V VBIAS = 1V/30V ID, IS (ON) + + IS (OFF) + – ID, IS (ON) + + IS (OFF) + – LEAKAGE CURRENT (nA) IS (OFF) – + –0.5 ID (OFF) – + ID, IS (ON) – – –1.0 ID (OFF) + – 0 IS (OFF) – + ID (OFF) – + –1 ID, IS (ON) – – ID (OFF) + – –2 –2.0 0 25 50 75 100 125 TEMPERATURE (°C) –3 0 25 50 75 100 125 TEMPERATURE (°C) Figure 17. Leakage Currents vs. Temperature, 36 V Single Supply Figure 14. Leakage Currents vs. Temperature, ±15 V Dual Supply Rev. 0 | Page 13 of 24 09206-036 –1.5 09206-034 LEAKAGE CURRENT (nA) 0 ADG5408/ADG5409 0 –10 –20 –20 –30 –30 ACPSRR (dB) TA = 25°C V = +15V –10 VDD = –15V SS –50 –60 –60 –80 –80 –90 –90 –100 –100 100k 1M 10M 100M 1G FREQUENCY (Hz) DECOUPLING CAPACITORS –50 –70 10k NO DECOUPLING CAPACITORS –40 –70 1k TA = 25°C VDD = +15V VSS = –15V 1k 0 1M 10M Figure 21. ACPSRR vs. Frequency, ±15 V Dual Supply 0.12 TA = 25°C VDD = +15V VSS = –15V VDD = 12V, VSS = 0V, VS = 6V p-p 0.10 –20 LOAD = 1kΩ TA = 25°C –30 0.08 THD + N (%) CROSSTALK (dB) 100k FREQUENCY (Hz) Figure 18. Off Isolation vs. Frequency, ±15 V Dual Supply –10 10k 09206-022 –40 09206-021 OFF ISOLATION (dB) 0 –40 –50 –60 0.06 VDD = 36V, VSS = 0V, VS = 18V p-p 0.04 –70 –80 VDD = 15V, VSS = 15V, VS = 15V p-p 0.02 –90 1M 10M 100M 1G FREQUENCY (Hz) 0 0 15 20 1G Figure 22. THD + N vs. Frequency 0 300 TA = 25°C TA = 25°C V = +15V –0.5 VDD = –15V SS VDD = +20V VSS = –20V 250 INSERTION LOSS (dB) –1.0 200 VDD = +36V VSS = 0V 150 100 VDD = +12V VSS = 0V 50 10 ADG5409 –1.5 ADG5408 –2.0 –2.5 –3.0 –3.5 –4.0 VDD = +15V VSS = –15V –4.5 0 10 20 30 VS (V) 40 09206-019 CHARGE INJECTION (pC) 10 FREQUENCY (kHz) Figure 19. Crosstalk vs. Frequency, ±15 V Dual Supply 0 20 5 09206-025 100k 09206-026 –100 10k 09206-020 VDD = 20V, VSS = 20V, VS = 20V p-p –5.0 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 23. Bandwidth Figure 20. Charge Injection vs. Source Voltage Rev. 0 | Page 14 of 24 100M ADG5408/ADG5409 400 350 300 VDD = +12V, VSS = 0V VDD = +36V, VSS = 0V 200 VDD = +15V, VSS = –15V 150 VDD = +20V, VSS = –20V 100 50 0 –40 –20 0 20 40 60 80 100 TEMPERATURE (°C) 120 09206-018 TIME (ns) 250 Figure 24. tTRANSITION Times vs. Temperature Rev. 0 | Page 15 of 24 ADG5408/ADG5409 TEST CIRCUITS ID (ON) IS (OFF) A A Dx NC = NO CONNECT VD ID (OFF) Sx D A VS 09206-007 Sx 09206-008 NC VD Figure 29. Off Leakage Figure 25. On Leakage VDD VSS 0.1µF 0.1µF AUDIO PRECISION VDD VSS RS IDS Sx IN V1 VS V p-p D VIN RL 10kΩ D GND 09206-006 VS RON = V1/IDS Figure 30. THD + Noise Figure Figure 26. On Resistance VDD VSS 0.1µF VDD 0.1µF VSS 0.1µF 0.1µF NETWORK ANALYZER VOUT VOUT 09206-015 Sx VDD S1 VSS RL 50Ω VDD D NETWORK ANALYZER VSS Sx S2 50Ω RL 50Ω VS D RL 50Ω GND CHANNEL-TO-CHANNEL CROSSTALK = 20 log 09206-014 GND VOUT VS INSERTION LOSS = 20 log VSS VDD 0.1µF 0.1µF VDD NETWORK ANALYZER VSS 50Ω Sx 50Ω VS D OFF ISOLATION = 20 log VOUT VS VOUT 09206-013 RL 50Ω GND VOUT WITH SWITCH VOUT WITHOUT SWITCH Figure 31. Bandwidth Figure 27. Channel-to-Channel Crosstalk Figure 28. Off Isolation Rev. 0 | Page 16 of 24 VOUT 09206-017 VS ADG5408/ADG5409 3V tr < 20ns tf < 20ns ADDRESS DRIVE (VIN) 50% 50% VDD VSS VDD VSS A0 S1 0V VIN VS1 A1 50Ω S2 TO S7 A2 tTRANSITION tTRANSITION VS8 S8 90% ADG5408* 2.4V OUTPUT OUTPUT D EN 300Ω GND 35pF 09206-009 90% *SIMILAR CONNECTION FOR ADG5409. Figure 32. Address to Output Switching Times, tTRANSITION 3V ADDRESS DRIVE (VIN) VDD VSS VDD VSS A0 S1 VIN 0V VS A1 50Ω S2 TO S7 A2 S8 80% ADG5408* 80% OUTPUT 2.4V OUTPUT D EN 300Ω GND 35pF 09206-010 tD *SIMILAR CONNECTION FOR ADG5409. Figure 33. Break-Before-Make Delay, tD 3V ENABLE DRIVE (VIN) 50% VDD VSS VDD VSS A0 50% S1 VS A1 S2 TO S8 0V A2 ADG5408* tOFF (EN) 0.9VO OUTPUT 0.9VO OUTPUT D EN VIN 50Ω 35pF 300Ω GND 09206-011 tON (EN) *SIMILAR CONNECTION FOR ADG5409. Figure 34. Enable Delay, tON (EN), tOFF (EN) 3V VDD VSS VDD VSS A0 A1 VIN A2 ADG5408* RS ΔVOUT Sx D EN QINJ = CL × ΔVOUT VS GND VOUT CL 1nF VIN *SIMILAR CONNECTION FOR ADG5409. Figure 35. Charge Injection Rev. 0 | Page 17 of 24 09206-012 VOUT ADG5408/ADG5409 TERMINOLOGY IDD IDD represents the positive supply current. CIN CIN represents digital input capacitance. ISS ISS represents the negative supply current. tON (EN) tON (EN) represents the delay time between the 50% and 90% points of the digital input and switch on condition. VD, VS VD and VS represent the analog voltage on Terminal D and Terminal S, respectively. tOFF (EN) tOFF (EN) represents the delay time between the 50% and 90% points of the digital input and switch off condition. RON RON is the ohmic resistance between Terminal D and Terminal S. tTRANSITION Delay time between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to another. ΔRON ΔRON represents the difference between the RON of any two channels. tD RFLAT (ON) The difference between the maximum and minimum value of on resistance as measured over the specified analog signal range is represented by RFLAT (ON). IS (Off) IS (Off) is the source leakage current with the switch off. ID (Off) ID (Off) is the drain leakage current with the switch off. ID (On), IS (On) ID (On) and IS (On) represent the channel leakage currents with the switch on. VINL VINL is the maximum input voltage for Logic 0. tD represents the off time measured between the 80% point of both switches when switching from one address state to another. Off Isolation Off isolation is a measure of unwanted signal coupling through an off channel. Charge Injection Charge injection is a measure of the glitch impulse transferred from the digital input to the analog output during switching. Crosstalk Crosstalk is a measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. Bandwidth Bandwidth is the frequency at which the output is attenuated by 3 dB. VINH VINH is the minimum input voltage for Logic 1. IINL, IINH IINL and IINH represent the low and high input currents of the digital inputs. On Response On response is the frequency response of the on switch. CD (Off) CD (Off) represents the off switch drain capacitance, which is measured with reference to ground. Total Harmonic Distortion + Noise (THD + N) The ratio of the harmonic amplitude plus noise of the signal to the fundamental is represented by THD + N. CS (Off) CS (Off) represents the off switch source capacitance, which is measured with reference to ground. AC Power Supply Rejection Ratio (ACPSRR) ACPSRR is a measure of the ability of a part to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p. The ratio of the amplitude of signal on the output to the amplitude of the modulation is the ACPSRR. CD (On), CS (On) CD (On) and CS (On) represent on switch capacitances, which are measured with reference to ground. Rev. 0 | Page 18 of 24 ADG5408/ADG5409 TRENCH ISOLATION In the ADG5408/ADG5409, an insulating oxide layer (trench) is placed between the NMOS and the PMOS transistors of each CMOS switch. Parasitic junctions, which occur between the transistors in junction isolated switches, are eliminated, and the result is a completely latch-up proof switch. PMOS P-WELL N-WELL TRENCH BURIED OXIDE LAYER HANDLE WAFER Figure 36. Trench Isolation Rev. 0 | Page 19 of 24 09206-016 In junction isolation, the N and P wells of the PMOS and NMOS transistors form a diode that is reverse-biased under normal operation. However, during overvoltage conditions, this diode can become forward-biased. A silicon controlled rectifier (SCR) type circuit is formed by the two transistors causing a significant amplification of the current that, in turn, leads to latch-up. With trench isolation, this diode is removed, and the result is a latch-up proof switch. NMOS ADG5408/ADG5409 APPLICATIONS INFORMATION The ADG54xx family switches and multiplexers provide a robust solution for instrumentation, industrial, automotive, aerospace, and other harsh environments that are prone to latch-up, which is an undesirable high current state that can lead to device failure and persist until the power supply is turned off. The ADG5408/ADG5409 high voltage switches allow single-supply operation from 9 V to 40 V and dual-supply operation from ±9 V to ±22 V. The ADG5408/ADG5409 (as well as select devices within the same family) achieve an 8 kV human body model ESD rating that provides a robust solution eliminating the need for separate protect circuitry designs in some applications. Rev. 0 | Page 20 of 24 ADG5408/ADG5409 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.30 0.19 0.65 BSC COPLANARITY 0.10 0.75 0.60 0.45 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 37. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters PIN 1 INDICATOR 4.10 4.00 SQ 3.90 0.35 0.30 0.25 0.65 BSC 16 13 PIN 1 INDICATOR 12 1 EXPOSED PAD 2.70 2.60 SQ 2.50 4 9 0.80 0.75 0.70 0.45 0.40 0.35 8 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 5 0.25 MIN BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WGGC. 012909-B TOP VIEW Figure 38. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm Body, Very Very Thin Quad (CP-16-17) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADG5408BRUZ ADG5408BRUZ-REEL7 ADG5408BCPZ-REEL7 ADG5409BRUZ ADG5409BRUZ-REEL7 ADG5409BCPZ-REEL7 1 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Z = RoHS Compliant Part. Rev. 0 | Page 21 of 24 Package Option RU-16 RU-16 CP-16-17 RU-16 RU-16 CP-16-17 ADG5408/ADG5409 NOTES Rev. 0 | Page 22 of 24 ADG5408/ADG5409 NOTES Rev. 0 | Page 23 of 24 ADG5408/ADG5409 NOTES ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09206-0-9/10(0) Rev. 0 | Page 24 of 24