TI SN65LVDS94DGG

SN65LVDS94
LVDS SERDES RECEIVER
SLLS298E – MAY 1998 – REVISED FEBRUARY 2000
D
D
D
D
D
D
D
D
D
D
D
D
D
D
4:28 Data Channel Expansion at up to
1.820 Gigabits per Second Throughput
Suited for Point-to-Point Subsystem
Communication With Very Low EMI
4 Data Channels and Clock Low-Voltage
Differential Channels in and 28 Data and
Clock Out Low-Voltage TTL Channels Out
Operates From a Single 3.3-V Supply and
250 mW (Typ)
5-V Tolerant SHTDN Input
Rising Clock Edge Triggered Outputs
Bus Pins Tolerate 4-kV HBM ESD
Packaged in Thin Shrink Small-Outline
Package With 20 Mil Terminal Pitch
Consumes <1 mW When Disabled
Wide Phase-Lock Input Frequency Range
20 MHz to 65 MHz
No External Components Required for PLL
Meets or Exceeds the Requirements of
ANSI EIA/TIA-644 Standard
Industrial Temperature Qualified
TA = – 40°C to 85°C
Replacement for the DS90CR286
description
DGG PACKAGE
(TOP VIEW)
D22
D23
D24
GND
D25
D26
D27
LVDSGND
A0M
A0P
A1M
A1P
LVDSVCC
LVDSGND
A2M
A2P
CLKINM
CLKINP
A3M
A3P
LVDSGND
PLLGND
PLLVCC
PLLGND
SHTDN
CLKOUT
D0
GND
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
VCC
D21
D20
D19
GND
D18
D17
D16
VCC
D15
D14
D13
GND
D12
D11
D10
VCC
D9
D8
D7
GND
D6
D5
D4
D3
VCC
D2
D1
31
The SN65LVDS94 LVDS serdes (serializer/des27
30
erializer) receiver contains four serial-in 7-bit
28
29
parallel-out shift registers, a 7× clock synthesizer,
and five low-voltage differential signaling (LVDS)
line receivers in a single integrated circuit. These
functions allow receipt of synchronous data from
a compatible transmitter, such as the SN65LVDS93 and SN65LVDS95, over five balanced-pair conductors and
expansion to 28 bits of single-ended LVTTL synchronous data at a lower transfer rate.
When receiving, the high-speed LVDS data is received and loaded into registers at the rate seven times the
LVDS input clock (CLKIN). The data is then unloaded to a 28-bit wide LVTTL parallel bus at the CLKIN rate. A
phase-locked loop clock synthesizer circuit generates a 7× clock for internal clocking and an output clock for
the expanded data. The SN65LVDS94 presents valid data on the rising edge of the output clock (CLKOUT).
The SN65LVDS94 requires only five line termination resistors for the differential inputs and little or no control.
The data bus appears the same at the input to the transmitter and output of the receiver with the data
transmission transparent to the user(s). The only user intervention is the possible use of the shutdown/clear
(SHTDN) active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A
low level on this signal clears all internal registers to a low level.
The SN65LVDS94 is characterized for operation over ambient air temperatures of – 40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
SN65LVDS94
LVDS SERDES RECEIVER
SLLS298E – MAY 1998 – REVISED FEBRUARY 2000
functional block diagram
Serial-In/Parallel-Out
Shift Register
A0P
Serial In
A,B, ...G
A0M
CLK
Serial-In/Parallel-Out
Shift Register
A1P
Serial In
A,B, ...G
A1M
CLK
Serial-In/Parallel-Out
Shift Register
A2P
Serial In
A,B, ...G
A2M
CLK
Serial-In/Parallel-Out
Shift Register
A3P
Serial In
A,B, ...G
A3M
CLK
Control Logic
SHTDN
D0
D1
D2
D3
D4
D6
D7
D8
D9
D12
D13
D14
D15
D18
D19
D20
D21
D22
D24
D25
D26
D27
D5
D10
D11
D16
D17
D23
7× Clock/PLL
CLK
CLKINP
Clock In
Clock Out
CLKINM
2
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CLKOUT
SN65LVDS94
LVDS SERDES RECEIVER
SLLS298E – MAY 1998 – REVISED FEBRUARY 2000
CLKIN
Previous Cycle
Current Cycle
A0
Next Cycle
D7
D6
D4
D3
D2
D1
D0
D7+1
D18
D15
D14
D13
D12
D9
D8
D18+1
D26
D25
D24
D22
D21
D20
D19
D26+1
D23
D17
D16
D11
D10
D5
D27
D23+1
D0-1
A1
D86-1
A2
D19-1
A3
D27-1
CLKOUT
Dn
Dn-1
Dn
Dn+1
Figure 1. SN65LVDS94 Load and Shift Sequences
equivalent input and output schematic diagrams
VCC
300 kΩ
VCC
300 kΩ
50 Ω
AnP
AnM
50 Ω
D Output
SHTDN
7V
7V
VCC
7V
7V
300 kΩ
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3
SN65LVDS94
LVDS SERDES RECEIVER
SLLS298E – MAY 1998 – REVISED FEBRUARY 2000
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V
Voltage range at any terminal (except SHTDN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Voltage range at SHTDN terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 3 V
Electrostatic discharge (see Note 2): Bus pins (Class 3A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 KV
Bus pins (Class 2B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 V
All pins (Class 3A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 KV
All pins (Class 2B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 V
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (see Dissipation Rating Table)
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to the GND terminals unless otherwise noted.
2. This rating is measured using MIL-STD-883C Method, 3015.7.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR‡
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
DGG
1377 mW
11 mW/°C
882 mW
717 mW
‡ This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
recommended operating conditions
MIN
NOM
Supply voltage, VCC
3
3.3
High-level input voltage (SHTDN), VIH
2
Low-level input voltage (SHTDN), VIL
MAX
UNIT
3.6
V
V
0.8
Ť Ť
Magnitude of differential input voltage, VID
0.1
V
V
ID
2
Operating free–air temperature, TA
Ť Ť
0.6
V
Common–mode input voltage, VIC (see Figures 2 and 3)
V
2.4
ID
2
VCC–0.8
85
– 40
V
°C
timing requirements
tc§
Input clock period
§ tc is defined as the mean duration of a minimum of 32,000 clock periods.
4
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MIN
NOM
MAX
15.4
tc
50
UNIT
Vns
SN65LVDS94
LVDS SERDES RECEIVER
SLLS298E – MAY 1998 – REVISED FEBRUARY 2000
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT+
VIT–
Positive-going differential input voltage threshold
VOH
VOL
High-level output voltage
MIN
–100
IOH = –4 mA
IOL = 4 mA
2.4
IIH
IIL
Quiescent current (average)
Enabled, AnP at 1 V and AnM at 1.4 V,
tc = 15.38 ns
High-level input current (SHTDN)
Enabled, CL = 8 pF (5 places),
Worst-case pattern (see Figure 4),
tc = 15.38 ns
VIH = VCC
Low-level input current (SHTDN)
UNIT
mV
V
Disabled, all inputs open
ICC
MAX
100
Negative-going differential input voltage threshold‡
Low-level output voltage
TYP†
62
0.4
V
280
µA
84
mA
107
VIL = 0 V
0 V ≤ VI ≤ 2.4 V
mA
±20
µA
±20
µA
IIN
Input current (A inputs)
±20
µA
IOZ
High-impedance output current
VO = 0 V or VCC
±10
µA
† All typical values are VCC = 3.3 V, TA = 25°C.
‡ The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet for the negative-going
input voltage threshold only.
switching characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
tsu
TEST CONDITIONS
Data setup time, D0 through D27 to
CLKOUT
CL = 8 pF
MIN
TYP†
4
6
4
6
490
800
See Figure 5
Data hold time, CLKOUT to D0 through
D27
tRSKM
Receiver input skew margin
g §
(see Figure 7)
tc = 15.38 ns ((±0.2%),
),
|Input clock jitter| <50 ps¶
td
Delay time, input clock to output clock
(see Figure 7)
tc = 15.38 ns (±0.2%)
3.7
tc = 15.38 + 0.75 sin (2π500E3t)±0.05 ns,
See Figure 7
±80
∆tC(O)
Change
g in output clock period from cycle
y
to cycle#
ten
tdis
UNIT
ns
th
TA = 0°C to 85°C
TA = – 40°C to 0°C
MAX
390
tc = 15.38 + 0.75 sin (2≠3E6t) ±0.05 ns,
See Figure 7
ps
ns
ps
±300
Enable time, SHTDN to phase lock
See Figure 8
1
ms
Disable time, SHTDN to Off state
See FIgure 9
400
ns
tt
Output transition time (tr or tf)
CL = 8 pF
3
tw
Output clock pulse duration
0.43 tc
§ tRSKM is the timing margin available to allocate to the transmitter and interconnection skews and clock jitter. It is defined by
ns
ns
tc
–tsńh.
14
¶ |Input clock jitter| is the magnitude of the change in the input clock period.
# ∆tC(O) is the change in the output clock period from one cycle to the next cycle observed over 15,000 cycles.
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5
SN65LVDS94
LVDS SERDES RECEIVER
SLLS298E – MAY 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
AP
VID
(VIAP + VIAM)/2
VIC
AM
VIAP
VIAM
Figure 2. Voltage Definitions
COMMON-MODE INPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE AND VCC
2.5
VIC – Common-Mode Input Voltage – V
MAX at >3.15 V
MAX at 3 V
2
1.5
1
0.5
MIN
0
0
0.1
0.2
0.3
0.4
0.5
0.6
|VID|– Differential Input Voltage and VCC – V
Figure 3. Recommended VIC Versus VID and VCC
6
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SN65LVDS94
LVDS SERDES RECEIVER
SLLS298E – MAY 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
T
CLKIN/
CLKOUT
EVEN Dn
ODD Dn
Figure 4. Worst-Case Power Test Pattern
‡ The worst-case test pattern produces nearly the maximum switching frequency for all of the LV-TTL outputs.
tsu
VOH
70%
D0–27
30%
VOL
th
VOH
70%
CLKOUT
30%
VOL
Figure 5. Setup and Hold Time Measurements
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7
SN65LVDS94
LVDS SERDES RECEIVER
SLLS298E – MAY 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
Tektronix
HFS9003/HFS9DG1
Stimulus System
(Repeating Patterns
1110111 and 0001000)
An
D0–D27
DUT
CLKIN
Tektronix Microwave
Logic Multi-BERT-100RX
Word Error Detector
CLKOUT
CLKIN is advanced or delayed with respect to data until errors are observed at the receiver outputs.
The magnitude of the advance or delay is tRSKM.
tc
4/7 tc ± tRSKM
3/7 tc ± tRSKM
ts
th
An
and An
CLKIN
7×CLK
(Internal)
td
CLKOUT
tr < 1 ns
≅ 300 mV
90%
CLKIN or An
0V
10%
≅ –300 mV
VOH
CLKOUT
1.4 V
VOL
Figure 6. Receiver Input Skew Margin and td Definitions
8
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SN65LVDS94
LVDS SERDES RECEIVER
SLLS298E – MAY 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
Reference
+
Σ
Device
Under
Test
VCO
+
Modulation
v(t) = A sin(2πfmodt)
HP8656B Signal
Generator,
0.1 MHz–990 MHz
RF Output
HP8665A Synthesized
Signal Generator,
0.1 MHz–4200 MHz
Modulation Input
Device Under
Test
CLKIN
Output
CLKOUT
DTS2070C
Digital Time
Scope
Input
Figure 7. Output Clock Jitter Test Setup
CLKIN
An
ten
SHTDN
Dn
Invalid
Valid
Figure 8. Enable Time Waveforms
CLKIN
tdis
SHTDN
CLKOUT
Figure 9. Disable Time Waveforms
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9
SN65LVDS94
LVDS SERDES RECEIVER
SLLS298E – MAY 1998 – REVISED FEBRUARY 2000
TYPICAL CHARACTERISTICS
WORST-CASE SUPPLY CURRENT
vs
FREQUENCY
140
I CC – Supply Current – mA
120
100
ÁÁ
ÁÁ
VCC = 3.6 V
80
VCC = 3 V
VCC = 3.3 V
60
40
20
0
30
40
50
60
f – Frequency – MHz
Figure 10
10
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70
SN65LVDS94
LVDS SERDES RECEIVER
SLLS298E – MAY 1998 – REVISED FEBRUARY 2000
APPLICATION INFORMATION
16-bit bus extension
In a 16-bit bus application (Figure 11), TTL data and clock coming from bus transceivers that interface the
backplane bus arrive at the Tx parallel inputs of the LVDS serdes transmitter. The clock associated with the bus
is also connected to the device. The on-chip PLL synchronizes this clock with the parallel data at the input. The
data is then multiplexed into three different line drivers which perform the TTL to LVDS conversion. The clock
is also converted to LVDS and presented to a separate driver. This synchronized LVDS data and clock at the
receiver, which recovers the LVDS data and clock, performs a conversion back to TTL. Data is then
demultiplexed into a parallel format. An on-chip PLL synchronizes the received clock with the parallel data, and
then all are presented to the parallel output port of the receiver.
16-Bit
BTL Bus
Interface
SN74FB2032
SN74FB2032
CLK
TTL
Interface
LVDS
Interface
0 To 10 Meters
(Media Dependent)
SN75L0DS93
SN75LV0S94
TTL
Interface
D0–D7 8
8
D8–D15 8
8 D8–D15
D0–D7
16-Bit
BTL Bus
Interface
SN74FB2032
SN74FB2032
XMIT Clock
RCV Clock
CLK
Backplane
Bus
Backplane
Bus
Figure 11. 16-Bit Bus Extension
16-bit bus extension with parity
In the previous application we did not have a checking bit that would provide assurance that the data crosses
the link. If we add a parity bit to the previous example, we would have a diagram similar to the one in Figure 12.
The device following the SN74FB2032 is a low cost parity generator. Each transmit-side transceiver/parity
generator takes the LVTTL data from the corresponding transceiver, performs a parity calculation over the byte,
and then passes the bits with its calculated parity value on the parallel input of the LVDS serdes transmitter.
Again, the on-chip PLL synchronizes this transmit clock with the eighteen parallel bits (16 data + 2 parity) at the
input. The synchronized LVDS data/parity and clock arrive at the receiver.
The receiver performs the conversion from LVDS to LVTTL and the transceiver/parity generator performs the
parity calculations. These devices compare their corresponding input bytes with the value received on the parity
bit. The transceiver/parity generator will assert its parity error output if a mismatch is detected.
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11
SN65LVDS94
LVDS SERDES RECEIVER
SLLS298E – MAY 1998 – REVISED FEBRUARY 2000
APPLICATION INFORMATION
16-Bit
BTL Bus
Interface
LVDS
Interface
0 To 10 Meters
(Media Dependent)
TTL
Interface
W/Parity
TTL
Interface
SN75LVDS93
SN74FB2032
9 Bit Latchable
Transceiver/ With
Parity Generator
8
Parity
Parity
8
D8–D15
SN74FB2032
9 Bit Latchable
Transceiver/ With
Parity Generator
TTL
Interface
16-Bit
BTL Bus
Interface
SN75LVDS94
8
D0–D7
TTL
Interface
W/Parity
D0–D7
9 Bit Latchable
Transceiver/ With
Parity Generator
8
Parity
Parity
SN74FB2032
D8–D15
9 Bit Latchable
Transceiver/ With
Parity Generator
SN74FB2032
Parity
Error
CLK
XMIT Clock
CLK
RCV Clock
Backplane
Bus
Backplane
Bus
Figure 12. 16-Bit Bus Extension With Parity
low cost virtual backplane transceiver
Figure 13 represents LVDS serdes in an application as a virtual backplane transceiver (VBT). The concept of
a VBT can be achieved by implementing individual LVDS serdes chipsets in both directions of subsystem
serialized links.
Depending on the application, the designer will face varying choices when implementing a VBT. In addition to
the devices shown in Figure 13, functions such as parity and delay lines for control signals could be included.
Using additional circuitry, half-duplex or full-duplex operation can be achieved by configuring the clock and
control lines properly.
The designer may choose to implement an independent clock oscillator at each end of the link and then use
a PLL to synchronize LVDS serdes’s parallel I/O to the backplane bus. Resynchronizing FIFOs may also be
required.
Bus
Transceivers
LVDS Serdes
Transmitter
TTL
Inputs
Up To
21 or 28
Bits
Backplane
Bus
Bus
Transceivers
LVDS Serdes
Receiver
TTL
Outputs
Up To
21 or 28
Bits
LVDS
Serial Links
4 or 5
Pairs
LVDS Serdes
Transmitter
Bus
Transceivers
LVDS Serdes
Receiver
Figure 13. Virtual Backplane Transceiver
12
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Backplane
Bus
Bus
Transceivers
SN65LVDS94
LVDS SERDES RECEIVER
SLLS298E – MAY 1998 – REVISED FEBRUARY 2000
MECHANICAL DATA
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PIN SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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13
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pertaining to warranty, patent infringement, and limitation of liability.
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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Copyright  2000, Texas Instruments Incorporated