ROHM BD9882F

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STRUCTURE
Silicon Monolithic Integrated Circuit
NAME OF PRODUCT
DC-AC Inverter Control IC
TYPE
BD9882F, BD9882FV
FUNCTION
・1ch control with Push-Pull
・Lamp current and voltage sense feed back control
・Sequencing easily achieved with Soft Start Control
・Short circuit protection with Timer Latch
・Under Voltage Lock Out
・Short circuit protection with over voltage
・Mode-selectable the operating or stand-by mode by stand-by pin
・Synchronous operating the other BD9882F or BD9882FV IC’s
・BURST mode controlled by PWM and DC input
○Absolute Maximum Ratings(Ta = 25℃)
Parameter
Supply Voltage
Operating Temperature Range
Storage Temperature Range
Power Dissipation
Maximum Junction Temperature
*1
*2
Symbol
VCC
Topr
Tstg
Pd
Tjmax
Limits
15
-40~+95
-55~+125
550*1(BD9882F)
650*2(BD9882FV)
+125
Unit
V
℃
℃
mW
℃
Pd derate at 5.5mW/℃ for temperature above Ta = 25℃ (When mounted on a PCB 70.0mm×70.0mm×1.6mm)
Pd derate at 6.5mW/℃ for temperature above Ta = 25℃ (When mounted on a PCB 70.0mm×70.0mm×1.6mm)
〇Recommended operating condition
Parameter
Supply voltage
CT oscillation frequency
BCT oscillation frequency
Symbol
Vcc
fCT
fBCT
Status of this document
The Japanese language version of this document shall be the official specification.
Any translation of this document shall be for reference only.
REV. A
Limits
5.0~14.0
20~150
0.10~0.50
Unit
V
kHz
kHz
2/4
○Electric Characteristics(Ta=25℃,VCC=7V)
Parameter
((WHOLE DEVICE)
)
Operating current
Stand-by current
((OVER VOLTAGE DETECT))
FB over voltage detect voltage
((STAND-BY CONTROL))
Stand-by voltage H
Stand-by voltage L
((TIMER LATCH))
Timer Latch voltage
Timer Latch current
((OSC BLOCK))
OSC constant current
MIN.
Limits
TYP.
MAX.
Icc1
Icc2
-
-
8
2
16
10
mA
μA
Vovf
2.20
2.40
2.60
V
VstH
VstL
1.8
-0.3
-
-
VCC
0.8
V
V
Vcp
Icp
1.9
0.5
2.0
1.0
2.1
1.5
V
μA
Symbol
Unit
Conditions
CT=0.5V
System ON
System OFF
ICT
1.35/RT
1.5/RT
1.65/RT
A
OSC Max voltage
VoscH
1.8
2.0
2.2
V
fCT=60kHz
OSC Min voltage
MAX DUTY
VoscL
MAXDUTY
0.3
44
0.5
46.5
0.7
49
V
%
fCT=60kHz
fCT=60kHz
Iss
1.0
2.0
3.0
μA
Visc
Vss
RSRT
0.45
2.0
-
0.50
2.2
200
0.55
2.4
400
V
V
Ω
VuvloH
VuvloL
4.000
3.800
4.200
4.000
4.400
4.200
V
V
IS threshold voltage
Vis
1.225
1.250
1.275
V
VS threshold voltage
IS source current 1
IS source current 2
VS source current
((Output BLOCK)
)
Output voltage H
Output voltage L
Output sink resistance
Output source resistance
Drive output frequency
((BURST MODE))
BOSC Max voltage
BOSC Min Voltage
BOSC constant current
BOSC frequency
((REG BLOCK))
REG output voltage
REG source current
((COMP BLOCK))
Over voltage detect
Under voltage detect
((FAIL PIN))
Normal output voltage
Protect output voltage
Protect cancel voltage detect
Vvs
1.220
1.250
1.280
V
Iis1
Iis2
Ivs
-
13.0
-
-
20.0
-
1.5
27.0
1.0
μA
μA
μA
VoutNH
VoutNL
RsinkN
RsourceN
FN
VCC-0.3
-
-
-
58.5
VCC-0.1
0.1
8
10
60.0
-
0.3
16
20
61.5
V
V
Ω
Ω
kHz
VburH
VburL
Iburosc
FBOSC
1.94
0.4
1.35/BRT
261
2.0
0.5
1.5/BRT
275
2.06
0.6
1.65/BRT
289
V
V
A
Hz
VREG
IREG
3.038
5.0
3.100
-
3.162
-
V
mA
VCOMPH
VCOMPL
2.20
0.590
2.5
0.640
2.80
0.690
V
V
VPH
VPL
VFAIL
0.45
2.9
0.36
0.5
3.1
0.40
0.55
3.3
0.44
V
V
V
Soft start current
IS COMP detect Voltage
SS COMP detect voltage
SRT ON resistance
((UVLO BLOCK))
Operating voltage
Shut down voltage
((FEED BACK BLOCK))
(This product is not designed for normal operation with in a radio active environment.)
REV. A
DUTY=2.0V
DUTY=0V、IS=0.5V
Isink = 10mA
Isource = 10mA
RT=18kΩ CT=400pF
fBCT=0.2kHz
fBCT=0.2kHz
BRT=33kΩ BCT=0.051μF
3/4
〇Package Dimensions
Device Mark
(Include BURR 12.85)
BD9882F
BD9882FV
1
Lot No.
SSOP-B20 (Unit:mm)
SOP20 (Unit:mm)
〇Block Diagram
〇Pin Description
SS
CT
RT
BRT BCT
DUTY
VCC
+
OSC
STB
STB
BLOCK
PWM
BLOCK
LOGIC
BLOCK
+
VCC
-
-
OUTPUT
BLOCK
N1
N2
UVLO
VCC
REG
Reg
BLOCK
VS
IS
PROTECT
BLOCK
GND
COMP
1
DUTY
2
BRT
3
BCT
4
RT
5
SRT
6
CT
External resistor from BRT to GND for
adjusting the BURST triangle oscillator
External capacitor from BCT to GND for
adjusting the BURST triangle oscillator
External resistor from SRT to RT for
adjusting the triangle oscillator
External resistor from SRT to RT for
adjusting the triangle oscillator
External capacitor from CT to GND for
adjusting the triangle oscillator
7
GND
GROUND
8
FB
Error amplifier output
FAIL
+
+
Pin
Name
PGND
F/B
BLOCK
VS
-
SYSTEM ON/OFF
FB
IS
BOSC
Pin No.
SCP
SRT
Control PWM mode and BURST mode
9
IS
Error amplifier input①
10
VS
Error amplifier input②
11
STB
Stand-by switch
12
COMP
Under, over voltage detect
13
REG
14
SS
15
SCP
Internal regulator output
External capacitor from SS to GND for Soft
Start Control
External capacitor from SCP1 to GND for
Timer Latch
16
N2
FET driver
17
PGND
Ground for FET drivers
FET driver
18
N1
19
FAIL
Protect clock output
Vcc
Supply voltage input
20
REV. A
Function
4/4
〇NOTE FOR USE
1. When designing the external circuit, including adequate margins for variation between external devices and the IC.Use
adequate margins for steady state and transient characteristics.
2. Recommended Operating Range
The circuit functionality is guaranteed within of ambient temperature operation range as long as it is within
recommended operating range. The standard electrical characteristic values cannot be guaranteed at other voltages
in the operating ranges, however, the variation will be small.
3. Mounting failures, such as misdirection or miscounts, may harm the device.
4. A strong electromagnetic field may cause the IC to malfunction.
5.
The GND pin should be the location within
±0.3V compared with the PGND pin
6. The BD9882F and BD9882FV incorporate a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit
(TSD circuit) is designed only to shut the IC off to prevent runaway thermal operation. It is not designed to protect
the IC or guarantee its operation. Do not continue to use the IC after operating this circuit or use the IC in an
environment where the operation of the thermal shutdown circuit is assumed.
7. Absolute maximum ratings are those values that, if exceeded, may cause the life of a device to become significantly
shortened. Moreover, the exact failure mode caused by short or open is not defined. Physical countermeasures, such
as a fuse, need to be considered when using a device beyond its maximum ratings.
8.About the external FET, the parasitic Capacitor may cause the gate voltage to change, when the drain voltage is switching.
Make sure to leave adequate margin for this IC variation.
9. On operating Slow Start Control (SS is less than 2.2V), It does not operate Timer Latch.
10. By STB voltage, BD9882F and BD9882FV are changed to 2 states. Therefore, do not input STB pin voltage between one
state and the other state (0.8~1.8V).
11.The pin connected a connector need to connect to the resistor for electrical surge destruction.
12.This IC is a monolithic IC which (as shown is Fig-1)has P+ substrate and between the various pins. A P-N junction
is formed from this P layer of each pin. For example, the relation between each potential is as follows,
○(When GND > PinB and GND > PinA, the P-N junction operates as a parasitic diode.)
○(When PinB > GND > PinA, the P-N junction operates as a parasitic transistor.)
Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can result in
mutual
interference among circuits as well as operation faults and physical damage. Accordingly you must not
use methods by which parasitic diodes operate, such as applying a voltage that is lower than the GND (P substrate)
voltage to an input pin.
Transistor (NPN)
Resistance
(PinA)
(PinB)
B
E
C
C
GND
P
P+
N
P+
N
N
N
N
P substrate
GND
Parasitic diode
N
P substrate
GND
Parasitic diode
(PinB)
(PinA)
B
Parasitic diode
CC
B
EE
GND
GND
Other adjacent components
Parasitic diode
Fig-1 Simplified structure of a Bipolar IC
REV. A
Notice
Notes
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illustrate the standard usage and operations of the Products. The peripheral conditions must
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