Large Current External FET Controller Type Switching Regulators Single-output Step-up,High-efficiency Switching Regulator (Controller Type) BD9763FVM No.09028EAT07 ●Description BD9763FVM is a 1-channel high efficiency step-up switching regulator. It is possible to choose small application space due to its high-speed operation (Max switching frequency 1.2MHz) ●Features 1) Build-in under voltage lock out circuit. 2) High accuracy reference voltage (2.5V±1.0%) 3) Establish maximum duty cycle internally. 4) CTL/SS terminal for both stand-by and soft-start function. (Soft-start time can be set by external capacitor) 5) MSOP8 thin and small package. ●Applications Single-lens reflex cameras, digital video cameras, liquid crystal modules, DVD drive. ●Absolute Maximum Ratings(Ta=25℃) Parameter Symbol Limit Unit Supply voltage Vcc 10 V Storage temperature range Tstg -55 to +150 ℃ Pd 587 * mW Tjmax +150 ℃ Power dissipation Junction temperature * IC mounted on a PCB board (70mm x 70mm x 1.6mm, glass epoxy). Reduced by 4.7mW for each increase in Ta of 1℃ over 25℃. ●Recommended Operating Conditions Parameter Symbol Limit Min Typ Max Unit Supply voltage Vcc 4 7 9 V Oscillating frequency fosc 100 - 1200 kHz Operating temperature range Topr -40 - +85 ℃ www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 1/11 2009.05 - Rev.A Technical Note BD9763FVM ●Electrical characteristics (Unless otherwise specified, Ta=25℃, Vcc=7.0V) Limits Parameter Symbol Min Typ Max Unit Condition 【Oscillator】 Oscillating frequency fosc 522 600 678 kHz Frequency tolerance FDV -5 0 5 % Swing voltage Vpptr － 0.5 － V CTL/SS pin source current ISS -1.90 -1.00 -0.55 µA CTL/SS pin clamp voltage VSS 2.2 2.4 2.6 V VCTLTH 1.2 1.3 1.4 V 0% threshold voltage D0 1.5 1.6 1.7 V Maximum duty cycle DMAX 80 90 99.5 % Threshold voltage VIN 0.98 1.00 1.02 V Band width BW － 3.0 － MHz RRT=24kΩ Vcc=4 to 9V 【Stand-by, Soft start】 CTL threshold voltage VCTL/SS=1.5V 【PWM comparator】 【Error amplifier】 Voltage gain Av － 70 － dB Input bias current IIB -150 -70 － nA Maximum output voltage VCH 2.3 2.4 2.6 V Minimum output current AV=0dB VCL － 0.03 0.20 V Output source current IOI -3.1 -1.6 -1.0 mA VFB=1.0V Output sink current IOO 12 50 125 mA VFB=1.0V Output voltage VREF 2.475 2.500 2.525 V IVREF=0mA Load regulation △VREFlo - - 10 mV IVREF -45 -16 -1 mA Stand-by current ICCS 420 610 960 µA Circuit current ICCA 3.4 5.0 7.8 mA ON resistance RON 0.9 2.5 8.0 Ω Output rise/fall time Tr/Tf － 20 － nsec Output source current IOUTSO － -0.80 － A Ta=-40 to 85℃,VCC=4 to 9V, OUT=0V，rush current Output sink current IOUTSI － 0.85 － A Ta=-40 to 85℃,VCC=4 to 9V, OUT=VCC，rush current VUT 3.7 3.8 3.9 V Vcc sweep down VUThy 0.05 0.10 0.15 V 【Reference voltage】 Output short current IVREF=0 to -1mA 【Whole device】 No load 【Output】 Cout=1000pF 【Under voltage lock out】 Threshold voltage Hysteresis width www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 2/11 2009.05 - Rev.A Technical Note BD9763FVM ●Reference data (Unless otherwise specified, Ta=25℃) Oscillating frequency vs. Timing resistance VREF voltage vs. Ambient temperature 10000 Oscillating frequency [kHz] VREF voltage [V] 2.53 2.52 2.51 2.5 2.49 2.48 2.47 -60 -40 -20 0 20 40 60 80 100 120 140 1000 100 1 10 Ambient temperature [℃] Fig.1 VREF voltage – Ambient temperature Oscillating frequency vs. Ambient temperature 1200 640 Oscillating frequency [kHz] Oscillating frequency [kHz] 650 RT=24kΩ 620 610 600 590 580 570 560 550 -60 1000 Fig.2 Oscillating frequency – Timing resistance (RRT) Oscillating frequency vs. Ambient temperature 630 100 Timing resistance (RT) [kΩ] -40 -20 0 20 40 60 80 100 120 1180 1160 1140 1120 1100 1080 1060 1020 1000 -60 140 RT=10kΩ 1040 -40 -20 Ambient temperature [℃] 0 20 40 60 80 100 120 140 Ambient temperature [℃] Fig.3 Oscillating frequency – Ambient temperature (RT=24kΩ) Fig.4 Oscillating frequency – Ambient temperature (RT=10kΩ) ●Block diagram VCC 1 U.V.L.O VREF RT 8 4 VCC Vref TRI INV 5 Error 1.0V FB Amp 2 OUT Clamper PWM VREF Vdt COMP 6 T.S.D 7 3 CTL/SS GND Fig.5 www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 3/11 2009.05 - Rev.A Technical Note BD9763FVM ●Pin configuration VCC 1pin RT 8pin 2pin OUT CTL/SS 7pin 3pin GND FB 6pin 4pin VREF INV 5pin Fig.6 ●Pin number , Pin name Pin No. Pin name Function 1 VCC Power supply 2 OUT FET driver output 3 GND Ground 4 VREF Reference voltage (2.5V±1%) output 5 INV Inverting input of error amplifier 6 FB Output of error amplifier 7 CTL/SS 8 RT Stand-by switch/Soft start capacitor connecting pin Timing resistor connecting pin ●Block description ・VOLTAGE REFERENCE(VREF) BLOCK This voltage reference block generates 2.5V internal reference voltage. ・OSCILLATOR BLOCK Oscillator block sets the oscillating frequency adjusted by an external resistance in RT pin. The oscillating frequency can be set within a range of 100~1200kHz.. (See the description of how to set the frequency on page6.) ・PWM COMP The PWM comparator transforms the voltage outputted from error amp to PWM waveform and outputs to FET driver. The maximum duty cycle is limited up to 90%. ・ERROR AMP BLOCK The error amp block detects the output voltage from the INV pin, amplifies the difference between the detected voltage and the reference voltage, and outputs it to FB pin. The reference voltage is 1V±2%. ・PROTECTION CIRCUIT BLOCK The under voltage lock out circuit is activated to shut down the whole circuit when the VCC voltage is up to 3.8V. When the thermal shutdown circuit detects abnormal heating of the chip (150℃), the output becomes off. And the output turns back on when the chip temperature goes down to a specific level. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 4/11 2009.05 - Rev.A Technical Note BD9763FVM ●Application example R1 VOUT VCC C1 ＊ C2 ＊ 1μF VCC RT OUT CTL/SS GND FB VREF INV R2 ＊RRT ON/OFF H:OFF L:ON Fig.7 ●Selecting application components (1) Output inductor It is recommended to use an inductor which satisfies the following rating current (the following value of current), and also has low DCR. The shield type inductor is preferable. I peak = Io･(Vo/VIN) / η + VIN･(VOUT-VIN) / (2･VOUT･L･f) [A] [ Io : Output Vo : Output voltage VIN : Input voltage η : Efficiency L : Inductance f : Oscillating frequency ] (2) Output capacitor It is recommended to use the output capacitor which has the enough margin to maximum rating for output voltage and low fluctuation for temperature. The ripple voltage of the output is influenced by ESR of the output capacitor. Vripple = VIN･(VOUT-VIN) / (VOUT･L･f)･ESR [V] (f >> 1 / (2π√LC)･Vo / VIN) [ Io : Output Vo : Output voltage VIN : Input voltage η : Efficiency L : Inductance C : Output capacitor f : Oscillating frequency ] (3) FET It is recommended to use FETs which satisfy followings and have small Ciss or Qg and ON resistance. D-S Voltage : Over (Output voltage + Vf of Di) G-S Voltage : Over input voltage D-S Current : Over Ipeak at the section of output inductor (4) Diode It is recommended to use a schottky diode which satisfies followings and has low forward voltage drop and high switching speed. Maximum current : Over maximum output current Direct reverse voltage : Over output voltage * Please provide sufficient margin in the choice of external components by factoring into the worst case characteristics and temperature range. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 5/11 2009.05 - Rev.A Technical Note BD9763FVM (5) Setting the oscillator frequency Refer to Fig.5 and determine Timing resistor (RRT) when setting the oscillating frequency. Oscillating frequency [kHz] Oscillating frequency vs. Timing resistance 10000 1000 100 1 10 100 1000 Timing resistance (RT) [kΩ] Fig.8 Oscillating frequency – Timing resistance (RRT) (6) Setting the output voltage The output voltage is calculated by the following equation. Vo = VINVth･(R1+R2)/R2 [V] R1,R2 : Resistor divider network VINth : Error amp threshold voltage (typ.1V) (but Vo<VIN･5 because of MAXDUTY Min=80%) (7) CTL/SS setting the soft start time The time after CTL/SS is released before the output voltage starts to rise. t(start) = CCTL･(VDo-Voff)/Iss [S] approximated equation The time after the output voltage starts up before it reaches the specified output level. t(soft) = CCTL･(VDUTY-VDo)/Iss [S] approximated equation VDUTY = VDo+0.5･(1-VIN/VOUT) [V] CCTL : CTL/SS–GND capacitande Vdo : 0% duty threshold (Typ 1.6V) Voff : Output off CTL/SS voltage Iss : CTL/SS charge current (Typ 1uA) VDUTY : stabilization operating ON duty. ●Timing chart FB terminal voltage CTL/SS terminal voltage Dead-time setting voltage Oscillator output Stand-by threshold voltage t(start) t(soft) VDUTY Output waveform ON/OFF Fig.9 www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 6/11 2009.05 - Rev.A Technical Note BD9763FVM ●Recommended board patterns R1 VOUT R2 Di Lay out by the shortest pattern. FET L VCC ＊C1 VCC OUT ＊ C2 Short GNDs at one point as this figure. 1μF ＊ RT RRT CTL/SS GND FB VREF INV H:OFF L:ON *Place these parts with attention about patterns shown in following Fig.7 Fig.10 RT VCC RRT VCC OUT C1 RT OUT CTL/SS C1 GND GND FB VREF INV C2 VREF C1 : Capacitor terminals have to be close enough to terminals of VCC and GND. It is safe to pass OUT signal line under C1. C2 : Capacitor terminals have to be close enough to terminals of VREF and GND. R1 : Pattern area has to be small enough to reduce parasitic capacitance of RT terminal. Fig.11 Recommended board patterns www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 7/11 2009.05 - Rev.A Technical Note BD9763FVM ●I/O Equivalent Circuit OUT (2) VREF (4) VCC VCC 1.67k 50k VREF OUT ～ ～ 250k 200k GND 193k GND INV (5) FB (6) VCC VCC FB 20p INV 200k GND GND CTL/SS (7) VCC 20k RT (8) 5k CTL/SS 100k 500k VREF 1k 1k RT GND GND Fig.12 www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 8/11 2009.05 - Rev.A Technical Note BD9763FVM ●Operation Notes (1) Absolute maximum ratings Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range may result in IC deterioration or damage. Assumptions should not be made regarding the state of the IC(short mode or open mode) when such damage is suffered. A physical safety measure such as fuse should be implemented when use of the IC in a special mode where the absolute maximum ratings may be exceeded is anticipated. (2) GND potential Ensure a minimum GND pin potential in all operating conditions. In addition, ensure that no pins other than the GND pin. Carry a voltage lower then or equal to the GND pin, including during actual transient phenomena. (3) Thermal design Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions. (4) Inter-pin shorts and mounting errors Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result in damage to the IC. Shorts between output pins or between output pins and the power supply and GND pin caused by the presence of a foreign object may result in damage to the IC. (5) Operation in a strong electromagnetic field Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to malfunction. (6) Thermal shutdown circuit (TSD circuit) This IC incorporates a built-in thermal shutdown circuit (TSD circuit). The TSD circuit designed only to shut the IC off to prevent runaway thermal operation. do not continue to use the IC after operating this circuit or use the IC in an environment where the operation of the thermal shutdown circuit is assumed. (7) Testing on application boards When testing the IC on an application board, connecting a capacitor to pin with low impedance subjects the IC to stress. Always discharge capacitors after each process or step. Ground the IC during assembly steps as an antistatic measure, and use similar caution when transporting or storing the IC. Always turn the IC’s power supply off before connecting it to or removing it from a jig or fixture the inspection process. (8) Common impedance Power supply and ground wiring should reflect consideration of the need to lower common impedance and minimize ripple as much as possible (by making wiring as short and thick as possible or rejecting ripple by incorporating inductance and capacitance). (9) Applications with modes that reverse VCC and pin potentials may cause damage to internal IC circuits. For example, such damage might occur when VCC is shorted with the GND pin while an external capacitor is charged. It is recommended to insert a diode for preventing back current flow in series with VCC or bypass diodes between VCC and each pin. Bypass diode Back current prevention diode VCC Output pin Fig.13 (10) Timing resistor Timing resistor connected between RT and GND, has to be placed near RT terminal (8pin). And pattern has to be short Enough. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 9/11 2009.05 - Rev.A Technical Note BD9763FVM (11) IC pin input This monolithic IC contains P + isolation and PCB layers between adjacent elements in order to keep them isolated. P/N junctions are formed at the intersection of these P layers with the N layers of other elements to create a variety of parasitic elements. For example, when a resistor and transistor are connected to pins as shown in Fig.14, ○the P/N junction functions as a parasitic diode when GND > (Pin A) for the resistor or GND > (Pin B) for the transistor (NPN). ○Similarly, when GND > (Pin B) for the transistor (NPN), the parasitic diode described above combines With the N layer of other adjacent elements to operate as a parasitic NPN transistor. The formation of parasitic elements as a result of the relationships of the potentials of different pins is an inevitable result of the IC’s architecture. The operation of parasitic elements can cause interference with circuit operation as well as IC malfunction and damage. For these reasons, it is necessary to use caution so that the IC is not used in away that will trigger the operation of parasitic elements, such as by the application of voltage lower than the GND (PCB) voltage to input and output pins. (Pin A) (Pin A) Ｂ (Pin B) Ｅ Ｃ Ｎ Ｐ Ｐ ＋ Ｐ Ｐ ＋ Ｎ PCB Ｎ ＋ GND Ｐ Ｐ Ｎ PCB GND Ｎ Ｎ GND Parasitic diode (Pin B) Ｎ Ｂ Parasitic transistors Parasitic diode GND ＋ Other adjacent element Ｃ Ｅ GND Parasitic elements Fig.14 ●Power Dissipation Reduction pd(W) POWER DISSIPATION ： pd(W） 0.8 0.6 0.4 0.587W 0.2 0 0 25 50 75 100 125 150 175 AMBIENT TEMPERATURE ： Ta(℃） IC mounted on a ROHM standard board (70mm x 70mm x 1.6mm, glass epoxy) Fig.15 www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 10/11 2009.05 - Rev.A Technical Note BD9763FVM ●Ordering part number B D 9 Part No. 7 6 3 Part No. F V M - T R Packaging and forming specification TR: Embossed tape and reel (MSOP8) Package FVM: MSOP8 MSOP8 <Tape and Reel information> 2.8±0.1 4.0±0.2 8 7 6 5 0.6±0.2 +6° 4° −4° 0.29±0.15 2.9±0.1 (MAX 3.25 include BURR) Tape Embossed carrier tape Quantity 3000pcs Direction of feed TR The direction is the 1pin of product is at the upper right when you hold ( reel on the left hand and you pull out the tape on the right hand ) 1 2 3 4 1PIN MARK 1pin +0.05 0.145 –0.03 0.475 0.08±0.05 0.75±0.05 0.9MAX S +0.05 0.22 –0.04 0.08 S Direction of feed 0.65 (Unit : mm) www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. Reel 11/11 ∗ Order quantity needs to be multiple of the minimum quantity. 2009.05 - Rev.A Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. 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