TLCS-870/C1 Series Instruction Set

TLCS-870/C1 Series　Instruction Set
Semiconductor Company
TLCS-870/C1
1. Overview
The basic machine instructions available with the TLCS-870/C series of microcontrollers consist of 133 types,
providing a total of 732 instructions. The table below shows these instructions classifiled by type. The instructions
for the TLCS-870/C series vary in length from one byte to a maximum of five bytes. The frequently used instructions have their object code length reduced, making it possible to create memory-efficient programs.
The TLCS-870/C series offers a simple instruction architecture based on a memory-mapped I/O system. Although
only 42 kinds of mnemonics are available, it supports 8 addressing modes allowing for powerful memory manipulation.
In addition to the basic machine instruction, the TLCS-870/C series offers assembler-based extended machine
instructions in order to increase coding efficency.
Table 1-1 Intsruction Set
Load/Store,
Exchange
8-bit data Load/Store, Exchange
7 types
49
instructions
16-bit data Load/Store, Exchange
7
43
Flag Manipuration
5
5
SP Manipuration
1
2
Push, Pop
4
6
Compare
4
29
Increment, Decrement
4
28
Arithmetic
16
116
Logical
12
87
Decimal Adjust
2
2
Compare
3
15
Increment, Decrement
2
2
Arithmetic
12
60
Logical
9
45
2’s Complement
1
1
2
2
8-bit (Logical)
2
2
16-bit (Arithmetic)
2
2
8-bit
2
2
8-bit ALU
ALU
16-bit ALU
Multiply, Divide
Shift
Shift/Rotate
Rotate
Nibble
Manipulation
Swap, Nibble Rotate
3
27
Bit
Manipulation
Set, Clear, Complement, Load/Store, Exchange,
EXOR
18
162
Jump
6
24
Call
4
16
Return
3
3
Software Interrupt, Other
2
2
133 types
732
instructions
Branch
Others
Total
RA000
Page 1
1.1 Symbols Used in this Document
1.1 Symbols Used in this Document
TLCS-870/C1
Table 1-2 Addressing Modes
Register Indirect
7 types
Direct
2
Register
1
Immediate
1
Relative
2
Absolute
1
Vector
1
Direct Bit
2
Register Indirect Bit
1
Total
18
1.1 Symbols Used in this Document
The symbols shown below are used in the descriptions of instructions and addressing modes in the following
pages.
Symbol
RA000
Description
Symbol
Description
A
A register
r, g
8-bit register (SeeTable 1-3)
W
W register
rr, gg
16-bit register (SeeTable 1-4)
B
B register
n
4-bit or 8-bit immediate data
C
C register
mn
16-bit immediate data
D
D register
d
Signed 5-bit or 8-bit displacement
(−16 to +15/−128 to +127)
E
E register
x, y
8-bit direct address (0x0000 to 0x00FF)
H
H register
vw, uz
16-bit direct address (0x0000 to 0xFFFF)
L
L register
(XX)
Memory contents at the address specified by XX
WA
WA register
(XX + 1, XX)
Two consective bytes from the memory location
specified by XX
BC
BC register
b
Bit number (0 to 7)
DE
DE register
.b
Content of bit specified by b
HL
HL register
←
Load/store
IX
IX register
↔
Exchange
IY
IY register
+
Add
PC
Program Counter
−
Substract
SP
Stack Pointer
×
Multiply
PSW
Program Status Word
÷
Divide
JF
Jump Status flag
&
Bitwise AND
ZF
Zero flag
⏐
Bitwise OR
CF
Carry flag (1-bit accumulator)
^
Bitwise exclusive OR
HF
Halfcarry flag
null
No operation (Goes to instruction at the next
address without performing anything.)
SF
Sign flag
$
VF
Overflow flag
(src)
Start address of instruction bein executed (The program Counter points to the address two or three
bytes after $.)
Source memory
CF
Inverse of carry flag
(dst)
Destination memory
IMF
Interrupt Master Enable flag
RBS
Register Bank Selector
NxtOp
Next operation addresses (Start address of the next
instruction)
Page 2
TLCS-870/C1
Table 1-3
r, g
8-Bit Register
0
1
2
3
4
5
6
7
A
W
C
B
E
D
L
H
Table 1-4
rr, gg
16-Bit Register
0
1
2
3
4
5
6
7
WA
BC
DE
HL
IX
IY
SP
HL
Flag setting conditions
*
The value specified by the operation is set.
Z
Zero detection
C
RA000
•
Load/Store
When the 8-bit source data is 0x00, the Z flag is set to 1. Otherwise, the Z flag is cleared to 0.
•
Exchange
When the contents of g register or (src) before the exchange is 0x00, the Z flag is set to 1. Otherwise, the Z flag is cleared to 0.
•
ALU
When the operation result is 0x00 (8-bit operation) or 0x0000 (16-bit operation), the Z flag is set to
1. Otherwise, the Z flag is cleared to 0.
However, for multiply operation, this Z flag is set when the high-order 8 bits of the product are 0x00,
for divide operation, this Z flag is set when the remainder is 0x00. Otherwise, the Z flag is cleared
to 0.
•
Shift/Rotate
When the register contents is 0x00 after being shifted or rotated, the Z flag is set to 1. Otherwise,
the Z flag is cleared to 0.
•
Other
When Z appears in the JF column, it means that the value set in ZF is also set in JF.
Carry
•
Addition
When a carry occurs from the most significant bit, the C flag is set.
•
Subtraction
When a borrow occurs from the most significant bit, the C flag is set.
•
Division
When the divisor is 0x00 or the quotient is equal to or greater than 0x100, the C flag is set to 1.
Otherwise, the flag is cleared to 0.
•
Other
When C appears in the JF column, it means that the value set in CF is also set in JF.
C
An inverse of CF
H
Half carry
•
Half carry
Addition
When a carry occurs from bit 3, the H flag is set.
•
Subtraction
When a borrow occurs from bit 3, the H flag is set.
S
Sign (most significant bit of data)
V
Overflow
J
An inverse of JF
1
A logic 1 is set.
0
A logic 0 is set.
U
An indeterminate value is set.
−
The value before instruction execution is retained leaving the flag unchanged.
Page 3
1.1 Symbols Used in this Document
1.1 Symbols Used in this Document
TLCS-870/C1
1.2 Mnemonics
The following describes the rules on mnemonics of the TLCS-870/C1 series instructions.
Each mnemonics consists of an opcode and an operand (s). (Some instructions do not have any operand.) The
opcode and the operands are separated with one or more spaces. If an instruction has two or more operands, each
operand is separated with a comma.
If the instruction has two operands, source and destination, the destination operand is always placed before the
source operand. If there are multiple source operands, the first operand is placed first followed by the other operand.
If the operand includes a bit specifier, the address and the bit specifier are separated with a period.
Example:
RA000
mnemonic
opcode
RET
ROLC
A
opcode
operand
ADD
A, B
opcode
destination
operand
,
source
operand
CMP
A, B
opcode
1st source
operand
,
2nd source
operand
AND
(HL), n
opcode
1st source
operand
SET
(HL). b
opcode
LD
CF, (HL). b
opcode
2nd source
, operand
operand
bit
address
.
1st operand
Page 4
,
2nd operand
bit
address
.
TLCS-870/C1
Table 1-5 Mnemonics
Mnemonics
Description
ADD
ADDC
AND
Add
Add with carry
Logical AND
CALL
CALLV
CLR
CMP
CPL
Call
Vector call
Clear bit/byte
Compare
1’s complement bit
DAA
DAS
DEC
DI*
DIV
Decimal adjust for 8-bit addition
Decimal adjust for 8-bit subtraction
Decrement byte/word (Register)
Disable maskable interrupt
Divide byte quotient
EI*
Enable interrupt
INC
Increment byte/word (Register)
J*
JP
JR
JRS
Optimized jump
Absolute jump
Relative jump
Short relative jump
LD
LDW
Load bit/byte/word (Register)/effective address
Load word (Memory)
MUL
Multiply
NEG
Negate
NOP
No operation
OR
Logical OR
POP
PUSH
Pop up
Push down
RET
RETI
RETN
ROLC
ROLD
RORC
RORD
Return from subroutine
Return from maskable interrupt service routine
Return from non-maskable interrupt service routine
Rotate left through carry
Rotate left digit
Rotate right through carry
Rotate right digit
SET
SHLC
SHLCA
SHRC
SHRCA
SUB
SUBB
SWAP
SWI
Bit test and set
Logical shift left
Arithmetic shift left
Logical shift right
Arithmetic shift right
Subtract
Subtract with borrow
Swap nibble
Software interrupt
TEST*
Bit test
XCH
XOR
Exchange
Logical exclusive OR
Note: *: Instructions marked with an asterisk (*) are extended assembler machine instructions.
RA000
Page 5
1.1 Symbols Used in this Document
1.1 Symbols Used in this Document
TLCS-870/C1
1.3 Object Code Format
The TLCS-870/C1 series has instructions with 1-byte and 2-byte opcodes.
1.3.1
Format of Instructions with a 1-byte Opcode.
The opcode is placed in the first byte and the operand is placed in the second and subsequent bytes. If the
operand is 2 bytes long, the lower byte is placed first followed by the upper byte. When the operand consists of
source and destination, the source is placed after the destination if the source is an immediate (e.g., LD(x), n).
Examples:
Second byte
Third byte
LD
A, B
opcode
LD
A, n
opcode
n
LD
WA, mn
opcode
n
m
LD
(x), n
opcode
x
n
opcode
x
n
LDW (x), mn
1.3.2
First byte
Fourth byte
m
Format of Instructions with 2-byte Opcodes
The first opcode is placed in the first byte and then the operand specified by the first opcode is placed in the
next byte. Then, the second opcode and the operand specified by the second opcode are placed in the following
bytes.
The first opcode, which is used to specify an addressing mode, is called the "prefix code." There are two
types of prefix: the register prefix to specify a register and the source/destination memory prefix to specify the
source or destination memory address. Note that the first opcode in the five instructions shown below ignores
the contents of a specified register:
(1) RETN
(2) LD PSW, n
(3) PUSH PSW
(4) POP PSW
(5) JR M/P/SLT/SGE/SLE/SGT/VS/VC, a
Examples:
First byte
Second byte
Third byte
LD
B, C
1st opcode 2nd opcode
ADD B, n
1st opcode 2nd opcode
LD
B, (HL)
1st opcode 2nd opcode
LD
B, (x)
1st opcode
x
2nd opcode
LD
B, (HL + d) 1st opcode
d
2nd opcode
LD
(HL + d), n
1st opcode
d
2nd opcode
Fourth byte
Register prefix
Source memory prefix
Destination memory prefix
RA000
Page 6
n
n
TLCS-870/C1
1.4 Addressing Mode
The TLCS-870/C series supports 17 addressing modes (or the methods for specifying addresses). Some instructions use a combination of multiple addressing modes.
1.4.1
Register Indirect Addressing
1.4.1.1
Register Indirect Addressing (HL), (DE), (IX), (IY)
The effective address is specified by the contents of a 16-bit register pair HL, DE, IX or IY.
Data Area
Example 1:
HL
LD
01
A, (HL)
23
0x00123
5F
5F
A
The contents of the memory location pointed to by HL, i.e., 0x5F, at address 0x00123, is loaded into the
A register.
Data Area
Example 2:
IX
LD
A, (IX)
01
23
0x00123
75
75
A
The contents of the memory location pointed to by IX, i.e., 0x75, at address 0x00123, is loaded into the
A register.
Data Area
Example 3:
IY
LD
01
A, (IY)
23
0x00123
9B
9B
A
The contents of the memory location pointed to by IX, i.e., 0x9B, at address 0x00123, is loaded into the
A register.
RA000
Page 7
1.1 Symbols Used in this Document
1.1 Symbols Used in this Document
1.4.1.2
TLCS-870/C1
Register Indirect with 8-Bit Displacement Addressing (HL + d), (IX + d), (IY + d)
The effective address is formed by sign-extending the 8-bit displacement d in the instruction code (see
the table below) and adding it to the contents of the 16-bit register HL, IX or IY. Note that the contents of
the 16-bit register HL, IX or IY does not change.
Displacement d
Sign-extended Value
0x00 to 0x7F
0x0000 to 0x007F (0 to +127)
0x80 to 0xFF
0xFF80 to 0xFFFF (−128 to −1)
Instruction Code
d
First Opcode
Example 1:
LD
Operand
A, (HL + 0x12)
Second Opcode
Code Area
D7
12
HL
01
23
+
00
01
12
35
Signextended
Data Area
0x00135
C4
C4
A
The displacement (0x12) is sign-extended (0x0012) and added to the contents of the HL register
(0x0123) to form an effective address. The contents of the memory location specified by the effective
address, i.e., 0xC4, at address 0x00135, is loaded into the A register.
Example 2:
LD
A, (IX + 0xD6)
Code Area
D4
D6
IX
+
1
01
23
FF
D6
00
F9
Signextended
Data Area
0x000F9
27
27
A
The displacement (0xD6) is sign-extended (0xFFD6) and added to the contents of the IX register
(0x0123) to form an effective address. The contents of the memory location specified by the effective
address, i.e., 0x27, at address 0x000F9, is loaded into the A register.
RA000
Page 8
TLCS-870/C1
1.4.1.3
Register Indexed Addressing (HL + C)
The effective address is formed by sign-extending the contents of the C register (see the table below)
and adding it to the contents of the HL register. Note that the contents of the HL and C registers do not
change.
C Register
Example:
C
F5
Sign-extended Value
0x00 to 0x7F
0x0000 to 0x007F (0 to +127)
0x80 to 0xFF
0xFF80 to 0xFFFF (−128 to −1)
LD
A, (HL + C)
HL
Signextended
01
23
FF
F5
01
18
Data Area
+
1
36
0x00118
36
A
The contents of the C register (0xF5) is sign-extended (0xFFF5) and added to the contents of the HL
register (0x0123) to from an effective address. The contents of the memory location specified by the
effective address, i.e., 0x36, at address 0x00118, is loaded into the A register.
1.4.1.4
Stack Pointer Indirect with Auto-Pre-Increment Addressing (+SP)
The contents of the SP is incremented to form an effective address. Incrementing the SP does not affect
the flag bits.
This addressing mode can only be used to specify the source memory address.
Example:
LD
A, (+SP)
Data Area
SP (Before Execution)
4
3
1
F
SP (After Execution)
4
3
2
0
0x04320
B7
B7
A
The contents of the SP is incremented first to form an effective address. The memory contents at the
effective address, i.e., 0xB7, at address 0x04320, is then loaded into the A register.
RA000
Page 9
1.1 Symbols Used in this Document
1.1 Symbols Used in this Document
1.4.1.5
TLCS-870/C1
Stack Pointer Indirect with Auto-Decrement Addressing (SP-)
The SP holds the effective address. After the data manipulation, the contents of the SP is automatically
decremented. Decrementing the SP does not affect the flag bits. This addressing mode can only be used to
specify the destination memory address.
The contents of the A register (0x1C) is stored into the memory location specified by the contents of the
SP, i.e., address 0x03000. The SP is then decremented to 0x2FFF.
Example:
LD
(SP-), A
Data Area
SP (Before Execution)
3
0
0
0
SP (After Execution)
2
F
F
F
1.4.1.6
0x03000
1C
1C
A
Stack Pointer Indirect with 8-Bit Displacement Offset Addressing (SP + d)
The effective address is formed by sign-extending the 8-bit displacement d in the instruction code (see
the table below) and adding it to the contents of the Stack Pointer SP.
Displacement d
Sign-extended Value
0x00 to 0x7F
0x0000 to 0x007F (0 to +127)
0x80 to 0xFF
0xFF80 to 0xFFFF (−128 to −1)
Instruction Code
d
First Opcode
Example:
LD
WA, (SP + 0xD6)
Operand
Second Opcode
Code Area
D6
D6
48
Data Area
SP
12
34
+
FF
D6
12
0A
1
Signextended
0x0120A
0x0120B
27
4E
4E
27
WA
The displacement (0xD6) is sign-extended (0xFFD6) and added to the contents of SP (0x1234) to form
an effective address (0x0120A). Two consecutive bytes from the memory location specified by the effective address, i.e., 0x4E27, are loaded into the WA register.
RA000
Page 10
TLCS-870/C1
1.4.1.7
PC-Relative Register Indirect Addressing (PC + A)
The effective address is formed by sign-extending the contents of the A register (see the table below)
and adding it to the contents of the Program Counter (start address of the current instruction + 2). This
addressing mode can only be used to specify the source address. This addressing mode simplifies the coding of BCD to 7-segment conversions, table lookups, table searches and multi-way (n-way) branches.
Accumulator
Example 1:
LD
Sign-extended Value
0x00 to 0x7F
0x0000 to 0x007F (0 to +127)
0x80 to 0xFF
0xFF80 to 0xFFFF (−128 to −1)
A, (PC + A)
Code Area
+2
0x1C536
0x1C537
A (Before Execution)
07
PC
Signextended
C5
38
00
07
C5
3F
3F
40
Instruction:
LD A, (PC + A)
Data Area
+
0x0C53F
D8
D8
A (After Execution)
The contents of the A register (0x07) is sign-extended (0x0007) and added to the contents of the Program Counter (0xC538) to form an effective address (0x0C53F). The contents of the memory location
specified by the effective address, i.e., 0xD8 is loaded into the A register.
Example 2:
JP
(PC + A)
Code Area
+2
A
16
PC
Signextended
C1
74
00
16
C1
8A
0x1C172
3F
FE
Instruction:
JP (PC + A)
Data Area
+
0x0C18A
0x0C18B
4B
D0
Lower
Upper
D0
4B
PC
The contents of the A register (0x16) is sign-extended (0x0016) and added to the contents of the Program Counter (0xC174) to form an effective address (0x0C18A). Two consecutive bytes from the memory location specified by the effective address, 0xD04B, are loaded into the Program Counter. That is, a
jump is taken to the destination address, 0xD04B.
Note: The meaning of the operand (PC + A) differs between the 870/C and 870/C1.
In the 870/C1, the area that is accessed using the addressing mode using the operand (PC + A) is not a
code area but a data area. Therefore, the addressing mode using the operand (PC + A) in the 870/C1 is not
compatible with that in the 870/C.
Care should be taken when porting programs from the 870/C to the 870/C1.
RA000
Page 11
1.1 Symbols Used in this Document
1.1 Symbols Used in this Document
1.4.2
TLCS-870/C1
Direct Addressing
1.4.2.1
8-Bit Direct Addressing (x)
The address is specified directly by the 8-bit value x in the instruction code. The address is in the range
of 0x00000 to 0x000FF.
Example:
LD
A, (0x87)
Instruction Code
Data Area
x
0x00087
19
19
A
Opcode
Operand
Code Area
0C
87
Instruction: LD A, (0x87)
The contents of the memory location specified directly by the value x in the instruction code (0x87), i.e,
0x19, at address 0x00087, is loaded into the A register.
1.4.2.2
16-Bit Direct Addressing (vw)
The effective address is specified directly by the 16-bit value vw in the instruction code. The address is
in the range of 0x00000 to 0x0FFFF.
Example:
LD
A, (0x5678)
Instruction Code
Data Area
E1/F1
0x05678
24
24
w
v
A
First Opcode
Operand
First Opcode
Code Area
Lower
Upper
56
E1
78
56
40
LD Instruction
78
The contents of the memory location specified directly by the value vw in the instruction code
(0x5678), i.e., 0x24, at address 0x05678, is loaded into the A register.
RA000
Page 12
TLCS-870/C1
1.4.3
Register Addressing (r or rr)
The register specifier in the instruction code (opcode) specifies which register is to be accessed.
Example 1:
LD
A, B
Example 2:
Opcode
0001
0011
Opcode
0011
1010
Register Specifier
011 → B Register
1.4.4
INC DE
Register Specifier
010 → DE Register
Immediate Addressing (n or mn)
A specified operation is performed directly on the immediate operand in the instruction code. Note that when
the operand is a 16-bit immediate, it is stored with the low-order byte first, followed by the high-order byte.
Example 1:
LD
A, 0x53
Instruction Code
Code Area
n
0x1C000
0x1C001
Example 2:
LD
18
53
53
Opcode
A
Operand
WA, 0x1234
Instruction Code
Code Area
n
0x1C000
0x1C001
0x1C002
48
34
12
Lower
Upper
12
W
Opcode
m
Operand
34
A
Note:In the assembler source program, do not enclose the immediate with parentheses. Otherwise, it is interpreted
as the direct addressing mode.
RA000
Page 13
1.1 Symbols Used in this Document
1.1 Symbols Used in this Document
1.4.5
TLCS-870/C1
Relative Addressing
1.4.5.1
PC-Relative with 8-Bit Displacement Addressing
The effective address is formed by sign-extending the 8-bit displacement d in the instruction code (see
the table below) and adding it to the contents of the Program Counter (start address of the current instruction + 2 or 3).
Displacement d
Sign-extended Value
0x00 to 0x7F
0x0000 to 0x007F (0 to +127)
0x80 to 0xFF
0xFF80 to 0xFFFF (−128 to −1)
Instruction Code
d
Opcode
Example 1:
JR
Operand
$ + 2 + 35H or JR
0x0D578
Code Area
+2
PC
D5
43
+
00
35
D5
78
FC
35
0x1D541
JR Instruction
Signextended
0x1D578
The displacement (0x35) is sign-extended and added to the contents of the Program Counter (0xD543)
to form an effective address. Program control is then transferred to the effective address, 0x1D578.
Note: $ denotes the start address of the current instruction.
Example 2:
JR
M, $ + 3 + 35H or JR
M, 0x0D579
Code Area
+3
PC
D5
44
+
00
35
D5
79
0x1D541
E8
D0
35
Instruction: JR M, a
Signextended
0x1D579
The displacement (0x35) is sign-extended and added to the contents of the Program Counter (0xD544)
to form an effective address. Program control is then transferred to the effective address, 0x1D579, if the
sign flag is 1.
Note: $ denotes the start address of the current instruction.
RA000
Page 14
TLCS-870/C1
1.4.5.2
PC-Relative with 5-Bit Displacement Addressing
The effective address is formed be sign-extending the 5-bit displacement d in the opcode (see the table
below) and adding it to the contents of the Program Counter (start address of the current instruction + 2).
Displacement d
Sign-extended Value
0x00 to 0x0F
0x0000 to 0x000F (0 to +15)
0x10 to 0x1F
0xFFF0 to 0xFFFF (−16 to −1)
Instruction Code
7
6
5
4
3
2 1
0
d
Opcode
Example:
JRS
T, $ + 2 + 14H or JRS
T, 0x0E859
Code Area
0x1E859
+2
PC
E8
65
+
FF
F4
E8
59
1
0x1E863
94
JRS Instruction
Signextended
The displacement (0x14) is sign-extended (0xFFF4) and added to the contents of the Program Counter
(0xE865) to form an effective address. Program control is then transferred to the effective address,
0x1E859, if the Jump Status flag is 1.
Note: $ denotes the start address of the current instruction.
1.4.6
Absolute Addressing
The effective address is specified by a 16-bit value in the instruction code (stored with the low-order byte
first, followed by the high-order byte).
Example:
JP
0x0F1A3
Code Area
Instruction Code
n
Lower
0x1C075
Upper
PC
F1
A3
FE
A3
F1
JP
Instruction
Opcode
m
Operand
0x1F1A3
Program control is transferred to the address specified by the operand, 0x1F1A3.
RA000
Page 15
1.1 Symbols Used in this Document
1.1 Symbols Used in this Document
1.4.7
TLCS-870/C1
Vector Addressing
The 4-bit operand is multiplied by 2 and added to the top address of the vector call table to form a pointer to
a location where a 16-bit jump destination address (vector address) is located.
Example:
CALLV
0x9
Instruction Code
Code Area
7
0x1D201
n=
9
2
12
×
+
FF
A0
FF
B2
79
6
5
4
3
CALLV Instruction
2 1
0
n
Opcode
0x1E073
0x1FFB2
0x1FFB3
Lower
Upper
73
E0
E0
73
PC
The operand n (0x9) is multiplied by 2 and added to the top address of the vector call table (0xFFA0) to form
a pointer to a location (0x1FFB2) where a jump destination address, which is formed from the contents of two
consecutive bytes (0x1E073), is located.
1.4.8
Direct Bit Addressing
1.4.8.1
Register Bit Addressing
The register and bit specifiers in the instruction code specify a bit position in a register whose value
should be tested or changed.
Example:
SET
A.3
Instruction Code
1110
Bit 3 of the A register
contents is set to 1.
1000
A register = 000
Register
Specifier
First Opcode
1.4.8.2
1100
0011
Bit
Specifier
011 = Bit 3
Second Opcode
Memory Bit Addressing
In Memory Bit addressing mode, the bit specifier in the instruction code specifies the bit in the memory
location pointed to by (HL), (DE), (IX), (IY), (HL + d), (IX + d), (IY + d), (HL + C), (+SP), (SP + d), (PC
+ A), (x) or (vw). A bit manipulation is performed on the specified bit.
RA000
Example 1: SET
(HL). 1
Example 2: SET
(HL + 0x57). 6
Example 3: SET
(0x00058). 3
Page 16
TLCS-870/C1
1.4.9
Register Indirect Bit Addressing
In Memory Bit addressing mode, low-order 3 bits of the A register specify the bit in the memory location
pointed to by (HL), (DE), (IX), (IY), (HL + d), (IX + d), (IY + d), (HL + C), (+SP), (SP + d), (PC + A), (x) or
(vw). A bit manipulation is performed on the specified bit.
Example:
SET
(HL). A
Code Area
7 6 5 4 3 21 0
9C
A
Bit 4
HL
01
23
0x00123
1 1 0 0 0 11 0
1
The data in the memory location pointed to by the contents of the HL register (0x0123) is 0y11000110. Since
the low-order 3 bits of the A register (0y100) indicates bit 4, bit 4 of the data is set and the value is changed to
0y11010110.
Instruction Code
1110
0011
First Opcode
(HL)
Address Specification
1111
0010
Second Opcode
Operation Specification
SET (mem). A
1001
1100
Bit Specifier
100 = Bit 4
RA000
Page 17
1.1 Symbols Used in this Document
1.1 Symbols Used in this Document
RA000
TLCS-870/C1
Page 18
TLCS-870/C1
2. Instruction Set Details
2.1 Load/Store and Exchange Instructions
Flag
Mnemonic
Instruction Code (Binary)
Cycle
Operation
J Z C H S V
0 0 0 1
0 r r r
1 Z – – – – 1
LD A,r
A←r
Load the contents of 8-bit register r into A. The Zero flag is set to 1 when r = 0x00; otherwise, it is cleared to 0.
0 1 0 0
0 r r r
1 Z – – – – 1
LD r,A
r←A
Load the contents of A into 8-bit register r. The Zero flag is set to 1 when A = 0x00; otherwise, it is cleared to 0.
1 1 1 0
1 g g g 0 1 0 0
0 r r r
1 Z – – – – 2
LD r,g
r←g
Load the contents of an 8-bit register g into 8-bit register r. The Zero flag is set to 1 when g = 0x00; otherwise, it is cleared to 0.
1 1 1 0
LD rr,gg
1 r r r
1 – – – – – 2
rr ← gg
Load the contents of a 16-bit register pair gg (WA, BC, DE or HL) into 16-bit register pair rr.
Example: Assume DE contains 0x1234. Then, the instruction “LD HL, DE” loads 0x1234 into HL.
0 0 0 0
LD A,(x)
1 g g g 0 1 0 0
1 1 0 0 x x x x
x x x x
1 Z – – – – 3
A ← (x)
Load the contents of the memory location directly addressed by x into A. The Zero flag is set to 1 when the loaded value is 0x00.
(0x0000 ≤ x ≤ 0x00FF)
0 0 0 0
LD A,(HL)
1 1 0 1
1 Z – – – – 2
A ← (HL)
Load the contents of the memory location addressed by HL into A. The Zero flag is set to 1 when the loaded value is 0x00.
(0x0000 ≤ (HL) ≤ 0xFFFF)
1 1 1 0
LD r,(x)
0 0 0 0 x x x x
x x x x 0 1 0 0
0 r r r 1 Z – – – – 4
r ← (x)
Load the contents of the memory location directly addressed by x into 8-bit register r. The Zero flag is set to 1 when the loaded value is
0x00. (0x0000 ≤ x ≤ 0x00FF)
1 1 1 0
0 1 0 0
LD r,(vw)
0 0 0 1 w w w w
0 r r r
w w w w v v v v
v v v v 1 Z – – – – 5
r ← (vw)
Load the contents of the memory location directly addressed by vw into 8-bit register r. The Zero flag is set to 1 when the loaded value is
0x00. (0x0000 ≤ vw ≤ 0xFFFF)
1 1 1 0
LD r,(DE)
0 0 1 0 0 1 0 0
0 r r r
1 Z – – – – 3
r ← (DE)
Load the contents of the memory location addressed by DE into 8-bit register r. The Zero flag is set to 1 when the loaded value is 0x00.
(0x0000 ≤ (DE) ≤ 0xFFFF)
1 1 1 0
LD r,(HL)
0 0 1 1 0 1 0 0
0 r r r
1 Z – – – – 3
r ← (HL)
Load the contents of the memory location addressed by HL into 8-bit register r. The Zero flag is set to 1 when the loaded value is 0x00.
(0x0000 ≤ (HL) ≤ 0xFFFF)
1 1 1 0
LD r,(IX)
0 1 0 0 0 1 0 0
0 r r r
1 Z – – – – 3
r ← (IX)
Load the contents of the memory location addressed by the Index register IX into 8-bit register r. The Zero flag is set to 1 when the loaded
value is 0x00. (0x0000 ≤ (IX) ≤ 0xFFFF)
1 1 1 0
LD r,(IY)
0 1 0 1 0 1 0 0
0 r r r
1 Z – – – – 3
r ← (IY)
Load the contents of the memory location addressed by the Index register IY into 8-bit register r. The Zero flag is set to 1 when the loaded
value is 0x00. (0x0000 ≤ IY ≤ 0xFFFF)
1 1 0 1
0 1 0 0 d d d d
d d d d 0 1 0 0
0 r r r 1 Z – – – – 5
r ← (IX+d)
LD r,(IX+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to IX to form an effective address (EA). Load the contents
of the memory location at the EA into 8-bit register r. The Zero flag is set to 1 when the loaded value is 0x00.
LD r,(IY+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to IX to form an effective address (EA). Load the contents
of the memory location at the EA into 8-bit register r. The Zero flag is set to 1 when the loaded value is 0x00.
LD r,(SP+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to SP to form an effective address (EA). Load the contents
of the memory location at the EA into 8-bit register r. The Zero flag is set to 1 when the loaded value is 0x00.
LD r,(HL+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to HL to form an effective address (EA). Load the contents
of the memory location at the EA into 8-bit register r. The Zero flag is set to 1 when the loaded value is 0x00.
LD r,(HL+C)
Sign-extend the contents of C and add the result to HL to form an effective address (EA). Load the contents of the memory location at the
EA into 8-bit register r. The Zero flag is set to 1 when the loaded value is 0x00.
1 1 0 1
1 1 0 1
1 1 0 1
1 1 1 0
RA000
0 1 0 1 d d d d
0 1 1 0 d d d d
0 1 1 1 d d d d
0 1 1 1 0 1 0 0
d d d d 0 1 0 0
d d d d 0 1 0 0
d d d d 0 1 0 0
0 r r r
0 r r r 1 Z – – – – 5
0 r r r 1 Z – – – – 5
0 r r r 1 Z – – – – 5
1 Z – – – – 5
Page 19
r ← (IY+d)
r ← (SP+d)
r ← (HL + d)
r ← (HL+C)
2.1 Load/Store and Exchange Instructions
2.1 Load/Store and Exchange Instructions
TLCS-870/C1
Flag
Mnemonic
Instruction Code (Binary)
Cycle
Operation
J Z C H S V
1 1 1 0
0 1 1 0 0 1 0 0
0 r r r
1 Z – – – – 4
SP ← SP+1:r ← (SP)
LD r,(+SP)
Load the contents of the memory location at (SP+1) into 8-bit register r. The Zero flag is set to 1 when the loaded value is 0x00. This
instruction is used to pop 8-bit data off the stack.
LD r,(PC+A)Note
Sign-extend the contents of A and add the result to PC to form an effective address (EA). Load the contents of the memory location at the
EA into 8-bit register r. The Zero flag is set to 1 when the loaded value is 0x00. This instruction is useful for code conversions.
0 1 0 0
1 1 1 0
LD rr,(x)
0 0 0 0 x x x x
0 r r r
1 Z – – – – 5
x x x x 0 1 0 0
1 r r r 1 – – – – – 5
r ← (PC+A)
rr ← (x+1, x)
Load 2 consecutive bytes from the memory location directly addressed by x into 16-bit register pair rr. (0x0000 ≤ x ≤ 0x00FF)
Example: Assume the memory locations at addresses 0x0072 and 0x0073 contain 0x8E and 0x59 respectively. Then, the instruction “LD
WA, (0x72)” loads 0x59 and 0x8E into the registers W and A respectively.
1 1 1 0
0 1 0 0
LD rr,(vw)
1 1 1 1 0 1 0 0
0 0 0 1 w w w w
1 r r r
w w w w v v v v
v v v v 1 – – – – – 6
rr ← (vw+1, vw)
Load 2 consecutive bytes from the memory location directly addressed by vw into 16-bit register pair rr. This instruction loads the contents
of the memory location at address 0x1000 into the high-order byte of rr, when vw = 0x0FFF. (0x0000 ≤ vw ≤ 0xFFFF)
1 1 1 0
0 0 1 0 0 1 0 0
1 r r r
1 – – – – – 4
rr ← (DE+1, DE)
LD rr,(DE)
Load 2 consecutive bytes from the memory location addressed by DE into 16-bit register pair rr.
1 1 1 0
0 0 1 1 0 1 0 0
1 r r r
1 – – – – – 4
LD rr,(HL)
rr ← (HL+1, HL)
Load 2 consecutive bytes from the memory location addressed by HL into 16-bit register pair rr.
1 1 1 0
0 1 0 0 0 1 0 0
1 r r r
1 – – – – – 4
LD rr,(IX)
rr ← (IX+1, IX)
Load 2 consecutive bytes from the memory location addressed by IX into 16-bit register pair rr.
1 1 1 0
0 1 0 1 0 1 0 0
1 r r r
1 – – – – – 4
rr ← (IY+1, IY)
LD rr,(IY)
Load 2 consecutive bytes from the memory location addressed by IY into 16-bit register pair rr.
1 1 0 1
LD rr,(IX+d)
0 1 0 1 d d d d
d d d d 0 1 0 0
1 r r r 1 – – – – – 6
rr ← (IY+d+1, IY+d)
0 1 1 0 d d d d
d d d d 0 1 0 0
1 r r r 1 – – – – – 6
rr ← (SP+d+1, SP+d)
0 1 1 1 d d d d
d d d d 0 1 0 0
1 r r r 1 – – – – – 6
rr ← (HL+d+1, HL+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to HL to form an effective address (EA). Load 2 consecutive
bytes from the memory location addressed by the EA into 16-bit register pair rr.
1 1 1 0
LD rr,(HL+C)
rr ← (IX+d+1, IX+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to SP to form an effective address (EA). Load 2 consecutive
bytes from the memory location addressed by the EA into 16-bit register pair rr.
Example: Assume SP contains 0x51E4 and the memory locations at addresses 0x5216 and 0x5217 contain 0x9F and 0xC3 respectively.
Then, the instruction “LD WA, (SP + 0x32)” loads 0x9F and 0xC3 into A and W respectively.
1 1 0 1
LD rr,(HL+d)
1 r r r 1 – – – – – 6
Sign-extend the 8-bit displacement d in the instruction code and add the result to IY to form an effective address (EA). Load 2 consecutive
bytes from the memory location addressed by the EA into 16-bit register pair rr.
1 1 0 1
LD rr,(SP+d)
d d d d 0 1 0 0
Sign-extend the 8-bit displacement d in the instruction code and add the result to IX to form an effective address (EA). Load 2 consecutive
bytes from the memory location addressed by the EA into 16-bit register pair rr.
1 1 0 1
LD rr,(IY+d)
0 1 0 0 d d d d
0 1 1 1 0 1 0 0
1 r r r
1 – – – – – 6
rr ← (HL+C+1, HL+C)
Sign-extend the contents of C and add the result to HL to form an effective address (EA). Load 2 consecutive bytes from the memory location addressed by the EA into 16-bit register pair rr.
1 1 1 0
0 1 1 0 0 1 0 0
1 r r r
1 – – – – – 5
LD rr,(+SP)
SP ← SP+1:rr ← (SP+1, SP)
Load 2 consecutive bytes from the memory location addressed by (SP+1) into 16-bit register pair rr.
0 1 0 0
LD rr,(PC+A)Note
0 0 0 0
LD (x),A
LD (vw),r
1 – – – – – 6
rr ← (PC+A+1, PC+A)
1 1 1 0 x x x x
x x x x
1 – – – – – 3
(x) ← A
1 1 1 1
1 – – – – – 2
(HL) ← A
Store the contents of A into the memory location addressed by HL. (0x0000 ≤ (HL) ≤ 0xFFFF)
1 1 1 1
LD (x),r
1 r r r
Store the contents of A into the memory location directly addressed by x. (0x0000 ≤ x ≤ 0x00FF)
0 0 0 0
LD (HL),A
1 1 1 1 0 1 0 0
Sign-extend the contents of A and add the result to PC to form an effective address (EA). Load 2 consecutive bytes from the memory location addressed by the EA into 16-bit register pair rr.
0 0 0 0 x x x x
x x x x 0 1 1 1
1 r r r 1 – – – – – 4
(x) ← r
Store the contents of 8-bit register r into the memory location directly addressed by x. (0x0000 ≤ x ≤ 0x00FF)
1 1 1 1
0 1 1 1
0 0 0 1 w w w w
1 r r r
w w w w v v v v
v v v v 1 – – – – – 5
(vw) ← r
Store the contents of 8-bit register r into the memory location directly addressed by vw. (0x0000 ≤ vw ≤ 0xFFFF)
1 1 1 1
LD (DE),r
RA000
1 r r r
1 – – – – – 3
(DE) ← r
Store the contents of 8-bit register r into the memory location addressed by DE. (0x0000 ≤ (DE) ≤ 0xFFFF)
1 1 1 1
LD (HL),r
0 0 1 0 0 1 1 1
0 0 1 1 0 1 1 1
1 r r r
1 – – – – – 3
(HL) ← r
Store the contents of 8-bit register r into the memory location addressed by HL. (0x0000 ≤ (HL) ≤ 0xFFFF)
Page 20
TLCS-870/C1
Flag
Mnemonic
Instruction Code (Binary)
Cycle
Operation
J Z C H S V
1 1 1 1
LD (IX),r
1 1 1 1
LD (IY),r
(IY) ← r
0 1 0 0 d d d d
d d d d 0 1 1 1
1 r r r 1 – – – – – 4
(IX+d) ← r
0 1 0 1 d d d d
d d d d 0 1 1 1
1 r r r 1 – – – – – 4
(IY+d) ← r
0 1 1 0 d d d d
d d d d 0 1 1 1
1 r r r 1 – – – – – 4
(SP+d) ← r
0 1 1 1 d d d d
d d d d 0 1 1 1
1 r r r 1 – – – – – 4
(HL+d) ← r
0 1 1 1 0 1 1 1
1 r r r
1 – – – – – 5
(HL+C) ← r
0 1 1 0 0 1 1 1
1 r r r
1 – – – – – 4
(SP) ← r:SP ← SP−1
Store the contents of 8-bit register r into the memory location addressed by SP. Then, decrement the contents of SP. This instruction is
used to push 8-bit data onto the stack.
1 1 1 1
LD (x),rr
1 – – – – – 3
Sign-extend the contents of C and add the result to HL to form an effective address (EA). Store the contents of the memory location at the
EA into the 8-bit register r.
1 1 1 1
LD (SP−),r
1 r r r
Sign-extend the 8-bit displacement d in the instruction code and add the result to HL to form an effective address (EA). Store the contents
of the memory location at the EA into the 8-bit register r.
1 1 1 1
LD (HL+C),r
0 1 0 1 0 1 1 1
Sign-extend the 8-bit data d in the instruction code and add the result to SP to form an effective address (EA). Store the contents of the
memory location at the EA into the 8-bit register r.
0 1 0 1
LD (HL+d),r
(IX) ← r
Sign-extend the 8-bit displacement d in the instruction code and add the result to IY to form an effective address (EA). Store the contents
of the memory location at the EA into the 8-bit register r.
0 1 0 1
LD (SP+d),r
1 – – – – – 3
Sign-extend the 8-bit displacement d in the instruction code and add the result to IX to form an effective address (EA). Store the contents
of the memory location at the EA into the 8-bit register r.
0 1 0 1
LD (IY+d),r
1 r r r
Store the contents of 8-bit register r into the memory location addressed by IY. (0x0000 ≤ (IY) ≤ 0xFFFF)
0 1 0 1
LD (IX+d),r
0 1 0 0 0 1 1 1
Store the contents of 8-bit register r into the memory location addressed by IX. (0x0000 ≤ (IX) ≤ 0xFFFF)
0 0 0 0 x x x x
x x x x 0 1 1 0
1 r r r 1 – – – – – 5
(x+1, x) ← rr
Store the contents of 16-bit register pair rr into 2 consecutive memory locations directly addressed by x with the low-order byte first, followed by the high-order byte. (0x0000 ≤ x ≤ 0x00FF)
1 1 1 1
0 1 1 0
LD (vw),rr
0 0 0 1 w w w w
1 r r r
w w w w v v v v
v v v v 1 – – – – – 6
(vw+1, vw) ← rr
Store the contents of 16-bit register pair rr into 2 consecutive memory locations directly addressed by vw with the low-order byte first, followed by the high-order byte. (0x0000 ≤ vw ≤ 0xFFFF)
1 1 1 1
LD (DE),rr
RA000
0 1 0 0 0 1 1 0
1 r r r
1 – – – – – 4
(IX+1, IX) ← rr
0 1 0 1 0 1 1 0
1 r r r
1 – – – – – 4
(IY+1, IY) ← rr
0 1 0 0 d d d d
d d d d 0 1 1 0
1 r r r 1 – – – – – 5
(IX+d+1, IX+d) ← rr
0 1 0 1 d d d d
d d d d 0 1 1 0
1 r r r 1 – – – – – 5
(IY+d+1, IY+d) ← rr
0 1 1 0 d d d d
d d d d 0 1 1 0
1 r r r 1 – – – – – 5
(SP+d+1, SP+d) ← rr
0 1 1 1 d d d d
d d d d 0 1 1 0
1 r r r 1 – – – – – 5
(HL+d+1, HL+d) ← rr
Sign-extend the 8-bit displacement d in the instruction code and add the result to HL to form an effective address (EA). Store the contents
of 16-bit register pair rr into 2 consecutive memory locations addressed by the EA with the low-order byte first, followed by the high-order
byte.
1 1 1 1
LD (HL+C),rr
(HL+1, HL) ← rr
Sign-extend the 8-bit displacement d in the instruction code and add the result to SP to form an effective address (EA). Store the contents
of 16-bit register pair rr into 2 consecutive memory locations at the EA with the low-order byte first, followed by the high-order byte.
0 1 0 1
LD (HL+d),rr
1 – – – – – 4
Sign-extend the 8-bit displacement d in the instruction code and add the result to IY to form an effective address (EA). Store the contents
of 16-bit register pair rr into 2 consecutive memory locations at the EA with the low-order byte first, followed by the high-order byte.
0 1 0 1
LD (SP+d),rr
1 r r r
Sign-extend the 8-bit displacement d in the instruction code and add the result to IX to form an effective address (EA). Store the contents
of 16-bit register pair rr into 2 consecutive memory locations at the EA with the low-order byte first, followed by the high-order byte.
0 1 0 1
LD (IY+d),rr
0 0 1 1 0 1 1 0
Store the contents of 16-bit register pair rr into 2 consecutive memory locations addressed by IY with the low-order byte first, followed by
the high-order byte.
0 1 0 1
LD (IX+d),rr
(DE+1, DE) ← rr
Store the contents of 16-bit register pair rr into 2 consecutive memory locations addressed by IX with the low-order byte first, followed by
the high-order byte.
1 1 1 1
LD (IY),rr
1 – – – – – 4
Store the contents of 16-bit register pair rr into 2 consecutive memory locations addressed by HL with the low-order byte first, followed by
the high-order byte.
1 1 1 1
LD (IX),rr
1 r r r
Store the contents of 16-bit register pair rr into 2 consecutive memory locations addressed by DE with the low-order byte first, followed by
the high-order byte.
1 1 1 1
LD (HL),rr
0 0 1 0 0 1 1 0
0 1 1 1 0 1 1 0
1 r r r
1 – – – – – 6
(HL+C+1, HL+C) ← rr
Sign-extend the contents of C and add the result to HL to form an effective address (EA). Store the contents of 16-bit register pair rr into 2
consecutive memory locations addressed by the EA with the low-order byte first, followed by the high-order byte.
Page 21
2.1 Load/Store and Exchange Instructions
2.1 Load/Store and Exchange Instructions
TLCS-870/C1
Flag
Mnemonic
Instruction Code (Binary)
Cycle
Operation
J Z C H S V
1 1 1 1
0 1 1 0 0 1 1 0
1 r r r
1 – – – – – 5
(SP+1, SP) ← rr:SP ← SP−1
LD (SP−),rr
Store the contents of 16-bit register pair rr into 2 consecutive memory locations addressed by SP. Then, decrement the contents of SP.
0 0 0 1
LD r,n
LD (vw),n
1 – – – – – 2
r←n
1 r r r n n n n
n n n n mmmm
mmmm 1 – – – – – 3
rr ← mn
Load the immediate mn in the instruction code into 16-bit register pair rr.
Example: The instruction “LD WA, 0x1234” loads 0x34 and 0x12 into A and W respectively.
0 0 0 0
LD (x),n
n n n n
Load the immediate n in the instruction code into 8-bit register r.
Example: The instruction “LD A, 0x53” loads 0x53 into A.
0 1 0 0
LD rr,mn
1 r r r n n n n
1 0 1 0 x x x x
x x x x n n n n
n n n n 1 – – – – – 4
(x) ← n
Store the immediate n in the instruction code into the memory location directly addressed by x. (0x0000 ≤ x ≤ 0x00FF)
1 1 1 1
1 1 1 1
0 0 0 1 w w w w
1 0 0 1 n n n n
w w w w v v v v
n n n n
v v v v 1 – – – – – 6
(vw) ← n
Store the immediate n in the instruction code into the memory location directly addressed by vw. (0x0000 ≤ vw ≤ 0xFFFF)
1 1 1 1
0 0 1 0 1 1 1 1
1 0 0 1 n n n n
n n n n 1 – – – – – 4
LD (DE),n
(DE) ← n
Store the immediate n in the instruction code into the memory location addressed by DE.
0 0 0 0
1 0 1 1 n n n n
n n n n
1 – – – – – 3
LD (HL),n
(HL) ← n
Store the immediate n in the instruction code into the memory location addressed by HL.
1 1 1 1
0 1 0 0 1 1 1 1
1 0 0 1 n n n n
n n n n 1 – – – – – 4
(IX) ← n
LD (IX),n
Store the immediate n in the instruction code into the memory location addressed by IX.
1 1 1 1
0 1 0 1 1 1 1 1
1 0 0 1 n n n n
n n n n 1 – – – – – 4
LD (IY),n
(IY) ← n
Store the immediate n in the instruction code into the memory location addressed by IY.
0 1 0 1
n n n n
0 1 0 0 d d d d
n n n n
d d d d 1 1 1 1
1 0 0 1 1 – – – – – 5
(IX+d) ← n
LD (IX+d),n
Sign-extend the 8-bit displacement d in the instruction code and add the result to IX to form an effective address (EA). Store the immediate
n in the instruction code into the memory location at the EA.
0 1 0 1
n n n n
0 1 0 1 d d d d
n n n n
d d d d 1 1 1 1
1 0 0 1 1 – – – – – 5
(IY+d) ← n
LD (IY+d),n
Sign-extend the 8-bit displacement d in the instruction code and add the result to IY to form an effective address (EA). Store the immediate
n in the instruction code into the memory location at the EA.
0 1 0 1
n n n n
0 1 1 0 d d d d
n n n n
d d d d 1 1 1 1
1 0 0 1 1 – – – – – 5
(SP+d) ← n
LD (SP+d),n
Sign-extend the 8-bit displacement d in the instruction code and add the result to SP to form an effective address (EA). Store the immediate n in the instruction code into the memory location at the EA.
0 1 0 1
n n n n
0 1 1 1 d d d d
n n n n
d d d d 1 1 1 1
1 0 0 1 1 – – – – – 5
(HL+d) ← n
LD (HL+d),n
Sign-extend the 8-bit displacement d in the instruction code and add the result to HL to form an effective address (EA). Store the immediate n in the instruction code into the memory location at the EA.
1 1 1 1
LD (HL+C),n
0 1 1 1 1 1 1 1
1 0 0 1 n n n n
n n n n 1 – – – – – 6
(HL+C) ← n
Sign-extend the contents of C and add the result to HL to form an effective address (EA). Store the immediate n in the instruction code into
the memory location at the EA.
1 1 1 1
0 1 1 0 1 1 1 1
1 0 0 1 n n n n
n n n n 1 – – – – – 5
LD (SP−),n
(SP) ← n:SP ← SP−1
Store the immediate n in the instruction code into the memory location addressed by SP. Then, decrement the contents of the SP.
0 0 0 0
mmmm
LDW (x),mn
RA000
n n n n 1 – – – – – 6
(x+1, x) ← mn
high-order byte. (0x0000 ≤ x ≤ 0x00FF)
Example: The instruction “LDW (0x73), 0x1234” stores 0x34 and 0x12 into memory locations at addresses 0x0073 and 0x0074 respectively.
1 0 0 1 n n n n
n n n n mmmm
mmmm 1 – – – – – 5
(HL+1, HL) ← mn
Store the 16-bit immediate mn into 2 consecutive memory locations addressed by HL with the low-order byte first, followed by the highorder byte.
0 1 0 1
PUSH rr#1
x x x x n n n n
Store the 16-bit immediate mn into 2 consecutive memory locations directly addressed by x with the low-order byte first, followed by the
0 0 0 0
LDW (HL),mn
1 0 0 0 x x x x
mmmm
0 0 r r
– – – – – – 3
(SP, SP−1) ← rr:SP ← SP−2
Store the high-order byte of rr into the memory location addressed by SP, and the low-order byte into the memory location at (SP-1). Then,
decrement the contents of SP by 2. rr must be WA, BC, DE or HL.
Example: Assume SP and IX contain 0x013F and 0x1234 respectively. Then, the instruction “PUSH IX” stores 0x12 and 0x34 into the
memory locations at addresses 0x013F and 0x013E respectively. At the same time, the contents of SP is decremented to 0x013D.
Page 22
TLCS-870/C1
Flag
Mnemonic
Instruction Code (Binary)
Cycle
Operation
J Z C H S V
1 1 1 0
PUSH gg#2
1 g g g 1 1 0 1
1 0 0 0
– – – – – – 4
(SP, SP−1) ← gg:SP ← SP−2
Store the high-order byte of gg into the memory location addressed by SP, and the low-order byte into the memory location at (SP-1).
Then, decrement the contents of SP by 2.
Example: Assume SP and IX contain 0x013F and 0x1234 respectively. Then, the instruction “PUSH IX” stores 0x12 and 0x34 into the
memory locations at addresses 0x013F and 0x013E respectively. At the same time, the contents of SP is decremented to 0x013D.
1 1 0 1
0 0 r r
– – – – – – 4
SP ← SP+2:rr ← (SP, SP−1)
POP rr#1
Load the contents of the memory location at (SP+2) into the high-order 8 bits of rr. Load the contents of the memory location at (SP+1) into
the low-order 8 bits of rr. rr must be WA, BC, DE or HL.
POP gg#2
Load the contents of the memory location at (SP+2) into the high-order 8 bits of gg. Load the contents of the memory location at (SP+1)
into the low-order 8 bits of gg.
1 1 1 0
1 1 1 0
PUSH PSW
– – – – – – 5
1 1 0 0
– – – – – – 3
SP ← SP+2:gg ← (SP, SP−1)
(SP) ← PSW:SP ← SP−1
1 0 0 0 1 1 0 1
1 1 0 1
* * * * * * 4
SP ← SP+1:PSW ← (SP)
Load the contents of the memory location at (SP+1) into PSW.
Example: Assume the memory location at address 0x0137 and SP contain 0x63 and 0x0136 respectively. Then, the instruction “POP
PSW” increments the contents of SP to 0x0137 and loads 0x62 (JF = HF = SF = VF =0, ZF = CF = RBS = 1) into PSW.
1 1 1 0
LD PSW,n
1 0 0 0 1 1 0 1
1 0 0 1
Store the contents of PSW into the memory location addressed by SP. Then, decrement the contents of SP.
Example: Assume SP contains 0x2345 and PSW contains 0x62 (JF = HF = SF = VF =0, ZF = CF = RBS = 1). Then, the instruction “PUSH
PSW” stores 0x62 into the memory location at address 0x2345. At the same time, contents of SP is decremented to 0x2344.
1 1 1 0
POP PSW
1 g g g 1 1 0 1
1 0 0 0 1 1 0 1
1 1 1 0 n n n n
n n n n * * * * * * 3
PSW ← n.7-1
Load the immediate n in the instruction code into PSW. Each bit in the immediate n, beginning with the most significant bit, corresponds to
the JF, ZF, CF, HF, SF, VF and RBS respectively; the least significant bit is ignored.
Example: The “LD FLAG, 0y00110100” sets the flag bits as follows: JF = 0, ZF = 0, CF = 1, HF = 1, SF = 0, VF = 1 and RBS = 0.
1 1 1 1
1 0 0 1 0 0 0 0
0 0 0 0
– – – – – – 2
LD RBS,0
RBS ← 0
Load a 0 into the RBS bit in PSW to select the register bank BANK0. This instruction does not affect the flag bits.
1 1 1 1
1 0 0 1 0 0 0 0
0 0 1 0
– – – – – – 2
RBS ← 1
LD RBS,1
Load a 1 into the RBS bit in PSW to select the register bank BANK1. This instruction does not affect the flag bits.
0 0 1 1
LD SP,SP+d
1 1 1 1 d d d d
d d d d
1 – – – – – 2
SP ← SP−d
1 g g g 0 1 1 1
0 r r r
1 Z – – – – 3
r↔g
1 g g g 0 1 1 1
1 r r r
1 – – – – – 3
rr ↔ gg
Exchange the contents of 16-bit register pair rr with that of 16-bit register pair gg. The Zero flag remains unchanged.
Example: Assume HL and DE contain 0x0123 and 0x9587 respectively. Then, the instruction “XCH HL, DE” stores 0x9587 and 0x0123
into HL and DE.
1 1 1 0
XCH r,(x)
SP ← SP+d
Exchange the contents of 8-bit register r with that of 8-bit register g. The Zero flag is set to 1 when the contents of g before the instruction
execution is 0x00; otherwise, it is cleared to 0.
Example: Assume A and B contain 0x3C and 0x5C respectively. Then, the instruction “XCH A, B” stores 0x5F and 0x3C into A and B, and
clears ZF to 0.
1 1 1 0
XCH rr,gg
1 – – – – – 2
Subtract the 8-bit displacement d in the instruction code from the contents of SP and write back the result into SP. This instruction operates
like an subtract immediate instruction for SP.
1 1 1 0
XCH r,g
d d d d
Add the 8-bit displacement d in the instruction code to the contents of SP and write back the sum into SP. This instruction operates like an
add immediate instruction for SP.
Example: Assume SP contains 0x2345. The instruction “LD SP, SP + 4” loads 0x2349 into SP and sets JF to 1.
0 0 1 1
LD SP,SP−d
0 1 1 1 d d d d
0 0 0 0 x x x x
x x x x 0 1 1 1
0 r r r 1 Z – – – – 5
r ↔ (x)
Exchange the contents of the memory location directly addressed by x with that of 8-bit register r. The Zero flag is set to 1 when the value
stored into r register is 0x00. (0x0000 ≤ x ≤ 0x00FF)
1 1 1 0
0 1 1 1
XCH r,(vw)
0 0 0 1 w w w w
0 r r r
w w w w v v v v
v v v v 1 Z – – – – 6
r ↔ (vw)
Exchange the contents of the memory location directly addressed by vw with that of 8-bit register r. The Zero flag is set to 1 when the value
stored into r register is 0x00. (0x0000 ≤ vw ≤ 0xFFFF)
1 1 1 0
XCH r,(DE)
RA000
1 Z – – – – 4
r ↔ (DE)
0 0 1 1 0 1 1 1
0 r r r
1 Z – – – – 4
r ↔ (HL)
Exchange the contents of the memory location addressed by HL with that of 8-bit register r. The Zero flag is set to 1 when the value stored
into r register is 0x00.
1 1 1 0
XCH r,(IX)
0 r r r
Exchange the contents of the memory location addressed by DE with that of 8-bit register r. The Zero flag is set to 1 when the value stored
into r register is 0x00.
1 1 1 0
XCH r,(HL)
0 0 1 0 0 1 1 1
0 1 0 0 0 1 1 1
0 r r r
1 Z – – – – 4
r ↔ (IX)
Exchange the contents of the memory location addressed by IX with that of 8-bit register r. The Zero flag is set to 1 when the value stored
into r register is 0x00.
Page 23
2.1 Load/Store and Exchange Instructions
2.1 Load/Store and Exchange Instructions
TLCS-870/C1
Flag
Mnemonic
Instruction Code (Binary)
Cycle
Operation
J Z C H S V
1 1 1 0
0 1 0 1 0 1 1 1
0 r r r
1 Z – – – – 4
r ↔ (IY)
XCH r,(IY)
Exchange the contents of the memory location addressed by IY with that of 8-bit register r. The Zero flag is set to 1 when the value stored
into r register is 0x00.
XCH r,(IX+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to IX to form an effective address (EA). Exchange the contents of the memory location at the EA with that of 8-bit register r. The Zero flag is set to 1 when the value stored into r register is 0x00.
XCH r,(IY+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to IY to form an effective address (EA). Exchange the contents of the memory location at the EA with that of 8-bit register r. The Zero flag is set to 1 when the value stored into r register is 0x00.
XCH r,(SP+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to SP to form an effective address (EA). Exchange the contents of the memory location at the EA with that of 8-bit register r. The Zero flag is set to 1 when the value stored into r register is 0x00.
XCH r,(HL+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to HL to form an effective address (EA). Exchange the contents of the memory location at the EA with that of 8-bit register r. The Zero flag is set to 1 when the value stored into r register is 0x00.
XCH r,(HL+C)
Sign-extend the contents of C and add the result to HL to form an effective address (EA). Exchange the contents of the memory location
at the EA with that of 8-bit register r. The Zero flag is set to 1 when the value stored into r register is 0x00.
XCH r, (+SP)
Exchange the contents of the memory location at (SP+1) with that of 8-bit register r. The Zero flag is set to 1 when the value stored into r
register is 0x00.
XCH r,(PC+A)Note
Sign-extend the contents of A and add the result to PC to form an effective address (EA). Exchange the contents of the memory location
at the EA with that of 8-bit register r. The Zero flag is set to 1 when the value stored into r register is 0x00.
1 1 0 1
1 1 0 1
1 1 0 1
1 1 0 1
1 1 1 0
1 1 1 0
0 1 0 0
1 1 1 0
XCH rr,(x)
XCH rr,(vw)
0 1 0 0 d d d d
0 1 0 1 d d d d
0 1 1 0 d d d d
0 1 1 1 d d d d
0 1 1 1 0 1 1 1
0 1 1 0 0 1 1 1
1 1 1 1 0 1 1 1
0 0 0 0 x x x x
d d d d 0 1 1 1
d d d d 0 1 1 1
d d d d 0 1 1 1
d d d d 0 1 1 1
0 r r r
0 r r r 1 Z – – – – 6
0 r r r 1 Z – – – – 6
0 r r r 1 Z – – – – 6
0 r r r 1 Z – – – – 6
1 Z – – – – 6
0 r r r
1 Z – – – – 5
0 r r r
1 Z – – – – 6
x x x x 1 1 0 1
1 r r r 1 – – – – – 7
r ↔ (IX+d)
r ↔ (IY+d)
r ↔ (SP+d)
r ↔ (HL+d)
r ↔ (HL+C)
SP ← SP+1:r ↔ (SP)
r ↔ (PC+A)
rr ↔ (x+1, x)
Exchange the 16-bit memory word directly addressed by x with the contents of 16-bit register pair rr. (0x0000 ≤ x ≤ 0x00FF)
1 1 1 0
1 1 0 1
0 0 0 1 w w w w
1 r r r
w w w w v v v v
v v v v 1 – – – – – 8
rr ↔ (vw+1, vw)
Exchange the 16-bit memory word directly addressed by vw with the contents of 16-bit register pair rr. (0x0000 ≤ vw ≤ 0xFFFF)
1 1 1 0
0 0 1 0 1 1 0 1
1 r r r
1 – – – – – 6
rr ↔ (DE+1, DE)
XCH rr,(DE)
Exchange the 16-bit memory word addressed by DE with the contents of 16-bit register pair rr.
1 1 1 0
0 0 1 1 1 1 0 1
1 r r r
1 – – – – – 6
XCH rr,(HL)
rr ↔ (HL+1, HL)
Exchange the 16-bit memory word addressed by HL with the contents of 16-bit register pair rr.
1 1 1 0
0 1 0 0 1 1 0 1
1 r r r
1 – – – – – 6
XCH rr,(IX)
rr ↔ (IX+1, IX)
Exchange the 16-bit memory word addressed by IX with the contents of 16-bit register pair rr.
1 1 1 0
0 1 0 1 1 1 0 1
1 r r r
1 – – – – – 6
rr ↔ (IY+1, IY)
XCH rr,(IY)
Exchange the 16-bit memory word addressed by IY with the contents of 16-bit register pair rr.
1 1 0 1
0 1 0 0 d d d d
d d d d 1 1 0 1
1 r r r 1 – – – – – 8
rr ↔ (IX+d+1, IX+d)
XCH rr,(IX+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to IX to form an effective address (EA). Exchange the 16-bit
memory word addressed by the EA with the contents of 16-bit register pair rr.
XCH rr,(IY+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to IY to form an effective address (EA). Exchange the 16-bit
memory word addressed by the EA with the contents of 16-bit register pair rr.
XCH rr,(SP+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to SP to form an effective address (EA). Exchange the 16bit memory word addressed by the EA with the contents of 16-bit register pair rr.
XCH rr,(HL+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to HL to form an effective address (EA). Exchange the 16bit memory word addressed by the EA with the contents of 16-bit register pair rr.
XCH rr,(HL+C)
Sign-extend the contents of C and add the result to HL to form an effective address (EA). Exchange the 16-bit memory word addressed by
the EA with the contents of 16-bit register pair rr.
1 1 0 1
1 1 0 1
1 1 0 1
1 1 1 0
1 1 1 0
0 1 0 1 d d d d
0 1 1 0 d d d d
0 1 1 1 d d d d
0 1 1 1 1 1 0 1
0 1 1 0 1 1 0 1
d d d d 1 1 0 1
d d d d 1 1 0 1
d d d d 1 1 0 1
1 r r r
1 r r r 1 – – – – – 8
1 r r r 1 – – – – – 8
1 r r r 1 – – – – – 8
1 – – – – – 8
1 r r r
1 – – – – – 7
XCH rr,(+SP)
rr ↔ (IY+d+1, IY+d)
rr ↔ (SP+d+1, SP+d)
rr ↔ (HL+d+1, HL+d)
rr ↔ (HL+C+1, HL+C)
SP ← SP+1:rr ↔ (SP+1, SP)
Exchange the 16-bit memory word addressed by (SP+1) with the contents of 16-bit register pair rr.
0 1 0 0
XCH
rr,(PC+A)Note
RA000
1 1 1 1 1 1 0 1
1 r r r
1 – – – – – 8
rr ↔ (PC+A+1, PC+A)
Sign-extend the contents of A and add the result to PC to form an effective address (EA). Exchange the 16-bit memory word addressed by
the EA with the contents of 16-bit register pair rr.
Page 24
TLCS-870/C1
#1
#2
rr must be the register pair WA, BC, DE or HL.
gg must be the register IX or IY.
Note: There are restrictions on instructions that uses the operand (PC + A). For more details, see "1.4 Addressing Mode".
RA000
Page 25
2.1 Load/Store and Exchange Instructions
2.1 Load/Store and Exchange Instructions
RA000
TLCS-870/C1
Page 26
TLCS-870/C1
2.2 ALU Instructions
Flag
Mnemonic
Instruction Code (Binary)
Cycle
Operation
J Z C H S V
0 1 1 0
0 1 1 1 n n n n
n n n n
Z Z C H S V 2
A–n
CMP A,n
Compare the contents of A with the immediate n in the instruction code. The Carry flag is set to 1 when A < n; otherwise, it is cleared to 0.
1 1 1 0
CMP g,n
1 g g g 0 1 1 0
0 1 1 1 n n n n
n n n n Z Z C H S V 3
g–n
Compare the contents of 8-bit register g with the immediate n in the instruction code. The Carry flag is set to 1 when g < n; otherwise, it is
cleared to 0.
1 1 1 0
mmmm
1 g g g 0 1 1 0
mmmm
1 1 1 1 n n n n
n n n n Z Z C U S V 4
gg–mn
CMP gg,mn
Compare the contents of 16-bit register gg with the immediate mn in the instruction code. The Carry flag is set to 1 when gg < n; otherwise,
it is cleared to 0.
1 1 1 0
1 g g g 0 0 r r
r 1 1 1
Z Z C H S V 2
r–g
CMP r,g
Compare the contents of 8-bit register r with that of 8-bit register g. The Carry flag is set to 1 when r < g; otherwise, it is cleared to 0.
1 1 1 0
1 g g g 1 0 r r
r 1 1 1
Z Z C U S V 3
rr–gg
r 1 1 1 Z Z C H S V 4
r–(x)
CMP rr,gg
Compare the contents of 16-bit register rr with that of 16-bit register gg.
1 1 1 0
CMP r,(x)
CMP r,(vw)
0 0 0 0 x x x x
x x x x 0 0 r r
Compare the contents of the memory location directly addressed by x with the contents of 8-bit register r. (0x0000 ≤ x ≤ 0x00FF)
1 1 1 0
0 0 r r
0 0 0 1 w w w w
r 1 1 1
w w w w v v v v
v v v v Z Z C H S V 5
r–(vw)
Compare the contents of the memory location directly addressed by vw with the contents of 8-bit register r. (0x0000 ≤ vw ≤ 0xFFFF)
1 1 1 0
0 0 1 0 0 0 r r
r 1 1 1
Z Z C H S V 3
r–(DE)
CMP r,(DE)
Compare the contents of the memory location addressed by DE with the contents of 8-bit register r.
1 1 1 0
0 0 1 1 0 0 r r
r 1 1 1
Z Z C H S V 3
r–(HL)
CMP r,(HL)
Compare the contents of the memory location addressed by HL with the contents of 8-bit register r.
1 1 1 0
0 1 0 0 0 0 r r
r 1 1 1
Z Z C H S V 3
r–(IX)
CMP r,(IX)
Compare the contents of the memory location addressed by IX with the contents of 8-bit register r.
1 1 1 0
0 1 0 1 0 0 r r
r 1 1 1
Z Z C H S V 3
r–(IY)
CMP r,(IY)
Compare the contents of the memory location addressed by IY with the contents of 8-bit register r.
1 1 0 1
CMP r,(IX+d)
0 1 0 1 d d d d
d d d d 0 0 r r
r 1 1 1 Z Z C H S V 5
r–(IY+d)
0 1 1 0 d d d d
d d d d 0 0 r r
r 1 1 1 Z Z C H S V 5
r–(SP+d)
0 1 1 1 d d d d
d d d d 0 0 r r
r 1 1 1 Z Z C H S V 5
r–(HL+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to HL to form an effective address (EA). Compare the contents of the memory location at the EA with the contents of 8-bit register r.
1 1 1 0
CMP r,(HL+C)
r–(IX+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to SP to form an effective address (EA). Compare the contents of the memory location at the EA with the contents of 8-bit register r.
1 1 0 1
CMP r,(HL+d)
r 1 1 1 Z Z C H S V 5
Sign-extend the 8-bit displacement d in the instruction code and add the result to IY to form an effective address (EA). Compare the contents of the memory location at the EA with the contents of 8-bit register r.
1 1 0 1
CMP r,(SP+d)
d d d d 0 0 r r
Sign-extend the 8-bit displacement d in the instruction code and add the result to IX to form an effective address (EA). Compare the contents of the memory location at the EA with the contents of 8-bit register r.
1 1 0 1
CMP r,(IY+d)
0 1 0 0 d d d d
0 1 1 1 0 0 r r
r 1 1 1
Z Z C H S V 5
r–(HL+C)
Sign-extend the contents of C and add the result to HL to form an effective address (EA). Compare the contents of the memory location at
the EA with the contents of 8-bit register r.
1 1 1 0
0 1 1 0 0 0 r r
r 1 1 1
Z Z C H S V 4
CMP r,(+SP)
SP ← SP+1:r–(SP)
Compare the contents of the memory location at (SP+1) with the contents of 8-bit register r.
0 1 0 0
CMP r,(PC+A)Note
0 0 0 0
CMP (x),n
r 1 1 1
Z Z C H S V 5
r–(PC+A)
0 1 1 1 x x x x
x x x x n n n n
n n n n Z Z C H S V 4
(x)–n
Compare the contents of the memory location directly addressed by x with the immediate n in the instruction code. (0x0000 ≤ x ≤ 0x00FF)
1 1 1 0
0 1 1 0
CMP (vw),n
1 1 1 1 0 0 r r
Sign-extend the contents of A and add the result to PC to form an effective address (EA). Compare the contents of the memory location at
the EA with the contents of 8-bit register r.
0 0 0 1 w w w w
0 1 1 1 n n n n
w w w w v v v v
n n n n
v v v v Z Z C H S V 6
(vw)–n
Compare the contents of the memory location directly addressed by vw with the immediate n in the instruction code. (0x0000 ≤ vw ≤
0xFFFF)
1 1 1 0
0 0 1 0 0 1 1 0
0 1 1 1 n n n n
n n n n Z Z C H S V 4
(DE)–n
CMP (DE),n
Compare the contents of the memory location addressed by DE with the immediate n in the instruction code.
RA000
Page 27
2.2 ALU Instructions
2.2 ALU Instructions
TLCS-870/C1
Flag
Mnemonic
Instruction Code (Binary)
Cycle
Operation
J Z C H S V
1 1 1 0
0 0 1 1 0 1 1 0
0 1 1 1 n n n n
n n n n Z Z C H S V 4
(HL)–n
CMP (HL),n
Compare the contents of the memory location addressed by HL with the immediate n in the instruction code.
1 1 1 0
0 1 0 0 0 1 1 0
0 1 1 1 n n n n
n n n n Z Z C H S V 4
(IX)–n
CMP (IX),n
Compare the contents of the memory location addressed by IX with the immediate n in the instruction code.
1 1 1 0
0 1 0 1 0 1 1 0
0 1 1 1 n n n n
n n n n Z Z C H S V 4
(IY)–n
CMP (IY),n
Compare the contents of the memory location addressed by IY with the immediate n in the instruction code.
1 1 0 1
n n n n
0 1 0 0 d d d d
n n n n
d d d d 0 1 1 0
0 1 1 1 Z Z C H S V 6
(IX+d)–n
CMP (IX+d),n
Sign-extend the 8-bit displacement d in the instruction code and add the result to IX to form an effective address (EA). Compare the contents of the memory location at the EA with the immediate n in the instruction code.
1 1 0 1
n n n n
0 1 0 1 d d d d
n n n n
d d d d 0 1 1 0
0 1 1 1 Z Z C H S V 6
(IY+d)–n
CMP (IY+d),n
Sign-extend the 8-bit displacement d in the instruction code and add the result to IY to form an effective address (EA). Compare the contents of the memory location at the EA with the immediate n in the instruction code.
1 1 0 1
n n n n
0 1 1 0 d d d d
n n n n
d d d d 0 1 1 0
0 1 1 1 Z Z C H S V 6
(SP+d)–n
CMP (SP+d),n
Sign-extend the 8-bit displacement d in the instruction code and add the result to SP to form an effective address (EA). Compare the contents of the memory location at the EA with the immediate n in the instruction code.
1 1 0 1
n n n n
0 1 1 1 d d d d
n n n n
d d d d 0 1 1 0
0 1 1 1 Z Z C H S V 6
(HL+d)–n
CMP (HL+d),n
Sign-extend the 8-bit displacement d in the instruction code and add the result to HL to form an effective address (EA). Compare the contents of the memory location at the EA with the immediate n in the instruction code.
1 1 1 0
CMP (HL+C),n
0 1 1 1 0 1 1 0
0 1 1 1 n n n n
n n n n Z Z C H S V 6
(HL+C)–n
Sign-extend the contents of C and add the result to HL to form an effective address (EA). Compare the contents of the memory location at
the EA with the immediate n in the instruction code.
1 1 1 0
0 1 1 0 0 1 1 0
0 1 1 1 n n n n
n n n n Z Z C H S V 5
SP ← SP+1:(SP)–n
CMP (+SP),n
Compare the contents of the memory location at (SP+1) and the immediate n in the instruction code.
0 1 0 0
CMP (PC+A),nNote
1 1 1 0
CMP rr,(x)
CMP rr,(vw)
1 1 1 1 0 1 1 0
0 1 1 1 n n n n
n n n n Z Z C H S V 6
(PC+A)–n
Sign-extend the contents of A and add the result to PC to form an effective address (EA). Compare the contents of the memory location at
the EA with the immediate n in the instruction code.
0 0 0 0 x x x x
x x x x 1 0 r r
r 1 1 1 Z Z C U S V 5
rr–(x)
Compare the 16-bit memory word directly addressed by x with the contents of 16-bit register rr. (0x0000 ≤ x ≤ 0x00FF)
1 1 1 0
1 0 r r
0 0 0 1 w w w w
r 1 1 1
w w w w v v v v
v v v v Z Z C U S V 6
rr–(vw)
Compare the 16-bit memory word directly addressed by vw with the contents of 16-bit register rr. (0x0000 ≤ vw ≤ 0xFFFF)
1 1 1 0
0 0 1 0 1 0 r r
r 1 1 1
Z Z C U S V 4
rr–(DE)
CMP rr,(DE)
Compare the 16-bit memory word addressed by DE with the contents of 16-bit register rr.
1 1 1 0
0 0 1 1 1 0 r r
r 1 1 1
Z Z C U S V 4
rr–(HL)
CMP rr,(HL)
Compare the 16-bit memory word addressed by HL with the contents of 16-bit register rr.
1 1 1 0
0 1 0 0 1 0 r r
r 1 1 1
Z Z C U S V 4
rr–(IX)
CMP rr,(IX)
Compare the 16-bit memory word addressed by IX with the contents of 16-bit register rr.
1 1 1 0
0 1 0 1 1 0 r r
r 1 1 1
Z Z C U S V 4
rr–(IY)
CMP rr,(IY)
Compare the 16-bit memory word addressed by IY with the contents of 16-bit register rr.
1 1 0 1
0 1 0 0 d d d d
d d d d 1 0 r r
r 1 1 1 Z Z C U S V 6
rr–(IX+d)
CMP rr,(IX+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to IX to form an effective address (EA). Compare the 16-bit
memory word addressed by the EA with the contents of 16-bit register rr.
CMP rr,(IY+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to IY to form an effective address (EA). Compare the 16-bit
memory word addressed by the EA with the contents of 16-bit register rr.
CMP rr,(SP+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to SP to form an effective address (EA). Compare the 16bit memory word addressed by the EA with the contents of 16-bit register rr.
CMP rr,(HL+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to HL to form an effective address (EA). Compare the 16-bit
memory word addressed by the EA with the contents of 16-bit register rr.
1 1 0 1
1 1 0 1
1 1 0 1
RA000
0 1 0 1 d d d d
0 1 1 0 d d d d
0 1 1 1 d d d d
d d d d 1 0 r r
d d d d 1 0 r r
d d d d 1 0 r r
Page 28
r 1 1 1 Z Z C U S V 6
r 1 1 1 Z Z C U S V 6
r 1 1 1 Z Z C U S V 6
rr–(IY+d)
rr–(SP+d)
rr–(HL+d)
TLCS-870/C1
Flag
Mnemonic
Instruction Code (Binary)
Cycle
Operation
J Z C H S V
1 1 1 0
CMP rr,(HL+C)
0 1 1 1 1 0 r r
r 1 1 1
Z Z C U S V 6
rr–(HL+C)
Sign-extend the contents of C and add the result to HL to form an effective address (EA). Compare the 16-bit memory word addressed by
the EA with the contents of 16-bit register rr.
1 1 1 0
0 1 1 0 1 0 r r
r 1 1 1
Z Z C U S V 5
CMP rr,(+SP)
SP ← SP+1:rr–(SP)
Compare the 16-bit memory word addressed by (SP+1) with the contents of 16-bit register rr.
0 1 0 0
1 1 1 1 1 0 r r
r 1 1 1
Z Z C U S V 6
rr–(PC+A)
CMP rr,(PC+A)Note Sign-extend the contents of A and add the result to PC to form an effective address (EA). Compare the 16-bit memory word addressed by
the EA with the contents of 16-bit register rr.
0 1 1 0
0 0 0 1 n n n n
n n n n
C Z C H S V 2
ADD A,n
A ← A+n
Add the immediate n in the instruction code to the contents of A and write back the sum into A.
1 1 1 0
1 g g g 0 1 1 0
0 0 0 1 n n n n
n n n n C Z C H S V 3
ADD g,n
g ← g+n
Add the immediate n in the instruction code to the contents of 8-bit register g and write back the sum into g.
ADD gg,mn
1 1 1 0
mmmm
1 g g g 0 1 1 0
mmmm
1 0 0 1 n n n n
n n n n C Z C U S V 4
gg ← gg+mn
Add the immediate mn in the instruction code to the contents of 16-bit register gg and write back the sum into gg.
1 1 1 0
1 g g g 0 0 r r
r 0 0 1
C Z C H S V 2
ADD r,g
r ← r+g
Add the contents of 8-bit register g to that of 8-bit register r and write back the sum into r.
1 1 1 0
1 g g g 1 0 r r
r 0 0 1
C Z C U S V 3
ADD rr,gg
rr ← rr+gg
Add the contents of 16-bit register gg to that of 16-bit register rr and write back the sum into rr.
1 1 1 0
ADD r,(x)
ADD r,(vw)
0 0 0 0 x x x x
x x x x 0 0 r r
r 0 0 1 C Z C H S V 4
r ← r+(x)
Add the contents of the memory location directly addressed by x to that of 8-bit register r and write back the sum into r. (0x0000 ≤ x ≤
0x00FF)
1 1 1 0
0 0 r r
0 0 0 1 w w w w
r 0 0 1
w w w w v v v v
v v v v C Z C H S V 5
r ← r+(vw)
Add the contents of the memory location directly addressed by vw to that of 8-bit register r and write back the sum into r. (0x0000 ≤ vw ≤
0xFFFF)
1 1 1 0
0 0 1 0 0 0 r r
r 0 0 1
C Z C H S V 3
ADD r,(DE)
r ← r+(DE)
Add the contents of the memory location addressed by DE to that of 8-bit register r and write back the sum into r.
1 1 1 0
0 0 1 1 0 0 r r
r 0 0 1
C Z C H S V 3
ADD r,(HL)
r ← r+(HL)
Add the contents of the memory location addressed by HL to that of 8-bit register r and write back the sum into r.
1 1 1 0
0 1 0 0 0 0 r r
r 0 0 1
C Z C H S V 3
r ← r+(IX)
ADD r,(IX)
Add the contents of the memory location addressed by IX to that of 8-bit register r and write back the sum into r.
1 1 1 0
0 1 0 1 0 0 r r
r 0 0 1
C Z C H S V 3
ADD r,(IY)
r ← r+(IY)
Add the contents of the memory location addressed by IY to that of 8-bit register r and write back the sum into r.
1 1 0 1
ADD r,(IX+d)
0 1 0 1 d d d d
d d d d 0 0 r r
r 0 0 1 C Z C H S V 5
r ← r+(IY+d)
0 1 1 0 d d d d
d d d d 0 0 r r
r 0 0 1 C Z C H S V 5
r ← r+(SP+d)
0 1 1 1 d d d d
d d d d 0 0 r r
r 0 0 1 C Z C H S V 5
r ← r+(HL+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to HL to form an effective address (EA). Add the contents
of the memory location at the EA to that of 8-bit register r and write back the sum into r.
1 1 1 0
ADD r,(HL+C)
r ← r+(IX+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to SP to form an effective address (EA). Add the contents
of the memory location at the EA to that of 8-bit register r and write back the sum into r.
1 1 0 1
ADD r,(HL+d)
r 0 0 1 C Z C H S V 5
Sign-extend the 8-bit displacement d in the instruction code and add the result to IY to form an effective address (EA). Add the contents of
the memory location at the EA to that of 8-bit register r and write back the sum into r.
1 1 0 1
ADD r,(SP+d)
d d d d 0 0 r r
Sign-extend the 8-bit displacement d in the instruction code and add the result to IX to form an effective address (EA). Add the contents of
the memory location at the EA to that of 8-bit register r and write back the sum into r.
1 1 0 1
ADD r,(IY+d)
0 1 0 0 d d d d
0 1 1 1 0 0 r r
r 0 0 1
C Z C H S V 5
r ← r+(HL+C)
Sign-extend the contents of C and add the result to HL to form an effective address (EA). Add the contents of the memory location at the
EA to that of 8-bit register r and write back the sum into r.
1 1 1 0
0 1 1 0 0 0 r r
r 0 0 1
C Z C H S V 4
ADD r,(+SP)
SP ← SP+1:r ← r+(SP)
Add the contents of the memory location at (SP+1) to the contents of 8-bit register r and write back the sum into r.
0 1 0 0
ADD r,(PC+A)Note
RA000
1 1 1 1 0 0 r r
r 0 0 1
C Z C H S V 5
r ← r+(PC+A)
Sign-extend the contents of A and add the result to PC to form an effective address (EA). Add the contents of the memory location at the
EA to that of 8-bit register r and write back the sum into r.
Page 29
2.2 ALU Instructions
2.2 ALU Instructions
TLCS-870/C1
Flag
Mnemonic
Instruction Code (Binary)
Cycle
Operation
J Z C H S V
1 1 1 0
n n n n
ADD (x),n
0 0 0 0 x x x x
n n n n
x x x x 0 1 1 0
0 0 0 1 C Z C H S V 6
(x) ← (x)+n
Add the immediate n in the instruction code to the contents of the memory location directly addressed by x and write back the sum into the
same location. (0x0000 ≤ x ≤ 0x00FF)
1 1 1 0
0 1 1 0
ADD (vw),n
0 0 0 1 w w w w
0 0 0 1 n n n n
w w w w v v v v
n n n n
v v v v C Z C H S V 7
(vw) ← (vw)+n
Add the immediate n in the instruction code to the contents of the memory location directly addressed by vw and write back the sum into
the same location. (0x0000 ≤ vw ≤ 0xFFFF)
1 1 1 0
ADD (DE),n
(DE) ← (DE)+n
0 0 1 1 0 1 1 0
0 0 0 1 n n n n
n n n n C Z C H S V 5
(HL) ← (HL)+n
0 1 0 0 0 1 1 0
0 0 0 1 n n n n
n n n n C Z C H S V 5
(IX) ← (IX)+n
Add the immediate n in the instruction code to the contents of the memory location addressed by IX and write back the sum into the same
location.
1 1 1 0
ADD (IY),n
n n n n C Z C H S V 5
Add the immediate n in the instruction code to the contents of the memory location addressed by HL and write back the sum into the same
location.
1 1 1 0
ADD (IX),n
0 0 0 1 n n n n
Add the immediate n in the instruction code to the contents of the memory location addressed by DE and write back the sum into the same
location.
1 1 1 0
ADD (HL),n
0 0 1 0 0 1 1 0
0 1 0 1 0 1 1 0
0 0 0 1 n n n n
n n n n C Z C H S V 5
(IY) ← (IY)+n
Add the immediate n in the instruction code to the contents of the memory location addressed by IY and write back the sum into the same
location.
1 1 0 1
n n n n
0 1 0 0 d d d d
n n n n
d d d d 0 1 1 0
0 0 0 1 C Z C H S V 7
(IX+d) ← (IX+d)+n
ADD (IX+d),n
Sign-extend the 8-bit displacement d in the instruction code and add the result to IX to form an effective address (EA). Add the immediate
n in the instruction code to the contents of the memory location at the EA and write back the sum into the same location.
1 1 0 1
n n n n
0 1 0 1 d d d d
n n n n
d d d d 0 1 1 0
0 0 0 1 C Z C H S V 7
(IY+d) ← (IY+d)+n
ADD (IY+d),n
Sign-extend the 8-bit displacement d in the instruction code and add the result to IY to form an effective address (EA). Add the immediate
n in the instruction code to the contents of the memory location at the EA and write back the sum into the same location.
1 1 0 1
n n n n
0 1 1 0 d d d d
n n n n
d d d d 0 1 1 0
0 0 0 1 C Z C H S V 7
(SP+d) ← (SP+d)+n
ADD (SP+d),n
Sign-extend the 8-bit displacement d in the instruction code and add the result to SP to form an effective address (EA). Add the immediate
n in the instruction code to the contents of the memory location at the EA and write back the sum into the same location.
1 1 0 1
n n n n
0 1 1 1 d d d d
n n n n
d d d d 0 1 1 0
0 0 0 1 C Z C H S V 7
(HL+d) ← (HL+d)+n
ADD (HL+d),n
Sign-extend the 8-bit displacement d in the instruction code and add the result to HL to form an effective address (EA). Add the immediate
n in the instruction code to the contents of the memory location at the EA and write back the sum into the same location.
1 1 1 0
ADD (HL+C),n
(HL+C) ← (HL+C)+n
0 1 1 0 0 1 1 0
0 0 0 1 n n n n
n n n n C Z C H S V 6
SP ← SP+1:(SP) ← (SP)+n
1 1 1 1 0 1 1 0
0 0 0 1 n n n n
n n n n C Z C H S V 7
(PC+A) ← (PC+A)+n
Sign-extend the contents of A and add the result to PC to form an effective address (EA). Add the immediate n in the instruction code to
the contents of the memory location at the EA and write back the sum into the same location.
1 1 1 0
ADD rr,(x)
n n n n C Z C H S V 7
Add the immediate n in the instruction code to the contents of the memory location at (SP+1) and write back the sum into the same location.
0 1 0 0
ADD (PC+A),nNote
0 0 0 1 n n n n
Sign-extend the contents of C and add the result to HL to form an effective address (EA). Add the immediate n in the instruction code to
the contents of the memory location at the EA and write back the sum into the same location.
1 1 1 0
ADD (+SP),n
0 1 1 1 0 1 1 0
0 0 0 0 x x x x
x x x x 1 0 r r
r 0 0 1 C Z C U S V 5
rr ← rr+(x+1, x)
Add the 16-bit memory word directly addressed by x to the contents of 16-bit register rr and write back the sum into rr.
(0x0000 ≤ x ≤ 0x00FF)
1 1 1 0
1 0 r r
ADD rr,(vw)
0 0 0 1 w w w w
r 0 0 1
w w w w v v v v
v v v v C Z C U S V 6
rr ← rr+(vw+1, vw)
Add the 16-bit memory word directly addressed by vw to the contents of 16-bit register rr and write back the sum into rr.
(0x0000 ≤ vw ≤ 0xFFFF)
1 1 1 0
0 0 1 0 1 0 r r
r 0 0 1
C Z C U S V 4
ADD rr,(DE)
rr ← rr+(DE+1, DE)
Add the 16-bit memory word addressed by DE to the contents of 16-bit register rr and write back the sum into rr.
1 1 1 0
0 0 1 1 1 0 r r
r 0 0 1
C Z C U S V 4
ADD rr,(HL)
rr ← rr+(HL+1, HL)
Add the 16-bit memory word addressed by HL to the contents of 16-bit register rr and write back the sum into rr.
1 1 1 0
0 1 0 0 1 0 r r
r 0 0 1
C Z C U S V 4
ADD rr,(IX)
rr ← rr+(IX+1, IX)
Add the 16-bit memory word addressed by IX to the contents of 16-bit register rr and write back the sum into rr.
RA000
Page 30
TLCS-870/C1
Flag
Mnemonic
Instruction Code (Binary)
Cycle
Operation
J Z C H S V
1 1 1 0
0 1 0 1 1 0 r r
r 0 0 1
C Z C U S V 4
rr ← rr+(IY+1, IY)
ADD rr,(IY)
Add the 16-bit memory word addressed by IY to the contents of 16-bit register rr and write back the sum into rr.
1 1 0 1
ADD rr,(IX+d)
0 1 0 1 d d d d
d d d d 1 0 r r
r 0 0 1 C Z C U S V 6
rr ← rr+(IY+d+1, IY+d)
0 1 1 0 d d d d
d d d d 1 0 r r
r 0 0 1 C Z C U S V 6
rr ← rr+(SP+d+1, SP+d)
0 1 1 1 d d d d
d d d d 1 0 r r
r 0 0 1 C Z C U S V 6
rr ← rr+(HL+d+1, HL+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to HL to form an effective address (EA). Add the 16-bit
memory word addressed by the EA to the contents of 16-bit register rr and write back the sum into rr.
1 1 1 0
ADD rr,(HL+C)
rr ← rr+(IX+d+1, IX+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to SP to form an effective address (EA). Add the 16-bit
memory word addressed by the EA to the contents of 16-bit register rr and write back the sum into rr.
1 1 0 1
ADD rr,(HL+d)
r 0 0 1 C Z C U S V 6
Sign-extend the 8-bit displacement d in the instruction code and add the result to IY to form an effective address (EA). Add the 16-bit
memory word addressed by the EA to the contents of 16-bit register rr and write back the sum into rr.
1 1 0 1
ADD rr,(SP+d)
d d d d 1 0 r r
Sign-extend the 8-bit displacement d in the instruction code and add the result to IX to form an effective address (EA). Add the 16-bit
memory word addressed by the EA to the contents of 16-bit register rr and write back the sum into rr.
1 1 0 1
ADD rr,(IY+d)
0 1 0 0 d d d d
0 1 1 1 1 0 r r
r 0 0 1
C Z C U S V 6
rr ← rr+(HL+C+1, HL+C)
Sign-extend the contents of C and add the result to HL to form an effective address (EA). Add the 16-bit memory word addressed by the
EA to the contents of 16-bit register rr and write back the sum into rr.
1 1 1 0
0 1 1 0 1 0 r r
r 0 0 1
C Z C U S V 5
ADD rr,(+SP)
SP ← SP+1:rr ← rr+(SP+1, SP)
Add the 16-bit memory word addressed by (SP+1) to the contents of 16-bit register rr and write back the sum into rr.
0 1 0 0
ADD rr,(PC+A)Note
1 1 1 1 1 0 r r
r 0 0 1
C Z C U S V 6
rr ← rr+(PC+A+1, PC+A)
Sign-extend the contents of A and add the result to PC to form an effective address (EA). Add the 16-bit memory word addressed by the
EA to the contents of 16-bit register rr and write back the sum into rr.
0 1 1 0
0 0 0 0 n n n n
n n n n
C Z C H S V 2
A ← A+n+CF
ADDC A,n
Add both the immediate n in the instruction code and the contents of the Carry flag to A and write back the sum into A.
1 1 1 0
ADDC g,n
1 g g g 0 1 1 0
0 0 0 0 n n n n
n n n n C Z C H S V 3
g ← g+n+CF
Add both the immediate n in the instruction code and the contents of the Carry flag to the contents of 8-bit register g and write back the
sum into g.
1 1 1 0
mmmm
1 g g g 0 1 1 0
mmmm
1 0 0 0 n n n n
n n n n C Z C U S V 4
gg ← gg+mn+CF
ADDC gg,mn
Add both the immediate mn in the instruction code and the contents of the Carry flag to the contents of 16-bit register gg and write back the
sum into gg.
1 1 1 0
1 g g g 0 0 r r
r 0 0 0
C Z C H S V 2
r ← r+g+CF
ADDC r,g
Add both the contents of 8-bit register g and that of the Carry flag to the contents of 8-bit register r and write back the sum into r.
1 1 1 0
1 g g g 1 0 r r
r 0 0 0
C Z C U S V 3
ADDC rr,gg
rr ← rr+gg+CF
Add both the contents of 16-bit register gg and that of the Carry flag to the contents of 16-bit register rr and write back the sum into rr.
1 1 1 0
ADDC r,(x)
0 0 0 0 x x x x
x x x x 0 0 r r
r 0 0 0 C Z C H S V 4
r ← r+(x)+CF
Add both the contents of the memory location directly addressed by x and that of the Carry flag to the contents of 8-bit register r and write
back the sum into r. (0x0000 ≤ x ≤ 0x00FF)
1 1 1 0
0 0 r r
ADDC r, (vw)
0 0 0 1 w w w w
r 0 0 0
w w w w v v v v
v v v v C Z C H S V 5
r ← r+(vw)+CF
Add both the contents of the memory location directly addressed by vw and that of the Carry flag to the contents of 8-bit register r and write
back the sum into r. (0x0000 ≤ vw ≤ 0xFFFF)
1 1 1 0
0 0 1 0 0 0 r r
r 0 0 0
C Z C H S V 3
r ← r+(DE)+CF
ADDC r,(DE)
Add both the contents of the memory location addressed by DE and that of the Carry flag to the contents of 8-bit register r and write back
the sum into r.
ADDC r,(HL)
Add both the contents of the memory location addressed by HL and that of the Carry flag to the contents of 8-bit register r and write back
the sum into r.
ADDC r,(IX)
Add both the contents of the memory location addressed by IX and that of the Carry flag to the contents of 8-bit register r and write back
the sum into r.
ADDC r,(IY)
Add both the contents of the memory location addressed by IY and that of the Carry flag to the contents of 8-bit register r and write back
the sum into r.
ADDC r,(IX+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to IX to form an effective address (EA). Add both the contents of the memory location at the EA and that of the Carry flag to the contents of 8-bit register r and write back the sum into r.
1 1 1 0
1 1 1 0
1 1 1 0
1 1 0 1
RA000
0 0 1 1 0 0 r r
0 1 0 0 0 0 r r
0 1 0 1 0 0 r r
0 1 0 0 d d d d
r 0 0 0
C Z C H S V 3
r 0 0 0
C Z C H S V 3
r 0 0 0
C Z C H S V 3
d d d d 0 0 r r
Page 31
r 0 0 0 C Z C H S V 5
r ← r+(HL)+CF
r ← r+(IX)+CF
r ← r+(IY)+CF
r ← r+(IX+d)+CF
2.2 ALU Instructions
2.2 ALU Instructions
TLCS-870/C1
Flag
Mnemonic
Instruction Code (Binary)
Cycle
Operation
J Z C H S V
1 1 0 1
0 1 0 1 d d d d
d d d d 0 0 r r
r 0 0 0 C Z C H S V 5
r ← r+(IY+d)+CF
ADDC r,(IY+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to IY to form an effective address (EA). Add both the contents of the memory location at the EA and that of the Carry flag to the contents of 8-bit register r and write back the sum into r.
ADDC r,(SP+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to SP to form an effective address (EA). Add both the contents of the memory location at the EA and that of the Carry flag to the contents of 8-bit register r and write back the sum into r.
ADDC r,(HL+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to HL to form an effective address (EA). Add both the contents of the memory location at the EA and that of the Carry flag to the contents of 8-bit register r and write back the sum into r.
ADDC r,(HL+C)
Sign-extend the contents of C and add the result to HL to form an effective address (EA). Add both the contents of the memory location at
the EA and that of the Carry flag to the contents of 8-bit register r and write back the sum into r.
ADDC r,(+SP)
Add both the contents of the memory location at (SP+1) and that of the Carry flag to the contents of 8-bit register r and write back the sum
into r.
1 1 0 1
1 1 0 1
1 1 1 0
1 1 1 0
0 1 0 0
0 1 1 0 d d d d
0 1 1 1 d d d d
0 1 1 1 0 0 r r
0 1 1 0 0 0 r r
1 1 1 1 0 0 r r
d d d d 0 0 r r
d d d d 0 0 r r
r 0 0 0
r 0 0 0 C Z C H S V 5
r 0 0 0 C Z C H S V 5
C Z C H S V 5
r 0 0 0
C Z C H S V 4
r 0 0 0
C Z C H S V 5
r ← r+(SP+d)+CF
r ← r+(HL+d)+CF
r ← r+(HL+C)+CF
SP ← SP+1:r ← r+(SP)+CF
r ← r+(PC+A)+CF
ADDC r,(PC+A)Note Sign-extend the contents of A and add the result to PC to form an effective address (EA). Add both the contents of the memory location at
the EA and that of the Carry flag to the contents of 8-bit register r and write back the sum into r.
1 1 1 0
n n n n
ADDC (x),n
0 0 0 0 x x x x
n n n n
x x x x 0 1 1 0
0 0 0 0 C Z C H S V 6
(x) ← (x)+n+CF
Add both the immediate n in the instruction code and the contents of the Carry flag to the contents of the memory location directly
addressed by x. Then write back the sum into the same location. (0x0000 ≤ x ≤ 0x00FF)
1 1 1 0
0 1 1 0
ADDC (vw),n
0 0 0 1 w w w w
0 0 0 0 n n n n
w w w w v v v v
n n n n
v v v v C Z C H S V 7
(vw) ← (vw)+n+CF
Add both the immediate n in the instruction code and the contents of the Carry flag to the contents of the memory location directly
addressed by vw. Then write back the sum into the same location. (0x0000 ≤ vw ≤ 0xFFFF)
1 1 1 0
ADDC (DE),n
RA000
(HL) ← (HL)+n +CF
0 1 0 0 0 1 1 0
0 0 0 0 n n n n
n n n n C Z C H S V 5
(IX) ← (IX)+n+CF
0 1 0 1 0 1 1 0
0 0 0 0 n n n n
n n n n C Z C H S V 5
(IY) ← (IY)+n+CF
0 1 0 0 d d d d
n n n n
d d d d 0 1 1 0
0 0 0 0 C Z C H S V 7
(IX+d) ← (IX+d)+n+CF
0 1 0 1 d d d d
n n n n
d d d d 0 1 1 0
0 0 0 0 C Z C H S V 7
(IY+d) ← (IY+d)+n+CF
0 1 1 0 d d d d
n n n n
d d d d 0 1 1 0
0 0 0 0 C Z C H S V 7
(SP+d) ← (SP+d)+n+CF
Sign-extend the 8-bit displacement d in the instruction code and add the result to SP to form an effective address (EA). Add both the
immediate n in the instruction code and the contents of the Carry flag to the contents of the memory location at the EA. Then write back
the sum into the same location.
1 1 0 1
n n n n
ADDC (HL+d),n
n n n n C Z C H S V 5
Sign-extend the 8-bit displacement d in the instruction code and add the result to IY to form an effective address (EA). Add both the immediate n in the instruction code and the contents of the Carry flag to the contents of the memory location at the EA. Then write back the sum
into the same location.
1 1 0 1
n n n n
ADDC (SP+d),n
0 0 0 0 n n n n
Sign-extend the 8-bit displacement d in the instruction code and add the result to IX to form an effective address (EA). Add both the immediate n in the instruction code and the contents of the Carry flag to the contents of the memory location at the EA. Then write back the sum
into the same location.
1 1 0 1
n n n n
ADDC (IY+d),n
0 0 1 1 0 1 1 0
Add both the immediate n in the instruction code and the contents of the Carry flag to the contents of the memory location addressed by IY.
Then write back the sum into the same location.
1 1 0 1
n n n n
ADDC (IX+d),n
(DE) ← (DE)+n+CF
Add both the immediate n in the instruction code and the contents of the Carry flag to the contents of the memory location addressed by
IX. Then write back the sum into the same location.
1 1 1 0
ADDC (IY),n
n n n n C Z C H S V 5
Add both the immediate n in the instruction code and the contents of the Carry flag to the contents of the memory location addressed by
HL. Then write back the sum into the same location.
1 1 1 0
ADDC (IX),n
0 0 0 0 n n n n
Add both the immediate n in the instruction code and the contents of the Carry flag to the contents of the memory location addressed by
DE. Then write back the sum into the same location.
1 1 1 0
ADDC (HL),n
0 0 1 0 0 1 1 0
0 1 1 1 d d d d
n n n n
d d d d 0 1 1 0
0 0 0 0 C Z C H S V 7
(HL+d) ← (HL+d)+n+CF
Sign-extend the 8-bit displacement d in the instruction code and add the result to HL to form an effective address (EA). Add both the
immediate n in the instruction code and the contents of the Carry flag to the contents of the memory location at the EA. Then write back
the sum into the same location.
Page 32
TLCS-870/C1
Flag
Mnemonic
Instruction Code (Binary)
Cycle
Operation
J Z C H S V
1 1 1 0
0 1 1 1 0 1 1 0
0 0 0 0 n n n n
n n n n C Z C H S V 7
(HL+C) ← (HL+C)+n+CF
ADDC (HL+C),n
Sign-extend the contents of C and add the result to HL to form an effective address (EA). Add both the immediate n in the instruction code
and the contents of the Carry flag to the contents of the memory location at the EA. Then write back the sum into the same location.
ADDC (+SP),n
Add both the immediate n in the instruction code and the contents of the Carry flag to the contents of the memory location at (SP+1) and
write back the sum into the same location.
1 1 1 0
ADDC
0 1 0 0
0 1 1 0 0 1 1 0
1 1 1 1 0 1 1 0
0 0 0 0 n n n n
0 0 0 0 n n n n
n n n n C Z C H S V 6
n n n n C Z C H S V 7
SP ← SP+1:(SP) ← (SP)+n+CF
(PC+A) ← (PC+A)+n+CF
(PC+A),nNote
Sign-extend the contents of A and add the result to PC to form an effective address (EA). Add both the immediate n in the instruction code
and the contents of the Carry flag to the contents of the memory location at the EA and write back the sum into the same location.
ADDC rr,(x)
Add both the 16-bit memory word directly addressed by x and the contents of the Carry flag to the contents of 16-bit register rr. Then write
1 1 1 0
0 0 0 0 x x x x
x x x x 1 0 r r
r 0 0 0 C Z C U S V 5
rr ← rr+(x+1, x)+CF
back the sum into rr. (0x0000 ≤ x ≤ 0x00FF)
1 1 1 0
1 0 r r
ADDC rr,(vw)
0 0 0 1 w w w w
r 0 0 0
w w w w v v v v
v v v v C Z C U S V 6
rr ← rr+(vw+1, vw)+CF
Add both the 16-bit memory word directly addressed by vw and the contents of the Carry flag to the contents of 16-bit register rr. Then
write back the sum into rr. (0x0000 ≤ vw ≤ 0xFFFF)
1 1 1 0
0 0 1 0 1 0 r r
r 0 0 0
C Z C U S V 4
rr ← rr+(DE+1, DE)+CF
ADDC rr,(DE)
Add both the 16-bit memory word addressed by DE and the contents of the Carry flag to the contents of 16-bit register rr. Then write back
the sum into rr.
ADDC rr,(HL)
Add both the 16-bit memory word addressed by HL and the contents of the Carry flag to the contents of 16-bit register rr. Then write back
the sum into rr.
ADDC rr,(IX)
Add both the 16-bit memory word addressed by IX and the contents of the Carry flag to the contents of 16-bit register rr. Then write back
the sum into rr.
ADDC rr,(IY)
Add both the 16-bit memory word addressed by IY and the contents of the Carry flag to the contents of 16-bit register rr. Then write back
the sum into rr.
ADDC rr,(IX+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to IX to form an effective address (EA). Add both the 16-bit
memory word addressed by the EA and the contents of the Carry flag to the contents of 16-bit register rr. Then write back the sum into rr.
ADDC rr,(IY+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to IY to form an effective address (EA). Add both the 16-bit
memory word addressed by the EA and the contents of the Carry flag to the contents of 16-bit register rr. Then write back the sum into rr.
ADDC rr,(SP+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to SP to form an effective address (EA). Add both the 16-bit
memory word addressed by the EA and the contents of the Carry flag to the contents of 16-bit register rr. Then write back the sum into rr.
ADDC rr,(HL+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to HL to form an effective address (EA). Add both the 16-bit
memory word addressed by the EA and the contents of the Carry flag to the contents of 16-bit register rr. Then write back the sum into rr.
ADDC rr,(HL+C)
Sign-extend the contents of C and add the result to HL to form an effective address (EA). Add both the 16-bit memory word addressed by
the EA and the contents of the Carry flag to the contents of 16-bit register rr. Then write back the sum into rr.
1 1 1 0
1 1 1 0
1 1 1 0
1 1 0 1
1 1 0 1
1 1 0 1
1 1 0 1
1 1 1 0
1 1 1 0
0 0 1 1 1 0 r r
0 1 0 0 1 0 r r
0 1 0 1 1 0 r r
0 1 0 0 d d d d
0 1 0 1 d d d d
0 1 1 0 d d d d
0 1 1 1 d d d d
0 1 1 1 1 0 r r
0 1 1 0 1 0 r r
r 0 0 0
C Z C U S V 4
r 0 0 0
C Z C U S V 4
r 0 0 0
C Z C U S V 4
d d d d 1 0 r r
d d d d 1 0 r r
d d d d 1 0 r r
d d d d 1 0 r r
r 0 0 0
r 0 0 0 C Z C U S V 6
r 0 0 0 C Z C U S V 6
r 0 0 0 C Z C U S V 6
r 0 0 0 C Z C U S V 6
C Z C U S V 6
r 0 0 0
C Z C U S V 5
rr ← rr+(HL+1, HL)+CF
rr ← rr+(IX+1, IX)+CF
rr ← rr+(IY+1,IY)+CF
rr ← rr+(IX+d+1, IX+d)+CF
rr ← rr+(IY+d+1, IY+d)+CF
rr ← rr+(SP+d+1, SP+d)+CF
rr ← rr+(HL+d+1, HL+d)+CF
rr ← rr+(HL+C+1, HL+C)+CF
SP ← SP+1:rr ← rr+(SP+1,
SP)+CF
ADDC rr,(+SP)
Add both the 16-bit memory word addressed by (SP+1) and the contents of the Carry flag to the contents of 16-bit register rr. Then write
back the sum into rr.
ADDC
rr,(PC+A)Note
0 1 0 0
1 1 1 1 1 0 r r
r 0 0 0
C Z C U S V 6
rr ← rr+(PC+A+1, PC+A)+CF
Sign-extend the contents of A and add the result to PC to form an effective address (EA). Add both the 16-bit memory word addressed by
the EA and the contents of the Carry flag to the contents of 16-bit register rr. Then write back the sum into rr.
0 1 1 0
0 0 1 1 n n n n
n n n n
C Z C H S V 2
A ← A–n
SUB A,n
Subtract the immediate n in the instruction code from the contents of A and write back the difference into A.
1 1 1 0
1 g g g 0 1 1 0
0 0 1 1 n n n n
n n n n C Z C H S V 3
SUB g,n
g ← g–n
Subtract the immediate n in the instruction code from the contents of 8-bit register g and write back the difference into g.
SUB gg,mn
1 1 1 0
mmmm
1 g g g 0 1 1 0
mmmm
1 0 1 1 n n n n
n n n n C Z C U S V 4
gg ← gg–mn
Subtract the immediate mn in the instruction code from the contents of 16-bit register gg and write back the difference into gg.
RA000
Page 33
2.2 ALU Instructions
2.2 ALU Instructions
TLCS-870/C1
Flag
Mnemonic
Instruction Code (Binary)
Cycle
Operation
J Z C H S V
1 1 1 0
1 g g g 0 0 r r
r 0 1 1
C Z C H S V 2
r ← r–g
SUB r,g
Subtract the contents of 8-bit register g from that of 8-bit register r and write back the difference into r.
1 1 1 0
1 g g g 1 0 r r
r 0 1 1
C Z C U S V 3
SUB rr,gg
rr ← rr–gg
Subtract the contents of 16-bit register gg from that of 16-bit register rr and write back the difference into rr.
1 1 1 0
SUB r,(x)
0 0 0 0 x x x x
x x x x 0 0 r r
r 0 1 1 C Z C H S V 4
r ← r–(x)
Subtract the contents of the memory location directly addressed by x from that of 8-bit register r and write back the difference into r.
(0x0000 ≤ x ≤ 0x00FF)
1 1 1 0
0 0 r r
SUB r,(vw)
0 0 0 1 w w w w
r 0 1 1
w w w w v v v v
v v v v C Z C H S V 5
r ← r–(vw)
Subtract the contents of the memory location directly addressed by vw from that of 8-bit register r and write back the difference into r.
(0x0000 ≤ vw ≤ 0xFFFF)
1 1 1 0
0 0 1 0 0 0 r r
r 0 1 1
C Z C H S V 3
r ← r–(DE)
SUB r,(DE)
Subtract the contents of the memory location addressed by DE from that of 8-bit register r and write back the difference into r.
1 1 1 0
0 0 1 1 0 0 r r
r 0 1 1
C Z C H S V 3
SUB r,(HL)
r ← r–(HL)
Subtract the contents of the memory location addressed by HL from that of 8-bit register r and write back the difference into r.
1 1 1 0
0 1 0 0 0 0 r r
r 0 1 1
C Z C H S V 3
SUB r,(IX)
r ← r–(IX)
Subtract the contents of the memory location addressed by IX from that of 8-bit register r and write back the difference into r.
1 1 1 0
0 1 0 1 0 0 r r
r 0 1 1
C Z C H S V 3
r ← r–(IY)
SUB r,(IY)
Subtract the contents of the memory location addressed by IY from that of 8-bit register r and write back the difference into r.
1 1 0 1
0 1 0 0 d d d d
d d d d 0 0 r r
r 0 1 1 C Z C H S V 5
r ← r–(IX+d)
SUB r,(IX+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to IX to form an effective address (EA). Subtract the contents of the memory location at the EA from that of 8-bit register r and write back the difference into r.
SUB r,(IY+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to IY to form an effective address (EA). Subtract the contents of the memory location at the EA from that of 8-bit register r and write back the difference into r.
SUB r,(SP+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to SP to form an effective address (EA). Subtract the contents of the memory location at the EA from that of 8-bit register r and write back the difference into r.
SUB r,(HL+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to HL to form an effective address (EA). Subtract the contents of the memory location at the EA from that of 8-bit register r and write back the difference into r.
SUB r,(HL+C)
Sign-extend the contents of C and add the result to HL to form an effective address (EA). Subtract the contents of the memory location at
the EA from that of 8-bit register r and write back the difference into r.
1 1 0 1
1 1 0 1
1 1 0 1
1 1 1 0
1 1 1 0
0 1 0 1 d d d d
0 1 1 0 d d d d
0 1 1 1 d d d d
0 1 1 1 0 0 r r
0 1 1 0 0 0 r r
d d d d 0 0 r r
d d d d 0 0 r r
d d d d 0 0 r r
r 0 1 1
r 0 1 1 C Z C H S V 5
r 0 1 1 C Z C H S V 5
r 0 1 1 C Z C H S V 5
C Z C H S V 5
r 0 1 1
C Z C H S V 4
SUB r,(+SP)
r ← r–(IY+d)
r ← r–(SP+d)
r ← r–(HL+d)
r ← r–(HL)+C
SP ← SP+1:r ← r–(SP)
Subtract the contents of the memory location at (SP+1) from that of 8-bit register r and write back the difference into r.
0 1 0 0
SUB r,(PC+A)Note
r 0 1 1
C Z C H S V 5
r ← r–(PC+A)
Sign-extend the contents of A and add the result to PC to form an effective address (EA). Subtract the contents of the memory location at
the EA from that of 8-bit register r and write back the difference into r.
1 1 1 0
n n n n
SUB (x),n
1 1 1 1 0 0 r r
0 0 0 0 x x x x
n n n n
x x x x 0 1 1 0
0 0 1 1 C Z C H S V 6
(x) ← (x)–n
Subtract the immediate n in the instruction code from the contents of the memory location directly addressed by x and write back the difference into the same location. (0x0000 ≤ x ≤ 0x00FF)
1 1 1 0
0 1 1 0
SUB (vw),n
0 0 0 1 w w w w
0 0 1 1 n n n n
w w w w v v v v
n n n n
v v v v C Z C H S V 7
(vw) ← (vw)–n
Subtract the immediate n in the instruction code from the contents of the memory location directly addressed by vw and write back the difference into the same location. (0x0000 ≤ vw ≤ 0xFFFF)
1 1 1 0
0 0 1 0 0 1 1 0
0 0 1 1 n n n n
n n n n C Z C H S V 5
(DE) ← (DE)–n
SUB (DE),n
Subtract the immediate n in the instruction code from the contents of the memory location addressed by DE and write back the difference
into the same location.
SUB (HL),n
Subtract the immediate n in the instruction code from the contents of the memory location addressed by HL and write back the difference
into the same location.
SUB (IX),n
Subtract the immediate n in the instruction code from the contents of the memory location addressed by IX and write back the difference
into the same location.
1 1 1 0
1 1 1 0
RA000
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 0
0 0 1 1 n n n n
0 0 1 1 n n n n
Page 34
n n n n C Z C H S V 5
n n n n C Z C H S V 5
(HL) ← (HL)–n
(IX) ← (IX)–n
TLCS-870/C1
Flag
Mnemonic
Instruction Code (Binary)
Cycle
Operation
J Z C H S V
1 1 1 0
SUB (IY),n
0 1 0 1 0 1 1 0
0 0 1 1 n n n n
n n n n C Z C H S V 5
(IY) ← (IY)–n
Subtract the immediate n in the instruction code from the contents of the memory location addressed by IY and write back the difference
into the same location.
1 1 0 1
n n n n
0 1 0 0 d d d d
n n n n
d d d d 0 1 1 0
0 0 1 1 C Z C H S V 7
(IX+d) ← (IX+d)–n
SUB (IX+d),n
Sign-extend the 8-bit displacement d in the instruction code and add the result to IX to form an effective address (EA). Subtract the immediate n in the instruction code from the contents of the memory location at the EA and write back the difference into the same location.
1 1 0 1
n n n n
0 1 0 1 d d d d
n n n n
d d d d 0 1 1 0
0 0 1 1 C Z C H S V 7
(IY+d) ← (IY+d)–n
SUB (IY+d),n
Sign-extend the 8-bit displacement d in the instruction code and add the result to IY to form an effective address (EA). Subtract the immediate n in the instruction code from the contents of the memory location at the EA and write back the difference into the same location.
1 1 0 1
n n n n
0 1 1 0 d d d d
n n n n
d d d d 0 1 1 0
0 0 1 1 C Z C H S V 7
(SP+d) ← (SP+d)–n
SUB (SP+d),n
Sign-extend the 8-bit displacement d in the instruction code and add the result to SP to form an effective address (EA). Subtract the immediate n in the instruction code from the contents of the memory location at the EA and write back the difference into the same location.
1 1 0 1
n n n n
0 1 1 1 d d d d
n n n n
d d d d 0 1 1 0
0 0 1 1 C Z C H S V 7
(HL+d) ← (HL+d)–n
SUB (HL+d),n
Sign-extend the 8-bit displacement d in the instruction code and add the result to HL to form an effective address (EA). Subtract the immediate n in the instruction code from the contents of the memory location at the EA and write back the difference into the same location.
1 1 1 0
0 1 1 1 0 1 1 0
0 0 1 1 n n n n
n n n n C Z C H S V 7
(HL+C) ← (HL+C)–n
SUB (HL+C),n
Sign-extend the contents of C and add the result to HL to form an effective address (EA). Subtract the immediate n in the instruction code
from the contents of the memory location at the EA and write back the difference into the same location.
SUB (+SP),n
Subtract the immediate n in the instruction code from the contents of the memory location at (SP+1) and write back the difference into the
same location.
SUB (PC+A),nNote
Sign-extend the contents of A and add the result to PC to form an effective address (EA). Subtract the immediate n in the instruction code
from the contents of the memory location at the EA and write back the difference into the same location.
SUB rr,(x)
Subtract the 16-bit memory word directly addressed by x from the contents of 16-bit register rr and write back the difference into rr.
1 1 1 0
0 1 0 0
1 1 1 0
0 1 1 0 0 1 1 0
1 1 1 1 0 1 1 0
0 0 0 0 x x x x
0 0 1 1 n n n n
0 0 1 1 n n n n
x x x x 1 0 r r
n n n n C Z C H S V 6
n n n n C Z C H S V 7
r 0 1 1 C Z C U S V 5
SP ← SP+1:(SP) ← (SP)–n
(PC+A) ← (PC+A)–n
rr ← rr–(x+1, x)
(0x0000 ≤ x ≤ 0x00FF)
1 1 1 0
1 0 r r
SUB rr,(vw)
0 0 0 1 w w w w
r 0 1 1
w w w w v v v v
v v v v C Z C U S V 6
rr ← rr–(vw+1, vw)
Subtract the 16-bit memory word directly addressed by vw from the contents of 16-bit register rr and write back the difference into rr.
(0x0000 ≤ vw ≤ 0xFFFF)
1 1 1 0
0 0 1 0 1 0 r r
r 0 1 1
C Z C U S V 4
rr ← rr–(DE+1, DE)
SUB rr,(DE)
Subtract the 16-bit memory word addressed by DE from the contents of 16-bit register rr and write back the difference into rr.
1 1 1 0
0 0 1 1 1 0 r r
r 0 1 1
C Z C U S V 4
SUB rr,(HL)
rr ← rr–(HL+1, HL)
Subtract the 16-bit memory word addressed by HL from the contents of 16-bit register rr and write back the difference into rr.
1 1 1 0
0 1 0 0 1 0 r r
r 0 1 1
C Z C U S V 4
SUB rr,(IX)
rr ← rr–(IX+1, IX)
Subtract the 16-bit memory word addressed by IX from the contents of 16-bit register rr and write back the difference into rr.
1 1 1 0
0 1 0 1 1 0 r r
r 0 1 1
C Z C U S V 4
rr ← rr–(IY+1, IY)
SUB rr,(IY)
Subtract the 16-bit memory word addressed by IY from the contents of 16-bit register rr and write back the difference into rr.
1 1 0 1
0 1 0 0 d d d d
d d d d 1 0 r r
r 0 1 1 C Z C U S V 6
rr ← rr–(IX+d+1, IX+d)
SUB rr,(IX+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to IX to form an effective address (EA). Subtract the 16-bit
memory word addressed by the EA from the contents of 16-bit register rr and write back the difference into rr.
SUB rr,(IY+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to IY to form an effective address (EA). Subtract the 16-bit
memory word addressed by the EA from the contents of 16-bit register rr and write back the difference into rr.
SUB rr,(SP+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to SP to form an effective address (EA). Subtract the 16-bit
memory word addressed by the EA from the contents of 16-bit register rr and write back the difference into rr.
SUB rr,(HL+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to HL to form an effective address (EA). Subtract the 16-bit
memory word addressed by the EA from the contents of 16-bit register rr and write back the difference into rr.
SUB rr,(HL+C)
Sign-extend the contents of C and add the result to HL to form an effective address (EA). Subtract the 16-bit memory word addressed by
the EA from the contents of 16-bit register rr and write back the difference into rr.
1 1 0 1
1 1 0 1
1 1 0 1
1 1 1 0
RA000
0 1 0 1 d d d d
0 1 1 0 d d d d
0 1 1 1 d d d d
0 1 1 1 1 0 r r
d d d d 1 0 r r
d d d d 1 0 r r
d d d d 1 0 r r
r 0 1 1
r 0 1 1 C Z C U S V 6
r 0 1 1 C Z C U S V 6
r 0 1 1 C Z C U S V 6
C Z C U S V 6
Page 35
rr ← rr–(IY+d+1, IY+d)
rr ← rr–(SP+d+1, SP+d)
rr ← rr–(HL+d+1, HL+d)
rr ← rr–(HL+C+1, HL+C)
2.2 ALU Instructions
2.2 ALU Instructions
TLCS-870/C1
Flag
Mnemonic
Instruction Code (Binary)
Cycle
Operation
J Z C H S V
1 1 1 0
0 1 1 0 1 0 r r
r 0 1 1
C Z C U S V 5
SP ← SP+1:rr ← rr–(SP+1, SP)
SUB rr,(+SP)
Subtract the 16-bit memory word addressed by (SP+1) from the contents of 16-bit register rr and write back the difference into rr.
0 1 0 0
SUB rr,(PC+A)Note
C Z C U S V 6
rr ← rr–(PC+A+1, PC+A)
0 0 1 0 n n n n
n n n n
C Z C H S V 2
A ← A–n–CF
Subtract both the immediate n in the instruction code and the contents of the Carry flag from the contents of A and write back the difference into A.
1 1 1 0
SUBB g,n
r 0 1 1
Sign-extend the contents of A and add the result to PC to form an effective address (EA). Subtract the 16-bit memory word addressed by
the EA from the contents of 16-bit register rr and write back the difference into rr.
0 1 1 0
SUBB A,n
1 1 1 1 1 0 r r
1 g g g 0 1 1 0
0 0 1 0 n n n n
n n n n C Z C H S V 3
g ← g–n–CF
Subtract both the immediate n in the instruction code and the contents of the Carry flag from the contents of 8-bit register g and write back
the difference into g.
1 1 1 0
mmmm
1 g g g 0 1 1 0
mmmm
1 0 1 0 n n n n
n n n n C Z C U S V 4
gg ← gg–mn–CF
SUBB gg,mn
Subtract both the immediate mn in the instruction code and the contents of the Carry flag from the contents of 16-bit register gg and write
back the difference into gg.
1 1 1 0
1 g g g 0 0 r r
r 0 1 0
C Z C H S V 2
r ← r–g–CF
SUBB r,g
Subtract both the contents of 8-bit register g and that of the Carry flag from the contents of 8-bit register r and write back the difference into
r.
SUBB rr,gg
Subtract both the contents of 16-bit register gg and that of the Carry flag from the contents of 16-bit register rr and write back the difference
into rr.
SUBB r,(x)
Subtract both the contents of the memory location directly addressed by x and that of the Carry flag from the contents of 8-bit register r and
1 1 1 0
1 1 1 0
1 g g g 1 0 r r
0 0 0 0 x x x x
r 0 1 0
C Z C U S V 3
x x x x 0 0 r r
r 0 1 0 C Z C H S V 4
rr ← rr–gg–CF
r ← r–(x)–CF
write back the difference into r. (0x0000 ≤ x ≤ 0x00FF)
1 1 1 0
0 0 r r
SUBB r,(vw)
0 0 0 1 w w w w
r 0 1 0
w w w w v v v v
v v v v C Z C H S V 5
r ← r–(vw)–CF
Subtract both the contents of the memory location directly addressed by vw and that of the Carry flag from the contents of 8-bit register r
and write back the difference into r. (0x0000 ≤ vw ≤ 0xFFFF)
1 1 1 0
0 0 1 0 0 0 r r
r 0 1 0
C Z C H S V 3
r ← r–(DE)–CF
SUBB r,(DE)
Subtract both the contents of the memory location addressed by DE and that of the Carry flag from the contents of 8-bit register r and write
back the difference into r.
SUBB r,(HL)
Subtract both the contents of the memory location addressed by HL and that of the Carry flag from the contents of 8-bit register r and write
back the difference into r.
SUBB r,(IX)
Subtract both the contents of the memory location addressed by IX and that of the Carry flag from the contents of 8-bit register r and write
back the difference into r.
SUBB r,(IY)
Subtract both the contents of the memory location addressed by IY and that of the Carry flag from the contents of 8-bit register r and write
back the difference into r.
SUBB r,(IX+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to IX to form an effective address (EA). Subtract both the
contents of the memory location at the EA and that of the Carry flag from the contents of 8-bit register r and write back the difference into r.
SUBB r,(IY+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to IY to form an effective address (EA). Subtract both the
contents of the memory location at the EA and that of the Carry flag from the contents of 8-bit register r and write back the difference into r.
SUBB r,(SP+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to SP to form an effective address (EA). Subtract both the
contents of the memory location at the EA and that of the Carry flag from the contents of 8-bit register r and write back the difference into r.
SUBB r,(HL+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to HL to form an effective address (EA). Subtract both the
contents of the memory location at the EA and that of the Carry flag from the contents of 8-bit register r and write back the difference into r.
SUBB r,(HL+C)
Sign-extend the contents of C and add the result to HL to form an effective address (EA). Subtract both the contents of the memory location at the EA and that of the Carry flag from the contents of 8-bit register r and write back the difference into r.
SUBB r,(+SP)
Subtract both the contents of the memory location at (SP+1) and that of the Carry flag from the contents of 8-bit register r and write back
the difference into r.
1 1 1 0
1 1 1 0
1 1 1 0
1 1 0 1
1 1 0 1
1 1 0 1
1 1 0 1
1 1 1 0
1 1 1 0
RA000
0 0 1 1 0 0 r r
0 1 0 0 0 0 r r
0 1 0 1 0 0 r r
0 1 0 0 d d d d
0 1 0 1 d d d d
0 1 1 0 d d d d
0 1 1 1 d d d d
0 1 1 1 0 0 r r
0 1 1 0 0 0 r r
r 0 1 0
C Z C H S V 3
r 0 1 0
C Z C H S V 3
r 0 1 0
C Z C H S V 3
d d d d 0 0 r r
d d d d 0 0 r r
d d d d 0 0 r r
d d d d 0 0 r r
r 0 1 0
r 0 1 0 C Z C H S V 5
r 0 1 0 C Z C H S V 5
r 0 1 0 C Z C H S V 5
r 0 1 0 C Z C H S V 5
C Z C H S V 5
r 0 1 0
C Z C H S V 4
Page 36
r ← r–(HL)–CF
r ← r–(IX)–CF
r ← r–(IY)–CF
r ← r–(IX+d)–CF
r ← r–(IX+d)–CF
r ← r–(SP+d)–CF
r ← r–(HL+d)–CF
r ← r–(HL+C)–CF
SP ← SP+1:r ← r–(SP)–CF
TLCS-870/C1
Flag
Mnemonic
Instruction Code (Binary)
Cycle
Operation
J Z C H S V
0 1 0 0
1 1 1 1 0 0 r r
r 0 1 0
C Z C H S V 5
r ← r–(PC+A)–CF
SUBB r,(PC+A)Note Sign-extend the contents of A and add the result to PC to form an effective address (EA). Subtract both the contents of the memory location at the EA and that of the Carry flag from the contents of 8-bit register r and write back the difference into r.
1 1 1 0
n n n n
SUBB (x),n
0 0 0 0 x x x x
n n n n
x x x x 0 1 1 0
0 0 1 0 C Z C H S V 6
(x) ← (x)–n–CF
Subtract both the immediate n in the instruction code and the contents of the Carry flag from the contents of the memory location directly
addressed by x. Then write back the difference into the same location. (0x0000 ≤ x ≤ 0x00FF)
1 1 1 0
0 1 1 0
SUBB (vw),n
0 0 0 1 w w w w
0 0 1 0 n n n n
w w w w v v v v
n n n n
v v v v C Z C H S V 7
(vw) ← (vw)–n–CF
Subtract both the immediate n in the instruction code and the contents of the Carry flag from the contents of the memory location directly
addressed by vw. Then write back the difference into the same location. (0x0000 ≤ vw ≤ 0xFFFF)
1 1 1 0
SUBB (DE),n
0 1 0 0 0 1 1 0
0 0 1 0 n n n n
n n n n C Z C H S V 5
(IX) ← (IX)–n–CF
0 1 0 1 0 1 1 0
0 0 1 0 n n n n
n n n n C Z C H S V 5
(IY) ← (IY)–n–CF
0 1 0 0 d d d d
n n n n
d d d d 0 1 1 0
0 0 1 0 C Z C H S V 7
(IX+d) ← (IX+d)–n–CF
0 1 0 1 d d d d
n n n n
d d d d 0 1 1 0
0 0 1 0 C Z C H S V 7
(IY+d) ← (IY+d)–n–CF
0 1 1 0 d d d d
n n n n
d d d d 0 1 1 0
0 0 1 0 C Z C H S V 7
(SP+d) ← (SP+d)–n–CF
0 1 1 1 d d d d
n n n n
d d d d 0 1 1 0
0 0 1 0 C Z C H S V 7
(HL+d) ← (HL+d)–n–CF
Sign-extend the 8-bit displacement d in the instruction code and add the result to HL to form an effective address (EA). Subtract both the
immediate n in the instruction code and the contents of the Carry flag from the contents of the memory location at the EA. Then write back
the difference into the same location.
1 1 1 0
SUBB (HL+C),n
(HL) ← (HL)–n–CF
Sign-extend the 8-bit displacement d in the instruction code and add the result to SP to form an effective address (EA). Subtract both the
immediate n in the instruction code and the contents of the Carry flag from the contents of the memory location at the EA. Then write back
the difference into the same location.
1 1 0 1
n n n n
SUBB (HL+d),n
n n n n C Z C H S V 5
Sign-extend the 8-bit displacement d in the instruction code and add the result to IY to form an effective address (EA). Subtract both the
immediate n in the instruction code and the contents of the Carry flag from the contents of the memory location at the EA. Then write back
the difference into the same location.
1 1 0 1
n n n n
SUBB (SP+d),n
0 0 1 0 n n n n
Sign-extend the 8-bit displacement d in the instruction code and add the result to IX to form an effective address (EA). Subtract both the
immediate n in the instruction code and the contents of the Carry flag from the contents of the memory location at the EA. Then write back
the difference into the same location.
1 1 0 1
n n n n
SUBB (IY+d),n
0 0 1 1 0 1 1 0
Subtract both the immediate n in the instruction code and the contents of the Carry flag from the contents of the memory location
addressed by IY. Then write back the difference into the same location.
1 1 0 1
n n n n
SUBB (IX+d),n
(DE) ← (DE)–n–CF
Subtract both the immediate n in the instruction code and the contents of the Carry flag from the contents of the memory location
addressed by IX. Then write back the difference into the same location.
1 1 1 0
SUBB (IY),n
n n n n C Z C H S V 5
Subtract both the immediate n in the instruction code and the contents of the Carry flag from the contents of the memory location
addressed by HL. Then write back the difference into the same location.
1 1 1 0
SUBB (IX),n
0 0 1 0 n n n n
Subtract both the immediate n in the instruction code and the contents of the Carry flag from the contents of the memory location
addressed by DE. Then write back the difference into the same location.
1 1 1 0
SUBB (HL),n
0 0 1 0 0 1 1 0
0 1 1 1 0 1 1 0
0 0 1 0 n n n n
n n n n C Z C H S V 7
(HL+C) ← (HL+C)–n–CF
Sign-extend the contents of C and add the result to HL to form an effective address (EA). Subtract both the immediate n in the instruction
code and the contents of the Carry flag from the contents of the memory location at the EA. Then write back the difference into the same
location.
1 1 1 0
0 1 1 0 0 1 1 0
0 0 1 0 n n n n
n n n n C Z C H S V 6
SP ← SP+1:(SP) ← (SP)–n–CF
SUBB (+SP),n
Subtract both the immediate n in the instruction code and the contents of the Carry flag from the contents of the memory location at (SP+1)
and write back the difference into the same location.
SUBB
Sign-extend the contents of A and add the result to PC to form an effective address (EA). Subtract both the immediate n in the instruction
code and the contents of the Carry flag from the contents of the memory location at the EA. Then write back the difference into the same
location.
0 1 0 0
(PC+A),nNote
1 1 1 0
SUBB rr,(x)
1 1 1 1 0 1 1 0
0 0 0 0 x x x x
0 0 1 0 n n n n
x x x x 1 0 r r
r 0 1 0 C Z C U S V 5
(PC+A) ← (PC+A)–n–CF
rr ← rr–(x+1, x)–CF
Subtract both the 16-bit memory word directly addressed by x and the contents of the Carry flag from the contents of 16-bit register rr.
Then write back the difference into rr. (0x0000 ≤ x ≤ 0x00FF)
RA000
n n n n C Z C H S V 7
Page 37
2.2 ALU Instructions
2.2 ALU Instructions
TLCS-870/C1
Flag
Mnemonic
Instruction Code (Binary)
Cycle
Operation
J Z C H S V
1 1 1 0
1 0 r r
SUBB rr,(vw)
0 0 0 1 w w w w
r 0 1 0
w w w w v v v v
v v v v C Z C U S V 6
rr ← rr–(vw+1, vw)–CF
Subtract both the 16-bit memory word directly addressed by vw and the contents of the Carry flag from the contents of 16-bit register rr.
Then write back the difference into rr. (0x0000 ≤ vw ≤ 0xFFFF)
1 1 1 0
SUBB rr,(DE)
0 0 1 0 1 0 r r
r 0 1 0
C Z C U S V 4
rr ← rr–(DE+1, DE)–CF
Subtract both the 16-bit memory word directly addressed by vw and the contents of the Carry flag from the contents of 16-bit register rr.
Then write back the difference into rr. (0x0000 ≤ vw ≤ 0xFFFF)
1 1 1 0
0 0 1 1 1 0 r r
r 0 1 0
C Z C U S V 4
rr ← rr–(HL+1, HL)–CF
SUBB rr,(HL)
Subtract both the 16-bit memory word addressed by HL and the contents of the Carry flag from the contents of 16-bit register rr. Then write
back the difference into rr.
SUBB rr,(IX)
Subtract both the 16-bit memory word addressed by IX and the contents of the Carry flag from the contents of 16-bit register rr. Then write
back the difference into rr.
SUBB rr,(IY)
Subtract both the 16-bit memory word addressed by IY and the contents of the Carry flag from the contents of 16-bit register rr. Then write
back the difference into rr.
1 1 1 0
1 1 1 0
1 1 0 1
SUBB rr,(IX+d)
C Z C U S V 4
d d d d 1 0 r r
r 0 1 0 C Z C U S V 6
rr ← rr–(IY+1, IY)–CF
rr ← rr–(IX+d+1, IX+d)–CF
0 1 0 1 d d d d
d d d d 1 0 r r
r 0 1 0 C Z C U S V 6
rr ← rr–(IY+d+1, IY+d)–CF
0 1 1 0 d d d d
d d d d 1 0 r r
r 0 1 0 C Z C U S V 6
rr ← rr–(SP+d+1, SP+d)–CF
0 1 1 1 d d d d
d d d d 1 0 r r
r 0 1 0 C Z C U S V 6
rr ← rr–(HL+d+1, HL+d)–CF
Sign-extend the 8-bit displacement d in the instruction code and add the result to HL to form an effective address (EA). Subtract both the
16-bit memory word addressed by the EA and the contents of the Carry flag from the contents of 16-bit register rr. Then write back the difference into rr.
1 1 1 0
SUBB rr,(HL+C)
r 0 1 0
rr ← rr–(IX+1, IX)–CF
Sign-extend the 8-bit displacement d in the instruction code and add the result to SP to form an effective address (EA). Subtract both the
16-bit memory word addressed by the EA and the contents of the Carry flag from the contents of 16-bit register rr. Then write back the difference into rr.
1 1 0 1
SUBB rr,(HL+d)
0 1 0 0 d d d d
C Z C U S V 4
Sign-extend the 8-bit displacement d in the instruction code and add the result to IY to form an effective address (EA). Subtract both the
16-bit memory word addressed by the EA and the contents of the Carry flag from the contents of 16-bit register rr. Then write back the difference into rr.
1 1 0 1
SUBB rr,(SP+d)
0 1 0 1 1 0 r r
r 0 1 0
Sign-extend the 8-bit displacement d in the instruction code and add the result to IX to form an effective address (EA). Subtract both the
16-bit memory word addressed by the EA and the contents of the Carry flag from the contents of 16-bit register rr. Then write back the difference into rr.
1 1 0 1
SUBB rr,(IY+d)
0 1 0 0 1 0 r r
0 1 1 1 1 0 r r
r 0 1 0
C Z C U S V 6
rr ← rr–(HL+C+1, HL+C)–CF
Sign-extend the contents of C and add the result to HL to form an effective address (EA). Subtract both the 16-bit memory word addressed
by the EA and the contents of the Carry flag from the contents of 16-bit register rr. Then write back the difference into rr.
1 1 1 0
0 1 1 0 1 0 r r
r 0 1 0
C Z C U S V 5
SP ← SP+1:rr ← rr–(SP+1, SP)–
CF
SUBB rr,(+SP)
Subtract both the 16-bit memory word addressed by (SP+1) and the contents of the Carry flag from the contents of 16-bit register rr. Then
write back the difference into rr.
SUBB
rr,(PC+A)Note
0 1 0 0
1 1 1 1 1 0 r r
r 0 1 0
C Z C U S V 6
rr ← rr–(PC+A+1, PC+A)–CF
Sign-extend the contents of A and add the result to PC to form an effective address (EA). Subtract both the 16-bit memory word addressed
by the EA and the contents of the Carry flag from the contents of 16-bit register rr. Then write back the difference into rr.
0 1 1 0
0 1 0 0 n n n n
n n n n
Z Z – – – – 2
AND A,n
A ← A&n
Combine the contents of A with the immediate n in the instruction code in a bitwise logical AND operation and write back the result into A.
1 1 1 0
AND g,n
1 g g g 0 1 1 0
0 1 0 0 n n n n
n n n n Z Z – – – – 3
g ← g&n
Combine the contents of 8-bit register g with the immediate n in the instruction code in a bitwise logical AND operation and write back the
result into g.
1 1 1 0
mmmm
1 g g g 0 1 1 0
mmmm
1 1 0 0 n n n n
n n n n Z Z – – – – 4
gg ← gg&mn
AND gg,mn
Combine the contents of 16-bit register gg with the immediate mn in the instruction code in a bitwise logical AND operation and write back
the result into gg.
1 1 1 0
1 g g g 0 0 r r
r 1 0 0
Z Z – – – – 2
AND r,g
r ← r&g
Combine the contents of 8-bit register r with that of 8-bit register g in a bitwise logical AND operation and write back the result into r.
1 1 1 0
1 g g g 1 0 r r
r 1 0 0
Z Z – – – – 3
rr ← rr&gg
AND rr,gg
Combine the contents of 16-bit register rr with that of 16-bit register gg in a bitwise logical AND operation and write back the result into rr.
1 1 1 0
AND r,(x)
0 0 0 0 x x x x
x x x x 0 0 r r
r ← r&(x)
Combine the contents of 8-bit register r with that of the memory location directly addressed by x in a bitwise logical AND operation and
write back the result into r. (0x0000 ≤ x ≤ 0x00FF)
RA000
r 1 0 0 Z Z – – – – 4
Page 38
TLCS-870/C1
Flag
Mnemonic
Instruction Code (Binary)
Cycle
Operation
J Z C H S V
1 1 1 0
0 0 r r
AND r,(vw)
0 0 0 1 w w w w
r 1 0 0
w w w w v v v v
v v v v Z Z – – – –
5
r ← r&(vw)
Combine the contents of 8-bit register r with that of the memory location directly addressed by vw in a bitwise logical AND operation and
write back the result into r. (0x0000 ≤ vw ≤ 0xFFFF)
1 1 1 0
0 0 1 0 0 0 r r
r 1 0 0
Z Z – – – – 3
r ← r&(DE)
AND r,(DE)
Combine the contents of 8-bit register r with that of the memory location addressed by DE in a bitwise logical AND operation and write
back the result into r.
AND r,(HL)
Combine the contents of 8-bit register r with that of the memory location addressed by HL in a bitwise logical AND operation and write
back the result into r.
AND r,(IX)
Combine the contents of 8-bit register r with that of the memory location addressed by IX in a bitwise logical AND operation and write back
the result into r.
AND r,(IY)
Combine the contents of 8-bit register r with that of the memory location addressed by IY in a bitwise logical AND operation and write back
the result into r.
AND r,(IX+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to IX to form an effective address (EA). Combine the contents of 8-bit register r with that of the memory location at the EA in a bitwise logical AND operation and write back the result into r.
AND r,(IY+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to IY to form an effective address (EA). Combine the contents of 8-bit register r with that of the memory location at the EA in a bitwise logical AND operation and write back the result into r.
AND r,(SP+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to SP to form an effective address (EA). Combine the contents of 8-bit register r with that of the memory location at the EA in a bitwise logical AND operation and write back the result into r.
AND r,(HL+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to HL to form an effective address (EA). Combine the contents of 8-bit register r with that of the memory location at the EA in a bitwise logical AND operation and write back the result into r.
AND r,(HL+C)
Sign-extend the contents of C and add the result to HL to form an effective address (EA). Combine the contents of 8-bit register r with that
of the memory location at the EA in a bitwise logical AND operation and write back the result into r.
AND r,(+SP)
Combine the contents of 8-bit register r with that of the memory location at (SP+1) in a bitwise logical AND operation and write back the
result into r.
AND r,(PC+A)Note
Sign-extend the contents of A and add the result to PC to form an effective address (EA). Combine the contents of 8-bit register r with that
of the memory location at the EA in a bitwise logical AND operation and write back the result into r.
1 1 1 0
1 1 1 0
1 1 1 0
1 1 0 1
1 1 0 1
1 1 0 1
1 1 0 1
1 1 1 0
1 1 1 0
0 1 0 0
1 1 1 0
n n n n
0 0 1 1 0 0 r r
0 1 0 0 0 0 r r
0 1 0 1 0 0 r r
0 1 0 0 d d d d
0 1 0 1 d d d d
0 1 1 0 d d d d
0 1 1 1 d d d d
0 1 1 1 0 0 r r
0 1 1 0 0 0 r r
1 1 1 1 0 0 r r
0 0 0 0 x x x x
n n n n
r 1 0 0
Z Z – – – – 3
r 1 0 0
Z Z – – – – 3
r 1 0 0
Z Z – – – – 3
d d d d 0 0 r r
d d d d 0 0 r r
d d d d 0 0 r r
d d d d 0 0 r r
r 1 0 0
r 1 0 0 Z Z – – – – 5
r 1 0 0 Z Z – – – – 5
r 1 0 0 Z Z – – – – 5
r 1 0 0 Z Z – – – – 5
Z Z – – – – 5
r 1 0 0
Z Z – – – – 4
r 1 0 0
Z Z – – – – 5
x x x x 0 1 1 0
0 1 0 0 Z Z – – – – 6
r ← r&(HL)
r ← r&(IX)
r ← r&(IY)
r ← r&(IX+d)
r ← r&(IY+d)
r ← r&(SP+d)
r ← r&(HL+d)
r ← r&(HL+C)
SP ← SP+1:r ← r&(SP)
r ← r&(PC+A)
(x) ← (x)&n
AND (X),n
Combine the contents of the memory location directly addressed by x with the immediate n in the instruction code in a bitwise logical AND
operation. Then write back the result into the same location. (0x0000 £ x £ 0x00FF)
1 1 1 0
0 1 1 0
AND (vw),n
0 0 0 1 w w w w
0 1 0 0 n n n n
w w w w v v v v
n n n n
v v v v Z Z – – – – 7
(vw) ← (vw)&n
Combine the contents of the memory location directly addressed by vw with the immediate n in the instruction code in a bitwise logical
AND operation. Then write back the result into the same location. (0x0000 ≤ vw ≤ 0xFFFF)
1 1 1 0
0 0 1 0 0 1 1 0
0 1 0 0 n n n n
n n n n Z Z – – – – 5
(DE) ← (DE)&n
AND (DE),n
Combine the contents of the memory location addressed by DE with the immediate n in the instruction code in a bitwise logical AND operation. Then write back the result into the same location.
AND (HL),n
Combine the contents of the memory location addressed by HL with the immediate n in the instruction code in a bitwise logical AND operation. Then write back the result into the same location.
AND (IX),n
Combine the contents of the memory location addressed by IX with the immediate n in the instruction code in a bitwise logical AND operation. Then write back the result into the same location.
AND (IY),n
Combine the contents of the memory location addressed by IY with the immediate n in the instruction code in a bitwise logical AND operation. Then write back the result into the same location.
1 1 1 0
1 1 1 0
1 1 1 0
RA000
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 0
0 1 0 0 n n n n
0 1 0 0 n n n n
0 1 0 0 n n n n
Page 39
n n n n Z Z – – – – 5
n n n n Z Z – – – – 5
n n n n Z Z – – – – 5
(HL) ← (HL)&n
(IX) ← (IX)&n
(IY) ← (IY)&n
2.2 ALU Instructions
2.2 ALU Instructions
TLCS-870/C1
Flag
Mnemonic
Instruction Code (Binary)
Cycle
Operation
J Z C H S V
1 1 0 1
n n n n
AND (IX+d),n
0 1 0 0 Z Z – – – – 7
(IX+d) ← (IX+d)&n
0 1 0 1 d d d d
n n n n
d d d d 0 1 1 0
0 1 0 0 Z Z – – – – 7
(IY+d) ← (IY+d)&n
Sign-extend the 8-bit displacement d in the instruction code and add the result to IY to form an effective address (EA). Combine the contents of the memory location at the EA with the immediate n in the instruction code in a bitwise logical AND operation. Then write back the
result into the same location.
1 1 0 1
n n n n
AND (SP+d),n
d d d d 0 1 1 0
Sign-extend the 8-bit displacement d in the instruction code and add the result to IX to form an effective address (EA). Combine the contents of the memory location at the EA with the immediate n in the instruction code in a bitwise logical AND operation. Then write back the
result into the same location.
1 1 0 1
n n n n
AND (IY+d),n
0 1 0 0 d d d d
n n n n
0 1 1 0 d d d d
n n n n
d d d d 0 1 1 0
0 1 0 0 Z Z – – – – 7
(SP+d) ← (SP+d)&n
Sign-extend the 8-bit displacement d in the instruction code and add the result to SP to form an effective address (EA). Combine the contents of the memory location at the EA with the immediate n in the instruction code in a bitwise logical AND operation. Then write back the
result into the same location.
1 1 0 1
n n n n
0 1 1 1 d d d d
n n n n
d d d d 0 1 1 0
0 1 0 0 Z Z – – – – 7
(HL+d) ← (HL+d)&n
AND (HL+d),n
Sign-extend the 8-bit displacement d in the instruction code and add the result to HL to form an effective address (EA). Combine the contents of the memory location at the EA with the immediate n in the instruction code in a bitwise logical AND operation. Then write back the
result into the same location.
AND (HL+C),n
Sign-extend the contents of C and add the result to HL to form an effective address (EA). Combine the contents of the memory location at
the EA with the immediate n in the instruction code in a bitwise logical AND operation. Then write back the result into the same location.
AND (+SP),n
Combine the contents of the memory location at (SP+1) with the immediate n in the instruction code in a bitwise logical AND operation and
write back the result into the same location.
AND (PC+A),nNote
Sign-extend the contents of A and add the result to PC to form an effective address (EA). Combine the contents of the memory location at
the EA with the immediate n in the instruction code in a bitwise logical AND operation. Then write back the result into the same location.
AND rr,(x)
Combine the contents of 16-bit register rr with the 16-bit memory word directly addressed by x in a bitwise logical AND operation. Then
1 1 1 0
1 1 1 0
0 1 0 0
1 1 1 0
0 1 1 1 0 1 1 0
0 1 1 0 0 1 1 0
1 1 1 1 0 1 1 0
0 0 0 0 x x x x
0 1 0 0 n n n n
0 1 0 0 n n n n
0 1 0 0 n n n n
x x x x 1 0 r r
n n n n Z Z – – – – 7
n n n n Z Z – – – – 6
n n n n Z Z – – – – 7
r 1 0 0 Z Z – – – – 5
(HL+C) ← (HL+C)&n
SP ← SP+1:(SP) ← (SP)&n
(PC+A) ← (PC+A)&n
rr ← rr&(x)
write back the result into rr. (0x0000 ≤ x ≤ 0x00FF)
1 1 1 0
1 0 r r
AND rr,(vw)
0 0 0 1 w w w w
r 1 0 0
w w w w v v v v
v v v v Z Z – – – – 6
rr ← rr&(vw)
Combine the contents of 16-bit register rr with the 16-bit memory word directly addressed by vw in a bitwise logical AND operation. Then
write back the result into rr. (0x0000 ≤ vw ≤ 0xFFFF)
1 1 1 0
0 0 1 0 1 0 r r
r 1 0 0
Z Z – – – – 4
rr ← rr&(DE)
AND rr,(DE)
Combine the contents of 16-bit register rr with the 16-bit memory word addressed by DE in a bitwise logical AND operation. Then write
back the result into rr.
AND rr,(HL)
Combine the contents of 16-bit register rr with the 16-bit memory word addressed by HL in a bitwise logical AND operation. Then write
back the result into rr.
AND rr,(IX)
Combine the contents of 16-bit register rr with the 16-bit memory word addressed by IX in a bitwise logical AND operation. Then write back
the result into rr.
AND rr,(IY)
Combine the contents of 16-bit register rr with the 16-bit memory word addressed by IY in a bitwise logical AND operation. Then write back
the result into rr.
1 1 1 0
1 1 1 0
1 1 1 0
1 1 0 1
AND rr,(IX+d)
RA000
0 1 0 1 1 0 r r
0 1 0 0 d d d d
Z Z – – – – 4
r 1 0 0
Z Z – – – – 4
r 1 0 0
Z Z – – – – 4
d d d d 1 0 r r
r 1 0 0 Z Z – – – – 6
rr ← rr&(HL)
rr ← rr&(IX)
rr ← rr&(IY)
rr ← rr&(IX+d)
0 1 0 1 d d d d
d d d d 1 0 r r
r 1 0 0 Z Z – – – – 6
rr ← rr&(IY+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to IY to form an effective address (EA). Combine the contents of 16-bit register rr with the 16-bit memory word addressed by the EA in a bitwise logical AND operation. Then write back the result
into rr.
1 1 0 1
AND rr,(SP+d)
0 1 0 0 1 0 r r
r 1 0 0
Sign-extend the 8-bit displacement d in the instruction code and add the result to IX to form an effective address (EA). Combine the contents of 16-bit register rr with the 16-bit memory word addressed by the EA in a bitwise logical AND operation. Then write back the result
into rr.
1 1 0 1
AND rr,(IY+d)
0 0 1 1 1 0 r r
0 1 1 0 d d d d
d d d d 1 0 r r
r 1 0 0 Z Z – – – – 6
rr ← rr&(SP+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to SP to form an effective address (EA). Combine the contents of 16-bit register rr with the 16-bit memory word addressed by the EA in a bitwise logical AND operation. Then write back the result
into rr.
Page 40
TLCS-870/C1
Flag
Mnemonic
Instruction Code (Binary)
Cycle
Operation
J Z C H S V
1 1 0 1
AND rr,(HL+d)
1 1 1 0
AND rr,(HL+C)
r 1 0 0 Z Z – – – – 6
rr ← rr&(HL+d)
0 1 1 1 1 0 r r
r 1 0 0
Z Z – – – – 6
rr ← rr&(HL+C)
0 1 1 0 1 0 r r
r 1 0 0
Z Z – – – – 5
SP ← SP+1:rr ← rr&(SP)
Combine the contents of 16-bit register rr with the 16-bit memory word addressed by (SP+1) in a bitwise logical AND operation. Then write
back the result into rr.
0 1 0 0
AND rr,(PC+A)Note
d d d d 1 0 r r
Sign-extend the contents of C and add the result to HL to form an effective address (EA). Combine the contents of 16-bit register rr with
the 16-bit memory word addressed by the EA in a bitwise logical AND operation. Then write back the result into rr.
1 1 1 0
AND rr,(+SP)
0 1 1 1 d d d d
Sign-extend the 8-bit displacement d in the instruction code and add the result to HL to form an effective address (EA). Combine the contents of 16-bit register rr with the 16-bit memory word addressed by the EA in a bitwise logical AND operation. Then write back the result
into rr.
1 1 1 1 1 0 r r
r 1 0 0
Z Z – – – – 6
rr ← rr&(PC+A)
Sign-extend the contents of A and add the result to PC to form an effective address (EA). Combine the contents of 16-bit register rr with
the 16-bit memory word addressed by the EA in a bitwise logical AND operation. Then write back the result into rr.
0 1 1 0
0 1 1 0 n n n n
n n n n
Z Z – – – – 2
A ← A⏐n
OR A,n
Combine the contents of A with the immediate n in the instruction code in a bitwise logical OR operation and write back the result into A.
1 1 1 0
OR g,n
1 g g g 0 1 1 0
0 1 1 0 n n n n
n n n n Z Z – – – – 3
g ← g⏐n
Combine the contents of 8-bit register g with the immediate n in the instruction code in a bitwise logical OR operation and write back the
result into g.
1 1 1 0
mmmm
1 g g g 0 1 1 0
mmmm
1 1 1 0 n n n n
n n n n Z Z – – – – 4
gg ← gg⏐mn
OR gg,mn
Combine the contents of 16-bit register gg with the immediate mn in the instruction code in a bitwise logical OR operation and write back
the result into gg.
1 1 1 0
1 g g g 0 0 r r
r 1 1 0
Z Z – – – – 2
r ← r⏐g
OR r,g
Combine the contents of 8-bit register r with that of 8-bit register g in a bitwise logical OR operation and write back the result into r.
1 1 1 0
1 g g g 1 0 r r
r 1 1 0
Z Z – – – – 3
OR rr,gg
rr ← rr⏐gg
Combine the contents of 16-bit register rr with that of 16-bit register gg in a bitwise logical OR operation and write back the result into rr.
1 1 1 0
OR r,(x)
0 0 0 0 x x x x
x x x x 0 0 r r
r 1 1 0 Z Z – – – – 4
r ← r⏐(x)
Combine the contents of 8-bit register r with that of the memory location directly addressed by x in a bitwise logical OR operation and write
back the result into r. (0x0000 ≤ x ≤ 0x00FF)
1 1 1 0
0 0 r r
OR r,(vw)
0 0 0 1 w w w w
r 1 1 0
w w w w v v v v
v v v v Z Z – – – – 5
r ← r⏐(vw)
Combine the contents of 8-bit register r with that of the memory location directly addressed by vw in a bitwise logical OR operation and
write back the result into r. (0x0000 ≤ vw ≤ 0xFFFF)
1 1 1 0
OR r,(DE)
RA000
r ← r⏐(HL)
0 1 0 0 0 0 r r
r 1 1 0
Z Z – – – – 3
r ← r⏐(IX)
0 1 0 1 0 0 r r
r 1 1 0
Z Z – – – – 3
r ← r⏐(IY)
0 1 0 0 d d d d
d d d d 0 0 r r
r 1 1 0 Z Z – – – – 5
r ← r⏐(IX+d)
0 1 0 1 d d d d
d d d d 0 0 r r
r 1 1 0 Z Z – – – – 5
r ← r⏐(IY+d)
0 1 1 0 d d d d
d d d d 0 0 r r
r 1 1 0 Z Z – – – – 5
r ← r⏐(SP+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to SP to form an effective address (EA). Combine the contents of 8-bit register r with that of the memory location at the EA in a bitwise logical OR operation and write back the result into r.
1 1 0 1
OR r,(HL+d)
Z Z – – – – 3
Sign-extend the 8-bit displacement d in the instruction code and add the result to IY to form an effective address (EA). Combine the contents of 8-bit register r with that of the memory location at the EA in a bitwise logical OR operation and write back the result into r.
1 1 0 1
OR r,(SP+d)
r 1 1 0
Sign-extend the 8-bit displacement d in the instruction code and add the result to IX to form an effective address (EA). Combine the contents of 8-bit register r with that of the memory location at the EA in a bitwise logical OR operation and write back the result into r.
1 1 0 1
OR r,(IY+d)
0 0 1 1 0 0 r r
Combine the contents of 8-bit register r with that of the memory location addressed by IY in a bitwise logical OR operation and write back
the result into r.
1 1 0 1
OR r,(IX+d)
r ← r⏐(DE)
Combine the contents of 8-bit register r with that of the memory location addressed by IX in a bitwise logical OR operation and write back
the result into r.
1 1 1 0
OR r,(IY)
Z Z – – – – 3
Combine the contents of 8-bit register r with that of the memory location addressed by HL in a bitwise logical OR operation and write back
the result into r.
1 1 1 0
OR r,(IX)
r 1 1 0
Combine the contents of 8-bit register r with that of the memory location addressed by DE in a bitwise logical OR operation and write back
the result into r.
1 1 1 0
OR r,(HL)
0 0 1 0 0 0 r r
0 1 1 1 d d d d
d d d d 0 0 r r
r 1 1 0 Z Z – – – – 5
r ← r⏐(HL+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to HL to form an effective address (EA). Combine the contents of 8-bit register r with that of the memory location at the EA in a bitwise logical OR operation and write back the result into r.
Page 41
2.2 ALU Instructions
2.2 ALU Instructions
TLCS-870/C1
Flag
Mnemonic
Instruction Code (Binary)
Cycle
Operation
J Z C H S V
1 1 1 0
0 1 1 1 0 0 r r
r 1 1 0
Z Z – – – – 5
r ← r⏐(HL+C)
OR r,(HL+C)
Sign-extend the contents of C and add the result to HL to form an effective address (EA). Combine the contents of 8-bit register r with that
of the memory location at the EA in a bitwise logical OR operation and write back the result into r.
OR r,(+SP)
Combine the contents of 8-bit register r with that of the memory location at (SP+1) in a bitwise logical OR operation and write back the
result into r.
OR r,(PC+A)Note
Sign-extend the contents of A and add the result to PC to form an effective address (EA). Combine the contents of 8-bit register r with that
of the memory location at the EA in a bitwise logical OR operation and write back the result into r.
1 1 1 0
0 1 0 0
1 1 1 0
n n n n
OR (x),n
0 1 1 0 0 0 r r
1 1 1 1 0 0 r r
0 0 0 0 x x x x
n n n n
r 1 1 0
Z Z – – – – 4
r 1 1 0
Z Z – – – – 5
x x x x 0 1 1 0
0 1 1 0 Z Z – – – – 6
SP ← SP+1:r ← r⏐(SP)
r ← r⏐(PC+A)
(x) ← (x)⏐n
Combine the contents of the memory location directly addressed by x with the immediate n in the instruction code in a bitwise logical OR
operation. Then write back the result into the same location. (0x0000 ≤ x ≤ 0x00FF)
1 1 1 0
0 1 1 0
OR (vw),n
0 0 0 1 w w w w
0 1 1 0 n n n n
w w w w v v v v
n n n n
v v v v Z Z – – – – 7
(vw) ← (vw)⏐n
Combine the contents of the memory location directly addressed by vw with the immediate n in the instruction code in a bitwise logical OR
operation. Then write back the result into the same location. (0x0000 ≤ vw ≤ 0xFFFF)
1 1 1 0
OR (DE),n
1 1 1 0
n n n n Z Z – – – – 5
(DE) ← (DE)⏐n
0 0 1 1 0 1 1 0
0 1 1 0 n n n n
n n n n Z Z – – – – 5
(HL) ← (HL)⏐n
Combine the contents of the memory location addressed by HL with the immediate n in the instruction code in a bitwise logical OR operation. Then write back the result into the same location.
1 1 1 0
OR (IX),n
0 1 0 0 0 1 1 0
0 1 1 0 n n n n
n n n n Z Z – – – – 5
(IX) ← (IX)⏐n
Combine the contents of the memory location addressed by IX with the immediate n in the instruction code in a bitwise logical OR operation. Then write back the result into the same location.
1 1 1 0
OR (IY),n
0 1 0 1 0 1 1 0
0 1 1 0 n n n n
n n n n Z Z – – – – 5
(IY) ← (IY)⏐n
Combine the contents of the memory location addressed by IY with the immediate n in the instruction code in a bitwise logical OR operation. Then write back the result into the same location.
1 1 0 1
n n n n
OR (IX+d),n
0 1 0 0 d d d d
n n n n
d d d d 0 1 1 0
0 1 1 0 Z Z – – – – 7
(IX+d) ← (IX+d)⏐n
Sign-extend the 8-bit displacement d in the instruction code and add the result to IX to form an effective address (EA). Combine the contents of the memory location at the EA with the immediate n in the instruction code in a bitwise logical OR operation. Then write back the
result into the same location.
1 1 0 1
n n n n
OR (IY+d),n
0 1 0 1 d d d d
n n n n
d d d d 0 1 1 0
0 1 1 0 Z Z – – – – 7
(IY+d) ← (IY+d)⏐n
Sign-extend the 8-bit displacement d in the instruction code and add the result to IY to form an effective address (EA). Combine the contents of the memory location at the EA with the immediate n in the instruction code in a bitwise logical OR operation. Then write back the
result into the same location.
1 1 0 1
n n n n
OR (SP+d),n
0 1 1 0 d d d d
n n n n
d d d d 0 1 1 0
0 1 1 0 Z Z – – – – 7
(SP+d) ← (SP+d)⏐n
Sign-extend the 8-bit displacement d in the instruction code and add the result to SP to form an effective address (EA). Combine the contents of the memory location at the EA with the immediate n in the instruction code in a bitwise logical OR operation. Then write back the
result into the same location.
1 1 0 1
n n n n
OR (HL+d),n
0 1 1 1 d d d d
n n n n
d d d d 0 1 1 0
0 1 1 0 Z Z – – – – 7
(HL+d) ← (HL+d)⏐n
Sign-extend the 8-bit displacement d in the instruction code and add the result to HL to form an effective address (EA). Combine the contents of the memory location at the EA with the immediate n in the instruction code in a bitwise logical OR operation. Then write back the
result into the same location.
1 1 1 0
OR (HL+C),n
0 1 1 1 0 1 1 0
0 1 1 0 n n n n
n n n n Z Z – – – – 7
(HL+C) ← (HL+C)⏐n
Sign-extend the contents of C and add the result to HL to form an effective address (EA). Combine the contents of the memory location at
the EA with the immediate n in the instruction code in a bitwise logical OR operation. Then write back the result into the same location.
1 1 1 0
OR (+SP),n
0 1 1 0 0 1 1 0
0 1 1 0 n n n n
n n n n Z Z – – – – 6
SP ← SP+1:(SP) ← (SP)⏐n
Combine the contents of the memory location at (SP+1) with the immediate n in the instruction code in a bitwise logical OR operation and
write back the result into the same location.
0 1 0 0
RA000
0 1 1 0 n n n n
Combine the contents of the memory location addressed by DE with the immediate n in the instruction code in a bitwise logical OR operation. Then write back the result into the same location.
OR (HL),n
OR (PC+A),n
0 0 1 0 0 1 1 0
Note
1 1 1 1 0 1 1 0
0 1 1 0 n n n n
n n n n Z Z – – – – 7
(PC+A) ← (PC+A)⏐n
Sign-extend the contents of A and add the result to PC to form an effective address (EA). Combine the contents of the memory location at
the EA with the immediate n in the instruction code in a bitwise logical OR operation. Then write back the result into the same location.
Page 42
TLCS-870/C1
Flag
Mnemonic
Instruction Code (Binary)
Cycle
Operation
J Z C H S V
1 1 1 0
OR rr,(x)
0 0 0 0 x x x x
x x x x 1 0 r r
r 1 1 0 Z Z – – – – 5
rr ← rr⏐(x)
Combine the contents of 16-bit register rr with the 16-bit memory word directly addressed by x in a bitwise logical OR operation. Then write
back the result into rr. (0x0000 ≤ x ≤ 0x00FF)
1 1 1 0
1 0 r r
OR rr,(vw)
0 0 0 1 w w w w
r 1 1 0
w w w w v v v v
v v v v Z Z – – – – 6
rr ← rr⏐(vw)
Combine the contents of 16-bit register rr with the 16-bit memory word directly addressed by vw in a bitwise logical OR operation. Then
write back the result into rr. (0x0000 ≤ vw ≤ 0xFFFF)
1 1 1 0
0 0 1 0 1 0 r r
r 1 1 0
Z Z – – – – 4
rr ← rr⏐(DE)
OR rr,(DE)
Combine the contents of 16-bit register rr with the 16-bit memory word addressed by DE in a bitwise logical OR operation. Then write back
the result into rr.
OR rr,(HL)
Combine the contents of 16-bit register rr with the 16-bit memory word addressed by HL in a bitwise logical OR operation. Then write back
the result into rr.
OR rr,(IX)
Combine the contents of 16-bit register rr with the 16-bit memory word addressed by IX in a bitwise logical OR operation. Then write back
the result into rr.
OR rr,(IY)
Combine the contents of 16-bit register rr with the 16-bit memory word addressed by IY in a bitwise logical OR operation. Then write back
the result into rr.
1 1 1 0
1 1 1 0
1 1 1 0
1 1 0 1
OR rr,(IX+d)
0 1 0 0 d d d d
r 1 1 0
Z Z – – – – 4
r 1 1 0
Z Z – – – – 4
d d d d 1 0 r r
r 1 1 0 Z Z – – – – 6
rr ← rr⏐(HL)
rr ← rr⏐(IX)
rr ← rr⏐(IY)
rr ← rr⏐(IX+d)
0 1 0 1 d d d d
d d d d 1 0 r r
r 1 1 0 Z Z – – – – 6
rr ← rr⏐(IY+d)
0 1 1 0 d d d d
d d d d 1 0 r r
r 1 1 0 Z Z – – – – 6
rr ← rr⏐(SP+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to SP to form an effective address (EA). Combine the contents of 16-bit register rr with the 16-bit memory word addressed by the EA in a bitwise logical OR operation. Then write back the result
into rr.
1 1 0 1
OR rr,(HL+d)
0 1 0 1 1 0 r r
Z Z – – – – 4
Sign-extend the 8-bit displacement d in the instruction code and add the result to IY to form an effective address (EA). Combine the contents of 16-bit register rr with the 16-bit memory word addressed by the EA in a bitwise logical OR operation. Then write back the result
into rr.
1 1 0 1
OR rr,(SP+d)
0 1 0 0 1 0 r r
r 1 1 0
Sign-extend the 8-bit displacement d in the instruction code and add the result to IX to form an effective address (EA). Combine the contents of 16-bit register rr with the 16-bit memory word addressed by the EA in a bitwise logical OR operation. Then write back the result
into rr.
1 1 0 1
OR rr,(IY+d)
0 0 1 1 1 0 r r
0 1 1 1 d d d d
d d d d 1 0 r r
r 1 1 0 Z Z – – – – 6
rr ← rr⏐(HL+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to HL to form an effective address (EA). Combine the contents of 16-bit register rr with the 16-bit memory word addressed by the EA in a bitwise logical OR operation. Then write back the result
into rr.
1 1 1 0
0 1 1 1 1 0 r r
r 1 1 0
Z Z – – – – 6
rr ← rr⏐(HL+C)
OR rr,(HL+C)
Sign-extend the contents of C and add the result to HL to form an effective address (EA). Combine the contents of 16-bit register rr with
the 16-bit memory word addressed by the EA in a bitwise logical OR operation. Then write back the result into rr.
OR rr,(+SP)
Combine the contents of 16-bit register rr with the 16-bit memory word addressed by (SP+1) in a bitwise logical OR operation. Then write
back the result into rr.
OR rr,(PC+A)Note
Sign-extend the contents of A and add the result to PC to form an effective address (EA). Combine the contents of 16-bit register rr with
the 16-bit memory word addressed by the EA in a bitwise logical OR operation. Then write back the result into rr.
XOR A,n
Combine the contents of A with the immediate n in the instruction code in a bitwise logical exclusive-OR operation and write back the
result into A. This instruction replaces the contents of A with its 1’s complement when n = 0xFF.
Example: Assume A contains 0x69. Then, the instruction “XOR A, 0xFF” replaces the contents of A with 0x96 and clears ZF to 0.
1 1 1 0
0 1 0 0
0 1 1 0
1 1 1 0
XOR g,n
0 1 1 0 1 0 r r
1 1 1 1 1 0 r r
0 1 0 1 n n n n
1 g g g 0 1 1 0
r 1 1 0
Z Z – – – – 5
r 1 1 0
Z Z – – – – 6
n n n n
Z Z – – – – 2
0 1 0 1 n n n n
n n n n Z Z – – – – 3
SP ← SP+1:rr ← rr⏐(SP)
rr ← rr⏐(PC+A)
A ←A^n
g ←g^n
Combine the contents of 8-bit register g with the immediate n in the instruction code in a bitwise logical exclusive-OR operation and write
back the result into g. This instruction replaces the contents of g with its 1’s complement when n = 0xFF.
1 1 1 0
mmmm
1 g g g 0 1 1 0
mmmm
1 1 0 1 n n n n
n n n n Z Z – – – – 4
gg ← gg
^
mn
XOR gg,mn
Combine the contents of 16-bit register gg with the immediate mn in the instruction code in a bitwise logical exclusive-OR operation and
write back the result into gg. This instruction replaces the contents of gg with its 1’s complement when mn = 0xFFFF.
1 1 1 0
XOR r,g
RA000
1 g g g 0 0 r r
r 1 0 1
Z Z – – – – 2
r ←r^g
Combine the contents of 8-bit register r with that of 8-bit register g in a bitwise logical exclusive-OR operation and write back the result into
r.
Page 43
2.2 ALU Instructions
2.2 ALU Instructions
TLCS-870/C1
Flag
Mnemonic
Instruction Code (Binary)
Cycle
Operation
J Z C H S V
1 1 1 0
XOR rr,gg
1 g g g 1 0 r r
r 1 0 1
Z Z – – – – 3
rr ←rr^gg
Combine the contents of 16-bit register rr with that of 16-bit register gg in a bitwise logical exclusive-OR operation and write back the result
into rr.
1 1 1 0
0 0 0 0 x x x x
x x x x 0 0 r r
r 1 0 1 Z Z – – – – 4
XOR r,(x)
r ←r
^
(x)
Combine the contents of 8-bit register r with that of the memory location directly addressed by x in a bitwise logical exclusive-OR operation
and write back the result into r. (0x0000 ≤ x ≤ 0x00FF)
1 1 1 0
0 0 r r
XOR r,(vw)
0 0 0 1 w w w w
r 1 0 1
w w w w v v v v
v v v v Z Z – – – – 5
r ← r^(vw)
Combine the contents of 8-bit register r with that of the memory location directly addressed by vw in a bitwise logical exclusive-OR operation and write back the result into r. (0x0000 ≤ vw ≤ 0xFFFF)
1 1 1 0
0 0 1 0 0 0 r r
r 1 0 1
Z Z – – – – 3
XOR r,(DE)
r ←r
^
(DE)
Combine the contents of 8-bit register r with that of the memory location addressed by DE in a bitwise logical exclusive-OR operation and
write back the result into r.
1 1 1 0
XOR r,(HL)
0 0 1 1 0 0 r r
r 1 0 1
Z Z – – – – 3
r ←r^(HL)
Combine the contents of 8-bit register r with that of the memory location addressed by HL in a bitwise logical exclusive-OR operation and
write back the result into r.
1 1 1 0
0 1 0 0 0 0 r r
r 1 0 1
Z Z – – – – 3
XOR r,(IX)
r ←r
^
(IX)
Combine the contents of 8-bit register r with that of the memory location addressed by IX in a bitwise logical exclusive-OR operation and
write back the result into r.
1 1 1 0
XOR r,(IY)
1 1 0 1
XOR r,(IX+d)
0 1 0 1 0 0 r r
r 1 0 1
Z Z – – – – 3
r ←r^(IY)
Combine the contents of 8-bit register r with that of the memory location addressed by IY in a bitwise logical exclusive-OR operation and
write back the result into r.
0 1 0 0 d d d d
d d d d 0 0 r r
r 1 0 1 Z Z – – – – 5
r ←r^(IX+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to IX to form an effective address (EA). Combine the contents of 8-bit register r with that of the memory location at the EA in a bitwise logical exclusive-OR operation and write back the result into
r.
1 1 0 1
0 1 0 1 d d d d
d d d d 0 0 r r
r 1 0 1 Z Z – – – – 5
r ←r
^
(IY+d)
XOR r,(IY+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to IY to form an effective address (EA). Combine the contents of 8-bit register r with that of the memory location at the EA in a bitwise logical exclusive-OR operation and write back the result into
r.
1 1 0 1
0 1 1 0 d d d d
d d d d 0 0 r r
r 1 0 1 Z Z – – – – 5
r ←r
^
(SP+d)
XOR r,(SP+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to SP to form an effective address (EA). Combine the contents of 8-bit register r with that of the memory location at the EA in a bitwise logical exclusive-OR operation and write back the result into
r.
1 1 0 1
XOR r,(HL+d)
0 1 1 1 d d d d
d d d d 0 0 r r
r 1 0 1 Z Z – – – – 5
r ←r^(HL+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to HL to form an effective address (EA). Combine the contents of 8-bit register r with that of the memory location at the EA in a bitwise logical exclusive-OR operation and write back the result into
r.
1 1 1 0
0 1 1 1 0 0 r r
r 1 0 1
Z Z – – – – 5
XOR r,(HL+C)
r ←r
^
(HL+C)
Sign-extend the contents of C and add the result to HL to form an effective address (EA). Combine the contents of 8-bit register r with that
of the memory location at the EA in a bitwise logical exclusive-OR operation and write back the result into r.
1 1 1 0
XOR r,(+SP)
0 1 1 0 0 0 r r
r 1 0 1
Z Z – – – – 4
SP ← SP+1:r ← r^(SP)
Combine the contents of 8-bit register r with that of the memory location at (SP+1) in a bitwise logical exclusive-OR operation and write
back the result into r.
0 1 0 0
1 1 1 1 0 0 r r
r 1 0 1
Z Z – – – – 5
XOR r,(PC+A)Note
r ←r
^
(PC+A)
Sign-extend the contents of A and add the result to PC to form an effective address (EA). Combine the contents of 8-bit register r with that
of the memory location at the EA in a bitwise logical exclusive-OR operation and write back the result into r.
RA000
Page 44
TLCS-870/C1
Flag
Mnemonic
Instruction Code (Binary)
Cycle
Operation
J Z C H S V
1 1 1 0
n n n n
XOR (x),n
0 0 0 0 x x x x
n n n n
x x x x 0 1 1 0
0 1 0 1 Z Z – – – – 6
(x) ← (x)^n
Combine the contents of the memory location directly addressed by x with the immediate n in the instruction code in a bitwise logical
exclusive-OR operation. Then write back the result into the same location. (0x0000 ≤ x ≤ 0x00FF)
1 1 1 0
0 1 1 0
0 0 0 1 w w w w
0 1 0 1 n n n n
w w w w v v v v
n n n n
v v v v Z Z – – – – 7
(vw) ← (vw)
^
n
XOR (vw),n
Combine the contents of the memory location directly addressed by vw with the immediate n in the instruction code in a bitwise logical
exclusive-OR operation. Then write back the result into the same location. (0x0000 ≤ vw ≤ 0xFFFF)
1 1 1 0
XOR (DE),n
0 1 0 1 n n n n
n n n n Z Z – – – – 5
(DE) ← (DE)^n
Combine the contents of the memory location addressed by DE with the immediate n in the instruction code in a bitwise logical exclusiveOR operation. Then write back the result into the same location.
1 1 1 0
XOR (HL),n
0 0 1 0 0 1 1 0
0 0 1 1 0 1 1 0
0 1 0 1 n n n n
n n n n Z Z – – – – 5
(HL) ← (HL)^n
Combine the contents of the memory location addressed by HL with the immediate n in the instruction code in a bitwise logical exclusiveOR operation. Then write back the result into the same location.
1 1 1 0
0 1 0 0 0 1 1 0
0 1 0 1 n n n n
n n n n Z Z – – – – 5
XOR (IX),n
(IX) ← (IX)
^
n
Combine the contents of the memory location addressed by IX with the immediate n in the instruction code in a bitwise logical exclusiveOR operation. Then write back the result into the same location.
1 1 1 0
XOR (IY),n
0 1 0 1 0 1 1 0
0 1 0 1 n n n n
n n n n Z Z – – – – 5
(IY) ← (IY)^n
Combine the contents of the memory location addressed by IY with the immediate n in the instruction code in a bitwise logical exclusiveOR operation. Then write back the result into the same location.
1 1 0 1
n n n n
0 1 0 0 d d d d
n n n n
d d d d 0 1 1 0
0 1 0 1 Z Z – – – – 7
(IX+d) ← (IX+d)
^
n
XOR (IX+d),n
Sign-extend the 8-bit displacement d in the instruction code and add the result to IX to form an effective address (EA). Combine the contents of the memory location at the EA with the immediate n in the instruction code in a bitwise logical exclusive-OR operation. Then write
back the result into the same location.
1 1 0 1
n n n n
0 1 0 1 d d d d
n n n n
d d d d 0 1 1 0
0 1 0 1 Z Z – – – – 7
(IY+d) ← (IY+d)
^
n
XOR (IY+d),n
Sign-extend the 8-bit displacement d in the instruction code and add the result to IY to form an effective address (EA). Combine the contents of the memory location at the EA with the immediate n in the instruction code in a bitwise logical exclusive-OR operation. Then write
back the result into the same location.
1 1 0 1
n n n n
XOR (SP+d),n
0 1 0 1 Z Z – – – – 7
(SP+d) ← (SP+d)^n
0 1 1 1 d d d d
n n n n
d d d d 0 1 1 0
0 1 0 1 Z Z – – – – 7
(HL+d) ← (HL+d)^n
Sign-extend the 8-bit displacement d in the instruction code and add the result to HL to form an effective address (EA). Combine the contents of the memory location at the EA with the immediate n in the instruction code in a bitwise logical exclusive-OR operation. Then write
back the result into the same location.
1 1 1 0
XOR (HL+C),n
d d d d 0 1 1 0
Sign-extend the 8-bit displacement d in the instruction code and add the result to SP to form an effective address (EA). Combine the contents of the memory location at the EA with the immediate n in the instruction code in a bitwise logical exclusive-OR operation. Then write
back the result into the same location.
1 1 0 1
n n n n
XOR (HL+d),n
0 1 1 0 d d d d
n n n n
0 1 1 1 0 1 1 0
0 1 0 1 n n n n
n n n n Z Z – – – – 7
(HL+C) ← (HL+C)^n
Sign-extend the contents of C and add the result to HL to form an effective address (EA). Combine the contents of the memory location at
the EA with the immediate n in the instruction code in a bitwise logical exclusive-OR operation. Then write back the result into the same
location.
1 1 1 0
0 1 1 0 0 1 1 0
0 1 0 1 n n n n
n n n n Z Z – – – – 6
XOR (+SP),n
SP ← SP+1:(SP) ← (SP)
^
n
Combine the contents of the memory location at (SP+1) with the immediate n in the instruction code in a bitwise logical exclusive-OR operation and write back the result into the same location.
0 1 0 0
XOR (PC+A),nNote
RA000
1 1 1 1 0 1 1 0
0 1 0 1 n n n n
n n n n Z Z – – – – 7
(PC+A) ← (PC+A)^n
Sign-extend the contents of A and add the result to PC to form an effective address (EA). Combine the contents of the memory location at
the EA with the immediate n in the instruction code in a bitwise logical exclusive-OR operation. Then write back the result into the same
location.
Page 45
2.2 ALU Instructions
2.2 ALU Instructions
TLCS-870/C1
Flag
Mnemonic
Instruction Code (Binary)
Cycle
Operation
J Z C H S V
1 1 1 0
XOR rr,(x)
0 0 0 0 x x x x
x x x x 1 0 r r
r 1 0 1 Z Z – – – – 5
rr ← rr^(x)
Combine the contents of 16-bit register rr with the 16-bit memory word directly addressed by x in a bitwise logical exclusive-OR operation.
Then write back the result into rr. (0x0000 ≤ x ≤ 0x00FF)
1 1 1 0
1 0 r r
0 0 0 1 w w w w
r 1 0 1
w w w w v v v v
v v v v Z Z – – – – 6
rr ← rr
^
(vw)
XOR rr,(vw)
Combine the contents of 16-bit register rr with the 16-bit memory word directly addressed by vw in a bitwise logical exclusive-OR operation. Then write back the result into rr. (0x0000 ≤ vw ≤ 0xFFFF)
1 1 1 0
0 0 1 0 1 0 r r
r 1 0 1
Z Z – – – – 4
XOR rr,(DE)
rr ← rr
^
(DE)
Combine the contents of 16-bit register rr with the 16-bit memory word addressed by DE in a bitwise logical exclusive-OR operation. Then
write back the result into rr.
1 1 1 0
0 0 1 1 1 0 r r
r 1 0 1
Z Z – – – – 4
rr ← rr^(HL)
XOR rr,(HL)
Combine the contents of 16-bit register rr with the 16-bit memory word addressed by HL in a bitwise logical exclusive-OR operation. Then
write back the result into rr.
XOR rr,(IX)
Combine the contents of 16-bit register rr with the 16-bit memory word addressed by IX in a bitwise logical exclusive-OR operation. Then
write back the result into rr.
XOR rr,(IY)
Combine the contents of 16-bit register rr with the 16-bit memory word addressed by IY in a bitwise logical exclusive-OR operation. Then
write back the result into rr.
1 1 1 0
1 1 1 0
1 1 0 1
XOR rr,(IX+d)
0 1 0 1 1 0 r r
0 1 0 0 d d d d
r 1 0 1
Z Z – – – – 4
r 1 0 1
Z Z – – – – 4
d d d d 1 0 r r
r 1 0 1 Z Z – – – – 6
rr ← rr^(IX)
rr ← rr^(IY)
rr ← rr^(IX+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to IX to form an effective address (EA). Combine the contents of 16-bit register rr with the 16-bit memory word addressed by the EA in a bitwise logical exclusive-OR operation. Then write back the
result into rr.
1 1 0 1
XOR rr,(IY+d)
0 1 0 0 1 0 r r
0 1 0 1 d d d d
d d d d 1 0 r r
r 1 0 1 Z Z – – – – 6
rr ← rr^(IY+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to IY to form an effective address (EA). Combine the contents of 16-bit register rr with the 16-bit memory word addressed by the EA in a bitwise logical exclusive-OR operation. Then write back the
result into rr.
1 1 0 1
0 1 1 0 d d d d
d d d d 1 0 r r
r 1 0 1 Z Z – – – – 6
rr ← rr
^
(SP+d)
XOR rr,(SP+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to SP to form an effective address (EA). Combine the contents of 16-bit register rr with the 16-bit memory word addressed by the EA in a bitwise logical exclusive-OR operation. Then write back the
result into rr.
1 1 0 1
XOR rr,(HL+d)
0 1 1 1 d d d d
d d d d 1 0 r r
r 1 0 1 Z Z – – – – 6
rr ← rr^(HL+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to HL to form an effective address (EA). Combine the contents of 16-bit register rr with the 16-bit memory word addressed by the EA in a bitwise logical exclusive-OR operation. Then write back the
result into rr.
1 1 1 0
0 1 1 1 1 0 r r
r 1 0 1
Z Z – – – – 6
XOR rr,(HL+C)
rr ← rr
^
(HL+C)
Sign-extend the contents of C and add the result to HL to form an effective address (EA). Combine the contents of 16-bit register rr with
the 16-bit memory word addressed by the EA in a bitwise logical exclusive-OR operation. Then write back the result into rr.
1 1 1 0
0 1 1 0 1 0 r r
r 1 0 1
Z Z – – – – 5
SP ← SP+1:rr ← rr^(SP)
XOR rr,(+SP)
Combine the contents of 16-bit register rr with the 16-bit memory word addressed by (SP+1) in a bitwise logical exclusive-OR operation.
Then write back the result into rr.
XOR rr,(PC+A)Note
Sign-extend the contents of A and add the result to PC to form an effective address (EA). Combine the contents of 16-bit register rr with
the 16-bit memory word addressed by the EA in a bitwise logical exclusive-OR operation. Then write back the result into rr.
0 1 0 0
0 0 1 0
INC r
RA000
r 1 0 1
Z Z – – – – 6
0 r r r
C Z – – – – 1
rr ← rr^(PC+A)
r ← r+1
Increment the contents of 8-bit register r. The Jump Status and Zero flags are set to 1 when an overflow occurs. The Carry flag is not
affected.
Example: Assume L contains 0xFF. Then, the instruction “INC L” loads 0x00 into L and sets ZF and JF to 1.
0 0 1 1
INC rr
1 1 1 1 1 0 r r
0 r r r
C Z – – – – 2
rr ← rr+1
Increment the contents of 16-bit register rr. The Jump Status and Zero flags are set to 1 when an overflow occurs.
Example: Assume HL contains 0x1234. Then, the instruction “INC HL” loads 0x1235 into HL and clears ZF and JF to 0.
Page 46
TLCS-870/C1
Flag
Mnemonic
Instruction Code (Binary)
Cycle
Operation
J Z C H S V
1 1 1 0
INC (x)
0 0 0 0 x x x x
x x x x 1 1 1 1
0 0 0 0 C Z – – – – 5
(x) ← (x)+1
Increment the contents of the memory location directly addressed by x. The Jump Status and Zero flags are set to 1 when an overflow
occurs. (0x0000 ≤ x ≤ 0x00FF)
1 1 1 0
1 1 1 1
INC (vw)
0 0 0 1 w w w w
0 0 0 0
w w w w v v v v
v v v v C Z – – – – 6
(vw) ← (vw)+1
Increment the contents of the memory location directly addressed by vw. The Jump Status and Zero flags are set to 1 when an overflow
occurs. (0x0000 ≤ vw ≤ 0xFFFF)
1 1 1 0
0 0 1 0 1 1 1 1
0 0 0 0
C Z – – – – 4
(DE) ← (DE)+1
INC (DE)
Increment the contents of the memory location addressed by DE. The Jump Status and Zero flags are set to 1 when an overflow occurs.
1 1 1 0
0 0 1 1 1 1 1 1
0 0 0 0
C Z – – – – 4
INC (HL)
(HL) ← (HL)+1
Increment the contents of the memory location addressed by HL. The Jump Status and Zero flags are set to 1 when an overflow occurs.
1 1 1 0
0 1 0 0 1 1 1 1
0 0 0 0
C Z – – – – 4
(IX) ← (IX)+1
INC (IX)
Increment the contents of the memory location addressed by IX. The Jump Status and Zero flags are set to 1 when an overflow occurs.
1 1 1 0
0 1 0 1 1 1 1 1
0 0 0 0
C Z – – – – 4
INC (IY)
(IY) ← (IY)+1
Increment the contents of the memory location addressed by IY. The Jump Status and Zero flags are set to 1 when an overflow occurs.
1 1 0 1
0 1 0 0 d d d d
d d d d 1 1 1 1
0 0 0 0 C Z – – – – 6
(IX+d) ← (IX+d)+1
INC (IX+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to IX to form an effective address (EA). Increment the contents of the memory location at the EA. The Jump Status and Zero flags are set to 1 when an overflow occurs.
INC (IY+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to IY to form an effective address (EA). Increment the contents of the memory location at the EA. The Jump Status and Zero flags are set to 1 when an overflow occurs.
INC (SP+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to SP to form an effective address (EA). Increment the contents of the memory location at the EA. The Jump Status and Zero flags are set to 1 when an overflow occurs.
INC (HL+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to HL to form an effective address (EA). Increment the contents of the memory location at the EA. The Jump Status and Zero flags are set to 1 when an overflow occurs.
INC (HL+C)
Sign-extend the contents of C and add the result to HL to form an effective address (EA). Increment the contents of the memory location
at the EA. The Jump Status and Zero flags are set to 1 when an overflow occurs.
1 1 0 1
1 1 0 1
1 1 0 1
1 1 1 0
1 1 1 0
0 1 0 1 d d d d
0 1 1 0 d d d d
0 1 1 1 d d d d
0 1 1 1 1 1 1 1
0 1 1 0 1 1 1 1
d d d d 1 1 1 1
d d d d 1 1 1 1
d d d d 1 1 1 1
0 0 0 0
0 0 0 0 C Z – – – – 6
0 0 0 0 C Z – – – – 6
0 0 0 0 C Z – – – – 6
C Z – – – – 6
0 0 0 0
C Z – – – – 5
INC (+SP)
(IY+d) ← (IY+d)+1
(SP+d) ← (SP+d)+1
(HL+d) ← (HL+d)+1
(HL+C) ← (HL+C)+1
SP ← SP+1:(SP) ← (SP)+1
Increment the contents of the memory location at (SP+1). The Jump Status and Zero flags are set to 1 when an overflow occurs.
0 1 0 0
Note
INC (PC+A)
(PC+A) ← (PC+A)+1
1 r r r
C Z – – – – 1
r ← r–1
1 r r r
C Z – – – – 2
rr ← rr–1
Decrement the contents of 16-bit register rr. The Jump Status flag is set to 1 when an underflow occurs (i.e., when the result becomes
0xFFFF).
Example: Assume HL contains 0x8765. Then, the instruction “DEC HL” loads 0x8764 into HL and clears ZF and JF to 0.
1 1 1 0
DEC (x)
C Z – – – – 6
Decrement the contents of 8-bit register r. The Jump Status flag is set to 1 when an underflow occurs (i.e., when the result becomes 0xFF).
The Carry flag is not affected.
Example: Assume L contains 0x00. Then, the instruction “DEC L” loads 0xFF into L, clears ZF to 0 and sets JF to 1.
0 0 1 1
DEC rr
0 0 0 0
Sign-extend the contents of A and add the result to PC to form an effective address (EA). Increment the contents of the memory location
at the EA. The Jump Status and Zero flags are set to 1 when an overflow occurs.
0 0 1 0
DEC r
1 1 1 1 1 1 1 1
0 0 0 0 x x x x
x x x x 1 1 1 1
1 0 0 0 C Z – – – – 5
(x) ← (x)–1
Decrement the contents of the memory location directly addressed by x. The Jump Status flag is set to 1 when an underflow occurs.
(0x0000 ≤ x ≤ 0x00FF)
1 1 1 0
1 1 1 1
DEC (vw)
0 0 0 1 w w w w
1 0 0 0
w w w w v v v v
v v v v C Z – – – – 6
(vw) ← (vw)–1
Decrement the contents of the memory location directly addressed by vw. The Jump Status flag is set to 1 when an underflow occurs.
(0x0000 ≤ vw ≤ 0xFFFF)
1 1 1 0
0 0 1 0 1 1 1 1
1 0 0 0
C Z – – – – 4
DEC (DE)
(DE) ← (DE)–1
Decrement the contents of the memory location addressed by DE. The Jump Status flag is set to 1 when an underflow occurs.
1 1 1 0
0 0 1 1 1 1 1 1
1 0 0 0
C Z – – – – 4
(HL) ← (HL)–1
DEC (HL)
Decrement the contents of the memory location addressed by HL. The Jump Status flag is set to 1 when an underflow occurs.
1 1 1 0
0 1 0 0 1 1 1 1
1 0 0 0
C Z – – – – 4
DEC (IX)
(IX) ← (IX)–1
Decrement the contents of the memory location addressed by IX. The Jump Status flag is set to 1 when an underflow occurs.
RA000
Page 47
2.2 ALU Instructions
2.2 ALU Instructions
TLCS-870/C1
Flag
Mnemonic
Instruction Code (Binary)
Cycle
Operation
J Z C H S V
1 1 1 0
0 1 0 1 1 1 1 1
1 0 0 0
(IY) ← (IY)–1
C Z – – – – 4
DEC (IY)
Decrement the contents of the memory location addressed by IY. The Jump Status flag is set to 1 when an underflow occurs.
1 1 0 1
DEC (IX+d)
d d d d 1 1 1 1
(IY+d) ← (IY+d)–1
1 0 0 0 C Z – – – – 6
0 1 1 0 d d d d
d d d d 1 1 1 1
(SP+d) ← (SP+d)–1
1 0 0 0 C Z – – – – 6
0 1 1 1 d d d d
d d d d 1 1 1 1
(HL+d) ← (HL+d)–1
1 0 0 0 C Z – – – – 6
Sign-extend the 8-bit displacement d in the instruction code and add the result to HL to form an effective address (EA). Decrement the
contents of the memory location at the EA. The Jump Status flag is set to 1 when an underflow occurs.
1 1 1 0
DEC (HL+C)
0 1 0 1 d d d d
Sign-extend the 8-bit displacement d in the instruction code and add the result to SP to form an effective address (EA). Decrement the
contents of the memory location at the EA. The Jump Status flag is set to 1 when an underflow occurs.
1 1 0 1
DEC (HL+d)
(IX+d) ← (IX+d)–1
1 0 0 0 C Z – – – – 6
Sign-extend the 8-bit displacement d in the instruction code and add the result to IY to form an effective address (EA). Decrement the contents of the memory location at the EA. The Jump Status flag is set to 1 when an underflow occurs.
1 1 0 1
DEC (SP+d)
d d d d 1 1 1 1
Sign-extend the 8-bit displacement d in the instruction code and add the result to IX to form an effective address (EA). Decrement the contents of the memory location at the EA. The Jump Status flag is set to 1 when an underflow occurs.
1 1 0 1
DEC (IY+d)
0 1 0 0 d d d d
0 1 1 1 1 1 1 1
1 0 0 0
(HL+C) ← (HL+C)–1
C Z – – – – 6
Sign-extend the contents of C and add the result to HL to form an effective address (EA). Decrement the contents of the memory location
at the EA. The Jump Status flag is set to 1 when an underflow occurs.
1 1 1 0
0 1 1 0 1 1 1 1
1 0 0 0
SP ← SP+1:(SP) ← (SP)–1
C Z – – – – 5
DEC (+SP)
Decrement the contents of the memory location at (SP-1). The Jump Status flag is set to 1 when an underflow occurs.
0 1 0 0
DEC (PC+A)Note
1 1 1 1 1 1 1 1
1 0 0 0
(PC+A) ← (PC+A)–1
C Z – – – – 6
Sign-extend the contents of A and add the result to PC to form an effective address (EA). Decrement the contents of the memory location
at the EA. The Jump Status flag is set to 1 when an underflow occurs.
1 1 1 0
1 g g g 1 1 0 1
1 0 1 0
C Z C H – – 2
Decimal adjustment against g
(after addition)
When performing an add operation on an 8-bit packed BCD number, the contents of register g is decimal adjusted after the execution of an
add instruction (ADD/ADDC).
For multi-digit BCD number, add and adjust operations must be performed on each byte, beginning with the lowest-order digit.
DAA g
Carry Flag
Before
Adjustment
High-order 4
Bits of Register g
Before Adjusting
0
0 to 9
0
0 to 9
00
0
0
0 to 8
0
A to F
06
0
0
0 to 9
1
0 to 3
06
0
0
A to F
0
0 to 9
60
1
0
9 to F
0
A to F
66
1
0
A to F
1
0 to 3
66
1
1
0 to 2
0
0 to 9
60
1
1
0 to 2
0
A to F
66
1
1
0 to 3
1
0 to 3
66
1
Half Carry
Flag Before
Adjustment
Low-order 4
Bits of Register g
Before Adjusting
Value Added
for Adjustment
Carry Flag
After Adjustment
Example: Assume A and B contain 0x26 and 0x57 respectively. The instruction “ADD A, B” loads 0x7D into A and clears CF and HF to 0.
Then, the instruction “DAA A” loads 0x83 into A while CF is not affected.
RA000
Page 48
TLCS-870/C1
Flag
Mnemonic
Instruction Code (Binary)
Cycle
Operation
J Z C H S V
1 1 1 0
1 g g g 1 1 0 1
1 0 1 1
C Z C H – – 2
Decimal adjustment against g
(after subtraction)
When performing a subtract operation on an 8-bit packed BCD number, the contents of register g is decimal adjusted after the execution of
a subtract instruction (SUB/SUBB).
For multi-digit BCD number, subtract and adjust operations must be performed on each byte, beginning with the lowest-order digit.
DAS g
Carry Flag
Before
Adjustment
High-order 4
Bits of Register g
Before Adjusting
Half Carry
Flag Before
Adjustment
0
0 to 9
0
0
0 to 9
1
1
7 to F
0
1
6 to F
1
Low-order 4
Bits of Register g
Before Adjusting
Value Added
for Adjustment
Carry Flag
After Adjustment
0 to 9
00
0
6 to F
FA
0
0 to 9
A0
1
6 to F
9A
1
Example: Assume A and B contain 0x87 and 0x39 respectively. The instruction “SUB A, B” loads 0x4E into A, clears CF to 0 and sets HF
to 1. Then, the instruction “DAS A” loads 0x48 into A while CF is not affected.
1 1 1 0
1 0 0 0 1 1 1 1
0 0 1 0
Z Z – – – – 13
WA ← W×A
Multiply the contents of W (unsigned integer) and that of A (unsigned integer) and places the product into WA. The Zero flag is set to 1
when the high-order 8 bits of the result (the value loaded into W) is 0x00; otherwise, it is cleared to 0.
Example 1: Assume W and A contain 0x87 and 0xF2 respectively. Then, this instruction loads 0x7F9E into WA and clears ZF to 0.
Example 2: Assume W and A contain 0x16 and 0x05 respectively. Then, this instruction loads 0x006E into WA and sets ZF to 1.
MUL W,A
1 1 1 0
1 0 0 1 1 1 1 1
0 0 1 0
Z Z – – – – 13
BC ← B×C
MUL B,C
Multiply the contents of B (unsigned integer) and that of C (unsigned integer) and places the product into BC. The Zero flag is set to 1
when the high-order 8 bits of the result (the value loaded into B) is 0x00; otherwise, it is cleared to 0.
MUL D,E
Multiply the contents of D (unsigned integer) and that of E (unsigned integer) and places the product into DE. The Zero flag is set to 1
when the high-order 8 bits of the result (the value loaded into D) is 0x00; otherwise, it is cleared to 0.
MUL H,L
Multiply the contents of H (unsigned integer) and that of L (unsigned integer) and places the product into HL. The Zero flag is set to 1 when
the high-order 8 bits of the result (the value loaded into H) is 0x00; otherwise, it is cleared to 0.
1 1 1 0
1 1 1 0
1 1 1 0
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 1
1 0 0 0 1 1 1 1
0 0 1 0
Z Z – – – – 13
0 0 1 0
Z Z – – – – 13
0 0 1 1
Z Z C – – – 13
DE ← D×E
HL ← H×L
A ← WA÷C, W ← Remainder
Divide the contents of WA (unsigned integer) by that of C (unsigned integer) and places the quotient and the remainder into A and W,
respectively. The Carry flag is set to 1 when the divisor (contents of C) is 0x00 or when the quotient is greater than 0x100 (at the same
time, the contents of A and W become undefined); otherwise, it is cleared to 0. The Zero flag is set to 1 when the remainder is 0x00; otherwise it is cleared to 0. The contents of C is not affected.
Example 1: Assume WA and C contain 0x1234 and 0x56 respectively.
Then, this instruction loads 0x36 and 0x10 into A and W respectively, and clears CF and ZF to 0.
Example 2: Assume WA and C contain 0x4830 and 0x9A respectively.
Then, this instruction loads 0x78 and 0x00 into A and W respectively, clears CF to 0 and sets ZF to 1.
Example 3: Assume WA and C contain 0x3210 and 0x27 respectively.
Then, this instruction loads 0x48 and 0x18 into A and W respectively, sets CF to 1 and clea ZF to 0.
DIV WA,C
1 1 1 0
1 0 1 0 1 1 1 1
0 0 1 1
Z Z C – – – 13
E ← DE÷C, D ← Remainder
Divide the contents of DE (unsigned integer) by that of C (unsigned integer) and places the low-order 8 bits of the quotient and the remainder into E and D, respectively. The Carry flag is set to 1 when the divisor (contents of C) is 0x00 or when the quotient is greater than 0x100
(at the same time, the contents of DE becomes undefined). The Zero flag is set to 1 when the remainder is 0x00. The contents of C is not
affected.
DIV DE,C
1 1 1 0
1 0 1 1 1 1 1 1
0 0 1 1
Z Z C – – – 13
L ← HL÷C, H ← Remainder
Divide the contents of HL (unsigned integer) by that of C (unsigned integer) and places the low-order 8 bits of the quotient and the remainder into L and H, respectively. The Carry flag is set to 1 when the divisor (contents of C) is 0x00 or when the quotient is greater than 0x100
(at the same time, the contents of DE becomes undefined). The Zero flag is set to 1 when the remainder is 0x00. The contents of C is not
affected.
DIV HL,C
1 1 1 0
NEG CS,gg
1 g g g 1 1 1 1
1 0 1 0
1 – – – – – 3
if CF=1 then gg ← 0–gg else null
When the Carry flag is set, replace the contents of 16-bit register gg with its 2’s complement and set the Jump Status flag to 1.
When the Carry flag is cleared, set the Jump Status flag to 1 and skip to the next instruction (while the contents of register gg is not
affected).
Example 1: Assume HL contains 0x5678 and CF is set.
Then, the instruction “NEG CS, HL” replaces the contents of HL with 0xA988 and sets CF to 1.
Example 2: Assume DE contains 0x89AB and CF is cleared.
Then, the instruction “NEG CS, DE” replaces the contents of DE with 0x89AB and clears CF to 0.
Note: There are restrictions on instructions that uses the operand (PC + A). For more details, see "1.4 Addressing Mode".
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2.2 ALU Instructions
2.2 ALU Instructions
RA000
TLCS-870/C1
Page 50
TLCS-870/C1
2.3 Shift, Rotate and Nibble Manipulation Instructions
Flag
Mnemonic
Instruction Code (Binary)
J Z C H S V
1 1 1 0
SHLC g
7654321 0
CF
0
1 g g g 1 1 1 1
0 1 0 1
C Z * – – – 2
7654321 0
0
CF
1 g g g 1 1 1 1
0 1 1 0
C Z * – – – 2
CF
7654321 0
Rotate the contents of 8-bit register g and the Carry flag to left by 1 bit altogether. The Zero flag is set to 1 when g is 0x00 as a result of a
rotation.
Example 1: Assume A contains 0y10010110 and CF is cleared.
After executing this instruction, A has 0y00101100, CF and JF are set to 1 and ZF is cleared to 0.
Example 2: Assume A contains 0y10000000 and CF is cleared.
After executing this instruction, A has 0y00000000; and CF, JF and ZF are set to 1.
1 1 1 0
RORC g
C Z * – – – 2
Logically shift the contents of 8-bit register g right by 1 bit. (At the same time, insert a 0 into the most-significant bit of g. The Carry flag
holds the least-significant bit shifted out of g.) The Zero flag is set to 1 when the g is 0x00 as a result of a shift.
Example: Assume A contains 0y01011101 and CF is cleared. After executing this instruction, A has 0y00101110; CF is set to 1; and ZF is
cleared to 0.
1 1 1 0
ROLC g
0 1 0 0
Operation
Logically shift the contents of 8-bit register g left by 1 bit. (At the same time, insert a 0 into the least-significant bit of g. The Carry flag
holds the most-significant bit shifted out of g.) The Zero flag is set to 1 when g is 0x00 as a result of a shift.
Example: Assume A contains 0y00111011 and CF is set. After executing this instruction, A has 0y01110110; and CF and ZF are cleared
to 0.
1 1 1 0
SHRC g
1 g g g 1 1 1 1
Cycl
e
1 g g g 1 1 1 1
0 1 1 1
C Z * – – – 2
7654321 0
CF
Rotate the contents of 8-bit register g and the Carry flag to right by 1 bit altogether. The Zero flag is set to 1 when g is 0x00 as a result of
a rotation.
Example 1: Assume A contains 0y01101101 and CF is set.
After executing this instruction, A has 0y10110110; CF is set to 1; and ZF is cleared to 0.
1 1 1 0
1 g g g 1 1 1 1
0 0 0 0
gg
C Z * – S V 3
0
CF
SHLCA gg
Arithmetically shift the contents of 16-bit register gg left by 1 bit. (At the same time, insert a 0 into the least-significant bit of gg. The Carry
flag holds the most-significant bit shifted out of gg.) The Zero flag is set to 1 when gg is 0x0000 as a result of a shift. The Overflow flag is
set to 1 when the most-significant bit of gg changes as a result of a shift.
Example: Assume HL contains 0x3456 and CF is set.
After executing the instruction “SHLCA HL”, HL has 0x68AC; and CF, JF, ZF, SF and VF are cleared to 0.
1 1 1 0
1 g g g 1 1 1 1
0 0 0 1
gg
C Z * – S 0 3
CF
SHRCA gg
Arithmetically shift the contents of 16-bit register gg right by 1 bit. (The most-significant bit of gg is not affected. The Carry flag holds the
least-significant bit shifted out of gg.) The Zero flag is set to 1 when gg is 0x0000 as a result of a shift.
Example: Assume DE contains 0x89AB and CF is cleared.
After executing the instruction “SHLCA DE”, HL has 0xC4D5; CF and SF are set to 1; and JF, ZF and VF are cleared to 0.
1 1 1 0
1 g g g 1 1 1 1
1 1 1 1
1 – – – – – 7
SWAP g
7654321 0
(Swap the high- and low-order 4 bits)
Swap the high-order 4 bits of 8-bit register g with the remaining low-order 4 bits.
Example: Assume A contains 0x25. After executing this instruction, A has 0x52.
A
1 1 1 0
0 0 0 0 x x x x
x x x x 1 1 1 1
0 1 1 0 1 – – – – – 9
(x)
7654321 0
7654321 0
(Rotate left by 4 bits)
ROLD A,(x)
Concatenate the contents of the memory location directly addressed by x with the low-order 4 bits of A. Rotate the concatenated 12-bit
data left by 4 bits. The high-order 4 bits of A are not affected. (0x0000 ≤ x ≤ 0x00FF)
Example: Assume A and the memory location at address 0x0087 contain 0x12 and 0x56 respectively. After executing the instruction
“ROLD A, (0x87)”, A has 0x15 and the memory location at address 0x0087 has 0x62.
1 1 1 0
1 1 1 1
0 0 0 1 w w w w
0 1 1 0
w w w w v v v v
v v v v 1 – – – – – 10
A
(vw)
7654321 0
ROLD A,(vw)
7654321 0
(Rotate left by 4 bits)
Concatenate the contents of the memory location directly addressed by vw with the low-order 4 bits of A. Rotate the concatenated 12-bit
data left by 4 bits. The high-order 4 bits of A are not affected. (0x0000 ≤ vw ≤ 0xFFFF)
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2.3 Shift, Rotate and Nibble Manipulation Instructions
2.3 Shift, Rotate and Nibble Manipulation Instructions
TLCS-870/C1
Flag
Mnemonic
Instruction Code (Binary)
J Z C H S V
Cycl
e
Operation
A
1 1 1 0
0 0 1 0 1 1 1 1
0 1 1 0
1 – – – – – 8
(DE)
7654321 0
ROLD A,(DE)
7654321 0
(Rotate left by 4 bits)
Concatenate the contents of the memory location addressed by DE with the low-order 4 bits of A. Rotate the concatenated 12-bit data left
by 4 bits. The high-order 4 bits of A are not affected.
A
1 1 1 0
0 0 1 1 1 1 1 1
0 1 1 0
1 – – – – – 8
(HL)
7654321 0
ROLD A,(HL)
7654321 0
(Rotate left by 4 bits)
Concatenate the contents of the memory location addressed by HL with the low-order 4 bits of A. Rotate the concatenated 12-bit data left
by 4 bits. The high-order 4 bits of A are not affected.
A
1 1 1 0
0 1 0 0 1 1 1 1
0 1 1 0
1 – – – – – 8
(IX)
7654321 0
ROLD A,(IX)
7654321 0
(Rotate left by 4 bits)
Concatenate the contents of the memory location addressed by IX with the low-order 4 bits of A. Rotate the concatenated 12-bit data left
by 4 bits. The high-order 4 bits of A are not affected.
A
1 1 1 0
0 1 0 1 1 1 1 1
0 1 1 0
1 – – – – – 8
(IY)
7654321 0
ROLD A,(IY)
7654321 0
(Rotate left by 4 bits)
Concatenate the contents of the memory location addressed by IY with the low-order 4 bits of A. Rotate the concatenated 12-bit data left
by 4 bits. The high-order 4 bits of A are not affected.
A
1 1 0 1
0 1 0 0 d d d d
d d d d 1 1 1 1
0 1 1 0 1 – – – – – 10
(IX + d)
7654321 0
7654321 0
(Rotate left by 4 bits)
ROLD A,(IX+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to IX to form an effective address (EA). Concatenate the
contents of the memory location at the EA with the low-order 4 bits of A. Rotate the concatenated 12-bit data left by 4 bits. The high-order
4 bits of A are not affected.
A
1 1 0 1
0 1 0 1 d d d d
d d d d 1 1 1 1
0 1 1 0 1 – – – – – 10
(IY + d)
7654321 0
7654321 0
(Rotate left by 4 bits)
ROLD A,(IY+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to IY to form an effective address (EA). Concatenate the
contents of the memory location at the EA with the low-order 4 bits of A. Rotate the concatenated 12-bit data left by 4 bits. The high-order
4 bits of A are not affected.
A
1 1 0 1
0 1 1 0 d d d d
d d d d 1 1 1 1
0 1 1 0 1 – – – – – 10
(SP + d)
7654321 0
7654321 0
(Rotate left by 4 bits)
ROLD A,(SP+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to SP to form an effective address (EA). Concatenate the
contents of the memory location at the EA with the low-order 4 bits of A. Rotate the concatenated 12-bit data left by 4 bits. The high-order
4 bits of A are not affected.
A
1 1 0 1
0 1 1 1 d d d d
d d d d 1 1 1 1
0 1 1 0 1 – – – – – 10
(HL + d)
7654321 0
7654321 0
(Rotate left by 4 bits)
ROLD A,(HL+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to HL to form an effective address (EA). Concatenate the
contents of the memory location at the EA with the low-order 4 bits of A. Rotate the concatenated 12-bit data left by 4 bits. The high-order
4 bits of A are not affected.
A
1 1 1 0
0 1 1 1 1 1 1 1
0 1 1 0
1 – – – – – 10
(HL + C)
7654321 0
ROLD A,(HL+C)
7654321 0
(Rotate left by 4 bits)
Sign-extend the contents of C and add the result to HL to form an effective address (EA). Concatenate the contents of the memory location at the EA with the low-order 4 bits of A. Rotate the concatenated 12-bit data left by 4 bits. The high-order 4 bits of A are not affected.
A
1 1 1 0
0 1 1 0 1 1 1 1
0 1 1 0
1 – – – – – 9
ROLD A,(+SP)
(+SP)
7654321 0
7654321 0
(Rotate left by 4 bits)
Concatenate the contents of the memory location at (SP+1) with the low-order 4 bits of A. Rotate the concatenated 12-bit data left by 4
bits. The high-order 4 bits of A are not affected.
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TLCS-870/C1
Flag
Mnemonic
Instruction Code (Binary)
J Z C H S V
Cycl
e
Operation
A
ROLD
0 1 0 0
1 1 1 1 1 1 1 1
0 1 1 0
1 – – – – – 10
(PC + A)
7654321 0
A,(PC+A)Note
7654321 0
(Rotate left by 4 bits)
Sign-extend the contents of A and add the result to PC to form an effective address (EA). Concatenate the contents of the memory location at the EA with the low-order 4 bits of A. Rotate the concatenated 12-bit data left by 4 bits. The high-order 4 bits of A are not affected.
A
1 1 1 0
0 0 0 0 x x x x
x x x x 1 1 1 1
0 1 1 1 1 – – – – – 9
(x)
7654321 0
7654321 0
(Rotate right by 4 bits)
RORD A,(x)
Concatenate the contents of the memory location directly addressed by x with the low-order 4 bits of A. Rotate the concatenated 12-bit
data right by 4 bits. The high-order 4 bits of A are not affected. (0x0000 ≤ x ≤ 0x00FF)
Example: Assume A and the memory location at address 0x0087 contain 0x12 and 0x56 respectively. After executing the instruction
“ROLD A, (0x87)”, A has 0x16 and the memory location at address 0x0087 has 0x25.
1 1 1 0
1 1 1 1
0 0 0 1 w w w w
0 1 1 1
w w w w
v v v
v v v v 1 – – – – – 10
A
(vw)
7654321 0
RORD A,(vw)
7654321 0
(Rotate right by 4 bits)
Concatenate the contents of the memory location directly addressed by vw with the low-order 4 bits of A. Rotate the concatenated 12-bit
data right by 4 bits. The high-order 4 bits of A are not affected. (0x0000 ≤ vw ≤ 0xFFFF)
A
1 1 1 0
0 0 1 0 1 1 1 1
0 1 1 1
1 – – – – – 8
(DE)
7654321 0
RORD A,(DE)
7654321 0
(Rotate right by 4 bits)
Concatenate the contents of the memory location addressed by DE with the low-order 4 bits of A. Rotate the concatenated 12-bit data
right by 4 bits. The high-order 4 bits of A are not affected.
A
1 1 1 0
0 0 1 1 1 1 1 1
0 1 1 1
1 – – – – – 8
(HL)
7654321 0
RORD A,(HL)
7654321 0
(Rotate right by 4 bits)
Concatenate the contents of the memory location addressed by HL with the low-order 4 bits of A. Rotate the concatenated 12-bit data
right by 4 bits. The high-order 4 bits of A are not affected.
A
1 1 1 0
0 1 0 0 1 1 1 1
0 1 1 1
1 – – – – – 8
(IX)
7654321 0
RORD A,(IX)
7654321 0
(Rotate right by 4 bits)
Concatenate the contents of the memory location addressed by IX with the low-order 4 bits of A. Rotate the concatenated 12-bit data right
by 4 bits. The high-order 4 bits of A are not affected.
A
1 1 1 0
0 1 0 1 1 1 1 1
0 1 1 1
1 – – – – – 8
(IY)
7654321 0
RORD A,(IY)
7654321 0
(Rotate right by 4 bits)
Concatenate the contents of the memory location addressed by IY with the low-order 4 bits of A. Rotate the concatenated 12-bit data right
by 4 bits. The high-order 4 bits of A are not affected.
A
1 1 0 1
0 1 0 0 d d d d
d d d d 1 1 1 1
0 1 1 1 1 – – – – – 10
(IX + d)
7654321 0
7654321 0
(Rotate right by 4 bits)
RORD A,(IX+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to IX to form an effective address (EA). Concatenate the
contents of the memory location at the EA with the low-order 4 bits of A. Rotate the concatenated 12-bit data right by 4 bits. The highorder 4 bits of A are not affected.
A
1 1 0 1
0 1 0 1 d d d d
d d d d 1 1 1 1
0 1 1 1 1 – – – – – 10
(IY + d)
7654321 0
7654321 0
(Rotate right by 4 bits)
RORD A,(IY+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to IY to form an effective address (EA). Concatenate the
contents of the memory location at the EA with the low-order 4 bits of A. Rotate the concatenated 12-bit data right by 4 bits. The highorder 4 bits of A are not affected.
A
1 1 0 1
0 1 1 0 d d d d
d d d d 1 1 1 1
0 1 1 1 1 – – – – – 10
(SP + d)
7654321 0
7654321 0
(Rotate right by 4 bits)
RORD A,(SP+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to SP to form an effective address (EA). Concatenate the
contents of the memory location at the EA with the low-order 4 bits of A. Rotate the concatenated 12-bit data right by 4 bits. The highorder 4 bits of A are not affected.
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2.3 Shift, Rotate and Nibble Manipulation Instructions
2.3 Shift, Rotate and Nibble Manipulation Instructions
TLCS-870/C1
Flag
Mnemonic
Instruction Code (Binary)
J Z C H S V
Cycl
e
Operation
A
1 1 0 1
0 1 1 1 d d d d
d d d d 1 1 1 1
0 1 1 1 1 – – – – – 10
(HL + d)
7654321 0
7654321 0
(Rotate right by 4 bits)
RORD A,(HL+d)
Sign-extend the 8-bit displacement d in the instruction code and add the result to HL to form an effective address (EA). Concatenate the
contents of the memory location at the EA with the low-order 4 bits of A. Rotate the concatenated 12-bit data right by 4 bits. The highorder 4 bits of A are not affected.
A
1 1 1 0
0 1 1 1 1 1 1 1
0 1 1 1
1 – – – – – 10
(HL + C)
7654321 0
RORD A,(HL+C)
7654321 0
(Rotate right by 4 bits)
Sign-extend the contents of C and add the result to HL to form an effective address (EA). Concatenate the contents of the memory location at the EA with the low-order 4 bits of A. Rotate the concatenated 12-bit data right by 4 bits. The high-order 4 bits of A are not affected.
A
1 1 1 0
0 1 1 0 1 1 1 1
0 1 1 1
1 – – – – – 9
(+SP)
7654321 0
RORD A,(+SP)
7654321 0
(Rotate right by 4 bits)
Concatenate the contents of the memory location at (SP+1) with the low-order 4 bits of A. Rotate the concatenated 12-bit data right by 4
bits. The high-order 4 bits of A are not affected.
A
0 1 0 0
RORD
1 1 1 1 1 1 1 1
0 1 1 1
1 – – – – – 10
A,(PC+A)Note
(PC + A)
7654321 0
7654321 0
(Rotate right by 4 bits)
Sign-extend the contents of A and add the result to PC to form an effective address (EA). Concatenate the contents of the memory location at the EA with the low-order 4 bits of A. Rotate the concatenated 12-bit data right by 4 bits. The high-order 4 bits of A are not affected.
Note: There are restrictions on instructions that uses the operand (PC + A). For more details, see "1.4 Addressing Mode".
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TLCS-870/C1
2.4 Bit and Flag Manipulation Instructions
Flag
Mnemonic
Instruction Code (Binary)
Cycle
Operation
J Z C H S V
1 1 1 0
1 g g g 1 1 0 0
0 b b b
Z * – – – – 3
ZF ← g.b:g.b ← 1
SET g.b
Invert bit b of 8-bit register g and place the result into the Zero flag. Then set the specified register bit of g to 1.
Example: Assume A contains 0x3C. After executing the instruction “SET A. 7”, A has 0xBC; and ZF is set to 1.
SET (x).b
Invert bit b in the memory location directly addressed by x and place the result into the Zero flag. Then set the specified memory bit to 1.
1 1 0 0
0 b b b x x x x
x x x x
Z * – – – – 4
ZF ← (x).b:(x).b ← 1
(0x0000 ≤ x ≤ 0x00FF)
1 1 1 0
1 1 0 0
0 0 0 1 w w w w
0 b b b
w w w w v v v v
v v v v Z * – – – – 6
ZF ← (vw).b:(vw).b ← 1
SET (vw).b
Invert bit b in the memory location directly addressed by vw and place the result into the Zero flag. Then set the specified memory bit to 1.
(0x0000 ≤ vw ≤ 0xFFFF)
1 1 1 0
0 0 1 0 1 1 0 0
0 b b b
Z * – – – – 4
ZF ← (DE).b:(DE).b ← 1
SET (DE).b
Invert bit b in the memory location addressed by DE and place the result into the Zero flag. Then set the specified memory bit to 1.
1 1 1 0
0 0 1 1 1 1 0 0
0 b b b
Z * – – – – 4
ZF ← (HL).b:(HL).b ← 1
SET (HL).b
Invert bit b in the memory location addressed by HL and place the result into the Zero flag. Then set the specified memory bit to 1.
1 1 1 0
0 1 0 0 1 1 0 0
0 b b b
Z * – – – – 4
ZF ← (IX).b:(IX).b ← 1
SET (IX).b
Invert bit b in the memory location addressed by IX and place the result into the Zero flag. Then set the specified memory bit to 1.
1 1 1 0
0 1 0 1 1 1 0 0
0 b b b
Z * – – – – 4
ZF ← (IY).b:(IY).b ← 1
SET (IY).b
Invert bit b in the memory location addressed by IY and place the result into the Zero flag. Then set the specified memory bit to 1.
1 1 0 1
SET (IX+d).b
0 1 0 0 d d d d
d d d d 1 1 0 0
0 b b b Z * – – – – 6
ZF ← (IX+d).b:(IX+d).b ← 1
Sign-extend the 8-bit displacement d in the instruction code and add the result to IX to form an effective address (EA). Invert bit b in the memory location at the EA and place the result into the Zero flag. Then set the specified memory bit to 1.
1 1 0 1
0 1 0 1 d d d d
d d d d 1 1 0 0
0 b b b Z * – – – – 6
ZF ← (IY+d).b:(IY+d).b ← 1
SET (IY+d).b
Sign-extend the 8-bit displacement d in the instruction code and add the result to IY to form an effective address (EA). Invert bit b in the memory location at the EA and place the result into the Zero flag. Then set the specified memory bit to 1.
SET (SP+d).b
Sign-extend the 8-bit displacement d in the instruction code and add the result to SP to form an effective address (EA). Invert bit b in the memory location at the EA and place the result into the Zero flag. Then set the specified memory bit to 1.
1 1 0 1
1 1 0 1
0 1 1 0 d d d d
0 1 1 1 d d d d
d d d d 1 1 0 0
d d d d 1 1 0 0
0 b b b Z * – – – – 6
0 b b b Z * – – – – 6
ZF ← (SP+d).b:(SP+d).b ← 1
ZF ← (HL+d).b:(HL+d).b ← 1
SET (HL+d).b
Sign-extend the 8-bit displacement d in the instruction code and add the result to HL to form an effective address (EA). Invert bit b in the memory location at the EA and place the result into the Zero flag. Then set the specified memory bit to 1.
SET (HL+C).b
Sign-extend the contents of C and add the result to HL to form an effective address (EA). Invert bit b in the memory location at the EA and
place the result into the Zero flag. Then set the specified memory bit to 1.
1 1 1 0
1 1 1 0
0 1 1 1 1 1 0 0
0 1 1 0 1 1 0 0
0 b b b
Z * – – – – 6
0 b b b
Z * – – – – 5
ZF ← (HL+C).b:(HL+C).b ← 1
SP ← SP+1:ZF ← (SP).b:(SP).b ← 1
SET (+SP).b
Invert bit b in the memory location at (SP+1) and place the result into the Zero flag. Then set the specified memory bit to 1.
0 1 0 0
1 1 1 1 1 1 0 0
0 b b b
Z * – – – – 6
ZF ← (PC+A).b:(PC+A).b ← 1
SET (PC+A).bNote Sign-extend the contents of A and add the result to PC to form an effective address (EA). Invert bit b in the memory location at the EA and
place the result into the Zero flag. Then set the specified memory bit to 1.
1 1 1 0
SET (x).A
0 0 0 0 x x x x
x x x x 1 1 1 1
0 0 1 0 Z * – – – – 5
ZF ← (x).A:(x).A ← 1
Invert the bit specified by the low-order 3 bits of A in the memory location directly addressed by x and place the result into the Zero flag. Then
set the specified memory bit to 1. (0x0000 ≤ x ≤ 0x00FF)
1 1 1 0
1 1 1 1
0 0 0 1 w w w w
0 0 1 0
w w w w v v v v
v v v v Z * – – – – 6
ZF ← (vw).A:(vw).A ← 1
SET (vw).A
Invert the bit specified by the low-order 3 bits of A in the memory location directly addressed by vw and place the result into the Zero flag. Then
set the specified memory bit to 1. (0x0000 ≤ vw ≤ 0xFFFF)
1 1 1 0
SET (DE).A
1 1 1 0
SET (HL).A
RA000
0 0 1 0 1 1 1 1
0 0 1 0
Z * – – – – 4
ZF ← (DE).A:(DE).A ← 1
Invert the bit specified by the low-order 3 bits of A in the memory location addressed by DE and place the result into the Zero flag. Then set the
specified memory bit to 1.
0 0 1 1 1 1 1 1
0 0 1 0
Z * – – – – 4
ZF ← (HL).A:(HL).A ← 1
Invert the bit specified by the low-order 3 bits of A in the memory location addressed by HL and place the result into the Zero flag. Then set the
specified memory bit to 1.
Page 55
2.4 Bit and Flag Manipulation Instructions
2.4 Bit and Flag Manipulation Instructions
TLCS-870/C1
Flag
Mnemonic
Instruction Code (Binary)
Cycle
Operation
J Z C H S V
1 1 1 0
SET (IX).A
0 1 0 0 1 1 1 1
0 0 1 0
Z * – – – – 4
ZF ← (IX).A:(IX).A ← 1
Invert the bit specified by the low-order 3 bits of A in the memory location addressed by IX and place the result into the Zero flag. Then set the
specified memory bit to 1.
1 1 1 0
0 1 0 1 1 1 1 1
0 0 1 0
Z * – – – – 4
ZF ← (IY).A:(IY).A ← 1
SET (IY).A
Invert the bit specified by the low-order 3 bits of A in the memory location addressed by IY and place the result into the Zero flag. Then set the
specified memory bit to 1.
SET (IX+d).A
Sign-extend the 8-bit displacement d in the instruction code and add the result to IX to form an effective address (EA). Invert the bit specified by
the low-order 3 bits of A in the memory location at the EA and place the result into the Zero flag. Then set the specified memory bit to 1.
1 1 0 1
1 1 0 1
0 1 0 0 d d d d
0 1 0 1 d d d d
d d d d 1 1 1 1
d d d d 1 1 1 1
0 0 1 0 Z * – – – – 6
0 0 1 0 Z * – – – – 6
ZF ← (IX+d).A:(IX+d).A ← 1
ZF ← (IY+d).A:(IY+d).A ← 1
SET (IY+d).A
Sign-extend the 8-bit displacement d in the instruction code and add the result to IY to form an effective address (EA). Invert the bit specified by
the low-order 3 bits of A in the memory location at the EA and place the result into the Zero flag. Then set the specified memory bit to 1.
SET (SP+d).A
Sign-extend the 8-bit displacement d in the instruction code and add the result to SP to form an effective address (EA). Invert the bit specified
by the low-order 3 bits of A in the memory location at the EA and place the result into the Zero flag. Then set the specified memory bit to 1.
1 1 0 1
1 1 0 1
0 1 1 0 d d d d
0 1 1 1 d d d d
d d d d 1 1 1 1
d d d d 1 1 1 1
0 0 1 0 Z * – – – – 6
0 0 1 0 Z * – – – – 6
ZF ← (SP+d).A:(SP+d).A ← 1
ZF ← (HL+d).A:(HL+d).A ← 1
SET (HL+d).A
Sign-extend the 8-bit displacement d in the instruction code and add the result to HL to form an effective address (EA). Invert the bit specified
by the low-order 3 bits of A in the memory location at the EA and place the result into the Zero flag. Then set the specified memory bit to 1.
SET (HL+C).A
Sign-extend the contents of C and add the result to HL to form an effective address (EA). Invert the bit specified by the low-order 3 bits of A in
the memory location at the EA and place the result into the Zero flag. Then set the specified memory bit to 1.
1 1 1 0
1 1 1 0
SET (+SP).A
0 1 1 1 1 1 1 1
0 1 1 0 1 1 1 1
0 0 1 0
Z * – – – – 6
0 0 1 0
Z * – – – – 5
ZF ← (HL+C).A:(HL+C).A ← 1
SP ← SP+1:ZF ← (SP).A:(SP).A ← 1
Invert the bit specified by the low-order 3 bits of A in the memory location at (SP+1) and place the result into the Zero flag. Then set the specified memory bit to 1.
0 1 0 0
1 1 1 1 1 1 1 1
0 0 1 0
Z * – – – – 6
ZF ← (PC+A).A:(PC+A).A ← 1
SET (PC+A).ANote Sign-extend the contents of A and add the result to PC to form an effective address (EA). Invert the bit specified by the low-order 3 bits of A in
the memory location at the EA and place the result into the Zero flag. Then set the specified memory bit to 1.
1 1 1 0
1 g g g 1 1 0 0
1 b b b
Z * – – – – 3
ZF ← g.b:g.b ← 0
CLR g.b
Invert bit b of 8-bit register g and place the result into the Zero flag. Then clear the specified register bit of g to 0.
Example: Assume A contains 0x3C. After executing the instruction “CLR A. 2”, A has 0x38; and ZF is cleared to 0.
CLR (x).b
Invert bit b in the memory location directly addressed by x and place the result into the Zero flag. Then clear the specified memory bit to 0.
1 1 0 0
1 b b b x x x x
x x x x
Z * – – – – 4
ZF ← (x).b:(x).b ← 0
(0x0000 ≤ x ≤ 0x00FF)
1 1 1 0
1 1 0 0
0 0 0 1 w w w w
1 b b b
w w w w v v v v
v v v v Z * – – – – 6
ZF ← (vw).b:(vw).b ← 0
CLR (vw).b
Invert bit b in the memory location directly addressed by vw and place the result into the Zero flag. Then clear the specified memory bit to 0.
(0x0000 ≤ vw ≤ 0xFFFF)
1 1 1 0
0 0 1 0 1 1 0 0
1 b b b
Z * – – – – 4
ZF ← (DE).b:(DE).b ← 0
CLR (DE).b
Invert bit b in the memory location addressed by DE and place the result into the Zero flag. Then clear the specified memory bit to 0.
1 1 1 0
0 0 1 1 1 1 0 0
1 b b b
Z * – – – – 4
ZF ← (HL).b:(HL).b ← 0
CLR (HL).b
Invert bit b in the memory location addressed by HL and place the result into the Zero flag. Then clear the specified memory bit to 0.
1 1 1 0
0 1 0 0 1 1 0 0
1 b b b
Z * – – – – 4
ZF ← (IX).b:(IX).b ← 0
CLR (IX).b
Invert bit b in the memory location addressed by IX and place the result into the Zero flag. Then clear the specified memory bit to 0.
1 1 1 0
0 1 0 1 1 1 0 0
1 b b b
Z * – – – – 4
ZF ← (IY).b:(IY).b ← 0
CLR (IY).b
Invert bit b in the memory location addressed by IY and place the result into the Zero flag. Then clear the specified memory bit to 0.
1 1 0 1
CLR (IX+d).b
0 1 0 0 d d d d
d d d d 1 1 0 0
1 b b b Z * – – – – 6
ZF ← (IX+d).b:(IX+d).b ← 0
Sign-extend the 8-bit displacement d in the instruction code and add the result to IX to form an effective address (EA). Invert bit b in the memory location at the EA and place the result into the Zero flag. Then clear the specified memory bit to 0.
1 1 0 1
0 1 0 1 d d d d
d d d d 1 1 0 0
1 b b b Z * – – – – 6
ZF ← (IY+d).b:(IY+d).b ← 0
CLR (IY+d).b
Sign-extend the 8-bit displacement d in the instruction code and add the result to IY to form an effective address (EA). Invert bit b in the memory location at the EA and place the result into the Zero flag. Then clear the specified memory bit to 0.
CLR (SP+d).b
Sign-extend the 8-bit displacement d in the instruction code and add the result to SP to form an effective address (EA). Invert bit b in the memory location at the EA and place the result into the Zero flag. Then clear the specified memory bit to 0.
1 1 0 1
RA000
0 1 1 0 d d d d
d d d d 1 1 0 0
1 b b b Z * – – – – 6
Page 56
ZF ← (SP+d).b:(SP+d).b ← 0
TLCS-870/C1
Flag
Mnemonic
Instruction Code (Binary)
Cycle
Operation
J Z C H S V
1 1 0 1
CLR (HL+d).b
1 1 1 0
CLR (HL+C).b
0 1 1 1 d d d d
d d d d 1 1 0 0
1 b b b Z * – – – – 6
ZF ← (HL+d).b:(HL+d).b ← 0
Sign-extend the 8-bit displacement d in the instruction code and add the result to HL to form an effective address (EA). Invert bit b in the memory location at the EA and place the result into the Zero flag. Then clear the specified memory bit to 0.
0 1 1 1 1 1 0 0
1 b b b
Z * – – – – 6
ZF ← (HL+C).b:(HL+C).b ← 0
Sign-extend the contents of C and add the result to HL to form an effective address (EA). Invert bit b in the memory location at the EA and
place the result into the Zero flag. Then clear the specified memory bit to 0.
1 1 1 0
0 1 1 0 1 1 0 0
1 b b b
Z * – – – – 5
SP ← SP+1:ZF ← (SP).b:(SP).b ← 0
CLR (+SP).b
Invert bit b in the memory location at (SP+1) and place the result into the Zero flag. Then clear the specified memory bit to 0.
0 1 0 0
1 1 1 1 1 1 0 0
1 b b b
Z * – – – – 6
ZF ← (PC+A).b:(PC+A).b ← 0
CLR (PC+A).bNote Sign-extend the contents of A and add the result to PC to form an effective address (EA). Invert bit b in the memory location at the EA and
place the result into the Zero flag. Then clear the specified memory bit to 0.
1 1 1 0
CLR (x).A
0 0 0 0 x x x x
x x x x 1 1 1 1
1 0 1 0 Z * – – – – 5
ZF ← (x).A:(x).A ← 0
Invert the bit specified by the low-order 3 bits of A in the memory location directly addressed by x and place the result into the Zero flag. Then
clear the specified memory bit to 0. (0x0000 ≤ x ≤ 0x00FF)
1 1 1 0
1 1 1 1
0 0 0 1 w w w w
1 0 1 0
w w w w v v v v
v v v v Z * – – – – 6
ZF ← (vw).A:(vw).A ← 0
CLR (vw).A
Invert the bit specified by the low-order 3 bits of A in the memory location directly addressed by vw and place the result into the Zero flag. Then
clear the specified memory bit to 0. (0x0000 ≤ vw ≤ 0xFFFF)
1 1 1 0
0 0 1 0 1 1 1 1
1 0 1 0
Z * – – – – 4
ZF ← (DE).A:(DE).A ← 0
CLR (DE).A
Invert the bit specified by the low-order 3 bits of A in the memory location addressed by DE and place the result into the Zero flag. Then clear
the specified memory bit to 0.
CLR (HL).A
Invert the bit specified by the low-order 3 bits of A in the memory location addressed by HL and place the result into the Zero flag. Then clear
the specified memory bit to 0.
1 1 1 0
1 1 1 0
0 0 1 1 1 1 1 1
0 1 0 0 1 1 1 1
1 0 1 0
Z * – – – – 4
1 0 1 0
Z * – – – – 4
ZF ← (HL).A:(HL).A ← 0
ZF ← (IX).A:(IX).A ← 0
CLR (IX).A
Invert the bit specified by the low-order 3 bits of A in the memory location addressed by IX and place the result into the Zero flag. Then clear the
specified memory bit to 0.
CLR (IY).A
Invert the bit specified by the low-order 3 bits of A in the memory location addressed by IY and place the result into the Zero flag. Then clear the
specified memory bit to 0.
1 1 1 0
1 1 0 1
0 1 0 1 1 1 1 1
0 1 0 0 d d d d
1 0 1 0
Z * – – – – 4
d d d d 1 1 1 1
1 0 1 0 Z * – – – – 6
ZF ← (IY).A:(IY).A ← 0
ZF ← (IX+d).A:(IX+d).A ← 0
CLR (IX+d).A
Sign-extend the 8-bit displacement d in the instruction code and add the result to IX to form an effective address (EA). Invert the bit specified by
the low-order 3 bits of A in the memory location at the EA and place the result into the Zero flag. Then clear the specified memory bit to 0.
CLR (IY+d).A
Sign-extend the 8-bit displacement d in the instruction code and add the result to IY to form an effective address (EA). Invert the bit specified by
the low-order 3 bits of A in the memory location at the EA and place the result into the Zero flag. Then clear the specified memory bit to 0.
1 1 0 1
1 1 0 1
0 1 0 1 d d d d
0 1 1 0 d d d d
d d d d 1 1 1 1
d d d d 1 1 1 1
1 0 1 0 Z * – – – – 6
1 0 1 0 Z * – – – – 6
ZF ← (IY+d).A:(IY+d).A ← 0
ZF ← (SP+d).A:(SP+d).A ← 0
CLR (SP+d).A
Sign-extend the 8-bit displacement d in the instruction code and add the result to SP to form an effective address (EA). Invert the bit specified
by the low-order 3 bits of A in the memory location at the EA and place the result into the Zero flag. Then clear the specified memory bit to 0.
CLR (HL+d).A
Sign-extend the 8-bit displacement d in the instruction code and add the result to HL to form an effective address (EA). Invert the bit specified
by the low-order 3 bits of A in the memory location at the EA and place the result into the Zero flag. Then clear the specified memory bit to 0.
1 1 0 1
1 1 1 0
0 1 1 1 d d d d
0 1 1 1 1 1 1 1
d d d d 1 1 1 1
1 0 1 0 Z * – – – – 6
1 0 1 0
Z * – – – – 6
ZF ← (HL+d).A:(HL+d).A ← 0
ZF ← (HL+C).A:(HL+C).A ← 0
CLR (HL+C).A
Sign-extend the contents of C and add the result to HL to form an effective address (EA). Invert the bit specified by the low-order 3 bits of A in
the memory location at the EA and place the result into the Zero flag. Then clear the specified memory bit to 0.
CLR (+SP).A
Invert the bit specified by the low-order 3 bits of A in the memory location at (SP+1) and place the result into the Zero flag. Then clear the specified memory bit to 0.
1 1 1 0
CLR
0 1 0 0
0 1 1 0 1 1 1 1
1 1 1 1 1 1 1 1
1 0 1 0
Z * – – – – 5
1 0 1 0
Z * – – – – 6
SP ← SP+1:ZF ← (SP).A:(SP).A ← 0
ZF ← (PC+A).A:(PC+A).A ← 0
(PC+A).ANote
Sign-extend the contents of A and add the result to PC to form an effective address (EA). Invert the bit specified by the low-order 3 bits of A in
the memory location at the EA and place the result into the Zero flag. Then clear the specified memory bit to 0.
LD CF,g.b
Load the value of bit b of 8-bit register g into the Carry flag.
Example: Assume A contains 0y01101101. Then, the instruction “LD CF, A. 4” clears CF to 0 and sets JF to 1.
1 1 1 0
RA000
1 g g g 0 1 0 1
C – * – – – 2
1 b b b
Page 57
CF ← g.b
2.4 Bit and Flag Manipulation Instructions
2.4 Bit and Flag Manipulation Instructions
TLCS-870/C1
Flag
Mnemonic
Instruction Code (Binary)
Cycle
Operation
J Z C H S V
0 1 0 1
LD CF,(x).b
LD CF,(vw).b
1 b b b x x x x
x x x x
C – * – – – 3
CF ← (x).b
Load the value of bit b in the memory location directly addressed by x into the Carry flag. (0x0000 ≤ x ≤ 0x00FF)
1 1 1 0
0 1 0 1
0 0 0 1 w w w w
1 b b b
w w w w v v v v
v v v v C – * – – – 5
CF ← (vw).b
Load the value of bit b in the memory location directly addressed by vw into the Carry flag. (0x0000 ≤ vw ≤ 0xFFFF)
1 1 1 0
0 0 1 0 0 1 0 1
1 b b b
C – * – – – 3
CF ← (DE).b
LD CF,(DE).b
Load the value of bit b in the memory location addressed by DE into the Carry flag.
1 1 1 0
0 0 1 1 0 1 0 1
1 b b b
C – * – – – 3
CF ← (HL).b
LD CF,(HL).b
Load the value of bit b in the memory location addressed by HL into the Carry flag.
1 1 1 0
0 1 0 0 0 1 0 1
C – * – – – 3
1 b b b
CF ← (IX).b
LD CF,(IX).b
Load the value of bit b in the memory location addressed by IX into the Carry flag.
1 1 1 0
0 1 0 1 0 1 0 1
1 b b b
C – * – – – 3
CF ← (IY).b
LD CF,(IY).b
Load the value of bit b in the memory location addressed by IY into the Carry flag.
1 1 0 1
LD CF,(IX+d).b
0 1 0 0 d d d d
d d d d 0 1 0 1
1 b b b C – * – – – 5
CF ← (IX+d).b
Sign-extend the 8-bit displacement d in the instruction code and add the result to IX to form an effective address (EA). Load the value of bit b in
the memory location at the EA into the Carry flag.
1 1 0 1
0 1 0 1 d d d d
d d d d 0 1 0 1
1 b b b C – * – – – 5
CF ← (IY+d).b
LD CF,(IY+d).b
Sign-extend the 8-bit displacement d in the instruction code and add the result to IY to form an effective address (EA). Load the value of bit b in
the memory location at the EA into the Carry flag.
LD CF,(SP+d).b
Sign-extend the 8-bit displacement d in the instruction code and add the result to SP to form an effective address (EA). Load the value of bit b
in the memory location at the EA into the Carry flag.
1 1 0 1
1 1 0 1
0 1 1 0 d d d d
0 1 1 1 d d d d
d d d d 0 1 0 1
d d d d 0 1 0 1
1 b b b C – * – – – 5
1 b b b C – * – – – 5
CF ← (SP+d).b
CF ← (HL+d).b
LD CF,(HL+d).b
Sign-extend the 8-bit displacement d in the instruction code and add the result to HL to form an effective address (EA). Load the value of bit b
in the memory location at the EA into the Carry flag.
LD CF,(HL+C).b
Sign-extend the contents of C and add the result to HL to form an effective address (EA). Load the value of bit b in the memory location at the
EA into the Carry flag.
1 1 1 0
1 1 1 0
0 1 1 1 0 1 0 1
0 1 1 0 0 1 0 1
C – * – – – 5
1 b b b
C – * – – – 4
1 b b b
CF ← (HL+C).b
SP ← SP+1:CF ← (SP).b
LD CF,(+SP).b
Load the value of bit b in the memory location at (SP+1) into the Carry flag.
LD
0 1 0 0
1 1 1 1 0 1 0 1
1 b b b
C – * – – – 5
CF ← (PC+A).b
CF,(PC+A).bNote
Sign-extend the contents of A and add the result to PC to form an effective address (EA). Load the value of bit b in the memory location at the
EA into the Carry flag.
LD CF,(x).A
Load the value of the bit specified by the low-order 3 bits of A in the memory location directly addressed by x into the Carry flag. (0x0000 ≤ x ≤
0x00FF)
1 1 1 0
1 1 1 0
1 1 1 1
LD CF,(vw).A
0 0 0 0 x x x x
0 0 0 1 w w w w
1 1 0 0
x x x x 1 1 1 1
w w w w v v v v
1 1 0 0 C – * – – – 4
v v v v C – * – – – 5
CF ← (x).A
CF ← (vw).A
Load the value of the bit specified by the low-order 3 bits of A in the memory location directly addressed by vw into the Carry flag. (0x0000 ≤ vw
≤ 0xFFFF)
1 1 1 0
0 0 1 0 1 1 1 1
1 1 0 0
C – * – – – 3
CF ← (DE).A
LD CF,(DE).A
Load the value of the bit specified by the low-order 3 bits of A in the memory location addressed by DE into the Carry flag.
1 1 1 0
0 0 1 1 1 1 1 1
1 1 0 0
C – * – – – 3
CF ← (HL).A
LD CF,(HL).A
Load the value of the bit specified by the low-order 3 bits of A in the memory location addressed by HL into the Carry flag.
1 1 1 0
0 1 0 0 1 1 1 1
1 1 0 0
C – * – – – 3
CF ← (IX).A
LD CF,(IX).A
Load the value of the bit specified by the low-order 3 bits of A in the memory location addressed by IX into the Carry flag.
1 1 1 0
0 1 0 1 1 1 1 1
1 1 0 0
C – * – – – 3
CF ← (IY).A
LD CF,(IY).A
Load the value of the bit specified by the low-order 3 bits of A in the memory location addressed by IY into the Carry flag.
1 1 0 1
LD CF,(IX+d).A
RA000
0 1 0 0 d d d d
d d d d 1 1 1 1
1 1 0 0 C – * – – – 5
CF ← (IX+d).A
Sign-extend the 8-bit displacement d in the instruction code and add the result to IX to form an effective address (EA). Load the value of the bit
specified by the low-order 3 bits of A in the memory location at the EA into the Carry flag.
Page 58
TLCS-870/C1
Flag
Mnemonic
Instruction Code (Binary)
Cycle
Operation
J Z C H S V
1 1 0 1
LD CF,(IY+d).A
0 1 0 1 d d d d
d d d d 1 1 1 1
1 1 0 0 C – * – – – 5
CF ← (IY+d).A
Sign-extend the 8-bit displacement d in the instruction code and add the result to IY to form an effective address (EA). Load the value of the bit
specified by the low-order 3 bits of A in the memory location at the EA into the Carry flag.
1 1 0 1
0 1 1 0 d d d d
d d d d 1 1 1 1
1 1 0 0 C – * – – – 5
CF ← (SP+d).A
LD CF,(SP+d).A
Sign-extend the 8-bit displacement d in the instruction code and add the result to SP to form an effective address (EA). Load the value of the bit
specified by the low-order 3 bits of A in the memory location at the EA into the Carry flag.
LD CF,(HL+d).A
Sign-extend the 8-bit displacement d in the instruction code and add the result to HL to form an effective address (EA). Load the value of the bit
specified by the low-order 3 bits of A in the memory location at the EA into the Carry flag.
1 1 0 1
1 1 1 0
LD CF,(HL+C).A
0 1 1 1 d d d d
0 1 1 1 1 1 1 1
d d d d 1 1 1 1
1 1 0 0 C – * – – – 5
C – * – – – 5
1 1 0 0
CF ← (HL+d).A
CF ← (HL+C).A
Sign-extend the contents of C and add the result to HL to form an effective address (EA). Load the value of the bit specified by the low-order 3
bits of A in the memory location at the EA into the Carry flag.
1 1 1 0
0 1 1 0 1 1 1 1
C – * – – – 4
1 1 0 0
SP ← SP+1:CF ← (SP).A
LD CF,(+SP).A
Load the value of the bit specified by the low-order 3 bits of A in the memory location at (SP+1) into the Carry flag.
LD CF,(PC+A).A
Note
0 1 0 0
1 1 1 0
TEST g.b#1
TEST (vw).b#1
1 1 0 0
C – * – – – 5
CF ← (PC+A).A
1 g g g 0 1 0 1
1 b b b
* – J – – – 2
JF ← g.b
Invert bit b of 8-bit register g and place the result into the Jump Status flag.
Example: Assume A contains 0y01011100. Then, the instruction “TEST A. 5” sets ZF to 1 and clears CF to 0.
0 1 0 1
TEST (x).b#1
1 1 1 1 1 1 1 1
Sign-extend the contents of A and add the result to PC to form an effective address (EA). Load the value of the bit specified by the low-order 3
bits of A in the memory location at the EA into the Carry flag.
1 b b b x x x x
x x x x
* – J – – – 3
JF ← (x).b
Invert bit b in the memory location directly addressed by x and place the result into the Jump Status flag. (0x0000 ≤ x ≤ 0x00FF)
1 1 1 0
0 1 0 1
0 0 0 1 w w w w
1 b b b
w w w w v v v v
v v v v * – J – – – 5
JF ← (vw).b
Invert bit b in the memory location directly addressed by vw and place the result into the Jump Status flag. (0x0000 ≤ vw ≤ 0xFFFF)
TEST (DE).b#1
TEST (HL).b#1
TEST (IX).b#1
TEST (IY).b#1
1 1 1 0
1 b b b
* – J – – – 3
JF ← (DE).b
1 1 1 0
0 0 1 1 0 1 0 1
1 b b b
* – J – – – 3
JF ← (HL).b
Invert bit b in the memory location addressed by HL and place the result into the Jump Status flag.
1 1 1 0
0 1 0 0 0 1 0 1
1 b b b
* – J – – – 3
JF ← (IX).b
Invert bit b in the memory location addressed by IX and place the result into the Jump Status flag.
1 1 1 0
0 1 0 1 0 1 0 1
1 b b b
* – J – – – 3
JF ← (IY).b
Invert bit b in the memory location addressed by IY and place the result into the Jump Status flag.
1 1 0 1
TEST (IX+d).b#1
0 0 1 0 0 1 0 1
Invert bit b in the memory location addressed by DE and place the result into the Jump Status flag.
0 1 0 0 d d d d
d d d d 0 1 0 1
1 b b b * – J – – – 5
JF ← (IX+d).b
Sign-extend the 8-bit displacement d in the instruction code and add the result to IX to form an effective address (EA). Invert bit b in the memory location at the EA and place the result into the Jump Status flag.
1 1 0 1
0 1 0 1 d d d d
d d d d 0 1 0 1
1 b b b * – J – – – 5
JF ← (IY+d).b
TEST (IY+d).b#1
Sign-extend the 8-bit displacement d in the instruction code and add the result to IY to form an effective address (EA). Invert bit b in the memory location at the EA and place the result into the Jump Status flag.
TEST (SP+d).b#1
Sign-extend the 8-bit displacement d in the instruction code and add the result to SP to form an effective address (EA). Invert bit b in the memory location at the EA and place the result into the Jump Status flag.
1 1 0 1
1 1 0 1
TEST (HL+d).b#1
0 1 1 0 d d d d
0 1 1 1 d d d d
d d d d 0 1 0 1
d d d d 0 1 0 1
1 b b b * – J – – – 5
1 b b b * – J – – – 5
JF ← (SP+d).b
JF ← (HL+d).b
Sign-extend the 8-bit displacement d in the instruction code and add the result to HL to form an effective address (EA). Invert bit b in the memory location at the EA and place the result into the Jump Status flag.
1 1 1 0
0 1 1 1 0 1 0 1
1 b b b
* – J – – – 5
JF ← (HL+C).b
TEST (HL+C).b#1 Sign-extend the contents of C and add the result to HL to form an effective address (EA). Invert bit b in the memory location at the EA and
place the result into the Jump Status flag.
TEST (+SP).b#1
1 1 1 0
0 1 1 0 0 1 0 1
1 b b b
* – J – – – 4
SP ← SP+1:JF ← (SP).b
Invert bit b in the memory location at (SP+1) and place the result into the Jump Status flag.
0 1 0 0
1 1 1 1 0 1 0 1
1 b b b
* – J – – – 5
JF ← (PC+A).b
TEST
(PC+A).b#1Note
RA000
Sign-extend the contents of A and add the result to PC to form an effective address (EA). Invert bit b in the memory location at the EA and
place the result into the Jump Status flag.
Page 59
2.4 Bit and Flag Manipulation Instructions
2.4 Bit and Flag Manipulation Instructions
TLCS-870/C1
Flag
Mnemonic
Instruction Code (Binary)
Cycle
Operation
J Z C H S V
1 1 1 0
TEST (x).A#1
0 0 0 0 x x x x
x x x x 1 1 1 1
1 1 0 0 * – J – – – 4
JF ← (x).A
Invert the bit specified by the low-order 3 bits of A in the memory location directly addressed by x and place the result into the Jump Status flag.
(0x0000 ≤ x ≤ 0x00FF)
1 1 1 0
1 1 1 1
TEST (vw).A#1
0 0 0 1 w w w w
1 1 0 0
w w w w v v v v
v v v v * – J – – – 5
JF ← (vw).A
Invert the bit specified by the low-order 3 bits of A in the memory location directly addressed by vw and place the result into the Jump Status
flag. (0x0000 ≤ vw ≤ 0xFFFF)
TEST (DE).A#1
TEST (HL).A#1
TEST (IX).A#1
TEST (IY).A#1
1 1 1 0
1 1 1 0
* – J – – – 3
JF ← (DE).A
0 0 1 1 1 1 1 1
1 1 0 0
* – J – – – 3
JF ← (HL).A
1 1 1 0
0 1 0 0 1 1 1 1
1 1 0 0
* – J – – – 3
JF ← (IX).A
Invert the bit specified by the low-order 3 bits of A in the memory location addressed by IX and place the result into the Jump Status flag.
1 1 1 0
0 1 0 1 1 1 1 1
1 1 0 0
* – J – – – 3
JF ← (IY).A
Invert the bit specified by the low-order 3 bits of A in the memory location addressed by IY and place the result into the Jump Status flag.
0 1 0 0 d d d d
d d d d 1 1 1 1
1 1 0 0 * – J – – – 5
JF ← (IX+d).A
Sign-extend the 8-bit displacement d in the instruction code and add the result to IX to form an effective address (EA). Invert the bit specified by
the low-order 3 bits of A in the memory location at the EA and place the result into the Jump Status flag.
1 1 0 1
TEST (IY+d).A#1
1 1 0 0
Invert the bit specified by the low-order 3 bits of A in the memory location addressed by HL and place the result into the Jump Status flag.
1 1 0 1
TEST (IX+d).A#1
0 0 1 0 1 1 1 1
Invert the bit specified by the low-order 3 bits of A in the memory location addressed by DE and place the result into the Jump Status flag.
0 1 0 1 d d d d
d d d d 1 1 1 1
1 1 0 0 * – J – – – 5
JF ← (IY+d).A
Sign-extend the 8-bit displacement d in the instruction code and add the result to IY to form an effective address (EA). Invert the bit specified by
the low-order 3 bits of A in the memory location at the EA and place the result into the Jump Status flag.
1 1 0 1
0 1 1 0 d d d d
d d d d 1 1 1 1
1 1 0 0 * – J – – – 5
JF ← (SP+d).A
TEST (SP+d).A#1 Sign-extend the 8-bit displacement d in the instruction code and add the result to SP to form an effective address (EA). Invert the bit specified
by the low-order 3 bits of A in the memory location at the EA and place the result into the Jump Status flag.
1 1 0 1
0 1 1 1 d d d d
d d d d 1 1 1 1
1 1 0 0 * – J – – – 5
JF ← (HL+d).A
TEST (HL+d).A#1 Sign-extend the 8-bit displacement d in the instruction code and add the result to HL to form an effective address (EA). Invert the bit specified
by the low-order 3 bits of A in the memory location at the EA and place the result into the Jump Status flag.
1 1 1 0
0 1 1 1 1 1 1 1
1 1 0 0
* – J – – – 5
JF ← (HL+C).A
TEST (HL+C).A#1 Sign-extend the contents of C and add the result to HL to form an effective address (EA). Invert the bit specified by the low-order 3 bits of A in
the memory location at the EA and place the result into the Jump Status flag.
TEST (+SP).A#1
1 1 1 0
0 1 1 0 1 1 1 1
1 1 0 0
* – J – – – 4
SP ← SP+1:JF ← (SP).A
Invert the bit specified by the low-order 3 bits of A in the memory location at (SP+1) and place the result into the Jump Status flag.
0 1 0 0
1 1 1 1 1 1 1 1
1 1 0 0
* – J – – – 5
JF ← (PC+A).A
TEST
(PC+A).A#1Note
Sign-extend the contents of A and add the result to PC to form an effective address (EA). Invert the bit specified by the low-order 3 bits of A in
the memory location at the EA and place the result into the Jump Status flag.
LD g.b,CF
Store the contents of the Carry flag into bit b of 8-bit register g.
Example: Assume A contains 0x15 and CF is set. After executing the instruction “LD A. 5, CF”, A has 0x35; CF is not affected.
1 1 1 0
1 1 1 0
LD (x).b,CF
LD (vw).b,CF
1 g g g 1 1 1 0
0 0 0 0 x x x x
1 b b b
1 – – – – – 2
x x x x 1 1 1 0
1 b b b 1 – – – – – 5
g.b ← CF
(x).b ← CF
Store the contents of the Carry flag into bit b in the memory location directly addressed by x. (0x0000 ≤ x ≤ 0x00FF)
1 1 1 0
1 1 1 0
0 0 0 1 w w w w
1 b b b
w w w w v v v v
v v v v 1 – – – – – 6
(vw).b ← CF
Store the contents of the Carry flag into bit b in the memory location directly addressed by vw. (0x0000 ≤ vw ≤ 0xFFFF)
1 1 1 0
0 0 1 0 1 1 1 0
1 b b b
1 – – – – – 4
(DE).b ← CF
LD (DE).b,CF
Store the contents of the Carry flag into bit b in the memory location addressed by DE.
1 1 1 0
0 0 1 1 1 1 1 0
1 b b b
1 – – – – – 4
(HL).b ← CF
LD (HL).b,CF
Store the contents of the Carry flag into bit b in the memory location addressed by HL
1 1 1 0
0 1 0 0 1 1 1 0
1 b b b
1 – – – – – 4
(IX).b ← CF
LD (IX).b,CF
Store the contents of the Carry flag into bit b in the memory location addressed by IX.
1 1 1 0
0 1 0 1 1 1 1 0
1 b b b
1 – – – – – 4
LD (IY).b,CF
Store the contents of the Carry flag into bit b in the memory location addressed by IY.
RA000
Page 60
(IY).b ← CF
TLCS-870/C1
Flag
Mnemonic
Instruction Code (Binary)
Cycle
Operation
J Z C H S V
1 1 0 1
LD (IX+d).b,CF
0 1 0 0 d d d d
d d d d 1 1 1 0
1 b b b 1 – – – – – 6
(IX+d).b ← CF
Sign-extend the 8-bit displacement d in the instruction code and add the result to IX to form an effective address (EA). Store the contents of the
Carry flag into bit b in the memory location at the EA.
1 1 0 1
0 1 0 1 d d d d
d d d d 1 1 1 0
1 b b b 1 – – – – – 6
(IY+d).b ← CF
LD (IY+d).b,CF
Sign-extend the 8-bit displacement d in the instruction code and add the result to IY to form an effective address (EA). Store the contents of the
Carry flag into bit b in the memory location at the EA.
LD (SP+d).b,CF
Sign-extend the 8-bit displacement d in the instruction code and add the result to SP to form an effective address (EA). Store the contents of
the Carry flag into bit b in the memory location at the EA.
1 1 0 1
1 1 0 1
0 1 1 0 d d d d
0 1 1 1 d d d d
d d d d 1 1 1 0
d d d d 1 1 1 0
1 b b b 1 – – – – – 6
1 b b b 1 – – – – – 6
(SP+d).b ← CF
(HL+d).b ← CF
LD (HL+d).b,CF
Sign-extend the 8-bit displacement d in the instruction code and add the result to HL to form an effective address (EA). Store the contents of
the Carry flag into bit b in the memory location at the EA.
LD (HL+C).b,CF
Sign-extend the contents of C and add the result to HL to form an effective address (EA). Store the contents of the Carry flag into bit b in the
memory location at the EA.
1 1 1 0
1 1 1 0
0 1 1 1 1 1 1 0
0 1 1 0 1 1 1 0
1 b b b
1 – – – – – 6
1 b b b
1 – – – – – 5
(HL+C).b ← CF
SP ← SP+1:(SP).b ← CF
LD (+SP).b,CF
Store the contents of the Carry flag into bit b in the memory location at (SP+1)
LD
0 1 0 0
1 1 1 1 1 1 1 0
1 b b b
1 – – – – – 6
(PC+A).b ← CF
(PC+A).b,CFNote
Sign-extend the contents of A and add the result to PC to form an effective address (EA). Store the contents of the Carry flag into bit b in the
memory location at the EA.
LD (x).A,CF
Store the contents of the Carry flag into the bit specified by the low-order 3 bits of A in the memory location directly addressed by x. (0x0000 ≤
1 1 1 0
0 0 0 0 x x x x
x x x x 1 1 1 1
0 0 1 1 1 – – – – – 5
(x).A ← CF
x ≤ 0x00FF)
1 1 1 0
1 1 1 1
0 0 0 1 w w w w
0 0 1 1
w w w w v v v v
v v v v 1 – – – – – 6
(vw).A ← CF
LD (vw).A,CF
Store the contents of the Carry flag into the bit specified by the low-order 3 bits of A in the memory location directly addressed by vw. (0x0000
≤ vw ≤ 0xFFFF)
1 1 1 0
0 0 1 0 1 1 1 1
0 0 1 1
1 – – – – – 4
(DE).A ← CF
LD (DE).A,CF
Store the contents of the Carry flag into the bit specified by the low-order 3 bits of A in the memory location addressed by DE.
1 1 1 0
0 0 1 1 1 1 1 1
0 0 1 1
1 – – – – – 4
(HL).A ← CF
LD (HL).A,CF
Store the contents of the Carry flag into the bit specified by the low-order 3 bits of A in the memory location addressed by HL.
1 1 1 0
0 1 0 0 1 1 1 1
0 0 1 1
1 – – – – – 4
(IX).A ← CF
LD (IX).A,CF
Store the contents of the Carry flag into the bit specified by the low-order 3 bits of A in the memory location addressed by IX.
1 1 1 0
0 1 0 1 1 1 1 1
0 0 1 1
1 – – – – – 4
(IY).A ← CF
LD (IY).A,CF
Store the contents of the Carry flag into the bit specified by the low-order 3 bits of A in the memory location addressed by IY.
1 1 0 1
LD (IX+d).A,CF
0 1 0 0 d d d d
d d d d 1 1 1 1
0 0 1 1 1 – – – – – 6
(IX+d).A ← CF
Sign-extend the 8-bit displacement d in the instruction code and add the result to IX to form an effective address (EA). Store the contents of the
Carry flag into the bit specified by the low-order 3 bits of A in the memory location at the EA.
1 1 0 1
0 1 0 1 d d d d
d d d d 1 1 1 1
0 0 1 1 1 – – – – – 6
(IY+d).A ← CF
LD (IY+d).A,CF
Sign-extend the 8-bit displacement d in the instruction code and add the result to IY to form an effective address (EA). Store the contents of the
Carry flag into the bit specified by the low-order 3 bits of A in the memory location at the EA.
LD (SP+d).A,CF
Sign-extend the 8-bit displacement d in the instruction code and add the result to SP to form an effective address (EA). Store the contents of
the Carry flag into the bit specified by the low-order 3 bits of A in the memory location at the EA.
1 1 0 1
1 1 0 1
0 1 1 0 d d d d
0 1 1 1 d d d d
d d d d 1 1 1 1
d d d d 1 1 1 1
0 0 1 1 1 – – – – – 6
0 0 1 1 1 – – – – – 6
(SP+d).A ← CF
(HL+d).A ← CF
LD (HL+d).A,CF
Sign-extend the 8-bit displacement d in the instruction code and add the result to HL to form an effective address (EA). Store the contents of
the Carry flag into the bit specified by the low-order 3 bits of A in the memory location at the EA.
LD (HL+C).A,CF
Sign-extend the contents of C and add the result to HL to form an effective address (EA). Store the contents of the Carry flag into the bit specified by the low-order 3 bits of A in the memory location at the EA.
1 1 1 0
1 1 1 0
0 1 1 1 1 1 1 1
0 1 1 0 1 1 1 1
0 0 1 1
1 – – – – – 6
0 0 1 1
1 – – – – – 5
(HL+C).A ← CF
SP ← SP+1:(SP).A ← CF
LD (+SP).A,CF
Store the contents of the Carry flag into the bit specified by the low-order 3 bits of A in the memory location at (SP+1).
RA000
Page 61
2.4 Bit and Flag Manipulation Instructions
2.4 Bit and Flag Manipulation Instructions
TLCS-870/C1
Flag
Mnemonic
Instruction Code (Binary)
Cycle
Operation
J Z C H S V
LD
(PC+A).A,CFNote
0 1 0 0
1 1 1 1 1 1 1 1
0 0 1 1
1 – – – – – 6
(PC+A).A ← CF
Sign-extend the contents of A and add the result to PC to form an effective address (EA). Store the contents of the Carry flag into the bit specified by the low-order 3 bits of A in the memory location at the EA.
1 1 1 0
1 g g g 1 1 1 0
0 b b b
Z * – – – – 3
ZF ← g.b:g.b ← g.b
CPL g.b
Invert bit b of 8-bit register g and place the result into the Zero flag. Also write back the result into the specified register bit of g.
Example: Assume A contains 0x3C. After executing the instruction “CPL A. 3”, A has 0x34; and ZF is cleared to 1.
CPL (x).b
Invert bit b in the memory location directly addressed by x and place the result into the Zero flag. Also write back the result into the specified
1 1 1 0
0 0 0 0 x x x x
x x x x 1 1 1 0
0 b b b Z * – – – – 5
ZF ← (x).b:(x).b ← (x).b
memory bit. (0x0000 ≤ x ≤ 0x00FF)
1 1 1 0
1 1 1 0
0 0 0 1 w w w w
0 b b b
w w w w v v v v
v v v v Z * – – – – 6
ZF ← (vw).b:(vw).b ← (vw).b
CPL (vw).b
Invert bit b in the memory location directly addressed by vw and place the result into the Zero flag. Also write back the result into the specified
memory bit. (0x0000 ≤ vw ≤ 0xFFFF)
1 1 1 0
CPL (DE).b
0 0 1 0 1 1 1 0
0 b b b
Z * – – – – 4
ZF ← (DE).b:(DE).b ← (DE).b
Invert bit b in the memory location addressed by DE and place the result into the Zero flag. Also write back the result into the specified memory
bit.
1 1 1 0
0 0 1 1 1 1 1 0
0 b b b
Z * – – – – 4
ZF ← (HL).b:(HL).b ← (HL).b
CPL (HL).b
Invert bit b in the memory location addressed by HL and place the result into the Zero flag. Also write back the result into the specified memory
bit.
CPL (IX).b
Invert bit b in the memory location addressed by IX and place the result into the Zero flag. Also write back the result into the specified memory
bit.
1 1 1 0
1 1 1 0
0 1 0 0 1 1 1 0
0 1 0 1 1 1 1 0
0 b b b
Z * – – – – 4
0 b b b
Z * – – – – 4
ZF ← (IX).b:(IX).b ← (IX).b
ZF ← (IY).b:(IY).b ← (IY).b
CPL (IY).b
Invert bit b in the memory location addressed by IY and place the result into the Zero flag. Also write back the result into the specified memory
bit.
CPL (IX+d).b
Sign-extend the 8-bit displacement d in the instruction code and add the result to IX to form an effective address (EA). Invert bit b in the memory location at the EA and place the result into the Zero flag. Also write back the result into the specified memory bit.
1 1 0 1
1 1 0 1
0 1 0 0 d d d d
0 1 0 1 d d d d
d d d d 1 1 1 0
d d d d 1 1 1 0
0 b b b Z * – – – – 6
0 b b b Z * – – – – 6
ZF ← (IX+d).b:(IX+d).b ← (IX+d).b
ZF ← (IY+d).b:(IY+d).b ← (IY+d).b
CPL (IY+d).b
Sign-extend the 8-bit displacement d in the instruction code and add the result to IY to form an effective address (EA). Invert bit b in the memory location at the EA and place the result into the Zero flag. Also write back the result into the specified memory bit.
CPL (SP+d).b
Sign-extend the 8-bit displacement d in the instruction code and add the result to SP to form an effective address (EA). Invert bit b in the memory location at the EA and place the result into the Zero flag. Also write back the result into the specified memory bit.
1 1 0 1
1 1 0 1
0 1 1 0 d d d d
0 1 1 1 d d d d
d d d d 1 1 1 0
d d d d 1 1 1 0
0 b b b Z * – – – – 6
0 b b b Z * – – – – 6
ZF ← (SP+d).b:(SP+d).b ← (SP+d).b
ZF ← (HL+d).b:(HL+d).b ← (HL+d).b
CPL (HL+d).b
Sign-extend the 8-bit displacement d in the instruction code and add the result to HL to form an effective address (EA). Invert bit b in the memory location at the EA and place the result into the Zero flag. Also write back the result into the specified memory bit.
CPL (HL+C).b
Sign-extend the contents of C and add the result to HL to form an effective address (EA). Invert bit b in the memory location at the EA and
place the result into the Zero flag. Also write back the result into the specified memory bit.
1 1 1 0
1 1 1 0
0 1 1 1 1 1 1 0
0 1 1 0 1 1 1 0
0 b b b
Z * – – – – 6
0 b b b
Z * – – – – 5
ZF ← (HL+C).b:(HL+C).b ← (HL+C).b
SP ← SP+1:ZF ← (SP).b:(SP).b ← (SP).b
CPL (+SP).b
Invert bit b in the memory location at (SP+1) and place the result into the Zero flag. Also write back the result into the specified memory bit.
0 1 0 0
1 1 1 1 1 1 1 0
0 b b b
Z * – – – – 6
ZF ← (PC+A).b:(PC+A).b ← (PC+A).b
CPL (PC+A).bNote Sign-extend the contents of A and add the result to PC to form an effective address (EA). Invert bit b in the memory location at the EA and
place the result into the Zero flag. Also write back the result into the specified memory bit.
1 1 1 0
CPL (x).A
0 0 0 0 x x x x
x x x x 1 1 1 1
1 0 1 1 Z * – – – – 5
ZF ← (x).A:(x).A ← (x).A
Invert the bit specified by the low-order 3 bits of A in the memory location directly addressed by x, place the result into the Zero flag, and also
write back the result into the specified memory bit. (0x0000 ≤ x ≤ 0x00FF)
1 1 1 0
1 1 1 1
0 0 0 1 w w w w
1 0 1 1
w w w w v v v v
v v v v Z * – – – – 6
ZF ← (vw).A:(vw).A ← (vw).A
CPL (vw).A
Invert the bit specified by the low-order 3 bits of A in the memory location directly addressed by vw, place the result into the Zero flag, and also
write back the result into the specified memory bit. (0x0000 ≤ vw ≤ 0xFFFF)
1 1 1 0
CPL (DE).A
RA000
0 0 1 0 1 1 1 1
1 0 1 1
Z * – – – – 4
ZF ← (DE).A:(DE).A ← (DE).A
Invert the bit specified by the low-order 3 bits of A in the memory location addressed by DE, place the result into the Zero flag, and also write
back the result into the specified memory bit.
Page 62
TLCS-870/C1
Flag
Mnemonic
Instruction Code (Binary)
Cycle
Operation
J Z C H S V
1 1 1 0
CPL (HL).A
0 0 1 1 1 1 1 1
1 0 1 1
Z * – – – – 4
ZF ← (HL).A:(HL).A ← (HL).A
Invert the bit specified by the low-order 3 bits of A in the memory location addressed by HL, place the result into the Zero flag, and also write
back the result into the specified memory bit.
1 1 1 0
0 1 0 0 1 1 1 1
1 0 1 1
Z * – – – – 4
ZF ← (IX).A:(IX).A ← (IX).A
CPL (IX).A
Invert the bit specified by the low-order 3 bits of A in the memory location addressed by IX, place the result into the Zero flag, and also write
back the result into the specified memory bit.
CPL (IY).A
Invert the bit specified by the low-order 3 bits of A in the memory location addressed by IY, place the result into the Zero flag, and also write
back the result into the specified memory bit.
1 1 1 0
1 1 0 1
CPL (IX+d).A
d d d d 1 1 1 1
1 0 1 1 Z * – – – – 6
ZF ← (IY).A:(IY).A ← (IY).A
ZF ← (IX+d).A:(IX+d).A ← (IX+d).A
0 1 0 1 d d d d
d d d d 1 1 1 1
1 0 1 1 Z * – – – – 6
ZF ← (IY+d).A:(IY+d).A ← (IY+d).A
0 1 1 0 d d d d
d d d d 1 1 1 1
1 0 1 1 Z * – – – – 6
ZF ← (SP+d).A:(SP+d).A ← (SP+d).A
Sign-extend the 8-bit displacement d in the instruction code and add the result to SP to form an effective address (EA). Invert the bit specified
by the low-order 3 bits of A in the memory location at the EA, place the result into the Zero flag, and also write back the result into the specified
memory bit.
1 1 0 1
CPL (HL+d).A
Z * – – – – 4
Sign-extend the 8-bit displacement d in the instruction code and add the result to IY to form an effective address (EA). Invert the bit specified by
the low-order 3 bits of A in the memory location at the EA, place the result into the Zero flag, and also write back the result into the specified
memory bit.
1 1 0 1
CPL (SP+d).A
0 1 0 0 d d d d
1 0 1 1
Sign-extend the 8-bit displacement d in the instruction code and add the result to IX to form an effective address (EA). Invert the bit specified by
the low-order 3 bits of A in the memory location at the EA, place the result into the Zero flag, and also write back the result into the specified
memory bit.
1 1 0 1
CPL (IY+d).A
0 1 0 1 1 1 1 1
0 1 1 1 d d d d
d d d d 1 1 1 1
1 0 1 1 Z * – – – – 6
ZF ← (HL+d).A:(HL+d).A ← (HL+d).A
Sign-extend the 8-bit displacement d in the instruction code and add the result to HL to form an effective address (EA). Invert the bit specified
by the low-order 3 bits of A in the memory location at the EA, place the result into the Zero flag, and also write back the result into the specified
memory bit.
1 1 1 0
0 1 1 1 1 1 1 1
1 0 1 1
Z * – – – – 6
ZF ← (HL+C).A:(HL+C).A ← (HL+C).A
CPL (HL+C).A
Sign-extend the contents of C and add the result to HL to form an effective address (EA). Invert the bit specified by the low-order 3 bits of A in
the memory location at the EA, place the result into the Zero flag, and also write back the result into the specified memory bit.
CPL (+SP).A
Invert the bit specified by the low-order 3 bits of A in the memory location at (SP+1), place the result into the Zero flag, and also write back the
result into the specified memory bit.
1 1 1 0
0 1 0 0
0 1 1 0 1 1 1 1
1 1 1 1 1 1 1 1
1 0 1 1
Z * – – – – 5
1 0 1 1
Z * – – – – 6
SP ← SP+1:ZF ← (SP).A:(SP).A ← (SP).A
ZF ← (PC+A).A:(PC+A).A ← (PC+A).A
CPL (PC+A).ANote Sign-extend the contents of A and add the result to PC to form an effective address (EA). Invert the bit specified by the low-order 3 bits of A in
the memory location at the EA, place the result into the Zero flag, and also write back the result into the specified memory bit.
1 1 1 0
1 g g g 0 1 0 1
0 b b b
C – * – – – 2
CF ← CF
^
g.b
XOR CF,g.b
Combine the contents of bit b of 8-bit register g with that of the Carry flag in an exclusive-OR operation and place the result into the Carry flag.
Example: Assume A contains 0x58 and CF is set. After executing the instruction “XOR CF, A. 3”, A remains unchanged; CF is cleared to 0; and
JF is set to 1.
1 1 1 0
0 0 0 0 x x x x
x x x x 0 1 0 1
0 b b b C – * – – – 4
XOR CF,(x).b
CF ← CF
^
(x).b
Combine the contents of bit b in the memory location directly addressed by x with that of the Carry flag in an exclusive-OR operation and place
the result into the Carry flag. (0x0000 ≤ x ≤ 0x00FF)
1 1 1 0
0 1 0 1
0 0 0 1 w w w w
0 b b b
w w w w v v v v
v v v v C – * – – –
5
CF ← CF
^
(vw).b
XOR CF,(vw).b
Combine the contents of bit b in the memory location directly addressed by vw with that of the Carry flag in an exclusive-OR operation and
place the result into the Carry flag. (0x0000 ≤ vw ≤ 0xFFFF)
1 1 1 0
XOR CF,(DE).b
RA000
0 0 1 0 0 1 0 1
C – * – – – 3
0 b b b
CF ← CF ^ (DE).b
Combine the contents of bit b in the memory location addressed by DE with that of the Carry flag in an exclusive-OR operation and place the
result into the Carry flag.
Page 63
2.4 Bit and Flag Manipulation Instructions
2.4 Bit and Flag Manipulation Instructions
TLCS-870/C1
Flag
Mnemonic
Instruction Code (Binary)
Cycle
Operation
J Z C H S V
1 1 1 0
0 0 1 1 0 1 0 1
C – * – – – 3
0 b b b
XOR CF,(HL).b
CF ← CF
^
(HL).b
Combine the contents of bit b in the memory location addressed by HL with that of the Carry flag in an exclusive-OR operation and place the
result into the Carry flag.
1 1 1 0
0 1 0 0 0 1 0 1
C – * – – – 3
0 b b b
XOR CF,(IX).b
CF ← CF
^
(IX).b
Combine the contents of bit b in the memory location addressed by IX with that of the Carry flag in an exclusive-OR operation and place the
result into the Carry flag.
1 1 1 0
0 1 0 1 0 1 0 1
0 b b b
C – * – – – 3
XOR CF,(IY).b
CF ← CF
^
(IY).b
Combine the contents of bit b in the memory location addressed by IY with that of the Carry flag in an exclusive-OR operation and place the
result into the Carry flag.
1 1 0 1
0 1 0 0 d d d d
d d d d 0 1 0 1
0 b b b C – * – – – 5
XOR CF,(IX+d).b
CF ← CF
^
(IX+d).b
Sign-extend the 8-bit displacement d in the instruction code and add the result to IX to form an effective address (EA). Combine the contents of
bit b in the memory location at the EA with that of the Carry flag in an exclusive-OR operation and place the result into the Carry flag.
1 1 0 1
0 1 0 1 d d d d
d d d d 0 1 0 1
0 b b b C – * – – – 5
XOR CF,(IY+d).b
CF ← CF
^
(IY+d).b
Sign-extend the 8-bit displacement d in the instruction code and add the result to IY to form an effective address (EA). Combine the contents of
bit b in the memory location at the EA with that of the Carry flag in an exclusive-OR operation and place the result into the Carry flag.
1 1 0 1
0 1 1 0 d d d d
d d d d 0 1 0 1
0 b b b C – * – – – 5
XOR CF,(SP+d).b
CF ← CF
^
(SP+d).b
Sign-extend the 8-bit displacement d in the instruction code and add the result to SP to form an effective address (EA). Combine the contents
of bit b in the memory location at the EA with that of the Carry flag in an exclusive-OR operation and place the result into the Carry flag.
1 1 0 1
0 1 1 1 d d d d
d d d d 0 1 0 1
0 b b b C – * – – – 5
XOR CF,(HL+d).b
CF ← CF
^
(HL+d).b
Sign-extend the 8-bit displacement d in the instruction code and add the result to HL to form an effective address (EA). Combine the contents
of bit b in the memory location at the EA with that of the Carry flag in an exclusive-OR operation and place the result into the Carry flag.
1 1 1 0
0 1 1 1 0 1 0 1
C – * – – – 5
0 b b b
XOR CF,(HL+C).b
CF ← CF
^
(HL+C).b
Sign-extend the contents of C and add the result to HL to form an effective address (EA). Combine the contents of bit b in the memory location
at the EA with that of the Carry flag in an exclusive-OR operation and place the result into the Carry flag.
1 1 1 0
0 1 1 0 0 1 0 1
C – * – – – 4
0 b b b
XOR CF,(+SP).b
SP ← SP+1:CF ← CF
^
(SP).b
Combine the contents of bit b in the memory location at (SP+1) with that of the Carry flag in an exclusive-OR operation and place the result into
the Carry flag.
0 1 0 0
1 1 1 1 0 1 0 1
0 b b b
C – * – – – 5
XOR
CF,(PC+A).bNote
CF ← CF
^
(PC+A).b
Sign-extend the contents of A and add the result to PC to form an effective address (EA). Combine the contents of bit b in the memory location
at the EA with that of the Carry flag in an exclusive-OR operation and place the result into the Carry flag.
0 0 0 0
0 1 0 1
0 – 1 – – – 1
CF ← 1
1 – 0 – – – 1
CF ← 0
* – * – – – 1
JF ← CF:CF ← CF
SET CF
Set the Carry flag to 1.
0 0 0 0
0 1 0 0
CLR CF
Clear the Carry flag to 0.
0 0 0 0
CPL CF
RA000
0 1 1 0
Place the value of the Carry flag into the Jump Status flag. Then invert the Carry flag bit.
Example: Assume CF is cleared. Then, this instruction clears JF to 0 and sets CF to 1.
Page 64
TLCS-870/C1
Flag
Mnemonic
Instruction Code (Binary)
Cycle
Operation
J Z C H S V
1 1 0 0
DI#1
1 0 0 0 0 0 1 1
1 0 1 0
Z * – – – – 4
ZF ← IMF:IMF ← 0
Invert the Interrupt Master Enable flag bit and place the result into the Zero flag. Then clear the Interrupt Master Enable flag to 0 (which disables the maskable interrupts).
1 1 0 0
EI#1
0 0 0 0 0 0 1 1
1 0 1 0
Z * – – – – 4
ZF ← IMF:IMF ← 1
Invert the Interrupt Master Enable flag bit and place the result into the Zero flag. Then set the Interrupt Master Enable flag to 1 (which enables
the maskable interrupts).
#1
Assembler instructions
Note: There are restrictions on instructions that uses the operand (PC + A). For more details, see "1.4 Addressing Mode".
RA000
Page 65
2.4 Bit and Flag Manipulation Instructions
2.4 Bit and Flag Manipulation Instructions
RA000
TLCS-870/C1
Page 66
TLCS-870/C1
2.5 Jump Instructions
Flag
Mnemonic
Instruction Code (Binary)
Cycle
Operation
J Z C H S V
1 0 0 d
d d d d
1 – – – – – 4/2(t/f)
if JF=1 then PC ← PC+d else null
If JF is set, sign-extend the 5-bit displacement d in the instruction code (-16 to +15) and add the result to PC (2 plus the address of the current JRS
JRS T,$+2+d instruction) to form an effective address (EA). Then, jump to the EA. (Latency = 4 clock cycles)
If JF is cleared, set JF to 1 and skip to the next instruction. (Latency = 2 clock cycles).
Example: Assume JF is set. Then, the instruction “JRS T, $+9” at address 0xC134 causes a jump to the address 0xC13D.
1 0 1 d
JRS F,$+2+d
JR Z,$+2+d
1 1 1 0 d d d d
d d d d
1 – – – – – 4/2(t/f)
if JF=1 then PC ← PC+d else null
1 1 1 1 d d d d
d d d d
1 – – – – – 4/2(t/f)
if JF=0 then PC ← PC+d else null
If JF is cleared, sign-extend the 8-bit displacement d in the instruction code (-128 to +127) and add the result to PC to form an effective address
(EA). Then, jump to the EA. (Latency = 4 clock cycles)
If JF is set, just skip to the next instruction. (Latency = 2 clock cycles)
1 1 0 1
JR
EQ,$+2+d/
if JF=0 then PC ← PC+d else null
If JF is set, sign-extend the 8-bit displacement d in the instruction code (-128 to +127) and add the result to PC (2 plus the address of the current JR
instruction) to form an effective address (EA). Then, jump to the EA. (Latency = 4 clock cycles)
If JF is cleared, set JF to 1 and skip to the next instruction. (Latency = 2 clock cycles)
Example: Assume JF is set. Then, the instruction “JR T, $+0xF6” at address 0xC134 causes a jump to the address 0xC12A.
1 1 0 1
JR F,$+2+d
1 – – – – – 4/2(t/f)
If JF is cleared, sign-extend the 5-bit displacement d in the instruction code (-16 to +15) and add the result to PC (2 plus the address of the current
JRS instruction) to form an effective address (EA). Then, jump to the EA. (Latency = 4 clock cycles)
If JF is set, just skip to the next instruction. (Latency = 2 clock cycles)
1 1 0 1
JR T,$+2+d
d d d d
1 0 0 0 d d d d
d d d d
1 – – – – – 4/2(t/f)
if ZF=1 then PC ← PC+d else null
If ZF is set, sign-extend the 8-bit displacement d in the instruction code (-128 to +127) and add the result to PC to form an effective address (EA).
Then, jump to the EA. (Latency = 4 clock cycles)
If ZF is cleared, set JF to 1 and skip to the next instruction. (Latency = 2 clock cycles)
1 1 0 1
1 0 0 1 d d d d
d d d d
1 – – – – – 4/2(t/f)
JR
NE,$+2+d/
if ZF=0 then PC ← PC+d else null
If ZF is cleared, sign-extend the 8-bit displacement d in the instruction code (-128 to +127) and add the result to PC to form an effective address
(EA). Then, jump to the EA. (Latency = 4 clock cycles)
JR NZ,$+2+d
If ZF is set, set JF to 1 and skip to the next instruction. (Latency = 2 clock cycles)
1 1 0 1
JR
CS,$+2+d/
JR LT,$+2+d
1 0 1 0 d d d d
d d d d
1 – – – – – 4/2(t/f)
if CF=1 then PC ← PC+d else null
If CF is set, sign-extend the 8-bit displacement d in the instruction code (-128 to +127) and add the result to PC to form an effective address (EA).
Then, jump to the EA. (Latency = 4 clock cycles)
If CF is cleared, set JF to 1 and skip to the next instruction. (Latency = 2 clock cycles)
1 1 0 1
1 0 1 1 d d d d
d d d d
1 – – – – – 4/2(t/f)
JR
CC,$+2+d/
if CF=0 then PC ← PC+d else null
If CF is cleared, sign-extend the 8-bit displacement d in the instruction code (-128 to +127) and add the result to PC to form an effective address
(EA). Then, jump to the EA. (Latency = 4 clock cycles)
JR GE,$+2+d
If CF is set, set JF to 1 and skip to the next instruction. (Latency = 2 clock cycles)
1 1 0 1
JR LE,$+2+d
1 1 0 0 d d d d
d d d d
1 – – – – – 4/2(t/f)
if (CF ⏐ ZF)=1 then PC ← PC+d else null
If CF or ZF or both are set, sign-extend the 8-bit displacement d in the instruction code (-128 to +127) and add the result to PC to form an effective
address (EA). Then, jump to the EA. (Latency = 4 clock cycles)
If both CF and ZF are cleared, set JF to 1 and skip to the next instruction. (Latency = 2 clock cycles)
1 1 0 1
1 1 0 1 d d d d
d d d d
1 – – – – – 4/2(t/f)
if (CF ⏐ ZF)=0 then PC ← PC+d else null
If both CF and ZF are cleared, sign-extend the 8-bit displacement d in the instruction code (-128 to +127) and add the result to PC to form an effecJR GT,$+2+d
tive address (EA). Then, jump to the EA. (Latency = 4 clock cycles)
If CF or ZF or both are set, set JF to 1 and skip to the next instruction. (Latency = 2 clock cycles)
1 1 1 0
JR M,$+3+d
RA000
d d d d 1 – – – – – 5/3(t/f)
if SF=1 then PC ← PC+d else null
1 0 0 0 1 1 0 1
0 0 0 1 d d d d
d d d d 1 – – – – – 5/3(t/f)
if SF=0 then PC ← PC+d else null
If SF is cleared, sign-extend the 8-bit displacement d in the instruction code (-128 to +128) and add the result to PC to form an effective address
(EA). Then, jump to the EA. (Latency = 5 clock cycles)
If SF is set, set JF to 1 and skip to the next instruction. (Latency = 3 clock cycles).
1 1 1 0
JR
SLT,$+3+d
0 0 0 0 d d d d
If SF is set, sign-extend the 8-bit displacement d in the instruction code (-128 to +128) and add the result to PC (3 plus the address of the current JR
instruction) to form an effective address (EA). Then, jump to the EA. (Latency = 5 clock cycles)
If SF is cleared, set JF to 1 and skip to the next instruction. (Latency = 3 clock cycles).
1 1 1 0
JR P,$+3+d
1 0 0 0 1 1 0 1
1 0 0 0 1 1 0 1
0 0 1 0 d d d d
d d d d 1 – – – – – 5/3(t/f)
if (SF ^ VF)=1 then PC ← PC+d else null
Combine the Sign and Overflow flags in an exclusive-OR operation. If the result is 1, sign-extend the 8-bit displacement d in the instruction code (128 to +128) and add the result to PC to form an effective address (EA). Then, jump to the EA. (Latency = 5 clock cycles)
If the result is 0, set JF to 1 and skip to the next instruction. (Latency = 3 clock cycles).
Page 67
2.5 Jump Instructions
2.5 Jump Instructions
TLCS-870/C1
Flag
Mnemonic
Instruction Code (Binary)
Cycle
Operation
J Z C H S V
1 1 1 0
JR
SGE,$+3+d
1 0 0 0 1 1 0 1
0 0 1 1 d d d d
d d d d 1 – – – – – 5/3(t/f)
if (SF
^
VF)=0 then PC ← PC+d else null
Combine the Sign and Overflow flags in an exclusive-OR operation. If the result is 0, sign-extend the 8-bit displacement d in the instruction code (128 to +128) and add the result to PC to form an effective address (EA). Then, jump to the EA. (Latency = 5 clock cycles)
If the result is 1, set JF to 1 and skip to the next instruction. (Latency = 3 clock cycles).
if ZF ⏐ (SF ^
1 1 1 0
JR
SLE,$+3+d
0 1 0 0 d d d d
d d d d 1 – – – – – 5/3(t/f)
VF)=1 then PC ← PC+d else null
Combine the Sign and Overflow flags in an exclusive-OR operation. If the result or ZF or both are 1, sign-extend the 8-bit displacement d in the
instruction code (-128 to +128) and add the result to PC to form an effective address (EA). Then, jump to the EA. (Latency = 5 clock cycles)
If both the result and ZF are 0, set JF to 1 and skip to the next instruction. (Latency = 3 clock cycles).
1 1 1 0
JR
SGT,$+3+d
1 0 0 0 1 1 0 1
1 0 0 0 1 1 0 1
0 1 0 1 d d d d
d d d d 1 – – – – – 5/3(t/f)
if ZF⏐ (SF ^ VF)=0 then PC ← PC+d else null
Combine the Sign and Overflow flags in an exclusive-OR operation. If both the result and ZF are 0, sign-extend the 8-bit displacement d in the
instruction code (-128 to +128) and add the result to PC to form an effective address (EA). Then, jump to the EA. (Latency = 5 clock cycles)
If the result or ZF or both are 1, set JF to 1 and skip to the next instruction. (Latency = 3 clock cycles).
1 1 1 0
1 0 0 0 1 1 0 1
0 1 1 0 d d d d
d d d d 1 – – – – – 5/3(t/f)
if VF=1 then PC ← PC+d else null
JR VS,$+3+d If VF is set, sign-extend the 8-bit displacement d in the instruction code (-128 to +127) and add the result to PC to form an effective address (EA).
Then, jump to the EA. (Latency = 5 clock cycles)
If VF is cleared, set JF to 1 and skip to the next instruction. (Latency = 2 clock cycles)
1 1 1 0
1 0 0 0 1 1 0 1
0 1 1 1 d d d d
d d d d 1 – – – – – 5/3(t/f)
if VF=0 then PC ← PC+d else null
JR VC,$+3+d If VF is cleared, sign-extend the 8-bit displacement d in the instruction code (-128 to +127) and add the result to PC to form an effective address
(EA). Then, jump to the EA. (Latency = 5 clock cycles)
If VF is set, set JF to 1 and skip to the next instruction. (Latency = 2 clock cycles)
1 1 1 1
JR $+2+d
1 1 0 0 d d d d
d d d d
1 – – – – – 4
PC ← PC+d
Sign-extend the 8-bit displacement d in the instruction code (-128 to +128) and add the result to PC (2 plus the address of the current JR instruction)
to form an effective address (EA). Then, unconditionally jump to the EA.
Example: The instruction “JR $+0x73” at address 0xD5A7 causes a jump to the address 0xD61C.
1 1 1 1
1 1 1 0 n n n n
n n n n mmmm
mmmm – – – – – – 4
PC ← mn
JP mn
Unconditionally jump to the memory location directly addressed by 16-bit immediate mn.
1 1 1 0
JP gg
1 1 1 0
– – – – – – 3
PC ← gg
Unconditionally jump to the memory location addressed by 16-bit register gg.
Example: Assume HL contains 0xE325. Then, the instruction “JP HL” causes a jump to the address 0xE325.
1 1 1 0
JP (x)
1 g g g 1 1 1 1
0 0 0 0 x x x x
x x x x 1 1 1 1
1 1 1 0 – – – – – – 6
PC ← (x+1,x)
Form an effective address (EA) with 2 consecutive bytes from the memory location directly addressed by x. Then, unconditionally jump to the EA.
(0x0000 ≤ x ≤ 0x00FF)
Example: Assume memory locations at addresses 0x0085 and 0x0086 contain 0x27 and 0xC3 respectively. Then, the instruction “JP (0x85)”
causes a jump to the address 0xC327.
1 1 1 0
1 1 1 1
0 0 0 1 w w w w
1 1 1 0
w w w w v v v v
v v v v – – – – – – 7
PC ← (vw+1,vw)
JP (vw)
Form an effective address (EA) with 2 consecutive bytes from the memory location directly addressed by vw. Then, unconditionally jump to the EA.
(0x0000 ≤ vw ≤ 0xFFFF)
1 1 1 0
JP (DE)
1 1 1 0
JP (HL)
RA000
PC ← (DE+1,DE)
0 0 1 1 1 1 1 1
1 1 1 0
– – – – – – 5
PC ← (HL+1,HL)
0 1 0 0 1 1 1 1
1 1 1 0
– – – – – – 5
PC ← (IX+1,IX)
0 1 0 1 1 1 1 1
1 1 1 0
– – – – – – 5
PC ← (IY+1,IY)
Form an effective address (EA) with 2 consecutive bytes from the memory location addressed by IY. Then, unconditionally jump to the EA.
Example: Assume IY and the memory locations at addresses 0x0125 and 0x0126 contain 0x0125, 0x87 and 0xE5 respectively. Then, the instruction
“JP (IY)” causes a jump to the address 0xE587.
1 1 0 1
JP (IX+d)
– – – – – – 5
Form an effective address (EA) with 2 consecutive bytes from the memory location addressed by IX. Then, unconditionally jump to the EA.
Example: Assume IX and the memory locations at addresses 0x0125 and 0x0126 contain 0x0125, 0x87 and 0xE5 respectively. Then, the instruction
“JP (IX)” causes a jump to the address 0xE587.
1 1 1 0
JP (IY)
1 1 1 0
Form an effective address (EA) with 2 consecutive bytes from the memory location addressed by HL. Then, unconditionally jump to the EA.
Example: Assume HL and the memory locations at addresses 0x0125 and 0x0126 contain 0x0125, 0x87 and 0xE5 respectively. Then, the instruction “JP (HL)” causes a jump to the address 0xE587.
1 1 1 0
JP (IX)
0 0 1 0 1 1 1 1
Form an effective address (EA) with 2 consecutive bytes from the memory location addressed by DE. Then, unconditionally jump to the EA.
Example: Assume DE and the memory locations at addresses 0x0125 and 0x0126 contain 0x0125, 0x87 and 0xE5 respectively. Then, the instruction “JP (DE)” causes a jump to the address 0xE587.
0 1 0 0 d d d d
d d d d 1 1 1 1
1 1 1 0 – – – – – – 7
PC ← (IX+d+1,IX+d)
Form an effective address (EA) with 2 consecutive bytes from the memory location addressed by sign-extending the 8-bit displacement d in the
instruction code and adding the result to IX. Then, unconditionally jump to the EA.
Page 68
TLCS-870/C1
Flag
Mnemonic
Instruction Code (Binary)
Cycle
Operation
J Z C H S V
1 1 0 1
0 1 0 1 d d d d
d d d d 1 1 1 1
1 1 1 0 – – – – – – 7
PC ← (IY+d+1,IY+d)
JP (IY+d)
Form an effective address (EA) with 2 consecutive bytes from the memory location addressed by sign-extending the 8-bit displacement d in the
instruction code and adding the result to IY. Then, unconditionally jump to the EA.
JP (SP+d)
Form an effective address (EA) with 2 consecutive bytes from the memory location addressed by sign-extending the 8-bit displacement d in the
instruction code and adding the result to SP. Then, unconditionally jump to the EA.
JP (HL+d)
Form an effective address (EA) with 2 consecutive bytes from the memory location addressed by sign-extending the 8-bit displacement d in the
instruction code and adding the result to HL. Then, unconditionally jump to the EA.
JP (HL+C)
Form an effective address (EA) with 2 consecutive bytes from the memory location addressed by sign-extending the contents of C and adding the
result to HL. Then, unconditionally jump to the EA.
1 1 0 1
1 1 0 1
1 1 1 0
1 1 1 0
0 1 1 0 d d d d
0 1 1 1 d d d d
0 1 1 1 1 1 1 1
0 1 1 0 1 1 1 1
d d d d 1 1 1 1
d d d d 1 1 1 1
1 1 1 0 – – – – – – 7
1 1 1 0 – – – – – – 7
1 1 1 0
– – – – – – 7
1 1 1 0
– – – – – – 6
JP (+SP)
PC ← (SP+d+1,SP+d)
PC ← (HL+d+1,HL+d)
PC ← (HL+C+1,HL+C)
SP ← SP+1:PC ← (SP+1,SP)
Form an effective address (EA) with 2 consecutive bytes from the memory location addressed by (SP+1). Then, unconditionally jump to the EA.
JP
(PC+A)Note
0 1 0 0
1 1 1 1 1 1 1 1
1 1 1 0
– – – – – – 7
PC ← (PC+A+1,PC+A)
Form an effective address (EA) with 2 consecutive bytes from the memory location addressed by sign-extending the contents of A and adding the
result to PC (2 plus the address of the current JP instruction). Then, unconditionally jump to the EA. This instruction is useful for multi-way branches.
Note: There are restrictions on instructions that uses the operand (PC + A). For more details, see "1.4 Addressing Mode".
RA000
Page 69
2.5 Jump Instructions
2.5 Jump Instructions
RA000
TLCS-870/C1
Page 70