Chapter 3 TLCS-900/H1 CPU - TOSHIBA Semiconductor & Storage

Chapter 3 TLCS-900/H1 CPU
Semiconductor Company
TLCS-900H1 CPU
900, 900/L, 900/H, 900/L1,900/H1 CPU Core Different Points
There are 5 type CPU core : [1] 900, [2] 900/L, [3] 900/H, [4] 900/L1, [5] 900/H1 in TLCS-900 series
and they are different from following points.
CPU core Different Point
CPU
900
900/L
900/H, 900/L1
Address Bus
24 bit
←
←
←
Data Bus
16 bit
←
←
32 bit
Difference
Instruction Queue
Instruction Set
Code Fetch
Micro DMA
Operation Mode
Register Mode
Interrupt
Normal Stack
Pointer
XNSP
Interrupt Nesting Counter
(INTNEST)
4 byte
TLCS-900
←
Deleted instruction
NORMAL
MAX
Added instruction
MIN
←
Deleted instruction
NORMAL
MAX
900/H1
12 bit
Deleted instruction
NORMAL
MAX
LDX
←
←
4 channels
←
←
8 channels
Normal mode,
System mode
System mode
←
←
←
MAX mode
←
Only when branch,
CPU fetch branch
destination code.
MIN mode,
MAX mode
(MIN mode @ reset )
Even when not branch,
CPU fetch branch
destination code.
(MAX mode @ reset )
Restart formula
Vector formula
←
←
exist
not exist
←
←
not exist
exist
←
←
Page 1
TLCS-900H1 CPU
1. Outline
The TLCS-900/H1 series has an original Toshiba high-performance 32-bit CPU. Combining the
CPU with various I/O function blocks (such as timers, serial I/Os, ADs) creates broad possibilities in
application fields.
The TLCS-900/H1 CPU is 32-bit CPU. It has a 32-bit register bank configuration, therefore it is
suitable as an embedded controller.
The TLCS-900/H1 CPU features are as follows :
(1) General-purpose registers
•
All 8 registers usable as accumulator
(2) Register bank system
•
four 32-bit register banks
(3) 16M-byte linear address space ; 9 types addressing modes
(4) Dynamic bus sizing system
•
Can consist 8-/16-/32-bit external data bus together
(5) Orthogonal instruction sets
•
8-/16-/32-bit data transfer/arithmetic instructions
•
16-bit multiplication/division
16 × 16 to 32-bits (signed/unsigned)
32 ÷ 16 to 16-bits...remainder 16-bits (signed/unsigned)
•
Bit processing including bit arithmetic
•
Supporting instruction for C compiler
•
Filter calculations : multiplication-addition arithmetic, modulo increment instruction
(6) High-speed processing
•
Minimum instruction execution time : 1 clock (50 ns at using 20 MHz)
•
Pipeline system with 12-byte instruction queue buffer
•
32-bit ALU
Page 2
TLCS-900H1 CPU
2. Resources
The CPU resources are as follows :
(1) General-purpose registers
•
Four 32-bit general-purpose registers × 4 banks
•
Four 32-bit general-purpose registers (including system stack pointer : XSP)
(2) Status register (SR)
(3) Program counter (PC): It is 32 bits, but only 24 bits are output.
(4) Control register: Micro-DMA control register and interrupt nesting counter
(5) All CPU instructions
(6) All built-in I/O registers
(7) All built-in memories
Page 3
TLCS-900H1 CPU
3. Registers
3.1
Register Structure......16 M-byte program area/16 M-byte data area
Figure 3.1 illustrates the format of registers.
Four 32-bit general-purpose registers × 4 banks
+
Four 32-bit general-purpose registers
+
32-bit program counter
+
Status register
Figure 3.1 Register Format
Page 4
TLCS-900H1 CPU
3.2
3.2.1
Register Details
General-purpose bank registers
There is the following four 32-bit general-purpose registers consisting of 4 banks. The register
format in a bank is shown below.
Four 32-bit registers (XWA, XBC, XDE, and XHL) are general-purpose registers and can be
used as an accumulators and index registers. They can also be used as 16-bit registers (WA, BC,
DE, and HL), in which case, the lower 16 bits of the 32-bit registers are assigned.
16-bit registers can be used as accumulators, index registers in index addressing mode, and
displacement registers. They can also be used as two 8-bit general-purpose registers (W, A, B, C,
D, E, H, and L) to function for example as accumulators.
3.2.2
32-bit General-purpose Registers
The TLCS-900 series has four 32-bit general-purpose registers (XIX, XIY, XIZ, and XSP). The
register format is shown below.
These registers can also be used as accumulators, index registers, and displacement registers.
They can be used either as 16-bit, or 8-bit registers. Names when registers are used as 8-bit
registers are listed later.
The XSP register is utilized for stack pointer. It is used when the interrupt is occured or
"CALL", "RET" instruction are executed. The stack pointer (XSP) is set to 00000000H by
resetting.
Page 5
TLCS-900H1 CPU
3.2.3
Status Register (SR)
The status register contains flags indicating the status (operating mode, register format, etc. )
of the CPU and operation results. This register consists of two parts. The upper byte of the status
register (bits 8 to 15) indicates the CPU status. The lower byte (bits 0 to 7) are referred to as the
flag register (F). This indicates the status of the operation result. The TLCS-900 series has two
flag registers (F and F' ). They can be switched using the EX instruction.
(1) Upper Byte of Status Register
15
14
13
12
11
10
9
8
“1”
IFF2
IFF1
IFF0
“1”
“0”
RFP1
RFP0
[1] IFF2 to IFF0 (Interrupt mask Flip-Flop2 to 0)
Mask registers with interrupt levels from 1 to 7. Level 7 has the highest priority.
Initialized to 111 by reset.
000
Enables interrupts with level 1 or higher.
001
Enables interrupts with level 1 or higher.
010
Enables interrupts with level 2 or higher.
011
Enables interrupts with level 3 or higher.
100
Enables interrupts with level 4 or higher.
101
Enables interrupts with level 5 or higher.
110
Enables interrupts with level 6 or higher.
111
Enables interrupts with level 7 only (non-maskable interrupt).
Same
Any value can be set using the EI instruction.
When an interrupt is received, the mask register sets a value higher by 1 than the interrupt level
received. When an interrupt with level 7 is received, 111 is set. The EI instruction becomes effective
immediately after execution.
[2] RFP1 to RFP0 (Register File Pointer1 to 0)
Indicates the number of register file (register bank) currently being used. Initialized to
00 by reset.
The values in these registers can be operated on using the following three instructions.
•
LDF imm
; RFP ← imm (0 to 3)
•
INCF
; RFP ← RFP + 1
•
DECF
; RFP ← RFP − 1
Page 6
TLCS-900H1 CPU
(2) Flag Register, F
7
6
5
4
3
2
1
0
S
Z
“0”
H
“0”
V
N
C
: R/W
[1] S (Sign flag)
"1" is set when the operation result is negative, "0" when positive.
(The value of the most significant bit of the operation result is copied.)
[2] Z (Zero flag)
"1" is set when the operation result is zero, otherwise "0".
[3] H (Half carry flag)
"1" is set when a carry or borrow from bit 3 to bit 4 occurs as a result of the operation,
otherwise "0". With a 32-bit operation instruction, an undefined value is set.
[4] V (Parity/over-flow flag)
Indicates either parity or overflow, depending on the operation type.
Parity (P):
"0" is set when the number of bits set to 1 is odd, "1" when even.
An undefined value is set with a 32-bit operation instruction.
Overflow (V):
"0" is set if no overflow, if overflow "1".
[5] N (Negative)
ADD/SUB flag
"0" is set after an addition instruction such as ADD is executed, "1" after a subtraction
instruction such as SUB.
Used when executing the DAA (decimal addition adjust accumulator) instruction.
[6] C (Carry flag)
"1" is set when a carry or borrow occurs, otherwise "0".
Read and write process of status register
Read from bits 0 to 15
[1]
PUSH
POP
SR
dst
SR
Write to bits 0 to 15
[1]
POP
Only bits 14 to12
<IFF2:0>
[1]
EI num
A value of "num" is written.
Only bits 9 to 8
<RFP1:0>
[1]
[2]
[3]
LDF
INCF
DECF
Only bits 7 to 0
[1]
[2]
[3]
PUSH F/POP F
EX
F, F′
A flag is set indirectly by executing arithmetic instruction etc.
imm
Page 7
TLCS-900H1 CPU
3.2.4
Program Counter (PC)
The program counter is a pointer indicating the memory address to be executed next.
A maximum program area of 16M bytes can be accessed as a linear address space.
Though the program counter is 32-bit width, it can only be used 24-bit width for the CPU
address bus.
PC after reset
The 900/H1 reads a value of a reset vector from a vector base address by reset and sets the value into a
program counter. Then, program after the vector specified by the program counter are executed.
The vector base address is as follows:
Vector Base Address
3.2.5
PC setting after reset
PC (7:0) ← 0FFFF00H
PC (15:8) ← 0FFFF01H
PC (23:16) ← 0FFFF02H
0FFFF00H
Control registers (CR)
The control registers consist of registers used to control micro DMA operation and an interrupt nesting
counter. Control registers can be accessed by using the LDC instruction.
Control registers are illustrated below.
<DMA S0>
<DMA S1>
<DMA S2>
DMA
source address
register
<DMA S3>
<DMA S4>
<DMA S5>
<DMA S6>
<DMA S7>
<DMA D0>
<DMA D1>
<DMA D2>
DMA
destination
address
register
<DMA D3>
<DMA D4>
<DMA D5>
<DMA D6>
<DMA D7>
DMAM0
(DMA C0)
DMAM1
(DMA C1)
DMAM2
(DMA C2)
DMAM3
(DMA C3)
DMAM4
(DMA C4)
DMAM5
(DMA C5)
DMAM6
(DMA C6)
DMAM7
(DMA C7)
(INTN EST)
( ): Word register name (16 bits)
< >: Long word register name (32 bits)
For micro DMA, refer to "Part 2 TLCS-900/H1 LSI Devices".
Page 8
DMA
counter / mode
register
Interrupt Nesting
Counter
TLCS-900H1 CPU
3.3
Register Bank Switching
Register banks are classified into the following three types.
Current bank registers
Previous bank registers
Absolute bank registers
The current bank is indicated by the register file pointer, <RFP>, (status register bits 8 to 9).
The registers in the current bank are used as general-purpose registers, as described in the
previous section. By changing the contents of the <RFP>, another register bank becomes the
current register bank.
The previous bank is indicated by the value obtained by subtracting 1 from the <RFP>. For
example, if the current bank is bank 3, bank 2 is the previous bank. The names of registers in the
previous bank are indicated with a dash (WA', BC', DE', HL' ). The EX instruction (EX A, A' ) is
used to switch between current and previous banks.
All bank registers, including the current and previous ones, have a numerical value (absolute
bank number) to indicate the bank. With a register name which includes a numerical value such
as RW0, RA0, etc., all bank registers can be used. These registers (that is, all registers) are called
absolute bank registers.
The TLCS-900/H1 series CPU is designed to perform optimally when the current bank registers
are operated as the working registers. In other words, if the CPU uses other bank registers, its
performance degrades somewhat. In order to obtain maximum CPU efficiency, the TLCS-900/H1
series has a function which easily switches register banks.
The bank switching function provides the following advantages:
•
Optimum CPU operating efficiency
•
Reduced programming size (Object codes)
•
Higher response speed and reduced programming size when used as a context switch for an
interrupt sevice routine.
Bank switching is performed by the instructions listed below.
LDF imm:
Sets the contents of the immiediate value in <RFP>. imm: 0 to 3
INCF:
Increments <RFP> by 1.
DECF:
Decrements <RFP> by 1.
The immediate values used by the LDF instruction are from 0 to 3. If a carry or borrow occurs
when the INCF or DECF instruction is executed, it is ignored. The value of the <RFP> rotates. For
example, if the INCF instruction is executed with bank 3, the result is bank 0. If the DECF
instruction is executed with bank 0, the result is bank 3.
Page 9
TLCS-900H1 CPU
•
Example of Register Bank Usage
The TLCS-900/H1 series registers are formatted in banks. Banks can be used for
processing objectives or interrupt levels. Two examples are given below.
<Example 1>
When assigning register banks to interrupt processing routines.
Register bank 0 = Used for the main program and interrupt processing other than
that shown below.
Register bank 1 = Used for processing INT0.
Register bank 2 = Used for processing timer 0.
Register bank 3 = Used for processing timer 1.
For example, if a timer 1 interrupt occurs during main program execution, processing
jumps to a subroutine as follows. PUSH/POP processing for the register is unnecessary.
LDF 3
; Sets register bank to 3.
:
:
RETI
; Returns to previous status including <RFP>.
<Example2> When assigning register banks to their appropriate interrupt level.
Note:
The INCF instruction is used to execute <RFP>←<RFP> + 1.
Page 10
TLCS-900H1 CPU
3.4
Accessing General-purpose Registers
The register access code is formatted in a varied code length on byte basis. The current bank
registers can be accessed by the shortest code length. All general-purpose registers can be accessed
by an instruction code which is 1 byte longer. General-purpose registers are as follows.
[1] General-purpose registers in current bank
QW
( Q WA)
QA
< X WA>
W
( W A)
A
QB
( Q BC)
QC
< X BC>
B
( B C)
C
QD
( Q DE)
QE
< X DE>
D
( D E)
E
QH
( Q HL)
QL
< X HL>
H
( H L)
L
( ): Word register name (16 bits)
< >: Long word register name (32 bits)
[2] General-purpose registers in previous bank
QW’
( Q WA’)
QA’
< X WA’>
W’
( W A’)
A’
QB’
( Q BC’)
QC’
< X BC’>
B’
( B C’)
C’
QD’
( Q DE’)
QE’
< X DE’>
D’
( D E’)
E’
QH’
( Q HL’)
QL’
< X HL’>
H’
( H L’)
L’
[3] 32-bit general-purpose registers
QIXH
( Q IX)
QIXL
< X IX>
IXH
( I X)
IXL
QIYH
( Q IY)
QIYL
< X IY>
IYH
( I Y)
IYL
QIZH
( Q IZ)
QIZL
< X IZ>
IZH
( I Z)
IZL
QSPH
( Q SP)
QSPL
< X SP>
SPH
( S P)
SPL
[4] Absolute bank registers
QW0
( QWA 0)
QA0
< XWA 0>
RW0
( RWA 0)
RA0
QB0
( QBC 0)
QC0
< XBC 0>
RB0
( RBC 0)
RC0
QD0
( QDE 0)
QE0
< XDE 0>
RD0
( RDE 0)
RE0
QH0
( QHL 0)
QL0
< XHL 0>
RH0
( RHL 0)
RL0
QW1
( QWA 1)
QA1
< XWA 1>
RW1
( RWA 1)
RA1
QB1
( QBC 1)
QC1
< XBC 1>
RB1
( RBC 1)
RC1
QD1
( QDE 1)
QE1
< XDE 1>
RD1
( RDE 1)
RE1
QH1
( QHL 1)
QL1
< XHL 1>
RH1
( RHL 1)
RL1
QW2
( QWA 2)
QA2
< XWA 2>
RW2
( RWA 2)
RA2
QB2
( QBC 2)
QC2
< XBC 2>
RB2
( RBC 2)
RC2
QD2
( QDE 2)
QE2
< XDE 2>
RD2
( RDE 2)
RE2
QH2
( QHL 2)
QL2
< XHL 2>
RH2
( RHL 2)
RL2
QW3
( QWA 3)
QA3
< XWA 3>
RW3
( RWA 3)
RA3
QB3
( QBC 3)
QC3
< XBC 3>
RB3
( RBC 3)
RC3
QD3
( QDE 3)
QE3
< XDE 3>
RD3
( RDE 3)
RE3
QH3
( QHL 3)
QL3
< XHL 3>
RH3
( RHL 3)
RL3
( ): Word register name (16 bits)
< >: Long word register name (32 bits)
Page 11
Bank0
Bank1
Bank2
Bank3
TLCS-900H1 CPU
4. Addressing Modes
The TLCS-900/H1 has nine addressing modes. These are combined with most instructions to improve CPU
processing capabilities.
TLCS-900/H1 addressing modes are listed below.
No.
Addressing mode
Description
1.
Register
reg8
reg16
reg32
2.
Immediate
n8
n16
n32
3.
Register indirect
(reg)
4.
Register indirect
pre-decrement
(−reg)
5.
Register indirect
post-increment
(reg+)
6.
Index
(reg + d8)
(reg + d16)
7.
Register index
(reg + reg8)
(reg + reg16)
8.
Absolute
(n8)
(n16)
(n24)
9.
Relative
(PC + d8)
(PC + d16)
reg8:
reg16:
reg32:
reg:
d8:
d16:
n8:
n16:
n32:
All 8-bit registers such as W, A, B, C, D, E, H, L, etc.
All 16-bit registers such as WA, BC, DE, HL, IX, IY, IZ, SP, etc.
All 32-bit registers such as XWA, XBC, XDE, XHL, XIX, XIY, XIZ, XSP, etc.
All 32-bit registers such as XWA, XBC, XDE, XHL, XIX, XIY, XIZ, XSP, etc.
8-bit displacement (-80H to +7FH)
16-bit displacement (-8000H to +7FFFH)
8-bit constant (00H to FFH)
16-bit constant (0000H to FFFFH)
32-bit constant (00000000H to FFFFFFFFH)
Note 1: Relative addressing mode can only be used with the following instructions:
LDAR, JR, JRL, DJNZ, CALR
Note 2: Though the addressing mode can use 32-bit width, it can only be used 24-bit width for the
CPU address bus.
Page 12
TLCS-900H1 CPU
(1) Register Addressing Mode
In this mode, the operand is the specified register.
Example: LD HL, IX
CPU
HL
1
2
3
4
IX
1
2
3
4
The IX register contents, 1234H, are loaded to the HL register.
(2) Immediate Addressing Mode
In this mode, the operand is in the instruction code.
Example: LD HL, 5678H
The immediate data, 5678H, is loaded to the HL register.
(3) Register Indirect Addressing Mode
In this mode, the operand is memory address specified by the contents of the register.
Example: LD HL, (XIX)
Memory data, 2233H, at address 345678H is loaded to the HL register.
Page 13
TLCS-900H1 CPU
(4) Register Indirect Pre-decrement Addressing Mode
In this mode, the contents of the register is decremented by the pre-decrement values. In this case, the
operand is the memory address specified by the decremented register.
Example 1: LD HL, ( - XIX)
The pre-decrement values are as follows:
When the size of the operand is one byte (8 bits) : −1
When the size of the operand is one word (16 bits) : −2
When the size of the operand is one long word (32 bits) : −4
Example 2: LD XIX, ( - XBC)
Page 14
TLCS-900H1 CPU
(5) Register Indirect Post-increment Addressing Mode
In this mode, the operand is the memory address specified by the contents of the register. After the operation,
the contents of the register are incremented by the size of the operand.
Example 1: LD HL, (XIX + )
Example 2: LD A, (XBC + )
Page 15
TLCS-900H1 CPU
(6) Index Addressing Mode
In this mode, the operand is the memory address obtained by adding the contents of the register (32-bit)
specified as the base to the 8- or 16-bit displacement value in the instruction code.
Example 1: LD HL, (XIX + 13H)
Example 2: LD HL, (XBC - 1000H)
The displacement values range from −8000H to +7FFFH.
Page 16
TLCS-900H1 CPU
(7) Register Index Addressing Mode
In this mode, the operand is the memory address obtained by adding the contents of the 32-bit
register specified as the base to the register specified as the 8- or 16-bit displacement.
Example 1: LD HL, (XIX + A)
Example 2: LD HL, (XBC + DE)
Page 17
TLCS-900H1 CPU
(8)
Absolute Addressing Mode
In this mode, the operand is the memory address specified by 1 to 3 bytes in the instruction
code. Addresses 000000H to 0000FFH can be specified by 1 byte. Addresses 000000H to
00FFFFH can be specified by 2 bytes. Addresses 000000H to FFFFFFH can be specified by 3
bytes.
Example 1: LD HL, (80H)
Example 2: LD HL, (1234H)
Example 3: LD HL, (56789AH)
Page 18
TLCS-900H1 CPU
(9) Relative Addressing Mode
In this mode, the operand is the memory address obtained by adding the 8- or 16-bit
displacement value to the address where the instruction code being executed is located.
In this mode, only the following five instructions can be used.
LDAR
R, $ + 4 + d16
JR
cc, $ + 2 + d8
JRL
cc, $ + 3 + d16
CALR
$ + 3 + d16
DJNZ
r, $ + 3 + d8
($: start address of instruction code)
In calculating the displacement object code value, the adjustment value (+2 to +4) depends on the instruction
type.
Example 1: JR 2034H
In the above example, the displacement object code value is:
2034H − (2000H + 2) = 32H
Page 19
TLCS-900H1 CPU
5. Instructions
In addition to its various addressing modes, the TLCS-900/H1 also has a powerful instruction set.
The basic instructions are classified into the following nine groups:
•
Load instructions (8/16/32 bits)
•
Exchange instructions (8/16 bits)
•
Block transfer & Block search instructions (8/16 bits)
•
Arithmetic operation instructions (8/16/32 bits)
•
Logical operation instructions (8/16/32 bits)
•
Bit operation instructions (1 bit)
•
Special operations, CPU control instructions
•
Rotate and Shift instructions (8/16/32 bits)
•
Jump, Call, and Return instructions
Table 5 lists the basic instructions of the TLCS-900/H1. For details of instructions, see Appendix
A; for the instruction list, Appendix B; for the instruction code map, Appendix C.
Page 20
TLCS-900H1 CPU
Table 5 (1) TLCS-900/H1 Basic Instructions
LD
dst, src
Load dst ← src
PUSH
src
Push src data to stack
SP ← SP − size: (SP) ← src
POP
dst
Pop data from stack to dst
dst ← (SP): SP ← SP + size
LDA
dst, src
Load address: set src effective address in dst
LDAR
dst, PC + dd
Load address relative:
set program counter relative address value in dst. dst ← PC + dd
EX
dst1, dst2
Exchange dst1 and dst2 data
MIRR
dst
Mirror-invert dst bit pattern.
LDI
Load increment
LDIR
Load increment repeat
LDD
Load decrement
LDDR
Load decrement repeat
CPI
Compare increment
CPIR
Compare increment repeat
CPD
Compare decrement
CPDR
Compare decrement repeat
dst ← PC + dd
ADD
dst, src
Add
ADC
dst, src
Add with carry
dst ← dst + src + CY
SUB
dst, src
Subtract
dst ← dst + src + CY
SBC
dst, src
Subtact with carry
dst ← dst − src − CY
CP
dst, src
Compare
dst − src
AND
dst, src
And
dst ← dst AND src
OR
dst, src
Or
dst ← dst OR src
XOR
dst, src
Exclusive-or
dst ← dst XOR src
INC
imm, dst
Increment
dst ← dst + imm
DEC
imm, dst
Decrement
dst ← dst − imm
MUL
dst, src
Multiply unsigned
dst ← dst (low) × src
MULS
dst, src
Multiply signed
dst ← dst (low) × src
DIV
dst, src
Divide unsigned
dst (low) ← dst ÷ src
dst (high) ← remainder
V flag set due to division by 0 or overflow.
DIVS
dst, src
Divide signed
dst (low) ← dst ÷ src
dst (high) ← remainder: sign is same as that of dividend.
V flag set due to division by 0 or overflow.
MULA
dst
Multiply and add
MINC1
num, dst
Modulo increment 1
MINC2
num, dst
Modulo increment 2
MINC4
num, dst
Modulo increment 4
MDEC1
num, dst
Modulo decrement 1
MDEC2
num, dst
Modulo decrement 2
MDEC4
num, dst
Modulo decrement 4
NEG
dst
Negate
dst ← 0 − dst (Twos complement)
CPL
dst
Complement
dst ← not dst (Ones complement)
EXTZ
dst
Extend zero: set upper data of dst to 0
EXTS
dst
Extend signed: copy the MSB of the lower data of dst to upper data
DAA
dst
Decimal adjustment accumulator
PAA
dst
Pointer adjustment accumulator
when dst is odd, increment dst by 1 to make it even
if dst (0) = 1 then dst ← dst + 1.
LDCF
bit, src
Load carry flag: copy src<bit> value to C flag.
dst ← dst + (XDE) × (XHL−)
32bit 32bit 16bit 16bit
Page 21
TLCS-900H1 CPU
STCF
bit, dst
Store carry flag: copy C flag value to dst<bit>.
ANDCF
bit, src
And carry flag
and src<bit> value and C flag, then load the result to C flag.
ORCF
bit, src
Or carry flag: or src<bit> and C flag, then load result to C flag.
XORCF
bit, src
Exclusive-or carry flag:
exclusive-or src<bit> value and C flag, then load result to C flag.
RCF
Reset carry flag: reset C flag to 0.
SCF
Set carry flag: set C flag to 1.
CCF
Complement carry flag: invert C flag value.
ZCF
Zero flag to carry flag: copy inverted value of Z flag to C flag.
BIT
bit, src
Bit test: Z flag ← not src<bit>
RES
bit, dst
Bit reset
SET
bit, dst
Bit set
CHG
bit, dst
Bit change dst<bit> ← not dst<bit>
TSET
bit, dst
Bit test and set:
Z flag ← not dst<bit>
dst<bit> ← 1
BS1F
A, dst
Bit Search 1 forward: search dst for the first bit set to 1 starting from the LSB, then set the bit
numbr in the A register.
BS1B
A,dst
Bit Search 1 backward: search dst for the first bit set to 1 starting from the MSB, then set the bit
numbr in the A register.
NOP
EI
No operation
imm
DI
Enable interrupt.
IFF ← imm
Disable maskable interrupt.
IFF ← 7
PUSH
SR
Push status registers.
POP
SR
Pop status registers.
SWI
imm
Software interrupt
PUSH PC&SR : JP 8000H + 10H × imm
HALT
Halt CPU
LDC
CTRL − REG, reg
Load control: copy the register contents to control register of CPU.
LDC
reg, CTRL − REG
Load control: copy the control register contents to register.
LINK
reg, dd
Link: generate stack frame.
PUSH reg
LD
reg, XSP
ADD XSP, dd
UNLK
reg
Unlink: delete stack frame.
LD
XSP, reg
POP reg
LDF
imm
Load register file pointer:
specify register bank.
RFP ← imm
INCF
Increment register file pointer:
move to new register bank.
RFP ← RFP + 1
DECF
Decrement register file pointer:
return to previous register bank.
RFP ← RFP − 1
SCC
cc, dst
Set dst with condition codes.
if cc
then dst ← 1
else dst ← 0.
Page 22
TLCS-900H1 CPU
RLC
RRC
RL
RR
num, dst
num, dst
num, dst
num, dst
Rotate left without carry
CY
MSB
LSB
CY
MSB
LSB
CY
MSB
LSB
CY
MSB
LSB
Rotate right without carry
Rotate left
Rotate right
SLA
num, dst
Shift left arithmetic
SRA
num, dst
Shift right arithmetic
CY
MSB
CY
SLL
num, dst
Shift left logical
SRL
num, dst
Shift right logical
RLD
dst
MSB
CY
CY
LSB
LSB
MSB
0
LSB
MSB
LSB
43
0
7
43
0
dst
0
7
43
0
dst
Areg
dst
Rotate right digit
7
CY
MSB
43
LSB
JR
cc, PC + d
Jump relative (8-bit displacement)
if cc then PC ← PC + d.
JRL
cc, PC + dd
Jump relative long (16-bit displacement)
if cc then PC ← PC + dd.
JP
cc, dst
Jump
CALR
RC + dd
Relative call (16-bit displacement)
PUSH PC: PC ← PC + dd.
CALL
cc, dst
Call relative
if cc then PUSH PC: PC ← dst.
DJNZ
dst, PC + d
Decrement and jump if non-zero
dst ← dst − 1
if dst ≠ 0 then PC ← PC + d.
RET
cc
Return
RETD
dd
Return and deallocate
RET
XSP ← XSP + dd
if cc then PC ← dst.
if cc then POP PC.
RETI
0
Rotate left digit
7
RRD
0
Return from interrupt
POP SR&PC
Page 23
Areg
TLCS-900H1 CPU
Table 5 (2) TLCS-900/H1 Basic Instructions
BWL LD
reg, reg
BWL LD
reg, imm
BWL INC
DEC
imm3, reg
---
NOP
imm3, mem.B/W
BWL LD
reg, mem
BWL LD
mem, reg
---
EI
BW-
LD
mem, imm
---
DI
BW-
LD
(nn), mem
BW-
LD
mem, (nn)
BW-
MUL
reg, reg
-W-
PUSH
SR
MULS
reg, imm
-W-
POP
SR
DIV
reg, mem
---
SWI
[imm3]
---
HALT
DIVS
BWL PUSH
reg/F
BW-
PUSH
imm
BW-
PUSH
mem
-W-
[imm3]
MULA
reg
BWL LDC
CTRL − R, reg
BWL LDC
reg, CTRL − R
-W-
MINC1
imm, reg
--L
LINK
reg, dd
BWL POP
reg/F
-W-
MINC2
imm, reg
--L
UNLK
reg
BW-
mem
-W-
MINC4
imm, reg
---
LDF
imm2
-W-
MDEC1
imm, reg
---
INCF
POP
-WL
LDA
reg, mem
-WL
LDAR
reg, PC + dd
-W-
MDEC2
imm, reg
---
-W-
MDEC4
imm, reg
BW-
DECF
BW-
NEG
reg
BWL RLC
BW-
CPL
reg
RRC
A, reg
-WL
EXTZ
reg
RL
mem. B/W
-WL
EXTS
reg
RR
SCC
B--
EX
F, F’
BW-
EX
reg, reg
B--
DAA
reg
SLA
BW-
EX
mem, reg
-WL
PAA
reg
SRA
cc, reg
imm, reg
SLL
SRL
-W-
MIRR
reg
BW-
LDCF
imm, reg
STCF
A, reg
B--
RLD
[A,] mem
ANDCF
imm, mem.B
B--
RRD
[A,] mem
ORCF
A, mem.B
[cc,] PC + d
BW-
LDI
XORCF
BW-
LDIR
---
JR
BW-
LDD
---
RCF
---
JRL
[cc,] PC + dd
BW-
LDDR
---
SCF
---
JP
[cc,] mem
---
CCF
---
CALR
PC + dd
---
ZCF
---
CALL
[cc,] mem
BW-
DJNZ
[reg], PC + d
BW-
CPI
BW-
CPIR
BW-
CPD
BW-
CPDR
BWL ADD
BW-
BIT
imm, reg
RES
imm, mem.B
SET
---
RET
[cc]
CHG
---
RETD
dd
TSET
---
RETI
reg, reg
ADC
reg, imm
SUB
reg, mem
SBC
mem, reg
CP
mem, imm.B/W
-W-
BS1F
A, reg
BS1B
AND
OR
XOR
B = Byte (8 bit), W = Word (16 bit), L = Long-Word (32 bit).
[ ]: Indicates can be omitted.
Page 24
TLCS-900H1 CPU
6. Data Formats
The TLCS-900/H1 can handle 1/4/8/16/32-bit data.
(1) Register Data Format
(2) Memory Data Format
Note: There are no restrictions on the location of word or long word data in memory. They can be
located from even or odd numbered address.
Page 25
TLCS-900H1 CPU
(3) Dynamic Bus sizing
The TLCS-900/H1 can switch between 8-, 16- and 32-bit data buses dynamically during each bus cycle.
This is called dynamic bus sizing. The function enables external memory extension using both 8-, 16- and 32bit data bus memories. Products with a built-in memory controller can control external data bus size for each
address area.
Note: Prohibit the memory accesses between continuous data bus memories with another bus band
width in same instruction. It cannot switch the data buses dynamically.
Data size
(bit)
Start
address
Data size at
memory (bit)
CPU
address
D31-D24
D23-D16
D15-D8
D7-D0
8
4n + 0
8/16/32
4n + 0
xxxxx
xxxxx
xxxxx
b7-b0
4n + 1
8
4n + 1
xxxxx
xxxxx
xxxxx
b7-b0
16/32
4n + 1
xxxxx
xxxxx
b7-b0
xxxxx
8/16
4n + 2
xxxxx
xxxxx
xxxxx
b7-b0
32
4n + 2
xxxxx
b7-b0
xxxxx
xxxxx
8
4n + 3
xxxxx
xxxxx
xxxxx
b7-b0
16
4n + 3
xxxxx
xxxxx
b7-b0
xxxxx
32
4n + 3
b7-b0
xxxxx
xxxxx
xxxxx
8
(1) 4n + 0
(2) 4n + 1
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
b7-b0
b15-b8
4n + 2
4n + 3
16
4n + 0
4n + 1
4n + 2
4n + 3
CPU
16/32
4n + 0
xxxxx
xxxxx
b15-b8
b7-b0
8
(1) 4n + 1
(2) 4n + 2
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
b7-b0
b15-b8
16
(1) 4n + 1
(2) 4n + 2
xxxxx
xxxxx
xxxxx
xxxxx
b7-b0
xxxxx
xxxxx
b15-b8
32
4n + 1
xxxxx
b15-b8
b7-b0
xxxxx
8
(1) 4n + 2
(2) 4n + 1
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
b7-b0
b15-b8
16
4n + 2
xxxxx
xxxxx
b15-b8
b7-b0
32
4n + 2
b15-b8
b7-b0
xxxxx
xxxxx
8
(1) 4n + 3
(2) 4n + 4
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
b7-b0
b15-b8
16
(1) 4n + 3
(2) 4n + 4
xxxxx
xxxxx
xxxxx
xxxxx
b7-b0
xxxxx
xxxxx
b15-b8
32
(1) 4n + 3
(2) 4n + 4
b7-b0
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
b15-b8
Page 26
TLCS-900H1 CPU
32
4n + 0
4n + 1
4n + 2
4n + 3
xxxxx:
8
(1) 4n + 0
(2) 4n + 1
(3) 4n + 2
(4) 4n + 3
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
b7-b0
b15-b8
b23-b16
b31-b24
16
(1) 4n + 0
(2) 4n + 2
xxxxx
xxxxx
xxxxx
xxxxx
b15-b8
b31-b24
b7-b0
b23-b16
32
4n + 0
b31-b24
b23-b16
b15-b8
b7-b0
8
(1) 4n + 1
(2) 4n + 2
(3) 4n + 3
(4) 4n + 4
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
b7-b0
b15-b8
b23-b16
b31-b24
16
(1) 4n + 1
(2) 4n + 2
(3) 4n + 4
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
b7-b0
b23-b16
xxxxx
xxxxx
b15-b8
b31-b24
32
(1) 4n + 1
(2) 4n + 4
b23-b16
xxxxx
b15-b8
xxxxx
b7-b0
xxxxx
xxxxx
b31-b24
8
(1) 4n + 2
(2) 4n + 3
(3) 4n + 4
(4) 4n + 5
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
b7-b0
b15-b8
b23-b16
b31-b24
16
(1) 4n + 2
(2) 4n + 4
xxxxx
xxxxx
xxxxx
xxxxx
b15-b8
b31-b24
b7-b0
b23-b16
32
(1) 4n + 2
(2) 4n + 4
b15-b8
xxxxx
b7-b0
xxxxx
xxxxx
b31-b24
xxxxx
b23-b16
8
(1) 4n + 3
(2) 4n + 4
(3) 4n + 5
(4) 4n + 6
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
b7-b0
b15-b8
b23-b16
b31-b24
16
(1) 4n + 3
(2) 4n + 4
(3) 4n + 6
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
b7-b0
b23-b16
xxxxx
xxxxx
b15-b8
b31-b24
32
(1) 4n + 3
(2) 4n + 4
b7-b0
xxxxx
xxxxx
b31-b24
xxxxx
b23-b16
xxxxx
b15-b8
During read, indicates the data input to the bus are ignored.
During write, indicates the bus is at high impedance and the write strobe signal is non-active.
Page 27
TLCS-900H1 CPU
(4) Internal Data Bus Format
With the TLCS-900/H1 series, the CPU and the internal memory (built-in ROM or RAM) are connected via
a 32-bit internal data bus. The internal RAM is always accessed by one clock (50ns @ 20 MHz). The internal
ROM is accessed by the interleave method, so that the first bus cycle is accessed by two clocks and the
following address is accessed by one clock. Almost the CPU and the built-in I/Os are connected using an 8/16bit internal data bus. This is because the built-in I/O access speed has little influence on the overall system
operation speed. Overall system operation speed depends largely on the speed of program memory access. The
built-in I/O has two types; high-speed accessing and low-speed accessing. The built-in I/O of the high-speed
accessing is called TLCS-900/H1 type. It is always accessed by two clocks (100ns @ 20 MHz).
On the other hand, the built-in I/O of the low-speed accessing is called TLCS-900/L1 type. It is operates in
sync with the signal devised by four (200ns cycle @ 20 MHz) of the system clock (50ns @ 20 MHz). It is
accessed by five clocks min. (250ns @ 20 MHz) and six clocks max. (300ns @ 20 MHz).
Page 28
TLCS-900H1 CPU
7. Basic Timings
The TLCS-900/H1 series runs with the clock system mentioned in figure 7 (1).
The values in parenthesis represent the frequency of the respective clocks at operation in the 20MHz .
Figure 7 (2) and (3) show the basic bus timing to the external memory. For details, see "Memory controller in
section 3.6" which explains the functions of the derivative products.
[for CPU,900/H1 I/O]
[for 900/L1 I/O]
Figure 7 (1) Clock System
Note: The Figure 7 is one of the TLCS-900/H1 system.
Page 29
TLCS-900H1 CPU
Figure 7 (2) External Read/Write Bus Cycle (0 Wait)
Figure 7 (3) External Read/Write Bus Cycle (1 Wait)
Page 30
TLCS-900/H1 CPU
Appendix A: Details of Instructions
■
Instruction List
[1]
Load
LD
[2]
[5]
[7]
[8]
[9]
LDAR
MIRR
LDIR
LDD
LDDR
CPI
CPIR
CPD
CPDR
Arithmetic operations
ADD
ADC
SUB
SBC
CP
INC
DEC
NEG
EXTZ
EXTS
DAA
PAA
MUL
MULS
DIV
DIVS
MULA
MINC
MDEC
CCF
Logical operations
AND
[6]
LDA
Load Increment/Decrement & Compare Increment/Decrement
LDI
[4]
POP
Exchange
EX
[3]
PUSH
OR
XOR
CPL
Bit operations
LDCF
STCF
ANDCF ORCF
XORCF RCF
SCF
ZCF
BIT
RES
CHG
BS1
SET
TSET
Special operations and CPU control
NOP
EI
DI
PUSH _ SR
POP _ SR
SWI
HALT
LDC
LINK
UNLK
LDF
INCF
DECF
SCC
RL
RR
SLA
SRA
SLL
SRL
CALL
CALR
DJNZ
RET
RETD
Rotate and shift
RLC
RRC
RLD
RRD
Jump, call, and return
JP
JR
JRL
RETI
Page 31
TLCS-900/H1 CPU
■
Explanations of symbols used in this document
dst
Destination: destination of data transfer or operation result load.
src
Source: source of data transfer or operation data read.
num
condition
R
r
Number: numerical value.
Condition: based on flag status.
Eight general-purpose registers including 8/16/32-bit current bank registers.
8-bit registers : W, A, B, C, D, E, H, L (only eight registers)
16-bit registers: WA, BC, DE, HL, IX, IY, IZ, SP (only eight registers)
32-bit registers: XWA, XBC, XDE, XHL, XIX, XIY, XIZ, XSP (only eight registers)
8/16/32-bit general-purpose registers (Please refer to " Register map" on page CPU900-54,55.)
r16
16-bit general-purpose registers (Please refer to " Register map" on page CPU900-54,55.)
r32
32-bit general-purpose registers (Please refer to " Register map" on page CPU900-54,55.)
cr
All 8/16/32-bit CPU control registers
DMAS0 to DMAS7, DMAD0 to DMAD7, DMAC0 to DMAC7, DMAM0 to DMAM7, INTNEST
A
A register (8 bits)
F
Flag registers (8 bits)
F’
Inverse flag registers (8 bits)
SR
Status registers (16 bits)
PC
Program counter (32 bits)
(mem)
8/16/32-bit memory data
mem
Effective address value
<W>
When the operand size is a word, W must be specified.
[]
Operands enclosed in square brackets can be omitted.
#
8/16/32-bit immediate data
#3
3-bit immediate data: 0 to 7 or 1 to 8 ......... for abbreviated codes.
#4
4-bit immediate data: 0 to 15 or 1 to 16
d8
d16
cc
CY
Z
(#8)
(#16)
8-displacement: −80H to +7FH
16-bit displacement: −8000H to +7FFFH
Condition code
Carry flag
Zero flag
Direct addressing: (00H) to (0FFH) ......................... 256-byte area
64 K-byte area addressing: (0000H) to (0FFFFH)
(−r32)
Pre-decrement addressing
(r32+)
Post-increment addressing
$
Start address of instruction
Page 32
TLCS-900/H1 CPU
■
Explanation of symbols in object codes
Page 33
TLCS-900/H1 CPU
m
Memory addressing mode specify code
(XWA)
=
-0--0000
(XBC)
=
-0--0001
(XDE)
=
-0--0010
(XHL)
=
-0--0011
(XIX)
=
-0--0100
(XIY)
=
-0--0101
<7:0> = Indicates the data bit range.
This example means 8-bit data
from bit 0 to bit 7.
(XIZ)
=
-0--0110
(XSP)
=
-0--0111
(XWA + d8)
=
-0--1000
d<7:0>
(XBC + d8)
=
-0--1001
d<7:0>
(XDE + d8)
=
-0--1010
d<7:0>
(XHL + d8)
=
-0--1011
d<7:0>
(XIX + d8)
=
-0--1100
d<7:0>
(XIY + d8)
=
-0--1101
d<7:0>
(XIZ + d8)
=
-0--1110
d<7:0>
(XSP + d8)
=
-0--1111
d<7:0>
(#8)
=
-1--0000
#<7:0>
(#16)
=
-1--0001
#<7:0>
(#24)
=
-1--0010
#<7:0>
(r32)
=
-1--0011
r32’
00
(r32 + d16)
=
-1--0011
r32’
(r32 + r8)
=
-1--0011
(r32 + r16)
=
-1--0011
(−r32)
=
(r32+)
=
r32:
r16
r8:
#<15:8>
#<15:8>
#<23:16>
01
d<7:0>
d<15:8>
000000
11
r32
r8
000001
11
r32
r16
-1--0100
r32’
zz
-1--0101
r32’
zz
zz = Code used to specify the value of
increments or decrements.
00: ±1
01: ±2
10: ±4
11: (Not defined)
r32’ = Upper 6 bits of register code
32-bit register
Signed 16-bit register
Signed 8-bit register
Page 34
TLCS-900/H1 CPU
cc
Condition codes
Code
0000
1000
0110
1110
0111
1111
1101
0101
1110
0110
0100
1100
0100
1100
1001
0001
1010
0010
1111
0111
1011
0011
Symbol
F
(none)
Z
NZ
C
NC
PL or P
MI or M
NE
EQ
OV
NOV
PE
PO
GE
LT
GT
LE
UGE
ULT
UGT
ULE
Description
always False
always True
Zero
Not Zero
Carry
Not Carry
PLus
MInus
Not Equal
EQual
OVerflow
No OVerflow
Parity is Even
Parity is Odd
Greater than or Equal (signed)
Less Than (signed)
Greater Than (signed)
Less than or Equal (signed)
Unsigned Greater than or Equal
Unsigned Less Than
Unsigned Greater Than
Unsigned Less than or Equal
Page 35
Conditional expression
−
−
Z=1
Z=0
C=1
C=0
S=0
S=1
Z=0
Z=1
P/V = 1
P/V = 0
P/V = 1
P/V = 0
(S xor P/V) = 0
(S xor P/V) = 1
[Z or (S xor P/V)] = 0
[Z or (S xor P/V)] = 1
C=0
C=1
(C or Z) = 0
(C or Z) = 1
TLCS-900/H1 CPU
Flag changes
Page 36
TLCS-900/H1 CPU
■
Register map “r”
+3
00H
+2
+1
QW0
( QWA 0)
QA0
< XWA 0>
04H
QB0
( QBC 0)
QC0
08H
QD0
( QDE 0)
QE0
0CH
QH0
( QHL 0)
QL0
< XHL 0>
10H
QW1
( QWA 1)
QA1
< XWA 1>
14H
QB1
( QBC 1)
QC1
18H
QD1
( QDE 1)
QE1
1CH
QH1
( QHL 1)
20H
QW2
( QWA 2)
24H
QB2
28H
QD2
2CH
30H
+0
RW0
( RWA 0)
RA0
< XBC 0>
RB0
( RBC 0)
RC0
< XDE 0>
RD0
( RDE 0)
RE0
RH0
( RHL 0)
RL0
RW1
( RWA 1)
RA1
< XBC 1>
RB1
( RBC 1)
RC1
< XDE 1>
RD1
( RDE 1)
RE1
QL1
< XHL 1>
RH1
( RHL 1)
RL1
QA2
< XWA 2>
RW2
( RWA 2)
RA2
( QBC 2)
QC2
< XBC 2>
RB2
( RBC 2)
RC2
( QDE 2)
QE2
< XDE 2>
RD2
( RDE 2)
RE2
QH2
( QHL 2)
QL2
< XHL 2>
RH2
( RHL 2)
RL2
QW3
( QWA 3)
QA3
< XWA 3>
RW3
( RWA 3)
RA3
34H
QB3
( QBC 3)
QC3
< XBC 3>
RB3
( RBC 3)
RC3
38H
QD3
( QDE 3)
QE3
< XDE 3>
RD3
( RDE 3)
RE3
3CH
QH3
( QHL 3)
QL3
< XHL 3>
RH3
( RHL 3)
RL3
D0H
QW’
( Q WA’)
QA’
< X WA’>
W’
( W A’)
A’
D4H
QB’
( Q BC’)
QC’
< X BC’>
B’
( B C’)
C’
D8H
QD’
( Q DE’)
QE’
< X DE’>
D’
( D E’)
E’
DCH
QH’
( Q HL’)
QL’
< X HL’>
H’
( H L’)
L’
E0H
QW
( Q WA)
QA
< X WA>
W
( W A)
A
E4H
QB
( Q BC)
QC
< X BC>
B
( B C)
C
E8H
QD
( Q DE)
QE
< X DE>
D
( D E)
E
ECH
QH
( Q HL)
QL
< X HL>
H
( H L)
L
F0H
QIXH
( Q IX)
QIXL
< X IX>
IXH
( I X)
IXL
F4H
QIYH
( Q IY)
QIYL
< X IY>
IYH
( I Y)
IYL
F8H
QIZH
( Q IZ)
QIZL
< X IZ>
IZH
( I Z)
IZL
FCH
QSPH
( Q SP)
QSPL
< X SP>
SPH
( S P)
SPL
( ): Word register name (16 bits)
< >: Long word register name (32 bits)
Page 37
Bank 0
Bank 1
Bank 2
Bank 3
Previous
bank
Current
bank
TLCS-900/H1 CPU
■
Control register map"cr"
+3
+2
+1
00H
<DMA S0>
04H
<DMA S1>
08H
<DMA S2>
0CH
<DMA S3>
10H
<DMA S4>
14H
<DMA S5>
18H
<DMA S6>
1CH
<DMA S7>
20H
<DMA D0>
24H
<DMA D1>
28H
<DMA D2>
2CH
<DMA D3>
30H
<DMA D4>
34H
<DMA D5>
38H
<DMA D6>
3CH
<DMA D7>
+0
DMA
Source
Address
DMA
Destination
Address Register
40H
DMAM0
(DMA C0)
44H
DMAM1
(DMA C1)
48H
DMAM2
(DMA C2)
4CH
DMAM3
(DMA C3)
50H
DMAM4
(DMA C4)
54H
DMAM5
(DMA C5)
58H
DMAM6
(DMA C6)
5CH
DMAM7
(DMA C7)
7CH
(INT NEST)
DMA
Counter / Mode
Register
Interrupt Nesting
Register
( ): Word register name (16 bits)
< >: Long word register name (32 bits)
Note: This control register map is particular to TLCS-900/H1. It’s different from conventional TLCS900/L or TLCS-900/H.
Page 38
TLCS-900/H1 CPU
ADC dst, src
< Add with Carry >
Operation:
dst ← dst + src + CY.
Description:
Adds the contents of dst, src, and carry flag, and transfers the result to dst.
Details:
Byte
○
○
Size
Word Long word
○
○
○
○
Mnemonic
ADC
ADC
Code
R, r
r, #
1
1
z
z
1
r
1
0
0
1
0
R
1
1
z
z
1
r
1
1
0
0
1
0
0
1
m
m
m
#<7:0>
#<15:8>
#<23:16>
#<31:24>
○
○
○
○
○
○
○
○
×
ADC
ADC
ADC<W>
R, (mem)
(mem), R
(mem), #
1
m
z
z
m
1
0
0
1
0
1
m
z
z
m
1
0
0
1
1
1
m
0
z
m
m
m
m
0
0
1
1
1
0
0
1
#<7:0>
#<15:8>
Page 39
R
m
m
m
R
TLCS-900/H1 CPU
Flags:
S
Z
H
V
N
C
S
Z
H
V
N
C
*
*
*
*
0
*
= MSB value of the result is set.
= 1 is set if the result is 0, otherwise 0.
= 1 is set if a carry from bit 3 to bit 4 occurs as a result of the operation; otherwise, 0. If the operand
is 32-bit, an undefined value is set.
= 1 is set if an overflow occurs as a result of the operation; otherwise, 0.
= Cleared to zero.
= 1 is set if a carry occurs from the MSB, otherwise 0.
Execution example:
ADC HL, IX
When the HL register = 2000H, the IX register = 3456H, and the carry flag = 1,
execution sets the HL register to 5457H.
Page 40
TLCS-900/H1 CPU
ADD dst, src
< Add >
Operation:
dst ← dst + src.
Description:
Adds the contents of dst to those of src and transfers the result to dst.
Details:
Byte
○
○
Size
Word Long word
○
○
○
○
Mnemonic
ADD
ADD
Code
R, r
r, #
1
1
z
z
1
r
1
0
0
0
0
R
1
1
z
z
1
r
1
1
0
0
1
0
0
0
m
m
m
#<7:0>
#<15:8>
#<23:16>
#<31:24>
○
○
○
○
○
○
○
○
×
ADD
ADD
ADD<W>
R, (mem)
(mem), R
(mem), #
1
m
z
z
m
1
0
0
0
0
1
m
z
z
m
1
0
0
0
1
1
m
0
z
m
m
m
m
0
0
1
1
1
0
0
0
#<7:0>
#<15:8>
Page 41
R
m
m
m
R
TLCS-900/H1 CPU
Flags:
S
*
S
Z
H
V
N
C
Execution example:
Z
*
H
*
V
*
N
0
C
*
= MSB value of the result is set.
= 1 is set if the result is 0, otherwise 0.
= 1 is set if a carry from bit 3 to bit 4 occurs as a result of the operation, otherwise 0. If
the operand is 32-bit, an undefined value is set.
= 1 is set if an overflow occurs as a result of the operation, otherwise 0.
= Cleared to zero.
= 1 is set if a carry occurs from the MSB, otherwise 0.
ADD HL, IX
When the HL register = 2000H and the IX register = 3456H, execution sets the
HL register to 5456H.
Page 42
TLCS-900/H1 CPU
AND dst, src
< And >
Operation:
dst ← dst AND src.
Description:
Ands the contents of dst and src, then transfers the result to dst.
(Truth table)
A
B
A and B
0
0
0
0
1
0
1
0
0
1
1
1
Details:
Byte
○
○
Size
Word Long word
○
○
○
○
Mnemonic
AND
AND
Code
R, r
r, #
1
1
z
z
1
r
1
1
0
0
0
R
1
1
z
z
1
r
1
1
0
0
1
1
0
0
m
m
m
#<7:0>
#<15:8>
#<23:16>
#<31:24>
○
○
○
○
○
○
○
○
×
AND
AND
AND<W>
R, (mem)
(mem), R
(mem), #
1
m
z
z
m
1
1
0
0
0
1
m
z
z
m
1
1
0
0
1
1
m
0
z
m
m
m
m
0
0
1
1
1
1
0
0
#<7:0>
#<15:8>
Page 43
R
m
m
m
R
TLCS-900/H1 CPU
Flags:
S
*
Z
*
V
*
N
0
C
0
=
=
=
=
MSB value of the result is set.
1 is set if the result is 0, otherwise 0.
1 is set.
1 is set if a parity of the result is even, 0 if odd. If the operand is 32 bits, an undefined
value is set.
= Cleared to zero.
= Cleared to zero.
S
Z
H
V
N
C
Execution example:
AND)
H
1
AND　HL, IX
When the HL register = 7350H and the IX register = 3456H,　execution sets the HL
register to 3050H.
0111　0011　0101　0000　← HL register
0011　0100　0101　0110　← IX register
0011　0000　0101　0000　← HL register
Page 44
(before execution)
(before execution)
(after execution)
TLCS-900/H1 CPU
ANDCF num, src
< And Carry Flag >
Operation:
CY ← CY AND src<num>.
Description:
Ands the contents of the carry flag and bit num of src, and transfers the result to the carry
flag.
Details:
Byte
Size
Word Long word
○
○
○
○
○
×
○
×
×
×
×
×
Mnemonic
ANDCF
Code
#4, r
ANDCF
A, r
ANDCF
#3, (mem)
ANDCF
A, (mem)
1
1
0
z
1
r
0
0
1
0
0
0
0
0
0
1
1
0
z
1
0
0
1
0
1
0
0
0
1
m
1
1
m
m
m
m
1
0
0
0
0
1
m
1
1
m
m
m
m
0
0
1
0
1
0
0
0
0
0
#
4
0
r
#3
Note: When bit num is specified by the A register, the value of the lower 4 bits of the A register is
used as bit num. When the operand is a byte and the value of the lower 4 bits of bit num is
from 8 to 15, the result is undefined.
Flags:
S
Z
H
V
N
C
=
=
=
=
=
=
S
Z
H
V
N
C
–
–
–
–
–
*
No change
No change
No change
No change
No change
The value obtained by anding the contents of the carry flag and the bit num of src is
set.
Page 45
TLCS-900/H1 CPU
Execution example:
ANDCF　6, (100H)
When the contents of memory address 100 = 01000000B (binary) and the carry
flag = 1, execution sets the carry flag to 1.
Page 46
TLCS-900/H1 CPU
BIT num, src
< Bit test >
Operation:
Z flag ← inverted value of src<num>
Description:
Transfers the inverted value of the bit num of src to the Z flag.
Details:
Byte
Size
Word Long word
○
○
○
×
×
Flags:
S
×
S
Z
H
V
N
C
Execution example:
=
=
=
=
=
=
BIT
×
Z
*
H
1
Mnemonic
#4, r
BIT
V
×
N
0
Code
#3, (mem)
1
1
0
z
1
0
0
1
1
0
0
0
0
0
1
m
1
1
m
1
1
0
0
1
r
0
1
#
4
m
m
#3
C
–
An undefined value is set.
The inverted value of src<num> is set.
1 is set.
An undefined value is set.
Reset to 0.
No change
BIT　5, (100H)
When the contents of memory address 100 = 00100000B (binary), execution sets
the Z flag to 0.
Page 47
1
m
TLCS-900/H1 CPU
BS1B dst, src
< Bit Search 1 Backward >
Operation:
dst ← src backward searched value
Description:
Searches the src bit pattern backward (from MSB to LSB) for the first bit set to 1 and
transfers the bit number to dst.
Details:
Byte
Size
Word Long word
×
○
×
Mnemonic
BS1B
Code
A, r
1
1
0
1
1
0
0
0
0
1
r
1
1
1
Note: dst in the operand must be the A register; src must be the register in words. If no bit set to
1 is found in the searched bit pattern, sets the A register to an undefined value and the V
flag to 1.
Flags:
S
Z
H
V
N
C
Execution example:
=
=
=
=
=
=
S
Z
H
V
N
C
–
–
–
*
–
–
No change
No change
No change
1 is set if the contents of src are all 0s (no bit is set to 1), otherwise 0.
No change
No change
BS1B A, IX
When the IX register = 1200H, execution sets the A register to 0CH.
Page 48
TLCS-900/H1 CPU
BS1F dst, src
< Bit Search 1 Forward >
Operation:
dst ← src forward searched result
Description:
Searches the src bit pattern forward (from LSB to MSB) for the first bit set to 1 and transfers
the bit number to dst.
Details:
Byte
Size
Word Long word
×
○
×
Mnemonic
BS1F
Code
A, r
1
1
0
1
1
0
0
0
0
1
r
1
1
0
Note: dst in the operand must be the A register; src must be a register in words. If no bit set to
1 is found in the searched bit pattern, sets the A register to an undefined value and the V
flag to 1.
Flags:
S
Z
H
V
C
Execution example:
=
=
=
=
=
S
Z
H
V
N
C
–
–
–
*
–
–
No change
No change
No change
1 is set if the contents of src are all 0s (no bit is set to 1), otherwise 0.N=No change
No change
BS1F A, IX
When the IX register = 1200H, execution sets the A register to 09H.
Page 49
TLCS-900/H1 CPU
CALL condition, dst
< Call subroutine >
Operation:
If cc is true, then XSP ← XSP - 4, (XSP) ← 32-bit PC, PC ← dst.
Description:
If the operand condition is true, saves the contents of the program counter to the stack area
and jumps to the program address specified by dst.
Details:
Mnemonic
CALL
Code
#16
0
0
0
1
1
1
0
0
1
0
1
m
m
m
c
c
#<7:0>
#<15:8>
CALL
#24
0
0
0
1
1
#<7:0>
#<15:8>
#<23:16>
CALL
Flags:
S
Z
H
V
N
C
Execution example:
=
=
=
=
=
=
[cc, ] mem
S
Z
H
V
N
C
–
–
–
–
–
–
1
m
1
1
1
1
1
0
m
No change
No change
No change
No change
No change
No change
CALL 9000H
When the stack pointer XSP is 100H, executing this instruction at memory
address 8000H writes the return address 8003H (long word data) to memory
address 0FCH, sets the stack pointer XSP to 0FCH, and jumps to address
9000H.
Note: The cpu takes the proceeding memory fetch cycle, so that the cpu may read next
program which does not branch. But the program is not used.
Page 50
TLCS-900/H1 CPU
CALR dst
< Call Relative >
Operation:
XSP ← XSP − 4, (XSP) ← 32-bit PC, PC ← dst.
Description:
Saves the contents of the program counter to the stack area and makes a relative jump to the
program address specified by dst.
Details:
Mnemonic
Code
$ + 3 + d16
CALR
0
0
0
1
1
1
1
0
d<7:0>
d<15:8>
Flags:
S
Z
H
V
N
C
=
=
=
=
=
=
S
Z
H
V
N
C
–
–
–
–
–
–
No change
No change
No change
No change
No change
No change
Note: The cpu takes the proceeding memory fetch cycle, so that the cpu may read next program
which does not branch. But the program is not used.
Page 51
TLCS-900/H1 CPU
CCF
< Complement Carry Flag >
Operation:
CY ←inverted value of CY
Description:
Inverts the contents of the carry flag.
Details:
Mnemonic
Code
CCF
Flags:
S
Z
H
V
N
C
Execution example:
=
=
=
=
=
=
0
S
Z
H
V
N
C
–
–
×
–
0
*
0
0
1
0
0
No change
No change
An undefined value is set.
No change
Reset to 0.
Inverted value of itself is set.
When the carry flag = 0, executing CCF sets the carry flag to 1; executing CCF
again sets the carry flag to 0.
Page 52
1
0
TLCS-900/H1 CPU
CHG num, dst
< Change >
Operation:
dst<num> ← Inverted value of dst<num>
Description:
Inverts the value of bit num of dst.
Details:
Byte
Size
Word Long word
○
○
○
×
×
Mnemonic
CHG
×
S
Z
H
V
N
C
=
=
=
=
=
=
Execution example:
#4, r
CHG
Flags:
Code
#3, (mem)
S
Z
H
V
N
C
–
–
–
–
–
–
1
1
0
z
1
0
0
1
1
0
0
0
0
0
1
m
1
1
m
1
1
0
0
0
r
0
1
#
4
m
m
0
m
#3
No change
No change
No change
No change
No change
No change
CHG 5, (100H)
When the contents of memory address 100 = 00100111B (binary), execution sets
the contents to 00000111B (binary).
Page 53
TLCS-900/H1 CPU
CP src1, src2
< Compare >
Operation:
src1 − src2.
Description:
Compares the contents of src1 with those of src2 and indicates the results in flag register F.
Details:
Byte
○
○
○
Size
Word Long word
○
○
○
○
×
○
Mnemonic
CP
CP
CP
Code
R, r
r, #3
r, #
1
1
z
z
1
r
1
1
1
1
0
R
1
1
0
z
1
r
1
1
0
1
1
#3
1
1
z
z
1
r
1
1
0
0
1
1
1
1
m
m
m
#<7:0>
#<15:8>
#<23:16>
#<31:24>
○
○
○
○
○
○
○
○
×
CP
CP
CP<W>
R, (mem)
(mem), R
(mem), #
1
m
z
z
m
1
1
1
1
0
1
m
z
z
m
1
1
1
1
1
1
m
0
z
m
m
m
m
0
0
1
1
1
1
1
1
#<7:0>
#<15:8>
Note: #3 in operands indicates from 0 to 7.
Page 54
R
m
m
m
R
TLCS-900/H1 CPU
Flags:
S
Z
H
V
N
C
S
Z
H
V
N
C
*
*
*
*
1
*
= MSB value of the result is set.
= 1 is set if the result is 0, otherwise 0.
= 1 is set if a borrow from bit 3 to bit 4 occurs as a result of the operation, otherwise 0.
If the operand is 32 bits, an undefined value is set.
= 1 is set if an overflow occurs as a result of the operation, otherwise 0.
= 1 is set.
= 1 is set if a borrow occurs from the MSB bit as a result of the operation, otherwise 0.
Execution example:
CP HL, IX
When the HL register = 1234H and the IX register = 1234H, execution sets the
Z and N flags to 1 and clears the S, H, V, and C flags to zero.
Page 55
TLCS-900/H1 CPU
CPD src1, src2
< Compare Decrement >
Operation:
src1 − src2, BC ← BC − 1.
Description:
Compares the contents of src1 with those of src2, then decrements the contents of the BC
register by 1. src1 must be the A or WA register. src2 must be in post-decrement register
indirect addressing mode.
Details:
Byte
Size
Word Long word
○
○
×
Mnemonic
Code
[A/WA, (R −)]
CPD
1
0
0
z
0
0
0
0
1
0
R
1
1
0
Note: Omitting operands in square brackets [ ] specifies A, (XHL −).
Flags:
S
Z
H
V
N
C
=
=
=
=
=
=
Execution example:
S
Z
H
V
N
C
*
*
*
*
1
–
MSB value of the result of src1 − src2 is set.
1 is set if the result of src1 − src2 is 0, otherwise 0.
1 is set if a borrow from bit 3 to bit 4 occurs as a result of src1 − src2
0 is set if the BC register value is 0 after execution, otherwise 1.
1 is set.
No change
CPD A, (XIX −)
When the XIX register = 00123456H and the BC register = 0200H, execution
compares the contents of the A register with those of memory address 123456H,
then sets the XIX register to 00123455H, the BC register to 01FFH.
Page 56
TLCS-900/H1 CPU
CPDR src1, src2
< Compare Decrement Repeat >
Operation:
src1 − src2, BC ← BC − 1, Repeat until src1 = src2 or BC = 0.
Description:
Compares the contents of src1 with those of src2. Then decrements the contents of the BC
register by 1. Repeats until src1 = src2 or BC = 0. src1 must be the A or WA register. src2
must be in post-decrement register indirect addressing mode.
Details:
Byte
Size
Word Long word
○
○
×
Mnemonic
Code
[A/WA, (R −)]
CPDR
1
0
0
z
0
0
0
0
1
0
R
1
1
1
Note: Omitting operands in square brackets [ ] specifies A, (XHL −).
Flags:
S
Z
H
V
N
C
=
=
=
=
=
=
Execution example:
S
Z
H
V
N
C
*
*
*
*
1
–
MSB value of the result of src1 − src2 is set.
1 is set if the result of src1 − src2 is 0, otherwise 0.
1 is set if a borrow from bit 3 to bit 4 occurs as a result of src1 − src2, otherwise 0.
0 is set if the BC register value is 0 after execution, otherwise 1.
1 is set.
No change
CPDR A, (XIX −)
Under the following conditions, execution reads the contents of memory
addresses 123456H, 123455H, and 123454H. The instruction ends with
condition BC = 0 and sets the XIX register to 00123453H and the BC register to
0000H.
Conditions :
A register = 55H
XIX register = 00123456H
BC register = 0003H
Memory address 123456H = 11H
Memory address 123455H = 22H
Memory address 123454H = 33
Page 57
TLCS-900/H1 CPU
CPI src1, src2
< Compare Increment >
Operation:
src1 − src2, BC ← BC − 1.
Description:
Compares the contents of src1 with those of src2, then decrements the contents of the BC
register by 1. src1 must be the A or WA register. src2 must be in post-increment register
indirect addressing mode.
Details:
Byte
Size
Word Long word
○
○
×
Mnemonic
Code
[A/WA, (R +) ]
CPI
1
0
0
z
0
0
0
0
1
0
R
1
0
0
Note: Omitting operands enclosed in square brackets [ ] specifies A, (XHL +).
Flags:
S
Z
H
V
N
C
=
=
=
=
=
=
Execution example:
S
Z
H
V
N
C
*
*
*
*
1
–
MSB value of the result of src1 − src2 is set.
1 is set if the result of src1 − src2 is 0, otherwise 0.
1 is set if a borrow from bit 3 to bit 4 occurs as a result of src1 − src2, otherwise 0.
0 is set if the BC register value is 0 after execution, otherwise 1.
1 is set.
No change
CPI A, (XIX +)
When the XIX register = 00123456H and the BC register = 0200H, execution
compares the contents of the A register with those of memory address 123456H,
and sets the XIX register to 00123457H and the BC register to 01FFH.
Page 58
TLCS-900/H1 CPU
CPIR src1, src2
< Compare Increment Repeat >
Operation:
src1 − src2, BC ← BC − 1, repeat until src1 = src2 or BC = 0.
Description:
Compares the contents of src1 with those of src2. Then decrements the contents of the BC
register by 1. Repeats until src1 = src2 or BC = 0. src1 must be the A or WA register. src2
must be in post-increment register indirect addressing mode.
Details:
Byte
Size
Word Long word
○
○
×
Mnemonic
Code
[A/WA, (R +)]
CPIR
1
0
0
z
0
0
0
0
1
0
R
1
0
1
Note: Omitting operands in square brackets [ ] specifies A, (XHL +).
Flags:
S
Z
H
V
N
C
=
=
=
=
=
=
Execution example:
S
Z
H
V
N
C
*
*
*
*
1
–
MSB value of the result of src1 − src2 is set.
1 is set if the result of src1 − src2 is 0, otherwise 0.
1 is set if a borrow from bit 3 to bit 4 occurs as a result of src1 − src2, otherwise 0.
0 is set if the BC register value is 0 after execution, otherwise 1.
1 is set.
No change
CPIR A, (XIX +)
Under the following conditions, execution reads memory addresses 123456H,
123457H, and 123458H. The instruction ends with condition src1 = src2, sets
the XIX register to 00123459H and the BC register to 01FDH.
Conditions :
A register = 33H
XIX register = 00123456
HBC register = 0200H
Memory address 123456H = 11H
Memory address 123457H = 22H
Memory address 123458H = 33H
Page 59
TLCS-900/H1 CPU
CPL dst
< Complement >
Operation:
dst ← Ones complement of dst
Description:
Transfers the value of ones complement (inverted bit of 0/1) of dst to dst.
Details:
Byte
Size
Word Long word
○
○
×
Mnemonic
CPL
Flags:
S
Z
H
V
N
C
=
=
=
=
=
=
Execution example:
Code
r
S
Z
H
V
N
C
–
–
1
–
1
–
1
1
0
z
1
0
0
0
0
0
r
1
1
0
No change
No change
1 is set.
No change
1 is set.
No change
CPL WA
When the WA register = 1234H, execution sets the WA register to EDCBH.
Page 60
TLCS-900/H1 CPU
DAA dst
< Decimal Adjust Accumulator >
Operation:
dst ← decimal adjustment of dst
Description:
Decimal adjusts the contents of dst depending on the states of the C, H, and N flags. Used to
adjust the execution result of the add or subtract instruction as binary-coded decimal (BCD).
Details:
Byte
○
Size
Word Long word
×
Mnemonic
×
DAA
C flag
N flag
before DAA before DAA
Operation
instruction instruction
execution execution
ADD
ADC
SUB
SBC
NEG
Code
r
H flag
Upper 4 before DAA
bits of dst instruction
execution
1
1
0
0
1
0
0
0
1
0
r
0
0
0
Lower 4
bits of dst
Added
value
C flag after
DAA
instruction
execution
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0 to 9
0 to 8
0 to 9
A to F
9 to F
A to F
0 to 2
0 to 2
0 to 3
0
0
1
0
0
1
0
0
1
0 to 9
A to F
0 to 3
0 to 9
A to F
0 to 3
0 to 9
A to F
0 to 3
00
06
06
60
66
66
60
66
66
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0 to 9
0 to 8
7 to F
6 to F
0
1
0
1
0 to 9
6 to F
0 to 9
6 to F
00
FA
A0
9A
0
0
1
1
Note: Decimal adjustment cannot be performed for the INC or DEC instruction. This is because
the C flag does not change.
Page 61
TLCS-900/H1 CPU
Flags:
S
Z
H
V
N
C
=
=
=
=
=
=
Execution example:
S
Z
H
V
N
C
*
*
*
*
–
*
MSB value of the result is set.
1 is set if the result is 0, otherwise 0.
1 is set if a carry from bit 3 to bit 4 occurs as a result of the operation, otherwise 0.
1 is set if the parity (number of 1s) of the result is even, otherwise 0.
No change
1 is set if a carry occurs from the MSB as a result of the operation or a carry was 1
before operation, otherwise 0.
ADD A, B
DAA A
When the A register = 59H and the B register = 13H,
execution sets the A register to 72H.
Page 62
TLCS-900/H1 CPU
DEC num, dst
< Decrement >
Operation:
dst ← dst − num.
Description:
Decrements dst by the contents of num and transfers the result to dst.
Details:
Byte
Size
Word Long word
○
○
○
○
○
×
Mnemonic
DEC
Code
#3, r
DEC<W>
#3, (mem)
1
1
z
z
1
r
0
1
1
0
1
#3
1
m
0
z
m
0
1
1
0
1
m
m
m
#3
Note: #3 in operands indicates from 1 to 8; object codes correspond from 1 to 7, 0.
Flags:
S
Z
H
V
N
C
=
=
=
=
=
=
S
Z
H
V
N
C
*
*
*
*
1
–
MSB value of the result is set.
1 is set if the result is 0, otherwise 0.
1 is set if a borrow from bit 3 to bit 4 occurs as a result of the operation, otherwise 0.
1 is set if an overflow occurs as a result of the operation, otherwise 0.
1 is set.
No change
Note: With the DEC #3, r instruction, if the operand is a word or a long word, no flags change.
Execution example:
DEC　4, HL
When the HL register = 5678H, execution sets the HL register to 5674H.
Page 63
TLCS-900/H1 CPU
DECF
< Decrement Register File Pointer >
Operation:
RFP<1:0> ← RFP<1:0> − 1.
Description:
Decrements the contents of register file pointer RFP<1:0> in the status register by 1.
Details:
Mnemonic
Code
DECF
Flags:
S
Z
H
V
N
C
=
=
=
=
=
=
Execution example:
0
S
Z
H
V
N
C
–
–
–
–
–
–
0
0
0
1
1
0
1
No change
No change
No change
No change
No change
No change
DECF
When the contents of RFP<1:0> = 2, execution sets the contents of RFP<1:0> to
1.
Page 64
TLCS-900/H1 CPU
DI
< Disable Interrupt >
Operation:
IFF<2:0> ← 7
Description:
Sets the contents of the interrupt enable flag (IFF) <2:0> in status register to 7. After
execution, only non-maskable interrupts (interrupt level 7) can be received.
Details:
Mnemonic
Code
DI
Flags:
S
Z
H
V
N
C
=
=
=
=
=
=
S
Z
H
V
N
C
–
–
–
–
–
–
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
No change
No change
No change
No change
No change
No change
Note: The instruction execution unit and the bus interface unit in this CPU operate
independently. Therefore if, immediately before an interrupt is generated, the CPU
fetches an instrucion which clears the corresponding interrupt request flag, the CPU
may execute this instruction in between accepting the interrupt and reading the
interrupt vector. In this case, the CPU will read the default vector 0004H.To avoid this, an
instruction which clears an interrupt request flag shoud always be preceded by a DI
instruction.
Page 65
TLCS-900/H1 CPU
DIV dst, src
< Divide >
Operation:
dst<lower half> ← dst ÷ src, dst<upper half> ← remainder (unsigned)
Description:
Divides unsigned the contents of dst by those of src and transfers the quotient to the lower
half of dst, the remainder to the upper half of dst.
Details:
Byte
Size
Word Long word
○
○
○
○
×
×
Mnemonic
DIV
Code
RR, r
DIV
rr, #
1
1
0
z
1
r
0
1
0
1
0
R
1
1
0
z
1
r
0
0
0
0
1
0
1
0
m
m
m
#<7:0>
#<15:8>
○
○
×
DIV
RR, (mem)
1
m
0
z
m
0
1
0
1
0
R
*For RR, see the following page.
Note: When the operation is in bytes, dst (lower byte) ← dst (word) ÷ src (byte),
dst (upper byte) ← remainder.
When the operation is in words, dst (lower word) ← dst (long word) ÷ src (word),
dst (upper word) ← remainder. Match coding of the operand dst with the size of the
dividend.
Flags:
S
Z
H
V
N
C
S
Z
H
V
N
C
–
–
–
V
–
–
=
=
=
=
No change
No change
No change
1 is set when divided by 0 or the quotient exceeds the numerals which can be
expressed in bits of dst for load; otherwise, 0 is set.
= No change
= No change
Page 66
TLCS-900/H1 CPU
Execution example:
DIV XIX, IY
When the XIX register = 12345678H and the IY register = 89ABH, execution
results in a quotient of 21DAH and a remainder of 0FDAH, and sets the XIX
register to 0FDA21DAH.
Note: “ “RR” of the DIV RR, r and DIV RR, (mem) instruction is as listed below.
Operation size in bytes
Operation size in words
(8 bits ← 16 bits ÷ 8 bits)
(16 bits ← 32 bits ÷ 16 bits)
RR
Code "R"
RR
WA
001
XWA
000
BC
011
XBC
001
DE
101
XDE
010
HL
111
XHL
011
XIX
100
XIY
101
XIZ
110
XSP
111
IX
IY
IZ
Specification not
possible!
SP
Code "R"
“rr” of the DIV rr, # instruction is as listed below.
Operation size in bytes
Operation size in words
(8 bits ← 16 bits ÷ 8 bits)
(16 bits ← 32 bits ÷ 16 bits)
rr
Code"r"
rr
WA
001
XWA
Code"r"
000
BC
011
XBC
001
DE
101
XDE
010
HL
111
XHL
011
IX
C7H:F0H
XIX
100
IY
C7H:F4H
XIY
101
IZ
C7H:F8H
XIZ
110
SP
C7H:FCH
XSP
111
1st byte 2nd byte
Notes: Any other long word registers can
be specified in the extension coding.
Notes: Any other word registers can be
specified in the same extension coding
as IX to SP.
Page 67
TLCS-900/H1 CPU
DIVS dst, src
< Divide Signed >
Operation:
dst<lower half> ← dst ÷ src, dst<upper half> ← remainder (signed)
Description:
Divides signed the contents of dst by those of src and transfers the quotient to the lower half
of dst, the remainder to the upper half of dst.
Details:
Byte
Size
Word Long word
○
○
○
○
×
×
Mnemonic
DIVS
Code
RR, r
DIVS
rr, #
1
1
0
z
1
r
0
1
0
1
1
R
1
1
0
z
1
r
0
0
0
0
1
0
1
1
m
m
m
#<7:0>
#<15:8>
○
○
×
DIVS
RR, (mem)
1
m
0
z
m
0
1
0
1
1
R
*For RR, see the following page.
Note: When the operation is in bytes, dst (lower byte) ← dst (word) ÷ src (byte),
dst (upper byte) ← remainder.
When the operation is in words, dst (lower word)¨ dst (long word) ÷ src (word),
dst (upper word) ← remainder.
Match coding of the operand dst with the size of the dividend. The sign of the remainder is
the same as that of the dividend.
Flags:
S
Z
H
V
N
C
S
Z
H
V
N
C
–
–
–
*
–
–
=
=
=
=
No change
No change
No change
1 is set when divided by 0, or the quotient exceeds the value which can be expressed
in bits of the dst used for loading, otherwise 0.
= No change
= No change
Page 68
TLCS-900/H1 CPU
Execution example:
DIV XIX, IY
When the XIX register = 12345678H and the IY register = 89ABH, execution
results in the quotient as 16EEH and the remainder as D89EH, and sets the
XIX register to 16EED89EH.
Note: “RR” of the DIVS RR,r and DIVS RR, (mem) instruction is as listed below.
Operation size in bytes
Operation size in words
(8 bits ← 16 bits ÷ 8 bits)
(16 bits ← 32 bits ÷ 16 bits)
RR
Code "R"
RR
WA
001
XWA
000
BC
011
XBC
001
DE
101
XDE
010
HL
111
XHL
011
XIX
100
XIY
101
XIZ
110
XSP
111
IX
IY
IZ
Specification not
possible!
SP
Code "R"
“rr” of the DIVS rr, # instruction is as listed below.
Operation size in bytes
Operation size in words
(8 bits ← 16 bits ÷ 8 bits)
(16 bits ← 32 bits ÷ 16 bits)
rr
Code "r"
rr
WA
001
XWA
Code "r"
000
BC
011
XBC
001
DE
101
XDE
010
HL
111
XHL
011
IX
C7H:F0H
XIX
100
IY
C7H:F4H
XIY
101
IZ
C7H:F8H
XIZ
110
SP
C7H:FCH
XSP
111
1st byte 2nd byte
Notes: Any other long word registers can
be specified in the extension coding.
Notes: Any other word registers can be
specified in the same extension coding
as those for IX to SP.
Page 69
TLCS-900/H1 CPU
DJNZ dst1, dst2
< Decrement and Jump if Non Zero >
Operation:
dst1 ← dst1 − 1. if dst1 ≠ 0 then PC ← dst2.
Description:
Decrements the contents of dst1 by 1. Makes a relative jump to the program address
specified by dst2 if the result is other than 0.
Details:
Byte
Size
Word Long word
○
○
×
Mnemonic
Code
[r, ]$ + 3/4 + d8
DJNZ
1
1
0
z
1
0
0
0
1
1
r
1
0
0
d<7:0>
Note: $ + 4 + d8 ( “r” is specified using extension codes. )
$ + 3 + d8 (otherwise)
Note: Omitting “r” of the operand in square brackets [ ] is regarded as specifying the B register.
Flags:
S
Z
H
V
N
C
=
=
=
=
=
=
Execution example:
S
Z
H
V
N
C
–
–
–
–
–
–
No change
No change
No change
No change
No change
No change
LOOP :
ADD A, A
DJNZ W, LOOP
DJNZ
W, LOOP
When the A register = 12H and the W register = 03H, execution loops three
times and sets the A register to 24H → 48H → 90H, and the W register to
02H → 01H → 00H.
Page 70
TLCS-900/H1 CPU
EI num
< Enable Interrupt >
Operation:
IFF<2:0> ← num.
Description:
Sets the contents of the IFF<2:0> in the status register to num. After execution, the CPU
interrupt receive level becomes num.
Details:
Mnemonic
EI
Code
[#3]
0
0
0
0
0
0
0
0
0
0
1
1
0
#3
Note: A value from 0 to 7 can be specified as the operand value. If the operand is omitted, the
default value is “0” (EI 0).
Flags:
S
Z
H
V
N
C
=
=
=
=
=
=
S
Z
H
V
N
C
–
–
–
–
–
–
No change
No change
No change
No change
No change
No change
Page 71
TLCS-900/H1 CPU
EX dst, src
< Exchange >
Operation:
dst ↔ src.
Description:
Exchanges the contents of dst and src.
Details:
Byte
Size
Word Long word
Mnemonic
Code
○
×
×
EX
F, F’
0
0
0
1
0
○
○
×
EX
R, r
1
1
z
z
1
r
1
0
1
1
1
R
1
m
z
z
m
0
0
1
1
0
○
○
×
EX
Flags:
S
Z
H
V
N
C
=
=
=
=
=
=
(mem), r
S
Z
H
V
N
C
–
–
–
–
–
–
1
m
1
m
0
m
R
No change
No change
No change
No change
No change
No change
* Executing EX F, F’ changes all flags.
Execution example:
EX A, B
When the A register = 12H and the B register = 34H, execution sets the A
register to 34H and the B register to 12H.
Page 72
TLCS-900/H1 CPU
EXTS dst
< Extend Sign >
Operation:
dst<upper half> ← signed bit of dst<lower half>
Description:
Transfers (copies) the signed bit (bit 7 when the operand size is a word, bit 15 when a long
word) of the lower half of dst to all bits of the upper half of dst.
Details:
Byte
Size
Word Long word
×
○
○
Mnemonic
EXTS
Flags:
S
Z
H
V
N
C
=
=
=
=
=
=
Execution example:
Code
r
S
Z
H
V
N
C
–
–
–
–
–
–
1
1
z
z
1
0
0
0
1
0
r
0
1
1
No change
No change
No change
No change
No change
No change
EXTS HL
When the HL register = 6789H, execution sets the HL register to FF89H.
Page 73
TLCS-900/H1 CPU
EXTZ dst
< Extend Zero >
Operation:
dst<upper half> ← 0.
Description:
Clears the upper half of dst to zero. Used for making the operand sizes the same when they
are different.
Details:
Byte
Size
Word Long word
×
○
○
Mnemonic
EXTZ
Flags:
S
Z
H
V
N
C
=
=
=
=
=
=
Execution example:
Code
r
S
Z
H
V
N
C
–
–
–
–
–
–
1
1
z
z
1
0
0
0
1
0
r
0
1
No change
No change
No change
No change
No change
No change
EXTZ HL
When the HL register = 6789H, execution sets the HL register to 0089H.
EXTZ XIX
When the XIX register = 12345678H, execution sets the XIX register to
00005678H.
Page 74
0
TLCS-900/H1 CPU
HALT
< Halt CPU >
Operation:
CPU halt
Description:
Halts the instruction execution. To resume, an interrupt must be received.
Details:
Mnemonic
Code
HALT
Flags:
S
Z
H
V
N
C
=
=
=
=
=
=
0
S
Z
H
V
N
C
–
–
–
–
–
–
No change
No change
No change
No change
No change
No change
Page 75
0
0
0
0
1
0
1
TLCS-900/H1 CPU
INC num, dst
< Increment >
Operation:
dst ← dst + num.
Description:
Adds the contents of dst and num and transfers the result to dst.
Details:
Byte
Size
Word Long word
○
○
○
○
○
×
Mnemonic
INC
Code
#3, r
INC<W>
#3, (mem)
1
1
z
z
1
r
0
1
1
0
0
#3
1
m
0
z
m
0
1
1
0
0
m
m
m
#3
Note: #3 in operands indicates from 1 to 8 and object codes correspond from 1 to 7, 0.
Flags:
S
Z
H
V
N
C
=
=
=
=
=
=
S
Z
H
V
N
C
*
*
*
*
0
–
MSB value of the result is set.
1 is set if the result is 0, otherwise 0.
1 is set if a carry occurs from bit 3 to bit 4 as a result of the operation, otherwise 0.
1 is set if an overflow occurs as a result of the operation, otherwise 0.
Cleared to zero.
No change
Note: With the INC #3, r instruction, if the operand is a word or a long word, no flags change.
Execution example:
INC 5, WA
When the WA register = 1234H, execution sets the WA register to 1239H.
Page 76
TLCS-900/H1 CPU
INCF
< Increment Register File Pointer >
Operation:
RFP<1:0> ← RFP<1:0> + 1.
Description:
Increments the contents of RFP<1:0> in the status register by 1.
Details:
Mnemonic
Code
INCF
Flags:
S
Z
H
V
N
C
=
=
=
=
=
=
Execution example:
0
S
Z
H
V
N
C
–
–
–
–
–
–
0
0
0
1
1
0
0
No change
No change
No change
No change
No change
No change
INCF
When the contents of RFP<1:0> = 2, execution sets the contents of RFP<1:0> to
3.
Page 77
TLCS-900/H1 CPU
JP condition, dst
< Jump >
Operation:
If cc is true, then PC ← dst.
Description:
If the operand condition is true, jumps to the program address specified by dst.
Details:
Mnemonic
JP
Code
#16
0
0
0
1
1
0
1
0
0
1
1
m
m
m
c
c
#<7:0>
#<15:8>
JP
#24
0
0
0
1
1
#<7:0>
#<15:8>
#<23:16>
JP
Flags:
S
Z
H
V
N
C
=
=
=
=
=
=
Execution example:
[cc, ]mem
S
Z
H
V
N
C
–
–
–
–
–
–
1
m
1
1
1
1
0
1
m
No change
No change
No change
No change
No change
No change
JP 2000H
Execution jumps unconditionally to address 2000H.
JP C, XIX + 2
Execution jumps to address 123458H when carry flag is "1".
Note: The cpu takes the proceeding memory fetch cycle, so that the cpu may read next program
which does not branc. But the program is not used.
Page 78
TLCS-900/H1 CPU
JR condition, dst
< Jump Relative >
Operation:
If cc is true, then PC ← dst.
Description:
If the operand condition is true, makes a relative jump to the program address specified by
dst.
Details:
Mnemonic
Code
[cc, ]$ + 2 + d8
JR
0
1
1
0
c
c
c
c
d<7:0>
[cc, ]$ + 3 + d16
JRL
0
1
1
1
d<7:0>
d<15:8>
Flags:
S
Z
H
V
N
C
=
=
=
=
=
=
Execution example:
S
Z
H
V
N
C
–
–
–
–
–
–
No change
No change
No change
No change
No change
No change
JR 2078H
When this instruction is executed at memory address 2000H, execution relative
jumps unconditionally to address 2078H. The object code of the instruction is
68H : 76H.
Note: The cpu takes the proceeding memory fetch cycle, so that the cpu may read next program
which does not branch. But the program is not used.
Page 79
TLCS-900/H1 CPU
LD dst, src
< Load >
Operation:
dst ← src.
Description:
Loads the contents of src to dst.
Details:
Byte
○
○
○
○
Size
Word Long word
○
○
○
○
○
○
○
○
Mnemonic
LD
LD
LD
LD
Code
R, r
r, R
r, #3
R, #
1
1
z
z
1
r
1
0
0
0
1
R
1
1
z
z
1
r
1
0
0
1
1
R
1
1
z
z
1
r
1
0
1
0
1
#3
0
z
z
z
0
R
#<7:0>
#<15:8>
#<23:16>
#<31:24>
○
○
○
LD
r, #
1
1
z
z
1
0
0
0
0
0
r
0
1
1
m
m
m
#<7:0>
#<15:8>
#<23:16>
#<31:24>
○
○
○
○
○
○
○
○
×
LD
LD
LD <W>
R, (mem)
(mem), R
(#8), #
1
m
z
z
m
0
0
1
0
0
1
m
1
1
m
0
1
z
z
0
0
0
0
0
1
#8
#<7:0>
#<15:8>
Page 80
R
m
m
m
R
0
z
0
TLCS-900/H1 CPU
Byte
Size
Word Long word
○
○
×
Mnemonic
LD<W>
Code
(mem), #
1
m
1
1
m
m
m
m
0
0
0
0
0
0
z
0
#<7:0>
#<15:8>
○
○
×
LD<W>
(#16), (mem)
1
m
0
z
m
m
m
m
0
0
0
1
1
0
0
1
#16<7:0>
#16<15:8>
○
○
×
LD<W>
(mem), (#16)
1
m
1
1
m
m
m
m
0
0
0
1
0
1
z
0
#16<7:0>
#16<15:8>
Flags:
S
Z
H
V
N
C
=
=
=
=
=
=
Execution example:
S
Z
H
V
N
C
–
–
–
–
–
–
No change
No change
No change
No change
No change
No change
LD IX, DE
When the DE register = 4567H, execution sets the IX register to 4567H.
Page 81
TLCS-900/H1 CPU
LDA dst, src
< Load Address >
Operation:
dst ← src effective address value
Description:
Loads the src effective address value to dst.
Details:
Byte
Size
Word Long word
×
○
○
Mnemonic
LDA
Code
R, mem
1
m
1
1
m
0
0
1
s
0
m
m
m
R
Note: This instruction operates much like the ADD instruction; the difference is that dst is
specified independently from src. Mainly used for handling the pointer with the C
compiler.
Flags:
S
Z
H
V
N
C
=
=
=
=
=
=
Execution example:
S
Z
H
V
N
C
–
–
–
–
–
–
No change
No change
No change
No change
No change
No change
LDA XIX, XIY + 33H
When the XIY register = 00123456H, execution sets the XIX register to
00123489H.
Note: Though the LDA instruction can use 32-bit width,the width of CPU address bus is 24-bit.
Page 82
TLCS-900/H1 CPU
LDAR dst, src
< Load Address Relative >
Operation:
dst ← src relative address value
Description:
Loads the relative address value specified in src to dst.
Details:
Byte
Size
Word Long word
×
○
○
Mnemonic
Code
R, $ + 4 + d16
LDAR
1
1
1
1
0
0
1
1
0
0
0
1
0
0
1
1
d<7:0>
d<15:8>
0
Flags:
S
Z
H
V
N
C
=
=
=
=
=
=
Execution example:
S
Z
H
V
N
C
–
–
–
–
–
–
0
1
s
0
R
No change
No change
No change
No change
No change
No change
LDAR XIX, $ + 1345H
When this instruction is executed at memory address 1000H, execution sets the
XIX register to 00002345H. $ indicates the start address of the instruction. The
instruction’s object codes are: F3H: 13H: 41H: 13H: 34H.
Page 83
TLCS-900/H1 CPU
LDC dst, src
< Load Control Register >
Operation:
dst ← src.
Description:
Loads the contents of src to dst.
Details:
Byte
Size
Word Long word
○
○
○
Mnemonic
LDC
Code
cr, r
1
1
z
z
1
0
0
1
0
1
r
1
1
0
cr
○
○
○
LDC
r, cr
1
1
z
z
1
0
0
1
0
1
r
1
1
1
cr
Flags:
S
Z
H
V
N
C
=
=
=
=
=
=
Execution example:
S
Z
H
V
N
C
–
–
–
–
–
–
No change
No change
No change
No change
No change
No change
LDC DMAC0, WA
When the WA register = 1234H, execution sets control register DMAC0 to
1234H.
Page 84
TLCS-900/H1 CPU
LDCF num, src
< Load Carry Flag >
Operation:
CY ← src<num>.
Description:
Loads the contents of bit num of src to the carry flag.
Details:
Byte
Size
Word Long word
○
○
○
○
○
×
○
×
×
×
×
×
Mnemonic
LDCF
Code
#4, r
LDCF
A, r
LDCF
#3, (mem)
LDCF
A, (mem)
1
1
0
z
1
r
0
0
1
0
0
0
0
0
0
1
1
0
z
1
0
0
1
0
1
0
1
1
1
m
1
1
m
m
m
m
1
0
0
1
1
1
m
1
1
m
m
m
m
0
0
1
0
1
0
1
1
0
1
#
4
1
r
#3
Note: When bit num is specified by the A register, the value of the lower 4 bits of the A register is
used as bit num. When the operand is a byte and the value of the lower 4 bits of bit num is
from 8 to 15, the value of the carry flag is undefined.
Flags:
S
Z
H
V
N
C
=
=
=
=
=
=
S
Z
H
V
N
C
–
–
–
–
–
*
No change
No change
No change
No change
No change
Contents of bit num of src is set.
Page 85
TLCS-900/H1 CPU
Execution example:
LDCF 6, (100H)
When the contents of memory at address 100 = 01000000B (binary), execution
sets the carry flag to 1.
Page 86
TLCS-900/H1 CPU
LDD dst, src
< Load Decrement >
Operation:
dst ← src, BC ← BC − 1.
Description:
Loads the contents of src to dst, then decrements the contents of the BC register by 1. src
and dst must be in post-decrement register indirect addressing mode.
Details:
Byte
Size
Word Long word
○
○
○
○
×
×
Mnemonic
LDD<W>
LDD<W>
Code
[(XDE −), (XHL −)]
(XIX −), (XIY −)
1
0
0
z
0
0
1
1
0
0
0
1
0
0
1
0
1
0
0
z
0
1
0
1
0
0
0
1
0
0
1
0
* Coding in square brackets [ ] can be omitted.
Flags:
S
Z
H
V
N
C
Execution example:
=
=
=
=
=
=
S
Z
H
V
N
C
–
–
0
*
0
–
No change
No change
Cleared to 0.
0 is set if the BC register value is 0 after execution, otherwise 1.
Cleared to zero.
No change
LDD (XIX −), (XIY −)
When the XIX register = 00123456H, the XIY register = 00335577H, and the
BC register = 0700H, execution loads the contents at address 335577 to address
123456H and sets the XIX register to 123455H, the XIY register to 00335576H,
and the BC register to 06FFH.
Page 87
TLCS-900/H1 CPU
LDDR dst, src
< Load Decrement Repeat >
Operation:
dst ← src, BC ← BC − 1, repeat until BC = 0.
Description:
Loads the contents of src to dst, then decrements the contents of the BC register by 1. If the
result is other than 0, the operation is repeated. src and dst must be in post-decrement
register indirect addressing mode.
Details:
Byte
Size
Word Long word
○
○
○
○
×
×
Mnemonic
Code
LDDR<W> [(XDE −), (XHL −)]
LDDR<W> (XIX −), (XIY −)
1
0
0
z
0
0
1
1
0
0
0
1
0
0
1
1
1
0
0
z
0
1
0
1
0
0
0
1
0
0
1
1
* Coding in square brackets [ ] can be omitted.
Note: Interrupt requests are sampled every time 1 item of data is loaded.
Flags:
S
Z
H
V
N
C
Execution example:
=
=
=
=
=
=
S
Z
H
V
N
C
–
–
0
0
0
–
No change
No change
Cleared to zero.
Cleared to zero.
Cleared to zero.
No change
LDDR (XIX −), (XIY −)
When the XIX register = 00123456H, the XIY register = 00335577H, and the
BC register = 0003H, the results of the execution are as follows:
Loads the contents of address 335577H to 123456H.
Loads the contents of address 335576H to 123455H.
Loads the contents of address 335575H to 123454H.
Sets the XIX register to 00123453H.
Sets the XIY register to 00335574H.
Sets the BC register to 0000H.
Note: When the BC register is 0000H, the cpu executes one more memory read cycle(example
0033557H). But the read data is not used.
Page 88
TLCS-900/H1 CPU
LDF num
< Load Register File Pointer >
Operation:
RFP<1:0> ← num.
Description:
Loads the num value to the register file pointer RFP<1:0> in status register.
Details:
Mnemonic
LDF
Code
#2
0
0
0
1
0
1
0
0
0
0
0
0
1
1
# 2
Note: In minimum mode, the operand value can be specified from 0 to 7; in maximum mode,
from 0 to 3.
Flags:
S
Z
H
V
N
C
=
=
=
=
=
=
S
Z
H
V
N
C
–
–
–
–
–
–
No change
No change
No change
No change
No change
No change
Page 89
TLCS-900/H1 CPU
LDI dst, src
< Load Increment >
Operation:
dst ← src, BC ← BC − 1.
Description:
Loads the contents of src to dst, then decrements the contents of the BC register by 1. src
and dst must be in post-increment register indirect addressing mode.
Details:
Byte
Size
Word Long word
○
○
○
○
×
×
Mnemonic
Code
LDI<W> [(XDE +), (XHL +)]
LDI<W> (XIX +), (XIY +)
1
0
0
z
0
0
1
1
0
0
0
1
0
0
0
0
1
0
0
z
0
1
0
1
0
0
0
1
0
0
0
0
* Coding in square brackets [ ] can be omitted.
Flags:
S
Z
H
V
N
C
Execution example:
=
=
=
=
=
=
S
Z
H
V
N
C
–
–
0
*
0
–
No change
No change
Cleared to zero.
0 is set when the BC register value is 0 after execution, otherwise 1.
Cleared to zero.
No change
LDI (XIX +), (XIY +)
When the XIX register = 00123456H, the XIY register = 00335577H, and the
BC register = 0700H, execution loads the contents of address 335577H to
123456H and sets the XIX register to 00123457H, the XIY register to
00335578H, and the BC register to 06FFH.
Page 90
TLCS-900/H1 CPU
LDIR dst, src
< Load Increment Repeat >
Operation:
dst ← src, BC ← BC − 1, repeat until BC = 0.
Description:
Loads the contents of src to dst, then decrements the contents of the BC register by 1. If the
result is other than 0, the operation is repeated. src and dst must be in post-increment
register indirect addressing mode.
Details:
Byte
Size
Word Long word
○
○
○
○
×
×
Mnemonic
LDIR<W>
LDIR<W>
Code
[(XDE +), (XHL +)]
(XIX +), (XIY +)
1
0
0
z
0
0
1
1
0
0
0
1
0
0
0
1
1
0
0
z
0
1
0
1
0
0
0
1
0
0
0
1
* Coding in square brackets [ ] can be omitted.
Note: Interrupt requests are sampled every time 1 item of data is loaded.
Flags:
S
Z
H
V
N
C
Execution example:
=
=
=
=
=
=
S
Z
H
V
N
C
–
–
0
0
0
–
No change
No change
Cleared to zero.
Cleared to zero.
Cleared to zero.
No change
LDIR (XIX +), (XIY +)
When the XIX register = 00123456H, the XIY register = 00335577H, and the
BC register = 0003H, execution results as follows:
Loads the contents of address 335577H to 123456H.
Loads the contents of address 335578H to 123457H.
Loads the contents of address 335579H to 123458H.
Sets the XIX register to 00123459H.
Sets the XIY register to 0033557AH.
Sets the BC register to 0000H.
Note: When the BC register is 0000H, the cpu executes one more memory read cycle(example
0033557H). But the read data is not used.
Page 91
TLCS-900/H1 CPU
LINK dst, num
< Link >
Operation:
(− XSP) ← dst, dst ← XSP, XSP ← XSP + num.
Description:
Saves the contents of dst to the stack area. Loads the contents of stack pointer XSP to dst.
Adds the contents of XSP to those of num (signed) and loads the result to XSP. Used for
obtaining a local variable area in the stack area for − num bytes.
Details:
Byte
Size
Word Long word
×
×
○
Mnemonic
LINK
Code
r, d16
1
1
1
0
1
0
0
0
0
1
r
1
0
0
d<7:0>
d<15:8>
Flags:
S
Z
H
V
N
C
Execution example:
=
=
=
=
=
=
S
Z
H
V
N
C
–
–
–
–
–
–
No change
No change
No change
No change
No change
No change
LINK XIZ, −40H
When stack pointer XSP = 280H and the XIZ register = 290H, execution writes
00000290H (long data) at memory address 27CH and sets the XIZ register to
27CH and the stack pointer to XSP 23CH.
Page 92
TLCS-900/H1 CPU
MDEC1 num, dst
< Modulo Decrement 1 >
Operation:
if (dst mod num) = 0 then dst ← dst + (num − 1) else dst ← dst − 1.
Description:
When the modulo num of dst is 0, increments dst by num − 1.
Otherwise, decrements dst by 1. Used to operate pointers for cyclic memory table.
Details:
Byte
Size
Word Long word
×
○
×
Mnemonic
MDEC1
Code
#, r
1
1
0
1
1
0
0
1
1
1
#<7:0>
r
1
0
0
1
#<15:8>
Note: The operand # must be 2 to the nth power. (n = 1 to 15)
Flags:
S
Z
H
V
N
C
Execution example:
=
=
=
=
=
=
S
Z
H
V
N
C
–
–
–
–
–
–
No change
No change
No change
No change
No change
No change
Decrements the IX register by cycling from 1230H to 1237H.
MDEC1 8, IX
When the IX register = 1231H, execution sets the IX register to 1230H. Further
execution increments the IX register by 8 − 1 and sets the IX register to 1237H,
since the IX register modulo 8 = 0.
Page 93
TLCS-900/H1 CPU
MDEC2 num, dst
< Modulo Decrement 2 >
Operation:
if (dst mod num) = 0 then dst ← dst + (num − 2) else dst ← dst − 2.
Description:
When the modulo num of dst is 0, increments dst by num − 2.
Otherwise, decrements dst by 2. Used to operate pointers for cyclic memory table.
Details:
Byte
Size
Word Long word
×
○
×
Mnemonic
MDEC2
Code
#, r
1
1
0
1
1
0
0
1
1
1
#<7:0>
r
1
0
1
2
#<15:8>
Note: The operand # must be 2 to the nth power. (n = 2 to 15)
Flags:
S
Z
H
V
N
C
Execution example:
=
=
=
=
=
=
S
Z
H
V
N
C
–
–
–
–
–
–
No change
No change
No change
No change
No change
No change
Decrements the IX register by cycling from 1238H to 123FH.
MDEC2 8, IX
When the IX register = 123AH, execution sets the IX register to 1238H.
Further execution increments the IX register by 8 − 2 and sets the IX register
to 123EH, since the IX register modulo 8 = 0.
Page 94
TLCS-900/H1 CPU
MDEC4 num, dst
< Modulo Decrement 4 >
Operation:
if (dst mod num) = 0 then dst ← dst + (num − 4) else dst ← dst − 4.
Description:
When the modulo num of dst is 0, increments dst by num − 4. Otherwise, decrements dst by
4. Used to operate pointers for cyclic memory table.
Details:
Byte
Size
Word Long word
×
○
×
Mnemonic
MDEC4
Code
#, r
1
1
0
1
1
0
0
1
1
1
#<7:0>
r
1
1
4
#<15:8>
Note: The operand # must be 2 to the nth power. (n = 3 to 15)
Flags:
S
Z
H
V
N
C
Execution example:
=
=
=
=
=
=
S
Z
H
V
N
C
–
–
–
–
–
–
No change
No change
No change
No change
No change
No change
Decrements the IX register by cycling from 1280H to 12FFH.
MDEC4 80H, IX
When the IX register = 1284H, execution sets the IX register to 1280H.
Further execution increments the IX register by 80H − 4 and sets the IX
register to 12FCH, since the IX register modulo 80H = 0.
Page 95
0
TLCS-900/H1 CPU
MINC1 num, dst
< Modulo Increment 1 >
Operation:
if (dst mod num) = (num − 1) then dst ← dst − (num − 1) else dst ← dst + 1.
Description:
When the modulo num of dst is num − 1, decrements dst by num − 1.
Otherwise, increments dst by 1. Used to operate pointers for cyclic memory table.
Details:
Byte
Size
Word Long word
×
○
×
Mnemonic
MINC1
Code
#, r
1
1
0
1
1
0
0
1
1
1
#<7:0>
r
0
0
0
1
#<15:8>
Note: The operand # must be 2 to the nth power. (n = 1 to 15)
Flags:
S
Z
H
V
N
C
Execution example:
=
=
=
=
=
=
S
Z
H
V
N
C
–
–
–
–
–
–
No change
No change
No change
No change
No change
No change
Increments the IX register by cycling from 1200H to 1207H.
MINC1 8, IX
When the IX register = 1206H, execution sets the IX register to 1207H.
Further execution decrements the IX register by 8 − 1 and sets the IX register
to 1200H, since the IX register modulo 8 = 8 − 1.
Page 96
TLCS-900/H1 CPU
MINC2 num, dst
< Modulo Increment 2 >
Operation:
if (dst mod num) = (num − 2) then dst ← dst − (num − 2) else dst ← dst + 2.
Description:
When the modulo num of dst is num − 2, decrements dst by num − 2
Otherwise, increments dst by 2. Used to operate pointers for cyclic memory table.
Details:
Byte
Size
Word Long word
×
○
×
Mnemonic
MINC2
Code
#, r
1
1
0
1
1
0
0
1
1
1
#<7:0>
r
0
0
1
2
#<15:8>
Note: The operand # must be 2 to the nth power. (n = 2 to 15)
Flags:
S
Z
H
V
N
C
Execution example:
=
=
=
=
=
=
S
Z
H
V
N
C
–
–
–
–
–
–
No change
No change
No change
No change
No change
No change
Increments the IX register by cycling from 1230H to 1237H.
MINC2 8, IX
When the IX register = 1234H, execution sets the IX register to 1236H. Further
execution decrements the IX register by 8 − 2 and sets the IX Register to
1230H, since the IX register modulo 8 = 8 − 2.
Page 97
TLCS-900/H1 CPU
MINC4 num, dst
< Modulo Increment 4 >
Operation:
if (dst mod num) = (num − 4) then dst ← dst − (num − 4) else dst ← dst + 4.
Description:
When the modulo num of dst is num − 4, decrements dst bynum − 4.
Otherwise, increments dst by 4. Used to operate pointers for cyclic memory table.
Details:
Byte
Size
Word Long word
×
○
×
Mnemonic
MINC4
Code
#, r
1
1
0
1
1
0
0
1
1
1
#<7:0>
r
0
1
4
#<15:8>
Note: The operand # must be 2 to the nth power. (n = 3 to 15)
Flags:
S
Z
H
V
N
C
Execution example:
=
=
=
=
=
=
S
Z
H
V
N
C
–
–
–
–
–
–
No change
No change
No change
No change
No change
No change
Increments the IX register by cycling from 1240H to 127FH.
MINC4 40H, IX
When the IX register = 1278H, execution sets the IX register to 127CH.
Further execution decrements the IX register by 40H − 4 and sets the IX
register to 1240H, since the IX register modulo 40H = 40H − 4.
Page 98
0
TLCS-900/H1 CPU
MIRR dst
< Mirror >
Operation:
dst<MSB:LSB> ← dst<LSB:MSB>.
Description:
Mirror-exchanges the contents of dst using the bit pattern image.
Details:
Byte
Size
Word Long word
×
○
×
Mnemonic
MIRR
Flags:
S
Z
H
V
N
C
Execution example:
=
=
=
=
=
=
Code
r
S
Z
H
V
N
C
–
–
–
–
–
–
1
1
0
1
1
0
0
0
1
0
r
1
1
0
No change
No change
No change
No change
No change
No change
MIRR HL
When the HL register = 0001 0010 0011 0100B (binary), execution sets the HL
register to 0010 1100 0100 1000B (binary).
Page 99
TLCS-900/H1 CPU
MUL dst, src
< Multiply >
Operation:
dst ← dst<lower half> × src (unsigned)
Description:
Multiplies unsigned the contents of lower half of dst by those of src and loads the result to
dst.
Details:
Byte
Size
Word Long word
○
○
○
○
×
Mnemonic
MUL
×
Code
RR, r
MUL
rr, #
1
1
0
z
1
r
0
1
0
0
0
R
1
1
0
z
1
r
0
0
0
0
1
0
0
0
m
m
m
#<7:0>
#<15:8>
○
○
×
MUL
RR, (mem)
1
m
0
z
m
0
1
0
0
0
R
Note: When the operation is in bytes, dst (word) ← dst (byte) × src (byte).
When the operation is in words, dst (long word) ← dst (word) × src (word)
Match coding of the operand dst with the size of the result.
Flags:
S
Z
H
V
N
C
Execution example:
=
=
=
=
=
=
S
Z
H
V
N
C
–
–
–
–
–
–
No change
No change
No change
No change
No change
No change
MUL XIX, IY
When the IX register = 1234H and the IY register = 89ABH, execution
multiplies unsigned the contents of the IX register by those of the IY register
and sets the XIX register to 09C9FCBCH.
Page 100
TLCS-900/H1 CPU
Note: “RR” for the MUL RR, r and MUL RR, (mem) instructions is as listed below:
Operation size in bytes
Operation size in words
(16 bits ← 8 bits × 8 bits)
(32 bits ← 16 bits × 16 bits)
RR
Code "R"
RR
WA
001
XWA
000
BC
011
XBC
001
DE
101
XDE
010
HL
111
XHL
011
XIX
100
XIY
101
XIZ
110
XSP
111
IX
IY
IZ
Specification not
possible !
SP
Code "R"
“rr” of the MUL rr, # instruction is as listed below.
Operation size in bytes
Operation size in words
(16 bits ← 8 bits × 8 bits)
(32 bits ← 16 bits × 16 bits)
rr
Code "r"
rr
WA
001
XWA
Code "r"
000
BC
011
XBC
001
DE
101
XDE
010
HL
111
XHL
011
IX
C7H:F0H
XIX
100
IY
C7H:F4H
XIY
101
IZ
C7H:F8H
XIZ
110
SP
C7H:FCH
XSP
111
Note: Any other long word registers can
be specified in the extension coding.
1st byte 2nd byte
Note: Any other word registers can be
specified in the same extension coding
as those for IX to SP.
Page 101
TLCS-900/H1 CPU
MULA dst
< Multiply and Add >
Operation:
dst ← dst + (XDE) × (XHL), XHL ← XHL − 2.
Description:
Multiplies signed the memory data (16 bits) specified by the XDE register by the memory
data (16 bits) specified by the XHL register. Adds the result (32 bits) to the contents of dst
(32 bits) and loads the sum to dst (32 bits). Then, decrements the contents of the XHL
register by 2.
Details:
Byte
Size
Word Long word
×
○
×
Mnemonic
MULA
Code
rr
1
1
0
1
1
0
0
0
1
1
r
0
0
1
Note: Match coding of the operand dst with the operation size (long word).
Flags:
S
Z
H
V
N
C
Execution example:
=
=
=
=
=
=
S
Z
H
V
N
C
*
*
–
*
–
–
MSB value of the result is set.
1 is set when the result is 0, otherwise 0.
No change
1 is set when an overflow occurs as a result, otherwise 0.
No change
No change
MULA XIX
Under the following conditions, execution sets the XIX register to 4795FCBCH
and the XHL register to 1FEH.
Conditions:
XIX register = 50000000H
XDE register = 100H
XHL register = 200H
Memory data (word) at address 100H = 1234H
Memory data (word) at address 200H = 89ABH
Page 102
TLCS-900/H1 CPU
MULS dst, src
< Multiply Signed >
Operation:
dst ← dst<lower half> × src (signed)
Description:
Multiplies signed the contents of the lower half of dst by those of src and loads the result to
dst.
Details:
Byte
Size
Word Long word
○
○
○
○
×
Mnemonic
MULS
×
Code
RR, r
MULS
rr, #
1
1
0
z
1
r
0
1
0
0
1
R
1
1
0
z
1
r
0
0
0
0
1
0
0
1
m
m
m
#<7:0>
#<15:8>
○
○
×
MULS
RR, (mem)
1
m
0
z
m
0
1
0
0
1
R
Note: When the operation is in bytes, dst (word) ← dst (byte) × src (byte).
When the operation is in words, dst (long word) ← dst (word)× src (word).
Match coding of the operand dst with the size of the result.
Flags:
S
Z
H
V
N
C
Execution example:
=
=
=
=
=
=
S
Z
H
V
N
C
–
–
–
–
–
–
No change
No change
No change
No change
No change
No change
MULS XIX, IY
When the IX register = 1234H and the IY register = 89ABH, execution
multiplies signed the contents of the IX register by those of the IY register and
sets the XIX register to F795FCBCH.
Page 103
TLCS-900/H1 CPU
Note: “RR” for the MULS RR,r and MULS RR, (mem) instructions is as listed below:
Operation size in bytes
Operation size in word
(16 bits ← 8 bits × 8 bits)
(32 bits ← 16 bits × 16 bits)
RR
Code R
RR
WA
001
XWA
000
BC
011
XBC
001
DE
101
XDE
010
HL
111
XHL
011
XIX
100
XIY
101
XIZ
110
XSP
111
IX
IY
IZ
Specification not
possible !
SP
Code R
“rr” for the MULS rr, # instruction is as listed below.
Operation size in bytes
Operation size in words
(16 bits ← 8 bits × 8 bits)
(32 bits ← 16 bits × 16 bits)
rr
Code r
rr
WA
001
XWA
Code r
000
BC
011
XBC
001
DE
101
XDE
010
HL
111
XHL
011
IX
C7H:F0H
XIX
100
IY
C7H:F4H
XIY
101
IZ
C7H:F8H
XIZ
110
SP
C7H:FCH
XSP
111
*2 Any other long word registers can be
specified in the extension coding.
1st byte 2nd byte
*1 Any other word registers can be
specified in the same extension coding
as those for IX to SP.
Page 104
TLCS-900/H1 CPU
NEG dst
< Negate >
Operation:
dst ← 0 − dst.
Description:
Decrements 0 by the contents of dst and loads the result to dst.
(Twos complement)
Details:
Byte
Size
Word Long word
○
○
×
Mnemonic
NEG
Flags:
S
Z
H
V
N
C
Execution example:
=
=
=
=
=
=
Code
r
S
Z
H
V
N
C
*
*
*
*
1
*
1
1
0
z
1
0
0
0
0
0
r
1
1
MSB value of the result is set.
1 is set when the result is 0, otherwise 0.
1 is set when a borrow from bit 3 to bit 4 occurs as a result, otherwise 0.
1 is set when an overflow occurs as a result, otherwise 0.
1 is set.
1 is set when a borrow from the MSB occurs as a result, otherwise 0.
NEG IX
When the IX register = 0002H, execution sets the IX register to FFFEH.
Page 105
1
TLCS-900/H1 CPU
NOP
< No Operation >
Operation:
None
Description:
Does nothing but moves execution to the next instruction. The object code of this instruction
is 00H.
Details:
Mnemonic
Code
NOP
Flags:
S
Z
H
V
N
C
=
=
=
=
=
=
0
S
Z
H
V
N
C
–
–
–
–
–
–
No change
No change
No change
No change
No change
No change
Page 106
0
0
0
0
0
0
0
TLCS-900/H1 CPU
OR dst, src
< Logical Or >
Operation:
dst ← dst OR src.
Description:
Ors the contents of dst with those of src and loads the result to dst.
(Truth table)
A
B
A OR B
0
0
0
0
1
1
1
0
1
1
1
1
Details:
Byte
○
○
Size
Word Long word
○
○
○
○
Mnemonic
OR
OR
Code
R, r
r, #
1
1
z
z
1
r
1
1
1
0
0
R
1
1
z
z
1
r
1
1
0
0
1
1
1
0
m
m
m
#<7:0>
#<15:8>
#<23:16>
#<31:24>
○
○
○
○
○
○
○
○
×
OR
OR
OR<W>
R, (mem)
(mem), R
(mem), #
1
m
z
z
m
1
1
1
0
0
1
m
z
z
m
1
1
1
0
1
1
m
0
z
m
m
m
m
0
0
1
1
1
1
1
0
#<7:0>
#<15:8>
Page 107
R
m
m
m
R
TLCS-900/H1 CPU
Flags:
S
Z
H
V
N
C
Execution example:
OR)
S
Z
H
V
N
C
*
*
0
*
0
0
=
=
=
=
MSB value of the result is set.
1 is set when the result is 0, otherwise 0.
0 is set.
1 is set when the parity (number of 1s) of the result is even, 0 when odd.
When the operand is 32-bit, an undefined value is set.
= Cleared to 0.
= Cleared to 0.
OR HL, IX
When the HL register = 7350H and the IX register is 3456H, execution sets the
HL register to 7756H.
0111　0011　0101　0000　← HL register(before execution)
0011　0100　0101　0110　← IX register(before execution)
0111　0111　0101　0110　← HL register(after execution)
Page 108
TLCS-900/H1 CPU
ORCF num, src
< Or Carry Flag >
Operation:
CY ← CY OR src<num>.
Description:
Ors the contents of the carry flag with those of bit num of src and loads the result to the
carry flag.
Details:
Byte
Size
Word Long word
○
○
○
○
○
×
○
×
×
×
×
×
Mnemonic
ORCF
Code
#4, r
ORCF
A, r
ORCF
#3, (mem)
ORCF
A, (mem)
1
1
0
z
1
r
0
0
1
0
0
0
0
0
0
1
1
0
z
1
0
0
1
0
1
0
0
1
1
m
1
1
m
m
m
m
1
0
0
0
1
1
m
1
1
m
m
m
m
0
0
1
0
1
0
0
1
0
0
#
4
1
r
#3
Note: When bit num is specified by the A register, the value of the lower 4 bits of the A register is used as bit
num. When the operand is a byte and the value of the lower bits of bit num is from 8 to 15, the result is
undefined.
Flags:
S
Z
H
V
N
C
=
=
=
=
=
=
S
Z
H
V
N
C
–
–
–
–
–
*
No change
No change
No change
No change
No change
The result of or-ing the contents of the carry flag with those of bit num of src is set.
Page 109
TLCS-900/H1 CPU
Execution example:
ORCF 6, (100H)
When the contents of memory at address 100H = 01000000B (binary) and the
carry flag = 0, execution sets the carry flag to 1.
Page 110
TLCS-900/H1 CPU
PAA dst
< Pointer Adjust Accumulator >
Operation:
if dst <LSB> = 1 then dst ← dst + 1.
Description:
Increments dst by 1 when the LSB of dst is 1. Does nothing when the LSB of dst is 0.
Used to make the contents of dst even.
Details:
Byte
Size
Word Long word
×
○
○
Mnemonic
PAA
Flags:
S
Z
H
V
N
C
Execution example:
=
=
=
=
=
=
Code
r
S
Z
H
V
N
C
–
–
–
–
–
–
1
1
z
z
1
0
0
0
1
0
r
1
0
0
No change
No change
No change
No change
No change
No change
PAA XIZ
When the XIZ register = 00234567H, execution increments the XIZ register by 1
so that it becomes 00234568H.
Page 111
TLCS-900/H1 CPU
POP dst
< Pop >
Operation:
dst ← (XSP +).
: dst ← (XSP), XSP ← XSP + 1
: dst ← (XSP), XSP ← XSP + 2
: dst ← (XSP), XSP ← XSP + 4
Description:
First loads the contents of memory address specified by the stack pointer XSP to dst. Then
increments the stack pointer XSP by the number of bytes in the operand.
In bytes
In words
In long words
Details:
Byte
Size
Word Long word
Mnemonic
Code
○
×
×
POP
F
0
0
0
1
1
0
0
1
○
×
×
POP
A
0
0
0
1
0
1
0
1
×
○
○
POP
R
0
1
0
s
1
R
○
○
○
POP
r
1
1
z
z
1
r
0
0
0
0
0
1
0
1
1
m
1
1
m
m
m
m
0
0
0
0
0
1
z
0
○
○
×
POP <W>
Flags:
S
Z
H
V
N
C
=
=
=
=
=
=
(mem)
S
Z
H
V
N
C
–
–
–
–
–
–
No change
No change
No change
No change
No change
No change
Note: Executing POP F changes all flags.
Page 112
TLCS-900/H1 CPU
Execution example:
POP IX
When the stack pointer XSP = 0100H, the contents of address 100H = 56H, and
the contents of address 101H = 78H, execution sets the IX register to 7856H
and the stack pointer XSP to 0102H.
Page 113
TLCS-900/H1 CPU
POP SR
< Pop SR >
Operation:
SR ← (XSP +).
Description:
Loads the contents of the address specified by the stack pointer XSP to status register. Then
increments the contents of the stack pointer XSP by 2.
Details:
Byte
×
Size
Word Long word
○
×
Mnemonic
POP
Flags:
S=
Z=
H=
V=
N=
C=
Code
SR
0
S
Z
H
V
N
C
*
*
*
*
*
*
0
0
0
0
0
1
1
Contents of the memory address specified by the stack pointer XSP are set.
Note: The timing for executing this instruction is delayed by several states than that for fetching
the instruction. This is because an instruction queue (12 bytes) and pipeline processing
method is used.
Page 114
TLCS-900/H1 CPU
PUSH SR
< Push SR >
Operation:
(− XSP) ← SR.
Description:
Decrements the contents of the stack pointer XSP by 2. Then loads the contents of status
register to the memory address specified by the stack pointer XSP.
Details:
Byte
Size
Word Long word
×
○
×
Mnemonic
PUSH
Flags:
S
Z
H
V
N
C
=
=
=
=
=
=
Code
SR
0
S
Z
H
V
N
C
–
–
–
–
–
–
No change
No change
No change
No change
No change
No change
Page 115
0
0
0
0
0
1
0
TLCS-900/H1 CPU
PUSH src
< Push >
Operation:
(− XSP) ← src.
: XSP ← XSP − 1, (XSP) ← src
: XSP ← XSP − 2, (XSP) ← src
: XSP ← XSP − 4, (XSP) ← src
Description:
Decrements the stack pointer XSP by the byte length of the operand.
Then loads the contents of src to the memory address specified by the stack pointer XSP.
In bytes
In words
In long words
Details:
Byte
Size
Word Long word
Mnemonic
Code
○
×
×
PUSH
F
0
0
0
1
1
0
0
0
○
×
×
PUSH
A
0
0
0
1
0
1
0
0
×
○
○
PUSH
R
0
0
1
s
1
R
○
○
○
PUSH
r
1
1
z
z
1
r
0
0
0
0
0
1
0
0
0
0
0
0
1
0
z
1
○
○
×
PUSH <W>
#
#<7:0>
#<15:8>
○
○
×
PUSH <W>
Flags:
S
Z
H
V
N
C
=
=
=
=
=
=
(mem)
S
Z
H
V
N
C
–
–
–
–
–
–
No change
No change
No change
No change
No change
No change
Page 116
1
m
0
z
m
m
m
m
0
0
0
0
0
1
0
0
TLCS-900/H1 CPU
Execution example:
PUSH HL
When the stack pointer XSP = 0100H and the HL register = 1234H, execution
changes address 00FEH to 34H, address 00FFH to 12H, and sets the stack
pointer XSP to 00FEH.
Page 117
TLCS-900/H1 CPU
RCF
< Reset Carry Flag >
Operation:
CY ← 0.
Description:
Resets the carry flag to 0.
Details:
Mnemonic
Code
RCF
Flags:
S
Z
H
V
N
C
=
=
=
=
=
=
0
S
Z
H
V
N
C
–
–
0
–
0
0
No change
No change
Reset to 0.
No change
Reset to 0.
Reset to 0.
Page 118
0
0
1
0
0
0
0
TLCS-900/H1 CPU
RES num, dst
< Reset >
Operation:
dst<num> ← 0.
Description:
Resets bit num of dst to 0.
Details:
Byte
Size
Word Long word
○
○
○
×
×
Mnemonic
RES
×
S
Z
H
V
N
C
Execution example:
=
=
=
=
=
=
#4, r
RES
Flags:
Code
#3, (mem)
S
Z
H
V
N
C
–
–
–
–
–
–
1
1
0
z
1
0
0
1
1
0
0
0
0
0
1
m
1
1
m
1
0
1
1
0
r
0
0
#
4
m
m
0
m
#3
No change
No change
No change
No change
No change
No change
RES 5, (100H)
When the contents of memory at address 100H = 00100111B (binary), execution
sets the contents to 00000111B (binary).
Page 119
TLCS-900/H1 CPU
RET condition
< Return >
Operation:
If cc is true, then the 32-bit PC ← (XSP), XSP ← XSP + 4.
Description:
Pops the return address from the stack area to the program counter when the operand
condition is true.
Details:
Mnemonic
Code
RET
RET
Flags:
S
Z
H
V
N
C
Execution example:
=
=
=
=
=
=
cc
S
Z
H
V
N
C
–
–
–
–
–
–
0
0
0
0
1
1
1
0
1
0
1
1
0
0
0
0
1
1
1
1
c
c
No change
No change
No change
No change
No change
No change
RET
When the stack pointer XSP = 0FCH and the contents of memory at address
0FCH = 9000H (long word data), execution sets the stack pointer XSP to 100H
and jumps (returns) to address 9000H.
Note: This instruction can be used with CALL instruction.
Note: The cpu takes the proceeding memory fetch cycle, so that the cpu may read next program
which does not branch. But the program is not used.
Page 120
TLCS-900/H1 CPU
RETD num
< Return and Deallocate >
Operation:
32-bit PC ← (XSP), XSP ← XSP + 4, XSP ← XSP + num.
Description:
Pops the return address from the stack area to the program counter. Then increments the
stack pointer XSP by signed num.
Details:
Mnemonic
RETD
Code
d16
0
0
0
0
1
1
1
1
d<7:0>
d<15:8>
Flags:
S
Z
H
V
N
C
Execution example:
=
=
=
=
=
=
S
Z
H
V
N
C
–
–
–
–
–
–
No change
No change
No change
No change
No change
No change
RETD 8
When the stack pointer XSP = 0FCH and the contents of memory at address
0FCH = 9000H (long word data) in minimum mode, execution sets the stack
pointer XSP to 0FCH + 4 + 8→108H and jumps (returns) to address 9000H.
Usage of the RETD instruction is shown below. In this example, the 8-bit
parameter is pushed to the stack before the subroutine call. After the
subroutine processing complete, the used parameter area is deleted by the
RETD instruction.
Note: This instruction can be used with CALL instruction.
Note: The cpu takes the proceeding memory fetch cycle, so that the cpu may read next program
which does not branch. But the program is not used.
Page 121
TLCS-900/H1 CPU
RETI
< Return from Interrupt >
Operation:
SR ← (XSP), 32-bit PC ← (XSP + 2), XSP ← XSP + 6.
After the above operation is executed, the 900/H decrement a value of interrupt nesting
counter INTNEST by 1.
Description:
Pops data from the stack area to status register and program counter.
After the above operation is executed, the 900/H decrement a value of interrupt nesting
counter INTNEST by 1.
Details:
Mnemonic
Code
RETI
Flags:
S
Z
H
V
N
C
=
=
=
=
=
=
0
S
Z
H
V
N
C
*
*
*
*
*
*
0
0
0
0
1
1
1
The value popped from the stack area is set.
The value popped from the stack area is set.
The value popped from the stack area is set.
The value popped from the stack area is set.
The value popped from the stack area is set.
The value popped from the stack area is set.
Note: This instruction can be used with the interrupt instruction.
Note: The cpu takes the proceeding memory fetch cycle, so that the cpu may read next program
which does not branch. But the program is not used.
Page 122
TLCS-900/H1 CPU
RL num, dst
< Rotate Left >
Operation:
{CY & dst ← left rotates the value of CY & dst} Repeat num
Description:
Rotates left the contents of the linked carry flag and dst.
Repeats the number of times specified in num.
Description figure:
Details:
Byte
Size
Word Long word
○
○
○
○
○
○
○
○
×
Mnemonic
RL
Code
#4, r
RL
A, r
RL<W>
(mem)
1
1
z
z
1
r
1
1
1
0
1
0
0
0
0
1
1
z
z
1
1
1
1
1
1
0
1
0
1
m
0
z
m
m
m
m
0
1
1
1
1
0
1
0
0
1
#
4
0
r
Note: When the number of rotates is specified by the A register, the value of the lower 4 bits of
the A register is used. Specifying 0 rotates 16 times.
When dst is memory, rotating is performed only once.
Flags:
S
Z
H
V
N
C
Execution example:
S
Z
H
V
N
C
*
*
0
*
0
*
=
=
=
=
MSB value of dst after rotate is set.
1 is set when the contents of dst after rotate is 0, otherwise 0.
Reset to 0.
1 is set when the parity (number of 1s) of dst is even after rotate, otherwise 0. If the
operand is 32 bits, an undefined value is set.
= Reset to 0.
= The value after rotate is set.
RL 4, HL
When the HL register = 6230H and the carry flag = 1, execution sets the HL
register to 230BH and the carry flag to 0.
Page 123
TLCS-900/H1 CPU
RLC num, dst
< Rotate Left without Carry >
Operation:
{CY ← dst <MSB>,dst ← left rotate value of dst} Repeat num
Description:
Loads the contents of the MSB of dst to the carry flag and rotates left the contents of dst.
Repeats the number of times specified in num.
Description figure:
Details:
Byte
Size
Word Long word
○
○
○
○
○
○
○
○
×
Mnemonic
RLC
Code
#4, r
RLC
A, r
RLC<W>
(mem)
1
1
z
z
1
r
1
1
1
0
1
0
0
0
0
1
1
z
z
1
1
1
1
1
1
0
0
0
1
m
0
z
m
m
m
m
0
1
1
1
1
0
0
0
0
0
#
4
0
r
Note: When the number of rotates is specified by the A register, the value of the lower 4 bits of
the A register is used. Specifying 0 rotates 16 times.
When dst is memory, rotating is performed only once.
Flags:
S
Z
H
V
N
C
Execution example:
S
Z
H
V
N
C
*
*
0
*
0
*
=
=
=
=
MSB value of dst after rotate is set.
1 is set when the contents of dst after rotate is 0, otherwise, 0.
Reset to 0.
1 is set when the parity (number of 1s) of dst is even after rotate. If the operand is 32
bits, an undefined value is set.
= Reset to 0.
= MSB value of dst before the last rotate is set.
RLC 4, HL
When the HL register = 1230H, execution sets the HL register to 2301H and the
carry flag to 1.
Page 124
TLCS-900/H1 CPU
RLD dst1, dst2
< Rotate Left Digit >
Operation:
dst1<3:0> ← dst2<7:4>, dst2<7:4> ← dst2<3:0>, dst2<3:0> ← dst1<3:0>.
Description:
Rotates left the lower 4 bits of dst1 and the contents of dst2 in units of 4 bits.
Description figure:
dst1
7
4
dst2
3
0
7
4
3
0
Details:
Byte
Size
Word Long word
○
×
×
Mnemonic
RLD
Flags:
S
Z
H
V
N
C
Execution example:
Code
[A, ] (mem)
S
Z
H
V
N
C
*
*
0
*
0
–
1
m
0
0
m
m
m
m
0
0
0
0
0
1
1
0
=
=
=
=
MSB value of the A register after rotate is set.
1 is set when the contents of the A register after the rotate are 0, otherwise 0.
Reset to 0.
1 is set when the parity (number of 1s) of the A register is even after the rotate,
otherwise 0.
= Reset to 0.
= No change
RLD A, (100H)
When the A register = 12H and the contents of memory at address 100H = 34H,
execution sets the A register to 13H and the contents of memory at address
100H to 42H.
Page 125
TLCS-900/H1 CPU
RR num, dst
< Rotate Right >
Operation:
{CY & dst ← right rotates the value of CY & dst} Repeat num
Description:
Rotates right the linked contents of the carry flag and dst.
Repeats the number of times specified in num.
Description figure:
Details:
Byte
Size
Word Long word
○
○
○
○
○
○
○
○
×
Mnemonic
RR
Code
#4, r
RR
A, r
RR<W>
(mem)
1
1
z
z
1
r
1
1
1
0
1
0
0
0
0
1
1
z
z
1
1
1
1
1
1
0
1
1
1
m
0
z
m
m
m
m
0
1
1
1
1
0
1
1
0
1
#
4
1
r
Note: When the number of rotates is specified by the A register, the value of the lower 4 bits of
the A register is used. Specifying 0 rotates 16 times.
When dst is memory, rotating is performed only once.
Flags:
S
Z
H
V
N
C
Execution example:
S
Z
H
V
N
C
*
*
0
*
0
*
=
=
=
=
MSB value of dst after rotate is set.
1 is set when the contents of dst after rotate is 0, otherwise 0.
Reset to 0.
1 is set when the parity (number of 1s) of dst is even after the rotate, otherwise 0. If
the operand is 32 bits, an undefined value is set.
= Reset to 0.
= The value after rotate is set.
RR 4, HL
When the HL register = 6230H and the carry flag = 1, execution sets the HL
register to 1623H and the carry flag to 0.
Page 126
TLCS-900/H1 CPU
RRC num, dst
< Rotate Right without Carry >
Operation:
{CY ← dst<LSB>、dst ← right rotate value of dst} Repeat num
Description:
Loads the contents of the LSB of dst to the carry flag and rotates the contents of dst to the
right. Repeats the number of times specified in num.
Description figure:
dst
MSB
LSB
CY
Details:
Byte
Size
Word Long word
○
○
○
○
○
○
○
○
×
Mnemonic
RRC
Code
#4, r
RRC
A, r
RRC<W>
(mem)
1
1
z
z
1
r
1
1
1
0
1
0
0
0
0
1
1
z
z
1
1
1
1
1
1
0
0
1
1
m
0
z
m
m
m
m
0
1
1
1
1
0
0
1
0
0
#
4
1
r
Note: When the number of rotates num is specified by the A register, the value of the lower 4 bits
of the A register is used as the number of rotates.
Specifying 0 rotates 16 times. When dst is memory, rotating is only once.
Flags:
S
Z
H
V
N
C
Execution example:
S
Z
H
V
N
C
*
*
0
*
0
*
=
=
=
=
MSB value of dst after rotate is set.
1 is set when the contents of dst after rotate is 0, otherwise 0.
Reset to 0.
1 is set when the parity (number of 1s) of dst is even after rotate, otherwise 0. If the
operand is 32 bits, an undefined value is set.
= Reset to 0.
= MSB value of dst before the last rotate is set.
RRC 4, HL
When the HL register = 1230H, execution sets the HL register to 0123H and the
carry flag to 0.
Page 127
TLCS-900/H1 CPU
RRD dst1, dst2
< Rotate Right Digit >
Operation:
dst1<3:0> ← dst2<3:0>, dst2<7:4> ← dst1<3:0>, dst2<3:0> ← dst2<7:4>.
Description:
Rotates right the lower 4 bits of dst1 and the contents of dst2 in units of 4 bits.
Description figure:
dst1
7
4
dst2
3
0
7
4
3
0
Details:
Byte
Size
Word Long word
○
×
×
Mnemonic
RRD
Flags:
S
Z
H
V
N
C
Execution example:
Code
[A,] (mem)
S
Z
H
V
N
C
*
*
0
*
0
–
1
m
0
0
m
m
m
m
0
0
0
0
0
1
1
1
=
=
=
=
MSB value of the A register after rotate is set.
1 is set when the contents of the A register after rotate is 0, otherwise 0.
Reset to 0.
1 is set when the parity (number of 1s) of the A register is even after rotate, otherwise
0.
= Reset to 0.
= No change
RRD A, (100H)
When the A register = 12H and the contents of memory at address 100H = 34H,
execution sets the A register to 14H and the contents of memory at address
100H to 23H.
Page 128
TLCS-900/H1 CPU
SBC dst, src
< Subtract with Carry >
Operation:
dst ← dst − src − CY.
Description:
Subtracts the contents of src and the carry flag from those of dst, and loads the result to dst.
Details:
Byte
○
○
Size
Word Long word
○
○
○
○
Mnemonic
SBC
SBC
Code
R, r
r, #
1
1
z
z
1
r
1
0
1
1
0
R
1
1
z
z
1
r
1
1
0
0
1
0
1
1
m
m
m
#<7:0>
#<15:8>
#<23:16>
#<31:24>
○
○
○
○
○
○
○
○
×
SBC
SBC
SBC <W>
R, (mem)
(mem), R
(mem), #
1
m
z
z
m
1
0
1
1
0
1
m
z
z
m
1
0
1
1
1
1
m
0
z
m
m
m
m
0
0
1
1
1
0
1
1
#<7:0>
#<15:8>
Page 129
R
m
m
m
R
TLCS-900/H1 CPU
Flags:
S
Z
H
V
N
C
Execution example:
S
Z
H
V
N
C
*
*
*
*
1
*
= MSB value of the result is set.
= 1 is set when the result is 0, otherwise 0.
= 1 is set when a borrow from bit 3 to bit 4 occurs as a result, otherwise 0. When the
operand is 32 bits, an undefined value is set.
= 1 is set when an overflow occurs as a result, otherwise 0.
= 1 is set.
= 1 is set when a borrow from the MSB occurs as a result, otherwise 0.
BC HL, IX
When the HL register is 7654H, the IX register = 5000H, and the carry flag = 1,
execution sets the HL register to 2653H.
Page 130
TLCS-900/H1 CPU
SCC condition, dst
< Set Condition Code >
Operation:
If cc is true, then dst← 1 else dst ← 0.
Description:
Loads 1 to dst when the operand condition is true; when false, 0 is loaded to dst.
Details:
Byte
Size
Word Long word
○
○
×
Mnemonic
SCC
Flags:
S
Z
H
V
N
C
Execution example:
=
=
=
=
=
=
Code
cc, r
S
Z
H
V
N
C
–
–
–
–
–
–
1
1
0
z
0
1
1
1
1
r
c
c
No change
No change
No change
No change
No change
No change
SCC OV, HL
When the contents of the V flag = 1, execution sets the HL register to 0001H.
Page 131
TLCS-900/H1 CPU
SCF
< Set Carry Flag >
Operation:
CY ← 1.
Description:
Sets the carry flag to 1.
Details:
Mnemonic
Code
SCF
Flags:
S
Z
H
V
N
C
=
=
=
=
=
=
0
S
Z
H
V
N
C
–
–
0
–
0
1
No change
No change
Reset to 0.
No change
Reset to 0.
Set to 1.
Page 132
0
0
1
0
0
0
1
TLCS-900/H1 CPU
SET num, dst
< Set >
Operation:
dst<num> ← 1.
Description:
Sets bit num of dst to 1.
Details:
Byte
Size
Word Long word
○
○
○
×
×
Mnemonic
SET
×
S
Z
H
V
N
C
Execution example:
=
=
=
=
=
=
#4, r
SET
Flags:
Code
#3, (mem)
S
Z
H
V
N
C
–
–
–
–
–
–
1
1
0
z
1
0
0
1
1
0
0
0
0
0
1
m
1
1
m
1
0
1
1
1
r
0
0
#
4
m
m
1
m
#3
No change
No change
No change
No change
No change
No change
SET 5, (100H)
When the contents of memory at address 100H = 00000000B (binary), execution
sets the contents of memory at address 100H to 00100000B (binary).
Page 133
TLCS-900/H1 CPU
SLA num, dst
< Shift Left Arithmetic >
Operation:
{CY ← dst<MSB>, dst ← left shift value of dst, dst<LSB>←0} Repeat num
Description:
Loads the contents of the MSB of dst to the carry flag, shifts left the contents of dst, and
loads 0 to the LSB of dst. Repeats the number of times specified in num.
Description chart:
dst
CY
MSB
LSB
"0"
Details:
Byte
Size
Word Long word
○
○
○
○
○
○
○
○
×
Mnemonic
SLA
Code
#4, r
SLA
A, r
SLA<W>
(mem)
1
1
z
z
1
r
1
1
1
0
1
0
0
0
0
1
1
z
z
1
1
1
1
1
1
1
0
0
1
m
0
z
m
m
m
m
0
1
1
1
1
1
0
0
1
0
#
4
0
r
Note: When the number of shifts, num, is specified by the A register, the value of the lower 4 bits
of the A register is used. Specifying 0 shifts 16 times. When dst is memory, shifting is
performed only once.
Flags:
S
Z
H
V
N
C
Execution example:
S
Z
H
V
N
C
*
*
0
*
0
*
=
=
=
=
MSB value of dst after shift is set.
1 is set when the contents of dst after shift is 0, otherwise 0.
Reset to 0.
1 is set when the parity (number of 1s) of dst is even after shifting, otherwise 0. If the
operand is 32 bits, an undefined value is set.
= Reset to 0.
= MSB value of dst before the last shift is set.
SLA 4, HL
When the HL register = 1234H, execution sets the HL register to 2340H and the
carry flag to 1.
Page 134
TLCS-900/H1 CPU
SLL num, dst
< Shift Left Logical >
Operation:
{CY ← dst<MSB>, dst ← left shift value of dst, dst<LSB>←0} Repeat num
Description:
Loads the contents of the MSB of dst to the carry flag, shifts left the contents of dst, and
loads 0 to the MSB of dst. Repeats the number of times specified in num.
Description chart:
dst
CY
MSB
LSB
"0"
Details:
Byte
Size
Word Long word
○
○
○
○
○
○
○
○
×
Mnemonic
SLL
Code
#4, r
SLL
A, r
SLL<W>
(mem)
1
1
z
z
1
r
1
1
1
0
1
0
0
0
0
1
1
z
z
1
1
1
1
1
1
1
1
0
1
m
0
z
m
m
m
m
0
1
1
1
1
1
1
0
1
1
#
4
0
r
Note: When the number of shifts, num, is specified by the A register, the value of the lower 4 bits
of the A register is used. Specifying 0 shifts 16 times. When dst is memory, shifting is
performed only once.
Flags:
S
Z
H
V
N
C
Execution example:
S
Z
H
V
N
C
*
*
0
*
0
*
=
=
=
=
MSB value of dst after shift is set.
1 is set when the contents of dst after shift is 0, otherwise 0.
Reset to 0.
1 is set when the parity (number of 1s) of dst is even after shifting, otherwise 0. If the
operand is 32 bits, an undefined value is set.
= Reset to 0.
= MSB value of dst before the last shift is set.
SLL 4, HL
When the HL register = 1234H, execution sets the HL register to 2340H and the
carry flag to 1.
Page 135
TLCS-900/H1 CPU
SRA num, dst
< Shift Right Arithmetic >
Operation:
{CY ← dst<MSB>, dst ← right shift value of dst, dst<MSB> is fixed} Repeat num
Description:
Loads the contents of the LSB of dst to the carry flag and shifts right the contents of dst
(MSB is fixed). Repeats the number of times specified in num.
Description chart:
dst
MSB
LSB
CY
Details:
Byte
Size
Word Long word
○
○
○
○
○
○
○
○
×
Mnemonic
SRA
Code
#4, r
SRA
A, r
SRA<W>
(mem)
1
1
z
z
1
r
1
1
1
0
1
0
0
0
0
1
1
z
z
1
1
1
1
1
1
1
0
1
1
m
0
z
m
m
m
m
0
1
1
1
1
1
0
1
1
0
#
4
1
r
Note: When the number of shifts, num, is specified by the A register, the value of the lower 4 bits
of the A register is used. Specifying 0 shifts 16 times. When dst is memory, shifting is
performed only once.
Flags:
S
Z
H
V
N
C
Execution example:
S
Z
H
V
N
C
*
*
0
*
0
*
=
=
=
=
MSB value of dst after shift is set.
1 is set when the contents of dst after shift is 0, otherwise 0.
Reset to 0.
1 is set when the parity (number of 1s) of dst is even after shift, otherwise 0. If the
operand is 32 bits, an undefined value is set.
= Reset to 0.
= LSB value of dst before the last shift is set.
SRA 4, HL
When the HL register = 8230H, execution sets the HL register to F823H and
the carry flag to 0.
Page 136
TLCS-900/H1 CPU
SRL num, dst
< Shift Right Logical >
Operation:
{CY ← dst<LSB>, dst ← right shift value of dst, dst<MSB>←0} Repeat num
Description:
Loads the contents of the LSB of dst to the carry flag, shifts right the contents of dst, and
loads 0 to the MSB of dst. Repeats the number of times specified in num.
Description chart:
dst
MSB
"0"
LSB
CY
Details:
Byte
Size
Word Long word
○
○
○
○
○
○
○
○
×
Mnemonic
SRL
Code
#4, r
SRL
A, r
SRL<W>
(mem)
1
1
z
z
1
r
1
1
1
0
1
0
0
0
0
1
1
z
z
1
1
1
1
1
1
1
1
1
1
m
0
z
m
m
m
m
0
1
1
1
1
1
1
1
1
1
#
4
1
r
Note: When the number of shifts, num, is specified by the A register, the value of the lower 4 bits
of the A register is used. Specifying 0 shifts 16 times. When dst is memory, shifting is
performed only once.
Flags:
S
Z
H
V
N
C
Execution example:
S
Z
H
V
N
C
*
*
0
*
0
*
=
=
=
=
MSB value of dst after shift is set.
1 is set when the contents of dst after shift is 0, otherwise 0.
Reset to 0.
1 is set when the parity (number of 1s) of dst is even after shift, otherwise 0. If the
operand is 32 bits, an undefined value is set.
= Reset to 0.
= LSB value of dst before the last shift is set.
SRL 4, HL
When the HL register = 1238H, execution sets the HL register to 0123H and the
carry flag to 1.
Page 137
TLCS-900/H1 CPU
STCF num, dst
< Store Carry Flag >
Operation:
dst<num> ← CY.
Description:
Loads the contents of the carry flag to bit num of dst.
Details:
Byte
Size
Word Long word
○
○
○
○
○
×
○
×
×
Mnemonic
STCF
×
#4, r
STCF
×
A, r
STCF
×
Code
#3, (mem)
STCF
A, (mem)
1
1
0
z
1
r
0
0
1
0
0
0
0
0
0
1
1
0
z
1
0
0
1
0
1
1
0
0
1
m
1
1
m
m
m
m
1
0
1
0
0
1
m
1
1
m
m
m
m
0
0
1
0
1
1
0
0
1
0
#
4
0
r
#3
Note: When bit num is specified by the A register, the value of the lower 4 bits of the A register is
used. When the operand is a byte and the value of the lower 4 bits of bit num is from 8 to
15, the operand value does not change.
Flags:
S
Z
H
V
N
C
=
=
=
=
=
=
S
Z
H
V
N
C
–
–
–
–
–
–
No change
No change
No change
No change
No change
No change
Page 138
TLCS-900/H1 CPU
Execution example:
STCF 5, (100H)
When the contents of memory at address 100H = 00H and the carry flag = 1,
execution sets the contents of memory at address 100H to 00100000B (binary).
Page 139
TLCS-900/H1 CPU
SUB dst, src
< Subtract >
Operation:
dst ← dst − src.
Description:
Subtracts the contents of src from those of dst and loads the result to dst.
Details:
Byte
○
○
Size
Word Long word
○
○
○
○
Mnemonic
SUB
SUB
Code
R, r
r, #
1
1
z
z
1
r
1
0
1
0
0
R
1
1
z
z
1
r
1
1
0
0
1
0
1
0
m
m
m
#<7:0>
#<15:8>
#<23:16>
#<31:24>
○
○
○
○
○
○
○
○
×
SUB
SUB
SUB <W>
R, (mem)
(mem), R
(mem), #
1
m
z
z
m
1
0
1
0
0
1
m
z
z
m
1
0
1
0
1
1
m
0
z
m
m
m
m
0
0
1
1
1
0
1
0
#<7:0>
#<15:8>
Page 140
R
m
m
m
R
TLCS-900/H1 CPU
Flags:
S
Z
H
V
N
C
Execution example:
S
Z
H
V
N
C
*
*
*
*
1
*
= MSB value of the result is set.
= 1 is set when the result is 0, otherwise 0.
= 1 is set when a borrow from bit 3 to bit 4 occurs as a result, otherwise 0. When the
operand is 32 bits, an undefined value is set.
= 1 is set when an overflow occurs as a result, otherwise 0.
= 1 is set.
= 1 is set when a borrow from MSB occurs as a result, otherwise 0.
SUB HL, IX
When the HL register = 7654H and the IX register = 5000H, execution sets the
HL register to 2654H.
Page 141
TLCS-900/H1 CPU
SWI num
< Software Interrupt >
XSP ← XSP − 6.
(XSP) ← SR.
(XSP + 2) ← 32 bit PC.
PC ← (FFFF00H + num × 4).
Operation:
1)
2)
3)
4)
Description:
Saves to the stack area the contents of the status register and contents of the program
counter which indicate the address next to the SWI instruction. Finally, jumps to vector is
indicated “FFFF00H + num× 4”
Details:
Mnemonic
Code
SWI
[#3]
1
1
1
1
1
#3
Note: A value from 0 to 7 can be specified as the operand value. When the operand coding is
omitted, SWI 7 is assumed.
Note: The status register structure is as shown below.
15
14
13
12
11
10
“1”
IFF2
IFF1
IFF0
“1”
“0”
Flags:
S
Z
H
V
N
C
=
=
=
=
=
=
9
8
RFP1 RFP0
7
6
5
4
3
2
1
0
S
Z
“0”
H
“0”
V
N
C
S
Z
H
V
N
C
–
–
–
–
–
–
No change
No change
No change
No change
No change
No change
Page 142
TLCS-900/H1 CPU
Execution example:
When the stack pointer XSP = 1000H, the status register SR = 8800H, executing the “SWI5”
instruction at memory address 128400H, writes the contents of the status register SR in
memory address 0FFAH, and the contents of the program counter 00128401H in memory
address 0FFCH, and after jumps to address 345678H.
Note: The SWI instruction does not change the IFF( interrupt mask ), so the another interrupt
which have high level may occurred during the SWI.
Note: The SWI 1(04H) is same as the default vector interrupt. The SWI 2(08H) is same as the
illegal instruction interrupt.
Page 143
TLCS-900/H1 CPU
TSET num, dst
< Test and Set >
Operation:
Z flag ← inverted value of dst<num>
dst <num> ← 1.
Description:
Loads the inverted value of the bit num of dst to the Z flag.
Then the bit num of dst is set to “1”.
Details:
Byte
Size
Word Long word
○
○
○
×
×
×
Mnemonic
TSET
S
Z
H
V
N
C
Execution example:
=
=
=
=
=
=
#4, r
TSET
Flags:
Code
#3, (mem)
S
Z
H
V
N
C
×
*
1
×
0
–
1
1
z
z
1
0
0
1
1
0
0
0
0
0
1
m
1
1
m
1
0
1
0
1
r
1
0
#
4
m
m
0
m
#3
An undefined value is set.
The inverted value of the src<num> is set.
Set to 1
An undefined value is set.
Set to 0
No change
When the contents of memory at address 100H = 00100000B (binary), TSET 3,
(100H) execution sets the Z flag to 1, the contents of memory at address 100H =
00101000B (binary).
Page 144
TLCS-900/H1 CPU
UNLK dst
< Unlink >
Operation:
XSP ← dst, dst ← (XSP +).
Description:
Loads the contents of dst to the stack pointer XSP, then pops long word data from the stack
area to dst. Used paired with the Link instruction.
Details:
Byte
Size
Word Long word
×
×
○
Mnemonic
UNLK
Flags:
S
Z
H
V
N
C
Execution example:
=
=
=
=
=
=
Code
r
S
Z
H
V
N
C
–
–
–
–
–
–
1
1
1
0
1
0
0
0
0
1
r
1
0
1
No change
No change
No change
No change
No change
No change
UNLK XIZ
As a result of executing this instruction after executing the Link instruction,
the stack pointer XSP and the XIZ register revert to the same values they had
before the Link instruction was executed. (For details of the Link instruction,
see page 91)
Page 145
TLCS-900/H1 CPU
XOR dst, src
< Exclusive Or >
Operation:
dst ← dst XOR src.
Description:
Exclusive ors the contents of dst with those of src and loads the result to dst.
(Truth table)
A
B
A XOR B
0
0
0
0
1
1
1
0
1
1
1
0
Details:
Byte
○
○
Size
Word Long word
○
○
○
○
Mnemonic
XOR
XOR
Code
R, r
r, #
1
1
z
z
1
r
1
1
0
1
0
R
1
1
z
z
1
r
1
1
0
0
1
1
0
1
m
m
m
#<7:0>
#<15:8>
#<23:16>
#<31:24>
○
○
○
○
○
○
○
○
×
XOR
XOR
XOR <W>
R, (mem)
(mem), R
(mem), #
1
m
z
z
m
1
1
0
1
0
1
m
z
z
m
1
1
0
1
1
1
m
0
z
m
m
m
m
0
0
1
1
1
1
0
1
#<7:0>
#<15:8>
Page 146
R
m
m
m
R
TLCS-900/H1 CPU
Flags:
S
Z
H
V
N
C
Execution example:
XOR)
S
Z
H
V
N
C
*
*
0
*
0
0
=
=
=
=
MSB value of the result is set.
1 is set when the result is 0, otherwise 0.
Reset to 0.
1 is set when the parity (number of 1s) of dst is even as a result, otherwise 0. If the
operand is 32 bits, an undefined value is set.
= Cleared to 0.
= Cleared to 0.
XOR HL, IX
When the HL register = 7350H and the IX register = 3456H, execution sets the
HL register to 4706H.
0111　0011　0101　0000　← HL register (before execution)
0011　0100　0101　0110　← IX register (before execution)
0100　0111　0000　0110　← HL register (after execution)
Page 147
TLCS-900/H1 CPU
XORCF num, src
< Exclusive OR Carry Flag >
Operation:
CY ← CY XOR　src<num>.
Description:
Exclusive ors the contents of the carry flag and bit num of src, and loads the result to the
carry flag.
Details:
Byte
Size
Word Long word
○
○
○
○
○
×
○
×
×
×
×
×
Mnemonic
XORCF
Code
#4, r
XORCF
A, r
XORCF
#3, (mem)
XORCF
A, (mem)
1
1
0
z
1
r
0
0
1
0
0
0
0
0
0
1
1
0
z
1
0
0
1
0
1
0
1
0
1
m
1
1
m
m
m
m
1
0
0
1
0
1
m
1
1
m
m
m
m
0
0
1
0
1
0
1
0
0
1
#
4
0
r
#3
Note: When bit num is specified by the A register, the value of the lower 4 bits of the A register is
used. When the operand is a byte and the value of the lower 4 bits of bit num is from 8 to
15, the result is undefined.
Flags:
S
Z
H
V
N
C
=
=
=
=
=
=
S
Z
H
V
N
C
–
–
–
–
–
*
No change
No change
No change
No change
No change
The value obtained by exclusive or-ing the contents of the carry flag with those of bit
num of src is set.
Page 148
TLCS-900/H1 CPU
Execution example:
XORCF 6, (100H)
When the contents of memory at address 100H = 01000000B (binary) and the
carry flag = 1, execution sets the carry flag to 0.
Page 149
TLCS-900/H1 CPU
ZCF
< Zero flag to Carry Flag >
Operation:
CY ← inverted value of Z flag
Description:
Loads the inverted value of the Z flag to the carry flag.
Details:
Mnemonic
Code
ZCF
Flags:
S
Z
H
V
N
C
Execution example:
=
=
=
=
=
=
0
S
Z
H
V
N
C
–
–
×
–
0
*
0
No change
No change
An undefined value is set.
No change
Reset to 0.
The inverted value of the Z flag is set.
ZCF
When the Z flag = 0, execution sets the carry flag to 1.
Page 150
0
1
0
0
1
1
TLCS-900/H1 CPU
Appendix B Instruction Lists
■
Explanation of symbols used in this document
1.Size
B
The operand size is in bytes (8 bits)
W
The operand size is in word (16 bits)
L
The operand size is in long word (32 bits)
2.Mnemonic
R
Eight general-purpose registers including 8/16/32-bit current bank registers.
8 bit register : W, A, B, C, D, E, H, L
16 bit register : WA, BC, DE, HL, IX, IY, IZ, SP
32 bit register : XWA, XBC, XDE, XHL, XIX, XIY, XIZ, XSP
r
8/16/32-bit general-purpose registers
cr
All 8/16/32-bit CPU control registers
DMAS0 to DMAS7, DMAD0 to DMAD7, DMAC0 to DMAC7, DMAM0 to DMAM7, INTNEST
A
A register (8 bits)
F
Flag registers (8 bits)
F’
Inverse flag registers (8 bits)
SR
Status registers (16 bits)
PC
Program Counter ( in minimum mode, 16 bits; in maximum mode, 32 bits)
(mem)
8/16/32-bit memory data
mem
Effective address value
<W>
When operand size is a word, "W" must be specified.
[]
Operands enclosed in square brackets can be omitted.
#
8/16/32-bit immediate data.
#3
3-bit immediate data: 0 to 7 or 1 to 8 ............... for abbreviated codes.
#4
4-bit immediate data: 0 to 15 or 1 to 16
d8
8-bit displacement : −80H to +7FH
d16
16-bit displacement : −8000H to +7FFFH
cc
Condition code
(#8)
Direct addressing : (00H) to (0FFH) ................ 256-byte area
(#16)
64 K-byte area addressing : (0000H) to (0FFFFH)
$
A start address of the instruction is located
Page 151
TLCS-900/H1 CPU
3.Code
Z
The code represent the operand sizes.
byte (8 bit) = 0
word (16 bit) = 2
long word (32 bit) = 4
ZZ
The code represent the operand sizes.
byte (8 bit) = 00H
word (16 bit) = 10H
long word (32 bit) = 20H
4.
Flag (SZHVNC)
−
Flag doesn’t change.
*
Flag changes by executing instruction.
0
Flag is cleared to "0".
1
Flag is set to "1".
P
Flag changes by executing instruction (It works as parity flag).
V
Flag changes by executing instruction (It works as overflow flag).
X
An undefined value is set in flag.
5.Instruction length
Instruction length is represented in byte unit.
+#
adds immediate data length.
+M
adds immediate code length.
+#M
adds immediate data length and addressing code length.
6.State
Execution processing time of instruction are shown in order of 8 bit, 16 bit, 32 bit processing in status unit.
1 state = 50 ns at 20 MHz
However, the number of state shown in the instruction lists is the value at best
condition as below;
•
The data bus width is 32-bit
•
The bus cycle is at minimum ( 1clock)
•
The optimum data allocation in the memory ( The 2-byte data is allocated in even address, 4-byte data in
four-multiple address.)
Page 152
TLCS-900/H1 CPU
■
900/H1 Instruction Lists (1/10)
(1) Load
Group
Size
Mnemonic
Codes (16 hex)
Function
SZHVNC
Length
(byte)
State
BWL
BWL
BWL
BWL
BWL
BWL
BWL
LD
LD
LD
LD
LD
LD
LD
R,r
r,R
r,#3
R,#
r,#
R,(mem)
(mem),R
C8+zz+r
C8+zz+r
C8+zz+r
20+zz+R
C8+zz+r
80+zz+mem
B0+mem
:88+R
:98+R
:A8+#3
:#
:03:#
:20+R
:40+zz+R
R←r
r←R
r ← #3
R←#
r←#
R ← (mem)
(mem) ← R
------------------------------------
2
2
2
1+#
2+#
2+M
2+M
1. 1. 1
1. 1. 1
1. 1. 1
1. 1. 1
1. 1. 1
2. 2. 2
2. 2. 2
BWBWBWBW-
LD<W>
LD<W>
LD<W>
LD<W>
(#8),#
(mem),#
(#16),(mem)
(mem),(#16)
08+z
B0+mem
80+zz+mem
B0+mem
:#8:#
:00+z:#
:19:#16
:14+z:#16
(#8) ← #
(mem) ← #
(#16) ← (mem)
(mem) ← (#16)
---------------------
2+#
2+M#
4+M
4+M
2. 2. 2. 2. 3. 3. 4. 4. -
PUSH
B-B--WL
BWL
BWBW-
PUSH
F
PUSH
A
PUSH
R
PUSH
r
PUSH<W> #
PUSH<W> (mem)
18
14
18+zz+R
C8+zz+r
:04
09+z
:#
80+zz+mem :04
(−XSP) ← F
(−XSP) ← A
(−XSP) ← R
(−XSP) ← r
(−XSP) ← #
(−XSP) ← (mem)
-------------------------------
1
1
1
2
1+#
2+M
2. -. 2. -. -. 2. 2
3. 3. 3
2. 2. 4. 4. -
POP
B-B--WL
BWL
BW-
POP
POP
POP
POP
POP<W>
19
15
38+zz+R
C8+zz+r
B0+mem
:05
:04+z
F ← (XSP+)
A ← (XSP+)
R ← (XSP+)
r ← (XSP+)
(mem) ← (XSP+)
******
---------------------
1
1
1
2
2+M
2. -. 2. -. -. 2. 2
3. 3. 3
5. 5. -
LDA
-WL
LDA
R,mem
B0+mem
:10+zz+R
R ← mem
------
2+M
-. 2. 2
LDAR
-WL
LDAR
R,$+4+d16
F3:13:d16
:20+zz+R
R ← PC+d16
------
5
-. 2. 2
SZHVNC
Length
(byte)
LD
F
A
R
r
(mem)
(2) Exchange
Group
Size
Mnemonic
Codes (16 hex)
Function
State
EX
B-BWBW-
EX
EX
EX
F,F’
R,r
(mem),R
16
C8+zz+r
:B8+R
80+zz+mem :30+R
F ↔ F’
R↔r
(mem) ↔ R
******
-----------
1
2
2+M
1. -. 2. 2. 3. 3. -
MIRR
-W-
MIRR
r
D8+r
r<0:MSB> ← r<MSB:0>
------
2
-. 2. -
:16
Page 153
TLCS-900/H1 CPU
■
900/H1 Instruction Lists (2/10)
(3) Load/Increment/Decrement & Compare Increment/Decrement Size
Group
Size
Mnemonic
Codes (16 hex)
Function
SZHVNC
Length
(byte)
State
BW-
LDI<W>
[(XDE+),(XHL+)]
83 + zz
:10
(XDE+) ← (XHL+)
BC ← BC − 1
--0[1]0-
2
5. 5. -
BW-
LDI<W>
(XIX+),(XIY+)
85 + zz
:10
(XIX+) ← (XIY+)
BC ← BC − 1
--0[1]0-
2
5. 5. -
BW-
LDIR<W>
[(XDE+),(XHL+)]
:11
repeat
(XDE+) ← (XHL+)
BC ← BC − 1
until BC = 0
--000-
2
2n + 6
BW-
LDIR<W>
(XIX+),(XIY+)
85 + zz
:11
repeat
(XIX+) ← (XIY+)
BC ← BC − 1
until BC = 0
--000-
2
2n + 6
BW-
LDD<W>
[(XDE−),(XHL−)]
83 + zz
:12
(XDE−) ← (XHL−)
BC ← BC − 1
--0[1]0-
2
5. 5. -
BW-
LDD<W>
(XIX−),(XIY−)
85 + zz
:12
(XIX−) ← (XIY−)
BC ← BC − 1
--0[1]0-
2
5. 5. -
BW-
LDDR<W>
[(XDE−),(XHL−)]
:13
repeat
(XDE−) ← (XHL−)
BC ← BC − 1
until BC = 0
--000-
2
2n + 6
BW-
LDDR<W>
(XIX−),(XIY−)
85 + zz
:13
repeat
(XIX−) ← (XIY−)
BC ← BC − 1
until BC = 0
--000-
2
2n + 6
BW-
CPI
80 + zz + R :14
A/WA − (R+)
BC ← BC − 1
*[2]*[1]1-
2
4. 4. -
*[2]*[1]1-
2
4n + 4
LDxx
[A/WA,(R+)]
83 + zz
83 + zz
BW-
CPIR
[A/WA,(R+)]
80 + zz + R :15
repeat
A/WA − (R+)
BC ← BC − 1
until A/WA = (R)
or BC = 0
BW-
CPD
[A/WA,(R−)]
80 + zz + R :16
A/WA − (R−)
BC ← BC − 1
*[2]*[1]1-
2
4. 4. -
80 + zz + R :17
repeat
A/WA − (R−)
BC ← BC − 1
until A/WA = (R)
or BC = 0
*[2]*[1]1-
2
4n + 4
CPxx
BW-
CPDR [A/WA,(R−)]
Note 1: [1];If BC = 0 after execution, the P/V flag is set to 0, otherwise 1.
[2];If A/WA = (R), the Z flag is set to 1, otherwise, 0 is set.
Note 2: When the operand is omitted in the CPI, CPIR, CPD, or CPDR instruction, A, (XHL +/-) is
used as the default value.
Page 154
TLCS-900/H1 CPU
■
900/H1 Instruction Lists (3/10)
(4) Arithmetic Operations
Group
Size
Mnemonic
Codes (16 hex)
Function
SZHVNC
Length
(byte)
State
ADD
BWL
BWL
BWL
BWL
BW-
ADD
ADD
ADD
ADD
ADD<W>
R,r
r,#
R,(mem)
(mem),R
(mem),#
C8 + zz + r
C8 + zz + r
80 + zz + mem
80 + zz + mem
80 + zz + mem
:80 + R
:C8:#
:80 + R
:88 + R
:38:#
R←R+r
r←r+#
R ← R + (mem)
(mem) ← (mem) + R
(mem) ← (mem) + #
***V0*
***V0*
***V0*
***V0*
***V0*
2
2+#
2+M
2+M
2 + M#
1. 1. 1
1. 1. 1
2. 2. 2
3. 3. 3
3. 3. -
ADC
BWL
BWL
BWL
BWL
BW-
ADC
ADC
ADC
ADC
ADC<W>
R,r
r,#
R,(mem)
(mem),R
(mem),#
C8 + zz + r
C8 + zz + r
80 + zz + mem
80 + zz + mem
80 + zz + mem
:90 + R
:C9:#
:90 + R
:98 + R
:39:#
R ← R + r + CY
r ← r + # ++ CY
R ← R + (mem) + CY
(mem) ← (mem) + R + CY
(mem) ← (mem) + # + CY
***V0*
***V0*
***V0*
***V0*
***V0*
2
2+#
2+M
2+M
2 + M#
1. 1. 1
1. 1. 1
2. 2. 2
3. 3. 3
3. 3. -
SUB
BWL
BWL
BWL
BWL
BW-
SUB
SUB
SUB
SUB
SUB<W>
R,r
r,#
R,(mem)
(mem),R
(mem),#
C8 + zz + r
C8 + zz + r
80 + zz + mem
80 + zz + mem
80 + zz + mem
:A0 + R
:CA:#
:A0 + R
:A8 + R
:3A:#
R←R-r
r←r-#
R ← R − (mem)
(mem) ← (mem) − R
(mem) ← (mem) − #
***V1*
***V1*
***V1*
***V1*
***V1*
2
2+#
2+M
2+M
2 + M#
1. 1. 1
1. 1. 1
2. 2. 2
3. 3. 3
3. 3. -
SBC
BWL
BWL
BWL
BWL
BW-
SBC
SBC
SBC
SBC
SBC<W>
R,r
r,#
R,(mem)
(mem),R
(mem),#
C8 + zz + r
C8 + zz + r
80 + zz + mem
80 + zz + mem
80 + zz + mem
:B0 + R
:CB:#
:B0 + R
:B8 + R
:3B:#
R ← R − r − CY
r ← r − # − CY
R ← R -(mem) − CY
(mem) ← (mem) − R − CY
(mem) ← (mem) − # − CY
***V1*
***V1*
***V1*
***V1*
***V1*
2
2+#
2+M
2+M
2 + M#
1. 1. 1
1. 1. 1
2. 2. 2
3. 3. 3
3. 3. -
CP
BWL
BWBWL
BWL
BWL
BW-
CP
CP
CP
CP
CP
CP<W>
R,r
r,#3
r,#
R,(mem)
(mem),R
(mem),#
C8 + zz + r
C8 + zz + r
C8 + zz + r
80 + zz + mem
80 + zz + mem
80 + zz + mem
:F0 + R
:D8 + #3
:CF:#
:F0 + R
:F8 + R
:3F:#
R−r
r − #3
r−#
R − (mem)
(mem) − R
(mem) − #
***V1*
***V1*
***V1*
***V1*
***V1*
***V1*
2
2
2+#
2+M
2+M
2 + M#
1. 1. 1
1. 1. 1. 1. 1
2. 2. 2
2. 2. 2
2. 2. -
INC
B--WL
BW-
INC
#3,r
INC
#3,r
INC<W> #3,(mem)
C8 + r
:60 + #3
C8 + zz + r
:60 + #3
80 + zz + mem :60 + #3
r ← r + #3
r ← r + #3
(mem) ← (mem) + #3
***V0-----***V0-
2
2
2+M
1. -. -. 1. 1
3. 3. -
DEC
B--WL
BW-
DEC
#3,r
DEC
#3,r
DEC<W> #3,(mem)
C8 + r
:68 + #3
C8 + zz + r
:68 + #3
80 + zz + mem :68 + #3
r ← r − #3
r ← r − #3
(mem) ← (mem) − #3
***V1-----***V1-
2
2
2+M
1. -. -. 1. 1
3. 3. -
NEG
BW-
NEG
r
C8 + zz + r
:07
r←0−r
***V1*
2
1. 1. -
EXTZ
-WL
EXTZ
r
C8 + zz + r
:12
r<high> ← 0
------
2
-. 1. 1
EXTS
-WL
EXTS
r
C8 + zz + r
:13
r<high> ← r<low.MSB>
------
2
-. 1. 1
***P-*
2
2. -. -
------
2
-. 3. 3
DAA
B--
DAA
r
C8 + r
:10
Decimal adjustment after
addition or subtraction
PAA
-WL
PAA
r
C8 + zz + r
:14
if r<0> = 1 then INC r
Note: With the INC/DEC instruction, when the code value of #3 = 0, functions as +8/-8.
Page 155
TLCS-900/H1 CPU
■
Group
900/H1 Instruction Lists (4/10)
Size
Mnemonic
Codes (16 hex)
Function
SZHVNC
Length
(byte)
State
MUL
BWBWBW-
MUL
MUL
MUL
RR,r
rr,#
RR,(mem)
C8 + zz + r
:40 + R
C8 + zz + r
:08:#
80 + zz + mem :40 + R
RR ← R × r
rr ← r × #
RR ← R × (mem)
----------------
2
2+#
2+M
5. 9. 5. 9. 6.10. -
MULS
BWBWBW-
MULS
MULS
MULS
RR,r
rr,#
RR,(mem)
C8 + zz + r
:48 + R
C8+ + zz + r
:09:#
80 + zz + mem :48 + R
RR ← R × r
; signed
rr ← r × #
; signed
RR ←R × (mem) ; signed
----------------
2
2+#
2+ + M
4. 8. 4. 8. 5. 9. -
DIV
BWBWBW-
DIV
DIV
DIV
RR,r
rr,#
RR,(mem)
C8 + zz + r
:50 + R
C8 + zz + r
:0A:#
80 + zz + mem :50 + R
R ← RR ÷ r
r ← rr ÷ #
R ← RR ÷ (mem)
---V----V----V--
2
2+#
2+M
11.19. 13.21. 14.22. -
DIVS
BWBWBW-
DIVS
DIVS
DIVS
RR,r
rr,#
RR,(mem)
C8 + zz + r
:58 + R
C8 + zz + r
:0B:#
80 + zz + mem :58 + R
R ← RR ÷ r
; signed
r ← rr ÷ #
; signed
R ← RR ÷ (mem) ; signed
---V----V----V--
2
2+#
2+M
12.20. 14.22. 15.23. -
D8 + r
Multiply and add signed
rr ← rr + (XDE) × (XHL)
**-V--
2
-.12. -
:38:#-1
modulo increment ; +1
if (r mod #) = (# − 1)
then r ← r − (# − 1)
else r ← r + 1
------
4
-. 5. -
:39:#-2
modulo increment ; +2
if (r mod #) = (# − 2)
then r ← r − (# − 2)
else r ← r + 2
------
4
-. 5. -
:3A:#-4
modulo increment ; +4
if (r mod #) = (# − 4)
then r ← r − (# − 4)
else r ← r + 4
------
4
-. 5. -
:3C:#-1
modulo decrement ; −1
if (r mod #) = 0
then r ← r + (# − 1)
else r ← r − 1
------
4
-. 4. -
:3D:#-2
modulo decrement ; −2
if (r mod #) = 0
then r ← r + (# − 2)
else r ← r − 2
------
4
-. 4. -
:3E:#-4
modulo decrement ; −4
if (r mod #) = 0
then r ← r + (# − 4)
else r ← r − 4
------
4
-. 4. -
MULA
-W-
MULA
rr
:19
32bit 32bit 16bit 16bit
XHL ← XHL − 2
MINC
MDEC
-W-
MINC1
#,r
(#=2**n)
(1<=n<=15)
-W-
MINC2
#,r
(#=2**n)
(2<=n<=15)
-W-
MINC4
#,r
(#=2**n)
(3<=n<=15)
-W-
MDEC1
#,r
(#=2**n)
(1<=n<=15)
-W-
MDEC2
#,r
(#=2**n)
(2<=n<=15)
-W-
MDEC4
#,r
(#=2**n)
(3<=n<=15)
D8 + r
D8 + r
D8 + r
D8 + r
D8 + r
D8 + r
Note: Operand RR of the MUL, MULS, DIV, and DIVS instructions indicates that a register twice the
size of the operation is specified. When the operation is in bytes (8 bits × 8 bits, 16/8 bits),
word register (16 bits) is specified; when the operation is in words (16 bits × 16 bits, 32/16 bits),
long word register (32 bits) is specified.
Page 156
TLCS-900/H1 CPU
■
900/H1 Instruction Lists (5/10)
(5) Logical operations
Group
Size
Mnemonic
Codes (16 hex)
Function
SZHVNC
Length
(byte)
State
AND
BWL
BWL
BWL
BWL
BW-
AND
AND
AND
AND
AND<w>
R,r
r,#
R,(mem)
(mem),R
(mem),#
C8 + zz + r
C8 + zz + r
80 + zz + mem
80 + zz + mem
80 + zz + mem
:C0+R
:CC:#
:C0 + R
:C8 + R
:3C:#
R ← R and r
r ← r and #
R ← R and (mem)
(mem) ← (mem) and R
(mem) ← (mem) and #
**1P00
**1P00
**1P00
**1P00
**1P00
2
2+#
2+M
2+M
2 + M#
1. 1. 1
1. 1. 1
2. 2. 2
3. 3. 3
3. 3. -
OR
BWL
BWL
BWL
BWL
BW-
OR
OR
OR
OR
OR<W>
R,r
r,#
R,(mem)
(mem),R
(mem),#
C8 + zz + r
C8 + zz + r
80 + zz + mem
80 + zz + mem
80 + zz + mem
:E0 + R
:CE:#
:E0 + R
:E8 + R
:3E:#
R ← R or r
r ← r or #
R ← R or (mem)
(mem) ← (mem) or R
(mem) ← (mem) or #
**0P00
**0P00
**0P00
**0P00
**0P00
2
2+#
2+M
2+M
2 + M#
1. 1. 1
1. 1. 1
2. 2. 2
3. 3. 3
3. 3. -
XOR
BWL
BWL
BWL
BWL
BW-
XOR
XOR
XOR
XOR
XOR<W>
R,r
r,#
R,(mem)
(mem),R
(mem),#
C8 + zz + r
C8 + zz + r
80 + zz + mem
80 + zz + mem
80 + zz + mem
:D0 + R
:CD:#
:D0 + R
:D8 + R
:3D:#
R ← R xor r
r ← r xor #
R ← R xor (mem)
(mem) ← (mem) xor R
(mem) ← (mem) xor #
**0P00
**0P00
**0P00
**0P00
**0P00
2
2+#
2+M
2+M
2 + M#
1. 1. 1
1. 1. 1
2. 2. 2
3. 3. 3
3. 3. -
CPL
BW-
CPL
r
C8+zz+r
:06
r ← not r
--1-1-
2
1. 1. -
Page 157
TLCS-900/H1 CPU
■
900/H1 Instruction Lists (6/10)
(6) Bit operations
Group
Size
Mnemonic
Codes (16 hex)
Function
SZHVNC
Length
(byte)
State
LDCF
BWBWB-B--
LDCF
LDCF
LDCF
LDCF
#4,r
A ,r
#3,(mem)
A ,(mem)
C8 + zz + r
C8 + zz + r
B0 + men
B0 + men
:23:#4
:2B
:98 + #3
:2B
CY ← r<#4>
CY ← r<A>
CY ← (mem)<#3>
CY ← (mem)<A>
-----*
-----*
-----*
-----*
3
2
2+M
2+M
1. 1. 1. 1. 3. -. 3. -. -
STCF
BWBWB-B--
STCF
STCF
STCF
STCF
#4,r
A ,r
#3,(mem)
A ,(mem)
C8 + zz + r
C8 + zz + r
B0 + mem
B0 + mem
:24:#4
:2C
:A0 + #3
:2C
r<#4> ← CY
r<A> ← CY
(mem)<#3> ← CY
(mem)<A> ← CY
---------------------
3
2
2+M
2+M
1. 1. 1. 1. 4. -. 4. -. -
ANDCF
BWBWB-B--
ANDCF
ANDCF
ANDCF
ANDCF
#4,r
A ,r
#3,(mem)
A ,(mem)
C8 + zz + r
C8 + zz + r
B0 + mem
B0 + mem
:20:#4
:28
:80 + #3
:28
CY ← CY and r<#4>
CY ← CY and r<A>
CY ← CY and (mem)<#3>
CY ← CY and (mem)<A>
-----*
-----*
-----*
-----*
3
2
2+M
2+M
1. 1. 1. 1. 3. -. 3. -. -
ORCF
BWBWB-B--
ORCF
ORCF
ORCF
ORCF
#4,r
A ,r
#3,(mem)
A ,(mem)
C8 + zz + r
C8 + zz + r
B0 + mem
B0 + mem
:21:#4
:29
:88 + #3
:29
CY ← CY or
CY ← CY or
CY ← CY or
CY ← CY or
r<#4>
r<A>
(mem)<#3>
(mem)<A>
-----*
-----*
-----*
-----*
3
2
2+M
2+M
1. 1. 1. 1. 3. -. 3. -. -
XORCF
BWBWB-B--
XORCF
XORCF
XORCF
XORCF
#4,r
A ,r
#3,(mem)
A ,(mem)
C8 + zz + r
C8 + zz + r
B0 + mem
B0 + mem
:22:#4
:2A
:90 + #3
:2A
CY ← CY xor r<#4>
CY ← CY xor r<A>
CY ← CY xor (mem)<#3>
CY ← CY xor (mem)<A>
-----*
-----*
-----*
-----*
3
2
2+M
2+M
1. 1. 1. 1. 3. -. 3. -. -
RCF
SCF
CCF
ZCF
---------
RCF
SCF
CCF
ZCF
CY ← 0
CY ← 1
CY ← not CY
CY ← not “Z” flag
--0-00
--0-01
--X-0*
--X-0*
1
1
1
1
1
1
1
1
BIT
BWB--
BIT
BIT
#4,r
#3,(mem)
C8 + zz + r
B0 + mem
:33:#4
:C8 + #3
Z ← not r<#4>
Z ← not (mem)<#3>
X*1X0X*1X0-
3
2+M
1. 1. 3. -. -
RES
BWB--
RES
RES
#4,r
#3,(mem)
C8 + zz + r
B0 + mem
:30:#4
:B0 + #3
r<#4> ← 0
(mem)<#3> ← 0
-----------
3
2+M
1. 1. 4. -. -
SET
BWB--
SET
SET
#4,r
#3,(mem)
C8 + zz + r
B0 + mem
:31:#4
:B8 + #3
r<#4> ← 1
(mem)<#3> ← 1
-----------
3
2+M
1. 1. 4. -. -
CHG
BWB--
CHG
CHG
#4,r
#3,(mem)
C8 + zz + r
B0 + mem
:32:#4
:C0 + #3
r<#4> ← not r<#4>
(mem)<#3> ← not
(mem)<#3>
-----------
3
2+M
1. 1. 4. -. -
TSET
BWB--
TSET
TSET
#4,r
#3,(mem)
C8 + zz + r
B0 + mem
:34:#4
:A8 + #3
Z ← not r<#4>:r<#4> ← 1
Z ← not (mem)<#3>
(mem)<#3> ← 1
X*1X0X*1X0-
3
2+M
3. 3. 6. -. -
BS1
-W-W-
BS1F
BS1B
A,r
A,r
D8 + r
D8 + r
:0E
:0F
A ← 1 search r; Forward
A ← 1 search r; Backward
---[1]----[1]--
2
2
-. 1. -. 1. -
10
11
12
13
Note: [1]:0 is set when the bit searched for is found, otherwise 1 is set and an undefined value is set
in the A register.
Page 158
TLCS-900/H1 CPU
■
900/H1 Instruction Lists (7/10)
(7) Special operations and CPU control
Group
NOP
Size
---
Mnemonic
NOP
[#3]
Codes (16 hex)
Function
SZHVNC
Length
(byte)
State
00
no operation
------
1
1
06
:#3
Sets interrupt enable flag.
IFF ← #3
------
2
2
06
:07
Disables interrupt.
IFF ← 7
------
2
2
EI
---
EI
DI
---
DI
PUSH
-W-
PUSH
SR
02
(-XSP) ← SR
------
1
-. 2. -
POP
-W-
POP
SR
03
SR ← (XSP+)
******
1
-. 7. -
SWI
---
SWI
[#3]
F8+#3
Software interrupt
PUSH PC&SR
JP (FFFF00H+4×#3)
------
1
9
HALT
---
HALT
05
CPU halt
------
1
6
LDC
BWL
BWL
LDC
LDC
cr,r
r,cr
C8 + zz + r:2E:cr
C8 + zz + r:2F:cr
cr ← r
r ← cr
-----------
3
3
4. 4. 4
2. 2. 2
LINK
--L
LINK
r,d16
E8 + r
:0C:d16
PUSH r
LD r,XSP
ADD XSP,d16
------
4
-. -. 3
UNLK
--L
UNLK
r
E8 + r
:0D
LD XSP,r
POP r
------
2
-. -. 2
LDF
---
LDF
#2
17
:#2
Set a register bank.
RFP ← #2 (0 at reset)
------
2
6
INCF
---
INCF
0C
Switches register banks.
RFP ← RFP + 1
------
1
6
DECF
---
DECF
0D
Switches register banks.
RFP ← RFP − 1
------
1
6
SCC
BW-
SCC
C8 + zz + r:70 + cc
if cc then r ← 1
else r ← 0
------
2
2. 2. -
cc,r
Note: When operand #3 coding in the EI instruction is omitted, 0 is used as the default value.
Note: When operand #3 coding in the SWI instruction is omitted, 7 is used as the default value.
Page 159
TLCS-900/H1 CPU
■
900/H1 Instruction Lists (8/10)
(8) Rotate and Shift
Group
Size
Mnemonic
Codes (16 hex)
Function
RLC
BWL
BWL
BW-
RLC
#4,r
RLC
A,r
RLC<W> (mem)
C8 + zz + r
:E8:#4
C8 + zz + r
:F8
80 + zz + mem :78
RRC
BWL
BWL
BW-
RRC
#4,r
RRC
A,r
RRC<W> (mem)
C8 + zz + r
:E9:#4
C8 + zz + r
:F9
80 + zz + mem :79
RL
BWL
BWL
BW-
RL
RL
RL<W>
#4,r
A,r
(mem)
C8 + zz + r
:EA:#4
C8 + zz + r
:FA
80 + zz + mem :7A
RR
BWL
BWL
BW-
RR
RR
RR<W>
#4,r
A,r
(mem)
C8 + zz + r
:EB:#4
C8 + zz + r
:FB
80 + zz + mem :7B
SLA
BWL
BWL
BW-
SLA
#4,r
SLA
A,r
SLA<W> (mem)
C8 + zz + r
:EC:#4
C8 + zz + r
:FC
80 + zz + mem :7C
SRA
BWL
BWL
BW-
SRA
#4,r
SRA
A,r
SRA<W> (mem)
C8 + zz + r
:ED:#4
C8 + zz + r
:FD
80 + zz + mem :7D
SLL
BWL
BWL
BW-
SLL
SLL
SLL<W>
#4,r
A,r
(mem)
C8 + zz + r
:EE:#4
C8 + zz + r
:FE
80 + zz + mem :7E
SRL
BWL
BWL
BW-
SRL
#4,r
SRL
A,r
SRL<W> (mem)
C8 + zz + r
:EF:#4
C8 + zz + r
:FF
80 + zz + mem :7F
RLD
B--
RLD
[A,](mem)
80 + mem
:06
7-4
RRD
B--
RRD
[A,](mem)
80 + mem
:07
7-4
CY
MSB
MSB
CY
0
CY
MSB
MSB
CY
0
0
CY
MSB
MSB
CY
0
0
0
CY
MSB
MSB
Areg
3-0
Areg
3-0
0
0
0
0
0
CY
SZHVNC
Length
(byte)
State
**0P0*
**0P0*
**0P0*
3
2
2+M
1 + n/4
1 + n/4
3. 3. -
**0P0*
**0P0*
**0P0*
3
2
2+M
1 + n/4
1 + n/4
3. 3. -
**0P0*
**0P0*
**0P0*
3
2
2+M
1 + n/4
1 + n/4
3. 3. -
**0P0*
**0P0*
**0P0*
3
2
2+M
1 + n/4
1 + n/4
3. 3. -
**0P0*
**0P0*
**0P0*
3
2
2+M
1 + n/4
1 + n/4
3. 3. -
**0P0*
**0P0*
**0P0*
3
2
2+M
1 + n/4
1 + n/4
3. 3. -
**0P0*
**0P0*
**0P0*
3
2
2+M
1 + n/4
1 + n/4
3. 3. -
**0P0*
**0P0*
**0P0*
3
2
2+M
1 + n/4
1 + n/4
3. 3. -
**0P0-
2+M
8. -. -
**0P0-
2+M
8. -. -
mem
7-4
3-0
mem
7-4
3-0
Note: When #4/A is used to specify the number of shifts, module 16 (0 to 15) is used. Code 0 means
16 shifts.
Note: When calculating state’s number, it rounds up the following of decimal point.
Page 160
TLCS-900/H1 CPU
■
900/H1 Instruction Lists (9/10)
(9) Jump,Call and Return
Group
Size
Mnemonic
Codes (16 hex)
Function
SZHVNC
Length
(byte)
State
JP
-----------
JP
JP
JR
JRL
JP
#16
#24
[cc,]$ + 2 + d8
[cc,]$+ + 3 + d16
[cc,]mem
1A
1B
60+cc
70+cc
B0+mem
:#16
:#24
:d8
:d16
:DO + cc
PC ← #16
PC ← #24
if cc then PC ← PC + d8
if cc then PC ← PC + d16
if cc then PC ← mem
--------------------------
3
4
2
3
2+M
2
2
2/1 (T/F)
2/1 (T/F)
3 (T/F)
CALL
---------
CALL
CALL
CALR
CALL
#16
#24
$ + 3 + d16
[cc,]mem
1C
1D
1E
B0+mem
:#16
:#24
:d16
:E0 + cc
PUSH PC:JP #16
PUSH PC:JP #24
PUSH PC:JR $ + 3 + d16
if cc then
PUSH PC:JP mem
---------------------
3
4
3
2+M
4
4
5
6/3 (T/F)
DJNZ
BW-
DJNZ [r,]$ + 3/4 + d8
C8+zz+r
:1C:d8
r ← r − 1(Omitting "r", B
register)
if r ≠ 0 then JR $ + 3 + d8
------
3
2 (r ≠ 0)
1 (r = 0)
RET
---------
RET
RET cc
RETD d16
RETI
0E
B0
0F
07
:F0 + cc
:d16
POP PC
if cc then POP PC
RET:ADD XSP,d16
POP SR&PC
---------------******
1
2
3
1
4
7/3 (T/F)
5
9
Note: (T/F) represents the number of states at true / false.
Page 161
TLCS-900/H1 CPU
■
900/H1 Instruction Lists (10/10)
(10) Addressing mode
classification
mode
state
R
R
+0
r
r
+0
(R)
+0
(R + d8)
+0
(#8)
+0
(#16)
+0
(#24)
+0
(r)
+0
(r + d16)
+1
(r + r8)
+1
(r + r16)
+1
(−r)
+1
(r+)
+1
(mem)
(11) Interrupt
mode
state
9
I/O to MEM
(DMADn+) ← (DMASn)
5. 5. 5
I/O to MEM
(DMADn−) ← (DMASn)
5. 5. 5
MEM to I/O
(DMADn) ← (DMASn+)
5. 5. 5
MEM to I/O
(DMADn) ← (DMASn−)
5. 5. 5
MEM to MEM
(DMADn+) ← (DMASn+)
6. 6. 6
MEM to MEM
(DMADn−) ← (DMASn−)
6. 6. 6
I/O to I/O
(DMADn) ← (DMASn)
5. 5. 5
Counter
DMASn ← DMASn+1
5
General-purpose interrupt processing
micro DMA
oepration
PUSH PC
PUSH SR
IFF ← accepted level + 1
INTNEST ← INTNEST + 1
JP (FFFF00H + vector)
Page 162
TLCS-900/H1 CPU
Appendix C 900/H1 Instruction Code Maps
■
900/H1 Instruction Code Maps (1/4)
1- byte op code instructions
H/L
0
0
NOP
1
RCF
1
SCF
2
3
PUSH
SR
POP
SR
4
CCF
ZCF
PUSH
A
5
6
7
HALT
EI
n
RETI
LD
PUSH LDW
(n), n
n
(n), nn
8
9
POP
A
EX
F, F’
LDF
n
PUSH
F
POP
F
A
JP
nn
B
C
D
E
F
PUSHW
INCF
DECF
RET
RETD
dd
CALL
nn
CALL CALR
nnn PC+dd
nn
JP
nnn
2
LD
R, n
PUSH RR
3
LD
RR, nn
PUSH XRR
4
LD
XRR, nnnn
POP
RR
POP
XRR
5
6
JR
F
LT
LE
ULE
PE/OV
M/MI
Z
7
cc, PC+d
C
(T)
JRL
GE
GT
UGT
(XDE
+d)
(XHL
+d)
P/PL
NZ
NC
(XIY
+d)
(XIZ
+d)
(XSP
+d)
E
H
L
IX
IY
IZ
SP
XIX
XIY
XIZ
XSP
4
5
6
7
PO/NOV
cc, PC+dd
↑
8
src. B
(XWA) (XBC) (XDE) (XHL)
(XIX)
src. B
(XIY)
(XIZ)
(XWA
(XSP)
+d)
(XBC
+d)
(XIX
+d)
9
src. W
↑
src. W
↑
A
src. L
↑
src. L
↑
B
dst
↑
dst
↑
C
src. B
(n)
(nn)
(nnn) (mem) (−xrr)
D
src. W
E
src. L
F
dst
↑
↑
(xrr+)
reg. B
r
reg. W
rr
reg. L
xrr
reg. B
W
A
B
C
D
reg. W
WA
BC
DE
HL
reg. L
XWA
XBC
XDE
XHL
SWI
↑
0
1
2
3
n
Note: Codes in blank parts are undefined instructions (i.e., illegal instructions).
Note: Dummy instructions are assigned to codes 1FH. Do not use them.
Page 163
TLCS-900/H1 CPU
■
900/H1 Instruction Code Maps (2/4)
1st byte: reg
H/L
0
1
2
3
4
0
1
2
3
LD
4
PUSH
5
POP
r,#
r
EXTZ EXTS PAA
WL
WL
WL
r
r
r
r
ANDCF ORCF XORCF LDCF STCF
BW
#, r
#, r
#, r
#, r
#, r
RES
SET CHG
BIT TSET
BW
#, r
#, r
#, r
#, r
#, r
MUL
R, r
r
DAA B
5
6
8
1
2
F
LT
LE
DIV
R, r
INC
3
#3, r
4
5
6
CPL
BW
r
MIRR
W
r
6
7
8
ULE PE/OV M/MI
ADD
R, r
9
ADC
R, r
A
SUB
R, r
B
SBC
R, r
C
AND
R, r
D
XOR
R, r
E
OR
R, r
F
CP
R, r
r:
Z
7
NEG
BW
r
8
MUL
9
MULS
A
DIV
B
C
D
E
F
DIVS LINK L UNLKL BS1F BS1B
W
BW
W
rr,#
A, r
r, dd
r
A, r
rr,#
rr,#
rr,#
MULA
DJNZ
W
BW
r
r, d
ANDCF ORCF XORCF LDCF STCF
LDC
LDC
BW
A, r
A, r
A, r
A, r
A, r
cr, r
r, cr
MDEC1 MDEC2 MDEC4
MINC1 MINC2 MINC4
#, r
W
#, r
W
BW
MULS
R, r
BW
BW
DIVS
R, r
BW
DEC
3
#3, r
4
5
6
UGT
LD
PO/NOV
P/PL
NZ
LD
r, R
LD
3
EX
r, #3
4
R, r
5
6
SBC
r, #
CP
3
RR
#, r
RR
A, r
AND
r, #
r, #3
4
SLA
#, r
SLA
A, r
XOR
r, #
OR
r, #
5
SRA
#, r
SRA
A, r
6
SLL
#, r
SLL
A, r
7
SCC
C
8
cc, r
(T)
1
2
GE
GT
0
1
2
ADD
r, #
ADC
r, #
SUB
r, #
0
RLC
#, r
RLC
A, r
1
RRC
#, r
RRC
A, r
2
RL
#, r
RL
A, r
7
BW
NC
R, r
7
BW
CP
r, #
BW
7
SRL
#, r
SRL
A, r
Register specified by the 1st byte code. (Any CPU registers can be specified.)
R: Register specified by the 2nd byte code. (Only eight current registers can be specified.)
B:
Operand size is a byte.
W: Operand size is a word.
L: Operand size is a long word.
Note: Dummy instructions are assigned to codes 1AH, 1BH, 1DH, 1EH, 1FH, 3BH, and 3FH. Do not
use them.
Page 164
TLCS-900/H1 CPU
■
900/H1 Instruction Code Maps (3/4)
1st byte: src (mem)
H/L
0
1
2
3
0
4
5
PUSH
BW
(mem)
1
LDI
LDIR
LDD
LDDR
BW
CPI
6
7
RLD
RRD B
8
9
A
B
C
D
E
F
SUB
SBC
AND
XOR
OR
CP BW
A,(mem)
CPIR
2
LD
R, (mem)
3
EX
(mem), R
CPD
CPDR
BW
LD BW
(nn), (m)
BW ADD
ADC
(mem), #
4
MUL
R, (mem)
BW
MULS R, (mem)
BW
5
DIV
R, (mem)
BW
DIVS
R, (mem)
BW
INC
#3, (mem)
DEC
#3, (mem)
6
8
1
2
3
4
BW
5
6
7
7
8
1
2
3
RLC
RRC
RL
RR
5
6
7
SLA
SRA
SLL
SRL BW
(mem)
8
ADD
R, (mem)
ADD
(mem), R
9
ADC
R, (mem)
ADC
(mem), R
A
SUB
R, (mem)
SUB
(mem), R
B
SBC
R, (mem)
SBC
(mem), R
C
AND
R, (mem)
AND
(mem), R
D
XOR
R, (mem)
XOR
(mem), R
E
OR
R, (mem)
OR
(mem), R
F
CP
R, (mem)
CP
(mem), R
B:
Operand size is a byte.
W: Operand size is a word.
Page 165
BW
4
TLCS-900/H1 CPU
■
900/H1 Instruction Code Maps (4/4)
1st byte: dst (mem)
H/L
0
0
LD B
(m), #
1
2
3
LD W
(m), #
1
2
4
5
POP B
(mem)
LDA
6
7
8
9
A
B
C
XORCF
LDCF
STCF B
D
E
F
6
7
6
7
6
7
6
7
POP W
(mem)
LD B
LD W
(m), (nn)
(m), (nn)
R, mem
W ANDCF ORCF
A, (mem)
3
LDA
R, mem
L
4
LD
(mem), R
B
5
LD
(mem), R
W
6
LD
(mem), R
L
7
8
ANDCF
0
1
2
9
3
XORCF
4
5
B
6
7
6
7
6
7
6
7
7
#3, (mem)
1
2
0
1
2
0
1
2
0
1
2
3
4
5
6
F
LT
LE
ULE
PE/OV
M/MI
Z
STCF
B
3
RES
C
3
CHG
4
5
#3, (mem)
4
5
5
0
1
2
JP
CALL
F
RET
5
0
1
2
0
1
2
0
1
2
3
4
5
6
7
GT
UGT
PO/NOV
P/PL
NZ
NC
#3, (mem)
3
4
TSET
5
#3, (mem)
3
4
SET
5
4
BIT
5
B
#3, (mem)
(T)
GE
cc, mem
cc (1st byte code is B0H.)
↑
Operand size is a byte.
W: Operand size is a word.
L:
B
#3, (mem)
3
↑
B:
B
B
cc, mem
C
E
4
LDCF
B
D
3
B
2
B
#3, (mem)
#3, (mem)
1
B
#3, (mem)
4
ORCF
0
B
0
A
3
#3, (mem)
Operand size is a long word.
Note: Dummy instructions are assigned to codes 01H, 05H and 15H. Do not use them.
Page 166