issfd-m051_e_sm59r16..

SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
Description ..........................................................................................................................................................................3
Features..............................................................................................................................................................................3
Pin Configuration ................................................................................................................................................................4
Block Diagram.....................................................................................................................................................................8
Pin Description....................................................................................................................................................................9
Special Function Register (SFR) ......................................................................................................................................11
Function Description .........................................................................................................................................................15
1.
General Features .....................................................................................................................................................15
1.1.
Embedded Flash.....................................................................................................................................15
1.2.
IO Pads ...................................................................................................................................................15
1.3.
2T/1T Selection.......................................................................................................................................15
1.4.
RESET ....................................................................................................................................................16
1.4.1.
Hardware RESET function .............................................................................................................16
1.4.2.
Software RESET function ..............................................................................................................16
1.4.3.
Time Access Key register (TAKEY)................................................................................................16
1.4.4.
Software Reset register (SWRES).................................................................................................16
1.4.5.
Example of software reset .............................................................................................................17
1.5.
Clocks .....................................................................................................................................................17
2.
Instruction Set ..........................................................................................................................................................18
3.
Memory Structure.....................................................................................................................................................22
3.1.
Program Memory ....................................................................................................................................22
3.2.
Data Memory ..........................................................................................................................................24
3.2.1.
Data memory - lower 128 byte (00h to 7Fh) ..................................................................................24
3.2.2.
Data memory - higher 128 byte (80h to FFh) ................................................................................25
3.2.3.
Data memory - Expanded 2048 bytes ($0000 to $07FF) ..............................................................25
4.
CPU Engine .............................................................................................................................................................26
4.1.
Accumulator............................................................................................................................................26
4.2.
B Register ...............................................................................................................................................26
4.3.
Program Status Word .............................................................................................................................27
4.4.
Stack Pointer...........................................................................................................................................27
4.5.
Data Pointer ............................................................................................................................................27
4.6.
Data Pointer 1 .........................................................................................................................................28
4.7.
Internal RAM control register ..................................................................................................................28
4.8.
Interface control register .........................................................................................................................28
5.
GPIO ........................................................................................................................................................................30
6.
Multiplication Division Unit (MDU)............................................................................................................................32
6.1.
Operating registers of the MDU ..............................................................................................................32
6.2.
Operation of the MDU.............................................................................................................................33
6.2.1.
First phase: loading the MDx registers, x = 0~5: ...........................................................................33
6.2.2.
Second phase: executing calculation. ...........................................................................................33
6.2.3.
Third phase: reading the result from the MDx registers. ...............................................................33
6.3.
Normalizing.............................................................................................................................................34
6.4.
Shifting ....................................................................................................................................................34
7.
Timer 0 and Timer 1 .................................................................................................................................................35
7.1.
Timer/counter mode control register (TMOD).........................................................................................35
7.2.
Timer/counter control register (TCON) ...................................................................................................36
8.
Timer 2 and Capture/Compare Unit .........................................................................................................................37
8.1.
Timer 2 function ......................................................................................................................................39
8.1.1.
Timer mode ....................................................................................................................................39
8.1.2.
Event counter mode.......................................................................................................................39
8.1.3.
Gated timer mode ..........................................................................................................................39
8.1.4.
Reload of Timer 2...........................................................................................................................39
8.2.
Compare function ...................................................................................................................................39
8.2.1.
Compare Mode 0 ...........................................................................................................................40
8.2.2.
Compare Mode 1 ...........................................................................................................................40
8.3.
Capture function .....................................................................................................................................41
8.3.1.
Capture Mode 0 .............................................................................................................................41
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
1
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
8.3.2.
Capture Mode 1 .............................................................................................................................41
Serial interface 0 and 1 ............................................................................................................................................42
9.1.
Serial interface 0.....................................................................................................................................43
9.1.1.
Mode 0 ...........................................................................................................................................43
9.1.2.
Mode 1 ...........................................................................................................................................44
9.1.3.
Mode 2 ...........................................................................................................................................44
9.1.4.
Mode 3 ...........................................................................................................................................45
9.2.
Serial interface 1.....................................................................................................................................45
9.2.1.
Mode A ...........................................................................................................................................45
9.2.2.
Mode B...........................................................................................................................................46
9.3.
Multiprocessor communication of Serial Interface 0 and 1.....................................................................46
9.4.
Baud rate generator................................................................................................................................46
9.4.1.
Serial interface 0 modes 1 and 3 ...................................................................................................46
9.4.2.
Serial interface 1 modes A and B...................................................................................................47
9.5.
Clock source for baud rate......................................................................................................................47
10.
Watchdog timer ...............................................................................................................................................48
11.
Interrupt ...........................................................................................................................................................51
11.1.
Priority level structure .............................................................................................................................53
12.
Power Management Unit.................................................................................................................................55
12.1.
Idle mode ................................................................................................................................................55
12.2.
Stop mode...............................................................................................................................................55
13.
Pulse Width Modulation (PWM) ......................................................................................................................56
14.
IIC function ......................................................................................................................................................59
15.
SPI function .....................................................................................................................................................63
16.
KBI – Keyboard Interface ................................................................................................................................67
17.
LVI – Low Voltage Interrupt .............................................................................................................................70
18.
10-bit Analog-to-Digital Converter (ADC) ........................................................................................................71
19.
In-System Programming (Internal ISP) ...........................................................................................................74
19.1.
ISP service program ...............................................................................................................................74
19.2.
Lock Bit (N) .............................................................................................................................................74
19.3.
Program the ISP Service Program .........................................................................................................75
19.4.
Initiate ISP Service Program...................................................................................................................75
19.5.
ISP register – TAKEY, IFCON, ISPFAH, ISPFAL, ISPFD and ISPFC ....................................................75
Operating Conditions ........................................................................................................................................................78
DC Characteristics ............................................................................................................................................................78
9.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
2
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
Product List
Features
SM59R16A3L25, SM59R16A3C25
SM59R09A3L25, SM59R09A3C25
SM59R05A3L25, SM59R05A3C25
Description
The SM59R16A3 is a 1T (one machine cycle per clock)
single-chip 8-bit microcontroller. It has 64K-byte
embedded Flash for program, and executes all ASM51
instructions fully compatible with MCS-51.
SM59R16A3 contains 2KB on-chip RAM, more than 46
GPIOs (LQFP-48 package type), various serial interfaces
and many peripheral functions as described below. It can
be programmed via writers. Its on-chip ICE is convenient
for users in verification during development stage.
The high performance of SM59R16A3 can achieve
complicated manipulation within short time. About one
third of the instructions are pure 1T, and the average
speed is 8 times of traditional 8051, the fastest one
among all the 1T 51-series.Its excellent EMI and ESD
characteristics are advantageous for many different
applications.
Ordering Information
SM59R16A3ihhkL yymmv
i: process identifier {L = 2.7V ~ 3.6V, C = 4.5V ~ 5.5V}
hh: working clock in MHz {25}
k: package type postfix {as table below }
L:PB Free identifier
{No text is Non-PB free，”P” is PB free}
yy: year
mm: month
v: version identifier{ A, B,…}
Postfix
P
J
Q
U
V
Package
40L PDIP
44L PLCC
44L PQFP
44L LQFP
48L LQFP
Pin / Pad Configuration
Page 4
Page 5
Page 6
Page 6
Page 7
Contact SyncMOS : www.syncmos.com.tw
6F, No.10-2 Li- Hsin 1st Road , SBIP, Hsinchu, Taiwan
TEL: 886-3-567-1820 FAX: 886-3-567-1891
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z
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z
z
z
z
z
Operating Voltage: 4.5V ~ 5.5V or 2.7V ~ 3.6V
High speed architecture of 1 clock/machine cycle
(1T), runs up to 25MHz
1T/2T modes are software programmable on the fly
Instruction-set compatible with MCS-51
64K/36K/20KBytes on-chip flash program memory.
External RAM addresses up to 64K bytes.
Standard 12T interface for external RAM access.
256 bytes RAM as standard 8052, plus 2K bytes
on-chip expandable RAM
Dual 16-bit Data Pointers (DPTR0 & DPTR1)
Two serial peripheral interfaces in full duplex mode
(UART0 & UART1),
Additional Baud Rate Generator for Serial 0.
Three 16-bit Timers/Counters. (Timer 0 , 1, 2)
38 GPIOs(PDIP 40)，42 GPIOs(PLCC 44/PQFP
44/LQFP 44)，46 GPIOs(LQFP 48),GPIOs can
select four Type(quasi-bidirectional、push-pull、open
drain、input-only)，default is
quasi-bidirectional(pull-up)
External interrupt 0,1 with four priority levels
Programmable watchdog timer (WDT)
One IIC interface (Master/Slave mode)
One SPI interface (Master/Slave mode)
4-channel PWM on port 2 or port 4 (default)
4-channel 16-bit compare /capture /load functions
8-channel 10-bit analog-to-digital converter (ADC)
On–chip flash memories support ISP/IAP/ICP and
EEPROM functions.
ISP service program space configurable in N*256 byte
(N=0 to 16) size.
On-chip in-circuit emulator (ICE) function with
On-Chip Debugger（OCD）
EMI reduction mode (ALE output inhibited).
Fast multiplication-division unit (MDU) : 16*16,
32/16, 16/16, 32-bit L/R shifting and 32-bit
normalization
Keyboard interface (KBI) on port 0 or port 2 (default)
for eight more interrupts.
LVI/LVR
Enhanced user code protection
Power management unit for idle and power down
modes
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
3
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
Pin Configuration
40
VDD
CC1/T2EX/ADC1/P1.1
2
39
P0.0/AD0/KBI0
RXD1/ADC2/P1.2
3
38
P0.1/AD1/KBI1
CC2/TXD1/ADC3/P1.3
4
37
P0.2/AD2/KBI2
CC3/SS/ADC4/P1.4
5
36
P0.3/AD3/KBI3
MOSI/ADC5/P1.5
6
35
P0.4/AD4/KBI4
IIC_SCL/MISO/ADC6/P1.6
7
34
P0.5/AD5/KBI5
IIC_SDA/SPI_CLK/ADC7/P1.7
8
33
P0.6/AD6/KBI6
P4.7/RESET(default)
9
32
P0.7/AD7/KBI7
RXD0/P3.0
10
31
OCI_SDA/P4.6
TXD0/P3.1
11
30
ALE/P4.5
INT0/P3.2
12
29
OCI_SCL/P4.4
INT1/P3.3
13
28
P2.7/A15/KBI7/PWM3
T0/P3.4
14
27
P2.6/A14/KBI6/PWM2
T1/P3.5
15
26
P2.5/A13/KBI5/PWM1
WR/P3.6
16
25
P2.4/A12/KBI4/PWM0
RD/P3.7
17
24
P2.3/A11/KBI3/CC3
P5.4/XTAL2
18
23
P2.2/A10/KBI2/CC2
P5.5/XTAL1
19
22
P2.1/A9/KBI1/CC1
VSS
20
21
P2.0/A8/KBI0/CC0
SyncMOS
1
yymmv
(40L PDIP Top View)
CC0/T2/ADC0/P1.0
Notes：
1. The pin Reset/P4.7 factory default is Reset, user must keep this pin at low during power-up. User can configure it to
GPIO (P4.7) by a flash programmer.
2. To avoid accidentally entering ISP-Mode(refer to section 19.4), care must be taken not asserting pulse signal at P3.0
during power-up while P2.6、P2.7、P4.3 are set to high.
3. To apply ICP function, OSI_SDA/P4.6 and OCI_SCL/P4.7 must be set to Bi-direction mode if they are configured as
GPIO in system.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
4
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
39
38
P0.3/AD3/KBI3
37
P0.2/AD2/KBI2
36
P0.1/AD1/KBI1
P0.7/AD7/KBI7
RXD0/P3.0
35
P0.0/AD0/KBI0
P4.7/RESET(default)
OCI_SDA/P4.6
SPI_CLK/TXD1/CC3/PWM3/P4.3
34
VDD
P0.6/AD6/KBI6
P4.1/PWM1/CC1/IIC_SDA/MOSI
TXD0/P3.1
33
P4.2/PWM2/CC2/RXD1/MISO
IIC_SDA/SPI_CLK/ADC7/P1.7
ALE/P4.5
INT0/P3.2
32
P1.0/ADC0/T2/CC0
P0.5/AD5/KBI5
OCI_SCL/P4.4
INT1/P3.3
P2.7/A15/KBI7/PWM3
T0/P3.4
P2.6/A14/KBI6/PWM2
T1/P3.5
P2.5/A13/KBI5/PWM1
SyncMOS
18
19
20
21
22
23
24
25
26
27
28
WR/P3.6
RD/P3.7
P5.4/XTAL2
P5.5/XTAL1
VSS
SS/IIC_SCL/CC0/PWM0/P4.0
CC0/KBI0/A8/P2.0
CC1/KBI1/A9/P2.1
CC2/KBI2/A10/P2.2
CC3/KBI3/A11/P2.3
PWM0/KBI4/A12/P2.4
IIC_SCL/MISO/ADC6/P1.6
8
MOSI/ADC5/P1.5
7
P0.4/AD4/KBI4
31
P1.1/ADC1/T2EX/CC1
40
30
P1.2/ADC2/RXD1
41
29
P1.3/ADC3/TXD1/CC2
42
9
43
10
44
11
1
12
2
13
3
14
4
15
5
16
6
17
P1.4/ADC4/SS/CC3
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
5
Ver.E SM59R16A3 02/2012
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
MOSI/ADC5/P1.5
IIC_SCL/MISO/ADC6/P1.6
IIC_SDA/SPI_CLK/ADC7/P1.7
P4.7/RESET(default)
RXD0/P3.0
SPI_CLK/TXD1/CC3/PWM3/P4.3
TXD0/P3.1
INT0/P3.2
INT1/P3.3
T0/P3.4
T1/P3.5
P2.5/A13/KBI5/PWM1
P2.6/A14/KBI6/PWM2
P2.7/A15/KBI7/PWM3
OCI_SCL/P4.4
ALE/P4.5
P4.1/PWM1/CC1/IIC_SDA/MOSI
OCI_SDA/P4.6
P0.7/AD7/KBI7
P0.6/AD6/KBI6
P0.5/AD5/KBI5
P0.4/AD4/KBI4
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
6
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
KBI3/AD3/P0.3
37
24
P5.0
KBI2/AD2/P0.2
38
23
P2.4/A12/KBI4/PWM0
KBI1/AD1/P0.1
39
22
P2.3/A11/KBI3/CC3
KBI0/AD0/P0.0
40
21
P2.2/A10/KBI2/CC2
VDD
41
20
P2.1/A9/KBI1/CC1
MISO/RXD1/CC2/PWM2/P4.2
42
19
P2.0/A8/KBI0/CC0
CC0/T2/ADC0/P1.0
43
18
P4.0/PWM0/CC0/IIC_SCL/SS
CC1/T2EX/ADC1/P1.1
44
17
VSS
RXD1/ADC2/P1.2
45
16
XTAL1/P5.5
CC2/TXD1/ADC3/P1.3
46
15
XTAL2/P5.4
CC3/SS/ADC4/P1.4
47
14
P3.7/RD
P5.2
48
13
P3.6/WR
SyncMOS
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
7
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
RESET
RXD0
TXD0
RXD1
TXD1
PWM0
PWM1
PWM2
PWM3
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
IIC_SCL
IIC_SDA
SPI_MISO
SPI_MOSI
SPI_CLK
SPI_SS
Block Diagram
MAX810
UART 0
UART1
PWM
ADC
IIC
SPI
XTAL2
XTAL1
SRAM
2KBytes
SRAM
256Bytes
Flash 64KBytes
Port 0
Port 0
Port 1
Port 1
Port 2
Port 2
Port 3
Port 3
Port 4
Port 4
Port 5
Port 5
Timer 0/1
T0
T1
MDU
Watchdog
Interrupt
ALE
WR
RD
ICE
ICP
OCI_SCL
CC0~CC3
T2
T2EX
OCI_SDA
Interface control
Timer2
& CCU
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
8
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
Pin Description
44L
PLCC
44L
PQFP/
LQFP
48L
LQFP
Symbol
I/O
1
39
42
P4.2/PWM2/CC2/
RXD1/MISO
I/O
1
2
40
43
2
3
41
44
3
4
42
45
P1.2/ADC2/RXD1
I/O
4
5
43
46
P1.3/ADC3/TXD1/
CC2
I/O
5
6
44
47
40L
PDIP
P1.0/ADC0/T2/C
C0
P1.1/ADC1/T2EX/
CC1
I/O
I/O
48
1
P1.4/ADC4/SS/C
C3
P5.2
P5.3
I/O
I/O
P1.5/ADC5/MOSI
I/O
I/O
6
7
1
2
7
8
2
3
8
9
3
4
9
10
4
5
10
11
5
6
12
6
7
P4.3/PWM3/CC3/
TXD1/SPI_CLK
I/O
11
13
7
8
P3.1/TXD0
I/O
12
13
14
15
16
17
18
19
20
14
15
16
17
18
19
20
21
22
8
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
17
I/O
I/O
I/O
I/O
I/O
I/O
O
I
I
23
17
18
21
24
18
19
22
25
19
20
23
26
20
21
24
27
21
22
P3.2/#INT0
P3.3/#INT1
P3.4/T0
P3.5/T1
P3.6/#WR
P3.7/#RD
XTAL2/P5.4
XTAL1/P5.5
VSS
P4.0/PWM0/CC0/
IIC_SCL/SS
P2.0
/A8/KBI0/CC0
P2.1
/A9/KBI1/CC1
P2.2/A10/KBI2/C
C2
P2.3/A11/KBI3/C
C3
P1.6/ADC6/MISO/
IIC_SCL
P1.7/ADC7/SPI_
CLK/IIC_SDA
RESET(default)/P
4.7
P3.0/RXD0
I/O
I/O
Description
Bit 2 of port 4 & PWM Channel 2 & Timer 2 compare/capture
Channel 2 & Serial interface channel 1 receive data & SPI
interface Serial Data Master Input or Slave Output pin
Bit 0 of port 1 & ADC input channel 0 & Timer 2 external input
clock & Timer 2 compare/capture Channel 0
Bit 1 of port 1 & ADC input channel 1 & Timer 2 capture trigger &
Timer 2 compare/capture Channel 1
Bit 2 of port 1 & ADC input channel 2 & Serial interface channel
1 receive data
Bit 3 of port 1 & ADC input channel 3 & Serial interface channel
1 transmit data or receive clock in mode 0 & Timer 2
compare/capture Channel 2
Bit 4 of port 1 & ADC input channel 4 & SPI interface Slave
Select pin & Timer 2 compare/capture Channel 3
Bit 2 of port 5
Bit 3 of port 5
Bit 5 of port 1 & ADC input channel 5 & SPI interface Serial Data
Master Output or Slave Input pin
Bit 6 of port 1 & ADC input channel 6 & SPI interface Serial Data
Master Input or Slave Output pin & IIC SCL pin
Bit 7 of port 1 & ADC input channel 7 & SPI interface Clock pin &
IIC SDA pin
I/O
RESET(default) & Bit 7 of port 4
I/O
Bit 0 of port 3 & Serial interface channel 0 receive/transmit data
Bit 3 of port 4 & PWM Channel 3 & Timer 2 compare/capture
Channel 3 & Serial interface channel 1 transmit data or receive
clock in mode 0 & SPI interface Clock pin
Bit 1 of port 3 & Serial interface channel 0 transmit data or
receive clock in mode 0
Bit 2 of port 3 & External interrupt 0
Bit 3 of port 3 & External interrupt 1
Bit 4 of port 3 & Timer 0 external input
Bit 5 of port 3 & Timer 1 external input
Bit 6 of port 3 & external memory write signal
Bit 7 of port 3 & external memory read signal
Crystal output & bit4 of port 5
Crystal input & bit5 of port 5
Power supply
Bit 0 of port 4 & PWM Channel 0 & Timer 2 compare/capture
Channel 0 & IIC SCL pin & SPI interface Slave Select pin
Bit 0 of port 2 & Bit 8 of external memory address & KBI interrupt
0 & Timer 2 compare/capture Channel 0
Bit 1 of port 2 & Bit 9 of external memory address & KBI interrupt
1 & Timer 2 compare/capture Channel 1
Bit 2 of port 2 & Bit 10 of external memory address & KBI
interrupt 2 & Timer 2 compare/capture Channel 2
Bit 3 of port 2 & Bit 11 of external memory address & KBI
interrupt 3 & Timer 2 compare/capture Channel 3
I/O
I/O
I/O
I/O
I/O
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
9
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
40L
PDIP
44L
PLCC
44L
PQFP/
LQFP
48L
LQFP
25
28
22
23
24
25
Symbol
P2.4/A12/KBI4/P
WM0
P5.0
P5.1
P2.5/A13/KBI5/P
WM1
P2.6/A14/KBI6/P
WM2
P2.7/A15/KBI7/P
WM3
I/O
I/O
I/O
I/O
26
29
23
26
27
30
24
27
28
31
25
28
29
32
26
29
OCI_SCL/P4.4
I/O
30
33
27
30
ALE/P4.5
I/O
34
28
31
P4.1/PWM1/CC1/
IIC_SDA/MOSI
I/O
31
35
29
32
OCI_SDA/P4.6
I/O
32
36
30
33
P0.7/AD7/KBI7
I/O
33
37
31
34
P0.6/AD6/KBI6
I/O
34
38
32
35
P0.5/AD5/KBI5
I/O
35
39
33
36
P0.4/AD4/KBI4
I/O
36
40
34
37
P0.3/AD3/KBI3
I/O
37
41
35
38
P0.2/AD2/KBI2
I/O
38
42
36
39
P0.1/AD1/KBI1
I/O
39
43
37
40
P0.0/AD0/KBI0
I/O
40
44
38
41
VDD
I/O
I/O
I/O
I
Description
Bit 4 of port 2 & Bit 12 of external memory address & KBI
interrupt 4 & PWM Channel 0
Bit 0 of port 5
Bit 1 of port 5
Bit 5 of port 2 & Bit 13 of external memory address & KBI
interrupt 5 & PWM Channel 1
Bit 6 of port 2 & Bit 14 of external memory address & KBI
interrupt 6 & PWM Channel 2
Bit 7 of port 2 & Bit 15 of external memory address & KBI
interrupt 7 & PWM Channel 3
On-Chip Instrumentation Clock I/O pin of ICE and ICP functions
& Bit 4 of port 4
Address latch enable & Bit 5 of port 4
Bit 1 of port 4 & PWM Channel 1 & Timer 2 compare/capture
Channel 1 & IIC SDA pin & SPI interface Serial Data Master
Output or Slave Input pin
On-Chip Instrumentation Command and data I/O pin
synchronous to OCI_SCL in ICE and ICP functions & Bit 6 of
port 4
Bit 7 of port 0 & Bit 7 of external memory address/ data & KBI
interrupt 7
Bit 6 of port 0 & Bit 6 of external memory address/ data & KBI
interrupt 6
Bit 5 of port 0 & Bit 5 of external memory address/ data & KBI
interrupt 5
Bit 4 of port 0 & Bit 4 of external memory address/ data & KBI
interrupt 4
Bit 3 of port 0 & Bit 3 of external memory address/ data & KBI
interrupt 3
Bit 2 of port 0 & Bit 2 of external memory address/ data & KBI
interrupt 2
Bit 1 of port 0 & Bit 1 of external memory address/ data & KBI
interrupt 1
Bit 0 of port 0 & Bit 0 of external memory address/ data & KBI
interrupt 0
Power supply
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
10
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
Special Function Register (SFR)
A map of the Special Function Registers is shown as below:
Hex\Bin
F8
X000
IICS
X001
IICCTL
X010
IICA1
X011
IICA2
X100
IICRWD
X101
IICS2
F0
B
SPIC1
SPIC2
SPITXD
SPIRXD
SPIS
E8
E0
D8
P4
ACC
P5
MD0
ISPFAH
MD1
ISPFAL
P3M0
MD2
ISPFD
P3M1
MD3
ISPFC
P4M0
MD4
X110
X111
Bin/Hex
FF
TAKEY
F7
P4M1
MD5
LVC
P5M0
ARCON
SWRES
P5M1
EF
E7
DF
P1M1
P2M0
P2M1
D0
PSW
CCEN2
P0M0
P0M1
P1M0
C8
C0
B8
T2CON
IRCON
IEN1
CCCON
CCEN
IP1
CRCL
CCL1
S0RELH
CRCH
CCH1
S1RELH
TL2
CCL2
PWMD0H
B0
P3
PWMD2H
PWMD2L
PWMD3H
PWMD3L
PWMC
WDTC
WDTK
B7
A8
A0
98
IEN0
P2
S0CON
IP0
S0RELL
ADCC1
ADCC2
ADCDH
ADCDL
ADCCS
S0BUF
IEN2
S1CON
S1BUF
S1RELL
AF
A7
9F
90
P1
AUX
AUX2
KBLS
KBE
KBF
KBD
88
80
Hex\Bin
TCON
P0
X000
TMOD
SP
X001
TL0
DPL
X010
TL1
DPH
X011
TH0
DPL1
X100
TH1
DPH1
X101
RCON
X110
TH2
PWMMDH PWMMDL
CCH2
CCL3
CCH3
PWMD0L PWMD1H PWMD1L
D7
CF
C7
BF
97
IFCON
PCON
X111
8F
87
Bin/Hex
Note: Special Function Registers reset values and description for SM59R16A3
Register
Location
P0
SP
DPL
DPH
DPL1
DPH1
RCON
PCON
TCON
TMOD
TL0
TL1
TH0
TH1
IFCON
P1
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Fh
90h
Reset
value
FFh
07h
00h
00h
00h
00h
00h
40h
00h
00h
00h
00h
00h
00h
00h
FFh
Description
Port 0
Stack Pointer
Data Pointer 0 low byte
Data Pointer 0 high byte
Data Pointer 1 low byte
Data Pointer 1 high byte
Internal RAM control register
Power Control
Timer/Counter Control
Timer Mode Control
Timer 0, low byte
Timer 1, low byte
Timer 0, high byte
Timer 1, high byte
Interface control register
Port 1
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
11
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
Register
Location
AUX
AUX2
KBLS
KBE
KBF
91h
92h
93h
94h
95h
Reset
value
00h
00h
00h
00h
00h
KBD
S0CON
S0BUF
IEN2
S1CON
S1BUF
S1RELL
P2
96h
98h
99h
9Ah
9Bh
9Ch
9Dh
A0h
00h
00h
00h
00h
00h
00h
00h
FFh
Keyboard interface De-bounce control register
Serial Port 0, Control Register
Serial Port 0, Data Buffer
Interrupt Enable Register 2
Serial Port 1, Control Register
Serial Port 1, Data Buffer
Serial Port 1, Reload Register, low byte
Port 2
IEN0
IP0
S0RELL
ADCC1
ADCC2
ADCDH
ADCDL
ADCCS
A8h
A9h
AAh
ABh
ACh
ADh
AEh
AFh
00h
00h
00h
00h
00h
00h
00h
00h
Interrupt Enable Register 0
Interrupt Priority Register 0
Serial Port 0, Reload Register, low byte
ADC Control 1 Register
ADC Control 2 Register
ADC data high byte
ADC data low byte
ADC clock select
P3
PWMD2H
PWMD2L
PWMD3H
PWMD3L
PWMC
WDTC
WDTK
B0h
B1h
B2h
B3h
B4h
B5h
B6h
B7h
FFh
00h
00h
00h
00h
00h
04h
00h
Port 3
PWM channel 2 data high byte
PWM channel 2 data low byte
PWM channel 3 data high byte
PWM channel 3 data low byte
PWM control register
Watchdog timer control register
Watchdog timer refresh key.
IEN1
IP1
S0RELH
S1RELH
PWMD0H
PWMD0L
PWMD1H
PWMD1L
B8h
B9h
BAh
BBh
BCh
BDh
BEh
BFh
00h
00h
00h
00h
00h
00h
00h
00h
Interrupt Enable Register 1
Interrupt Priority Register 1
Serial Port 0, Reload Register, high byte
Serial Port 1, Reload Register, high byte
PWM channel 0 data high byte
PWM channel 0 data low byte
PWM channel 1 data high byte
PWM channel 1 data low byte
IRCON
CCEN
CCL1
CCH1
CCL2
C0h
C1h
C2h
C3h
C4h
00h
00h
00h
00h
00h
Interrupt Request Control Register
Compare/Capture Enable Register
Compare/Capture Register 1, low byte
Compare/Capture Register 1, high byte
Compare/Capture Register 2, low byte
Description
Auxiliary register
Auxiliary register 2
Keyboard level selector Register
Keyboard input enable Register
Keyboard interrupt flag Register
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
12
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
Register
Location
CCH2
CCL3
CCH3
T2CON
CCCON
C5h
C6h
C7h
C8h
C9h
Reset
value
00h
00h
00h
00h
00h
CRCL
CRCH
TL2
TH2
PWMMDH
PWMMDL
PSW
CCEN2
CAh
CBh
CCh
CDh
CEh
CFh
D0h
D1h
00h
00h
00h
00h
00h
FFh
00h
00h
Compare/Reload/Capture Register, low byte
Compare/Reload/Capture Register, high byte
Timer 2, low byte
Timer 2, high byte
PWM Max Data Register, high byte.
PWM Max Data Register, low byte.
Program Status Word
Compare/Capture Enable 2 register
P0M0
P0M1
P1M0
P1M1
P2M0
P2M1
P5
P3M0
P3M1
P4M0
P4M1
P5M0
P5M1
D2h
D3h
D4h
D5h
D6h
D7h
D8h
DAh
DBh
DCh
DDh
DEh
DFh
00h
00h
00h
00h
00h
00h
3Fh
00h
00h
00h
00h
00h
00h
Port 0 output mode 0
Port 0 output mode 1
Port 1 output mode 0
Port 1 output mode 1
Port 2 output mode 0
Port 2 output mode 1
Port 5
Port 3 output mode 0
Port 3 output mode 1
Port 4 output mode 0
Port 4 output mode 1
Port 5 output mode 0
Port 5 output mode 1
ACC
ISPFAH
ISPFAL
ISPFD
ISPFC
LVC
SWRES
P4
E0h
E1h
E2h
E3h
E4h
E6h
E7h
E8h
00h
FFh
FFh
FFh
00h
20h
00h
FFh
Accumulator
ISP Flash Address-High register
ISP Flash Address-Low register
ISP Flash Data register
ISP Flash control register
Low voltage control register
Software Reset register
Port 4
MD0
MD1
MD2
MD3
MD4
MD5
ARCON
B
E9h
EAh
EBh
ECh
EDh
EEh
EFh
F0h
00h
00h
00h
00h
00h
00h
00h
00h
Multiplication/Division Register 0
Multiplication/Division Register 1
Multiplication/Division Register 2
Multiplication/Division Register 3
Multiplication/Division Register 4
Multiplication/Division Register 5
Arithmetic Control Register
B Register
Description
Compare/Capture Register 2, high byte
Compare/Capture Register 3, low byte
Compare/Capture Register 3, high byte
Timer 2 Control
Compare/Capture Control
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
13
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
Register
Location
SPIC1
SPIC2
SPITXD
SPIRXD
SPIS
F1h
F2h
F3h
F4h
F5h
Reset
value
08h
00h
00h
00h
40h
TAKEY
IICS
IICCTL
IICA1
IICA2
IICRWD
IICS2
F7h
F8h
F9h
FAh
FBh
FCh
FDh
00h
00h
04h
A0h
60h
00h
00h
Description
SPI control register 1
SPI control register 2
SPI transmit data buffer
SPI receive data buffer
SPI status register
Time Access Key register
IIC status register
IIC control register
IIC channel 1 Address 1 register
IIC channel 1 Address 2 register
IIC channel 1 Read / Write Data buffer
IIC status2 register
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
14
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
Function Description
1. General Features
SM59R16A3 is an 8-bit micro-controller。All of its functions and the detailed meanings of SFR will be given in the following
sections。
1.1.
Embedded Flash
The program can be loaded into the embedded 64KB/36KB/20KB Flash memory via writer or In-System Programming
(ISP). The high-quality Flash has a 100K-write cycle life，suitable for re-programming and data recording as EEPROM。
1.2.
IO Pads
The SM59R16A3 has six I/O ports: Port 0, Port 1, Port 2, Port 3, Port 4, and Port 5. Ports 0, 1, 2, 3, 4 are 8-bit ports and
Port 5 is a 6-bit port. These are: quasi-bidirectional (standard 8051 port outputs), push-pull, open drain, and input-only. As
description in section 5。
The OCI_SCL、ALE、OCI_SDA and RESET can be configured as I/O ports P4.4、P4.5、P4.6 and P4.7 by writer or in ISP
mode.
The XTAL2 and XTAL1 can be configured as I/O ports P5.4 and P5.5 by writer or in ISP mode, when the on-chip
RC-Oscillator is set to main system clock source.
All the pins on P0 ~ P5 are with slew rate adjustment to reduce EMI. The other way to reduce EMI is to disable the ALE
output if unused. This is selected by its SFR. The IO pads can withstand 4KV ESD in human body mode guaranteeing the
SM59R16A3’s quality in high electro-static environments.
1.3.
2T/1T Selection
The conventional 52-series MCUs are 12T, i.e., 12 oscillator clocks per machine cycle. SM59R16A3 is a 2T or 1T MCU,
i.e., its machine cycle is two-clock or one-clock. In the other words, it can execute one instruction within two clocks or
only one clock. The difference between 2T mode and 1T mode are given in the example in Fig. 1-1.
Fig. 1-1(a): The waveform of internal instruction signal in 2T mode
Fig. 1-1(b): The waveform of internal instruction signal in 1T mode
The default is in 2T mode, and it can be changed to 1T mode if IFCON [7] (at address 8Fh) is set to high any time. Not
every instruction can be executed with one machine cycle. The exact machine cycle number for all the instructions are
given in the next section.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
15
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
1.4.
1.4.1.
RESET
Hardware RESET function
SM59R16A3 provides on-chip hardware RESET mechanism, the reset duration is programmable by writer or ISP。
Internal Reset time
25ms (default)
200ms
100ms
50ms
16ms
8ms
4ms
1.4.2.
Software RESET function
SM59R16A3 provides one software reset mechanism to reset whole chip. To perform a software reset, the firmware must
write three specific values 55h, AAh and 5Ah sequentially to the TAKEY register to enable the Software Reset register
(SWRES) write attribute. After SWRES register obtain the write authority, the firmware can write FFh to the SWRES
register. The hardware will decode a reset signal that “OR” with the other hardware reset. The SWRES register is
self-reset at the end of the software reset procedure.
Mnemonic
TAKEY
SWRES
1.4.3.
Description
Time Access Key
register
Software Reset
register
Direct
Bit 7
Bit 6
Bit 5
Bit 4
Software Reset function
Bit 3
Bit 2
Bit 1
Bit 0
RESET
F7h
TAKEY [7:0]
00H
E7h
SWRES [7:0]
00H
Time Access Key register (TAKEY)
Mnemonic: TAKEY
7
6
5
4
3
TAKEY [7:0]
2
1
Address: F7H
0
Reset
00H
Software reset register (SWRES) is read-only by default; software must write three specific values
55h, AAh and 5Ah sequentially to the TAKEY register to enable the SWRES register write attribute. That
is:
MOV TAKEY, #55h
MOV TAKEY, #AAh
MOV TAKEY, #5Ah
1.4.4.
Software Reset register (SWRES)
Mnemonic: SWRES
7
6
5
4
3
SWRES [7:0]
2
1
Address: E7H
0
Reset
00H
SWRES [7:0]: Software reset register bit. These 8-bit is self-reset at the end of the reset procedure.
SWRES [7:0] = FFh, software reset.
SWRES [7:0] = 00h ~ FEh, MCU no action.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
16
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
1.4.5.
Example of software reset
MOV TAKEY, #55h
MOV TAKEY, #AAh
MOV TAKEY, #5Ah ; enable SWRES write attribute
MOV SWRES, #FFh ; software reset MCU
1.5.
Clocks
The default clock is the external crystal. This clock is used during the initialization stage. The major work of the
initialization stage is to determine the clock source used in normal operation.
The internal clock sources are from the on-chip RC-Oscillator with programmable frequency outputs as table 1-1，the
clock source can set by writer or ICP。
Table 1-1: Selection of clock source
Clock source
external crystal(default)
24MHz from internal OSC
20MHz from internal OSC
16MHz from internal OSC
12MHz from internal OSC
8MHz from internal OSC
4MHz from internal OSC
2MHz from internal OSC
1MHz from internal OSC
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
17
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
2. Instruction Set
All SM59R16A3 instructions are binary code compatible and perform the same functions as they do with the industry
standard 8051. The following tables give a summary of the instruction set cycles of the SM59R16A3 Microcontroller core.
Mnemonic
ADD A,Rn
ADD A,direct
Table 2-1: Arithmetic operations
Description
Add register to accumulator
Add direct byte to accumulator
Code
28-2F
25
Bytes
1
2
Cycles
1
2
ADD A,@Ri
ADD A,#data
ADDC A,Rn
ADDC A,direct
Add indirect RAM to accumulator
Add immediate data to accumulator
Add register to accumulator with carry flag
Add direct byte to A with carry flag
26-27
24
38-3F
35
1
2
1
2
2
2
1
2
ADDC A,@Ri
ADDC A,#data
SUBB A,Rn
SUBB A,direct
Add indirect RAM to A with carry flag
Add immediate data to A with carry flag
Subtract register from A with borrow
Subtract direct byte from A with borrow
36-37
34
98-9F
95
1
2
1
2
2
2
1
2
SUBB A,@Ri
SUBB A,#data
INC A
INC Rn
INC direct
Subtract indirect RAM from A with borrow
Subtract immediate data from A with borrow
Increment accumulator
Increment register
Increment direct byte
96-97
94
04
08-0F
05
1
2
1
1
2
2
2
1
2
3
INC @Ri
Increment indirect RAM
06-07
1
3
INC DPTR
DEC A
DEC Rn
Increment data pointer
Decrement accumulator
Decrement register
A3
14
18-1F
1
1
1
1
1
2
DEC direct
Decrement direct byte
15
2
3
DEC @Ri
MUL AB
DIV
DA A
Decrement indirect RAM
Multiply A and B
Divide A by B
Decimal adjust accumulator
16-17
A4
84
D4
1
1
1
1
3
5
5
1
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
18
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
Mnemonic
ANL A,Rn
ANL A,direct
Table 2-2: Logic operations
Description
AND register to accumulator
AND direct byte to accumulator
Code
58-5F
55
Bytes
1
2
Cycles
1
2
ANL A,@Ri
ANL A,#data
ANL direct,A
ANL direct,#data
AND indirect RAM to accumulator
AND immediate data to accumulator
AND accumulator to direct byte
AND immediate data to direct byte
56-57
54
52
53
1
2
2
3
2
2
3
4
ORL A,Rn
ORL A,direct
ORL A,@Ri
ORL A,#data
OR register to accumulator
OR direct byte to accumulator
OR indirect RAM to accumulator
OR immediate data to accumulator
48-4F
45
46-47
44
1
2
1
2
1
2
2
2
ORL direct,A
ORL direct,#data
XRL A,Rn
XRL A,direct
OR accumulator to direct byte
OR immediate data to direct byte
Exclusive OR register to accumulator
Exclusive OR direct byte to accumulator
42
43
68-6F
65
2
3
1
2
3
4
1
2
XRL A,@Ri
Exclusive OR indirect RAM to accumulator
66-67
1
2
XRL A,#data
XRL direct,A
XRL direct,#data
CLR A
Exclusive OR immediate data to accumulator
Exclusive OR accumulator to direct byte
Exclusive OR immediate data to direct byte
Clear accumulator
64
62
63
E4
2
2
3
1
2
3
4
1
CPL A
RL A
RLC A
RR A
Complement accumulator
Rotate accumulator left
Rotate accumulator left through carry
Rotate accumulator right
F4
23
33
03
1
1
1
1
1
1
1
1
RRC A
SWAP A
Rotate accumulator right through carry
Swap nibbles within the accumulator
13
C4
1
1
1
1
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
19
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
Mnemonic
MOV A,Rn
MOV A,direct
Table 2-3: Data transfer
Description
Move register to accumulator
Move direct byte to accumulator
Code
E8-EF
E5
Bytes
1
2
Cycles
1
2
MOV A,@Ri
MOV A,#data
MOV Rn,A
MOV Rn,direct
Move indirect RAM to accumulator
Move immediate data to accumulator
Move accumulator to register
Move direct byte to register
E6-E7
74
F8-FF
A8-AF
1
2
1
2
2
2
2
4
MOV Rn,#data
MOV direct,A
MOV direct,Rn
MOV direct1,direct2
Move immediate data to register
Move accumulator to direct byte
Move register to direct byte
Move direct byte to direct byte
78-7F
F5
88-8F
85
2
2
2
3
2
3
3
4
MOV direct,@Ri
MOV direct,#data
MOV @Ri,A
MOV @Ri,direct
Move indirect RAM to direct byte
Move immediate data to direct byte
Move accumulator to indirect RAM
Move direct byte to indirect RAM
86-87
75
F6-F7
A6-A7
2
3
1
2
4
3
3
5
MOV @Ri,#data
Move immediate data to indirect RAM
76-77
2
3
MOV DPTR,#data16
Load data pointer with a 16-bit constant
90
3
3
MOVC A,@A+DPTR
Move code byte relative to DPTR to accumulator
93
1
3
MOVC A,@A+PC
MOVX A,@Ri
Move code byte relative to PC to accumulator
Move external RAM (8-bit addr.) to A
83
E2-E3
1
1
3
3
MOVX A,@DPTR
MOVX @Ri,A
MOVX @DPTR,A
PUSH direct
Move external RAM (16-bit addr.) to A
Move A to external RAM (8-bit addr.)
Move A to external RAM (16-bit addr.)
Push direct byte onto stack
E0
F2-F3
F0
C0
1
1
1
2
3
4
4
4
POP direct
XCH A,Rn
XCH A,direct
XCH A,@Ri
XCHD A,@Ri
Pop direct byte from stack
Exchange register with accumulator
Exchange direct byte with accumulator
Exchange indirect RAM with accumulator
Exchange low-order nibble indir. RAM with A
D0
C8-CF
C5
C6-C7
D6-D7
2
1
2
1
1
3
2
3
3
3
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
20
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
Mnemonic
ACALL addr11
LCALL addr16
Table 2-4: Program branches
Description
Absolute subroutine call
Long subroutine call
Code
xxx11
12
Bytes
2
3
Cycles
6
6
RET
RETI
AJMP addr11
LJMP addr16
from subroutine
from interrupt
Absolute jump
Long iump
22
32
xxx01
02
1
1
2
3
4
4
3
4
SJMP rel
JMP @A+DPTR
JZ rel
JNZ rel
Short jump (relative addr.)
Jump indirect relative to the DPTR
Jump if accumulator is zero
Jump if accumulator is not zero
80
73
60
70
2
1
2
2
3
2
3
3
JC rel
JNC
JB bit,rel
JNB bit,rel
Jump if carry flag is set
Jump if carry flag is not set
Jump if direct bit is set
Jump if direct bit is not set
40
50
20
30
2
2
3
3
3
3
4
4
JBC bit,direct rel
Jump if direct bit is set and clear bit
10
3
4
CJNE A,direct rel
CJNE A,#data rel
CJNE Rn,#data rel
CJNE @Ri,#data rel
Compare direct byte to A and jump if not equal
Compare immediate to A and jump if not equal
Compare immed. to reg. and jump if not equal
Compare immed. to ind. and jump if not equal
B5
B4
B8-BF
B6-B7
3
3
3
3
4
4
4
4
DJNZ Rn,rel
DJNZ direct,rel
NOP
Decrement register and jump if not zero
Decrement direct byte and jump if not zero
No operation
D8-DF
D5
00
2
3
1
3
4
1
Mnemonic
CLR C
CLR bit
Table 2-5: Boolean manipulation
Description
Clear carry flag
Clear direct bit
Code
C3
C2
SETB C
Set carry flag
SETB bit
CPL C
CPL bit
Bytes
1
2
Cycles
1
3
D3
1
1
Set direct bit
Complement carry flag
Complement direct bit
D2
B3
B2
2
1
2
3
1
3
ANL C,bit
AND direct bit to carry flag
82
2
2
ANL C,/bit
ORL C,bit
ORL C,/bit
AND complement of direct bit to carry
OR direct bit to carry flag
OR complement of direct bit to carry
B0
72
A0
2
2
2
2
2
2
MOV C,bit
Move direct bit to carry flag
A2
2
2
MOV bit,C
Move carry flag to direct bit
92
2
3
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
21
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
3. Memory Structure
The SM59R16A3 memory structure follows general 8052 structure. It is integrate the expanded 2KB data memory and
64KB program memory.
3.1.
Program Memory
The SM59R16A3 has 64KB on-chip flash memory which can be used as general program memory or EEPROM, on which
include up to 4K byte specific ISP service program memory space. The address range for the 64K byte is $0000 to $FFFF.
The address range for the ISP service program is $F000 to $FFFF. The ISP service program size can be partitioned as N
blocks of 256 byte (N=0 to 16). When N=0 means no ISP service program space available, total 64K byte memory used
as program memory. When N=1 means address $FF00 to $FFFF reserved for ISP service program. When N=2 means
memory address $FE00 to $FFFF reserved for ISP service program…etc. Value N can be set and programmed into
SM59R16A3 by the writer or ICP. It can be used to record any data as EEPROM. The procedure of this EEPROM
application function is described in the section 19 on internal ISP.
Fig. 3-1: SM59R16A3 programmable Flash
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
22
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
ISP service
Program space,
Up to 4K
FFFF
FF00
FE00
FD00
FC00
FB00
FA00
F900
F800
F700
F600
F500
F400
F300
F200
F100
F000
N=0
N=1
N=2
N=3
N=4
N=5
N=6
N=7
N=8
N=9
N=10
N=11
N=12
N=13
N=14
N=15
N=16
8000
7FFF
32K Program
Memory space
0000
Fig. 3-2 : SM59R09A3 programmable Flash
ISP service
Program space,
Up to 4K
FFFF
FF00
FE00
FD00
FC00
FB00
FA00
F900
F800
F700
F600
F500
F400
F300
F200
F100
F000
N=0
N=1
N=2
N=3
N=4
N=5
N=6
N=7
N=8
N=9
N=10
N=11
N=12
N=13
N=14
N=15
N=16
4000
3FFF
16K Program
Memory space
0000
Fig. 3-3 : SM59R05A3 programmable Flash
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
23
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
3.2. Data Memory
The SM59R16A3 has 2K + 256Bytes on-chip SRAM, 256 Bytes of it are the same as general 8052 internal memory
structure while the expanded 2KBytes on-chip SRAM can be accessed by external memory addressing method ( by
instruction MOVX.)
Fig 3-2 (a)：External memory access as read
Fig 3-2 (b)：External memory access as write
Fig. 3-3: RAM architecture
3.2.1.
Data memory - lower 128 byte (00h to 7Fh)
Data memory 00h to FFh is the same as 8052.
The address 00h to 7Fh can be accessed by direct and indirect addressing modes.
Address 00h to 1Fh is register area.
Address 20h to 2Fh is memory bit area.
Address 30h to 7Fh is for general memory area.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
24
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
3.2.2.
Data memory - higher 128 byte (80h to FFh)
The address 80h to FFh can be accessed by indirect addressing mode.
Address 80h to FFh is data area.
3.2.3.
Data memory - Expanded 2048 bytes ($0000 to $07FF)
From external address 0000h to 07FFh is the on-chip expanded SRAM area, total 2K Bytes. This area can be accessed
by external direct addressing mode (by instruction MOVX).
If the address of instruction MOVX @DPTR is larger then 07FFh, the SM59R16A3 will generate the external memory
control signal automatically.
The address space of instruction MOVX @Ri, i=0, 1 is determined by RCON [7:0] of special function register $86 RCON
(internal RAM control register). The default setting of RCON [7:0] is 00h (page0). One page of data RAM is 256 bytes.
When EMEN = 0, the internal 2K expanded RAM is enabled. If access memory space is more than 2K byte, the value of
RCON is sent to Port2 to access external RAM.
When EMEN = 1, the internal 2K expanded RAM is disabled. The value of RCON is invalid and high byte address is
decided by register context of Port2 register P2 [7:0].
MOVX @Ri, A
MOVX A,@Ri
EMEN = 0
EMEN = 1
0 ≦ RCON[7:0] ≦ 3
4 ≦ RCON [7:0] ≦ 255
Addr [15:8] <= RCON[7:0]
Port2 [7:0] <= P2 [7:0]
Port2 [7:0] <= RCON[7:0]
Port2 [7:0] <= P2 [7:0]
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
25
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
4. CPU Engine
The SM59R16A3 engine is composed of four components:
a. Control unit
b. Arithmetic – logic unit
c. Memory control unit
d. RAM and SFR control unit
The SM59R16A3 engine allows to fetch instruction from program memory and to execute using RAM or SFR. The
following paragraphs describe the main engine registers.
Mnemonic
Description
Direct
Bit 7
ACC
B
Accumulator
B register
Program status
word
Stack Pointer
Data pointer low 0
Data pointer high
0
Data pointer low 1
Data pointer high
1
E0h
F0h
ACC.7
B.7
D0h
CY
PSW
SP
DPL
DPH
DPL1
DPH1
AUX
RCON
IFCON
4.1.
Auxiliary register
Internal RAM
control register
Interface control
register
Bit 6
Bit 5
8051 Core
ACC.6 ACC.5
B.6
B.5
AC
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESET
ACC.4
B.4
ACC.3
B.3
ACC.2
B.2
ACC.1
B.1
ACC.0
B.0
00H
00H
OV
PSW.1
P
00H
F0
RS[1:0]
81h
82h
SP[7:0]
DPL[7:0]
07H
00H
83h
DPH[7:0]
00H
84h
DPL1[7:0]
00H
85h
DPH1[7:0]
00H
91h
BRGS
-
P4SPI
P4UR
1
86h
P4IIC
P0KBI
P2PW
M
DPS
RCON[7:0]
8Fh
ITS
CDPR
-
-
00H
00H
ALEC[1:0]
EMEN
ISPE
00H
Accumulator
ACC is the Accumulator register. Most instructions use the accumulator to store the operand.
Mnemonic: ACC
7
6
ACC.7 ACC.6
5
ACC05
4
ACC.4
3
ACC.3
2
ACC.2
1
ACC.1
Address: E0h
0
Reset
ACC.0
00h
ACC[7:0]: The A (or ACC) register is the standard 8052 accumulator.
4.2.
B Register
The B register is used during multiply and divide instructions. It can also be used as a scratch pad register to store
temporary data.
Mnemonic: B
7
6
B.7
B.6
5
B.5
4
B.4
3
B.3
2
B.2
1
B.1
Address: F0h
0
Reset
B.0
00h
B[7:0]: The B register is the standard 8052 register that serves as a second accumulator.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
26
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
4.3.
Program Status Word
Mnemonic: PSW
7
6
CY
AC
5
F0
4
3
RS [1:0]
2
OV
1
F1
Address: D0h
0
Reset
P
00h
CY: Carry flag.
AC: Auxiliary Carry flag for BCD operations.
F0: General purpose Flag 0 available for user.
RS[1:0]: Register bank select, used to select working register bank.
RS[1:0]
Bank Selected
Location
00
Bank 0
00h – 07h
01
Bank 1
08h – 0Fh
10
Bank 2
10h – 17h
11
Bank 3
18h – 1Fh
OV: Overflow flag.
F1: General purpose Flag 1 available for user.
P: Parity flag, affected by hardware to indicate odd/even number of “one” bits in the
Accumulator, i.e. even parity.
4.4.
Stack Pointer
The stack pointer is a 1-byte register initialized to 07h after reset. This register is incremented before PUSH and CALL
instructions, causing the stack to start from location 08h.
Mnemonic: SP
7
6
5
4
3
2
1
SP [7:0]
Address: 81h
0
Reset
07h
SP[7:0]: The Stack Pointer stores the scratchpad RAM address where the stack begins. In other
words, it always points to the top of the stack.
4.5.
Data Pointer
The data pointer (DPTR) is 2-bytes wide. The lower part is DPL, and the highest is DPH. It can be loaded as a 2-byte
register (e.g. MOV DPTR, #data16) or as two separate registers (e.g. MOV DPL,#data8). It is generally used to access
the external code or data space (e.g. MOVC A, @A+DPTR or MOVX A, @DPTR respectively).
Mnemonic: DPL
7
6
5
4
3
DPL [7:0]
2
1
Address: 82h
0
Reset
00h
4
3
DPH [7:0]
2
1
Address: 83h
0
Reset
00h
DPL[7:0]: Data pointer Low 0
Mnemonic: DPH
7
6
5
DPH [7:0]: Data pointer High 0
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
27
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
4.6.
Data Pointer 1
The Dual Data Pointer accelerates the moves of data block. The standard DPTR is a 16-bit register that is used to
address external memory or peripherals. In the SM59R16A3 core the standard data pointer is called DPTR, the second
data pointer is called DPTR1. The data pointer select bit chooses the active pointer. The data pointer select bit is located
in LSB of AUX register (DPS).
The user switches between pointers by toggling the LSB of AUX register. All DPTR-related instructions use the currently
selected DPTR for any activity.
Mnemonic: DPL1
7
6
5
4
3
DPL1 [7:0]
2
1
Address: 84h
0
Reset
00h
4
3
DPH1 [7:0]
2
1
Address: 85h
0
Reset
00h
DPL1[7:0]: Data pointer Low 1
Mnemonic: DPH1
7
6
5
DPH1[7:0]: Data pointer High 1
Mnemonic: AUX
7
6
5
BRGS
P4SPI
4
P4UR1
3
P4IIC
2
P0KBI
1
P2PWM
Address: 91h
0
Reset
DPS
00H
DPS: Data Pointer selects register.
DPS = 1 is selected DPTR1.
4.7.
Internal RAM control register
SM59R16A3 has 2K byte on-chip expanded RAM which can be accessed by external memory addressing method only
(By instruction MOVX). The address space of instruction MOVX @Ri, i= 0, 1 is determined by RCON [7:0] of RCON. The
default setting of RCON [7:0] is 00h (page0).
Mnemonic: RCON
7
6
4.8.
5
4
3
RCON[7:0]
5
-
4
-
2
1
Address: 86h
0
Reset
00H
1
EMEN
Address: 8Fh
0
Reset
ISPE
00h
Interface control register
Mnemonic: IFCON
7
6
ITS
CDPR
3
2
ALEC[1:0]
ITS: Instruction timing select. (default is 2T)
ITS = 0, 2T instruction mode.
ITS = 1, 1T instruction mode.
CDPR: code protect (Read Only)
ALEC[1:0]: ALE output control register.
ALEC[1:0]
ALE Output
00
Always output
01
No ALE output
10
Only Read or Write have ALE output
11
reserved
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
28
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
EMEN: Internal 2K SRAM disable.(default is enable)
EMEN = 0, Enable internal 2K RAM.
EMEN = 1, Disable internal 2K RAM.
ISPE: ISP function enable bit
ISPE = 1, enable ISP function
ISPE = 0, disable ISP function
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
29
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
5. GPIO
The SM59R16A3 has six I/O ports: Port 0, Port 1, Port 2, Port 3, Port 4, and Port 5. Ports 0, 1, 2, 3, 4 are 8-bit ports and
Port 5 is a 6-bit port. These are: quasi-bidirectional (standard 8051 port outputs), push-pull, open drain, and input-only.
Two configuration registers for each port select the output type for each port pin. All I/O port pins on the SM59R16A3 may
be configured by software to one of four types on a pin-by-pin basis, shown as below:
Mnemonic
P0M0
P0M1
P1M0
P1M1
P2M0
P2M1
P3M0
P3M1
P4M0
P4M1
P5M0
P5M1
Description
Direct
Port 0 output mode 0
Port 0 output mode 1
Port 1 output mode 0
Port 1 output mode 1
Port 2 output mode 0
Port 2 output mode 1
Port 3 output mode 0
Port 3 output mode 1
Port 4 output mode 0
Port 4 output mode 1
Port 5 output mode 0
Port 5 output mode 1
PxM1.y
0
0
1
1
PxM0.y
0
1
0
1
D2h
D3h
D4h
D5h
D6h
D7h
DAh
DBh
DCh
DDh
DEh
DFh
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
I/O port function register
P0M0 [7:0]
P0M1[7:0]
P1M0[7:0]
P1M1[7:0]
P2M0[7:0]
P2M1[7:0]
P3M0[7:0]
P3M1[7:0]
P4M0[7:0]
P4M1[7:0]
P5M0[5:0]
P5M1[5:0]
Bit 1
Bit 0
RESET
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
Port output mode
Quasi-bidirectional (standard 8051 port outputs) (pull-up)
Push-pull
Input only (high-impedance)
Open drain
The OCI_SCL、ALE、OCI_SDA and RESET can be define as P4.4、P4.5、P4.6 and P4.7 by writer or ISP。
The XTAL2 and XTAL1 can define as P5.4 and P5.5 by writer or ISP，when user use internal OSC as system clock.
For general-purpose applications, every pin can be assigned to either high or low independently as given below:
Mnemonic
Port 5
Port 4
Port 3
Port 2
Port 1
Port 0
Description
Port 5
Port 4
Port 3
Port 2
Port 1
Port 0
Direct
Bit 7
Bit 6
D8h
E8h
B0h
A0h
90h
80h
P4.7
P3.7
P2.7
P1.7
P0.7
P4.6
P3.6
P2.6
P1.6
P0.6
Mnemonic: P0
7
6
P0.7
P0.6
5
P0.5
Bit 5
Ports
P5.5
P4.5
P3.5
P2.5
P1.5
P0.5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESET
P5.4
P4.4
P3.4
P2.4
P1.4
P0.4
P5.3
P4.3
P3.3
P2.3
P1.3
P0.3
P5.2
P4.2
P3.2
P2.2
P1.2
P0.2
P5.1
P4.1
P3.1
P2.1
P1.1
P0.1
P5.0
P4.0
P3.0
P2.0
P1.0
P0.0
0Fh
FFh
FFh
FFh
FFh
FFh
4
P0.4
3
P0.3
2
P0.2
1
P0.1
Address: 80h
0
Reset
P0.0
FFh
4
P1.4
3
P1.3
2
P1.2
1
P1.1
Address: 90h
0
Reset
P1.0
FFh
P0.7~ 0: Port0 [7] ~ Port0 [0]
Mnemonic: P1
7
6
P1.7
P1.6
5
P1.5
P1.7~ 0: Port1 [7] ~ Port1 [0]
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
30
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
Mnemonic: P2
7
6
P2.7
P2.6
5
P2.5
4
P2.4
3
P2.3
2
P2.2
1
P2.1
Address: A0h
0
Reset
P2.0
FFh
4
P3.4
3
P3.3
2
P3.2
1
P3.1
Address: B0h
0
Reset
P3.0
FFh
4
P4.4
3
P4.3
2
P4.2
1
P4.1
Address: E8h
0
Reset
P4.0
FFh
4
P5.4
3
P5.3
2
P5.2
1
P5.1
Address: D8h
0
Reset
P5.0
3Fh
P2.7~ 0: Port2 [7] ~ Port2 [0]
Mnemonic: P3
7
6
P3.7
P3.6
5
P3.5
P3.7~ 0: Port3 [7] ~ Port3 [0]
Mnemonic: P4
7
6
P4.7
P4.6
5
P4.5
P4.7~ 0: Port4 [7] ~ Port4 [0]
Mnemonic: P5
7
6
-
5
P5.5
P5.5~ 0: Port5 [5] ~ Port5 [0]
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
31
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
6. Multiplication Division Unit (MDU)
This on-chip arithmetic unit provides 32-bit division, 16-bit multiplication, shift and normalize features, etc. All operations
are unsigned integer operations.
Mnemonic
Description
Direct
PCON
Power control
Arithmetic Control
register
Multiplication/Divi
sion Register 0
Multiplication/Divi
sion Register 1
Multiplication/Divi
sion Register 2
Multiplication/Divi
sion Register 3
Multiplication/Divi
sion Register 4
Multiplication/Divi
sion Register 5
87H
Bit 6
Bit 5
Bit 4
Multiplication Division Unit
SMOD MDUF
-
EFh
MDEF
ARCON
MD0
MD1
MD2
MD3
MD4
MD5
6.1.
Bit 7
MDOV
Bit 3
Bit 2
Bit 1
Bit 0
RESET
-
-
STOP
IDLE
40H
SLR
SC[4:0]
00H
00H
E9h
MD0[7:0]
EAh
MD1[7:0]
EBh
MD2[7:0]
ECh
MD3[7:0]
EDh
MD4[7:0]
00H
EEh
MD5[7:0]
00H
00H
00H
00H
Operating registers of the MDU
The MDU is handled by seven registers, which are memory mapped as special function registers. The arithmetic unit
allows operations concurrently to and independent of the CPU’s activity. Operands and results registers are MD0 to MD5.
Control register is ARCON. Any calculation of the MDU overwrites its operands.
Mnemonic: ARCON
7
6
5
MDEF MDOV
SLR
4
3
2
SC[4:0]
1
Address: EFh
0
Reset
00H
MDEF: Multiplication Division Error Flag.
The MDEF is an error flag. The error flag is read only. The error flag indicates an
improperly performed operation (when one of the arithmetic operations has been
restarted or interrupted by a new operation). The error flag mechanism is automatically
enabled with the first write to MD0 and disabled with the final read instruction from MD3
multiplication or shift/normalizing) or MD5 (division) in phase three.
The error flag is set when:
1. Phase two in process and write access to mdx registers (restart or interrupt
calculations)
The error flag is reset only if:
Phase two finished (arithmetic operation successful completed) and read access to MDx
registers.
MDOV: Multiplication Division Overflow flag. The overflow flag is read only.
The overflow flag is set when:
1. Division by Zero
2. Multiplication with a result greater then 0000FFFFh
3. Start of normalizing if the most significant bit of MD3 is set(MD3.7=1)
The overflow flag is reset when:
Write access to MD0 register(Start Phase one)
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
32
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
SLR: Shift direction bit.
SLR = 0 – shift left operation.
SLR = 1 – shift right operation.
SC[4:0]: Shift counter.
When preset with 00000b, normalizing is selected. After normalize sc.0 – sc.4 contains
the number of normalizing shifts performed. When sc.4 – sc.0 ≠ 0, shift operation is
started. The number of shifts performed is determined by the count written to sc.4 to sc.0.
sc.4 – MSB ... sc.0 – LSB
6.2.
Operation of the MDU
The operation of the MDU consists of three phases:
6.2.1.
First phase: loading the MDx registers, x = 0~5:
The type of calculation the MDU has to perform is selected following the order in which the mdx registers are written to.
Operation
First write
Last write
32bit/16bit
MD0 Dividend Low
MD1 Dividend
MD2 Dividend
MD3 Dividend High
MD4 Divisor Low
MD5 Divisor High
Table 6-1: MDU registers write sequence
16bit/16bit
16bit x 16bit
MD0 Dividend Low
MD0 Multiplicand Low
MD1 Dividend High
MD4 Multiplicator Low
MD1 Multiplicand High
MD4 Divisor Low
MD5 Divisor High
MD5 Multiplicator High
shift/normalizing
MD0 LSB
MD1
MD2
MD3 MSB
ARCON start conversion
A write to md0 is the first transfer to be done in any case. Next writes must be done as shown in table 6.1 to determine
MDU operation. Last write finally starts selected operation.
6.2.2.
Second phase: executing calculation.
During executing operation, the MDU works on its own parallel to the CPU. When MDU is finished, the MDUF register will
be set to one by hardware and the flag will clear at next calculation.
Mnemonic: PCON
7
6
SMOD MDUF
5
-
4
-
3
-
2
-
1
STOP
Address: 87h
0
Reset
IDLE
40h
MDUF: MDU finish flag.
When MDU is finished, the MDUF will be set by hardware and the bit will clear
by hardware at next calculation.
The following table gives the execution time in every mathematical operation.
Operation
Division 32bit/16bit
Division 16bit/16bit
Multiplication
Shift
Normalize
6.2.3.
Table 6-2: MDU execution times
Number of Tclk
17 clock cycles
9 clock cycles
11 clock cycles
Min. 3 clock cycles, Max. 18 clock cycles
Min. 4 clock cycles, Max. 19 clock cycles
Third phase: reading the result from the MDx registers.
Read out sequence of the first MDx registers is not critical but the last read (from MD5 - division and MD3 - multiplication,
shift and normalizing) determines the end of a whole calculation (end of phase three).
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
33
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
Operation
First read
Last read
Table 6-3: MDU registers read sequence
32Bit/16Bit
16Bit/16Bit
16Bit x 16Bit
MD0 Quotient Low
MD0 Quotient Low
MD0 Product Low
MD1 Quotient
MD1 Quotient High
MD1 Product
MD2 Quotient
MD2 Product
MD3 Quotient High
MD4 Remainder L
MD4 Remainder Low
MD5 Remainder H
MD5 Remainder High
MD3 Product High
shift/normalizing
MD0 LSB
MD1
MD2
MD3 MSB
Here the operation of normalization and shift will be explained more. In normalization, all reading zeroes in registers
MD0 to MD3 are removed by shift left. The whole operation is completed when the MSB (most significant bit) of MD3
register contains a ’1’. After normalizing, bits ARCON.4 (MSB) to ARCON.0 (LSB) contain the number of shift left
operations. As for shift, SLR bit (ARCON.5) has to contain the shift direction, and ARCON.4 to ARCON.0 represent the
shift count (which must not be 0). During shift, zeroes come into the left or right end of the registers MD0 or MD3,
respectively.
6.3.
Normalizing
All reading zeroes of integers variables in registers MD0 to MD3 are removed by shift left operations. The whole operation
is completed when the MSB (most significant bit) of MD3 register contains a ’1’. After normalizing, bits ARCON.4 (MSB)
to ARCON.0 (LSB) contain the number of shift left operations, which were done.
6.4.
Shifting
SLR bit (ARCON.5) has to contain the shift direction, and ARCON.4 to ARCON.0 the shift count (which must not be 0).
During shift, zeroes come into the left or right end of the registers MD0 or MD3, respectively.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
34
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
7. Timer 0 and Timer 1
The SM59R16A3 has three 16-bit timer/counter registers: Timer 0, Timer 1 and Timer 2. All can be configured for counter
or timer operations.
In timer mode, the Timer 0 register or Timer 1 register is incremented every 12 machine cycles, which means that it
counts up after every 12 periods of the clk signal.
In counter mode, the register is incremented when the falling edge is observed at the corresponding input pin T0or T1.
Since it takes 2 machine cycles to recognize a 1-to-0 event, the maximum input count rate is 1/2 of the oscillator
frequency. There are no restrictions on the duty cycle, however to ensure proper recognition of 0 or 1 state, an input
should be stable for at least 1 machine cycle.
Four operating modes can be selected for Timer 0 and Timer 1. Two Special Function registers (TMOD and TCON) are
used to select the appropriate mode.
Mnemonic
Description
Direct
TL0
Timer 0 , low byte
Timer 0 , high
byte
Timer 1 , low byte
Timer 1 , high
byte
Timer Mode
Control
Timer/Counter
Control
8Ah
TL0[7:0]
00h
8Ch
TH0[7:0]
00h
8Bh
TL1[7:0]
00h
8Dh
TH1[7:0]
00h
TH0
TL1
TH1
TMOD
TCON
7.1.
Bit 7
Bit 6
Bit 5
Timer 0 and 1
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESET
89h
GATE
C/T
M1
M0
GATE
C/T
M1
M0
00h
88h
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
00h
Timer/counter mode control register (TMOD)
Mnemonic: TMOD
7
6
5
GATE
C/T
M1
Timer 1
4
M0
3
GATE
2
1
C/T
M1
Timer 0
Address: 89h
0
Reset
M0
00h
GATE: If set, enables external gate control (pin INT0 or INT1 for Counter 0 or 1,
respectively). When INT0 or INT1 is high, and TRx bit is set (see TCON register), a
counter is incremented every falling edge on T0 or T1 input pin
C/T: Selects Timer or Counter operation. When set to 1, a counter operation is performed,
when cleared to 0, the corresponding register will function as a timer.
M[1:0]: Selects mode for Timer/Counter 0 or Timer/Counter 1.
M1
M0
Mode
Function
0
0
Mode0
13-bit counter/timer, with 5 lower bits in TL0 or TL1
register and 8 bits in TH0 or TH1 register (for Timer 0
and Timer 1, respectively). The 3 high order bits of
TL0 and TL1 are hold at zero.
0
1
Mode1
16-bit counter/timer.
1
0
Mode2
8 -bit auto-reload counter/timer. The reload value is
kept in TH0 or TH1, while TL0 or TL1 is incremented
every machine cycle. When TLx overflows, a value
from THx is copied to TLx.
1
1
Mode3
If Timer 1 M1 and M0 bits are set to 1, Timer 1 stops.
If Timer 0 M1 and M0 bits are set to 1, Timer 0 acts
as two independent 8 bit timers / counters.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
35
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
7.2.
Timer/counter control register (TCON)
Mnemonic: TCON
7
6
5
TF1
TR1
TF0
4
TR0
3
IE1
2
IT1
1
IE0
Address: 88h
0
Reset
IT0
00h
TF1: Timer 1 overflow flag set by hardware when Timer 1 overflows. This flag can
be cleared by software and is automatically cleared when interrupt is
processed.
TR1: Timer 1 Run control bit. If cleared, Timer 1 stops.
TF0: Timer 0 overflow flag set by hardware when Timer 0 overflows. This flag can
be cleared by software and is automatically cleared when interrupt is
processed.
TR0: Timer 0 Run control bit. If cleared, Timer 0 stops.
IE1: Interrupt 1 edge flag. Set by hardware, when falling edge on external pin INT1
is observed. Cleared when interrupt is processed.
IT1: Interrupt 1 type control bit. Selects falling edge or low level on input pin to
cause interrupt.
IE0: Interrupt 0 edge flag. Set by hardware, when falling edge on external pin INT0
is observed. Cleared when interrupt is processed.
IT0: Interrupt 0 type control bit. Selects falling edge or low level on input pin to
cause interrupt.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
36
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
8. Timer 2 and Capture/Compare Unit
Timer 2 is not only a 16-bit timer, also a 4-channel unit with compare, capture and reload functions. It is very similar to
the programmable counter array (PCA) in some other MCUs except pulse width modulation (PWM).
Mnemonic
Description
Direct
AUX2
T2CON
Auxiliary register2
Timer 2 control
Compare/Capture
Control
Compare/Capture
Enable register
Compare/Capture
Enable 2 register
Timer 2, low byte
Timer 2, high byte
Compare/Reload/
Capture register,
low byte
Compare/Reload/
Capture register,
high byte
Compare/Capture
register 1, low
byte
Compare/Capture
register 1, high
byte
Compare/Capture
register 2, low
byte
Compare/Capture
register 2, high
byte
Compare/Capture
register 3, low
byte
Compare/Capture
register 3, high
byte
CCCON
CCEN
CCEN2
TL2
TH2
CRCL
CRCH
CCL1
CCH1
CCL2
CCH2
CCL3
CCH3
Bit 2
92h
C8h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Timer 2 and Capture Compare Unit
T2PS[2:0]
T2R[1:0]
C9h
CCI3
CCF2
C1h
-
COCAM1[2:0]
-
COCAM0[2:0]
00h
D1h
-
COCAM3[2:0]
-
COCAM2[2:0]
00h
CCI2
CCI1
CCI0
CCF3
CCh
CDh
TL2[7:0]
TH2[7:0]
CAh
CRCL[7:0]
CBh
CRCH[7:0]
C2h
CCL1[7:0]
C3h
CCH1[7:0]
C4h
CCL2[7:0]
C5h
CCH2[7:0]
C6h
CCL3[7:0]
C7h
CCH3[7:0]
-
Bit 1
Bit 0
P42CC[1:0]
T2I[1:0]
CCF1
CCF0
RESET
00H
00h
00H
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
Mnemonic: AUX2
7
6
5
4
3
Address: 92h
1
0
Reset
P42CC[1: 0]
00H
2
P42CC[1: 0] 00: Capture/Compare function on Port1.
01: Capture/Compare function on Port2
10: Capture/Compare function on Port4
11: reserved
Mnemonic: T2CON
7
6
5
T2PS[2:0]
4
3
T2R[1:0]
2
-
1
Address: C8h
0
Reset
T2I[1:0]
00H
T2PS[2:0]: Prescaler select bit:
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
37
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
T2PS = 000 – timer 2 is clocked with the oscillator frequency.
T2PS = 001 – timer 2 is clocked with 1/2 of the oscillator frequency.
T2PS = 010 – timer 2 is clocked with 1/4 of the oscillator frequency.
T2PS = 011 – timer 2 is clocked with 1/6 of the oscillator frequency.
T2PS = 100 – timer 2 is clocked with 1/8 of the oscillator frequency.
T2PS = 101 – timer 2 is clocked with 1/12 of the oscillator frequency.
T2PS = 110 – timer 2 is clocked with 1/24 of the oscillator frequency.
T2R[1:0]: Timer 2 reload mode selection
T2R[1:0] = 0X – Reload disabled
T2R[1:0] = 10 – Mode 0: Auto Reload
T2R[1:0] = 11 – Mode 1: T2EX Falling Edge Reload
T2I[1:0]: Timer 2 input selection
T2I[1:0] = 00 – Timer 2 stop
T2I[1:0] = 01 – Input frequency from prescaler(T2PS[2:0])
T2I[1:0] = 10 – Timer 2 is incremented by external signal at pin T2
T2I[1:0] = 11 – internal clock input is gated to the Timer 2
Mnemonic: CCCON
7
6
5
CCI3
CCI2
CCI1
4
CCI0
3
CCF3
2
CCF2
1
CCF1
Address: C9h
0
Reset
CCF0
00H
CCI3: Compare/Capture 3 interrupt control bit.
“1” is enable.
CCI2: Compare/Capture 2 interrupt control bit.
“1” is enable.
CCI1: Compare/Capture 1 interrupt control bit.
“1” is enable.
CCI0: Compare/Capture 0 interrupt control bit.
“1” is enable.
CCF3: Compare/Capture 3 flag set by hardware. This flag can be cleared by software.
CCF2: Compare/Capture 2 flag set by hardware. This flag can be cleared by software.
CCF1: Compare/Capture 1 flag set by hardware. This flag can be cleared by software.
CCF0: Compare/Capture 0 flag set by hardware. This flag can be cleared by software.
Compare/Capture interrupt share T2 interrupt vector.
Mnemonic: CCEN
7
6
5
4
-COCAM1[2:0]
3
--
2
Address: C1h
1
0
Reset
COCAM0[2:0]
00H
COCAM1[2:0] 000: Compare/Capture disable
001: Compare enable but no output on Pin
010: Compare mode 0
011: Compare mode 1
100: Capture on rising edge at pin CC1
101: Capture on falling edge at pin CC1
110: Capture on both rising and falling edge at pin CC1
111: Capture on write operation into register CC1
COCAM0[2:0] 000: Compare/Capture disable
001: Compare enable but no output on Pin
010: Compare mode 0
011: Compare mode 1
100: Capture on rising edge at pin CC0
101: Capture on falling edge at pin CC0
110: Capture on both rising and falling edge at pin CC0
111: Capture on write operation into register CC0
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
38
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
Mnemonic: CCEN2
7
6
5
4
-COCAM3[2:0]
3
--
2
Address: D1h
1
0
Reset
COCAM2[2:0]
00H
COCAM3[2:0] 000: Compare/Capture disable
001: Compare enable but no output on Pin
010: Compare mode 0
011: Compare mode 1
100: Capture on rising edge at pin CC3
101: Capture on falling edge at pin CC3
110: Capture on both rising and falling edge at pin CC3
111: Capture on write operation into register CC3
COCAM2[2:0] 000: Compare/Capture disable
001: Compare enable but no output on Pin
010: Compare mode 0
011: Compare mode 1
100: Capture on rising edge at pin CC2
101: Capture on falling edge at pin CC2
110: Capture on both rising and falling edge at pin CC2
111: Capture on write operation into register CC2
8.1.
Timer 2 function
Timer 2 can operate as timer, event counter, or gated timer as explained later.
8.1.1.
Timer mode
In this mode Timer 2 can by incremented in various frequency that depending on the prescaler. The prescaler is selected
by bit T2PS[2:0] in register T2CON.
8.1.2.
Event counter mode
In this mode, the timer is incremented when external signal T2 change value from 1 to 0. The T2 input is sampled in
every cycle. Timer 2 is incremented in the cycle following the one in which the transition was detected.
8.1.3.
Gated timer mode
In this mode, the internal clock which incremented timer 2 is gated by external signal T2.
8.1.4.
Reload of Timer 2
Reload (16-bit reload from the crc register) can be executed in the following two modes:
Mode 0: Reload signal is generate by a Timer 2 overflows - auto reload
Mode 1: Reload signal is generate by a negative transition at the corresponding input pin T2EX.
8.2.
Compare function
In the four independent comparators, the value stored in any compare/capture register is compared with the contents of
the timer register. The compare modes 0 and 1 are selected by bits C0CAMx. In both compare modes, the results of
comparison arrives at Port 1 within the same machine cycle in which the internal compare signal is activated.
When the channel 1、2 and 3 use at compare function，The compare mode setting of Channel 2 and Channel 3 should be
same as the compare mode setting of channel 1.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
39
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
8.2.1.
Compare Mode 0
In mode 0, when the value in Timer 2 equals the value of the compare register, the output signal changes from low to high.
It goes back to a low level on timer overflow. In this mode, writing to the port will have no effect, because the input line
from the internal bus and the write-to-latch line are disconnected. The following figure illustrates the function of compare
mode 0.
Fig. 8-1: Compare mode 0 function
8.2.2.
Compare Mode 1
In compare mode 1, the transition of the output signal can be determined by software. A timer 2 overflow causes no
output change. In this mode, both transitions of a signal can be controlled. Fig. 8-2 shows a functional diagram of a
register/port configuration in compare Mode 1. In compare Mode 1, the value is written first to the “Shadow Register”,
when compare signal is active, this value is transferred to the output register.
Fig. 8-2: Compare mode 1 function
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
40
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
8.3.
Capture function
Actual timer/counter contents can be saved into registers CCx or CRC upon an external event (mode 0) or a software
write operation (mode 1).
8.3.1.
Capture Mode 0
In mode 0, value capture of Timer 2 is executed when:
(a) Rising edge on input CC0-CC3
(b) Falling edge on input CC0-CC3
(c) Both rising and falling edge on input CC0-CC3
The contents of Timer 2 will be latched into the appropriate capture register.
8.3.2.
Capture Mode 1
In mode 1, value capture of timer 2 is caused by writing any value into the low-order byte of the dedicated capture register.
The value written to the capture register is irrelevant to this function. The contents of Timer 2 will be latched into the
appropriate capture register.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
41
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
9. Serial interface 0 and 1
There are two serial interfaces for data communication in SM59R16A3, they are the so called UART0 and UART1.
As the conventional UART, the communication speed can be selected by configuring the baud rate in SFRs.
These two serial buffers consists of two separate registers, a transmit buffer and a receive buffer. Writing data to the
SFR S0BUF or S1BUF sets this data in serial output buffer and starts the transmission. Reading from the S0BUF or
S1BUF reads data from the serial receive buffer. The serial port can simultaneously transmit and receive data. It can
also buffer 1 byte at receive, which prevents the receive data from being lost if the CPU reads the second byte before the
transmission of the first byte is completed.
Mnemonic
PCON
AUX
S0CON
S0RELL
S0RELH
S0BUF
S1CON
S1RELL
S1RELH
S1BUF
Description
Power control
Auxiliary
register
Serial Port 0
control register
Serial Port 0
reload register
low byte
Serial Port 0
reload register
high byte
Serial Port 0
data buffer
Serial Port 1
control register
Serial Port 1
reload register
low byte
Serial Port 1
reload register
high byte
Serial Port 1
data buffer
Direct
Bit 7
Bit 6
Bit 5
Bit 4
Serial interface 0 and 1
MDUF
P4UR
P4SPI
1
Bit 3
Bit 2
Bit 1
Bit 0
RESET
87h
SMOD
-
-
IDLE
40h
P4IIC
P0KBI
STOP
P2PW
M
91h
BRGS
DPS
00H
98h
SM0
SM1
SM20
REN0
TB80
RB80
TI0
RI0
00h
AAh
S0REL
.7
S0REL
.6
S0REL
.5
S0REL
.4
S0REL
.3
S0REL
.2
S0REL
.1
S0REL
.0
00h
BAh
-
-
-
-
-
-
S0REL
.9
S0REL
.8
00h
99h
S0BUF[7:0]
00h
9Bh
SM
-
SM21
REN1
TB81
RB81
TI1
RI1
00h
9Dh
S1REL
.7
S1REL
.6
S1REL
.5
S1REL
.4
S1REL
.3
S1REL
.2
S1REL
.1
S1REL
.0
00h
BBh
-
-
-
-
-
-
S1REL
.9
S1REL
.8
00h
9Ch
Mnemonic: AUX
7
6
5
BRGS
P4SPI
S1BUF[7:0]
4
P4UR1
3
P4IIC
2
P0KBI
1
P2PWM
00h
Address: 91h
0
Reset
DPS
00H
P4UR1: P4UR1 = 0 – Serial interface 1 function on P1.
P4UR1 = 1 – Serial interface 1 function on P4.
Mnemonic: S0CON
7
6
5
SM0
SM1
SM20
4
REN0
3
TB80
2
RB80
1
TI0
Address: 98h
0
Reset
RI0
00h
SM0,SM1: Serial Port 0 mode selection.
SM0 SM1
Mode
0
0
0
0
1
1
1
0
2
1
1
3
The 4 modes in UART0, Mode 0 ~ 3, are explained later.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
42
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
SM20: Enables multiprocessor communication feature
REN0: If set, enables serial reception. Cleared by software to disable reception.
TB80: The 9th transmitted data bit in modes 2 and 3. Set or cleared by the CPU
depending on the function it performs such as parity check, multiprocessor
communication etc.
RB80: In modes 2 and 3, it is the 9th data bit received. In mode 1, if SM20 is 0, RB80
is the stop bit. In mode 0, this bit is not used. Must be cleared by software.
TI0: Transmit interrupt flag, set by hardware after completion of a serial transfer.
Must be cleared by software.
RI0: Receive interrupt flag, set by hardware after completion of a serial reception.
Must be cleared by software.
Mnemonic: S1CON
7
6
5
SM
SM21
4
REN1
3
TB81
2
RB81
1
TI1
Address: 9Bh
0
Reset
RI1
00h
SM: Serial Port 1 mode select.
SM
Mode
0
A
1
B
The 2 modes in UART1, Mode A and Mode B, are explained later.
SM21: Enables multiprocessor communication feature.
REN1: If set, enables serial reception. Cleared by software to disable reception.
TB81: The 9th transmitted data bit in mode A. Set or cleared by the CPU depending on
the function it performs such as parity check, multiprocessor communication
etc.
RB81: In mode A, it is the 9th data bit received. In mode B, if SM21 is 0, RB81 is the
stop bit. Must be cleared by software.
TI1: Transmit interrupt flag, set by hardware after completion of a serial transfer.
Must be cleared by software.
RI1: Receive interrupt flag, set by hardware after completion of a serial reception.
Must be cleared by software.
9.1.
Serial interface 0
The Serial Interface 0 can operate in the following 4 modes:
SM0
0
0
1
1
SM1
0
1
0
1
Mode
0
1
2
3
Description
Shift register
8-bit UART
9-bit UART
9-bit UART
Board Rate
Fosc/12
Variable
Fosc/32 or Fosc/64
Variable
Here Fosc is the crystal or oscillator frequency.
9.1.1.
Mode 0
Pin RXD0 serves as input and output. TXD0 outputs the shift clock. 8 bits are transmitted with LSB first. The baud
rate is fixed at 1/12 of the crystal frequency. Reception is initialized in Mode 0 by setting the flags in S0CON as follows:
RI0 = 0 and REN0 = 1. In the other modes, a start bit when REN0 = 1 starts receiving serial data.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
43
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
Fig. 9-1: Transmit mode 0 for Serial 0
Fig. 9-2: Receive mode 0 for Serial 0
9.1.2.
Mode 1
Here Pin RXD0 serves as input, and TXD0 serves as serial output. No external shift clock is used, 10 bits are
transmitted: a start bit (always 0), 8 data bits (LSB first), and a stop bit (always 1). On receive, a start bit synchronizes
the transmission, 8 data bits are available by reading S0BUF, and a stop bit sets the flag RB80 in the SFR S0CON. In
mode 1, either internal baud rate generator or timer 1 can be use to specify the desired baud rate.
Fig. 9-3: Transmit mode 1 for Serial 0
Fig. 9-4: Receive mode 1 for Serial 0
9.1.3.
Mode 2
This mode is similar to Mode 1, but with two differences. The baud rate is fixed at 1/32 (SMOD=1) or 1/64(SMOD=0) of
oscillator frequency, and 11 bits are transmitted or received: a start bit (0), 8 data bits (LSB first), a programmable Bit 9,
and a stop bit (1). Bit 9 can be used to control the parity of the serial interface: at transmission, bit TB80 in S0CON is
output as Bit 9, and at receive, Bit 9 affects RB80 in SFR S0CON.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
44
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
9.1.4.
Mode 3
The only difference between Mode 2 and Mode 3 is that: in Mode 3, either internal baud rate generator or timer 1 can be
use to specify baud rate.
Fig. 9-5: Transmit modes 2 and 3 for Serial 0
Fig. 9-6: Receive modes 2 and 3 for Serial 0
9.2.
Serial interface 1
The interrupt vector is 83h.
The Serial Interface 1 can operate in the following 2 modes:
SM
0
1
9.2.1.
Mode
A
B
Description
9-bit UART
8-bit UART
Baud Rate
Variable
Variable
Mode A
This mode is similar to Mode 2 and 3 of Serial interface 0, 11 bits are transmitted or received: a start bit (0), 8 data bits
(LSB first), a programmable Bit 9, and a stop bit (1). Bit 9 can be used to control the parity of the serial interface: at
transmission, bit TB81 in S1CON is outputted as Bit 9, and at receive, Bit 9 affects RB81 in SFR S1CON.
Fig. 9-7: Transmit mode A for Serial 1
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
45
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
Fig. 9-8: Receive mode A for Serial 1
9.2.2.
Mode B
This mode is similar to Mode 1 of Serial interface 0. Pin RXD1 serves as input, and TXD1 serves as serial output. No
external shift clock is used. 10 bits are transmitted: a start bit (always 0), 8 data bits (LSB first), and a stop bit (always 1).
On receive, a start bit synchronizes the transmission, 8 data bits are available by reading S1BUF, and stop bit sets the
flag RB81 in the SFR S1CON. In mode B, internal baud rate generator is use to specify the baud rate.
Fig. 9-9: Transmit mode B for Serial 1
Fig. 9-10: Receive mode B for Serial 1
9.3.
Multiprocessor communication of Serial Interface 0 and 1
The feature of receiving 9 bits in Modes 2 and 3 of Serial Interface 0 or in Mode A of Serial Interface 1 can be used for
multiprocessor communication. In this case, the slave processors have bit SM20 in S0CON or SM21 in S1CON set to 1.
When the master processor outputs slave’s address, it sets the Bit 9 to 1, causing a serial port receive interrupt in all the
slaves. The slave processors compare the received byte with their network address. If matched, the addressed slave
will clear SM20 or SM21 and receive the rest of the message, while other slaves will leave SM20 or SM21 bit unaffected
and ignore this message. After addressing the slave, the host will output the rest of the message with the Bit 9 set to 0, so
no serial port receive interrupt will be generated in unselected slaves.
9.4.
Baud rate generator
9.4.1.
Serial interface 0 modes 1 and 3
(a) When BRGS = 0 (in SFR AUX):
Baud Rate =
2SMOD × FOSC
32 × 12 × (256 − TH1)
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
46
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
(b) When BRGS = 1 (in SFR AUX):
9.4.2.
9.5.
Baud Rate =
2SMOD × FOSC
64 × 210 − S0REL
)
Baud Rate =
FOSC
32 × 2 − S1REL
)
(
Serial interface 1 modes A and B
(
10
Clock source for baud rate
It is not recommended to use the on-chip RC-Oscillator frequency as the clock source when the serial interface functions
are used. In case of application with higher clock precision requirement, external Crystal is usually recommended clock
source.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
47
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
10. Watchdog timer
The Watch Dog Timer (WDT) is an 8-bit free-running counter that generate reset signal if the counter overflows. The WDT
is useful for systems which are susceptible to noise, power glitches, or electronics discharge which causing software
dead loop or runaway. The WDT function can help user software recover from abnormal software condition. The WDT is
different from Timer0, Timer1 and Timer2 of general 8052. To prevent a WDT reset can be done by software periodically
clearing the WDT counter. User should check WDTF bit of WDTC register whenever un-predicted reset happened. After
an external reset the watchdog timer is disabled and all registers are set to zeros.
The watchdog timer has a free running on-chip RC oscillator (250KHz ±20%). The WDT will keep on running even after
the system clock has been turned off (for example, in sleep mode). During normal operation or sleep mode, a WDT
time-out (if enabled) will cause the MCU to reset. The WDT can be enabled or disabled any time during the normal mode.
Please refer the WDTE bit of WDTC register. The default WDT time-out period is approximately 16.38ms (WDTM [3:0] =
0100b).
The WDT has selectable divider input for the time base source clock. To select the divider input, the setting of bit3 ~ bit0
(WDTM [3:0]) of Watch Dog Timer Control Register (WDTC) should be set accordingly.
250KHz
2WDTM
256
Watchdog reset time =
WDTCLK
WDTCLK =
WDTM [3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Table 10.1 WDT time-out period
Divider
Time period @ 250KHz
(250 KHz RC oscillator in)
1
1.02ms
2
2.05ms
4
4.10ms
8
8.19ms
16
16.38ms (default)
32
32.77ms
64
65.54ms
128
131.07ms
256
262.14ms
512
524.29ms
1024
1.05s
2048
2.10s
4096
4.19s
8192
8.39s
16384
16.78s
32768
33.55s
When MCU is reset, the MCU will be read WDTEN control bit status. When WDTEN bit is set to 1, the watchdog function
will be disabled no matter what the WDTE bit status is. When WDTEN bit is clear to 0, the watchdog function will be
enabled if WDTE bit is set to 1 by program. User can to set WDTEN on the writer or ISP.
The program can enable the WDT function by programming 1 to the WDTE bit premise that WDTEN control bit is clear to
0. After WDTE set to 1, the 8 bit-counter starts to count with the selected time base source clock which set by WDTM [3:0].
It will generate a reset signal when overflows. The WDTE bit will be cleared to 0 automatically when MCU been reset,
either hardware reset or WDT reset.
Once the watchdog is started it cannot be stopped. User can refreshed the watchdog timer to zero by writing 0x55 to
Watch Dog Timer refresh Key (WDTK) register. This will clear the content of the 8-bit counter and let the counter re-start
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
48
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
to count from the beginning. The watchdog timer must be refreshed regularly to prevent reset request signal from
becoming active.
When Watchdog timer is overflow, the WDTF flag will set to one and automatically reset MCU. The WDTF flag can be
clear by software or external reset or power on reset.
1
2WDTM
Fig. 10-1: Watchdog timer block diagram
Mnemonic
TAKEY
WDTC
WDTK
Description
Direct
Time Access Key
register
Watchdog timer
control register
Watchdog timer
refresh key
Bit 7
Bit 6
Bit 5
Bit 4
Watchdog Timer
F7h
B6h
Bit 3
Bit 2
Bit 1
Bit 0
RESET
TAKEY [7:0]
WDTF
-
WDTE
-
B7h
Mnemonic: TAKEY
7
6
5
00H
WDTM [3:0]
WDTK[7:0]
4
3
TAKEY [7:0]
2
1
04H
00H
Address: F7h
0
Reset
00H
Watchdog timer control register (WDTC) is read-only by default; software must write three specific
values 55h, AAh and 5Ah sequentially to the TAKEY register to enable the WDTC write attribute. That is:
MOV TAKEY, #55h
MOV TAKEY, #AAh
MOV TAKEY, #5Ah
Mnemonic: WDTC
7
6
5
WDTF
WDTE
4
-
3
2
1
WDTM [3:0]
Address: B6h
0
Reset
04H
WDTF: Watchdog timer reset flag.
When MCU is reset by watchdog, WDTF flag will be set to one by hardware. This flag
clear by software or external reset or power on reset.
WDTE: Control bit used to enable Watchdog timer.
The WDTE bit can be used only if WDTEN is "0". If the WDTEN bit is "0", then WDT
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
49
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
can be disabled / enabled by the WDTE bit.
0: Disable WDT.
1: Enable WDT.
The WDTE bit is not used if WDTEN is "1". That is, if the WDTEN bit is "1", WDT is
always disabled no matter what the WDTE bit status is. The WDTE bit can be read and
written.
WDTM [3:0]: WDT clock source divider bit. Please see table 10.1 to reference the WDT time-out
period.
Mnemonic: WDTK
7
6
5
4
3
WDTK[7:0]
2
1
Address: B7h
0
Reset
00h
WDTK: Watchdog timer refresh key.
A programmer must write 0x55 into WDTK register, and then the watchdog
timer will be cleared to zero.
For example, if enable WDT and select time-out reset period is 262.14ms.
First, programming the WDTEN to “0”.
Secondly,
MOV TAKEY, #55h
MOV TAKEY, #AAh
MOV TAKEY, #5Ah
; enable WDTC write attribute.
MOV WDTC, #28h
; Set WDTM [3:0] = 1000b. Set WDTE =1 to enable WDT
; function.
.
.
.
MOV WDTK, #55h
; Clear WDT timer to 0.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
50
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
11. Interrupt
The SM59R16A3 provides 13 interrupt sources with four priority levels. Each source has its own request flag(s) located in
a special function register. Each interrupt requested by the corresponding flag could individually be enabled or disabled
by the enable bits in SFR’s IEN0, IEN1, and IEN2.
When the interrupt occurs, the engine will vector to the predetermined address as shown in Table 11.1. Once interrupt
service has begun, it can be interrupted only by a higher priority interrupt. The interrupt service is terminated by a return
from instruction RETI. When an RETI is performed, the processor will return to the instruction that would have been next
when interrupt occurred.
When the interrupt condition occurs, the processor will also indicate this by setting a flag bit. This bit is set regardless of
whether the interrupt is enabled or disabled. Each interrupt flag is sampled once per machine cycle, and then samples are
polled by hardware. If the sample indicates a pending interrupt when the interrupt is enabled, then interrupt request flag is
set. On the next instruction cycle the interrupt will be acknowledged by hardware forcing an LCALL to appropriate vector
address.
Interrupt response will require a varying amount of time depending on the state of microcontroller when the interrupt
occurs. If microcontroller is performing an interrupt service with equal or greater priority, the new interrupt will not be
invoked. In other cases, the response time depends on current instruction. The fastest possible response to an interrupt is
7 machine cycles. This includes one machine cycle for detecting the interrupt and six cycles for perform the LCALL.
Table 11-1: Interrupt vectors
Interrupt Vector
Interrupt Request Flags
Address
IE0 – External interrupt 0
0003h
TF0 – Timer 0 interrupt
000Bh
Interrupt Number
*(use Keil C Tool)
0
1
IE1 – External interrupt 1
0013h
2
TF1 – Timer 1 interrupt
RI0/TI0 – Serial channel 0 interrupt
TF2/EXF2 – Timer 2 interrupt
001Bh
0023h
002Bh
3
4
5
PWMIF – PWM interrupt
0043h
8
SPIIF – SPI interrupt
004Bh
9
ADCIF – A/D converter interrupt
KBIIF – keyboard Interface interrupt
LVIIF – Low Voltage Interrupt
IICIF – IIC interrupt
RI1/TI1 – Serial channel 1 interrupt
0053h
005Bh
0063h
006Bh
0083h
10
11
12
13
16
*See Keil C about C51 User’s Guide about Interrupt Function description
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
51
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
Mnemonic
IEN0
IEN1
IEN2
IRCON
IP0
IP1
Description
Interrupt Enable
0 register
Interrupt Enable
1 register
Interrupt Enable
2 register
Interrupt request
register
Interrupt priority
level 0
Interrupt priority
level 1
Direct
Bit 7
Bit 6
Bit 5
Interrupt
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESET
A8h
EA
-
ET2
ES0
ET1
EX1
ET0
EX0
00h
B8h
EXEN2
-
IEIIC
IELVI
IEKBI
IEADC
IESPI
IEPWM
00h
9Ah
-
-
-
-
-
-
-
ES1
00h
C0H
EXF2
TF2
IICIF
LVIIF
KBIIF
ADCIF
SPIIF
PWMIF
00H
A9h
-
-
IP0.5
IP0.4
IP0.3
IP0.2
IP0.1
IP0.0
00h
B9h
-
-
IP1.5
IP1.4
IP1.3
IP1.2
IP1.1
IP1.0
00h
Interrupt Enable 0 register(IEN0)
Mnemonic: IEN0
7
6
EA
-
5
ET2
4
ES0
3
ET1
2
EX1
1
ET0
Address: A8h
0
Reset
EX0
00h
EA: EA=0 – Disable all interrupt.
EA=1 – Enable all interrupt.
ET2: ET2=0 – Disable Timer 2 overflow or external reload interrupt.
ET2=1 – Enable Timer 2 overflow or external reload interrupt.
ES0: ES0=0 – Disable Serial channel 0 interrupt.
ES0=1 – Enable Serial channel 0 interrupt.
ET1: ET1=0 – Disable Timer 1 overflow interrupt.
ET1=1 – Enable Timer 1 overflow interrupt.
EX1: EX1=0 – Disable external interrupt 1.
EX1=1 – Enable external interrupt 1.
ET0: ET0=0 – Disable Timer 0 overflow interrupt.
ET0=1 – Enable Timer 0 overflow interrupt.
EX0: EX0=0 – Disable external interrupt 0.
EX0=1 – Enable external interrupt 0.
Interrupt Enable 1 register(IEN1)
Mnemonic: IEN1
7
6
EXEN2
-
5
IEIIC
4
IELVI
3
IEKBI
2
IEADC
1
IESPI
Address: B8h
0
Reset
IEPWM
00h
EXEN2: Timer 2 reload interrupt enable.
EXEN2 = 0 – Disable Timer 2 external reload interrupt.
EXEN2 = 1 – Enable Timer 2 external reload interrupt.
IEIIC: IIC interrupt enable.
IEIICS = 0 – Disable IIC interrupt.
IEIICS = 1 – Enable IIC interrupt.
IELVI: LVI interrupt enable.
IELVI = 0 – Disable LVI interrupt.
IELVI = 1 – Enable LVI interrupt.
IEKBI: KBI interrupt enable.
IEKBI = 0 – Disable KBI interrupt.
IEKBI = 1 – Enable KBI interrupt.
IEADC: A/D converter interrupt enable
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
52
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
IEADC = 0 – Disable ADC interrupt.
IEADC = 1 – Enable ADC interrupt.
IESPI: SPI interrupt enable.
IESPI = 0 – Disable SPI interrupt.
IESPI = 1 – Enable SPI interrupt.
IEPWM: PWM interrupt enable.
IEPWM = 0 – Disable PWM interrupt.
IEPWM = 1 – Enable PWM interrupt.
Interrupt Enable 2 register(IEN2)
Mnemonic: IEN2
7
6
-
5
-
4
-
3
-
2
-
1
-
2
ADCIF
1
SPIIF
Address: 9Ah
0
Reset
ES1
00h
ES1: ES1=0 – Disable Serial channel 1 interrupt.
ES1=1 – Enable Serial channel 1 interrupt.
Interrupt request register(IRCON)
Mnemonic: IRCON
7
6
5
EXF2
TF2
IICIF
4
LVIIF
3
KBIIF
Address: C0h
0
Reset
PWMIF
00H
EXF2: Timer 2 external reloads flag. Must be cleared by software.
TF2: Timer 2 overflows flag. Must be cleared by software.
IICIF: IIC interrupt flag.
LVIIF: LVI interrupt flag.
KBIIF: KBI interrupt flag.
ADCIF: A/D converter end interrupt flag.
SPIIF: SPI interrupt flag.
PWMIF: PWM interrupt flag. Must be cleared by software.
11.1.
Priority level structure
All interrupt sources are combined in groups:
External interrupt 0
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
Serial channel 0 interrupt
Timer 2 interrupt
Table 11-2: Priority level groups
Groups
Serial channel 1 interrupt
-
PWM interrupt
SPI interrupt
ADC interrupt
KBI interrupt
LVI interrupt
IIC interrupt
Each group of interrupt sources can be programmed individually to one of four priority levels by setting or clearing one bit
in the special function register IP0 and one in IP1. If requests of the same priority level will be received simultaneously, an
internal polling sequence determines which request is serviced first.
Mnemonic: IP0
7
6
-
5
IP0.5
4
IP0.4
3
IP0.3
2
IP0.2
1
IP0.1
Address: A9h
0
Reset
IP0.0
00h
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
53
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
Mnemonic: IP1
7
6
-
5
IP1.5
4
IP1.4
3
IP1.3
2
IP1.2
1
IP1.1
Address: B9h
0
Reset
IP1.0
00h
Table 11-3: Priority levels
IP1.x
IP0.x
Priority Level
0
0
1
1
Bit
IP1.0, IP0.0
IP1.1, IP0.1
IP1.2, IP0.2
IP1.3, IP0.3
IP1.4, IP0.4
IP1.5, IP0.5
0
1
0
1
Level0 (lowest)
Level1
Level2
Level3 (highest)
Table 11-4: Groups of priority
Group
External interrupt 0
Serial channel 1 interrupt
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
Serial channel 0 interrupt
Timer 2 interrupt
-
PWM interrupt
SPI interrupt
ADC interrupt
KBI interrupt
LVI interrupt
IIC interrupt
Table 11-5: Polling sequence
Interrupt source
External interrupt 0
Serial channel 0 interrupt
Polling sequence
Serial channel 1 interrupt
PWM interrupt
Timer 0 interrupt
SPI interrupt
External interrupt 1
ADC interrupt
Timer 1 interrupt
KBI interrupt
Sequence
LVI interrupt
Timer 2 interrupt
IIC interrupt
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
54
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
12. Power Management Unit
Power management unit serves two power management modes, IDLE and STOP, for the users to do power saving
function.
Mnemonic: PCON
7
6
SMOD MDUF
5
-
4
-
3
-
2
-
1
STOP
Address: 87h
0
Reset
IDLE
40h
STOP: Stop mode control bit. Setting this bit turning on the Stop Mode.
Stop bit is always read as 0
IDLE: Idle mode control bit. Setting this bit turning on the Idle Mode.
Idle bit is always read as 0
12.1. Idle mode
Setting the IDLE bit of PCON register invokes the IDLE mode. The IDLE mode leaves internal clocks and peripherals
running. Power consumption drops because the CPU is not active. The CPU can exit the IDLE state with any interrupts or
a reset.
12.2. Stop mode
Setting the STOP bit of PCON register invokes the STOP mode. All internal clocking in this mode is turn off. The CPU will
exit this state only if interrupts asserted from external INT0/1, KBI and LVI, or hardware reset by WDT and LVR.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
55
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
13. Pulse Width Modulation (PWM)
SM59R16A3 provides four-channel PWM outputs.
The interrupt vector is 43h.
Mnemonic
Description
Direct
Bit 7
Bit 6
Bit 5
Bit 4
P4SPI
P4UR
1
Bit 3
Bit 2
Bit 1
Bit 0
RESET
AUX
PWMC
PWMD0H
PWMD0L
PWMD1H
PWMD1L
PWMD2H
PWMD2L
PWMD3H
PWMD3L
PWMMDH
PWMMDL
Auxiliary register
PWM Control
register
PWM 0 Data
register high byte
PWM 0 Data
register low byte
PWM 1 Data
register high byte
PWM 1 Data
register low byte
PWM 2 Data
register high byte
PWM 2 Data
register low byte
PWM 3 Data
register high byte
PWM 3 Data
register low byte
PWM Max Data
register high byte
PWM Max Data
register low byte
91h
BRGS
B5h
-
PWMCS[2:0]
BCh
PWMP0
-
-
BDh
P2PW
DPS
M
PWM3E PWM2E PWM1E PWM0E
N
N
N
N
P4IIC
-
-
P0KBI
-
PWMD0[9:8]
PWMD0[7:0]
BEh
PWMP1
-
-
BFh
-
-
PWMP2
-
-
B2h
-
-
-
PWMD1[9:8]
PWMP3
-
-
B4h
-
-
-
PWMD2[9:8]
-
-
-
CFh
-
-
-
PWMD3[9:8]
4
P4UR1
3
P4IIC
2
P0KBI
1
P2PWM
-
PWMMD[9:8]
5
4
-
00H
00H
FFH
Address: 91h
0
Reset
DPS
00H
P2PWM : P2PWM = 0 – PWM function on P4.
P2PWM = 1 – PWM function on P2.
Mnemonic: PWMC
7
6
PWMCS[2:0]
00H
00H
PWMMD[7:0]
Mnemonic: AUX
7
6
5
BRGS
P4SPI
00H
00H
PWMD3[7:0]
CEh
00H
00H
PWMD2[7:0]
B3h
00H
00H
PWMD1[7:0]
B1h
00H
Address: B5h
3
2
1
0
Reset
PWM3EN PWM2EN PWM1EN PWM0EN 00H
PWMCS[2:0]: PWM clock select.
PWMCS [2:0]
Mode
000
Fosc
001
Fosc/2
010
Fosc/4
011
Fosc/6
100
Fosc/8
101
Fosc/12
110
Timer 0 overflow
111
Timer 0 external input (P3.4/T0)
PWM3EN: PWM channel 3 enable control bit.
PWM3EN = 1 – PWM channel 3 enable.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
56
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
PWM3EN = 0 – PWM channel 3 disable.
PWM2EN: PWM channel 2 enable control bit.
PWM2EN = 1 – PWM channel 2 enable.
PWM2EN = 0 – PWM channel 2 disable.
PWM1EN: PWM channel 1 enable control bit.
PWM1EN = 1 – PWM channel 1 enable.
PWM1EN = 0 – PWM channel 1 disable.
PWM0EN: PWM 0 enable control bit.
PWM0EN = 1 – PWM channel 0 enable.
PWM0EN = 0 – PWM channel 0 disable.
Mnemonic: PWMD0H
7
6
5
PWMP0
Mnemonic: PWMD0L
7
6
5
4
-
3
-
4
3
PWMD0[7:0]
2
2
Address: BCh
1
0
Reset
PWMD0[9:8]
00H
1
Address: BDh
0
Reset
00h
PWMP0: PWM channel 0 idle polarity select.
“0” – PWM channel 0 will idle low.
“1” – PWM channel 0 will idle high.
PWMD0[9:0]: PWM channel 0 data register.
Mnemonic: PWMD1H
7
6
5
PWMP1
Mnemonic: PWMD1L
7
6
5
4
-
3
-
4
3
PWMD1[7:0]
2
2
Address: BEh
1
0
Reset
PWMD1[9:8]
00H
1
Address: BFh
0
Reset
00H
PWMP1: PWM channel 1 idle polarity select.
“0” – PWM channel 1 will idle low.
“1” – PWM channel 1 will idle high.
PWMD1[9:0]: PWM channel 1 data register.
Mnemonic: PWMD2H
7
6
5
PWMP2
Mnemonic: PWMD2L
7
6
5
4
-
3
-
4
3
PWMD2[7:0]
2
2
Address: B1h
1
0
Reset
PWMD2[9:8]
00H
1
Address: B2h
0
Reset
00H
PWMP2: PWM channel 2 idle polarity select.
“0” – PWM channel 2 will idle low.
“1” – PWM channel 2 will idle high.
PWMD2[9:0]: PWM channel 2 data register.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
57
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
Mnemonic: PWMD3H
7
6
5
PWMP3
Mnemonic: PWMD3L
7
6
5
4
-
3
-
4
3
PWMD3[7:0]
2
2
Address: B3h
1
0
Reset
PWMD3[9:8]
00H
1
Address: B4h
0
Reset
00H
PWMP3: PWM channel 3 idle polarity select.
“0” – PWM channel 3 will idle low.
“1” – PWM channel 3 will idle high.
PWMD3[9:0]: PWM channel 3 data register.
Mnemonic: PWMMDH
7
6
5
Mnemonic: PWMMDL
7
6
5
4
-
3
-
4
3
PWMMD[7:0]
2
2
Address: CEh
1
0
Reset
PWMMD[9:8]
00H
1
Address: CFh
0
Reset
FFH
PWMMD[9:0]: PWM Max Data register.
PWM count from 0000h to PWMMD[9:0]. When PWM count data equal PWMMD[9:0]
is overflow.
PWMPx = 0 & PWMDx = 00h
PWMPx = 0 & PWMDx ≠ 00h
PWMPx = 1 & PWMDx = 00h
PWMPx = 1 & PWMDx ≠ 00h
PWMMD + 1
PWM clock
PWMDx
Leader pulse =
PWM clock
PWM period =
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
58
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
14. IIC function
The IIC module uses the SCL (clock) and the SDA (data) line to communicate with external IIC interface. Its speed can be
selected to 400Kbps (maximum) by software setting the IICBR [2:0] control bit. The IIC module provided 2 interrupts
(RXIF, TXIF). It will generate START, repeated START and STOP signals automatically in master mode and can detects
START, repeated START and STOP signals in slave mode. The maximum communication length and the number of
devices that can be connected are limited by a maximum bus capacitance of 400pF.
The interrupt vector is 6Bh.
Mnemonic
AUX
IICCTL
IICS
IICA1
IICA2
IICRWD
IICS2
Description
Auxiliary register
IIC control
register
IIC status register
IIC Address 1
register
IIC Address 2
register
IIC Read/Write
register
IIC status2
register
Direct
Bit 7
91h
BRGS
F9h
IICEN
F8h
MStart
Bit 6
Bit 5
IIC function
-
RXIF
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESET
P4SPI
P4UR
1
P4IIC
P0KBI
P2PW
M
DPS
00H
MSS
MAS
RStart
TXIF
RDR
TDR
FAh
IICA1[7:1]
FBh
IICA2[7:1]
FCh
FDh
Mnemonic: AUX
7
6
5
BRGS
P4SPI
RXAK
IICBR[2:0]
04H
TXAK
00H
RW
MATCH1
or RW1
MATCH2
or RW2
IICRWD[7:0]
-
-
4
P4UR1
-
-
AB_EN
3
P4IIC
2
P0KBI
1
P2PWM
3
RStart
2
A0H
60H
00H
BF_E
N
AB_F
BF
00H
Address: 91h
0
Reset
DPS
00H
P4IIC: P4IIC = 0 – IIC function on P1.
P4IIC = 1 – IIC function on P4.
Mnemonic: IICCTL
7
6
5
IICEN
MSS
4
MAS
1
IICBR[2:0]
Address: F9h
0
Reset
04h
IICEN: Enable IIC module
IICEN = 1 is Enable
IICEN = 0 is Disable.
MSS: Master or slave mode select.
MSS = 1 is master mode.
MSS = 0 is slave mode.
*The software must set this bit before setting others register.
MAS: Master address select (master mode only)
MAS = 0 is to use IICA1.
MAS = 1 is to use IICA2.
RStart: Re-start control bit (master mode only)
When this bit is set, the module will generate a start condition to the SDA and SCL lines (after
current ACK) and send out the calling address which is stored in the IICA1 or IICA2( selected by
MAS control bit).When module is finished to send out address, this bit will be cleared by
hardware.
IICBR[2:0]: Baud rate selection (master mode only), where Fosc is the external crystal or oscillator
frequency. The default is Fosc/512 for users’ convenience.
IICBR[2:0]
Baud rate
000
Fosc/32
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
59
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
001
010
011
100
101
110
111
Mnemonic: IICS
7
6
MStart
RxIF
Fosc/64
Fosc/128
Fosc/256
Fosc/512
Fosc/1024
Fosc/2048
Fosc/4096
5
TxIF
4
RDR
3
TDR
2
RxAK
1
TxAK
Address: F8h
0
Reset
RW
00h
MStart: Master Start control bit. (Master mode only)
If set the MStart bit, the module will generate a start condition to the SDA and SCL lines
and send out the calling address which is stored in the IICA1 or IICA2 (selected by MAS
control bit). When software cleared this bit, the module will generate a stop condition to
the SDA and SCL.
RxIF: The data Receive Interrupt Flag (RXIF) is set after the IICRWD (IIC Read Write Data
Buffer) is loaded with a newly receive data.
TxIF: The data Transmit Interrupt Flag (TXIF) is set when the data of the IICRWD (IIC Read
Write Data Buffer) is downloaded to the shift register.
RDR: The MCU must clear this bit after it gets the data from IICRWD. The IIC module is able to
write new data into IICRWD only when this bit is cleared.
TDR: When MCU finish writing data to IICRWD, the MCU needs to set this bit to ‘1’ to inform
the IIC module to send the data in the IICRWD. After IIC module finishes sending the
data from IICRWD, this bit will be cleared automatically.
RxAK: The Acknowledge Status indicate bit. When clear, it means an acknowledge signal has
been received after the complete 8 bits data transmit on the bus.
TxAK: The Acknowledge status transmit bit. When received complete 8 bits data, this bit will set
(NoAck) or clear (Ack) and transmit to master to indicate the receive status. Actually, it is
sent as the 9th bit in one byte transmission as show in Fig. 14-1.
RW: The slave mode read (received) or wrote (transmit) on the IIC bus. When this bit is clear,
the slave module received data on the IIC bus (SDA).(Slave mode only)
Fig. 14-1: Acknowledgement bit in the 9th bit of a byte transmission
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
60
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
Mnemonic: IICA1
7
6
5
4
3
2
1
IICA1[7:1]
R/W
Address: FAH
0
Reset
Match1 or
A0H
RW1
R or R/W
Slave mode:
IICA1[7:1]: IIC Address registers
This is the first 7-bit address for this slave module. It will be checked when an address (from
master) is received
Match1: When IICA1 matches with the received address from the master side, this bit will set to 1 by
hardware. When IIC bus gets or send first data, this bit will clear automatically.
Master mode:
IICA1[7:1]: IIC Address registers
This 7-bit address indicate the slave with which it want to communicate.
RW1: This bit will be sent out as RW of the slave side if the module has set the MStart or RStart bit. It
appears at the 8th bit after the IIC address as shown in Fig. 14-2. It is used to tell the salve the
direction of the following communication. If it is 1, the module is in master receive mode. If 0, the
module is in master transmit mode.
Fig. 14-2: RW bit in the 8th bit after IIC address
Mnemonic: IICA2
7
6
5
Address: FBh
4
IICA2[7:1]
R/W
3
2
1
0
Match2 or RW2
R or R/W
Reset
60h
Slave mode:
IICA2[7:1]: IIC Address registers
This is the second 7-bit address for this slave module.
It will be checked when an address (from master) is received
Match2: When IICA2 matches with the received address from the master side, this bit will set to 1 by
hardware. When IIC bus gets or send first data, this bit will clear automatically.
Master mode:
IICA2[7:1]: IIC Address registers
This 7-bit address indicate the slave with which it want to communicate.
RW2: This bit will be sent out as RW of the slave side if the module has set the MStart or RStart bit. It is
used to tell the salve the direction of the following communication. If it is 1, the module is in
master receive mode. If 0, the module is in master transmit mode.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
61
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
Mnemonic: IICRWD
7
6
5
4
3
IICRWD[7:0]
2
1
Address: FCh
0
Reset
00h
IICRWD[7:0]: IIC read write data buffer.
In receiving (read) mode, the received byte is stored here.
In transmitting mode, the byte to be shifted out through SDA stays here.
Mnemonic: IICS2
7
6
-
5
-
4
-
3
AB_EN
2
BF_EN
1
AB_F
Address: FDH
0
Reset
BF
00H
AB_EN: Arbitration lost enable bit. (Master mode only)
If set AB_EN bit, the hardware will check arbitration lost. Once arbitration lost occurred,
hardware will return to IDLE state. If this bit is cleared, hardware will not care arbitration
lost condition. Set this bit when multi-master and slave connection. Clear this bit when
single master to single slave.
BF_EN: Bus busy enable bit. (Master mode only)
If set BF_EN bit, hardware will not generate a start condition to bus until BF=0. Clear
this bit will always generate a start condition to bus when MStart is set. Set this bit when
multi-master and slave connection. Clear this bit when single master to single slave.
AB_F: Arbitration lost bit. (Master mode only)
In multi-master condition, when send out data bit “1” but return back “0”, bus arbitration
lost occurred and this bit will be set. Software need to clear this bit and check until BF=0
to resend data again.
BF: Bus busy bit. (Master mode only)
If detect scl=0 or sda=0 or bus start, this bit will be set. If detect stop and a period
passed(about 4.7us), this bit will be cleared. This bit can be cleared by software to
return ready state.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
62
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
15. SPI function
Serial Peripheral Interface (SPI) is a synchronous protocol that allows a master device to initiate communication with
slave devices.
The interrupt vector is 4Bh.
There are 4 signals used in SPI, they are
SPI_MOSI: data output in the master mode, data input in the slave mode,
SPI_MISO: data input in the master mode, data output in the slave mode,
SPI_SCK: clock output form the master, the above data are synchronous to this signal
SPI_SS: input in the slave mode.
This slave device detects this signal to judge if it is selected by the master.
In the master mode, it can select the desired slave device by any IO with value = 0. Fig. 15-1 is an example showing the
relation of the 4 signals between master and slaves.
Master
Slave 2
Slave 1
MOSI
MISO
CLK
IO
IO
MOSI
MISO
CLK
MOSI
MISO
CLK
SS
SS
Fig. 15-1: SPI signals between master and slave devices
There is only one channel SPI interface. The SPI SFRs are shown as below:
Mnemonic
AUX
SPIC1
SPIC2
SPIS
SPITXD
SPIRXD
Description
Auxiliary register
SPI control register
1
SPI control register
2
SPI status register
SPI transmit data
buffer
SPI receive data
buffer
Direct
Bit 7
Bit 6
Bit 5
SPI function
91h
BRGS
F1h
SPIEN SPIMSS
F2h
SPIFD
F5h
-
-
P4SPI
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESET
P4UR
1
P4IIC
P0KBI
P2PW
M
DPS
00H
SPISS
SPICKP SPICKE
P
TBC[2:0]
-
SPIBR[2:0]
08H
RBC[2:0]
00H
SPIMLS SPIOV SPITXIF SPITDR SPIRXIF SPIRDR SPIRS
40H
F3h
SPITXD[7:0]
00H
F4h
SPIRXD[7:0]
00H
Mnemonic: AUX
7
6
5
BRGS
P4SPI
4
P4UR1
3
P4IIC
2
P0KBI
1
P2PWM
Address: 91h
0
Reset
DPS
00H
P4SPI: P4SPI = 0 – SPI function on P1.
P4SPI = 1 – SPI function on P4.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
63
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
Mnemonic: SPIC1
7
6
5
SPIEN SPIMSS SPISSP
4
SPICKP
3
SPICKE
2
Address: F1h
1
0
Reset
SPIBR[2:0]
08h
SPIEN: Enable SPI module. “1” is Enable. “0” is Disable.
SPIMSS: Master or Slave mode Select
“1” is Master mode.
“0” is Slave mode.
SPISSP: Slave Select (SS) active polarity (slave mode used only)
“1” - high active.
“0” - low active.
SPICKP: Clock idle polarity (master mode used only)
“1” – SCK high during idle. Ex :
“0” - SCK low during idle. Ex :
SPICKE: Clock sample edge select.
“1” – data latch in rising edge
“0” – data latch in falling edge.
* To ensure the data latch stability, SM59R16A3 generate the output data as given in the following
example, the other side can latch the stable data no matter in rising or falling edge.
sufficient set-up time
sufficient hold time
SPIBR[2:0]: SPI baud rate select (master mode used only), here Fosc is the external crystal or oscillator
frequency :
SPIBR[2:0] Baud rate
0:0:0
Fosc/4
0:0:1
Fosc/8
0:1:0
Fosc/16
0:1:1
Fosc/32
1:0:0
Fosc/64
1:0:1
Fosc/128
1:1:0
Fosc/256
1:1:1
Fosc/512
Mnemonic: SPIC2
7
6
5
SPIFD
TBC[2:0]
4
3
-
2
1
RBC[2:0]
Address: F2h
0
Reset
00h
SPIFD: Full-duplex mode enable.
“1” : enable full-duplex mode.
“0” : disable full-duplex mode.
When it is set, the TBC[2:0] and RBC[2:0] will be reset and keep to zero, i.e., only 8-bit
communication is allowed in the full-duplex mode. When the master device transmits data to the
slave device via the MOSI line, the slave device responds sends data back to the master device
via the MISO line. This implies that full-duplex transmission with both out-data and in-data are
synchronized with the same clock SCK as shown below.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
64
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
Input Shift register
SPIRXD
Output Shift register
SPITXD
Clock Generator
MISO
MISO
MOSI
MOSI
SCK
SCK
Output Shift register
SPITXD
Input Shift register
SPIRXD
SyncMos Slave
SyncMos Master
TBC[2:0]: SPI transmitter bit counter, here 1-8 bits are allowed except for the full-duplex mode
TBC[2:0]
Bit counter
0:0:0
8 bits output
0:0:1
1 bit output
0:1:0
2 bits output
0:1:1
3 bits output
1:0:0
4 bits output
1:0:1
5 bits output
1:1:0
6 bits output
1:1:1
7 bits output
RBC[2:0]: SPI receiver bit counter, here 1-8 bits are allowed except for the full-duplex mode
RBC[2:0]
Bit counter
0:0:0
8 bits input
0:0:1
1 bit input
0:1:0
2 bits input
0:1:1
3 bits input
1:0:0
4 bits input
1:0:1
5 bits input
1:1:0
6 bits input
1:1:1
7 bits input
Mnemonic: SPIS
7
6
5
SPIMLS SPIOV
4
SPITXIF
3
SPITDR
2
SPIRXIF
1
SPIRDR
Address: F5h
0
Reset
SPIRS
40h
SPIMLS: MSB or LSB output /input first
“1” : MSB output/input first
“0” : LSB output/input first
SPIOV: Overflow flag.
When SPIRDR is set (one byte in SPIRXD but has not been taken away) and the next data also
enters (there is no blocking function), this flag will be set to inform that the received data in
SPIRXD is damaged by this overflow. It is clear by hardware when SPIRDR is cleared.
SPITXIF: Transmit Interrupt Flag.
This bit is set when the data of the SPITXD register is downloaded to the shift register.
SPITDR: Transmit Data Ready.
When MCU finish writing data to SPITXD register, the MCU needs to set this bit to ‘1’ to inform the
SPI module to send the data. After SPI module finishes sending the data from SPITXD or SPITXD
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
65
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
is downloaded to shift register, this bit will be cleared automatically.
SPIRXIF: Receive Interrupt Flag.
This bit is set after the SPIRXD is loaded with a newly receive data.
SPIRDR: Receive Data Ready.
When a byte is received, SPIRDR is set as a flag to inform MCU. The MCU must clear this bit
after it gets the data from SPIRXD register. If the SPI module on the transmit side writes new
data into the SPIRXD before this bit is cleared, then the data will be overwritten.
SPIRS: Receive Start.
This bit set to “1” to inform the SPI module to receive the data into SPIRXD register.
Mnemonic: SPITXD
7
6
5
4
3
SPITXD[7:0]
2
1
0
Address: F3h
Reset
00h
SPITXD[7:0]: Transmit data buffer.
Mnemonic: SPIRXD
7
6
5
4
3
SPIRXD[7:0]
2
1
Address: F4h
0
Reset
00h
SPIRXD[7:0]: Receive data buffer.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
66
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
16. KBI – Keyboard Interface
Keyboard interface (KBI) can be connected to an 8 x n matrix keyboard or any similar devices. It has 8 inputs with
programmable interrupt capability on either high or low level. These 8 inputs are through P2 or P0 and can be the external
interrupts to leave from the idle and stop modes. The 8 inputs are independent from each other but share the same
interrupt vector 5Bh.
KBI0
KBI1
KBI2
KBI3
KBI4
KBI5
KBI6
KBI7
Input
circuitry
Input
circuitry
Input
circuitry
Input
circuitry
Input
circuitry
Input
circuitry
Input
circuitry
Input
circuitry
OR
KBIIF: KBI interrupt flag
IEKBI: KBI interrupt enable
Figure 16.1 keyboard interface block diagram
Figure 16.2 keyboard input circuitry
Mnemonic
AUX
KBLS
KBE
KBF
KBD
Description
Auxiliary register
KBI level
selection
KBI input enable
KBI flag
KBI De-bounce
control register
Direct
Bit 7
Bit 6
Bit 5
KBI function
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESET
91h
BRGS
-
P4SPI
P4UR
1
P4IIC
P0KBI
P2PW
M
DPS
00H
93h
KBLS7
KBLS6
KBLS5
KBLS4
KBLS3
KBLS2
KBLS1
KBLS0
00H
94h
95h
KBE7
KBF7
KBE6
KBF6
KBE5
KBF5
KBE4
KBF4
KBE3
KBF3
KBE2
KBF2
KBE1
KBF1
KBE0
KBF0
00H
00H
96h
KBDEN
-
-
-
-
-
KBD1
KBD0
00H
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
67
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
Mnemonic: AUX
7
6
5
BRGS
P4SPI
4
P4UR1
3
P4IIC
2
P0KBI
1
P2PWM
Address: 91h
0
Reset
DPS
00H
P0KBI: P0KBI = 0 – KBI function on P2.
P0KBI = 1 – KBI function on P0.
Mnemonic: KBLS
7
6
KBLS.7
KBLS.6
5
KBLS.5
4
KBLS.4
3
KBLS.3
2
KBLS.2
1
KBLS.1
Address: 93h
0
Reset
KBLS.0
00h
2
KBE.2
1
KBE.1
Address: 94h
0
Reset
KBE.0
00h
KBLS.7: Keyboard Line 7 level selection bit
0 : enable a low level detection on KBI7.
1 : enable a high level detection on KBI7.
KBLS.6: Keyboard Line 6 level selection bit
0 : enable a low level detection on KBI6.
1 : enable a high level detection on KBI6.
KBLS.5: Keyboard Line 5 level selection bit
0 : enable a low level detection on KBI5.
1 : enable a high level detection on KBI5.
KBLS.4: Keyboard Line 4 level selection bit
0 : enable a low level detection on KBI4.
1 : enable a high level detection on KBI4.
KBLS.3: Keyboard Line 3 level selection bit
0 : enable a low level detection on KBI3.
1 : enable a high level detection on KBI3.
KBLS.2: Keyboard Line 2 level selection bit
0 : enable a low level detection on KBI2.
1 : enable a high level detection on KBI2.
KBLS.1: Keyboard Line 1 level selection bit
0 : enable a low level detection on KBI1.
1 : enable a high level detection on KBI1.
KBLS.0: Keyboard Line 0 level selection bit
0 : enable a low level detection on KBI0.
1 : enable a high level detection on KBI0.
Mnemonic: KBE
7
6
KBE.7
KBE.6
5
KBE.5
4
KBE.4
3
KBE.3
KBE.7: Keyboard Line 7 enable bit
0 : enable standard I/O pin.
1 : enable KBF.7 bit in KBF register to generate an interrupt request.
KBE.6: Keyboard Line 6 enable bit
0 : enable standard I/O pin.
1 : enable KBF.6 bit in KBF register to generate an interrupt request.
KBE.5: Keyboard Line 5 enable bit
0 : enable standard I/O pin.
1 : enable KBF.5 bit in KBF register to generate an interrupt request.
KBE.4: Keyboard Line 4 enable bit
0 : enable standard I/O pin.
1 : enable KBF.4 bit in KBF register to generate an interrupt request.
KBE.3: Keyboard Line 3 enable bit
0 : enable standard I/O pin.
1 : enable KBF.3 bit in KBF register to generate an interrupt request.
KBE.2: Keyboard Line 2 enable bit
0 : enable standard I/O pin.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
68
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
1 : enable KBF.2 bit in KBF register to generate an interrupt request.
KBE.1: Keyboard Line 1 enable bit
0 : enable standard I/O pin.
1 : enable KBF.1 bit in KBF register to generate an interrupt request.
KBE.0: Keyboard Line 0 enable bit
0 : enable standard I/O pin.
1 : enable KBF.0 bit in KBF register to generate an interrupt request.
Mnemonic: KBF
7
6
KBF.7
KBF.6
5
KBF.5
4
KBF.4
3
KBF.3
2
KBF.2
1
KBF.1
Address: 95h
0
Reset
KBF.0
00h
KBF.7: Keyboard Line 7 flag
This is set by hardware when KBI7 detects a programmed level.
It generates a Keyboard interrupt request if KBE.7 is also set. It must be cleared by software.
KBF.6: Keyboard Line 6 flag
This is set by hardware when KBI6 detects a programmed level.
It generates a Keyboard interrupt request if KBE.6 is also set. It must be cleared by software.
KBF.5: Keyboard Line 5 flag
This is set by hardware when KBI5 detects a programmed level.
It generates a Keyboard interrupt request if KBE.5 is also set. It must be cleared by software.
KBF.4: Keyboard Line 4 flag
This is set by hardware when KBI4 detects a programmed level.
It generates a Keyboard interrupt request if KBE.4 is also set. It must be cleared by software.
KBF.3: Keyboard Line 3 flag
This is set by hardware when KBI3 detects a programmed level.
It generates a Keyboard interrupt request if KBE.3 is also set. It must be cleared by software.
KBF.2: Keyboard Line 2 flag
This is set by hardware when KBI2 detects a programmed level.
It generates a Keyboard interrupt request if KBE.2 is also set. It must be cleared by software.
KBF.1: Keyboard Line 1 flag
This is set by hardware when KBI1 detects a programmed level.
It generates a Keyboard interrupt request if KBE.1 is also set. It must be cleared by software.
KBF.0: Keyboard Line 0 flag
This is set by hardware when KBI0 detects a programmed level.
It generates a Keyboard interrupt request if KBE.0 is also set. It must be cleared by software.
Mnemonic: KBD
7
6
KBDEN
-
5
-
4
-
3
-
2
-
1
KBD.1
Address: 96H
0
Reset
KBD.0
00H
KBDEN: Enable KBI de-bounce function. The default KBI function is enabled.
KBDEN = 0, enable KBI de-bounce function. The de-bounce time is selected by KBD [1:0].
KBDEN = 1, disable KBI de-bounce function. The KBI input pin without de-bounce mechanism.
KBD[1:0]: Select KBI de-bounce time. If KBDEN = “0”, the default de-bounce time is 320 ms.
KBD[1:0] = 00, the de-bounce time is 320 ms.
KBD[1:0] = 01, the de-bounce time is 160 ms.
KBD[1:0] = 10, the de-bounce time is 80 ms.
KBD[1:0] = 11, the de-bounce time is 40 ms.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
69
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
17. LVI – Low Voltage Interrupt
The interrupt vector 63h.
Mnemonic: LVC
7
6
5
LVI_EN
LVRXE
4
-
3
-
2
-
1
-
Address: E6h
0
Reset
20H
LVI_EN: Low voltage interrupt function enable bit.
LVI_EN = 0 : disable low voltage detect function.
LVI_EN = 1 : enable low voltage detect function.
LVRXE: External low voltage reset function enable bit.
LVRXE = 0 : disable external low voltage reset function.
LVRXE = 1 : enable external low voltage reset function.
Low Voltage Detect Level
SM59R16A3C
SM59R16A3L
LVI
3.5V
2.3V
LVRX
3.1V
2.1V
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
70
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
18. 10-bit Analog-to-Digital Converter (ADC)
The SM59R16A3 provides eight channels 10-bit ADC. The Digital output DATA [9:0] were put into ADCD [9:0]. The ADC
interrupt vector is 53H.
The ADC SFR show as below:
Mnemonic
ADCC1
ADCC2
ADCDH
ADCDL
ADCCS
Description
Direct
ADC Control
register 1
ADC Control
register 2
ADC data high
byte
ADC data low
byte
ADC clock select
ABh
Bit 7
Bit 6
Bit 5
ADC
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESET
ADC7EN ADC6EN ADC5EN ADC4EN ADC3EN ADC2EN ADC1EN ADC0EN
ACh
Start
ADJUST
-
-
-
ADCCH[2:0]
00H
00H
ADh
ADCDH [7:0]
00H
AEh
ADCDL [7:0]
00H
AFh
-
-
-
ADCCS[4:0]
Mnemonic: ADCC1
Address: ABh
7
6
5
4
3
2
1
0
Reset
ADC7EN ADC6EN ADC5EN ADC4EN ADC3EN ADC2EN ADC1EN ADC0EN
00H
ADC7EN: ADC channels 7 enable.
ADC7EN = 1 – Enable ADC channel 7
ADC6EN: ADC channels 6 enable.
ADC6EN = 1 – Enable ADC channel 6
ADC5EN: ADC channels 5 enable.
ADC5EN = 1 – Enable ADC channel 5
ADC4EN: ADC channels 4 enable.
ADC4EN = 1 – Enable ADC channel 4
ADC3EN: ADC channels 3 enable.
ADC3EN = 1 – Enable ADC channel 3
ADC2EN: ADC channels 2 enable.
ADC2EN = 1 – Enable ADC channel 2
ADC1EN: ADC channels 1 enable.
ADC1EN = 1 – Enable ADC channel 1
ADC0EN: ADC channels 0 enable.
ADC0EN = 1 – Enable ADC channel 0
Mnemonic: ADCC2
7
6
5
4
3
Start
ADJUST
-
-
-
2
Address: ACh
Rese
1
0
t
ADCCH[2:0]
00H
Start: When this bit is set, the ADC will be start conversion.
ADJUST: Adjust the format of ADC conversion DATA.
ADJUST = 0: (default value)
ADC data high byte ADCD [9:2] = ADCDH [7:0].
ADC data low byte ADCD [1:0] = ADCDL [1:0].
ADJUST = 1:
ADC data high byte ADCD [9:8] = ADCDH [1:0].
ADC data low byte ADCD [7:0] = ADCDL [7:0].
ADCCH[2:0]: ADC channel select.
ADCCH [2:0]
Channel
000
0
001
1
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
71
Ver.E SM59R16A3 02/2012
00H
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
010
011
100
101
110
111
2
3
4
5
6
7
ADJUST = 0:
Mnemonic: ADCDH
Address: ADh
7
6
5
4
3
2
1
0
Reset
ADCD[9] ADCD[8] ADCD[7] ADCD[6] ADCD[5] ADCD[4] ADCD[3] ADCD[2]
00H
Mnemonic: ADCDL
7
6
-
5
-
ADJUST = 1:
Mnemonic: ADCDH
7
6
-
4
-
5
-
4
-
3
-
2
-
3
-
1
ADCD[1]
2
-
Address: AEh
0
Reset
ADCD[0]
00H
Address: ADh
1
0
Reset
ADCD[9] ADCD[8]
00H
Mnemonic: ADCDL
Address: AEh
7
6
5
4
3
2
1
0
Reset
ADCD[7] ADCD[6] ADCD[5] ADCD[4] ADCD[3] ADCD[2] ADCD[1] ADCD[0]
00H
ADCD[9:0]: ADC data register.
Mnemonic: ADCCS
7
6
-
5
-
Address: AFh
4
3
2
1
0
Reset
ADCCS[4] ADCCS[3] ADCCS[2] ADCCS[1] ADCCS[0]
00H
ADCCS[4:0]: ADC clock select.
*The ADC clock maximum 12.5MHz.
*The ADC Conversion rate maximum 500KHz.
ADCCS[4:0]
ADC Clock(Hz)
Clocks for ADC Conversion
00000
Fclk/2
46
00001
Fclk/4
92
00010
Fclk/6
138
00011
Fclk/8
184
00100
Fclk/10
230
00101
Fclk/12
276
00110
Fclk/14
322
00111
Fclk/16
368
01000
Fclk/18
414
01001
Fclk/20
460
01010
Fclk/22
506
01011
Fclk/24
552
01100
Fclk/26
598
01101
Fclk/28
644
01110
Fclk/30
690
01111
Fclk/32
736
10000
Fclk/34
782
10001
Fclk/36
828
10010
Fclk/38
874
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
72
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Fclk/40
Fclk/42
Fclk/44
Fclk/46
Fclk/48
Fclk/50
Fclk/52
Fclk/54
Fclk/56
Fclk/58
Fclk/60
Fclk/62
Fclk/64
920
966
1012
1058
1104
1150
1196
1242
1288
1334
1380
1426
1472
Fclk
2 × ( ADCCS + 1)
ADC_Clock
ADC _ Conversion _ Rate =
23
ADC _ Clock =
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
73
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
19. In-System Programming (Internal ISP)
The SM59R16A3 can generate flash control signal by internal hardware circuit. Users utilize flash control register, flash
address register and flash data register to perform the ISP function without removing the SM59R16A3 from the system.
The SM59R16A3 provides internal flash control signals which can do flash program/chip erase/page erase/protect
functions. User need to design and use any kind of interface which SM59R16A3 can input data. User then utilize ISP
service program to perform the flash program/chip erase/page erase/protect functions.
19.1. ISP service program
The ISP service program is a user developed firmware program which resides in the ISP service program space.
After user developed the ISP service program, user then determine the size of the ISP service program. User need
to program the ISP service program in the SM59R16A3 for the ISP purpose.
The ISP service programs were developed by user so that it should includes any features which relates to the flash
memory programming function as well as communication protocol between SM59R16A3 and host device which
output data to the SM59R16A3. For example, if user utilize UART interface to receive/transmit data between
SM59R16A3 and host device, the ISP service program should include baud rate, checksum or parity check or any
error-checking mechanism to avoid data transmission error.
The ISP service program can be initiated under SM59R16A3 active or idle mode. It can not be initiated under power
down mode.
19.2. Lock Bit (N)
The Lock Bit N has two functions: one is for service program size configuration and the other is to lock the ISP
service program space from flash erase function.
The ISP service program space address range $F000 to $FFFF. It can be divided as blocks of N*256 byte. (N=0 to
16). When N=0 means no ISP function, all of 64K byte flash memory can be used as program memory. When N=1
means ISP service program occupies 256 byte while the rest of 63.75K byte flash memory can be used as program
memory. The maximum ISP service program allowed is 4K byte when N=16. Under such configuration, the usable
program memory space is 60K byte.
After N determined, SM59R16A3 will reserve the ISP service program space downward from the top of the program
address $FFFF. The start address of the ISP service program located at $Fx00 while x is an even number,
depending on the lock bit N. As shown in Table 19-1.
The lock bit N function is different from the flash protect function. The flash erase function can erase all of the flash
memory except for the locked ISP service program space. If the flash not has been protected, the content of ISP
service program still can be read. If the flash has been protected, the overall content of flash program memory space
including ISP service program space can not be read.
Table 19.1 ISP code area.
N
ISP service program address
0
No ISP service program
1
256 bytes ($FF00h ~ $FFFFh)
2
512 bytes ($FE00h ~ $FFFFh)
3
768 bytes ($FD00h ~ $FFFFh)
4
1.0 K bytes ($FC00h ~ $FFFFh)
5
1.25 K bytes ($FB00h ~ $FFFFh)
6
1.5 K bytes ($FA00h ~ $FFFFh)
7
1.75 K bytes ($F900h ~ $FFFFh)
8
2.0 K bytes ($F800h ~ $FFFFh)
9
2.25 K bytes ($F700h ~ $FFFFh)
10
2.5 K bytes ($F600h ~ $FFFFh)
11
2.75 K bytes ($F500h ~ $FFFFh)
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
74
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
12
13
14
15
16
3.0 K bytes ($F400h ~ $FFFFh)
3.25 K bytes ($F300h ~ $FFFFh)
3.5 K bytes ($F200h ~ $FFFFh)
3.75 K bytes ($F100h ~ $FFFFh)
4.0 K bytes ($F000h ~ $FFFFh)
ISP service program configurable in N*256 byte (N= 0 ~ 16)
19.3. Program the ISP Service Program
After Lock Bit N is set and ISP service program been programmed, the ISP service program memory will be
protected (locked) automatically. The lock bit N has its own program/erase timing. It is different from the flash
memory program/erase timing so the locked ISP service program can not be erased by flash erase function. If user
needs to erase the locked ISP service program, he can do it by writer only. User can not change ISP service program
when SM59R16A3 was in system.
19.4. Initiate ISP Service Program
To initiate the ISP service program is to load the program counter (PC) with start address of ISP service program and
execute it. There are four ways to do so:
(1) Blank reset. Hardware reset with first flash address blank ($0000=#FFH) will load the PC with start
address of ISP service program. The hardware reset includes Internal (power on reset) and external
pad reset.
(2) Execute jump instruction can load the start address of the ISP service program to PC.
(3) Enters ISP service program by hardware setting. User can force SM59R16A3 enter ISP service
program by setting P2.6, P2.7 “active low” or P4.3 “ active low” during hardware reset period. The
hardware reset includes Internal (power on reset) and external pad reset. In application system
design, user should take care of the setting of P2.6, P2.7 or P4.3 at reset period to prevent
SM59R16A3 from entering ISP service program.
(4) Enter’s ISP service program by hardware setting, the port3.0 will be detected the two clock signals
during hardware reset period. The hardware reset includes Internal (power on reset) and external
pad reset. And detect 2 clock signals after hardware reset.
During hardware reset period, the hardware will detect the status of P2.6/P2.7/P4.3/P3.0. If they meet one of above
conditions, chip will switch to ISP mode automatically. After ISP service program executed, user need to reset the
SM59R16A3, either by hardware reset or by WDT, or jump to the address $0000 to re-start the firmware program.
There are 8 kinds of entry mechanisms for user different applications. This entry method will select on the writer or
ISP.
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
First Address Blank. i.e. $0000 = 0xFF. And triggered by Internal reset signal.
First Address Blank. i.e. $0000 = 0xFF. And triggered by PAD reset signal.
P2.6 = 0 & P2.7 = 0. And triggered by Internal reset signal.
P2.6 = 0 & P2.7 = 0. And triggered by PAD reset signal.
P4.3 = 0. And triggered by Internal reset signal.
P4.3 = 0. And triggered by PAD reset signal.
P3.0 input 2 clocks. And triggered by Internal reset signal.
P3.0 input 2 clocks. And triggered by PAD reset signal.
19.5. ISP register – TAKEY, IFCON, ISPFAH, ISPFAL, ISPFD and ISPFC
Mnemonic
Description
Direct
TAKEY
Time Access Key
register
F7h
Bit 7
Bit 6
Bit 5
ISP function
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESET
TAKEY [7:0]
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
75
Ver.E SM59R16A3 02/2012
00H
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
IFCON
ISPFAH
ISPFAL
ISPFD
ISPFC
Interface Control
register
ISP Flash
Address - High
register
ISP Flash
Address - Low
register
ISP Flash Data
register
ISP Flash Control
register
8Fh
ITS
CDPR
-
-
ALEC[1:0]
EMEN
ISPE
00H
E1h
ISPFAH [7:0]
FFH
E2h
ISPFAL [7:0]
FFH
E3h
ISPFD [7:0]
FFH
E4h
EMF1
Mnemonic: TAKEY
7
6
5
EMF2
EMF3
EMF4
4
3
TAKEY [7:0]
2
-
ISPF.2
1
ISPF.1
ISPF.0
00H
Address: F7H
0
Reset
00H
ISP enable bit (ISPE) is read-only by default, software must write three specific values 55h, AAh and 5Ah
sequentially to the TAKEY register to enable the ISPE bit write attribute. That is:
MOV TAKEY, #55h
MOV TAKEY, #AAh
MOV TAKEY, #5Ah
Mnemonic: IFCON
7
6
ITS
CDPR
5
-
4
-
3
2
ALEC[1:0]
1
EMEN
Address: 8FH
0
Reset
ISPE
00H
The bit 0 (ISPE) of IFCON is ISP enable bit. User can enable overall SM59R16A3 ISP function by setting ISPE
bit to 1, to disable overall ISP function by set ISPE to 0. The function of ISPE behaves like a security key. User
can disable overall ISP function to prevent software program be erased accidentally. ISP registers ISPFAH,
ISPFAL, ISPFD and ISPFC are read-only by default. Software must be set ISPE bit to 1 to enable these 4
registers write attribute.
Mnemonic: ISPFAH
Address: E1H
7
6
5
4
3
2
1
0
Reset
ISPFAH7 ISPFAH6 ISPFAH5 ISPFAH4 ISPFAH3 ISPFAH2 ISPFAH1 ISPFAH0
FFH
ISPFAH [7:0]: Flash address-high for ISP function
Mnemonic: ISPFAL
7
6
ISPFAL7 ISPFAL6
5
ISPFAL5
4
ISPFAL4
3
ISPFAL3
2
ISPFAL2
1
ISPFAL1
Address: E2H
0
Reset
ISPFAL0
FFH
ISPFAL [7:0]: Flash address-Low for ISP function
The ISPFAH & ISPFAL provide the 16-bit flash memory address for ISP function. The flash memory address
should not include the ISP service program space address. If the flash memory address indicated by ISPFAH
& ISPFAL registers overlay with the ISP service program space address, the flash program/page erase of ISP
function executed thereafter will have no effect.
Mnemonic: ISPFD
7
6
ISPFD7
ISPFD6
5
ISPFD5
4
ISPFD4
3
ISPFD3
2
ISPFD2
1
ISPFD1
Address: E3H
0
Reset
ISPFD0
FFH
ISPFD [7:0]: Flash data for ISP function.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
76
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
The ISPFD provide the 8-bit data register for ISP function.
Mnemonic: ISPFC
7
6
5
EMF1
EMF2
EMF3
4
EMF4
3
-
2
ISPF[2]
1
ISPF[1]
Address: E4H
0
Reset
ISPF[0]
00H
EMF1: Entry mechanism (1) flag, clear by reset. (Read only)
EMF2: Entry mechanism (2) flag, clear by reset. (Read only)
EMF3: Entry mechanism (3) flag, clear by reset. (Read only)
EMF4: Entry mechanism (4) flag, clear by reset. (Read only)
ISPF [2:0]: ISP function select bit.
ISPF[2:0]
ISP function
000
Byte program
001
Chip protect
010
Page erase
011
Chip erase
100
Write option
101
Read option
110
Erase option
111
One page of flash memory is 256 byte
The Option function can access the Internal reset time select(description in section
1.4.1)、clock source select(description in section 1.5)、P4[4:7] pins function
select(description in section 5)、WDTEN control bit(description in section 10)、or ISP
entry mechanisms select(description in section 19)。
When chip protected or no ISP service, option can only read.
The choice ISP function will start to execute once the software write data to ISPFC register.
To perform byte program/page erases ISP function, user need to specify flash address at first. When
performing page erase function, SM59R16A3 will erase entire page which flash address indicated by ISPFAH
& ISPFAL registers located within the page.
e.g. flash address: $XYMN
page erase function will erase from $XY00 to $XYFF
To perform the chip erase ISP function, SM59R16A3 will erase all the flash program memory except the ISP
service program space. To perform chip protect ISP function, the SM59R16A3 flash memory content will be
read #00H.
e.g. ISP service program to do the byte program - to program #22H to the address $1005H
MOV TAKEY, #55h
MOV TAKEY, #AAh
MOV TAKEY, #5Ah
MOV IFCON, #01H
MOV ISPFAH, #10H
MOV ISPFAL, #05H
MOV ISPFD, #22H
MOV ISPFC, #00H
; enable ISPE write attribute
; enable SM59R16A3 ISP function
; set flash address-high, 10H
; set flash address-low, 05H
; set flash data to be programmed, data = 22H
; start to program #22H to the flash address $1005H
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
77
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
Operating Conditions
Symbol
Description
Min.
Typ.
Max.
Unit.
Remarks
TA
Operating temperature
-40
25
85
℃
Ambient temperature under bias
VDD33
Supply voltage
2.7
3.3
3.6
V
VDD5
Supply voltage
4.5
5.0
5.5
V
DC Characteristics
TA = -40℃ to 85℃, VCC = 5.0V
Symbol
Parameter
Valid
VIL1
Input Low-voltage
Port 0,1,2,3,4,5
VIL2
Input Low-voltage
RES, XTAL1
VIH1
Input High-voltage
Port 0,1,2,3,4,5
VIH2
Input High-voltage
RES, XTAL1
VOL
Output Low-voltage
Port 0,1,2,3,4,5
Output High-voltage
Port 0,1,2,3,4,5
using Strong Pull-up(1)
VOH1
VOH2
IIL
ITL
ILI
RRST
CIO
ICC
Notes：
Output High-voltage
using Weak Pull-up(2)
Logic 0 Input Current
Logical Transition
Current
Input Leakage Current
Reset Pull-down
Resistor
Pin Capacitance
Port 0,1,2,3,4,5
Min
Max
Units
-0.5
0.8
V
0
0.8
V
2.0
VCC + 0.5
V
70%Vcc VCC + 0.5
V
0.4
Conditions
Vcc=5V
V
IOL=4.9mA
90% VCC
V
IOH= -4.6mA
2.4
V
IOH= -250uA
75% VCC
V
IOH= -162uA
90% VCC
V
IOH= -73uA
Vcc=5V
Port 0,1,2,3,4,5
-75
uA
Vin= 0.45V
Port 0,1,2,3,4,5
-650
uA
Vin= 2.0V
Port 0,1,2,3,4,5
±10
uA
0.45V<Vin<Vcc
300
kΩ
10
pF
Freq= 1MHz, Ta= 25℃
12
mA
Active mode, 12MHz VCC =5V
25 ℃
11
mA
Idle mode, 12MHz VCC =5V
25 ℃
5
uA
Power down mode VCC =5V
25 ℃
RES
Power Supply Current VDD
50
1. Port in Push-Pull Output Mode
2. Port in Quasi-Bidirectional Mode
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
78
Ver.E SM59R16A3 02/2012
SM59R16A3/SM59R09A3/SM59R05A3
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
TA = -40℃ to 85℃, VCC = 3.3V
Symbol
Parameter
Valid
VIL1
Input Low-voltage
Port 0,1,2,3,4,5
VIL2
Input Low-voltage
RES, XTAL1
VIH1
Input High-voltage
Port 0,1,2,3,4,5
VIH2
Input High-voltage
RES, XTAL1
VOL
Output Low-voltage
Port 0,1,2,3,4,5
Output High-voltage
Port 0,1,2,3,4,5
using Strong Pull-up(1)
VOH1
VOH2
IIL
ITL
ILI
RRST
CIO
ICC
Notes：
Output High-voltage
using Weak Pull-up(2)
Logic 0 Input Current
Logical Transition
Current
Input Leakage Current
Reset Pull-down
Resistor
Pin Capacitance
Port 0,1,2,3,4,5
Min
Max
Units
-0.5
0.8
V
0
0.8
V
2.0
VCC + 0.5
V
70%Vcc VCC + 0.5
V
0.4
Conditions
Vcc=3.3V
V
IOL=3.2mA
90% VCC
V
IOH= -2.3mA
2.4
V
IOH= -77uA
90% VCC
V
IOH= -33uA
Vcc=3.3V
Port 0,1,2,3,4,5
-75
uA
Vin= 0.45V
Port 0,1,2,3,4,5
-650
uA
Vin=1.5V
Port 0,1,2,3,4,5
±10
uA
0.45V<Vin<Vcc
300
kΩ
10
pF
Freq= 1MHz, Ta= 25℃
11
mA
Active mode ,12MHz VCC =
3.3 V 25 ℃
10
mA
Idle mode, 12MHz VCC =3.3V
25 ℃
4
uA
Power down mode VCC =3.3V
25 ℃
RES
Power Supply Current VDD
50
1. Port in Push-Pull Output Mode
2. Port in Quasi-Bidirectional Mode
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M051
79
Ver.E SM59R16A3 02/2012