issfd-m057_h_sm39r16..

SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
Table of Contents
Description............................................................................................................................................................3
Features.................................................................................................................................................................3
Pin Configuration..................................................................................................................................................4
28 Pin PDIP/SOP..........................................................................................................................................4
24 Pin PDIP/SOP..........................................................................................................................................5
20 Pin PDIP/SOP/SSOP ...............................................................................................................................5
Block Diagram......................................................................................................................................................6
Pin Description .....................................................................................................................................................7
Special Function Register (SFR) ........................................................................................................................10
Function Description ..........................................................................................................................................14
1 General Features ...........................................................................................................................................14
1.1
Embedded Flash..............................................................................................................................14
1.2
IO Pads............................................................................................................................................14
1.3
Instruction timing Selection............................................................................................................14
1.4
The Clock Out Selection.................................................................................................................15
1.5
RESET ............................................................................................................................................15
1.5.1
Hardware RESET function .................................................................................................15
1.5.2
Software RESET function ..................................................................................................15
1.5.3
Reset status .........................................................................................................................16
1.5.4
Time Access Key register (TAKEY) ..................................................................................16
1.5.5
Software Reset register (SWRES) ......................................................................................16
1.5.6
Example of software reset ..................................................................................................16
1.6
Clocks .............................................................................................................................................17
2 Instruction Set...............................................................................................................................................18
3 Memory Structure .........................................................................................................................................22
3.1
Program Memory............................................................................................................................22
3.2
Data Memory ..................................................................................................................................24
3.2.1
Data memory - lower 128 byte (00h to 7Fh) ......................................................................25
3.2.2
Data memory - higher 128 byte (80h to FFh).....................................................................25
4 CPU Engine ..................................................................................................................................................26
4.1
Accumulator ...................................................................................................................................26
4.2
B Register .......................................................................................................................................26
4.3
Program Status Word ......................................................................................................................27
4.4
Stack Pointer ...................................................................................................................................27
4.5
Data Pointer ....................................................................................................................................27
4.6
Data Pointer 1 .................................................................................................................................28
4.7
Clock control register .....................................................................................................................28
4.8
Interface control register.................................................................................................................29
5 GPIO .............................................................................................................................................................30
6 Timer 0 and Timer 1 .....................................................................................................................................32
6.1
Timer/counter mode control register (TMOD) ...............................................................................32
6.2
Timer/counter control register (TCON)..........................................................................................33
6.3
Peripheral Frequency control register.............................................................................................33
6.4
Mode 0 (13-bit Counter/Timer) ......................................................................................................34
6.5
Mode 1 (16-bit Counter/Timer) ......................................................................................................34
6.6
Mode 2 (8-bit auto-reload Counter/Timer) .....................................................................................35
Specifications subject to change without notice contact your sales representatives for the most recent information.
-1ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
6.7
Mode 3 (Timer 0 acts as two independent 8 bit Timers / Counters)...............................................35
7 Timer 2 and Capture Compare Unit..............................................................................................................36
7.1
Timer 2 function .............................................................................................................................38
7.1.1
Timer mode.........................................................................................................................38
7.1.2
Event counter mode ............................................................................................................38
7.1.3
Gated timer mode ...............................................................................................................39
7.1.4
Reload of Timer 2 ...............................................................................................................39
7.2
Compare function ...........................................................................................................................39
7.2.1
Compare Mode 0 ................................................................................................................39
7.2.2
Compare Mode 1 ................................................................................................................40
7.3
Capture function .............................................................................................................................41
7.3.1
Capture Mode 0 (by Hardware)..........................................................................................41
7.3.2
Capture Mode 1(by Software) ............................................................................................41
8 Serial interface ..............................................................................................................................................42
8.1
Serial interface ................................................................................................................................43
8.1.1
Mode 0 ................................................................................................................................43
8.1.2
Mode 1 ................................................................................................................................43
8.1.3
Mode 2 ................................................................................................................................44
8.1.4
Mode 3 ................................................................................................................................44
8.2
Multiprocessor Communication of Serial Interface .......................................................................45
8.3
Peripheral Frequency control register.............................................................................................45
8.4
Baud rate generator.........................................................................................................................46
8.4.1
Serial interface modes 1 and 3............................................................................................46
9 Watchdog timer.............................................................................................................................................47
10 Interrupt ........................................................................................................................................................50
10.1 Priority level structure ....................................................................................................................53
11 Power Management Unit ..............................................................................................................................55
11.1 Idle mode ........................................................................................................................................55
11.2 Stop mode .......................................................................................................................................55
12 Pulse Width Modulation (PWM) ..................................................................................................................56
13 IIC function...................................................................................................................................................58
14 SPI Function - Serial Peripheral Interface ....................................................................................................62
15 KBI – Keyboard Interface ............................................................................................................................66
16 LVI – Low Voltage Interrupt.........................................................................................................................69
17 10-bit Analog-to-Digital Converter (ADC) ..................................................................................................70
18 In-System Programming (Internal ISP) ........................................................................................................73
18.1 ISP service program........................................................................................................................73
18.2 Lock Bit (N)....................................................................................................................................73
18.3 Program the ISP Service Program ..................................................................................................74
18.4 Initiate ISP Service Program...........................................................................................................74
18.5 ISP register – TAKEY, IFCON, ISPFAH, ISPFAL, ISPFD and ISPFC .........................................75
19 Op/Comparator .............................................................................................................................................77
Operating Conditions..........................................................................................................................................79
DC Characteristics ..............................................................................................................................................79
OPA / Comparator Characteristics......................................................................................................................81
Specifications subject to change without notice contact your sales representatives for the most recent information.
-2ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
Product List
Features
SM39R16/12/08A2W20NP, SM39R16/12/08A2W24KP,
SM39R16/12/08A2W28KP, SM39R16/12/08A2W20SP,
SM39R16/12/08A2W24SP, SM39R16/12/08A2W28SP,
SM39R16/12/08A2W20GP
z
z
z
z
z
Description
The SM39R16A2 is a 1T (one machine cycle per clock)
single-chip 8-bit microcontroller. It has 16K-byte embedded
Flash for program, and executes all ASM51 instructions fully
compatible with MCS-51.
SM39R16A2 contains 256B on-chip RAM, more than 26
GPIOs (28L package), various serial interfaces and many
peripheral functions as described below. It can be
programmed via writers. Its on-chip ICE is convenient for
users in verification during development stage.
The high performance of SM39R16A2 can achieve
complicated manipulation within short time. About one third
of the instructions are pure 1T, and the average speed is 8
times of traditional 8051, the fastest one among all the 1T
51-series.Its excellent EMI and ESD characteristics are
advantageous for many different applications.
Ordering Information
SM39R16A2ihhkL yymmv
i: process identifier {W = 2.7V ~ 5.5V}
hh: pin count
k: package type postfix {as table below }
L:PB Free identifier
{No text is Non-PB free，”P” is PB free}
yy: year
mm: month
v: version identifier{ A, B,…}
Postfix
Package
N
S
K
G
PDIP (300 mil)
SOP (300 mil)
Skinny PDIP (300 mil)
SSOP (150 mil)
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
Operating Voltage: 2.7V ~ 5.5V
High speed architecture of 1 clock/machine cycle runs
up to 25MHz.
1~8T can be switched on the fly.
Instruction-set compatible with MCS-51.
22.1184MHz Internal RC oscillator, with programmable
clock divider
16K/12K/8K Bytes on-chip program memory.
256 bytes RAM as standard 8052,
Dual 16-bit Data Pointers (DPTR0 & DPTR1).
One serial peripheral interfaces in full duplex mode.
Additional Baud Rate Generator
Three 16-bit Timer/Counters. (Timer 0,1,2)
26 GPIOs(28L package)
External interrupt 0,1 with four priority levels
Programmable watchdog timer.
One IIC interface. (Master/Slave mode)
One SPI interface (Master/Slave mode)
2-channel PWM
4-channel 16-bit PCA for compare(PWM) / capture /
reload functions
8-channel 10-bit analog-to-digital converter (ADC)
OPA/CMP x1 Set (2 devices)
ISP/IAP/ICP functions.
ISP service program space configurable in N*256 byte
(N=0 to 16) size.
EEPROM function.
On-Chip in-circuit emulator (ICE) functions with
On-Chip Debugger (OCD).
Keyboard interface (KBI) for four more interrupts.
LVI/LVR (LVR deglitch 500ns)
IO PAD ESD over 4KV.
Enhance user code protection.
Power management unit for IDLE and power down modes.
Pin / Pad
Configuration
Page 3
Page 2,3
Page 2,3
Page 3
Contact SyncMOS : www.syncmos.com.tw
6F, No.10-2 Li- Hsin 1st Road , SBIP, Hsinchu, Taiwan
TEL: 886-3-567-1820
FAX: 886-3-567-1891
Specifications subject to change without notice contact your sales representatives for the most recent information.
3
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
Pin Configuration
28 Pin PDIP/SOP
28
P2.7/(IIC_SDA*)
CC3/(RXD*)/P2.1
2
27
P2.6/CC0/(IIC_SCL*)
OP1Out/ADC0/SPI_CLK/KBI0/P0.0
3
26
P0.1/KBI1/ADC1/OP1NIn
PWM1/MOSI/CC2/P1.7
4
25
P0.2/KBI2/ADC2/OP1PIn
PWM0/MISO/CC1/P1.6
5
24
P0.3/KBI3/T2/ADC3/OP0NIn
RST(default)/P1.5
6
23
P0.4/ADC4/OP0PIn
VSS
7
22
P0.5/ADC5
OSC_IN/XTAL1/P3.1
8
21
VDD
CLK_OUT/XTAL2/P3.0
9
20
P0.6/ADC6/OP0Out
SPI_SS/INT1/P1.4
10
19
P0.7/T1/ADC7
OCI_SDA/IIC_SDA/INT0/P1.3
11
18
P1.0/TXD
OCI_SCL/IIC_SCL/T0/P1.2
12
17
P1.1/RXD/T2EX
(MOSI*)/P2.2
13
16
P2.5/(SPI_CLK*)
(MISO*)/P2.3
14
15
P2.4/(SPI_SS*)
SyncMOS
1
SM39R16A2
yymmv
(28 Pin Top View)
(TXD*)/P2.0
Notes：
1. The pin Reset/P1.5 factory default is Reset, user must keep this pin at low during power-up. User can configure it to GPIO (P1.5)
by a flash programmer.
2. To avoid accidentally entering ISP-Mode(refer to section 18.4), care must be taken not asserting pulse signal at RXD P1.1/P2.1
during power-up while P2.6、P2.7、P1.6 are set to high.
3. To apply ICP function, OSI_SDA/P1.3 and OCI_SCL/P1.2 must be set to Bi-direction mode if they are configured as GPIO in
system.
4. Have *mark pins can offer the special function to switch, Please reference the SFR AUX introduction.
Specifications subject to change without notice contact your sales representatives for the most recent information.
4
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
24 Pin PDIP/SOP
24
P2.6/CC0
OP1Out/ADC0/SPI_CLK/KBI0/P0.0
2
23
P0.1/KBI1/ADC1/OP1NIn
PWM1/MOSI/CC2/P1.7
3
22
P0.2/KBI2/ADC2/OP1PIn
PWM0/MISO/CC1/P1.6
4
21
P0.3/KBI3/T2/ADC3/OP0NIn
RST(default)/P1.5
5
20
P0.4/ADC4/OP0PIn
VSS
6
19
P0.5/ADC5
OSC_IN/XTAL1/P3.1
7
18
VDD
CLKOUT/XTAL2/P3.0
8
17
P0.6/ADC6/OP0Out
SPI_SS/INT1/P1.4
9
16
P0.7/T1/ADC7
OCI_SDA/IIC_SDA/INT0/P1.3
10
15
P1.0/TXD
OCI_SCL/IIC_SCL/T0/P1.2
11
14
P1.1/RXD/T2EX
P2.2
12
13
P2.5
OP1Out/SPICLK/KBI0/P0.0
1
20
P0.1/KBI1/ADC1/OP1NIn
PWM1/MOSI/CC2/P1.7
2
19
P0.2/KBI2/ADC2/OP1PIn
PWM0/MISO/CC1/P1.6
3
18
P0.3/KBI3/T2/ADC3/OP0NIn
RST(default)/P1.5
4
17
P0.4/ADC4/OP0PIn
VSS
5
16
P0.5/ADC5
OSC_IN/XTAL1/P3.1
6
15
VDD
CLKOUT/XTAL2/P3.0
7
14
P0.6/ADC6/OP0Out
SPI_SS/INT1/P1.4
8
13
P0.7/T1/ADC7
OCI_SDA/IIC_SDA/INT0/P1.3
9
12
P1.0/TXD
OCI_SCL/IIC_SCL/T0/P1.2
10
11
P1.1/RXD/T2EX
SyncMOS
1
SM39R16A2
yymmv
(24 Pin Top View)
CC3/P2.1
20 Pin PDIP/SOP/SSOP
SyncMOS
SM39R16A2
yymmv
(20 Pin Top View)
Specifications subject to change without notice contact your sales representatives for the most recent information.
5
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
Block Diagram
Specifications subject to change without notice contact your sales representatives for the most recent information.
6
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
Pin Description
28L
Symbol
I/O
1
P2.0/(TXD*)
I/O
2
P2.1/(RXD*)/CC3
I/O
3
P0.0/KBI0/
SPI_CLK/ADC0/
OP1Out
I/O
4
P1.7/CC2/MOSI/
PWM1
I/O
5
P1.6/CC1/MISO/
PWM0
I/O
6
7
8
9
P1.5/RST
VSS
P3.1/XTAL1/OSC_IN
P3.0/XTAL2/CLKOUT
I/O
I
I/O
I/O
10
P1.4/INT1/SPI_SS
I/O
11
P1.3/INT0/
IIC_SDA/OCI_SDA
I/O
12
P1.2/T0/IIC_SCL/
OCI_SCL
I/O
13
P2.2/MOSI
I/O
14
P2.3/MISO
I/O
15
P2.4/(SPI_SS*)
I/O
16
P2.5/(SPI_CLK*)
I/O
17
P1.1/RXD/T2EX
I/O
18
P1.0/TXD
I/O
19
20
21
22
23
P0.7/T1/ADC7
P0.6/ADC6/ OP0Out
VDD
P0.5/ADC5
P0.4/ADC4/ OP0PIn
P0.3/KBI3/T2/
ADC3/OP0NIn
P0.2/KBI2/ADC2/
OP1Pin
P0.1/KBI1/ADC1/
OP1NIn
I/O
I/O
I
I/O
I/O
27
P2.6/CC0/(IIC_SCL*)
I/O
28
P2.7/(IIC_SDA*)
I/O
24
25
26
I/O
I/O
I/O
Description
Bit 0 of port 2 & Serial interface channel transmit data or
receive clock in mode 0 can be switch by AUX
Bit 1 of port 2 & Serial interface channel receive/transmit data
can be switch by AUX & Timer 2 compare/capture Channel 3
Bit 0 of port 0 & KBI interrupt 0 & SPI interface Clock pin &
ADC input channel 0 & Op1 output
Bit 7 of port 1 & Timer 2 compare/capture Channel 2 & SPI
interface Serial Data Master Output or Slave Input pin & PWM
Channel 1
Bit 6 of port 1 & Timer 2 compare/capture Channel 1 & SPI
interface Serial Data Master Input or Slave Output pin & PWM
Channel 0
Bit 5 of port 1 & Reset pin(default)
Power supply
Bit 1 of port 3 & Crystal input(default) & Oscillator input
Bit 0 of port 3 & Crystal output(default) & Clock Output
Bit 4 of port 1 & External interrupt 1 & SPI interface Slave
Select pin
Bit 3 of port 1 & External interrupt 0 & IIC SDA pin & On-Chip
Instrumentation Command and data I/O pin synchronous to
OCI_SCL in ICE and ICP functions
Bit 2 of port 1 & Timer 0 external input & IIC SCL pin &
On-Chip Instrumentation Clock I/O pin of ICE and ICP
functions
Bit 2 of Port 2 & SPI interface Serial Data Master Output or
Slave Input pin
Bit 3 of port 2 & SPI interface Serial Data Master Input or Slave
Output pin
Bit 4 of port 2 & SPI interface Slave Select pin can be switch by
AUX
Bit 5 of port 2 & SPI interface Clock pin can be switch by AUX
Bit 1 of port 1 & Serial interface channel 0 receive/transmit data
& Timer 2 capture trigger
Bit 0 of port 1 & Serial interface channel 0 transmit data or
receive clock in mode 0
Bit 7 of port 0 & Timer 1 external input & ADC input channel 7
Bit 6 of port 0 & ADC input channel 6 & Op0 Output
Power supply
Bit 5 of port 0 & ADC input channel 5
Bit 4 of port 0 & ADC input channel 4 & Op0 Positive Input
Bit 3 of port 0 & KBI interrupt 3 & Timer 2 external input clock
& ADC input channel 3 & Op0 Negative Input
Bit 2 of port 0 & KBI interrupt 2 & ADC input channel 2 & Op1
Positive Input
Bit 1 of port 0 & KBI interrupt 1 & ADC input channel 1 & Op1
Negative Input
Bit 6 of port 2 & Timer 2 compare/capture Channel 0 & IIC
SCL pin can be switch by AUX
Bit 7 of port 2 & IIC SDA pin can be switch by AUX
Specifications subject to change without notice contact your sales representatives for the most recent information.
7
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
24L
1
2
Symbol
P2.1/CC3
P0.0/KBI0/
SPI_CLK/ADC0/
OP1Out
I/O
I/O
I/O
3
P1.7/CC2/MOSI/
PWM1
I/O
4
P1.6/CC1/MISO/
PWM0
I/O
5
6
7
8
P1.5/RST
VSS
P3.1/XTAL1/OSC_IN
P3.0/XTAL2/CLKOUT
I/O
I
I/O
I/O
9
P1.4/INT1/SPI_SS
I/O
10
P1.3/INT0/
IIC_SDA/OCI_SDA
I/O
11
P1.2/T0/IIC_SCL/
OCI_SCL
I/O
12
13
P2.2
P2.5
I/O
I/O
14
P1.1/RXD/T2EX
I/O
15
P1.0/TXD
I/O
16
17
18
19
20
P0.7/T1/ADC7
P0.6/ADC6/ OP0Out
VDD
P0.5/ADC5
P0.4/ADC4/ OP0PIn
P0.3/KBI3/T2/
ADC3/OP0NIn
P0.2/KBI2/ADC2/
OP1Pin
P0.1/KBI1/ADC1/
OP1NIn
P2.6/CC0
I/O
I/O
I
I/O
I/O
21
22
23
24
I/O
I/O
I/O
I/O
Description
Bit 1 of port 2 & Timer 2 compare/capture Channel 3
Bit 0 of port 0 & KBI interrupt 0 & SPI interface Clock pin &
ADC input channel 0 & Op1 output
Bit 7 of port 1 & Timer 2 compare/capture Channel 2 & SPI
interface Serial Data Master Output or Slave Input pin & PWM
Channel 1
Bit 6 of port 1 & Timer 2 compare/capture Channel 1 & SPI
interface Serial Data Master Input or Slave Output pin & PWM
Channel 0
Bit 5 of port 1 & Reset pin(default)
Power supply
Bit 1 of port 3 & Crystal input(default) & Oscillator input
Bit 0 of port 3 & Crystal output(default) & Clock Output
Bit 4 of port 1 & External interrupt 1 & SPI interface Slave
Select pin
Bit 3 of port 1 & External interrupt 0 & IIC SDA pin & On-Chip
Instrumentation Command and data I/O pin synchronous to
OCI_SCL in ICE and ICP functions
Bit 2 of port 1 & Timer 0 external input & IIC SCL pin &
On-Chip Instrumentation Clock I/O pin of ICE and ICP
functions
Bit 2 of Port 2
Bit 5 of port 2 & SPI interface Clock pin
Bit 1 of port 1 & Serial interface channel 0 receive/transmit data
& Timer 2 capture trigger
Bit 0 of port 1 & Serial interface channel 0 transmit data or
receive clock in mode 0
Bit 7 of port 0 & Timer 1 external input & ADC input channel 7
Bit 6 of port 0 & ADC input channel 6 & Op0 Output
Power supply
Bit 5 of port 0 & ADC input channel 5
Bit 4 of port 0 & ADC input channel 4 & Op0 Positive Input
Bit 3 of port 0 & KBI interrupt 3 & Timer 2 external input clock
& ADC input channel 3 & Op0 Negative Input
Bit 2 of port 0 & KBI interrupt 2 & ADC input channel 2 & Op1
Positive Input
Bit 1 of port 0 & KBI interrupt 1 & ADC input channel 1 & Op1
Negative Input
Bit 6 of port 2 & Timer 2 compare/capture Channel 0
Specifications subject to change without notice contact your sales representatives for the most recent information.
8
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
20L
1
Symbol
P0.0/KBI0/SPI_CLK/
OP1Out
2
P1.7/CC2/MOSI/
PWM1
I/O
3
P1.6/CC1/MISO/
PWM0
I/O
4
5
6
7
P1.5/RST
VSS
P3.1/XTAL1/OSC_IN
P3.0/XTAL2/CLKOUT
I/O
I
I/O
I/O
8
P1.4/INT1/SPI_SS
I/O
9
P1.3/INT0/
IIC_SDA/OCI_SDA
I/O
10
P1.2/T0/IIC_SCL/
OCI_SCL
I/O
11
P1.1/RXD/T2EX
I/O
12
P1.0/TXD
I/O
13
14
15
16
17
P0.7/T1/ADC7
P0.6/ADC6/ OP0Out
VDD
P0.5/ADC5
P0.4/ADC4/ OP0PIn
P0.3/KBI3/T2/
ADC3/OP0NIn
P0.2/KBI2/ADC2/
OP1Pin
P0.1/KBI1/ADC1/
OP1NIn
I/O
I/O
I
I/O
I/O
18
19
20
I/O
I/O
I/O
I/O
I/O
Description
Bit 0 of port 0 & KBI interrupt 0 & SPI interface Clock pin &
Op1 output
Bit 7 of port 1 & Timer 2 compare/capture Channel 2 & SPI
interface Serial Data Master Output or Slave Input pin & PWM
Channel 1
Bit 6 of port 1 & Timer 2 compare/capture Channel 1 & SPI
interface Serial Data Master Input or Slave Output pin & PWM
Channel 0
Bit 5 of port 1 & Reset pin(default)
Power supply
Bit 1 of port 3 & Crystal input(default) & Oscillator input
Bit 0 of port 3 & Crystal output(default) & Clock Output
Bit 4 of port 1 & External interrupt 1 & SPI interface Slave
Select pin
Bit 3 of port 1 & External interrupt 0 & IIC SDA pin & On-Chip
Instrumentation Command and data I/O pin synchronous to
OCI_SCL in ICE and ICP functions
Bit 2 of port 1 & Timer 0 external input & IIC SCL pin &
On-Chip Instrumentation Clock I/O pin of ICE and ICP
functions
Bit 1 of port 1 & Serial interface channel 0 receive/transmit data
& Timer 2 capture trigger
Bit 0 of port 1 & Serial interface channel 0 transmit data or
receive clock in mode 0
Bit 7 of port 0 & Timer 1 external input & ADC input channel 7
Bit 6 of port 0 & ADC input channel 6 & Op0 Output
Power supply
Bit 5 of port 0 & ADC input channel 5
Bit 4 of port 0 & ADC input channel 4 & Op0 Positive Input
Bit 3 of port 0 & KBI interrupt 3 & Timer 2 external input clock
& ADC input channel 3 & Op0 Negative Input
Bit 2 of port 0 & KBI interrupt 2 & ADC input channel 2 & Op1
Positive Input
Bit 1 of port 0 & KBI interrupt 1 & ADC input channel 1 & Op1
Negative Input
Specifications subject to change without notice contact your sales representatives for the most recent information.
9
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
Special Function Register (SFR)
A map of the Special Function Registers is shown as below:
Hex\Bin
F8
X000
IICS
X001
IICCTL
X010
IICA1
X011
IICA2
X100
IICRWD
X101
IICEBT
X110
CMP0CON
X111
CMP1CON
Bin/Hex
FF
F0
E8
E0
D8
B
SPIC1
SPIC2
SPITXD
SPIRXD
SPIS
OPPIN
TAKEY
ACC
ISPFAH
PFCON
ISPFAL
P3M0
ISPFD
P3M1
ISPFC
LVC
SWRES
F7
EF
E7
DF
D0
PSW
CCEN2
P0M0
P0M1
P1M0
P1M1
P2M0
P2M1
D7
C8
C0
B8
T2CON
IRCON
IEN1
CCCON
CCEN
IP1
CRCL
CCL1
SRELH
CRCH
CCH1
TL2
CCL2
PWMD0H
TH2
CCH2
PWMD0L
PWMMDH
CCL3
PWMD1H
PWMMDL
CCH3
PWMD1L
CF
C7
BF
B0
A8
A0
98
P3
IEN0
P2
SCON
IP0
RSTS
SBUF
ADCC1
ADCC2
PWMC
ADCDH
WDTC
ADCDL
WDTK
ADCCS
B7
AF
A7
9F
90
P1
AUX
KBLS
KBE
KBF
KBD
IRCON2
97
88
80
Hex\Bin
TCON
P0
X000
TMOD
SP
X001
TL1
DPH
X011
TH0
DPL1
X100
TH1
DPH1
X101
CKCON
IFCON
PCON
X111
8F
87
Bin/Hex
SRELL
IEN2
TL0
DPL
X010
X110
Note: Special Function Registers reset values and description for SM39R16A2
Register
Location
Reset value
Description
81h
E0h
D0h
F0h
82h
83h
84h
85h
91h
87h
8Eh
07h
00h
00h
00h
00h
00h
00h
00h
00h
00h
10h
Stack Pointer
Accumulator
Program Status Word
B Register
Data Pointer 0 low byte
Data Pointer 0 high byte
Data Pointer 1 low byte
Data Pointer 1 high byte
Auxiliary register
Power Control
Clock control register
SYSTEM
SP
ACC
PSW
B
DPL
DPH
DPL1
DPH1
AUX
PCON
CKCON
INTERRUPT & PRIORITY
IRCON
C0h
00h
Interrupt Request Control Register
IRCON2
IEN0
IEN1
97h
A8h
B8h
00h
00h
00h
Interrupt Request Control Register 2
Interrupt Enable Register 0
Interrupt Enable Register 1
Specifications subject to change without notice contact your sales representatives for the most recent information.
10
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
Register
IEN2
IP0
Location
9Ah
A9h
Reset value
00h
00h
Description
Interrupt Enable Register 2
Interrupt Priority Register 0
IP1
B9h
00h
Interrupt Priority Register 1
KBLS
KBE
KBF
KBD
93h
94h
95h
96h
00h
00h
00h
00h
Keyboard level selector Register
Keyboard input enable Register
Keyboard interrupt flag Register
Keyboard interface De-bounce control register
87h
91h
98h
99h
AAh
BAh
D9h
00h
00h
00h
00h
00h
00h
00h
Power Control
Auxiliary register
Serial Port, Control Register
Serial Port, Data Buffer
Serial Port, Reload Register, low byte
Serial Port, Reload Register, high byte
Peripheral Frequency control register
ABh
ACh
ADh
AEh
AFh
00h
00h
00h
00h
00h
ADC Control 1 Register
ADC Control 2 Register
ADC data high byte
ADC data low byte
ADC clock select
RSTS
A1h
00h
Reset status register
WDTC
WDTK
TAKEY
B6h
B7h
F7h
04h
00h
00h
Watchdog timer control register
Watchdog timer refresh key.
Time Access Key register
PWMC
PWMD0H
PWMD0L
PWMD1H
B5h
BCh
BDh
BEh
00h
00h
00h
00h
PWM control register
PWM channel 0 data high byte
PWM channel 0 data low byte
PWM channel 1 data high byte
PWMD1L
PWMMDH
PWMMDL
BFh
CEh
CFh
00h
00h
FFh
PWM channel 1 data low byte
PWM Max Data Register, high byte.
PWM Max Data Register, low byte.
TCON
TMOD
TL0
88h
89h
8Ah
00h
00h
00h
Timer/Counter Control
Timer Mode Control
Timer 0, low byte
TL1
TH0
8Bh
8Ch
00h
00h
Timer 1, low byte
Timer 0, high byte
KBI
UART
PCON
AUX
SCON
SBUF
SRELL
SRELH
PFCON
ADC
ADCC1
ADCC2
ADCDH
ADCDL
ADCCS
WDT
PWM
TIMER0/TIMER1
Specifications subject to change without notice contact your sales representatives for the most recent information.
11
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
Register
TH1
PFCON
Location
8Dh
D9h
Reset value
00h
00h
Description
Timer 1, high byte
Peripheral Frequency control register
CCEN
CCL1
C1h
C2h
00h
00h
Compare/Capture Enable Register
Compare/Capture Register 1, low byte
CCH1
CCL2
CCH2
CCL3
CCH3
T2CON
CCCON
CRCL
C3h
C4h
C5h
C6h
C7h
C8h
C9h
CAh
00h
00h
00h
00h
00h
00h
00h
00h
Compare/Capture Register 1, high byte
Compare/Capture Register 2, low byte
Compare/Capture Register 2, high byte
Compare/Capture Register 3, low byte
Compare/Capture Register 3, high byte
Timer 2 Control
Compare/Capture Control
Compare/Reload/Capture Register, low byte
CRCH
TL2
TH2
CCEN2
CBh
CCh
CDh
D1h
00h
00h
00h
00h
Compare/Reload/Capture Register, high byte
Timer 2, low byte
Timer 2, high byte
Compare/Capture Enable 2 register
P0
P1
P2
80h
90h
A0h
FFh
FFh
FFh
Port 0
Port 1
Port 2
P3
P0M0
P0M1
P1M0
P1M1
P2M0
P2M1
P3M0
B0h
D2h
D3h
D4h
D5h
D6h
D7h
DAh
FFh
00h
00h
00h
00h
00h
00h
00h
Port 3
Port 0 output mode 0
Port 0 output mode 1
Port 1 output mode 0
Port 1 output mode 1
Port 2 output mode 0
Port 2 output mode 1
Port 3 output mode 0
P3M1
DBh
00h
Port 3 output mode 1
IFCON
ISPFAH
ISPFAL
ISPFD
ISPFC
8Fh
E1h
E2h
E3h
E4h
00h
FFh
FFh
FFh
00h
Interface control register
ISP Flash Address-High register
ISP Flash Address-Low register
ISP Flash Data register
ISP Flash control register
TAKEY
F7h
00h
Time Access Key register
00h
20h
00h
00h
Reset status register
Low voltage control register
Software Reset register
Time Access Key register
PCA(TIMER2)
GPIO
ISP/IAP/EEPROM
LVI/LVR/SOFTRESET
RSTS
LVC
SWRES
TAKEY
A1h
E6h
E7h
F7h
Specifications subject to change without notice contact your sales representatives for the most recent information.
12
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
Register
Location
Reset value
Description
AUX
SPIC1
SPIC2
SPITXD
91h
F1h
F2h
F3h
00h
08h
00h
00h
Auxiliary register
SPI control register 1
SPI control register 2
SPI transmit data buffer
SPIRXD
SPIS
F4h
F5h
00h
40h
SPI receive data buffer
SPI status register
AUX
IICS
IICCTL
IICA1
IICA2
91h
F8h
F9h
FAh
FBh
00h
00h
04h
A0h
60h
Auxiliary register
IIC status register
IIC control register
IIC channel 1 Address 1 register
IIC channel 1 Address 2 register
IICRWD
IICEBT
FCh
FDh
00h
00h
IIC channel 1 Read / Write Data buffer
IIC Enable Bus Transaction register
F6h
FEh
FFh
00H
00h
00h
Op/Comparator Pin Select register
Comparator 0 Control register
Comparator 1 Control register
SPI
IIC
OPA
OPPIN
CMP0CON
CMP1CON
Specifications subject to change without notice contact your sales representatives for the most recent information.
13
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
Function Description
1
General Features
SM39R16A2 is an 8-bit micro-controller. All of its functions and the detailed meanings of SFR will be given in the following
sections.
1.1
Embedded Flash
The program can be loaded into the embedded 16KB/12KB/8KB Flash memory via its writer or In-System Programming (ISP). The
high-quality Flash has a 100K-write cycle life，suitable for re-programming and data recording as EEPROM.
1.2
IO Pads
The SM39R16A2 has Four I/O ports: Port 0, Port 1, Port 2 and Port 3. Ports 0, 1, 2 are 8-bit ports and Port 3 is a 2-bit port. These are:
quasi-bidirectional (standard 8051 port outputs), push-pull, open drain, and input-only. As description in section 5.
All the pads for P0、P1、P2 and P3 are with slew rate to reduce EMI. The IO pads can withstand 4KV ESD in human body mode
guaranteeing the SM39R16A2’s quality in high electro-static environments.
The RESET Pin can define as General I/O P1.5 when user use Internal RESET.
The XTAL2 and XTAL1 can define as P3.0 and P3.1 by writer or ISP，when user use internal OSC as system clock；when user use
external OSC as system clock and input into XTAL1，Only XTAL2 can be defined as P3.0.
1.3
Instruction timing Selection
The conventional 52-series MCUs are 12T, i.e., 12 oscillator clocks per machine cycle. SM39R16A2 is a 1T to 8T MCU, i.e., its
machine cycle is one-clock to eight-clock. In the other words, it can execute one instruction within one clock to only eight clocks.
Mnemonic: CKCON
7
6
5
ITS[2:0]
ITS: Instruction timing select.
ITS [2:0]
000
001
010
011
100
101
110
111
4
3
-
2
-
Address: 8Eh
1
0
Reset
CLKOUT[1:0]
10H
Instruction timing
1T mode
2T mode (default)
3T mode
4T mode
5T mode
6T mode
7T mode
8T mode
The default is in 2T mode, and it can be changed to another Instruction timing mode if CKCON [6:4] (at address 8Eh) is change any
time. Not every instruction can be executed with one machine cycle. The exact machine cycle number for all the instructions are
given in the next section.
Specifications subject to change without notice contact your sales representatives for the most recent information.
14
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
1.4
The Clock Out Selection
The SM39R16A2 can Generator a clock out signal at P3.0， when user use Oscillator (XTAL1 as clock input) or internal OSC as
system clock. The CKCON [1:0] (at address 8Eh) can change any time.
CLKOUT: Clock output select.
CKCON [1:0]
Mode.
00
GPIO(default)
01
Fosc
10
Fosc/2
11
Fosc/4
It can be used when the system clock is the internal RC oscillator.
1.5
RESET
1.5.1 Hardware RESET function
SM39R16A2 provides Internal reset circuit inside，the Internal reset time can set by writer or ISP.
Internal Reset time
25ms (default)
200ms
100ms
50ms
16ms
8ms
4ms
1.5.2 Software RESET function
SM39R16A2 provides one software reset mechanism to reset whole chip. To perform a software reset, the firmware must write three
specific values 55h, AAh and 5Ah sequentially to the TAKEY register to enable the Software Reset register (SWRES) write attribute.
After SWRES register obtain the write authority, the firmware can write FFh to the SWRES register. The hardware will decode a
reset signal that “OR” with the other hardware reset. The SWRES register is self-reset at the end of the software reset procedure.
Mnemonic
Description
RSTS
Reset status register
Time Access Key
register
Software Reset
register
TAKEY
SWRES
Direc
t
Bit 7
A1h
-
Bit 6
Bit 5
Bit 4
Software Reset function
PDRF
-
Bit 3
Bit 2
Bit 1
Bit 0
RESE
T
WDTF
SWRF
LVRF
PORF
00H
F7h
TAKEY [7:0]
00H
E7h
SWRES [7:0]
00H
Specifications subject to change without notice contact your sales representatives for the most recent information.
15
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
1.5.3 Reset status
Mnemonic: RSTS
7
6
-
5
-
4
PDRF
3
WDTF
2
SWRF
1
LVRF
Address: A1h
0
Reset
PORF
00H
PDRF: Pad reset flag.
When MCU is reset by reset pad, PDRF flag will be set to one by hardware. This flag clear by
software.
WDTF: Watchdog timer reset flag.
When MCU is reset by watchdog, WDTF flag will be set to one by hardware. This flag clear by
software.
SWRF: Software reset flag.
When MCU is reset by software, SWRF flag will be set to one by hardware. This flag clear by
software.
LVRF: Low voltage reset flag.
When MCU is reset by LVR, LVRF flag will be set to one by hardware. This flag clear by
software.
PORF: Power on reset flag.
When MCU is reset by POR, PORF flag will be set to one by hardware. This flag clear by
software.
1.5.4 Time Access Key register (TAKEY)
Mnemonic: TAKEY
7
6
Address: F7H
5
4
3
TAKEY [7:0]
2
1
0
Reset
00H
Software reset register (SWRES) is read-only by default; software must write three specific values 55h, AAh
and 5Ah sequentially to the TAKEY register to enable the SWRES register write attribute. That is:
MOV TAKEY, #55h
MOV TAKEY, #0AAh
MOV TAKEY, #5Ah
1.5.5 Software Reset register (SWRES)
Mnemonic: SWRES
7
6
5
4
3
SWRES [7:0]
2
1
Address: E7H
0
Reset
00H
SWRES [7:0]: Software reset register bit. These 8-bit is self-reset at the end of the reset procedure.
SWRES [7:0] = FFh, software reset.
SWRES [7:0] = 00h ~ FEh, MCU no action.
1.5.6 Example of software reset
MOV TAKEY, #55h
MOV TAKEY, #0AAh
MOV TAKEY, #5Ah ; enable SWRES write attribute
MOV SWRES, #0FFh ; software reset MCU
Specifications subject to change without notice contact your sales representatives for the most recent information.
16
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
1.6
Clocks
The default clock is the 22.1184MHz Internal OSC. This clock is used during the initialization stage. The major work of the
initialization stage is to determine the clock source used in normal operation.
The internal clock sources are from the internal OSC with difference frequency division as given in
set by writer or ICP.
table 1-1，the clock source can
Table 1-1: Selection of clock source
Clock source
external crystal (use XTAL1 and XTAL2 pins )
external crystal (only use XTAL1, the XTAL2 define as I/O)
22.1184MHz from internal OSC
22.1184MHz/2 from internal OSC
22.1184MHz/4 from internal OSC
22.1184MHz/8 from internal OSC
22.1184MHz/16 from internal OSC
There may be having a little variance in the frequency from the internal OSC. The max variance as giving in table 1-2.
Table 1-2: Temperature with variance
Temperature Max Variance
25℃
±2%
Specifications subject to change without notice contact your sales representatives for the most recent information.
17
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
2
Instruction Set
All SM39R16A2 instructions are binary code compatible and perform the same functions as they do with the industry standard 8051.
The following tables give a summary of the instruction set cycles of the SM39R16A2 Microcontroller core.
Mnemonic
ADD A,Rn
ADD A,direct
Table 2-1: Arithmetic operations
Description
Add register to accumulator
Add direct byte to accumulator
Code
28-2F
25
Bytes
1
2
Cycles
1
2
ADD A,@Ri
ADD A,#data
ADDC A,Rn
ADDC A,direct
Add indirect RAM to accumulator
Add immediate data to accumulator
Add register to accumulator with carry flag
Add direct byte to A with carry flag
26-27
24
38-3F
35
1
2
1
2
2
2
1
2
ADDC A,@Ri
ADDC A,#data
SUBB A,Rn
SUBB A,direct
Add indirect RAM to A with carry flag
Add immediate data to A with carry flag
Subtract register from A with borrow
Subtract direct byte from A with borrow
36-37
34
98-9F
95
1
2
1
2
2
2
1
2
SUBB A,@Ri
SUBB A,#data
INC A
INC Rn
INC direct
Subtract indirect RAM from A with borrow
Subtract immediate data from A with borrow
Increment accumulator
Increment register
Increment direct byte
96-97
94
04
08-0F
05
1
2
1
1
2
2
2
1
2
3
INC @Ri
INC DPTR
DEC A
DEC Rn
Increment indirect RAM
Increment data pointer
Decrement accumulator
Decrement register
06-07
A3
14
18-1F
1
1
1
1
3
1
1
2
DEC direct
DEC @Ri
MUL AB
DIV
Decrement direct byte
Decrement indirect RAM
Multiply A and B
Divide A by B
15
16-17
A4
84
2
1
1
1
3
3
5
5
DA A
Decimal adjust accumulator
D4
1
1
Specifications subject to change without notice contact your sales representatives for the most recent information.
18
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
Mnemonic
ANL A,Rn
ANL A,direct
Table 2-2: Logic operations
Description
AND register to accumulator
AND direct byte to accumulator
Code
58-5F
55
Bytes
1
2
Cycles
1
2
ANL A,@Ri
ANL A,#data
ANL direct,A
ANL direct,#data
AND indirect RAM to accumulator
AND immediate data to accumulator
AND accumulator to direct byte
AND immediate data to direct byte
56-57
54
52
53
1
2
2
3
2
2
3
4
ORL A,Rn
ORL A,direct
ORL A,@Ri
ORL A,#data
OR register to accumulator
OR direct byte to accumulator
OR indirect RAM to accumulator
OR immediate data to accumulator
48-4F
45
46-47
44
1
2
1
2
1
2
2
2
ORL direct,A
ORL direct,#data
XRL A,Rn
XRL A,direct
OR accumulator to direct byte
OR immediate data to direct byte
Exclusive OR register to accumulator
Exclusive OR direct byte to accumulator
42
43
68-6F
65
2
3
1
2
3
4
1
2
XRL A,@Ri
Exclusive OR indirect RAM to accumulator
66-67
1
2
XRL A,#data
Exclusive OR immediate data to accumulator
64
2
2
XRL direct,A
XRL direct,#data
CLR A
Exclusive OR accumulator to direct byte
Exclusive OR immediate data to direct byte
Clear accumulator
62
63
E4
2
3
1
3
4
1
CPL A
Complement accumulator
F4
1
1
RL A
RLC A
RR A
Rotate accumulator left
Rotate accumulator left through carry
Rotate accumulator right
23
33
03
1
1
1
1
1
1
RRC A
Rotate accumulator right through carry
13
1
1
SWAP A
Swap nibbles within the accumulator
C4
1
1
Specifications subject to change without notice contact your sales representatives for the most recent information.
19
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
Mnemonic
MOV A,Rn
MOV A,direct
Table 2-3: Data transfer
Description
Move register to accumulator
Move direct byte to accumulator
Code
E8-EF
E5
Bytes
1
2
Cycles
1
2
MOV A,@Ri
MOV A,#data
MOV Rn,A
MOV Rn,direct
Move indirect RAM to accumulator
Move immediate data to accumulator
Move accumulator to register
Move direct byte to register
E6-E7
74
F8-FF
A8-AF
1
2
1
2
2
2
2
4
MOV Rn,#data
MOV direct,A
MOV direct,Rn
MOV direct1,direct2
Move immediate data to register
Move accumulator to direct byte
Move register to direct byte
Move direct byte to direct byte
78-7F
F5
88-8F
85
2
2
2
3
2
3
3
4
MOV direct,@Ri
MOV direct,#data
MOV @Ri,A
MOV @Ri,direct
Move indirect RAM to direct byte
Move immediate data to direct byte
Move accumulator to indirect RAM
Move direct byte to indirect RAM
86-87
75
F6-F7
A6-A7
2
3
1
2
4
3
3
5
MOV @Ri,#data
Move immediate data to indirect RAM
76-77
2
3
MOV DPTR,#data16
Load data pointer with a 16-bit constant
90
3
3
MOVC A,@A+DPTR
MOVC A,@A+PC
PUSH direct
Move code byte relative to DPTR to accumulator
Move code byte relative to PC to accumulator
Push direct byte onto stack
93
83
C0
1
1
2
3
3
4
POP direct
XCH A,Rn
XCH A,direct
XCH A,@Ri
XCHD A,@Ri
Pop direct byte from stack
Exchange register with accumulator
Exchange direct byte with accumulator
Exchange indirect RAM with accumulator
Exchange low-order nibble indir. RAM with A
D0
C8-CF
C5
C6-C7
D6-D7
2
1
2
1
1
3
2
3
3
3
Specifications subject to change without notice contact your sales representatives for the most recent information.
20
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
Mnemonic
ACALL addr11
LCALL addr16
Table 2-4: Program branches
Description
Absolute subroutine call
Long subroutine call
Code
xxx11
12
Bytes
2
3
Cycles
6
6
RET
RETI
AJMP addr11
LJMP addr16
from subroutine
from interrupt
Absolute jump
Long iump
22
32
xxx01
02
1
1
2
3
4
4
3
4
SJMP rel
JMP @A+DPTR
JZ rel
JNZ rel
Short jump (relative addr.)
Jump indirect relative to the DPTR
Jump if accumulator is zero
Jump if accumulator is not zero
80
73
60
70
2
1
2
2
3
2
3
3
JC rel
JNC
JB bit,rel
JNB bit,rel
Jump if carry flag is set
Jump if carry flag is not set
Jump if direct bit is set
Jump if direct bit is not set
40
50
20
30
2
2
3
3
3
3
4
4
JBC bit,direct rel
Jump if direct bit is set and clear bit
10
3
4
CJNE A,direct rel
Compare direct byte to A and jump if not equal
B5
3
4
CJNE A,#data rel
CJNE Rn,#data rel
CJNE @Ri,#data rel
Compare immediate to A and jump if not equal
Compare immed. to reg. and jump if not equal
Compare immed. to ind. and jump if not equal
B4
B8-BF
B6-B7
3
3
3
4
4
4
DJNZ Rn,rel
Decrement register and jump if not zero
D8-DF
2
3
DJNZ direct,rel
NOP
Decrement direct byte and jump if not zero
No operation
D5
00
3
1
4
1
Mnemonic
CLR C
CLR bit
Table 2-5: Boolean manipulation
Description
Clear carry flag
Clear direct bit
Code
C3
C2
SETB C
SETB bit
CPL C
CPL bit
Set carry flag
Set direct bit
Complement carry flag
Complement direct bit
ANL C,bit
ANL C,/bit
ORL C,bit
ORL C,/bit
MOV C,bit
MOV bit,C
Bytes
1
2
Cycles
1
3
D3
D2
B3
B2
1
2
1
2
1
3
1
3
AND direct bit to carry flag
AND complement of direct bit to carry
OR direct bit to carry flag
OR complement of direct bit to carry
82
B0
72
A0
2
2
2
2
2
2
2
2
Move direct bit to carry flag
Move carry flag to direct bit
A2
92
2
2
2
3
Specifications subject to change without notice contact your sales representatives for the most recent information.
21
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
3
Memory Structure
The SM39R16A2 memory structure follows general 8052 structure. It is 16KB program memory.
3.1
Program Memory
The SM39R16A2 has 16KB on-chip flash memory which can be used as general program memory or EEPROM, on which include
up to 4K byte specific ISP service program memory space. The address range for the 16K byte is $0000 to $3FFF. The address range
for the ISP service program is $3000 to $3FFF. The ISP service program size can be partitioned as N blocks of 256 byte (N=0 to 16).
When N=0 means no ISP service program space available, total 16K byte memory used as program memory. When N=1 means
address $3F00 to $3FFF reserved for ISP service program. When N=2 means memory address $3E00 to $3FFF reserved for ISP
service program…etc. Value N can be set and programmed into SM39R16A2 by the writer or ICP. It can be used to record any data
as EEPROM(If you need modify the data on program memory, please page erase first ). The procedure of this EEPROM application
function is described in the section 18 on internal ISP.
ISP service
Program space,
Up to 4K
16K Program
Memory space
3FFF
3F00
3E00
3D00
3C00
3B00
3A00
3900
3800
3700
3600
3500
3400
3300
3200
3100
3000
N=2
N=3
N=4
N=5
N=6
N=7
N=8
N=9
N=10
N=11
N=12
N=13
N=14
N=15
N=16
0000
Fig. 3-1: SM39R16A2 programmable Flash
Specifications subject to change without notice contact your sales representatives for the most recent information.
22
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
ISP service
Program space,
Up to 4K
3FFF
3F00
3E00
3D00
3C00
3B00
3A00
3900
3800
3700
3600
3500
3400
3300
3200
3100
3000
N=2
N=3
N=4
N=5
N=6
N=7
N=8
N=9
N=10
N=11
N=12
N=13
N=14
N=15
N=16
2000
1FFF
8K Program
Memory space
0000
Fig. 3-2 : SM39R12A2 programmable Flash
Specifications subject to change without notice contact your sales representatives for the most recent information.
23
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
3FFF
3F00
3E00
3D00
3C00
3B00
3A00
3900
3800
3700
3600
3500
3400
3300
3200
3100
3000
ISP service
Program space,
Up to 4K
N=2
N=3
N=4
N=5
N=6
N=7
N=8
N=9
N=10
N=11
N=12
N=13
N=14
N=15
N=16
1000
0FFF
4K Program
Memory space
0000
Fig. 3-3 : SM39R08A2 programmable Flash
3.2
Data Memory
The SM39R16A2 has 256Bytes on-chip SRAM; 256 Bytes of it are the same as general 8052 internal memory structure
FF
FF
Higher 128 Bytes (Accessed by
indirect addressing mode only)
SFR (Accessed by direct addressing
mode only)
80
7F
80
Lower 128 Bytes (Accessed by
direct & indirect addressing mode )
00
Fig. 3-4: RAM architecture
Specifications subject to change without notice contact your sales representatives for the most recent information.
24
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
3.2.1 Data memory - lower 128 byte (00h to 7Fh)
Data memory 00h to FFh is the same as 8052.
The address 00h to 7Fh can be accessed by direct and indirect addressing modes.
Address 00h to 1Fh is register area.
Address 20h to 2Fh is memory bit area.
Address 30h to 7Fh is for general memory area.
3.2.2 Data memory - higher 128 byte (80h to FFh)
The address 80h to FFh can be accessed by indirect addressing mode.
Address 80h to FFh is data area.
Specifications subject to change without notice contact your sales representatives for the most recent information.
25
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
4
CPU Engine
The SM39R16A2 engine is composed of four components:
a. Control unit
b. Arithmetic – logic unit
c. Memory control unit
d. RAM and SFR control unit
The SM39R16A2 engine allows to fetch instruction from program memory and to execute using RAM or SFR. The following
chapter describes the main engine register.
Mnemonic
Description
ACC
B
Accumulator
B register
Program status
word
Stack Pointer
Data pointer low 0
Data pointer high 0
Data pointer low 0
Data pointer high 0
Auxiliary register
Clock control
register
Interface control
register
PSW
SP
DPL
DPH
DPL1
DPH1
AUX
CKCON
IFCON
4.1
Direc
t
Bit 7
E0h
F0h
ACC.7
B.7
D0h
CY
81h
82h
83h
84h
85h
91h
BRGS
8Eh
-
8Fh
-
Bit 6
Bit 5
8051 Core
ACC.6 ACC.5
B.6
B.5
AC
-
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESE
T
ACC.4
B.4
ACC.3
B.3
ACC.2
B.2
ACC.1
B.1
ACC.0
B.0
00H
00H
OV
PSW.1
P
00H
DPS
07H
00H
00H
00H
00H
00H
CLKOUT[1:0]
10H
F0
RS[1:0]
P2SPI
SP[7:0]
DPL[7:0]
DPH[7:0]
DPL1[7:0]
DPH1[7:0]
P2UR
P2IIC
-
ITS[2:0]
CDPR
-
-
-
-
-
-
ISPE
00H
Accumulator
ACC is the Accumulator register. Most instructions use the accumulator to store the operand.
Mnemonic: ACC
7
6
ACC.7
ACC.6
5
ACC05
4
ACC.4
3
ACC.3
2
ACC.2
1
ACC.1
Address: E0h
0
Reset
ACC.0
00h
ACC[7:0]: The A (or ACC) register is the standard 8052 accumulator.
4.2
B Register
The B register is used during multiply and divide instructions. It can also be used as a scratch pad register to store temporary data.
Mnemonic: B
7
6
B.7
B.6
5
B.5
4
B.4
3
B.3
2
B.2
1
B.1
Address: F0h
0
Reset
B.0
00h
B[7:0]: The B register is the standard 8052 register that serves as a second accumulator.
Specifications subject to change without notice contact your sales representatives for the most recent information.
26
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
4.3
Program Status Word
Mnemonic: PSW
7
6
CY
AC
5
F0
4
3
2
OV
RS [1:0]
1
F1
0
P
Address: D0h
Reset
00h
CY: Carry flag.
AC: Auxiliary Carry flag for BCD operations.
F0: General purpose Flag 0 available for user.
RS[1:0]: Register bank select, used to select working register bank.
RS[1:0]
Bank Selected
Location
00
Bank 0
00h – 07h
01
Bank 1
08h – 0Fh
10
Bank 2
10h – 17h
11
Bank 3
18h – 1Fh
OV: Overflow flag.
F1: General purpose Flag 1 available for user.
P: Parity flag, affected by hardware to indicate odd/even number of “one” bits in the Accumulator, i.e.
even parity.
4.4 Stack Pointer
The stack pointer is a 1-byte register initialized to 07h after reset. This register is incremented before PUSH and CALL instructions,
causing the stack to start from location 08h.
Mnemonic: SP
7
6
5
4
3
2
1
SP [7:0]
Address: 81h
0
Reset
07h
SP[7:0]: The Stack Pointer stores the scratchpad RAM address where the stack begins. In other words, it
always points to the top of the stack.
4.5
Data Pointer
The data pointer (DPTR) is 2-bytes wide. The lower part is DPL, and the highest is DPH. It can be loaded as a 2-byte register (e.g.
MOV DPTR, #data16) or as two separate registers (e.g. MOV DPL,#data8). It is generally used to access the external code or data
space (e.g. MOVC A, @A+DPTR, @DPTR respectively).
Mnemonic: DPL
7
6
5
4
3
DPL [7:0]
2
1
Address: 82h
0
Reset
00h
4
3
DPH [7:0]
2
1
Address: 83h
0
Reset
00h
DPL[7:0]: Data pointer Low 0
Mnemonic: DPH
7
6
5
DPH [7:0]: Data pointer High 0
Specifications subject to change without notice contact your sales representatives for the most recent information.
27
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
4.6
Data Pointer 1
The Dual Data Pointer accelerates the moves of data block. The standard DPTR is a 16-bit register that is used to address external
memory or peripherals. In the SM39R16A2 core the standard data pointer is called DPTR, the second data pointer is called DPTR1.
The data pointer select bit chooses the active pointer. The data pointer select bit is located in LSB of AUX register (DPS).
The user switches between pointers by toggling the LSB of AUX register. All DPTR-related instructions use the currently selected
DPTR for any activity.
Mnemonic: DPL1
7
6
5
4
3
DPL1 [7:0]
2
1
Address: 84h
0
Reset
00h
4
3
DPH1 [7:0]
2
1
Address: 85h
0
Reset
00h
3
P2IIC
2
-
1
-
Address: 91h
0
Reset
DPS
00H
3
-
2
-
DPL1[7:0]: Data pointer Low 1
Mnemonic: DPH1
7
6
5
DPH1[7:0]: Data pointer High 1
Mnemonic: AUX
7
6
BRGS
-
5
P2SPI
4
P2UR
DPS: Data Pointer select register.
DPS = 1 is selected DPTR1.
4.7
Clock control register
Mnemonic: CKCON
7
6
5
ITS[2:0]
4
Address: 8Eh
1
0
Reset
CLKOUT[1:0]
10H
ITS[2:0]: Instruction timing select.
ITS [2:0]
Mode
000
1T mode
001
2T mode (default)
010
3T mode
011
4T mode
100
5T mode
101
6T mode
110
7T mode
111
8T mode
CLKOUT[1:0]: Clock output select.
CLKOUT[1:0]
Mode
00
GPIO(default)
01
Fosc
10
Fosc/2
11
Fosc/4
It can be used when the system clock is the internal RC oscillator.
Specifications subject to change without notice contact your sales representatives for the most recent information.
28
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
4.8
Interface control register
Mnemonic: IFCON
7
6
CDPR
5
-
4
-
3
-
2
-
1
-
Address: 8Fh
0
Reset
ISPE
00H
CDPR: Code protect (Read Only)
ISPE: ISP function enable bit
ISPE = 1, enable ISP function
ISPE = 0, disable ISP function
Specifications subject to change without notice contact your sales representatives for the most recent information.
29
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
5
GPIO
The SM39R16A2 has four I/O ports: Port 0, Port 1, Port 2, and Port 3. Ports 0, 1, 2 are 8-bit ports and Port 3 is a 2-bit port. These
are: quasi-bidirectional (standard 8051 port outputs), push-pull, open drain, and input-only. Two configuration registers for each port
select the output type for each port pin. All I/O port pins on the SM39R16A2 may be configured by software to one of four types on
a pin-by-pin basis, shown as below:
Mnemonic
Description
Direct
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
RESE
T
Bit 0
I/O port function register
P0M0
P0M1
P1M0
P1M1
P2M0
P2M1
P3M0
P3M1
Port 0 output mode 0
Port 0 output mode 1
Port 1 output mode 0
Port 1 output mode 1
Port 2 output mode 0
Port 2 output mode 1
Port 3 output mode 0
Port 3 output mode 1
PxM1.y
0
0
1
1
D2h
D3h
D4h
D5h
D6h
D7h
DAh
DBh
PxM0.y
0
1
0
1
P0M0 [7:0]
P0M1[7:0]
P1M0[7:0]
P1M1[7:0]
P2M0[7:0]
P2M1[7:0]
00H
00H
00H
00H
00H
00H
00H
00H
P3M0[1:0]
P3M1[1:0]
Port output mode
Quasi-bidirectional (standard 8051 port outputs) (pull-up)
Push-pull
Input only (high-impedance)
Open drain
The RESET Pin can define as General I/O P1.5 when user use Internal RESET.
The XTAL2 and XTAL1 can define as P3.0 and P3.1 by writer or ISP，when user use internal OSC as system clock；when user use
external OSC as system clock and input into XTAL1，Only XTAL2 can be defined as P3.0.
For general-purpose applications, every pin can be assigned to either high or low independently as given below:
Mnemonic
Description
Direct
Bit 7
Bit 6
Port 3
Port 2
Port 1
Port 0
Port 3
Port 2
Port 1
Port 0
B0h
A0h
90h
80h
P2.7
P1.7
P0.7
P2.6
P1.6
P0.6
Bit 5
Ports
P2.5
P1.5
P0.5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESET
P2.4
P1.4
P0.4
P2.3
P1.3
P0.3
P2.2
P1.2
P0.2
P3.1
P2.1
P1.1
P0.1
P3.0
P2.0
P1.0
P0.0
FFh
FFh
FFh
FFh
Specifications subject to change without notice contact your sales representatives for the most recent information.
30
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
Mnemonic: P0
7
6
P0.7
P0.6
5
P0.5
4
P0.4
3
P0.3
2
P0.2
1
P0.1
Address: 80h
0
Reset
P0.0
FFh
4
P1.4
3
P1.3
2
P1.2
1
P1.1
Address: 90h
0
Reset
P1.0
FFh
4
P2.4
3
P2.3
2
P2.2
1
P2.1
Address: A0h
0
Reset
P2.0
FFh
4
-
3
-
2
-
1
P3.1
Address: B0h
0
Reset
P3.0
FFh
P0.7~ 0: Port0 [7] ~ Port0[0]
Mnemonic: P1
7
6
P1.7
P1.6
5
P1.5
P1.7~ 0: Port1 [7] ~ Port1 [0]
Mnemonic: P2
7
6
P2.7
P2.6
5
P2.5
P2.7~ 0: Port2 [7] ~ Port2 [0]
Mnemonic: P3
7
6
-
5
-
P3.1~ 0: Por3 [1] ~ Port3 [0]
Specifications subject to change without notice contact your sales representatives for the most recent information.
31
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
6
Timer 0 and Timer 1
The SM39R16A2 has three 16-bit timer/counter registers: Timer 0, Timer 1 and Timer 2. All can be configured for counter or timer
operations.
In timer mode, the Timer 0 register or Timer 1 register is incremented every 1/12/96 machine cycles, which means that it counts up
after every 1/12/96 periods of the clk signal. It’s dependent on SFR(PFCON).
In counter mode, the register is incremented when the falling edge is observed at the corresponding input pin T0or T1. Since it takes
2 machine cycles to recognize a 1-to-0 event, the maximum input count rate is 1/2 of the oscillator frequency. There are no
restrictions on the duty cycle, however to ensure proper recognition of 0 or 1 state, an input should be stable for at least 1 machine
cycle.
Four operating modes can be selected for Timer 0 and Timer 1. Two Special Function registers (TMOD and TCON) are used to
select the appropriate mode.
Mnemonic
Description
TL0
TH0
TL1
TH1
Timer 0 , low byte
Timer 0 , high byte
Timer 1 , low byte
Timer 1 , high byte
Timer Mode
Control
Timer/Counter
Control
Peripheral
Frequency control
register
Direc
t
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESE
T
Timer 0 and 1
TMOD
TCON
PFCON
6.1
8Ah
8Ch
8Bh
8Dh
TL0[7:0]
TH0[7:0]
TL1[7:0]
TH1[7:0]
00H
00H
00H
00H
89h
GATE
C/T
M1
M0
GATE
C/T
M1
M0
00H
88h
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
00H
D9h
-
-
SRELPS[1:0]
T1PS[1:0]
T0PS[1:0]
00H
Timer/counter mode control register (TMOD)
Mnemonic: TMOD
7
6
5
GATE
C/T
M1
Timer 1
4
M0
3
GATE
2
1
C/T
M1
Timer 0
Address: 89h
0
Reset
M0
00h
GATE: If set, enables external gate control (pin INT0 or INT1 for Counter 0 or 1,
respectively). When INT0 or INT1 is high, and TRx bit is set (see TCON register), a
counter is incremented every falling edge on T0 or T1 input pin
C/T: Selects Timer or Counter operation. When set to 1, a counter operation is performed,
when cleared to 0, the corresponding register will function as a timer.
M[1:0]: Selects mode for Timer/Counter 0 or Timer/Counter 1.
M1
M0
Mode
Function
0
0
Mode0
13-bit counter/timer, with 5 lower bits in TL0 or
TL1 register and 8 bits in TH0 or TH1 register (for
Timer 0 and Timer 1, respectively). The 3 high
order bits of TL0 and TL1 are hold at zero.
0
1
Mode1
16-bit counter/timer.
1
0
Mode2
8 -bit auto-reload counter/timer. The reload value is
kept in TH0 or TH1, while TL0 or TL1 is
incremented every machine cycle. When TLx
overflows, a value from THx is copied to TLx.
1
1
Mode3
If Timer 1 M1 and M0 bits are set to 1, Timer 1
Specifications subject to change without notice contact your sales representatives for the most recent information.
32
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
stops. If Timer 0 M1 and M0 bits are set to 1, Timer
0 acts as two independent 8 bit timers / counters.
6.2
Timer/counter control register (TCON)
Mnemonic: TCON
7
6
TF1
TR1
5
TF0
4
TR0
3
IE1
2
IT1
1
IE0
Address: 88h
0
Reset
IT0
00h
TF1: Timer 1 overflow flag set by hardware when Timer 1 overflows. This flag can be
cleared by software and is automatically cleared when interrupt is processed.
TR1: Timer 1 Run control bit. If cleared, Timer 1 stops.
TF0: Timer 0 overflow flag set by hardware when Timer 0 overflows. This flag can be
cleared by software and is automatically cleared when interrupt is processed.
TR0: Timer 0 Run control bit. If cleared, Timer 0 stops.
IE1: Interrupt 1 edge flag. Set by hardware, when falling edge on external pin INT1 is
observed. Cleared when interrupt is processed.
IT1: Interrupt 1 type control bit. Selects falling edge or low level on input pin to cause
interrupt. IT1=1, interrupt 1 select falling edge trigger. IT1=0, interrupt1 select low
level trigger.
IE0: Interrupt 0 edge flag. Set by hardware, when falling edge on external pin INT0 is
observed. Cleared when interrupt is processed.
IT0: Interrupt 0 type control bit. Selects falling edge or low level on input pin to cause
interrupt. IT0=1, interrupt 0 select falling edge trigger. IT0=0, interrupt 0 select low
level trigger.
6.3
Peripheral Frequency control register：
Mnemonic: PFCON
7
6
5
4
SRELPS[1:0]
T1PS[1:0]: Timer1 Prescaler select
T1PS[1:0]
00
01
10
11
T0PS[1:0]: Timer0 Prescaler select
T0PS[1:0]
00
01
10
11
3
2
T1PS[1:0]
Address: D9h
1
0
Reset
T0PS[1:0]
00H
Prescaler
Fosc/12
Fosc
Fosc/96
reserved
Prescaler
Fosc/12
Fosc
Fosc/96
reserved
Specifications subject to change without notice contact your sales representatives for the most recent information.
33
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
6.4
Mode 0 (13-bit Counter/Timer)：
÷12
OSC
00
01
÷96
10
C/T = 1
T1PS[1:0]
T1 pin
TR1
GATE1
ET1
C/T = 0
TL1
TH1
(5 Bits) (8 Bits)
EA
0
1
1
Control
If not higher priority
Interrupt Processing
AND
NOT
TF1
0
Jump
001BH
OR
INT1 pin
D0D1D2D3D4
D5D6D7
D0D1D2D3D4D5D6D7
TL1
6.5
TH1
Mode 1 (16-bit Counter/Timer)：
÷12
OSC
00
01
÷96
ET1
C/T = 0
10
C/T = 1
T1PS[1:0]
T1 pin
TR1
GATE1
TF1
TL1
TH1
(8 Bits) (8 Bits)
0
0
1
1
Control
If not higher priority
Interrupt Processing
AND
NOT
TF1
EA
Jump
001BH
OR
INT1 pin
D0D1D2D3D4D5D6D7
D0D1D2D3D4D5D6D7
TL1
TH1
TF1
Specifications subject to change without notice contact your sales representatives for the most recent information.
34
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
6.6
Mode 2 (8-bit auto-reload Counter/Timer)：
÷12
OSC
00
01
÷96
10
C/T = 1
T1PS[1:0]
T1 pin
TR1
GATE1
INT1 pin
6.7
ET1
C/T = 0
TL1
(8 Bits)
OR
0
0
1
1
Control
Auto
Reload
AND
NOT
TF1
EA
TH1
(8 Bits)
If not higher priority
Interrupt Processing
Jump
001BH
Mode 3 (Timer 0 acts as two independent 8 bit Timers / Counters)：
Specifications subject to change without notice contact your sales representatives for the most recent information.
35
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
7
Timer 2 and Capture Compare Unit
Timer 2 is not only a 16-bit timer, also a 4-channel unit with compare, capture and reload functions. It is very similar to the
programmable counter array (PCA) in some other MCUs except pulse width modulation (PWM).
Mnemonic
Description
T2CON
Timer 2 control
Compare/Capture
Control
Compare/Capture
Enable register
Compare/Capture
Enable 2 register
Timer 2, low byte
Timer 2, high byte
Compare/Reload/C
apture register, low
byte
Compare/Reload/C
apture register, high
byte
Compare/Capture
register 1, low byte
Compare/Capture
register 1, high byte
Compare/Capture
register 2, low byte
Compare/Capture
register 2, high byte
Compare/Capture
register 3, low byte
Compare/Capture
register 3, high byte
CCCON
CCEN
CCEN2
TL2
TH2
CRCL
CRCH
CCL1
CCH1
CCL2
CCH2
CCL3
CCH3
Direc
t
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Timer 2 and Capture Compare Unit
T2PS[2:0]
T2R[1:0]
C8h
CCI2
CCI1
CCI0
Bit 2
Bit 1
-
CCF3
Bit 0
T2I[1:0]
CCI3
C1h
-
COCAM1[2:0]
-
COCAM0[2:0]
00H
D1h
-
COCAM3[2:0]
-
COCAM2[2:0]
00H
TL2[7:0]
TH2[7:0]
CAh
CRCL[7:0]
CBh
CRCH[7:0]
C2h
CCL1[7:0]
C3h
CCH1[7:0]
C4h
CCL2[7:0]
C5h
CCH2[7:0]
C6h
CCL3[7:0]
C7h
CCH3[7:0]
CCF1
CCF0
00H
C9h
CCh
CDh
CCF2
RESE
T
00H
00H
00H
00H
00H
Mnemonic: T2CON
7
6
T2PS[2:0]
5
4
3
T2R[1:0]
2
-
1
00H
00H
00H
00H
00H
00H
Address: C8h
0
Reset
T2I[1:0]
00H
T2PS[2:0]: Prescaler select bit:
T2PS = 000 – timer 2 is clocked with the oscillator frequency.
T2PS = 001 – timer 2 is clocked with 1/2 of the oscillator frequency.
T2PS = 010 – timer 2 is clocked with 1/4 of the oscillator frequency.
T2PS = 011 – timer 2 is clocked with 1/6 of the oscillator frequency.
T2PS = 100 – timer 2 is clocked with 1/8 of the oscillator frequency.
T2PS = 101 – timer 2 is clocked with 1/12 of the oscillator frequency.
T2PS = 110 – timer 2 is clocked with 1/24 of the oscillator frequency.
T2R[1:0]: Timer 2 reload mode selection
T2R[1:0] = 0X – Reload disabled
T2R[1:0] = 10 – Mode 0: Auto Reload
T2R[1:0] = 11 – Mode 1: T2EX Falling Edge Reload
T2I[1:0]: Timer 2 input selection
T2I[1:0] = 00 – Timer 2 stop
T2I[1:0] = 01 – Input frequency from prescaler (T2PS[2:0])
Specifications subject to change without notice contact your sales representatives for the most recent information.
36
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
T2I[1:0] = 10 – Timer 2 is incremented by external signal at pin T2
T2I[1:0] = 11 – internal clock input is gated to the Timer 2
Mnemonic: CCCON
7
6
5
CCI3
CCI2
CCI1
4
CCI0
3
CCF3
2
CCF2
1
CCF1
Address: C9h
0
Reset
CCF0
00H
CCI3: Compare/Capture 3 interrupt control bit.
“1” is enable.
CCI2: Compare/Capture 2 interrupt control bit.
“1” is enable.
CCI1: Compare/Capture 1 interrupt control bit.
“1” is enable.
CCI0: Compare/Capture 0 interrupt control bit.
“1” is enable.
CCF3: Compare/Capture 3 flag set by hardware. This flag can be cleared by software.
CCF2: Compare/Capture 2 flag set by hardware. This flag can be cleared by software.
CCF1: Compare/Capture 1 flag set by hardware. This flag can be cleared by software.
CCF0: Compare/Capture 0 flag set by hardware. This flag can be cleared by software.
Compare/Capture interrupt share T2 interrupt vector.
Mnemonic: CCEN
7
6
5
4
COCAM1[2:0]
3
-
2
Address: C1h
1
0
Reset
COCAM0[2:0]
00H
COCAM1[2:0] 000: Compare/Capture disable
001: Compare enable but no output on Pin
010: Compare mode 0
011: Compare mode 1
100: Capture on rising edge at pin CC1
101: Capture on falling edge at pin CC1
110: Capture on both rising and falling edge at pin CC1
111: Capture on write operation into register CC1
COCAM0[2:0] 000: Compare/Capture disable
001: Compare enable but no output on Pin
010: Compare mode 0
011: Compare mode 1
100: Capture on rising edge at pin CC0
101: Capture on falling edge at pin CC0
110: Capture on both rising and falling edge at pin CC0
111: Capture on write operation into register CC0
Mnemonic: CCEN2
7
6
5
4
COCAM3[2:0]
3
-
2
Address: D1h
1
0
Reset
COCAM2[2:0]
00H
COCAM3[2:0] 000: Compare/Capture disable
001: Compare enable but no output on Pin
010: Compare mode 0
011: Compare mode 1
100: Capture on rising edge at pin CC3
101: Capture on falling edge at pin CC3
110: Capture on both rising and falling edge at pin CC3
111: Capture on write operation into register CC3
COCAM2[2:0] 000: Compare/Capture disable
001: Compare enable but no output on Pin
Specifications subject to change without notice contact your sales representatives for the most recent information.
37
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
010: Compare mode 0
011: Compare mode 1
100: Capture on rising edge at pin CC2
101: Capture on falling edge at pin CC2
110: Capture on both rising and falling edge at pin CC2
111: Capture on write operation into register CC2
7.1
Timer 2 function
Timer 2 can operate as timer, event counter, or gated timer as explained later.
7.1.1 Timer mode
In this mode Timer 2 can by incremented in various frequency that depending on the prescaler. The prescaler is selected by bit
T2PS[2:0] in register T2CON.
Fig. 7-1: Timer mode and Reload mode function
7.1.2 Event counter mode
In this mode, the timer is incremented when external signal T2 change value from 1 to 0. The T2 input is sampled in every cycle.
Timer 2 is incremented in the cycle following the one in which the transition was detected.
Fig. 7-2: Event counter mode function
Specifications subject to change without notice contact your sales representatives for the most recent information.
38
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
7.1.3 Gated timer mode
In this mode, the internal clock which incremented timer 2 is gated by external signal T2.
Fig. 7-3: Gated timer mode function
7.1.4 Reload of Timer 2
Reload (16-bit reload from the crc register) can be executed in the following two modes:
Mode 0: Reload signal is generate by a Timer 2 overflows - auto reload
Mode 1: Reload signal is generate by a negative transition at the corresponding input pin T2EX.
7.2
Compare function
In the four independent comparators, the value stored in any compare/capture register is compared with the contents of the timer
register. The compare modes 0 and 1 are selected by bits C0CAMx . In both compare modes, the results of comparison arrives at
Port 1 within the same machine cycle in which the internal compare signal is activated.
7.2.1 Compare Mode 0
In mode 0, when the value in Timer 2 equals the value of the compare register, the output signal changes from low to high. It goes
back to a low level on timer overflow. In this mode, writing to the port will have no effect, because the input line from the internal
bus and the write-to-latch line are disconnected. The following figure illustrates the function of compare mode 0.
Fig. 7-4: Compare mode 0 function
Specifications subject to change without notice contact your sales representatives for the most recent information.
39
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
7.2.2 Compare Mode 1
In compare mode 1, the transition of the output signal can be determined by software. A timer 2 overflow causes no output change.
In this mode, both transitions of a signal can be controlled. Fig. 7-5 shows a functional diagram of a register/port configuration in
compare Mode 1. In compare Mode 1, the value is written first to the “Shadow Register”, when compare signal is active, this value
is transferred to the output register.
Fig. 7-2: Compare mode 1 function
Fig. 7-5: Compare mode 1 function
Specifications subject to change without notice contact your sales representatives for the most recent information.
40
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
7.3
Capture function
Actual timer/counter contents can be saved into registers CCx or CRC upon an external event (mode 0) or a software write operation
(mode 1).
7.3.1 Capture Mode 0 (by Hardware)
In mode 0, value capture of Timer 2 is executed when:
(a) Rising edge on input CC0-CC3
(b) Falling edge on input CC0-CC3
(c) Both rising and falling edge on input CC0-CC3
The contents of Timer 2 will be latched into the appropriate capture register.
Fig. 7-6: Capture mode 0 function
7.3.2 Capture Mode 1(by Software)
In mode 1, value capture of timer 2 is caused by writing any value into the low-order byte of the dedicated capture register. The
value written to the capture register is irrelevant to this function. The contents of Timer 2 will be latched into the appropriate capture
register.
Fig. 7-7: Capture mode 1 function
Specifications subject to change without notice contact your sales representatives for the most recent information.
41
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
8
Serial interface
The serial buffer consists of two separate registers, a transmit buffer and a receive buffer.
Writing data to the Special Function Register SBUF sets this data in serial output buffer and starts the transmission. Reading from
the SBUF reads data from the serial receive buffer. The serial port can simultaneously transmit and receive data. It can also buffer 1
byte at receive, which prevents the receive data from being lost if the CPU reads the first byte before transmission of the second byte
is completed.
Mnemonic
PCON
AUX
SCON
SRELL
SRELH
SBUF
PFCON
Description
Power control
Auxiliary register
Serial Port control
register
Serial Port reload
register low byte
Serial Port reload
register high byte
Serial Port data
buffer
Peripheral
Frequency control
register
Direc
t
Bit 7
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESE
T
87H
91h
SMOD
BRGS
Serial interface 0 and 1
P2SPI
P2UR
P2IIC
-
STOP
-
IDLE
DPS
00H
00H
98H
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
00H
AAH
SREL.
7
SREL.
6
SREL.
5
SREL.
4
SREL.
3
SREL.
2
-
-
-
-
SREL.
1
SREL.
9
SREL.
0
SREL.
8
BAH
-
-
Bit 6
Bit 5
99H
D9h
Mnemonic: AUX
7
6
BRGS
SBUF[7:0]
-
-
5
P2SPI
4
P2UR
SRELPS[1:0]
3
P2IIC
00H
00H
00H
T1PS[1:0]
T0PS[1:0]
2
-
1
-
Address: 91h
0
Reset
DPS
00H
2
RB8
1
TI
Address: 98h
0
Reset
RI
00H
00H
BRGS: Baud rate generator.
BRGS = 0 - baud rate generator from Timer 1.
BRGS = 1 - baud rate generator by SREL.
P2UR: P2UR = 0 – Serial interface function on P1.
P2UR = 1 – Serial interface function on P2.
Mnemonic: SCON
7
6
SM0
SM1
5
SM2
4
REN
3
TB8
SM0,SM1: Serial Port 0 mode selection.
SM0
SM1
Mode
0
0
0
0
1
1
1
0
2
1
1
3
The 4 modes in UART, Mode 0 ~ 3, are explained later.
SM2: Enables multiprocessor communication feature
REN: If set, enables serial reception. Cleared by software to disable reception.
TB8: The 9th transmitted data bit in modes 2 and 3. Set or cleared by the CPU depending on the
function it performs such as parity check, multiprocessor communication etc.
RB8: In modes 2 and 3, it is the 9th data bit received. In mode 1, if SM2 is 0, RB8 is the stop bit. In
mode 0, this bit is not used. Must be cleared by software.
TI: Transmit interrupt flag, set by hardware after completion of a serial transfer. Must be cleared by
software.
Specifications subject to change without notice contact your sales representatives for the most recent information.
42
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
RI: Receive interrupt flag, set by hardware after completion of a serial reception. Must be cleared by
software.
8.1
Serial interface
The Serial Interface can operate in the following 4 modes:
SM0
0
0
1
1
SM1
0
1
0
1
Mode
0
1
2
3
Description
Shift register
8-bit UART
9-bit UART
9-bit UART
Board Rate
Fosc/12
Variable
Fosc/32 or Fosc/64
Variable
Here Fosc is the crystal or oscillator frequency.
8.1.1 Mode 0
Pin RXD serves as input and output. TXD outputs the shift clock. 8 bits are transmitted with LSB first. The baud
rate is fixed at 1/12 of the crystal frequency. Reception is initialized in Mode 0 by setting the flags in SCON as follows:
RI = 0 and REN = 1. In other modes, a start bit when REN = 1 starts receiving serial data.
Fig. 8-1: Transmit mode 0
Fig. 8-2: Receive mode 0
8.1.2 Mode 1
Pin RXD serves as input, and TXD serves as serial output. No external shift clock is used, 10 bits are transmitted: a
start bit (always 0), 8 data bits (LSB first), and a stop bit (always 1). On receive, a start bit synchronizes the transmission,
8 data bits are available by reading SBUF, and stop bit sets the flag RB8 in the Special Function Register SCON. In mode
1 either internal baud rate generator or timer 1 can be use to specify baud rate.
Specifications subject to change without notice contact your sales representatives for the most recent information.
43
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
Fig. 8-3: Transmit mode 1
Fig. 8-4: Receive mode 1
8.1.3 Mode 2
This mode is similar to Mode 1, with two differences. The baud rate is fixed at 1/32 (SMOD=1) or 1/64(SMOD=0)
of oscillator frequency and 11 bits are transmitted or received: a start bit (0), 8 data bits (LSB first), a programmable 9th
bit, and a stop bit (1). The 9th bit can be used to control the parity of the serial interface: at transmission, bit TB8 in SCON
is output as the 9th bit, and at receive, the 9th bit affects RB8 in Special Function Register SCON.
8.1.4 Mode 3
The only difference between Mode 2 and Mode 3 is that in Mode 3 either internal baud rate generator or timer 1 can
be use to specify baud rate.
Fig. 8-5: Transmit modes 2 and 3
Fig. 8-6: Receive modes 2 and 3
Specifications subject to change without notice contact your sales representatives for the most recent information.
44
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
8.2
Multiprocessor Communication of Serial Interface
The feature of receiving 9 bits in Modes 2 and 3 of Serial Interface can be used for multiprocessor communication.
In this case, the slave processors have bit SM2 in SCON set to 1. When the master processor outputs slave’s address, it
sets the 9th bit to 1, causing a serial port receive interrupt in all the slaves. The slave processors compare the received byte
with their network address. If there is a match, the addressed slave will clear SM2 and receive the rest of the message,
while other slaves will leave SM2 bit unaffected and ignore this message. After addressing the slave, the host will output
the rest of the message with the 9th bit set to 0, so no serial port receive interrupt will be generated in unselected slaves.
8.3
Peripheral Frequency control register
Mnemonic: PFCON
7
6
5
4
SRELPS[1:0]
SRELPS[1:0]: SREL Prescaler select
SRELPS[1:0]
00
01
10
11
T1PS[1:0]: Timer1 Prescaler select
T1PS[1:0]
00
01
10
11
3
2
T1PS[1:0]
Address: D9h
1
0
Reset
T0PS[1:0]
00H
Prescaler
Fosc/64
Fosc /32
Fosc /16
Fosc /8
Prescaler
Fosc/12
Fosc
Fosc/96
reserved
Specifications subject to change without notice contact your sales representatives for the most recent information.
45
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
8.4
Baud rate generator
8.4.1 Serial interface modes 1 and 3
8.4.1.1 When BRGS = 0 (in Special Function Register AUX).
8.4.1.1.1 T1PS[1:0] is 00
Baud Rate =
2SMOD × Fosc
32 × 12 × (256 − TH1)
8.4.1.1.2 T1PS[1:0] is 01
2SMOD × Fosc
Baud Rate =
32 × (256 − TH1)
8.4.1.1.3 T1PS[1:0] is 10
Baud Rate =
2SMOD × Fosc
32 × 96 × (256 − TH1)
8.4.1.2 When BRGS = 1 (in Special Function Register AUX).
8.4.1.2.1 SRELPS[1:0] is 00
2 SMOD × Fosc
Baud Rate =
64 × 210 − SREL
)
8.4.1.2.2 SRELPS[1:0] is 01
2 SMOD × Fosc
Baud Rate =
32 × 210 − SREL
)
(
(
8.4.1.2.3 SRELPS[1:0] is 10
2 SMOD × Fosc
Baud Rate =
16 × 210 − SREL
(
8.4.1.2.4 SRELPS[1:0] is 11
2 SMOD × Fosc
Baud Rate =
8 × 210 − SREL
(
)
)
Specifications subject to change without notice contact your sales representatives for the most recent information.
46
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
9
Watchdog timer
The Watch Dog Timer (WDT) is an 8-bit free-running counter that generate reset signal if the counter overflows. The WDT is useful
for systems which are susceptible to noise, power glitches, or electronics discharge which causing software dead loop or runaway.
The WDT function can help user software recover from abnormal software condition. The WDT is different from Timer0, Timer1
and Timer2 of general 8052. To prevent a WDT reset can be done by software periodically clearing the WDT counter. User should
check WDTF bit of WDTC register whenever un-predicted reset happened. After an external reset the watchdog timer is disabled
and all registers are set to zeros.
The watchdog timer has a free running on-chip RC oscillator (250 KHz). The WDT will keep on running even after the system clock
has been turned off (for example, in sleep mode). During normal operation or sleep mode, a WDT time-out (if enabled) will cause
the MCU to reset. The WDT can be enabled or disabled any time during the normal mode. Please refer the WDTE bit of WDTC
register. The default WDT time-out period is approximately 16.38ms (WDTM [3:0] = 0100b).
The WDT has selectable divider input for the time base source clock. To select the divider input, the setting of bit3 ~ bit0 (WDTM
[3:0]) of Watch Dog Timer Control Register (WDTC) should be set accordingly.
250KHz
2WDTM
256
Watchdog reset time =
WDTCLK
WDTCLK =
WDTM [3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Table 9.1 WDT time-out period
Divider
(250 KHz RC oscillator in)
1
2
4
8
16
32
64
128
256
512
1024
2048
4096
8192
16384
32768
Time period @ 250KHz
1.02ms
2.05ms
4.10ms
8.19ms
16.38ms (default)
32.77ms
65.54ms
131.07ms
262.14ms
524.29ms
1.05s
2.10s
4.19s
8.39s
16.78s
33.55s
When MCU is reset, the MCU will be read WDTEN control bit status. When WDTEN bit is set to 1, the watchdog function will be
disabled no matter what the WDTE bit status is. When WDTEN bit is clear to 0, the watchdog function will be enabled if WDTE bit
is set to 1 by program. User can to set WDTEN on the writer or ISP.
The program can enable the WDT function by programming 1 to the WDTE bit premise that WDTEN control bit is clear to 0. After
WDTE set to 1, the 8 bit-counter starts to count with the selected time base source clock which set by WDTM [3:0]. It will generate
a reset signal when overflows. The WDTE bit will be cleared to 0 automatically when MCU been reset, either hardware reset or
WDT reset.
Once the watchdog is started it cannot be stopped. User can refreshed the watchdog timer to zero by writing 0x55 to Watch Dog
Timer refresh Key (WDTK) register. This will clear the content of the 8-bit counter and let the counter re-start to count from the
beginning. The watchdog timer must be refreshed regularly to prevent reset request signal from becoming active.
Specifications subject to change without notice contact your sales representatives for the most recent information.
47
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
When Watchdog timer is overflow, the WDTF flag will set to one and automatically reset MCU. The WDTF flag can be clear by
software or external reset or power on reset.
1
2WDTM
Fig. 9-1: Watchdog timer block diagram
Mnemonic
Direc
t
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESE
T
Watchdog Timer
TAKEY
WDTC
WDTK
RSTS
Time Access Key
register
Watchdog timer
control register
Watchdog timer
refresh key
Reset status register
F7h
TAKEY [7:0]
B6h
-
-
WDTE
-
B7h
WDTM [3:0]
04H
WDTK[7:0]
A1h
Mnemonic: TAKEY
7
6
00H
-
5
-
4
3
TAKEY [7:0]
-
PDRF
2
WDTF
1
00H
SWRF
LVRF
PORF
00H
Address: F7h
0
Reset
00H
Watchdog timer control register (WDTC) is read-only by default; software must write three specific values
55h, AAh and 5Ah sequentially to the TAKEY register to enable the WDTC write attribute. That is:
MOV TAKEY, #55h
MOV TAKEY, #0AAh
MOV TAKEY, #5Ah
Specifications subject to change without notice contact your sales representatives for the most recent information.
48
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
Mnemonic: WDTC
7
6
5
WDTE
4
-
3
2
1
WDTM [3:0]
Address: B6h
0
Reset
04H
WDTE: Control bit used to enable Watchdog timer.
The WDTE bit can be used only if WDTEN is "0". If the WDTEN bit is "0", then WDT can be
disabled / enabled by the WDTE bit.
0: Disable WDT.
1: Enable WDT.
The WDTE bit is not used if WDTEN is "1". That is, if the WDTEN bit is "1", WDT is always
disabled no matter what the WDTE bit status is. The WDTE bit can be read and written.
WDTM [3:0]: WDT clock source divider bit. Please see table 9.1 to reference the WDT time-out period.
Mnemonic: RSTS
7
6
-
5
-
4
PDRF
3
WDTF
2
SWRF
1
LVRF
Address: A1h
0
Reset
PORF
00h
WDTF: Watchdog timer reset flag. When MCU is reset by watchdog, WDTF flag will be set to one by
hardware. This flag clear by software
Mnemonic: WDTK
7
6
5
4
3
WDTK[7:0]
2
1
Address: B7h
0
Reset
00h
WDTK: Watchdog timer refresh key.
A programmer must write 0x55 into WDTK register, and then the watchdog timer will
be cleared to zero.
For example, if enable WDT and select time-out reset period is 262.14ms.
First, programming the information block OP3 bit7 WDTEN to “0”.
Secondly,
MOV TAKEY, #55h
MOV TAKEY, #0AAh
MOV TAKEY, #5Ah
; enable WDTC write attribute.
MOV WDTC, #28h
; Set WDTM [3:0] = 1000b. Set WDTE =1 to enable WDT
; function.
.
.
MOV WDTK, #55h
; Clear WDT timer to 0.
Specifications subject to change without notice contact your sales representatives for the most recent information.
49
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
10 Interrupt
The SM39R16A2 provides 13 interrupt sources with four priority levels. Each source has its own request flag(s) located in a special
function register. Each interrupt requested by the corresponding flag could individually be enabled or disabled by the enable bits in
SFR’s IEN0, IEN1, and IEN2.
When the interrupt occurs, the engine will vector to the predetermined address as shown in Table 10.1. Once interrupt service has
begun, it can be interrupted only by a higher priority interrupt. The interrupt service is terminated by a return from instruction RETI.
When an RETI is performed, the processor will return to the instruction that would have been next when interrupt occurred.
When the interrupt condition occurs, the processor will also indicate this by setting a flag bit. This bit is set regardless of whether the
interrupt is enabled or disabled. Each interrupt flag is sampled once per machine cycle, and then samples are polled by hardware. If
the sample indicates a pending interrupt when the interrupt is enabled, then interrupt request flag is set. On the next instruction cycle
the interrupt will be acknowledged by hardware forcing an LCALL to appropriate vector address.
Interrupt response will require a varying amount of time depending on the state of microcontroller when the interrupt occurs. If
microcontroller is performing an interrupt service with equal or greater priority, the new interrupt will not be invoked. In other cases,
the response time depends on current instruction. The fastest possible response to an interrupt is 7 machine cycles. This includes one
machine cycle for detecting the interrupt and six cycles for perform the LCALL.
Table 10-1: Interrupt vectors
IE0 – External interrupt 0
0003h
Interrupt Number
*(use Keil C Tool)
0
TF0 – Timer 0 interrupt
000Bh
1
IE1 – External interrupt 1
0013h
2
TF1 – Timer 1 interrupt
RI/TI – Serial channel interrupt
TF2/EXF2 – Timer 2 interrupt
001Bh
0023h
002Bh
3
4
5
Interrupt Request Flags
Interrupt Vector Address
PWMIF – PWM interrupt
0043h
8
SPIIF – SPI interrupt
004Bh
9
ADCIF – A/D converter interrupt
0053h
10
KBIIF – keyboard Interface interrupt
005Bh
11
LVIIF – Low Voltage Interrupt
0063h
12
IICIF – IIC interrupt
006Bh
13
Comparator interrupt
0093h
18
*See Keil C about C51 User’s Guide about Interrupt Function description
Specifications subject to change without notice contact your sales representatives for the most recent information.
50
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
Mnemonic
Description
Direct
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESE
T
Interrupt
IEN0
IEN1
IEN2
IRCON
IRCON2
IP0
IP1
Interrupt Enable 0
register
Interrupt Enable 1
register
Interrupt Enable 2
register
Interrupt request
register
Interrupt request
register 2
Interrupt priority
level 0
Interrupt priority
level 1
A8H
EA
-
ET2
ES
ET1
EX1
ET0
EX0
00H
B8H
EXEN2
-
IEIIC
IELVI
IEKBI
IEADC
IESPI
IEPWM
00H
9AH
-
-
-
-
-
ECmpI
-
-
00H
C0H
EXF2
TF2
IICIF
LVIIF
KBIIF
ADCIF
SPIIF
PWMIF
00H
97H
-
-
-
-
-
CmpIF
-
-
00H
A9H
-
-
IP0.5
IP0.4
IP0.3
IP0.2
IP0.1
IP0.0
00H
B9H
-
-
IP1.5
IP1.4
IP1.3
IP1.2
IP1.1
IP1.0
00H
Interrupt Enable 0 register (IEN0)
Mnemonic: IEN0
7
6
EA
-
5
ET2
4
ES
3
ET1
2
EX1
1
ET0
Address: A8h
0
Reset
EX0
00h
EA: EA=0 – Disable all interrupt.
EA=1 – Enable all interrupt.
ET2: ET2=0 – Disable Timer 2 overflow or external reload interrupt.
ET2=1 – Enable Timer 2 overflow or external reload interrupt.
ES: ES=0 – Disable Serial channel interrupt.
ES=1 – Enable Serial channel interrupt.
ET1: ET1=0 – Disable Timer 1 overflow interrupt.
ET1=1 – Enable Timer 1 overflow interrupt.
EX1: EX1=0 – Disable external interrupt 1.
EX1=1 – Enable external interrupt 1.
ET0: ET0=0 – Disable Timer 0 overflow interrupt.
ET0=1 – Enable Timer 0 overflow interrupt.
EX0: EX0=0 – Disable external interrupt 0.
EX0=1 – Enable external interrupt 0.
Interrupt Enable 1 register (IEN1)
Mnemonic: IEN1
7
6
EXEN2
-
5
IEIIC
4
IELVI
3
IEKBI
2
IEADC
1
IESPI
Address: B8h
0
Reset
IEPWM
00H
EXEN2: Timer 2 reload interrupt enable.
EXEN2 = 0 – Disable Timer 2 external reload interrupt.
EXEN2 = 1 – Enable Timer 2 external reload interrupt.
IEIIC: IIC interrupt enable.
IEIICS = 0 – Disable IIC interrupt.
IEIICS = 1 – Enable IIC interrupt.
IELVI: LVI interrupt enable.
IELVI = 0 – Disable LVI interrupt.
IELVI = 1 – Enable LVI interrupt.
Specifications subject to change without notice contact your sales representatives for the most recent information.
51
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
IEKBI: KBI interrupt enable.
IEKBI = 0 – Disable KBI interrupt.
IEKBI = 1 – Enable KBI interrupt.
IEADC: A/D converter interrupt enable
IEADC = 0 – Disable ADC interrupt.
IEADC = 1 – Enable ADC interrupt.
IESPI: SPI interrupt enable.
IESPI = 0 – Disable SPI interrupt.
IESPI = 1 – Enable SPI interrupt.
IEPWM: PWM interrupt enable.
IEPWM = 0 – Disable PWM interrupt.
IEPWM = 1 – Enable PWM interrupt.
Interrupt Enable 2 register (IEN2)
Mnemonic: IEN2
7
6
-
5
-
4
-
3
-
2
ECmpI
Address: 9Ah
0
Reset
00H
1
-
ECmpI Enable Comparator interrupt(include comparator_0 and comparator_1)
Interrupt request register (IRCON)
Mnemonic: IRCON
7
6
5
EXF2
TF2
IICIF
4
LVIIF
3
KBIIF
2
ADCIF
1
SPIIF
Address: C0h
0
Reset
PWMIF
00H
EXF2: Timer 2 external reload flag. Must be cleared by software.
TF2: Timer 2 overflow flag. Must be cleared by software.
IICIF: IIC interrupt flag.
LVIIF: LVI interrupt flag.
KBIIF: KBI interrupt flag.
ADCIF: A/D converter end interrupt flag.
SPIIF: SPI interrupt flag.
PWMIF: PWM interrupt flag. Must be cleared by software.
Interrupt request register 2 (IRCON2)
Mnemonic:IRCON2
7
6
-
5
-
4
-
3
-
2
CmpIF
1
-
Address: 97h
0
Reset
00H
CmpIF Comparator interrupt flag
HW will clear this flag automatically when enter interrupt vector.
SW can clear this flag also.(in case analog comparator INT disable)
Specifications subject to change without notice contact your sales representatives for the most recent information.
52
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
10.1 Priority level structure
All interrupt sources are combined in groups:
Table 10-2: Priority level groups
Groups
Comparator interrupt
-
External interrupt 0
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
Serial channel interrupt
Timer 2 interrupt
PWM interrupt
SPI interrupt
ADC interrupt
KBI interrupt
LVI interrupt
IIC interrupt
Each group of interrupt sources can be programmed individually to one of four priority levels by setting or clearing one bit in the
special function register ip0 and one in ip1. If requests of the same priority level will be received simultaneously, an internal polling
sequence determines which request is serviced first.
Mnemonic: IP0
7
6
-
5
IP0.5
4
IP0.4
3
IP0.3
2
IP0.2
1
IP0.1
Address: A9h
0
Reset
IP0.0
00h
Mnemonic: IP1
7
6
-
5
IP1.5
4
IP1.4
3
IP1.3
2
IP1.2
1
IP1.1
Address: B9h
0
Reset
IP1.0
00h
IP1.x
0
0
1
1
Bit
IP1.0, IP0.0
IP1.1, IP0.1
IP1.2, IP0.2
IP1.3, IP0.3
IP1.4, IP0.4
IP1.5, IP0.5
Table 10-3: Priority levels
IP0.x
Priority Level
0
1
0
1
Level0 (lowest)
Level1
Level2
Level3 (highest)
Table 10-4: Groups of priority
Group
External interrupt 0
Timer 0 interrupt
External interrupt 1
Comparator interrupt
Timer 1 interrupt
Serial channel 0 interrupt
Timer 2 interrupt
-
PWM interrupt
SPI interrupt
ADC interrupt
KBI interrupt
LVI interrupt
IIC interrupt
Specifications subject to change without notice contact your sales representatives for the most recent information.
53
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
Table 10-5: Polling sequence
Interrupt source
External interrupt 0
PWM interrupt
Timer 0 interrupt
Polling sequence
SPI interrupt
External interrupt 1
Comparator interrupt
ADC interrupt
Timer 1 interrupt
KBI interrupt
Serial channel 0 interrupt
Sequence
LVI interrupt
Timer 2 interrupt
IIC interrupt
Specifications subject to change without notice contact your sales representatives for the most recent information.
54
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
11 Power Management Unit
Power management unit serves two power management modes, IDLE and STOP, for the users to do power saving function.
Mnemonic: PCON
7
6
SMOD
-
5
-
4
-
3
-
2
-
1
STOP
Address: 87h
0
Reset
IDLE
00h
STOP: Stop mode control bit. Setting this bit turning on the Stop Mode.
Stop bit is always read as 0
IDLE: Idle mode control bit. Setting this bit turning on the Idle Mode.
Idle bit is always read as 0
11.1 Idle mode
Setting the IDLE bit of PCON register invokes the IDLE mode. The IDLE mode leaves internal clocks and peripherals running.
Power consumption drops because the CPU is not active. The CPU can exit the IDLE state with any interrupts or a reset.
11.2 Stop mode
Setting the STOP bit of PCON register invokes the STOP mode. All internal clocking in this mode is turn off. The CPU will exit this
state from a no-clocked interrupt (external INT0/1 and LVI) or a reset (WDT and LVR) condition. Internally generated interrupts
(timer, serial port ...) have no effect on stop mode since they require clocking activity.
Specifications subject to change without notice contact your sales representatives for the most recent information.
55
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
12 Pulse Width Modulation (PWM)
SM39R16A2 provides two-channel PWM outputs.
The interrupt vector is 43h.
Mnemonic
Description
Direc
t
Bit 7
Bit 6
Bit 5
Bit 1
Bit 0
RESE
T
Bit 4
Bit 3
Bit 2
-
-
-
PWM1E PWM0E
N
N
00H
-
-
-
PWMD0[9:8]
00H
PWM
PWMC
PWMD0H
PWMD0L
PWMD1H
PWMD1L
PWMMDH
PWMMDL
PWM Control
register
PWM 0 Data
register high byte
PWM 0 Data
register low byte
PWM 1 Data
register high byte
PWM 1 Data
register low byte
PWM Max Data
register high byte
PWM Max Data
register low byte
B5h
BCh
PWMCS[2:0]
PWMP0
-
-
BDh
BEh
PWMD0[7:0]
PWMP1
-
-
-
BFh
-
PWMD1[9:8]
PWMD1[7:0]
CEh
-
-
-
-
CFh
Mnemonic: PWMC
7
6
PWMCS[2:0]
-
00H
-
00H
-
PWMMD[9:8]
PWMMD[7:0]
5
4
-
3
-
2
-
1
PWM1EN
00H
00H
FFH
Address: B5h
0
Reset
PWM0EN
00H
PWMCS[2:0]: PWM clock select.
PWMCS [2:0]
Mode
000
Fosc
001
Fosc/2
010
Fosc/4
011
Fosc/6
100
Fosc/8
101
Fosc/12
110
Timer 0 overflow
111
Timer 0 external input (P1.2/T0)
PWM1EN: PWM channel 1 enable control bit.
PWM1EN = 1 – PWM channel 1 enable.
PWM1EN = 0 – PWM channel 1 disable.
PWM0EN: PWM 0 enable control bit.
PWM0EN = 1 – PWM channel 0 enable.
PWM0EN = 0 – PWM channel 0 disable.
Mnemonic: PWMD0H
7
6
5
PWMP0
Mnemonic: PWMD0L
7
6
5
4
-
3
-
4
3
PWMD0[7:0]
2
2
Address: BCh
1
0
Reset
PWMD0[9:8]
00H
1
Address: BDh
0
Reset
00H
PWMP0: PWM channel 0 idle polarity select.
“0” – PWM channel 0 will idle low.
“1” – PWM channel 0 will idle high.
Specifications subject to change without notice contact your sales representatives for the most recent information.
56
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
PWMD0[9:0]: PWM channel 0 data register.
Mnemonic: PWMD1H
7
6
5
PWMP1
Mnemonic: PWMD1L
7
6
5
4
-
3
-
4
3
PWMD1[7:0]
2
2
Address: BEh
1
0
Reset
PWMD1[9:8]
00H
1
Address: BFh
0
Reset
00H
PWMP1: PWM channel 1 idle polarity select.
“0” – PWM channel 1 will idle low.
“1” – PWM channel 1 will idle high.
PWMD1[9:0]: PWM channel 1 data register.
Mnemonic: PWMMDH
7
6
5
Mnemonic: PWMMDL
7
6
5
4
-
3
-
4
3
PWMMD[7:0]
2
2
Address: CEh
1
0
Reset
PWMMD[9:8]
00H
1
Address: CFh
0
Reset
FFH
PWMMD[9:0]: PWM Max Data register.
PWM count from 0000h to PWMMD[9:0]. When PWM count data equal PWMMD[9:0] is
overflow.
PWMPx = 0 & PWMDx = 00h
PWMPx = 0 & PWMDx ≠ 00h
PWMPx = 1 & PWMDx = 00h
PWMPx = 1 & PWMDx ≠ 00h
PWMMD + 1
PWM clock
PWMDx
Leader pulse =
PWM clock
PWM period =
Specifications subject to change without notice contact your sales representatives for the most recent information.
57
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
13 IIC function
The IIC module uses the SCL (clock) and the SDA (data) line to communicate with external IIC interface. Its speed can be selected
to 400Kbps (maximum) by software setting the IICBR [2:0] control bit. The IIC module provided 2 interrupts (RXIF, TXIF). It will
generate START, repeated START and STOP signals automatically in master mode and can detects START, repeated START and
STOP signals in slave mode. The maximum communication length and the number of devices that can be connected are limited by a
maximum bus capacitance of 400pF.
The interrupt vector is 6Bh.
Mnemonic
Description
Direc
t
Bit 7
AUX
IICCTL
Auxiliary register
IIC control register
91h
F9h
BRGS
IICEN
IICS
IIC status register
F8h
-
IICA1
IICA2
IICRWD
IICEBT
IIC Address 1
register
IIC Address 2
register
IIC Read/Write
register
IIC Enaable Bus
Transaction
Bit 6
Bit 5
Bit 4
IIC function
P2SPI
P2UR
MSS
MAS AB_EN
MPIF
LAIF
RXIF
FAh
IICA1[7:1]
FBh
IICA2[7:1]
FCh
Bit 2
P2IIC
BF_EN
-
TXIF
Bit 1
Bit 0
DPS
IICBR[2:0]
RW or
RXAK TXAK
BB
MATCH1
or RW1
MATCH2
or RW2
IICRWD[7:0]
FDh
Mnemonic: AUX
7
6
BRGS
-
Bit 3
FU_EN
5
P2SPI
4
P2UR
-
3
P2IIC
-
2
-
-
1
-
RESE
T
00H
04H
00H
A0H
60H
00H
-
-
-
00H
Address: 91h
0
Reset
DPS
00H
P2IIC: P2IIC = 0 – IIC function on P1.
P2IIC = 1 – IIC function on P2.
Mnemonic: IICCTL
7
6
5
IICEN
MSS
MAS
4
AB_EN
3
BF_EN
2
1
IICBR[2:0]
Address: F9h
0
Reset
04h
IICEN: Enable IIC module
IICEN = 1 is Enable
IICEN = 0 is Disable.
MSS: Master or slave mode select.
MSS = 1 is master mode.
MSS = 0 is slave mode.
*The software must set this bit before setting others register.
MAS: Master address select (master mode only)
MAS = 0 is to use IICA1.
MAS = 1 is to use IICA2.
AB_EN: Arbitration lost enable bit. (Master mode only)
If set AB_EN bit, the hardware will check arbitration lost. Once arbitration lost occurred, hardware will
return to IDLE state. If this bit is cleared, hardware will not care arbitration lost condition. Set this bit
when multi-master and slave connection. Clear this bit when single master to single slave.
BF_EN: Bus busy enable bit. (Master mode only)
If set BF_EN bit, hardware will not generate a start condition to bus until BF=0. Clear this bit will
always generate a start condition to bus when MStart is set. Set this bit when multi-master and slave
connection. Clear this bit when single master to single slave.
IICBR[2:0]: Baud rate selection (master mode only), where Fosc is the external crystal or oscillator frequency. The
Specifications subject to change without notice contact your sales representatives for the most recent information.
58
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
default is Fosc/512 for users’ convenience.
IICBR[2:0]
Baud rate
000
Fosc/32
001
Fosc/64
010
Fosc/128
011
Fosc/256
100
Fosc/512
101
Fosc/1024
110
Fosc/2048
111
Fosc/4096
Mnemonic: IICS
7
6
MPIF
5
LAIF
4
RXIF
3
TXIF
2
RXAK
1
TxAK
Address: F8H
0
Reset
RW or BB
00H
MPIF: The Stop condition Interrupt Flag
The stop condition occurred and this bit will be set. Software need to clear this bit
LAIF: Arbitration lost bit. (Master mode only)
The Arbitration Interrupt Flag, the bus arbitration lost occurred and this bit will be set. Software
need to clear this bit
RxIF: The data Receive Interrupt Flag (RXIF) is set after the IICRWD (IIC Read Write Data Buffer) is
loaded with a newly receive data.
TxIF: The data Transmit Interrupt Flag (TXIF) is set when the data of the IICRWD (IIC Read Write
Data Buffer) is downloaded to the shift register.
RxAK: The Acknowledge Status indicate bit. When clear, it means an acknowledge signal has been
received after the complete 8 bits data transmit on the bus.
TxAK: The Acknowledge status transmit bit. When received complete 8 bits data, this bit will set
(NoAck) or clear (Ack) and transmit to master to indicate the receive status.
RW or BB: Master Mode:
BB : Bus busy bit
If detect scl=0 or sda=0 or bus start, this bit will be set. If detect stop,this bit will be cleared.
This bit can be cleared by software to return ready state.
Slave Mode:
RW:The slave mode read (received) or wrote (transmit) on the IIC bus. When this bit is clear,
the slave module received data on the IIC bus (SDA).(Slave mode only)
Fig. 13-1: Acknowledgement bit in the 9th bit of a byte transmission
Mnemonic: IICA1
Address: FAH
Rese
7
6
5
4
3
2
1
0
t
IICA1[7:1]
Match1 or RW1 A0H
R/W
R or R/W
Specifications subject to change without notice contact your sales representatives for the most recent information.
59
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
Slave mode:
IICA1[7:1]: IIC Address registers
This is the first 7-bit address for this slave module. It will be checked when an address (from master) is
received
Match1: When IICA1 matches with the received address from the master side, this bit will set to 1 by hardware.
When IIC bus gets first data, this bit will clear.
Master mode:
IICA1[7:1]: IIC Address registers
This 7-bit address indicates the slave with which it wants to communicate.
RW1: This bit will be sent out as RW of the slave side if the module has set the MStart or RStart bit. It appears at
the 8th bit after the IIC address as shown in Fig. 13-2. It is used to tell the salve the direction of the
following communication. If it is 1, the module is in master receive mode. If 0, the module is in master
transmit mode.
RW1=1, master receive mode
RW1=0, master transmit mode
Fig. 13-2: RW bit in the 8th bit after IIC address
Mnemonic: IICA2
7
6
5
Address: FBh
4
IICA2[7:1]
R/W
3
2
1
0
Match2 or RW2
R or R/W
Reset
60h
Slave mode:
IICA2[7:1]: IIC Address registers
This is the second 7-bit address for this slave module.
It will be checked when an address (from master) is received
Match2: When IICA2 matches with the received address from the master side, this bit will set to 1 by hardware.
When IIC bus gets first data, this bit will clear.
Master mode:
IICA2[7:1]: IIC Address registers
This 7-bit address indicates the slave with which it wants to communicate.
RW2: This bit will be sent out as RW of the slave side if the module has set the MStart or RStart bit. It is used to
tell the salve the direction of the following communication. If it is 1, the module is in master receive
mode. If 0, the module is in master transmit mode.
RW2=1, master receive mode
RW2=0, master transmit mode
Mnemonic: IICRWD
7
6
5
4
3
2
1
IICRWD[7:0]
IICRWD[7:0]: IIC read write data buffer.
In receiving (read) mode, the received byte is stored here.
Address: FCh
0
Reset
00h
Specifications subject to change without notice contact your sales representatives for the most recent information.
60
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
In transmitting mode, the byte to be shifted out through SDA stays here.
Mnemonic: IICEBT
7
6
FU_EN
5
4
3
2
1
-
-
-
-
-
Address: FDH
Rese
0
t
00H
Master Mode：
00: reserved
01: IIC bus module will enable read/write data transfer on SDA and SCL.
10: IIC bus module generate a start condition on the SDA/SCL, then send out address
which is stored in the IICA1/IICA2(selected by MAS control bit)
11: IIC bus module generates a stop condition on the SDA/SCL.
FU_EN[7:6] will be auto-clear by hardware, so setting FU_EN[7:6] repeatedly is
necessary.
Slave mode:
01: FU_EN[7:6] should be set as 01 only. The other value is inhibited.
Notice:
1. FU_EN[7:6] should be set as 01 before read/write data transfer for bus release;
otherwise, SCL will be locked(pull low).
2. FU_EN[7:6] should be set as 01 after read/write data transfer for receiving a stop
condition from bus master.
3. In transmit data mode(slave mode), the output data should be filled into IICRWD
before setting FU_EN[7:6] as 01.
4. FU_EN[7:6] will be auto-clear by hardware, so setting FU_EN[7:6] repeatedly is
necessary.
Specifications subject to change without notice contact your sales representatives for the most recent information.
61
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
14 SPI Function - Serial Peripheral Interface
Serial Peripheral Interface (SPI) is a synchronous protocol that allows a master device to initiate communication with slave devices.
The interrupt vector is 4Bh.
There are 4 signals used in SPI, they are
SPI_MOSI: data output in the master mode, data input in the slave mode,
SPI_MISO: data input in the master mode, data output in the master mode,
SPI_SCK: clock output from the master, the above data are synchronous to this signal
SPI_SS: input in the slave mode.
This slave device detects this signal to judge if it is selected by the master.
In the master mode, it can select the desired slave device by any IO with value = 0. Fig. 14-1 is an example showing the relation of
the 4 signals between master and slaves.
Master
Slave 2
Slave 1
MOSI
MISO
CLK
IO
IO
MOSI
MISO
CLK
MOSI
MISO
CLK
SS
SS
Fig. 14-1: SPI signals between master and slave devices
There is only one channel SPI interface. The SPI SFRs are shown as below:
SPI
Description
AUX
Auxiliary register
SPI control register
1
SPI control register
2
SPI status register
SPI transmit data
buffer
SPI receive data
buffer
SPIC1
SPIC2
SPIS
SPITXD
SPIRXD
Direc
t
Bit 7
Bit 6
91h
BRGS
-
F1h
SPIEN
F2h
SPIFD
F5h
SPIRF
Bit 5
SPI function
P2SPI
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESE
T
P2UR
P2IIC
-
-
DPS
00H
SPIMSS SPISSP SPICKP SPICKE
TBC[2:0]
SPIMLS
SPIRST
SPIBR[2:0]
08H
RBC[2:0]
00H
SPIOV SPITXIF SPITDR SPIRXIF SPIRDR
SPIRS
40H
F3h
SPITXD[7:0]
00H
F4h
SPIRXD[7:0]
00H
Specifications subject to change without notice contact your sales representatives for the most recent information.
62
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
Mnemonic: AUX
7
6
BRGS
-
5
P2SPI
4
P2UR
P2SPI: P2SPI = 0 – SPI function on P1.
P2SPI = 1 – SPI function on P2.
P2SPI
MOSI
MISO
0
P1.7
P1.6
1
P2.2
P2.3
Mnemonic:SPIC1
7
6
SPIEN SPIMSS
5
SPISSP
4
SPICKP
3
P2IIC
SS
P1.4
P2.4
2
-
1
-
Address: 91h
0
Reset
DPS
00H
SPICLK
P0.0
P2.5
3
SPICKE
2
1
SPIBR[2:0]
0
Address:F1H
Reset
08H
SPIEN: Enable SPI module.
“1” is Enable.
“0” is Disable.
SPIMSS: Master or Slave mode Select
“1” is Master mode.
“0” is Slave mode.
SPISSP: SS or CS active polarity.(Slave mode used only)
“1” - high active.
“0” - low active.
SPICKP: Clock idle polarity select. (Master mode used only)
“1” - SCK will idle high. Ex :
“0” - SCK will idle low. Ex :
SPICKE: Clock sample edge select.
“1” – rising edge latch data.
“0” – falling edge latch data.
* To ensure the data latch stability, SM39R16A2 generate the output data as given in the
following example, the other side can latch the stable data no matter in rising or falling edge.
sufficient set-up time
sufficient hold time
SPIBR[2:0]: SPI baud rate select. (Master mode used only)
SPIBR[2:0]
Baud rate
0:0:0
Fosc/4
0:0:1
Fosc /8
0:1:0
Fosc /16
0:1:1
Fosc /32
1:0:0
Fosc /64
1:0:1
Fosc /128
1:1:0
Fosc /256
1:1:1
Fosc /512
Specifications subject to change without notice contact your sales representatives for the most recent information.
63
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
Mnemonic: SPIC2
7
6
5
SPIFD
TBC[2:0]
4
3
SPIRST
2
1
RBC[2:0]
Address: F2H
0
Reset
00H
SPIFD: Full-duplex mode enable.
“1” is enable full-duplex mode.
“0” is disable full-duplex mode.
When it is set, the TBC[2:0] and RBC[2:0] will be reset and keep to zero. When the Master device
transmits data to the Slave device via the MOSI line, the Slave device responds by sending data to the
Master device via the MISO line. This implies full-duplex transmission with both data out and data in
synchronized with the same clock.
Input Shift register
SPIRXD
Output Shift register
SPITXD
Clock Generator
SyncMos Master
MISO
MISO
MOSI
MOSI
SCK
SCK
Output Shift register
SPITXD
Input Shift register
SPIRXD
SyncMos Slave
SPIRST: SPI Re-start (Slave mode used only)
SPIRST=0:Re-start function disable.SPI transmit/receive data when SS active.
In SPITXD/SPIRXD buffer, data got from previous SS active period will not be removed
(i.e. it's valid).
SPIRST=1:Re-start function enable.SPI transmit/receive new data when SS re-active;
In SPITXD/SPIRXD buffer, data got from previous SS active period will be removed (i.e.
It's invalid).
TBC[2:0]: SPI transmitter bit counter.
TBC[2:0]
Bit counter
0:0:0
8 bits output
0:0:1
1 bit output
0:1:0
2 bits output
0:1:1
3 bits output
1:0:0
4 bits output
1:0:1
5 bits output
1:1:0
6 bits output
1:1:1
7 bits output
Specifications subject to change without notice contact your sales representatives for the most recent information.
64
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
RBC[2:0]: SPI receiver bit counter.
RBC[2:0]
Bit counter
0:0:0
8 bits input
0:0:1
1 bit input
0:1:0
2 bits input
0:1:1
3 bits input
1:0:0
4 bits input
1:0:1
5 bits input
1:1:0
6 bits input
1:1:1
7 bits input
Mnemonic: SPIS
7
6
SPIRF
SPIMLS
5
4
SPIOV SPITXIF
3
SPITDR
2
1
SPIRXIF SPIRDR
Address:F5H
0
Reset
SPIRS
40H
SPIRF: SPI SS pin Release Flag.
This bit is set when SS pin release & SPIRST as ‘1’.
SPIMLS: MSB or LSB first output /input Select.
“1” is MSB first output/input.
“0” is LSB first output/input.
SPIOV: Overflow flag.
When SPIRDR is set and next data already into shift register, this flag will be set.
It is clear by hardware, when SPIRDR is cleared.
SPITXIF: Transmit Interrupt Flag.
This bit is set when the data of the SPITXD register is downloaded to the shift register.
SPITDR: Transmit Data Ready.
When MCU finish writing data to SPITXD register, the MCU needs to set this bit to ‘1’ to
inform the SPI module to send the data. After SPI module finishes sending the data from
SPITXD, this bit will be cleared automatically.
SPIRXIF: Receive Interrupt Flag.
This bit is set after the SPIRXD is loaded with a newly receive data.
SPIRDR: Receive Data Ready.
The MCU must clear this bit after it gets the data from SPIRXD register. The SPI module is able
to write new data into SPIRXD only when this bit is cleared.
SPIRS: Receive Start.
This bit set to “1” to inform the SPI module to receive the data into SPIRXD register.
Mnemonic: SPITXD
7
6
5
4
3
SPITXD[7:0]
2
1
Address: F3H
0
Reset
00H
4
3
SPIRXD[7:0]
2
1
Address: F4H
0
Reset
00H
SPITXD[7:0]: Transmit data buffer.
Mnemonic: SPIRXD
7
6
5
SPIRXD[7:0]: Receive data buffer.
P.S. MISO pin must be float when SS or CS no-active in slave mode.
Specifications subject to change without notice contact your sales representatives for the most recent information.
65
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
15 KBI – Keyboard Interface
Keyboard interface (KBI) can be connected to a 4 x n matrix keyboard or any similar devices. It has 4 inputs with programmable
interrupt capability on either high or low level. These 4 inputs can be the external interrupts to leave from the idle and stop modes.
The 4 inputs are independent from each other but share the same interrupt vector 5Bh.
Figure 15.1 keyboard interface block diagram
Figure 15.2 keyboard input circuitry
KBI
Description
KBLS
KBE
KBF
KBI level selection
KBI input enable
KBI flag
KBI De-bounce
control register
KBD
Mnemonic: KBLS
7
6
-
Direc
t
Bit 7
Bit 6
93h
94h
95h
-
-
96h
KBDEN
-
5
-
4
-
Bit 5
KBI function
-
3
KBLS.3
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESE
T
-
KBLS3
KBE3
KBF3
KBLS2
KBE2
KBF2
KBLS1
KBE1
KBF1
KBLS0
KBE0
KBF0
00H
00H
00H
-
-
-
KBD1
KBD0
00H
2
KBLS.2
1
KBLS.1
Address: 93h
0
Reset
KBLS.0
00h
Specifications subject to change without notice contact your sales representatives for the most recent information.
66
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
KBLS.3: Keyboard Line 3 level selection bit
0 : enable a low level detection on KBI3.
1 : enable a high level detection on KBI3.
KBLS.2: Keyboard Line 2 level selection bit
0 : enable a low level detection on KBI2.
1 : enable a high level detection on KBI2.
KBLS.1: Keyboard Line 1 level selection bit
0 : enable a low level detection on KBI1.
1 : enable a high level detection on KBI1.
KBLS.0: Keyboard Line 0 level selection bit
0 : enable a low level detection on KBI0.
1 : enable a high level detection on KBI0.
Mnemonic: KBE
7
6
-
5
-
4
-
3
KBE.3
2
KBE.2
1
KBE.1
Address: 94h
0
Reset
KBE.0
00h
KBE.3: Keyboard Line 3 enable bit
0 : enable standard I/O pin.
1 : enable KBF.3 bit in KBF register to generate an interrupt request.
KBE.2: Keyboard Line 2 enable bit
0 : enable standard I/O pin.
1 : enable KBF.2 bit in KBF register to generate an interrupt request.
KBE.1: Keyboard Line 1 enable bit
0 : enable standard I/O pin.
1 : enable KBF.1 bit in KBF register to generate an interrupt request.
KBE.0: Keyboard Line 0 enable bit
0 : enable standard I/O pin.
1 : enable KBF.0 bit in KBF register to generate an interrupt request.
Mnemonic: KBF
7
6
-
5
-
4
-
3
KBF.3
2
KBF.2
1
KBF.1
Address: 95h
0
Reset
KBF.0
00h
KBF.3: Keyboard Line 3 flag
This is set by hardware when KBI3 detects a programmed level.
It generates a Keyboard interrupt request if KBE.3 is also set. It must be cleared by software.
KBF.2: Keyboard Line 2 flag
This is set by hardware when KBI2 detects a programmed level.
It generates a Keyboard interrupt request if KBE.2 is also set. It must be cleared by software.
KBF.1: Keyboard Line 1 flag
This is set by hardware when KBI1 detects a programmed level.
It generates a Keyboard interrupt request if KBE.1 is also set. It must be cleared by software.
KBF.0: Keyboard Line 0 flag
This is set by hardware when KBI0 detects a programmed level.
It generates a Keyboard interrupt request if KBE.0 is also set. It must be cleared by software.
Mnemonic: KBD
7
6
KBDEN
-
5
-
4
-
3
-
2
-
1
KBD.1
Address: 96H
0
Reset
KBD.0
00H
KBDEN: Enable KBI de-bounce function. The default KBI function is enabled.
KBDEN = 0, enable KBI de-bounce function. The de-bounce time is selected by KBD [1:0].
KBDEN = 1, disable KBI de-bounce function. The KBI input pin without de-bounce
mechanism.
KBD[1:0]: Select KBI de-bounce time. If KBDEN = “0”, the default de-bounce time is 320 ms.
Specifications subject to change without notice contact your sales representatives for the most recent information.
67
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
KBD[1:0] = 00, the de-bounce time is 320 ms.
KBD[1:0] = 01, the de-bounce time is 160 ms.
KBD[1:0] = 10, the de-bounce time is 80 ms.
KBD[1:0] = 11, the de-bounce time is 40 ms.
Specifications subject to change without notice contact your sales representatives for the most recent information.
68
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
16 LVI – Low Voltage Interrupt
The interrupt vector 63h.
Mnemonic
Description
RSTS
Reset status register
Low voltage
control register
LVC
Direc
t
Bit 7
A1h
-
E6h
LVI_EN
Mnemonic: RSTS
7
6
-
5
-
Bit 6
Bit 5
Bit 4
Watchdog Timer
PDRF
-
4
PDRF
LVRE
3
WDTF
Bit 3
Bit 2
Bit 1
Bit 0
RESE
T
WDTF
SWRF
LVRF
PORF
00H
-
-
-
LVIS
20H
LVIF
2
SWRF
1
LVRF
Address: A1h
0
Reset
PORF
00H
PDRF: Pad reset flag.
When MCU is reset by reset pad, PDRF flag will be set to one by hardware. This flag clear by
software.
LVRF: Low voltage reset flag.
When MCU is reset by LVR, LVRF flag will be set to one by hardware. This flag clear by
software.
PORF: Power on reset flag.
When MCU is reset by POR, PORF flag will be set to one by hardware. This flag clear by
software.
Mnemonic: LVC
7
6
LVI_EN
5
LVRE
4
LVIF
3
-
2
-
Address: E6h
0
Reset
LVIS
20H
1
-
LVI_EN: Low voltage interrupt function enable bit.
LVI_EN = 0 - disable low voltage detect function.
LVI_EN = 1 - enable low voltage detect function.
LVRE: External low voltage reset function enable bit.
LVRE = 0 - disable external low voltage reset function.
LVRE = 1 - enable external low voltage reset function.
LVIF: Low Voltage interrupt Flag
LVIS LVI level select:
LVIS = 0 - The level of voltage is set at Low-level
LVIS = 1 - The level of voltage is set at Hi-Level
Hi-level：
Symbol
VLVI
VLVR
Notes:
Parameter
Low Voltage Interrupt Voltage Level
Low Voltage Reset Voltage Level
The VLVI always above VLVR about 0.2V.
Low-level：
Symbol
Parameter
VLVI
Low Voltage Interrupt Voltage Level
VLVR
Low Voltage Reset Voltage Level
Notes: The VLVI always above VLVR about 0.2V.
Min
3.4
3.2
Typ
3.7
3.5
Max
4.0
3.8
Units
V
V
Min
2.1
1.9
Typ
2.3
2.1
Max
2.5
2.3
Units
V
V
Specifications subject to change without notice contact your sales representatives for the most recent information.
69
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
17 10-bit Analog-to-Digital Converter (ADC)
The SM39R16A2 provides eight channels 10-bit ADC. The Digital output DATA [9:0] were put into ADCD [9:0].
The ADC interrupt vector is 53H.
The ADC SFR show as below:
Mnemonic
Description
Direc
t
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESE
T
ADC
ADCC1
ADCC2
ADCDH
ADCDL
ADCCS
ADC Control
register 1
ADC Control
register 2
ADC data high byte
ADC data low byte
ADC clock select
ABh ADC7EN ADC6EN ADC5EN ADC4EN ADC3EN ADC2EN ADC1EN ADC0EN
00H
ACh
00H
ADh
AEh
AFh
Start
ADJUST
ADCR[1:0]
-
ADCCH[2:0]
ADCDH [7:0]
ADCDL [7:0]
-
-
-
ADCCS[4:0]
00H
00H
00H
Mnemonic: ADCC1
Address: ABh
7
6
5
4
3
2
1
0
Reset
ADC7EN ADC6EN ADC5EN ADC4EN ADC3EN ADC2EN ADC1EN ADC0EN 00H
ADC7EN: ADC channels 7 enable.
ADC7EN = 1 – Enable ADC channel 7
ADC6EN: ADC channels 6 enable.
ADC6EN = 1 – Enable ADC channel 6
ADC5EN: ADC channels 5 enable.
ADC5EN = 1 – Enable ADC channel 5
ADC4EN: ADC channels 4 enable.
ADC4EN = 1 – Enable ADC channel 4
ADC3EN: ADC channels 3 enable.
ADC3EN = 1 – Enable ADC channel 3
Specifications subject to change without notice contact your sales representatives for the most recent information.
70
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
ADC2EN: ADC channels 2 enable.
ADC2EN = 1 – Enable ADC channel 2
ADC1EN: ADC channels 1 enable.
ADC1EN = 1 – Enable ADC channel 1
ADC0EN: ADC channels 0 enable.
ADC0EN = 1 – Enable ADC channel 0
Mnemonic: ADCC2
7
6
Start ADJUST
5
4
ADCR[1:0]
3
-
2
1
ADCCH[2:0]
0
Address: ACh
Reset
00H
Start: When this bit is set, the ADC will be start conversion continuous.
ADJUST: Adjust the format of ADC conversion DATA.
ADJUST = 0: (default value)
ADC data high byte ADCD [9:2] = ADCDH [7:0].
ADC data low byte ADCD [1:0] = ADCDL [1:0].
ADJUST = 1: ADC data high byte ADCD [9:8] = ADCDH [1:0].
ADC data low byte ADCD [7:0] = ADCDL [7:0].
ADCR[1:0]: ADC range.
ADCR [1:0]
Range
00
0 ~ Vdd
01
4
× Vdd
0~
10
11
ADCCH[2:0]: ADC channel select.
ADCCH [2:0]
000
001
010
011
100
101
110
111
5
3
× Vdd
0~
5
reserved
Channel
0
1
2
3
4
5
6
7
ADJUST = 0:
Mnemonic: ADCDH
Address: ADh
7
6
5
4
3
2
1
0
Reset
ADCD[9] ADCD[8] ADCD[7] ADCD[6] ADCD[5] ADCD[4] ADCD[3] ADCD[2] 00H
Mnemonic: ADCDL
7
6
5
ADJUST = 1:
Mnemonic: ADCDH
7
6
5
-
4
-
3
-
2
-
Address: AEh
1
0
Reset
ADCD[1] ADCD[0] 00H
4
-
3
-
2
-
Address: ADh
1
0
Reset
ADCD[9] ADCD[8] 00H
Specifications subject to change without notice contact your sales representatives for the most recent information.
71
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
Mnemonic: ADCDL
Address: AEh
7
6
5
4
3
2
1
0
Reset
ADCD[7] ADCD[6] ADCD[5] ADCD[4] ADCD[3] ADCD[2] ADCD[1] ADCD[0] 00H
ADCD[9:0]: ADC data register.
Mnemonic: ADCCS
7
6
-
5
-
4
ADCCS[4]
3
ADCCS[3]
2
ADCCS[2]
1
ADCCS[1]
Address: AFh
0
Reset
ADCCS[0]
00H
ADCCS[4:0]: ADC clock select.
*The ADC clock maximum 12.5MHz.
*The ADC Conversion rate maximum 500KHz.
ADCCS[4:0]
ADC Clock(Hz)
Clocks for ADC Conversion
00000
Fosc /2
46
00001
Fosc/4
92
00010
Fosc /6
138
00011
Fosc /8
184
00100
Fosc /10
230
00101
Fosc /12
276
00110
Fosc /14
322
00111
Fosc /16
368
01000
Fosc /18
414
01001
Fosc /20
460
01010
Fosc /22
506
01011
Fosc /24
552
01100
Fosc /26
598
01101
Fosc /28
644
01110
Fosc /30
690
01111
Fosc /32
736
10000
Fosc /34
782
10001
Fosc /36
828
10010
Fosc /38
874
10011
Fosc /40
920
10100
Fosc /42
966
10101
Fosc /44
1012
10110
Fosc /46
1058
10111
Fosc /48
1104
11000
Fosc /50
1150
11001
Fosc /52
1196
11010
Fosc /54
1242
11011
Fosc /56
1288
11100
Fosc /58
1334
11101
Fosc /60
1380
11110
Fosc /62
1426
11111
Fosc /64
1472
Fosc
2 × ( ADCCS + 1)
ADC_Clock
ADC _ Conversion _ Rate =
23
ADC _ Clock =
Specifications subject to change without notice contact your sales representatives for the most recent information.
72
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
18 In-System Programming (Internal ISP)
The SM39R16A2 can generate flash control signal by internal hardware circuit. Users utilize flash control register, flash address
register and flash data register to perform the ISP function without removing the SM39R16A2 from the system. The SM39R16A2
provides internal flash control signals which can do flash program/chip erase/page erase/protect functions. User need to design and
use any kind of interface which SM39R16A2 can input data. User then utilize ISP service program to perform the flash
program/chip erase/page erase/protect functions.
18.1 ISP service program
The ISP service program is a user developed firmware program which resides in the ISP service program space. After user
developed the ISP service program, user then determine the size of the ISP service program. User need to program the ISP
service program in the SM39R16A2 for the ISP purpose.
The ISP service programs were developed by user so that it should includes any features which relates to the flash memory
programming function as well as communication protocol between SM39R16A2 and host device which output data to the
SM39R16A2. For example, if user utilize UART interface to receive/transmit data between SM39R16A2 and host device, the
ISP service program should include baud rate, checksum or parity check or any error-checking mechanism to avoid data
transmission error.
The ISP service program can be initiated under SM39R16A2 active or idle mode. It can not be initiated under power down
mode.
18.2 Lock Bit (N)
The Lock Bit N has two functions: one is for service program size configuration and the other is to lock the ISP service
program space from flash erase function.
The ISP service program space address range $3000 to $3FFF. It can be divided as blocks of N*256 byte. (N=0 to 16). When
N=0 means no ISP function, all of 16K byte flash memory can be used as program memory. When N=1 means ISP service
program occupies 256 byte while the rest of 15.75K byte flash memory can be used as program memory. The maximum ISP
service program allowed is 4K byte when N=16. Under such configuration, the usable program memory space is 12K byte.
After N determined, SM39R16A2 will reserve the ISP service program space downward from the top of the program address
$3FFF. The start address of the ISP service program located at $3x00 while x is depending on the lock bit N. Please see section
3.1 program memory diagram for this ISP service program space structure.
The lock bit N function is different from the flash protect function. The flash erase function can erase all of the flash memory
except for the locked ISP service program space. If the flash not has been protected, the content of ISP service program still can
be read. If the flash has been protected, the overall content of flash program memory space including ISP service program
space can not be read.
Table 18.1 ISP code area.
N
ISP service program address
0
No ISP service program
1
256 bytes ($3F00h ~ $3FFFh)
2
512 bytes ($3E00h ~ $3FFFh)
3
768 bytes ($3D00h ~ $3FFFh)
4
1.0 K bytes ($3C00h ~ $3FFFh)
5
1.25 K bytes ($3B00h ~ $3FFFh)
6
1.5 K bytes ($3A00h ~ $3FFFh)
7
1.75 K bytes ($3900h ~ $3FFFh)
8
2.0 K bytes ($3800h ~ $3FFFh)
9
2.25 K bytes ($3700h ~ $3FFFh)
10
2.5 K bytes ($3600h ~ $3FFFh)
Specifications subject to change without notice contact your sales representatives for the most recent information.
73
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
11
12
13
14
15
16
2.75 K bytes ($3500h ~ $3FFFh)
3.0 K bytes ($3400h ~ $3FFFh)
3.25 K bytes ($3300h ~ $3FFFh)
3.5 K bytes ($3200h ~ $3FFFh)
3.75 K bytes ($3100h ~ $3FFFh)
4.0 K bytes ($3000h ~ $3FFFh)
ISP service program configurable in N*256 byte (N= 0 ~ 16)
18.3 Program the ISP Service Program
After Lock Bit N is set and ISP service program been programmed, the ISP service program memory will be protected (locked)
automatically. The lock bit N has its own program/erase timing. It is different from the flash memory program/erase timing so
the locked ISP service program can not be erased by flash erase function. If user needs to erase the locked ISP service program,
he can do it by writer only. User can not change ISP service program when SM39R16A2 was in system.
18.4 Initiate ISP Service Program
To initiate the ISP service program is to load the program counter (PC) with start address of ISP service program and execute it.
There are four ways to do so:
(1) Blank reset. Hardware reset with first flash address blank ($0000=#FFH) will load the PC with start address of
ISP service program. The hardware reset includes MAX810 (power on reset) and external pad reset. The
hardware will issue a strobe window about 256us after hardware reset.
(2) Execute jump instruction can load the start address of the ISP service program to PC.
(3) Enter’s ISP service program by hardware setting. User can force SM39R16A2 enter ISP service program by
setting P2.6, P2.7 “active low” or P1.6 “ active low” during hardware reset period. The hardware reset
includes MAX810 (power on reset) and external pad reset. The hardware will issue after hardware reset. In
application system design, user should take care of the setting of P2.6, P2.7 or P1.6 at reset period to prevent
SM39R16A2 from entering ISP service program.
(4) Enter’s ISP service program by hardware setting, the P1.1(RXD) will be detected the two clock signals during
hardware reset period. The hardware reset includes MAX810 (power on reset) and external pad reset. The
hardware will issue to detect 2 clock signals after hardware reset.
During the strobe window, the hardware will detect the status of P2.6/P2.7/P1.6/P1.1. If they meet one of above conditions,
chip will switch to ISP mode automatically. After ISP service program executed, user need to reset the SM39R16A2, either by
hardware reset or by WDT, or jump to the address $0000 to re-start the firmware program.
There are 8 kinds of entry mechanisms for user different applications. This entry method will select on the writer or ISP.
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
First Address Blank. i.e. $0000 = 0xFF. And triggered by Internal reset signal.
First Address Blank. i.e. $0000 = 0xFF. And triggered by PAD reset signal.
P2.6 = 0 & P2.7 = 0. And triggered by Internal reset signal.
P2.6 = 0 & P2.7 = 0. And triggered by PAD reset signal.
P1.6 = 0. And triggered by Internal reset signal.
P1.6 = 0. And triggered by PAD reset signal.
P1.1 input 2 clocks. And triggered by Internal reset signal.
P1.1 input 2 clocks. And triggered by PAD reset signal.
Specifications subject to change without notice contact your sales representatives for the most recent information.
74
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
18.5 ISP register – TAKEY, IFCON, ISPFAH, ISPFAL, ISPFD and ISPFC
Mnemonic
Description
Direc
t
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESE
T
ISP function
TAKEY
IFCON
ISPFAH
ISPFAL
ISPFD
ISPFC
Time Access Key
register
Interface Control
register
ISP Flash Address High register
ISP Flash Address Low register
ISP Flash Data
register
ISP Flash Control
register
F7h
TAKEY [7:0]
8Fh
-
CDPR
E1h
-
-
-
-
00H
-
-
-
ISPE
ISPFAH [5:0]
00H
FFH
E2h
ISPFAL [7:0]
FFH
E3h
ISPFD [7:0]
FFH
E4h
EMF1
Mnemonic: TAKEY
7
6
5
EMF2
EMF3
EMF4
4
3
TAKEY [7:0]
-
ISPF.2
2
1
ISPF.1
0
ISPF.0
00H
Address: F7H
Reset
00H
ISP enable bit (ISPE) is read-only by default, software must write three specific values 55h, AAh and 5Ah sequentially
to the TAKEY register to enable the ISPE bit write attribute. That is:
MOV TAKEY, #55h
MOV TAKEY, #0AAh
MOV TAKEY, #5Ah
Mnemonic: IFCON
7
6
CDPR
5
-
4
-
3
-
2
-
1
-
0
ISPE
Address: 8FH
Reset
00H
The bit 0 (ISPE) of IFCON is ISP enable bit. User can enable overall SM39R16A2 ISP function by setting ISPE bit to 1,
to disable overall ISP function by set ISPE to 0. The function of ISPE behaves like a security key. User can disable
overall ISP function to prevent software program be erased accidentally. ISP registers ISPFAH, ISPFAL, ISPFD and
ISPFC are read-only by default. Software must be set ISPE bit to 1 to enable these 4 registers write attribute.
Mnemonic: ISPFAH
7
6
-
5
ISPFAH5
4
ISPFAH4
3
ISPFAH3
2
ISPFAH2
1
ISPFAH1
Address: E1H
0
Reset
ISPFAH0
FFH
ISPFAH [5:0]: Flash address-high for ISP function
Mnemonic: ISPFAL
7
6
ISPFAL7 ISPFAL6
5
ISPFAL5
4
ISPFAL4
3
ISPFAL3
2
ISPFAL2
1
ISPFAL1
Address: E2H
0
Reset
ISPFAL0
FFH
ISPFAL [7:0]: Flash address-Low for ISP function
The ISPFAH & ISPFAL provide the 14-bit flash memory address for ISP function. The flash memory address should not
include the ISP service program space address. If the flash memory address indicated by ISPFAH & ISPFAL registers
overlay with the ISP service program space address, the flash program/page erase of ISP function executed thereafter
will have no effect.
Mnemonic: ISPFD
Address: E3H
7
6
5
4
3
2
1
0
Reset
Specifications subject to change without notice contact your sales representatives for the most recent information.
75
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
ISPFD7
ISPFD6
ISPFD5
ISPFD4
ISPFD3
ISPFD2
ISPFD1
ISPFD0
FFH
ISPFD [7:0]: Flash data for ISP function.
The ISPFD provide the 8-bit data register for ISP function.
Mnemonic: ISPFC
7
6
EMF1
EMF2
5
EMF3
4
EMF4
3
-
2
ISPF[2]
1
ISPF[1]
Address: E4H
0
Reset
ISPF[0]
00H
EMF1: Entry mechanism (1) flag, clear by reset. (Read only)
EMF2: Entry mechanism (2) flag, clear by reset. (Read only)
EMF3: Entry mechanism (3) flag, clear by reset. (Read only)
EMF4: Entry mechanism (4) flag, clear by reset. (Read only)
ISPF [2:0]: ISP function select bit.
ISPF[2:0]
ISP function
000
Byte program
001
Chip protect
010
Page erase
011
Chip erase
100
Write option
101
Read option
110
Erase option
111
reserved
One page of flash memory is 256 byte
The Option function can access the XTAL1 and XTAL2 swap to I/O pins select(description in
section 1.2)、Internal reset time select(description in section 1.4.1)、clock source
select(description in section 1.5)、Reset swap to I/O pins function select(description in section
5)、WDTEN control bit(description in section 9)、or ISP entry mechanisms select(description in
section 18).
When chip protected or no ISP service, option can only read.
The choice ISP function will start to execute once the software write data to ISPFC register.
To perform byte program/page erases ISP function, user need to specify flash address at first. When performing page
erase function, SM39R16A2 will erase entire page which flash address indicated by ISPFAH & ISPFAL registers located
within the page.
e.g. flash address: $ XYMN
page erase function will erase from $XY00 to $XYFF
To perform the chip erase ISP function, SM39R16A2 will erase all the flash program memory except the ISP service
program space. To perform chip protect ISP function, the SM39R16A2 flash memory content will be read #00H.
e.g. ISP service program to do the byte program - to program #22H to the address $1005H
MOV TAKEY, #55h
MOV TAKEY, #0AAh
MOV TAKEY, #5Ah
; enable ISPE write attribute
MOV IFCON, #01H
; enable SM39R16A2 ISP function
MOV ISPFAH, #10H
; set flash address-high, 10H
MOV ISPFAL, #05H
; set flash address-low, 05H
MOV ISPFD, #22H
; set flash data to be programmed, data = 22H
MOV ISPFC, #00H
; start to program #22H to the flash address $1005H
Specifications subject to change without notice contact your sales representatives for the most recent information.
76
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
19 Op/Comparator
SM39R16A2 had integrated an OPA/Comparator module on chip. This module supports OPA and Comparator modes
individually according to user’s configuration. When OPA Mode enabled, dual OP-Amps may be applied to single or two-stage
amplifier network, and may be applied as a front-end signal process and internally routed to specific ADC channel. When
Comparator Mode enabled, an internal reference voltage is available to be configured on comparator terminals.
If OPA and Comparator Mode both are enabled at same module, the OPA Mode has higher priority.
Mnemonic
Description
Addr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESE
T
Op/Comparator
OpPin
Cmp0CON
Cmp1CON
OpCmp Pin
Select
Comparator_
0 control
Comparator_
1 control
F6h
Op0_En Cmp0_En C0PosVBG C0PosPad
Op1_En Cmp1_En C1PosVBG C1PosPad
00h
FEh
Hys0En
Cmp0o
CMF0MS[1:0]
CMF0
--
--
ToADC
00h
FFh
Hys1En
Cmp1o
CMF1MS[1:0]
CMF1
--
--
--
00h
Mnemonic: OpPin
Address: F6h
7
6
5
4
3
2
1
0
Reset
Op0_En Cmp0_En C0PosVBG C0PosPad Op1_En Cmp1_En C1PosVBG C1PosPad
00h
Op0_En : Op0 enable.
1: Op0 circuit enables and switch to corresponding signal in multi-function
P0.3/P0.4/P0.6 by HW automatically.
Cmp0_En : Cmp0 enable.
1: Comparator_0 circuit enables and switch to corresponding signal in multi-function
P0.3/P0.4/P0.6 by HW automatically.
C0PosVBG : Select Comparator_0 positive input source
1: set positive input source as internal reference voltage (1.23V±10%)
C0PosPad: Select Comparator_0 positive input source
1: set positive input source as external pin
Op1_En: Op1 enable.
1:Op1 circuit enables and switch to corresponding signal in multi-function
P0.0/P0.1/P0.2 by HW automatically.
Cmp1_En : Cmp1 enable.
1: Comparator_1 circuit enables and switch to corresponding signal in multi-function
P0.0/P0.1/P0.2 by HW automatically.
C1PosVBG: Select Comparator_1 positive input source
1: set positive input source as internal reference voltage (1.23V±10%)
C1PosPad: Select Comparator_1 positive input source
1: set positive input source as external pin
pin
pin
pin
pin
Opx_En、Cmpx_En、CxPosVBG 及 CxPosPad setting table：
OP/Comparator
OPxPIn
OPxNIn
OPxOUT
0
0
X
X
X
IO
IO
IO
0
1
0
0
0
IO
IO
IO
Specifications subject to change without notice contact your sales representatives for the most recent information.
77
ISSFD-M057
Ver.H SM39R16A2 07/2012
Opx_En
Cmpx_En
CxPosVBG
CxPosPad
HYSxEN
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Mnemonic: Cmp0CON
7
6
5
4
Hys0En Cmp0o
CMF0MS[1:0]
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
IO
CMP
CMP
IO
IO
IO
IO
IO
OP
IO
X
IO
OP
IO
X
3
CMF0
2
-
IO
CMP
CMP
CMP
CMP
CMP
CMP
IO
OP
OP
X
IO
OP
OP
X
1
-
IO
IO
IO
IO
IO
IO
IO
IO
OP
OP
X
IO
OP
OP
X
Address:FEh
0
Reset
ToADC
00h
Hys0En: Hysteresis function enable
0: disable Hysteresis at comparator_0 input
1: enable
Cmp0o: Comparator_0 output (read only)
0: The positive input source was lower than negative input source
1: The positive input source was higher than negative input source
CMF0MS[1:0] : CMF0(Comparator_0 Flag) setting mode select
00: CMF0 will be set when comprator_0 output toggle
01: CMF0 will be set when comprator_0 output rising
10: CMF0 will be set when comprator_0 output falling
11: reserved
CMF0: Comparator_0 Flag
This bit is setting by hardware according to meet CMF0MS [1:0] select condition.
This bit must clear by software.
ToADC: Select ADC channel as input source of Op0 output
0:set ADC input source as decided by SFR ADCC2 register ADCCH [2:0]
1:set ADC input source ( another ADC channel, not ADC channel 0~7)
Mnemonic: Cmp1CON
7
6
5
4
Hys1En Cmp1o
CMF1MS[1:0]
3
CMF1
2
-
1
-
0
-
Address:FFh
Reset
00h
Hys1En: Hysteresis function enable
0: disable Hysteresis at comparator_1 input
1: enable
Cmp1o: Comparator_1 output (read only)
0: The positive input source was lower than negative input source
1: The positive input source was higher than negative input source
CMF1MS[1:0] : CMF1(Comparator_1 Flag) setting mode select
00: CMF1 will be set when comprator_1 output toggle
01: CMF1 will be set when comprator_1 output rising
10: CMF1 will be set when comprator_1 output falling
11: reserved
CMF1: Comparator_1 Flag
This bit is setting by hardware according to meet CMF1MS [1:0] select condition.
This bit must clear by software.
Specifications subject to change without notice contact your sales representatives for the most recent information.
78
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
Operating Conditions
Symbol
Description
Min.
Typ.
Max.
Unit.
Remarks
TA
Operating temperature
-40
25
85
℃
Ambient temperature under bias
VDD
Supply voltage
2.7
5.5
V
DC Characteristics
TA = -40℃ to 85℃, VCC = 5.0V
Symbol
Parameter
Valid
VIL1
Input Low-voltage
Port 0,1,2,3
VIL2
Input Low-voltage
RES, XTAL1
VIH1
Input High-voltage
Port 0,1,2,3
VIH2
Input High-voltage
RES, XTAL1
VOL
Output Low-voltage
Port 0,1,2,3
Output High-voltage
using Strong Pull-up(1)
Port 0,1,2,3
VOH1
VOH2
IIL
ITL
ILI
RRST
CIO
ICC
Notes：
Output High-voltage
using Weak Pull-up(2)
Logic 0 Input Current
Logical Transition
Current
Input Leakage Current
Port 0,1,2,3
Max
Units
Conditions
-0.5
0.8
V
0
0.8
V
2.0
VCC + 0.5
V
70%Vcc
VCC + 0.5
V
0.4
V
IOL=4.9mA
90% VCC
V
IOH= -4.6mA
2.4
V
IOH= -14mA
2.4
V
IOH= -250uA
Vcc=5V
Port 0,1,2,3
-75
uA
Vin= 0.45V
Port 0,1,2,3
-650
uA
Vin= 2.0V
Port 0,1,2,3
±10
uA
0.45V<Vin<Vcc
300
kΩ
10
pF
12
mA
11
mA
5
uA
Reset Pull-down Resistor RES
Pin Capacitance
Power Supply Current
Min
VDD
50
Vcc=5V
Freq= 1MHz, Ta= 25℃
Active mode, 12MHz VCC =5V
25 ℃
Idle mode, 12MHz VCC =5V 25
℃
Power down mode VCC =5V 25
℃
1. Port in Push-Pull Output Mode
2. Port in Quasi-Bidirectional Mode
Specifications subject to change without notice contact your sales representatives for the most recent information.
79
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
TA = -40℃ to 85℃, VCC = 3.0V
Symbol
Parameter
Valid
VIL1
Input Low-voltage
Port 0,1,2,3
VIL2
Input Low-voltage
RES, XTAL1
VIH1
Input High-voltage
Port 0,1,2,3
VIH2
Input High-voltage
RES, XTAL1
VOL
Output Low-voltage
Output High-voltage
using Strong Pull-up(1)
Output High-voltage
using Weak Pull-up(2)
Logic 0 Input Current
Logical Transition
Current
Input Leakage Current
Port 0,1,2,3
VOH1
VOH2
IIL
ITL
ILI
RRST
CIO
ICC
Notes：
Max
Units
Conditions
-0.5
0.8
V
0
0.8
V
2.0
VCC + 0.5
V
70%Vcc
VCC + 0.5
V
0.4
V
IOL=3.2mA
Vcc=3.0V
Port 0,1,2,3
90% VCC
V
IOH= -2.3mA
Port 0,1,2,3
2.4
V
IOH= -77uA
Port 0,1,2,3
-75
uA
Vin= 0.45V
Port 0,1,2,3
-650
uA
Vin=1.5V
Port 0,1,2,3
±10
uA
0.45V<Vin<Vcc
300
kΩ
10
pF
11
mA
10
mA
4
uA
Reset Pull-down Resistor RES
Pin Capacitance
Power Supply Current
Min
VDD
50
Vcc=3.0V
Freq= 1MHz, Ta= 25℃
Active mode ,12MHz VCC = 3.0
V 25 ℃
Idle mode, 12MHz VCC =3.0V
25 ℃
Power down mode VCC =3.0V
25 ℃
1. Port in Push-Pull Output Mode
2. Port in Quasi-Bidirectional Mode
Specifications subject to change without notice contact your sales representatives for the most recent information.
80
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
OPA / Comparator Characteristics
VCC = 5.0V
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VOS
Input Offset Voltage
No load
3
5
mV
VOUT
Output Voltage Swing
RL=15KΩ CL=100pF
VIN+ - VIN- >200mV
0.1
VDD - 0.4
V
BW
Gain Band Width
Product
RL=10KΩ CL=100pF
0.4
0.5
0.55
MHz
CMRR
Common Mode
Rejection Ratio
No load
65
70
72
dB
PSRR
Power Supply Rejection
Ratio
No load
75
80
84
dB
SR
Slew Rate at Unity Gain
No load
0.57
0.7
0.78
V/us
RL
MAX. load
RL=10KΩ CL=100pF
H
Hysteresis
No load
>15
20
40
KΩ
60
mV
Specifications subject to change without notice contact your sales representatives for the most recent information.
81
ISSFD-M057
Ver.H SM39R16A2 07/2012
SM39R16A2/SM39R12A2/SM39R08A2
8-Bit Micro-controller
16KB/12KB/8KB with ISP Flash
& 256B RAM embedded
VCC = 3.0V
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VOS
Input Offset Voltage
No load
3
5
mV
VOUT
Output Voltage Swing
RL=15KΩ CL=100pF
VIN+ -VIN- >200mV
0.1
VDD – 0.4
V
BW
Gain Band Width
Product
RL=10KΩ CL=100pF
0.4
0.5
0.55
MHz
CMRR
Common Mode
Rejection Ratio
No load
60
65
68
dB
PSRR
Power Supply Rejection
Ratio
No load
60
65
68
dB
SR
Slew Rate at Unity Gain
No load
0.57
0.7
0.78
V/us
RL
MAX. load
RL=10KΩ CL=100pF
H
Hysteresis
No load
>15
20
40
KΩ
60
mV
Specifications subject to change without notice contact your sales representatives for the most recent information.
82
ISSFD-M057
Ver.H SM39R16A2 07/2012