SYNCMOS SM39R4051W20

SM39R4051/SM39R2051
8-Bit Micro-controller
FOSVOS TEL: 021-58998693
4KB/2KB with ISP Flash
& 256B RAM embedded
Description ..........................................................................................................................................................................3
Features..............................................................................................................................................................................3
Pin Configuration ................................................................................................................................................................4
Block Diagram.....................................................................................................................................................................5
Pin Description....................................................................................................................................................................6
Special Function Register (SFR) ........................................................................................................................................7
Function Description ...........................................................................................................................................................9
1.
General Features .......................................................................................................................................................9
1.1.
Embedded Flash ...........................................................................................................................................9
1.2.
IO Pads .........................................................................................................................................................9
1.3.
Instruction timing Selection ...........................................................................................................................9
1.4.
RESET ........................................................................................................................................................10
1.4.1.
Hardware RESET function .............................................................................................................10
1.4.2.
Software RESET function ..............................................................................................................10
1.4.3.
Time Access Key register (TAKEY)................................................................................................10
1.4.4.
Software Reset register (SWRES).................................................................................................11
1.4.5.
Example of software reset .............................................................................................................11
1.5.
Clocks .........................................................................................................................................................11
2.
Instruction Set ..........................................................................................................................................................12
3.
Memory Structure.....................................................................................................................................................16
3.1.
Program Memory ........................................................................................................................................16
3.2.
Data Memory...............................................................................................................................................17
3.2.1.
Data memory - lower 128 byte (00h to 7Fh) ..................................................................................18
3.2.2.
Data memory - higher 128 byte (80h to FFh) ................................................................................18
4.
CPU Engine .............................................................................................................................................................19
4.1.
Accumulator ................................................................................................................................................19
4.2.
B Register ...................................................................................................................................................19
4.3.
Program Status Word..................................................................................................................................20
4.4.
Stack Pointer ...............................................................................................................................................20
4.5.
Data Pointer ................................................................................................................................................20
4.6.
Data Pointer 1 .............................................................................................................................................21
4.7.
Interface control register .............................................................................................................................21
5.
GPIO ........................................................................................................................................................................22
6.
Timer 0 and Timer 1 .................................................................................................................................................24
6.1.
Timer/counter mode control register (TMOD) .............................................................................................24
6.2.
Timer/counter control register (TCON) .......................................................................................................25
6.3.
T0、T1 signal swapping：..........................................................................................................................25
7.
Serial interface 0 ......................................................................................................................................................26
7.1.
Mode 0 ........................................................................................................................................................27
7.2.
Mode 1 ........................................................................................................................................................27
7.3.
Mode 2 ........................................................................................................................................................28
7.4.
Mode 3 ........................................................................................................................................................28
7.5.
Multiprocessor communication of Serial Interface 0 ...................................................................................28
7.6.
Baud rate generator ....................................................................................................................................29
7.6.1.
Serial interface 0 modes 1 and 3 ...................................................................................................29
7.6.2.
Clock source for baud rate.............................................................................................................29
8.
Watchdog timer ........................................................................................................................................................30
9.
Interrupt ....................................................................................................................................................................33
9.1.
Priority level structure..................................................................................................................................35
10.
Power Management Unit.................................................................................................................................36
10.1.
Idle mode ................................................................................................................................................36
10.2.
Stop mode...............................................................................................................................................36
11.
IIC function ......................................................................................................................................................37
12.
LVI – Low Voltage Interrupt .............................................................................................................................41
13.
In-System Programming (Internal ISP) ...........................................................................................................42
13.1.
ISP service program ...............................................................................................................................42
13.2.
Lock Bit (N) .............................................................................................................................................42
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M055
1
Ver.E SM39R4051 09/2011
SM39R4051/SM39R2051
8-Bit Micro-controller
4KB/2KB with ISP Flash
& 256B RAM embedded
13.3.
Program the ISP Service Program .........................................................................................................43
13.4.
Initiate ISP Service Program...................................................................................................................43
13.5.
ISP register – TAKEY, IFCON, ISPFAH, ISPFAL, ISPFD and ISPFC ....................................................43
Operating Conditions ........................................................................................................................................................46
DC Characteristics ............................................................................................................................................................46
FOSVOS TEL: 021-58998693
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M055
2
Ver.E SM39R4051 09/2011
SM39R4051/SM39R2051
8-Bit Micro-controller
4KB/2KB with ISP Flash
& 256B RAM embedded
Product List
Features
SM39R4051W20, SM39R2051W20
z
z
Description
The original 8052 had 12-clock architecture. A machine
cycle needed 12 clocks and most instructions were either
one or two machine cycles. Thus except for the MUL and
DIV instructions, the 8052 used either 12 or 24 clocks for
each instruction. Furthermore, each cycle in the 8052
used two memory fetches. In many cases the second
fetch was dummy, and extra clocks were wasted.
The SM39R4051 is a core of a fast single-chip 8-bit
microcontroller. It is a fully functional 8-bit embedded
controller that executes all ASM51 instructions and has
the same instruction set as the MCS-51.
Ordering Information
SM39R4051ihhkL yymmv
i: process identifier {W = 2.7V ~ 5.5V}
hh: pin count
k: package type postfix {as table below }
L:PB Free identifier
{No text is Non-PB free，”P” is PB free}
yy: year
mm: month
v: version identifier{ A, B,…}
Postfix
Package
N
S
PDIP (300 mil)
SOP (300 mil)
Pin / Pad
Configuration
Page 4
Page 4
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
Operating Voltage: 2.7V ~ 5.5V
High speed architecture of 1 clock/machine cycle
runs up to 25MHz.
1~8T modes are software programmable.
Instruction-set compatible with MCS-51.
Internal OSC with range 1MHz~24MHz
4K/2K Bytes on-chip flash program memory.
256 bytes RAM as standard 8052,
One serial peripheral interfaces in full duplex mode.
„
Synchronous mode, fixed baud rate,
„
8-bit UART mode, variable baud rate.
„
9-bit UART mode, fixed baud rate,
„
9-bit UART mode, variable baud rate.
Additional Baud Rate Generator
Two 16-bit Timer/Counters. (Timer 0, 1)
18 GPIOs(20L PDIP&SOP)
Programmable watchdog timer.
One IIC interface. (Master/Slave mode)
On–chip flash memories support ISP/IAP/ICP and
EEPROM functions.
ISP service program space configurable in N*256
byte (N=0 to 4) size.
On-Chip in-circuit emulator (ICE) functions with
On-Chip Debugger (OCD).
EMI reduction mode (ALE output inhibited).
LVI/LVR.
IO PAD ESD over 4KV.
Enhance user code protection.
External interrupt 0, 1 with four priority levels.
Power management unit for IDLE and power down
modes.
FOSVOS TEL: 021-58998693
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M055
3
Ver.E SM39R4051 09/2011
SM39R4051/SM39R2051
8-Bit Micro-controller
4KB/2KB with ISP Flash
& 256B RAM embedded
Pin Configuration
SyncMOS
SM39R4051ihhNP
yymmv
(20L PDIP Top View)
P3.6/RESET(default)
20
VCC
INT0/T0/RXD/P3.0
2
19
P1.7
INT1/T1/TXD/P3.1
3
18
P1.6
P4.0/XTAL2
4
17
P1.5/INT1/T1
P4.1/XTAL1
5
16
P1.4/RESET/INT0/T0
INT0/P3.2
6
15
P1.3/T1
INT1/P3.3
7
14
P1.2/T0
T0/P3.4
8
13
P1.1/SCL
T1/P3.5
9
12
P1.0/SDA
VSS
10
11
P3.7
SyncMOS
(20L SOP Top View)
yymmv
SM39R4051ihhSP
1
Notes：
1. The pin Reset/P3.6 factory default is Reset, user must keep this pin at low during power-up. User can configure it to
GPIO (P3.6) by a flash programmer.
2. To avoid accidentally entering ISP-Mode(refer to section 13.4), care must be taken not asserting pulse signal at P3.0
during power-up while P1.5 are set to high.
3. To apply ICP function, SDA/P1.0 and SCL/P1.1 must be set to Bi-direction mode if they are configured as GPIO in
system.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M055
4
Ver.E SM39R4051 09/2011
SM39R4051/SM39R2051
8-Bit Micro-controller
4KB/2KB with ISP Flash
& 256B RAM embedded
Block Diagram
RESET
XTAL2
XTAL1
MAX810
UART 0
IIC
SRAM
256Bytes
Port 1
Port 1
Port 3
Port 3
Port 4
Port 4
Timer 0/1
T0
T1
Flash 4KBytes
Watchdog
Interrupt
ICE
ICP
Interface control
FOSVOS TEL: 021-58998693
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M055
5
Ver.E SM39R4051 09/2011
SM39R4051/SM39R2051
8-Bit Micro-controller
4KB/2KB with ISP Flash
& 256B RAM embedded
Pin Description
20L
PDIP/SOP
1
Symbol
I/O
Description
RESET(default)/ P3.6
I/O
2
P3.0/RXD/#INT0/T0
I/O
3
P3.1/TXD/#INT1/T1
I/O
4
5
6
7
8
9
10
11
XTAL2/P4.0
XTAL1/P4.1
P3.2/#INT0
P3.3/#INT1
P3.4/T0
P3.5/T1
VSS
P3.7
I/O
I/O
I/O
I/O
I/O
I/O
I
I/O
12
P1.0/SDA
I/O
13
P1.1/SCL
I/O
14
15
16
17
18
19
20
P1.2/T0
P1.3/T1
P1.4/#INT0/T0/RESET
P1.5/#INT1/T1
P1.6
P1.7
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I
Reset pin(default) & Bit 6 of port 3
Bit 0 of port 3 & Serial interface channel receive/transmit data & (External
interrupt 0 or Timer 0 external input)
Bit 1 of port 3 & Serial interface channel transmit data or receive clock in
mode 0 & (External interrupt 1 or Timer 1 external input)
Crystal output & Bit 0 of port 4
Crystal input & Bit 1 of port 4
Bit 2 of port 3 & External interrupt 0
Bit 3 of port 3 & External interrupt 1
Bit 4 of port 3 & Timer 0 external input
Bit 5 of port 3 & Timer 1 external input
Power supply
Bit 7 of port 3
Bit 0 of port 1 & On-Chip Instrumentation Command and data I/O pin
synchronous to OCI_SCL in ICE and ICP functions
Bit 1 of port 1 & On-Chip Instrumentation Clock I/O pin of ICE and ICP
functions
Bit 2 of port 1 & Timer 0 external input
Bit 3 of port 1 & Timer 1 external input
Bit 4 of port 1 & (External interrupt 0 or Timer 0 external input or RESET)
Bit 5 of port 1 & (External interrupt 1 or Timer 1 external input)
Bit 6 of port 1
Bit 7 of port 1
Power supply
The Special Function Pin Can configured as below Table (Can be Select By SFR)：
Signal
Default
Option1
Option2
Option3
#INT0
6(P3.2)
2(P3.0)
15(P1.3)
16(P1.4)
#INT1
7(P3.3)
3(P3.1)
14(P1.2)
17(P1.5)
T0
8(P3.4)
14(P1.2)
16(P1.4)
2(P3.0)
T1
9(P3.5)
15(P1.3)
17(P1.5)
3(P3.1)
The RESET Pin Can configured as below Table (Can be Select By ICP or ISP )：
Signal
Default
Option1
RESET
1
16
The RESET Pin Can Be configured as I/O port P3.6，when user use on-chip hardware RESET mechanism。
The XTAL2 can be configured as I/O port P4.0 by ICP or in ISP mode.，when user use Oscillator (XTAL1 as clock input) or
on-chip RC Oscillator is set to main system clock source。
The XTAL1 can be configured as I/O port P4.1 by ICP or in ISP mode，when user use on-chip RC Oscillator is set to main
system clock source。
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M055
6
Ver.E SM39R4051 09/2011
SM39R4051/SM39R2051
8-Bit Micro-controller
4KB/2KB with ISP Flash
& 256B RAM embedded
Special Function Register (SFR)
A map of the Special Function Registers is shown as below:
Hex\Bin
F8
X000
IICS
F0
B
E8
E0
D8
P4
ACC
D0
PSW
C8
C0
B8
IRCON
IEN1
B0
P3
A8
A0
98
IEN0
S0CON
X001
IICCTL
ISPFAH
IP1
X011
IICA2
ISPFAL
P3M0
ISPFD
P3M1
X100
IICRWD
X101
IICEBT
X110
IP0
X111
TAKEY
F7
SWRES
ISPFC
P4M0
P4M1
P1M0
P1M1
D7
LVC
CF
C7
BF
S0RELH
WDTK
S0RELL
P1WE
P3WE
P1
AUX
TCON
TMOD
SP
X001
TL1
DPH
X011
TH0
DPL1
X100
B7
AF
A7
9F
S0BUF
88
80
Hex\Bin
Bin/Hex
FF
EF
E7
DF
WDTC
90
X000
X010
IICA1
97
TL0
DPL
X010
TH1
DPH1
X101
CKCON
X110
IFCON
PCON
X111
8F
87
Bin/Hex
Note: Special Function Registers reset values and description for SM39R4051
Register
Location
Reset value
SP
DPL
DPH
DPL1
DPH1
PCON
81h
82h
83h
84h
85h
87h
07h
00h
00h
00h
00h
40h
Stack Pointer
Data Pointer 0 low byte
Data Pointer 0 high byte
Data Pointer 1 low byte
Data Pointer 1 high byte
Power Control
Description
TCON
TMOD
TL0
TL1
TH0
TH1
CKCON
IFCON
P1
AUX
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
00h
00h
00h
00h
00h
00h
10h
40h
FFh
00h
Timer/Counter Control
Timer Mode Control
Timer 0, low byte
Timer 1, low byte
Timer 0, high byte
Timer 1, high byte
Clock control register
Interface control register
Port 1
Auxiliary register
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M055
7
Ver.E SM39R4051 09/2011
SM39R4051/SM39R2051
8-Bit Micro-controller
4KB/2KB with ISP Flash
& 256B RAM embedded
Register
Location
Reset value
S0CON
S0BUF
P1WE
P3WE
98h
99h
A3h
A4h
00h
00h
FFh
FFh
Serial Port 0, Control Register
Serial Port 0, Data Buffer
Port 1 output enable
Port 3 output enable
Description
IEN0
IP0
S0RELL
P3
WDTC
WDTK
IEN1
IP1
A8h
A9h
AAh
B0h
B6h
B7h
B8h
B9h
00h
00h
00h
FFh
04h
00h
00h
00h
Interrupt Enable Register 0
Interrupt Priority Register 0
Serial Port 0, Reload Register, low byte
Port 3
Watchdog timer control register
Watchdog timer refresh key.
Interrupt Enable Register 1
Interrupt Priority Register 1
S0RELH
IRCON
PSW
P1M0
P1M1
P3M0
P3M1
P4M0
BAh
C0h
D0h
D4h
D5h
DAh
DBh
DCh
00h
00h
00h
00h
00h
00h
00h
00h
Serial Port 0, Reload Register, high byte
Interrupt Request Control Register
Program Status Word
Port 1 output mode 0
Port 1 output mode 1
Port 3 output mode 0
Port 3 output mode 1
Port 4 output mode 0
P4M1
ACC
ISPFAH
ISPFAL
ISPFD
ISPFC
LVC
SWRES
DDh
E0h
E1h
E2h
E3h
E4h
E6h
E7h
00h
00h
FFh
FFh
FFh
00h
20h
00h
Port 4 output mode 1
Accumulator
ISP Flash Address-High register
ISP Flash Address-Low register
ISP Flash Data register
ISP Flash control register
Low voltage control register
Software Reset register
P4
B
TAKEY
IICS
IICCTL
IICA1
IICA2
IICRWD
E8h
F0h
F7h
F8h
F9h
FAh
FBh
FCh
FFh
00h
00h
00h
04h
A0h
60h
00h
Port 4
B Register
Time Access Key register
IIC status register
IIC control register
IIC channel 1 Address 1 register
IIC channel 1 Address 2 register
IIC channel 1 Read / Write Data buffer
IICS2
FDh
00h
IIC status2 register
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M055
8
Ver.E SM39R4051 09/2011
SM39R4051/SM39R2051
8-Bit Micro-controller
4KB/2KB with ISP Flash
& 256B RAM embedded
Function Description
1. General Features
SM39R4051 is an 8-bit micro-controller。All of its functions and the detailed meanings of SFR will be given in the following
sections。
1.1.
Embedded Flash
The program can be loaded into the embedded 4KB/2KB Flash memory via its writer or In-System Programming (ISP)。
The high-quality Flash has a 100K-write cycle life，suitable for re-programming and data recording as EEPROM。
1.2.
IO Pads
The SM39R4051 has three I/O ports: Port 1, Port 3 and Port 4. Ports 1, 3 are 8-bit ports and Port 4 is a 2-bit port. These
are: quasi-bidirectional (standard 8051 port outputs), push-pull, open drain, and input-only. As description in section 5。
At 20L Package (DIP/SOP)，the Int0、Int1、T0、T0 signal can be configured to other I/O as below：
Signal
Default
Option1
Option2
Option3
#INT0
6(P3.2)
2(P3.0)
15(P1.3)
16(P1.4)
#INT1
7(P3.3)
3(P3.1)
14(P1.2)
17(P1.5)
T0
8(P3.4)
14(P1.2)
16(P1.4)
2(P3.0)
T1
9(P3.5)
15(P1.3)
17(P1.5)
3(P3.1)
The RESET Pin Can Be configured as I/O port P3.6，when user use on-chip hardware RESET mechanism。
The XTAL2 and XTAL1 can be configured as I/O port by ICP or in ISP mode，when user use external OSC or on-chip RC
Oscillator is set to main system clock source，show as below：
20L package
Xtal1
Xtal2
External OSC
Xtal1
P4.0
Internal OSC
P4.1
P4.0
All the pins on P1、P3 and P4 are with slew rate adjustment to reduce EMI. The other way to reduce EMI is to disable the
ALE output if unused. This is selected by its SFR. The IO pads can withstand 4KV ESD in human body mode
guaranteeing the SM39R4051’s quality in high electro-static environments.
1.3.
Instruction timing Selection
The conventional 52-series MCUs are 12T, i.e., 12 oscillator clocks per machine cycle. SM39R4051 is a 1T to 8T MCU,
i.e., its machine cycle is one-clock to eight-clock. In the other words, it can execute one instruction within one clock to only
eight clocks.
Mnemonic: CKCON
7
6
5
ITS
4
3
-
2
-
1
-
Address: 8Eh
0
Reset
10H
ITS: Instruction timing select.
ITS [6:4]
Instruction timing
000
1T mode
001
2T mode (default)
010
3T mode
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M055
9
Ver.E SM39R4051 09/2011
SM39R4051/SM39R2051
8-Bit Micro-controller
4KB/2KB with ISP Flash
& 256B RAM embedded
011
100
101
110
111
4T mode
5T mode
6T mode
7T mode
8T mode
The default is in 2T mode, and it can be changed to another Instruction timing mode if CKCON [6:4] (at address 8Eh) is
change any time. Not every instruction can be executed with one machine cycle. The exact machine cycle number for all
the instructions are given in the next section.
1.4.
1.4.1.
RESET
Hardware RESET function
SM39R4051 provides on-chip hardware RESET mechanism,，the reset duration is programmable by writer or ISP。
on-chip hardware RESET duration
25ms (default)
200ms
100ms
50ms
16ms
8ms
4ms
1.4.2.
Software RESET function
SM39R4051 provides one software reset mechanism to reset whole chip. To perform a software reset, the firmware must
write three specific values 55h, AAh and 5Ah sequentially to the TAKEY register to enable the Software Reset register
(SWRES) write attribute. After SWRES register obtain the write authority, the firmware can write FFh to the SWRES
register. The hardware will decode a reset signal that “OR” with the other hardware reset. The SWRES register is
self-reset at the end of the software reset procedure.
Mnemonic
TAKEY
SWRES
1.4.3.
Description
Time Access Key
register
Software Reset
register
Direct
Bit 7
Bit 6
Bit 5
Bit 4
Software Reset function
Bit 3
Bit 2
Bit 1
Bit 0
RESET
F7h
TAKEY [7:0]
00H
E7h
SWRES [7:0]
00H
Time Access Key register (TAKEY)
Mnemonic: TAKEY
7
6
5
4
3
TAKEY [7:0]
2
1
Address: F7H
0
Reset
00H
Software reset register (SWRES) is read-only by default; software must write three specific values
55h, AAh and 5Ah sequentially to the TAKEY register to enable the SWRES register write attribute. That
is:
MOV TAKEY, #55h
MOV TAKEY, #0AAh
MOV TAKEY, #5Ah
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M055
10
Ver.E SM39R4051 09/2011
SM39R4051/SM39R2051
8-Bit Micro-controller
4KB/2KB with ISP Flash
& 256B RAM embedded
1.4.4.
Software Reset register (SWRES)
Mnemonic: SWRES
7
6
5
4
3
SWRES [7:0]
2
1
Address: E7H
0
Reset
00H
SWRES [7:0]: Software reset register bit. These 8-bit is self-reset at the end of the reset procedure.
SWRES [7:0] = FFh, software reset.
SWRES [7:0] = 00h ~ FEh, MCU no action.
1.4.5.
Example of software reset
MOV TAKEY, #55h
MOV TAKEY, #0AAh
MOV TAKEY, #5Ah ; enable SWRES write attribute
MOV SWRES, #0FFh ; software reset MCU
1.5.
Clocks
The default clock is the external crystal. This clock is used during the initialization stage. The major work of the
initialization stage is to determine the clock source used in normal operation.
The internal clock sources are from the on-chip RC-Oscillator with programmable frequency outputs as table 1-1，the
clock source can set by writer or ICP。
Table 1-1: Selection of clock source
Clock source
external crystal (use XTAL1 and XTAL2 pins ) (default)
external crystal (only use XTAL1, the XTAL2 define as I/O)
20MHz from on-chip RC-Oscillator
16MHz from on-chip RC-Oscillator
12MHz from on-chip RC-Oscillator
8MHz from on-chip RC-Oscillator
4MHz from on-chip RC-Oscillator
2MHz from on-chip RC-Oscillator
1MHz from on-chip RC-Oscillator
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M055
11
Ver.E SM39R4051 09/2011
SM39R4051/SM39R2051
8-Bit Micro-controller
4KB/2KB with ISP Flash
& 256B RAM embedded
2. Instruction Set
All SM39R4051 instructions are binary code compatible and perform the same functions as they do with the industry
standard 8051. The following tables give a summary of the instruction set cycles of the SM39R4051 Microcontroller core.
Mnemonic
ADD A,Rn
ADD A,direct
Table 2-1: Arithmetic operations
Description
Add register to accumulator
Add direct byte to accumulator
Code
28-2F
25
Bytes
1
2
Cycles
1
2
ADD A,@Ri
Add indirect RAM to accumulator
26-27
1
2
ADD A,#data
ADDC A,Rn
ADDC A,direct
Add immediate data to accumulator
Add register to accumulator with carry flag
Add direct byte to A with carry flag
24
38-3F
35
2
1
2
2
1
2
ADDC A,@Ri
Add indirect RAM to A with carry flag
36-37
1
2
ADDC A,#data
SUBB A,Rn
SUBB A,direct
Add immediate data to A with carry flag
Subtract register from A with borrow
Subtract direct byte from A with borrow
34
98-9F
95
2
1
2
2
1
2
SUBB A,@Ri
Subtract indirect RAM from A with borrow
96-97
1
2
SUBB A,#data
INC A
INC Rn
INC direct
Subtract immediate data from A with borrow
Increment accumulator
Increment register
Increment direct byte
94
04
08-0F
05
2
1
1
2
2
1
2
3
INC @Ri
INC DPTR
DEC A
DEC Rn
Increment indirect RAM
Increment data pointer
Decrement accumulator
Decrement register
06-07
A3
14
18-1F
1
1
1
1
3
1
1
2
DEC direct
DEC @Ri
MUL AB
DIV
DA A
Decrement direct byte
Decrement indirect RAM
Multiply A and B
Divide A by B
Decimal adjust accumulator
15
16-17
A4
84
D4
2
1
1
1
1
3
3
5
5
1
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M055
12
Ver.E SM39R4051 09/2011
SM39R4051/SM39R2051
8-Bit Micro-controller
4KB/2KB with ISP Flash
& 256B RAM embedded
Mnemonic
ANL A,Rn
ANL A,direct
Table 2-2: Logic operations
Description
AND register to accumulator
AND direct byte to accumulator
Code
58-5F
55
Bytes
1
2
Cycles
1
2
ANL A,@Ri
ANL A,#data
ANL direct,A
ANL direct,#data
AND indirect RAM to accumulator
AND immediate data to accumulator
AND accumulator to direct byte
AND immediate data to direct byte
56-57
54
52
53
1
2
2
3
2
2
3
4
ORL A,Rn
ORL A,direct
ORL A,@Ri
ORL A,#data
OR register to accumulator
OR direct byte to accumulator
OR indirect RAM to accumulator
OR immediate data to accumulator
48-4F
45
46-47
44
1
2
1
2
1
2
2
2
ORL direct,A
ORL direct,#data
XRL A,Rn
XRL A,direct
OR accumulator to direct byte
OR immediate data to direct byte
Exclusive OR register to accumulator
Exclusive OR direct byte to accumulator
42
43
68-6F
65
2
3
1
2
3
4
1
2
XRL A,@Ri
Exclusive OR indirect RAM to accumulator
66-67
1
2
XRL A,#data
Exclusive OR immediate data to accumulator
64
2
2
XRL direct,A
XRL direct,#data
CLR A
Exclusive OR accumulator to direct byte
Exclusive OR immediate data to direct byte
Clear accumulator
62
63
E4
2
3
1
3
4
1
CPL A
Complement accumulator
F4
1
1
RL A
RLC A
RR A
Rotate accumulator left
Rotate accumulator left through carry
Rotate accumulator right
23
33
03
1
1
1
1
1
1
RRC A
Rotate accumulator right through carry
13
1
1
SWAP A
Swap nibbles within the accumulator
C4
1
1
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M055
13
Ver.E SM39R4051 09/2011
SM39R4051/SM39R2051
8-Bit Micro-controller
4KB/2KB with ISP Flash
& 256B RAM embedded
Mnemonic
MOV A,Rn
MOV A,direct
Table 2-3: Data transfer
Description
Move register to accumulator
Move direct byte to accumulator
Code
E8-EF
E5
Bytes
1
2
Cycles
1
2
MOV A,@Ri
MOV A,#data
MOV Rn,A
MOV Rn,direct
Move indirect RAM to accumulator
Move immediate data to accumulator
Move accumulator to register
Move direct byte to register
E6-E7
74
F8-FF
A8-AF
1
2
1
2
2
2
2
4
MOV Rn,#data
MOV direct,A
MOV direct,Rn
MOV direct1,direct2
Move immediate data to register
Move accumulator to direct byte
Move register to direct byte
Move direct byte to direct byte
78-7F
F5
88-8F
85
2
2
2
3
2
3
3
4
MOV direct,@Ri
MOV direct,#data
MOV @Ri,A
MOV @Ri,direct
Move indirect RAM to direct byte
Move immediate data to direct byte
Move accumulator to indirect RAM
Move direct byte to indirect RAM
86-87
75
F6-F7
A6-A7
2
3
1
2
4
3
3
5
MOV @Ri,#data
Move immediate data to indirect RAM
76-77
2
3
MOV DPTR,#data16
Load data pointer with a 16-bit constant
90
3
3
MOVC A,@A+DPTR
MOVC A,@A+PC
PUSH direct
Move code byte relative to DPTR to accumulator
Move code byte relative to PC to accumulator
Push direct byte onto stack
93
83
C0
1
1
2
3
3
4
POP direct
XCH A,Rn
XCH A,direct
XCH A,@Ri
XCHD A,@Ri
Pop direct byte from stack
Exchange register with accumulator
Exchange direct byte with accumulator
Exchange indirect RAM with accumulator
Exchange low-order nibble indir. RAM with A
D0
C8-CF
C5
C6-C7
D6-D7
2
1
2
1
1
3
2
3
3
3
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M055
14
Ver.E SM39R4051 09/2011
SM39R4051/SM39R2051
8-Bit Micro-controller
4KB/2KB with ISP Flash
& 256B RAM embedded
Mnemonic
ACALL addr11
LCALL addr16
Table 2-4: Program branches
Description
Absolute subroutine call
Long subroutine call
Code
xxx11
12
Bytes
2
3
Cycles
6
6
RET
RETI
AJMP addr11
LJMP addr16
from subroutine
from interrupt
Absolute jump
Long iump
22
32
xxx01
02
1
1
2
3
4
4
3
4
SJMP rel
JMP @A+DPTR
JZ rel
JNZ rel
Short jump (relative addr.)
Jump indirect relative to the DPTR
Jump if accumulator is zero
Jump if accumulator is not zero
80
73
60
70
2
1
2
2
3
2
3
3
JC rel
JNC
JB bit,rel
JNB bit,rel
Jump if carry flag is set
Jump if carry flag is not set
Jump if direct bit is set
Jump if direct bit is not set
40
50
20
30
2
2
3
3
3
3
4
4
JBC bit,direct rel
Jump if direct bit is set and clear bit
10
3
4
CJNE A,direct rel
Compare direct byte to A and jump if not equal
B5
3
4
CJNE A,#data rel
CJNE Rn,#data rel
CJNE @Ri,#data rel
Compare immediate to A and jump if not equal
Compare immed. to reg. and jump if not equal
Compare immed. to ind. and jump if not equal
B4
B8-BF
B6-B7
3
3
3
4
4
4
DJNZ Rn,rel
Decrement register and jump if not zero
D8-DF
2
3
DJNZ direct,rel
NOP
Decrement direct byte and jump if not zero
No operation
D5
00
3
1
4
1
Mnemonic
CLR C
CLR bit
Table 2-5: Boolean manipulation
Description
Clear carry flag
Clear direct bit
Code
C3
C2
SETB C
SETB bit
CPL C
CPL bit
Set carry flag
Set direct bit
Complement carry flag
Complement direct bit
ANL C,bit
ANL C,/bit
ORL C,bit
ORL C,/bit
MOV C,bit
MOV bit,C
Bytes
1
2
Cycles
1
3
D3
D2
B3
B2
1
2
1
2
1
3
1
3
AND direct bit to carry flag
AND complement of direct bit to carry
OR direct bit to carry flag
OR complement of direct bit to carry
82
B0
72
A0
2
2
2
2
2
2
2
2
Move direct bit to carry flag
Move carry flag to direct bit
A2
92
2
2
2
3
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M055
15
Ver.E SM39R4051 09/2011
SM39R4051/SM39R2051
8-Bit Micro-controller
4KB/2KB with ISP Flash
& 256B RAM embedded
3. Memory Structure
The SM39R4051 memory structure follows general 8052 structure. It is 4KB program memory.
3.1.
Program Memory
The SM39R4051 has 4KB on-chip flash memory which can be used as general program memory or EEPROM, on which
include up to 1K byte specific ISP service program memory space. The address range for the 4K byte is $000 to $FFF.
The address range for the ISP service program is $C00 to $FFF. The ISP service program size can be partitioned as N
blocks of 256 byte (N=0 to 4). When N=0 means no ISP service program space available, total 4K byte memory used as
program memory. When N=1 means address $F00 to $FFF reserved for ISP service program. When N=2 means memory
address $E00 to $FFF reserved for ISP service program…etc. Value N can be set and programmed into SM39R4051 by
the writer or ICP. It can be used to record any data as EEPROM. The procedure of this EEPROM application function is
described in the section 13 on internal ISP.
N=0
FFF
N=1
F00
ISP service
Program space,
Up to 1K
N=2
E00
N=3
D00
C00
N=4
4K Program
Memory space
000
Fig. 3-1: SM39R4051 programmable Flash
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M055
16
Ver.E SM39R4051 09/2011
SM39R4051/SM39R2051
8-Bit Micro-controller
4KB/2KB with ISP Flash
& 256B RAM embedded
FFF
N=0
F00
ISP service
Program space,
Up to 1K
N=1
N=2
E00
D00
C00
N=3
N=4
300
1K Program
Memory space
000
Fig. 3-2 : SM39R2051 programmable Flash
3.2. Data Memory
The SM39R4051 has 256Bytes on-chip SRAM; 256 Bytes of it are the same as general 8052 internal memory structure
FF
FF
Higher 128 Bytes (Accessed by
indirect addressing mode only)
80
7F
SFR (Accessed by direct addressing
mode only)
80
Lower 128 Bytes (Accessed by
direct & indirect addressing mode )
00
Fig. 3-3: RAM architecture
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M055
17
Ver.E SM39R4051 09/2011
SM39R4051/SM39R2051
8-Bit Micro-controller
4KB/2KB with ISP Flash
& 256B RAM embedded
3.2.1.
Data memory - lower 128 byte (00h to 7Fh)
Data memory 00h to FFh is the same as 8052.
The address 00h to 7Fh can be accessed by direct and indirect addressing modes.
Address 00h to 1Fh is register area.
Address 20h to 2Fh is memory bit area.
Address 30h to 7Fh is for general memory area.
3.2.2.
Data memory - higher 128 byte (80h to FFh)
The address 80h to FFh can be accessed by indirect addressing mode.
Address 80h to FFh is data area.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M055
18
Ver.E SM39R4051 09/2011
SM39R4051/SM39R2051
8-Bit Micro-controller
4KB/2KB with ISP Flash
& 256B RAM embedded
4. CPU Engine
The SM39R4051 engine is composed of four components:
a. Control unit
b. Arithmetic – logic unit
c. Memory control unit
d. RAM and SFR control unit
The SM39R4051 engine allows to fetch instruction from program memory and to execute using RAM or SFR. The
following chapter describes the main engine register.
Mnemonic
Description
Direct
Bit 7
ACC
B
Accumulator
B register
Program status
word
Stack Pointer
Data pointer low 0
Data pointer high
0
Data pointer low 0
Data pointer high
0
Auxiliary register
Interface control
register
E0h
F0h
ACC.7
B.7
D0h
CY
PSW
SP
DPL
DPH
DPL1
DPH1
AUX
IFCON
4.1.
Bit 6
Bit 5
8051 Core
ACC.6 ACC.5
B.6
B.5
AC
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESET
ACC.4
B.4
ACC.3
B.3
ACC.2
B.2
ACC.1
B.1
ACC.0
B.0
00H
00H
OV
PSW.1
P
00H
F0
RS[1:0]
81h
82h
SP[7:0]
DPL[7:0]
07H
00H
83h
DPH[7:0]
00H
84h
DPL1[7:0]
00H
85h
DPH1[7:0]
00H
91h
BRGS
-
-
8Fh
-
CDPR
-
PTS[1:0]
-
-
PINTS[1:0]
DPS
00H
-
ISPE
00H
-
Accumulator
ACC is the Accumulator register. Most instructions use the accumulator to store the operand.
Mnemonic: ACC
7
6
ACC.7 ACC.6
5
ACC05
4
ACC.4
3
ACC.3
2
ACC.2
1
ACC.1
Address: E0h
0
Reset
ACC.0
00h
ACC[7:0]: The A (or ACC) register is the standard 8052 accumulator.
4.2.
B Register
The B register is used during multiply and divide instructions. It can also be used as a scratch pad register to store
temporary data.
Mnemonic: B
7
6
B.7
B.6
5
B.5
4
B.4
3
B.3
2
B.2
1
B.1
Address: F0h
0
Reset
B.0
00h
B[7:0]: The B register is the standard 8052 register that serves as a second accumulator.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M055
19
Ver.E SM39R4051 09/2011
SM39R4051/SM39R2051
8-Bit Micro-controller
4KB/2KB with ISP Flash
& 256B RAM embedded
4.3.
Program Status Word
Mnemonic: PSW
7
6
CY
AC
5
F0
4
3
RS [1:0]
2
OV
1
F1
Address: D0h
0
Reset
P
00h
CY: Carry flag.
AC: Auxiliary Carry flag for BCD operations.
F0: General purpose Flag 0 available for user.
RS[1:0]: Register bank select, used to select working register bank.
RS[1:0]
Bank Selected
Location
00
Bank 0
00h – 07h
01
Bank 1
08h – 0Fh
10
Bank 2
10h – 17h
11
Bank 3
18h – 1Fh
OV: Overflow flag.
F1: General purpose Flag 1 available for user.
P: Parity flag, affected by hardware to indicate odd/even number of “one” bits in the
Accumulator, i.e. even parity.
4.4.
Stack Pointer
The stack pointer is a 1-byte register initialized to 07h after reset. This register is incremented before PUSH and CALL
instructions, causing the stack to start from location 08h.
Mnemonic: SP
7
6
5
4
3
2
1
SP [7:0]
Address: 81h
0
Reset
07h
SP[7:0]: The Stack Pointer stores the scratchpad RAM address where the stack begins. In other
words, it always points to the top of the stack.
4.5.
Data Pointer
The data pointer (DPTR) is 2-bytes wide. The lower part is DPL, and the highest is DPH. It can be loaded as a 2-byte
register (e.g. MOV DPTR, #data16) or as two separate registers (e.g. MOV DPL,#data8). It is generally used to access
the external code or data space (e.g. MOVC A, @A+DPTR, @DPTR respectively).
Mnemonic: DPL
7
6
5
4
3
DPL [7:0]
2
1
Address: 82h
0
Reset
00h
4
3
DPH [7:0]
2
1
Address: 83h
0
Reset
00h
DPL[7:0]: Data pointer Low 0
Mnemonic: DPH
7
6
5
DPH [7:0]: Data pointer High 0
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M055
20
Ver.E SM39R4051 09/2011
SM39R4051/SM39R2051
8-Bit Micro-controller
4KB/2KB with ISP Flash
& 256B RAM embedded
4.6.
Data Pointer 1
The Dual Data Pointer accelerates the moves of data block. The standard DPTR is a 16-bit register that is used to
address external memory or peripherals. In the SM39R4051 core the standard data pointer is called DPTR, the second
data pointer is called DPTR1. The data pointer select bit chooses the active pointer. The data pointer select bit is located
in LSB of AUX register (DPS).
The user switches between pointers by toggling the LSB of AUX register. All DPTR-related instructions use the currently
selected DPTR for any activity.
Mnemonic: DPL1
7
6
5
4
3
DPL1 [7:0]
2
1
Address: 84h
0
Reset
00h
4
3
DPH1 [7:0]
2
1
Address: 85h
0
Reset
00h
4
2
1
PINTS[1:0]
Address: 91h
0
Reset
DPS
00H
2
-
Address: 8Fh
0
Reset
ISPE
00H
DPL1[7:0]: Data pointer Low 1
Mnemonic: DPH1
7
6
5
DPH1[7:0]: Data pointer High 1
Mnemonic: AUX
7
6
BRGS
-
5
-
3
PTS[1:0]
DPS: Data Pointer selects register.
DPS = 1 is selected DPTR1.
4.7.
Interface control register
Mnemonic: IFCON
7
6
CDPR
5
-
4
-
3
-
1
-
CDPR: code protect (Read Only)
ISPE: ISP function enable bit
ISPE = 1, enable ISP function
ISPE = 0, disable ISP function
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M055
21
Ver.E SM39R4051 09/2011
SM39R4051/SM39R2051
8-Bit Micro-controller
4KB/2KB with ISP Flash
& 256B RAM embedded
5. GPIO
The SM39R4051 has three I/O ports: Port 1, Port 3 and Port 4. Ports 1, 3 are 8-bit ports and Port 4 is a 2-bit port. These
are: quasi-bidirectional (standard 8051 port outputs), push-pull, open drain, and input-only. Two configuration registers for
each port select the output type for each port pin. All I/O port pins on the SM39R4051 may be configured by software to
one of four types on a pin-by-pin basis, shown as below:
Mnemonic
P1M0
P1M1
P3M0
P3M1
P4M0
P4M1
P1WE
P3WE
Description
Port 1 output mode 0
Port 1 output mode 1
Port 3 output mode 0
Port 3 output mode 1
Port 4 output mode 0
Port 4 output mode 1
Port 3 output enable
Port 1 output enable
PxM1.y
0
0
1
1
PxM0.y
0
1
0
1
Direct
D4h
D5h
DAh
DBh
DCh
DDh
A3h
A4h
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
I/O port function register
P1M0[7:0]
P1M1[7:0]
P3M0[7:0]
P3M1[7:0]
Bit 2
Bit 1
Bit 0
P4M0[1:0]
P4M1[1:0]
P3WE[7:0]
P1WE[7:0]
RESET
00H
00H
00H
00H
00H
00H
FFH
FFH
Port output mode
Quasi-bidirectional (standard 8051 port outputs) (pull-up)
Push-pull
Input only (high-impedance)
Open drain
The RESET Pin Can Be configured as I/O port P3.6，when user use on-chip hardware RESET mechanism。
The XTAL2 and XTAL1 can be configured as I/O port by ICP or in ISP mode，when user use external OSC or on-chip RC
Oscillator is set to main system clock source。
Mnemonic: P1WE
7
6
5
P1.7
P1.6
P1.5
4
P1.4
3
P1.3
2
P1.2
1
P1.1
Address: A3h
0
Reset
P1.0
FFH
Mnemonic: P3WE
7
6
5
P3.7
P3.6
P3.5
4
P3.4
3
P3.3
2
P3.2
1
P3.1
Address: A4h
0
Reset
P3.0
FFH
For general-purpose applications, every pin can be assigned to either high or low independently as given below:
Mnemonic
Description
Direct
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Ports
Port 4
Port 4
E8h
P4.1
P4.0
Port 3
Port 3
B0h
P3.7
P3.6
P3.5
P3.4
P3.3
P3.2
P3.1
P3.0
Port 1
Port 1
90h
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
Mnemonic: P1
7
6
P1.7
P1.6
5
P1.5
4
P1.4
3
P1.3
2
P1.2
1
P1.1
Address: 90h
0
Reset
P1.0
FFh
4
P3.4
3
P3.3
2
P3.2
1
P3.1
Address: B0h
0
Reset
P3.0
FFh
RESET
FFh
FFh
FFh
P1.7~ 0: Port1 [7] ~ Port1 [0]
Mnemonic: P3
7
6
P3.7
P3.6
5
P3.5
P3.7~ 0: Port3 [7] ~ Port3 [0]
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M055
22
Ver.E SM39R4051 09/2011
SM39R4051/SM39R2051
8-Bit Micro-controller
4KB/2KB with ISP Flash
& 256B RAM embedded
Mnemonic: P4
7
6
-
5
-
4
-
3
-
2
-
1
P4.1
Address: E8h
0
Reset
P4.0
FFh
P4.1~ 0: Port4 [1] ~ Port4 [0]
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M055
23
Ver.E SM39R4051 09/2011
SM39R4051/SM39R2051
8-Bit Micro-controller
4KB/2KB with ISP Flash
& 256B RAM embedded
6. Timer 0 and Timer 1
The SM39R4051 has two 16-bit timer/counter registers: Timer 0 and Timer 1. All can be configured for counter or timer
operations.
In timer mode, the Timer 0 register or Timer 1 register is incremented every 12 machine cycles, which means that it
counts up after every 12 periods of the clock signal.
In counter mode, the register is incremented when the falling edge is observed at the corresponding input pin T0or T1.
Since it takes 2 machine cycles to recognize a 1-to-0 event, the maximum input count rate is 1/2 of the oscillator
frequency. There are no restrictions on the duty cycle, however to ensure proper recognition of 0 or 1 state, an input
should be stable for at least 1 machine cycle.
Four operating modes can be selected for Timer 0 and Timer 1. Two Special Function registers (TMOD and TCON) are
used to select the appropriate mode.
Mnemonic
Description
Direct
TL0
Timer 0 , low byte
Timer 0 , high
byte
Timer 1 , low byte
Timer 1 , high
byte
Timer Mode
Control
Timer/Counter
Control
Auxiliary register
8Ah
TL0[7:0]
00h
8Ch
TH0[7:0]
00h
8Bh
TL1[7:0]
00h
8Dh
TH1[7:0]
00h
TH0
TL1
TH1
TMOD
TCON
AUX
6.1.
Bit 7
Bit 6
Bit 5
Timer 0 and 1
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESET
89h
GATE
C/T
M1
M0
GATE
C/T
M1
M0
00h
88h
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
00h
91h
BRGS
-
-
PTS[1:0]
DPS
00H
3
GATE
2
1
C/T
M1
Timer 0
PINTS[1:0]
Timer/counter mode control register (TMOD)
Mnemonic: TMOD
7
6
5
GATE
C/T
M1
Timer 1
4
M0
Address: 89h
0
Reset
M0
00h
GATE: If set, enables external gate control (pin INT0 or INT1 for Counter 0 or 1,
respectively). When INT0 or INT1 is high, and TRx bit is set (see TCON
register), a counter is incremented every falling edge on T0 or T1 input pin
C/T: Selects Timer or Counter operation. When set to 1, a counter operation is
performed, when cleared to 0, the corresponding register will function as a
timer.
M[1:0]: Selects mode for Timer/Counter 0 or Timer/Counter 1.
M1
M0
Mode
Function
0
0
Mode0
13-bit counter/timer, with 5 lower bits in TL0 or
TL1 register and 8 bits in TH0 or TH1 register
(for Timer 0 and Timer 1, respectively). The 3
high order bits of TL0 and TL1 are hold at zero.
0
1
Mode1
16-bit counter/timer.
1
0
Mode2
8 -bit auto-reload counter/timer. The reload
value is kept in TH0 or TH1, while TL0 or TL1 is
incremented every machine cycle. When TLx
overflows, a value from THx is copied to TLx.
1
1
Mode3
If Timer 1 M1 and M0 bits are set to 1, Timer 1
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M055
24
Ver.E SM39R4051 09/2011
SM39R4051/SM39R2051
8-Bit Micro-controller
4KB/2KB with ISP Flash
& 256B RAM embedded
stops. If Timer 0 M1 and M0 bits are set to 1,
Timer 0 acts as two independent 8 bit timers /
counters.
6.2.
Timer/counter control register (TCON)
Mnemonic: TCON
7
6
5
TF1
TR1
TF0
4
TR0
3
IE1
2
IT1
1
IE0
Address: 88h
0
Reset
IT0
00h
TF1: Timer 1 overflow flag set by hardware when Timer 1 overflows. This flag can
be cleared by software and is automatically cleared when interrupt is
processed.
TR1: Timer 1 Run control bit. If cleared, Timer 1 stops.
TF0: Timer 0 overflow flag set by hardware when Timer 0 overflows. This flag can
be cleared by software and is automatically cleared when interrupt is
processed.
TR0: Timer 0 Run control bit. If cleared, Timer 0 stops.
IE1: Interrupt 1 edge flag. Set by hardware, when falling edge on external pin INT1
is observed. Cleared when interrupt is processed.
IT1: Interrupt 1 type control bit. Selects falling edge or low level on input pin to
cause interrupt.
IE0: Interrupt 0 edge flag. Set by hardware, when falling edge on external pin INT0
is observed. Cleared when interrupt is processed.
IT0: Interrupt 0 type control bit. Selects falling edge or low level on input pin to
cause interrupt.
6.3.
T0、T1 signal swapping：
The T0、T1 signal can be configured to other I/O。
Mnemonic: AUX
7
6
BRGS
-
PTS [1:0]
0x00
0x01
0x10
0x11
5
-
4
3
PTS [1:0]
Package = 20 Pin
T0
P3.4
P3.0
P1.4
P1.2
2
1
PINTS[1:0]
Address: 91h
0
Reset
DPS
00H
T1
P3.5
P3.1
P1.5
P1.3
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M055
25
Ver.E SM39R4051 09/2011
SM39R4051/SM39R2051
8-Bit Micro-controller
4KB/2KB with ISP Flash
& 256B RAM embedded
7. Serial interface 0
The serial buffer consists of two separate registers, a transmit buffer and a receive buffer.
Writing data to the Special Function Register S0BUF sets this data in serial output buffer and starts the transmission.
Reading from the S0BUF reads data from the serial receive buffer. The serial port can simultaneously transmit and
receive data. It can also buffer 1 byte at receive, which prevents the receive data from being lost if the CPU reads the first
byte before transmission of the second byte is completed.
Mnemonic
Description
Direct
Bit 7
PCON
AUX
Power control
Auxiliary register
Serial Port 0
control register
Serial Port 0 data
buffer
Serial Port 0 reload
register low byte
Serial Port 0 reload
register high byte
87H
91h
SMOD
BRGS
98H
SM0
S0CON
S0BUF
S0RELL
S0RELH
Bit 6
Bit 5
Bit 4
Bit 3
Serial interface 0
PTS[1:0]
Bit 2
SM1
RB80
SM20
REN0
99H
AAH
Bit 0
RESET
STOP
PINTS[1:0]
IDLE
DPS
40H
00H
RI0
00H
TI0
S0BUF[7:0]
S0REL
.7
S0REL
.6
S0REL
.5
BAH
Mnemonic: AUX
7
6
BRGS
TB80
Bit 1
S0REL
.4
S0REL
.3
-
5
-
4
3
PTS[1:0]
2
1
PINTS[1:0]
00H
S0REL
.2
S0REL
.1
S0REL
.9
S0REL
.0
S0REL
.8
Address: 91h
0
Reset
DPS
00H
BRGS: BRGS = 0 –Baud rate generator use Timer 1 TH1 SFR.
BRGS = 1 –Baud rate generator use S0REL SFR.
Mnemonic: S0CON
7
6
5
SM0
SM1
SM20
4
REN0
3
TB80
2
RB80
1
TI0
Address: 98h
0
Reset
RI0
00h
SM0,SM1: Serial Port 0 mode selection.
SM0 SM1
Mode
0
0
0
0
1
1
1
0
2
1
1
3
The 4 modes in UART0, Mode 0 ~ 3, are explained later.
SM20: Enables multiprocessor communication feature
REN0: If set, enables serial reception. Cleared by software to disable reception.
TB80: The 9th transmitted data bit in modes 2 and 3. Set or cleared by the CPU
depending on the function it performs such as parity check, multiprocessor
communication etc.
RB80: In modes 2 and 3, it is the 9th data bit received. In mode 1, if SM20 is 0, RB80
is the stop bit. In mode 0, this bit is not used. Must be cleared by software.
TI0: Transmit interrupt flag, set by hardware after completion of a serial transfer.
Must be cleared by software.
RI0: Receive interrupt flag, set by hardware after completion of a serial reception.
Must be cleared by software.
The Serial Interface 0 can operate in the following 4 modes:
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M055
26
Ver.E SM39R4051 09/2011
00H
00H
SM39R4051/SM39R2051
8-Bit Micro-controller
4KB/2KB with ISP Flash
& 256B RAM embedded
SM0
0
0
1
1
SM1
0
1
0
1
Mode
0
1
2
3
Description
Shift register
8-bit UART
9-bit UART
9-bit UART
Board Rate
Fosc/12
Variable
Fosc/32 or Fosc/64
Variable
Here Fosc is the crystal or oscillator frequency.
7.1.
Mode 0
Pin RXD0 serves as input and output. TXD0 outputs the shift clock. 8 bits are transmitted with LSB first. The baud rate is
fixed at 1/12 of the crystal frequency. Reception is initialized in Mode 0 by setting the flags in S0CON as follows: RI0 = 0
and REN0 = 1. In other modes, a start bit when REN0 = 1 starts receiving serial data.
Fig. 7-1: Transmit mode 0 for Serial 0
Fig. 7-2: Receive mode 0 for Serial 0
7.2.
Mode 1
Pin RXD0 serves as input, and TXD0 serves as serial output. No external shift clock is used, 10 bits are transmitted: a
start bit (always 0), 8 data bits (LSB first), and a stop bit (always 1). On receive, a start bit synchronizes the transmission,
8 data bits are available by reading S0BUF, and stop bit sets the flag RB80 in the Special Function Register S0CON. In
mode 1 either internal baud rate generator or timer 1 can be use to specify baud rate.
Fig. 7-3: Transmit mode 1 for Serial 0
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M055
27
Ver.E SM39R4051 09/2011
SM39R4051/SM39R2051
8-Bit Micro-controller
4KB/2KB with ISP Flash
& 256B RAM embedded
Fig. 7-4: Receive mode 1 for Serial 0
7.3.
Mode 2
This mode is similar to Mode 1, with two differences. The baud rate is fixed at 1/32 (SMOD=1) or 1/64(SMOD=0) of
oscillator frequency and 11 bits are transmitted or received: a start bit (0), 8 data bits (LSB first), a programmable 9th bit,
and a stop bit (1). The 9th bit can be used to control the parity of the serial interface: at transmission, bit TB80 in S0CON is
output as the 9th bit, and at receive, the 9th bit affects RB80 in Special Function Register S0CON.
7.4.
Mode 3
The only difference between Mode 2 and Mode 3 is that in Mode 3 either internal baud rate generator or timer 1 can be
use to specify baud rate.
Fig. 7-5: Transmit modes 2 and 3 for Serial 0
Fig. 7-6: Receive modes 2 and 3 for Serial 0
7.5.
Multiprocessor communication of Serial Interface 0
The feature of receiving 9 bits in Modes 2 and 3 of Serial Interface 0 can be used for multiprocessor communication. In
this case, the slave processors have bit SM20 in S0CON. When the master processor outputs slave’s address, it sets the
9th bit to 1, causing a serial port receive interrupt in all the slaves. The slave processors compare the received byte with
their network address. If there is a match, the addressed slave will clear SM20 and receive the rest of the message, while
other slaves will leave SM20 bit unaffected and ignore this message. After addressing the slave, the host will output the
rest of the message with the 9th bit set to 0, so no serial port receive interrupt will be generated in unselected slaves.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M055
28
Ver.E SM39R4051 09/2011
SM39R4051/SM39R2051
8-Bit Micro-controller
4KB/2KB with ISP Flash
& 256B RAM embedded
7.6.
Baud rate generator
7.6.1.
Serial interface 0 modes 1 and 3
(a) When BRGS = 0 (in SFR AUX):
2SMOD × FOSC
Baud Rate =
32 × 12 × (256 − TH1)
(b) When BRGS = 1 (in SFR AUX):
Baud Rate =
7.6.2.
2SMOD × FOSC
64 × 210 − S0REL
(
)
Clock source for baud rate
The on-chip RC-Oscillator frequency varies within +3% after factory calibration. In case of application with higher clock
precision requirement, external Crystal is usually recommended clock source.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M055
29
Ver.E SM39R4051 09/2011
SM39R4051/SM39R2051
8-Bit Micro-controller
4KB/2KB with ISP Flash
& 256B RAM embedded
8. Watchdog timer
The Watch Dog Timer (WDT) is an 8-bit free-running counter that generate reset signal if the counter overflows. The WDT
is useful for systems which are susceptible to noise, power glitches, or electronics discharge which causing software
dead loop or runaway. The WDT function can help user software recover from abnormal software condition. The WDT is
different from Timer0, Timer1 of general 8052. To prevent a WDT reset can be done by software periodically clearing the
WDT counter. User should check WDTF bit of WDTC register whenever un-predicted reset happened. After an external
reset the watchdog timer is disabled and all registers are set to zeros.
The watchdog timer has a free running on-chip RC oscillator (250KHz ±20%). The WDT will keep on running even after
the system clock has been turned off (for example, in sleep mode). During normal operation or sleep mode, a WDT
time-out (if enabled) will cause the MCU to reset. The WDT can be enabled or disabled any time during the normal mode.
Please refer the WDTE bit of WDTC register. The default WDT time-out period is approximately 16.38ms (WDTM [3:0] =
0100b).
The WDT has selectable divider input for the time base source clock. To select the divider input, the setting of bit3 ~ bit0
(WDTM [3:0]) of Watch Dog Timer Control Register (WDTC) should be set accordingly.
250KHz
2WDTM
256
Watchdog reset time =
WDTCLK
WDTCLK =
WDTM [3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Table 8.1 WDT time-out period
Divider
Time period @ 250KHz
(250 KHz RC oscillator in)
1
1.02ms
2
2.05ms
4
4.10ms
8
8.19ms
16
16.38ms (default)
32
32.77ms
64
65.54ms
128
131.07ms
256
262.14ms
512
524.29ms
1024
1.05s
2048
2.10s
4096
4.19s
8192
8.39s
16384
16.78s
32768
33.55s
When MCU is reset, the MCU will be read WDTEN control bit status. When WDTEN bit is set to 1, the watchdog function
will be disabled no matter what the WDTE bit status is. When WDTEN bit is clear to 0, the watchdog function will be
enabled if WDTE bit is set to 1 by program. User can to set WDTEN on the writer or ISP.
The program can enable the WDT function by programming 1 to the WDTE bit premise that WDTEN control bit is clear to
0. After WDTE set to 1, the 8 bit-counter starts to count with the selected time base source clock which set by WDTM [3:0].
It will generate a reset signal when overflows. The WDTE bit will be cleared to 0 automatically when MCU been reset,
either hardware reset or WDT reset.
Once the watchdog is started it cannot be stopped. User can refreshed the watchdog timer to zero by writing 0x55 to
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M055
30
Ver.E SM39R4051 09/2011
SM39R4051/SM39R2051
8-Bit Micro-controller
4KB/2KB with ISP Flash
& 256B RAM embedded
Watch Dog Timer refresh Key (WDTK) register. This will clear the content of the 8-bit counter and let the counter re-start
to count from the beginning. The watchdog timer must be refreshed regularly to prevent reset request signal from
becoming active.
When Watchdog timer is overflow, the WDTF flag will set to one and automatically reset MCU. The WDTF flag can be
clear by software or external reset or power on reset.
1
2WDTM
Fig. 8-1: Watchdog timer block diagram
Mnemonic
TAKEY
WDTC
WDTK
Description
Direct
Time Access Key
register
Watchdog timer
control register
Watchdog timer
refresh key
Bit 7
Bit 6
Bit 5
Bit 4
Watchdog Timer
F7h
B6h
Bit 3
Bit 2
Bit 1
Bit 0
RESET
TAKEY [7:0]
WDTF
-
WDTE
-
B7h
Mnemonic: TAKEY
7
6
5
00H
WDTM [3:0]
WDTK[7:0]
4
3
TAKEY [7:0]
2
1
04H
00H
Address: F7h
0
Reset
00H
Watchdog timer control register (WDTC) is read-only by default; software must write three specific
values 55h, AAh and 5Ah sequentially to the TAKEY register to enable the WDTC write attribute. That is:
MOV TAKEY, #55h
MOV TAKEY, #AAh
MOV TAKEY, #5Ah
Mnemonic: WDTC
7
6
5
WDTF
WDTE
4
-
3
2
1
WDTM [3:0]
Address: B6h
0
Reset
04H
WDTF: Watchdog timer reset flag.
When MCU is reset by watchdog, WDTF flag will be set to one by hardware. This flag
clear by software or external reset or power on reset.
WDTE: Control bit used to enable Watchdog timer.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M055
31
Ver.E SM39R4051 09/2011
SM39R4051/SM39R2051
8-Bit Micro-controller
4KB/2KB with ISP Flash
& 256B RAM embedded
The WDTE bit can be used only if WDTEN is "0". If the WDTEN bit is "0", then WDT
can be disabled / enabled by the WDTE bit.
0: Disable WDT.
1: Enable WDT.
The WDTE bit is not used if WDTEN is "1". That is, if the WDTEN bit is "1", WDT is
always disabled no matter what the WDTE bit status is. The WDTE bit can be read and
written.
WDTM [3:0]: WDT clock source divider bit. Please see table 8.1 to reference the WDT time-out
period.
Mnemonic: WDTK
7
6
5
4
3
WDTK[7:0]
2
1
Address: B7h
0
Reset
00h
WDTK: Watchdog timer refresh key.
A programmer must write 0x55 into WDTK register, and then the watchdog
timer will be cleared to zero.
For example, if enable WDT and select time-out reset period is 327.68ms.
First, programming the information block OP3 bit7 WDTEN to “0”.
Secondly,
MOV TAKEY, #55h
MOV TAKEY, #AAh
MOV TAKEY, #5Ah
; enable WDTC write attribute.
MOV WDTC, #28h
; Set WDTM [3:0] = 1000b. Set WDTE =1 to enable WDT
; function.
.
.
.
MOV WDTK, #55h
; Clear WDT timer to 0.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M055
32
Ver.E SM39R4051 09/2011
SM39R4051/SM39R2051
8-Bit Micro-controller
4KB/2KB with ISP Flash
& 256B RAM embedded
9. Interrupt
The SM39R4051 provides 7 interrupt sources with four priority levels. Each source has its own request flag(s) located in a
special function register. Each interrupt requested by the corresponding flag could individually be enabled or disabled by
the enable bits in SFR’s IEN0, and IEN1.
When the interrupt occurs, the engine will vector to the predetermined address as shown in Table 9.1. Once interrupt
service has begun, it can be interrupted only by a higher priority interrupt. The interrupt service is terminated by a return
from instruction RETI. When an RETI is performed, the processor will return to the instruction that would have been next
when interrupt occurred.
When the interrupt condition occurs, the processor will also indicate this by setting a flag bit. This bit is set regardless of
whether the interrupt is enabled or disabled. Each interrupt flag is sampled once per machine cycle, and then samples are
polled by hardware. If the sample indicates a pending interrupt when the interrupt is enabled, then interrupt request flag is
set. On the next instruction cycle the interrupt will be acknowledged by hardware forcing an LCALL to appropriate vector
address.
Interrupt response will require a varying amount of time depending on the state of microcontroller when the interrupt
occurs. If microcontroller is performing an interrupt service with equal or greater priority, the new interrupt will not be
invoked. In other cases, the response time depends on current instruction. The fastest possible response to an interrupt is
7 machine cycles. This includes one machine cycle for detecting the interrupt and six cycles for perform the LCALL.
Table 9-1: Interrupt vectors
Interrupt Vector
Interrupt Request Flags
Address
IE0 – External interrupt 0
0003h
TF0 – Timer 0 interrupt
000Bh
Interrupt Number
*(use Keil C Tool)
0
1
IE1 – External interrupt 1
0013h
2
TF1 – Timer 1 interrupt
RI0/TI0 – Serial channel 0 interrupt
LVIIF – Low Voltage Interrupt
001Bh
0023h
0063h
3
4
12
IICIF – IIC interrupt
006Bh
13
*See Keil C about C51 User’s Guide about Interrupt Function description
Mnemonic
Description
Direct
Bit 7
AUX
Auxiliary register
Interrupt Enable
0 register
Interrupt Enable
1 register
Interrupt request
register
Interrupt priority
level 0
Interrupt priority
level 1
91h
BRGS
A8H
EA
-
-
ES0
ET1
EX1
B8H
-
-
IEIIC
IELVI
-
C0H
-
-
IICIF
LVIIF
A9h
-
-
IP0.5
B9h
-
-
IP1.5
IEN0
IEN1
IRCON
IP0
IP1
Bit 6
Bit 5
Interrupt
-
Bit 4
Bit 3
Bit 0
RESET
DPS
00H
ET0
EX0
00H
-
-
-
00H
-
-
-
-
00H
IP0.4
IP0.3
IP0.2
IP0.1
IP0.0
00h
IP1.4
IP1.3
IP1.2
IP1.1
IP1.0
00h
PTS[1:0]
Bit 2
Bit 1
PINTS[1:0]
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M055
33
Ver.E SM39R4051 09/2011
SM39R4051/SM39R2051
8-Bit Micro-controller
4KB/2KB with ISP Flash
& 256B RAM embedded
Mnemonic: AUX
7
6
BRGS
-
5
-
4
3
PTS[1:0]
2
1
PINTS[1:0]
Address: 91h
0
Reset
DPS
00H
The INT0、INT1 signal can be configured to other I/O。
PINTS [1:0]
0x00
0x01
0x10
0x11
Package = 20 Pin
INT0
P3.2
P3.0
P1.4
P3.2
INT1
P3.3
P3.1
P1.5
P3.3
Interrupt Enable 0 register(IEN0)
Mnemonic: IEN0
7
6
EA
-
5
-
4
ES0
3
ET1
2
EX1
1
ET0
Address: A8h
0
Reset
EX0
00h
1
-
Address: B8h
0
Reset
00h
EA: EA=0 – Disable all interrupt.
EA=1 – Enable all interrupt.
ES0: ES0=0 – Disable Serial channel 0 interrupt.
ES0=1 – Enable Serial channel 0 interrupt.
ET1: ET1=0 – Disable Timer 1 overflow interrupt.
ET1=1 – Enable Timer 1 overflow interrupt.
EX1: EX1=0 – Disable external interrupt 1.
EX1=1 – Enable external interrupt 1.
ET0: ET0=0 – Disable Timer 0 overflow interrupt.
ET0=1 – Enable Timer 0 overflow interrupt.
EX0: EX0=0 – Disable external interrupt 0.
EX0=1 – Enable external interrupt 0.
Interrupt Enable 1 register(IEN1)
Mnemonic: IEN1
7
6
-
5
IEIIC
4
IELVI
3
-
2
-
IEIIC: IIC interrupt enable.
IEIICS = 0 – Disable IIC interrupt.
IEIICS = 1 – Enable IIC interrupt.
IELVI: LVI interrupt enable.
IELVI = 0 – Disable LVI interrupt.
IELVI = 1 – Enable LVI interrupt.
Interrupt request register(IRCON)
Mnemonic: IRCON
7
6
5
IICIF
4
LVIIF
3
-
2
-
1
-
Address: C0h
0
Reset
00H
IICIF: IIC interrupt flag.
LVIIF: LVI interrupt flag.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M055
34
Ver.E SM39R4051 09/2011
SM39R4051/SM39R2051
8-Bit Micro-controller
4KB/2KB with ISP Flash
& 256B RAM embedded
9.1.
Priority level structure
All interrupt sources are combined in groups:
Table 9-2: Priority level groups
GroupsExternal interrupt 0
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
Serial channel 0 interrupt
LVI interrupt
IIC interrupt
Each group of interrupt sources can be programmed individually to one of four priority levels by setting or clearing one bit
in the special function register ip0 and one in ip1. If requests of the same priority level will be received simultaneously, an
internal polling sequence determines which request is serviced first.
Mnemonic: IP0
7
6
-
5
IP0.5
4
IP0.4
3
IP0.3
2
IP0.2
1
IP0.1
Address: A9h
0
Reset
IP0.0
00h
Mnemonic: IP1
7
6
-
5
IP1.5
4
IP1.4
3
IP1.3
2
IP1.2
1
IP1.1
Address: B9h
0
Reset
IP1.0
00h
Table 9-3: Priority levels
IP1.x
IP0.x
Priority Level
0
0
1
1
Bit
IP1.0, IP0.0
IP1.1, IP0.1
IP1.2, IP0.2
IP1.3, IP0.3
IP1.4, IP0.4
IP1.5, IP0.5
0
1
0
1
Level0 (lowest)
Level1
Level2
Level3 (highest)
Table 9-4: Groups of priority
Group
External interrupt 0
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
Serial channel 0 interrupt
-
LVI interrupt
IIC interrupt
Table 9-5: Polling sequence
Serial channel 0 interrupt
Sequence
Polling
sequence
Interrupt source
External interrupt 0
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
LVI interrupt
IIC interrupt
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M055
35
Ver.E SM39R4051 09/2011
SM39R4051/SM39R2051
8-Bit Micro-controller
4KB/2KB with ISP Flash
& 256B RAM embedded
10. Power Management Unit
Power management unit serves two power management modes, IDLE and STOP, for the users to do power saving
function.
Mnemonic: PCON
7
6
SMOD
-
5
-
4
-
3
-
2
-
1
STOP
Address: 87h
0
Reset
IDLE
40h
STOP: Stop mode control bit. Setting this bit turning on the Stop Mode.
Stop bit is always read as 0
IDLE: Idle mode control bit. Setting this bit turning on the Idle Mode.
Idle bit is always read as 0
10.1. Idle mode
Setting the IDLE bit of PCON register invokes the IDLE mode. The IDLE mode leaves internal clocks and peripherals
running. Power consumption drops because the CPU is not active. The CPU can exit the IDLE state with any interrupts or
a reset.
10.2. Stop mode
Setting the STOP bit of PCON register invokes the STOP mode. All internal clocking in this mode is turn off. The CPU will
exit this state only if interrupts asserted from external INT0/1 and LVI or hardware reset by WDT and LVR.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M055
36
Ver.E SM39R4051 09/2011
SM39R4051/SM39R2051
8-Bit Micro-controller
4KB/2KB with ISP Flash
& 256B RAM embedded
11. IIC function
The IIC module uses the SCL (clock) and the SDA (data) line to communicate with external IIC interface. Its speed can be
selected to 400Kbps (maximum) by software setting the IICBR [2:0] control bit. The IIC module provided 2 interrupts
(RXIF, TXIF). It will generate START, repeated START and STOP signals automatically in master mode and can detects
START, repeated START and STOP signals in slave mode. The maximum communication length and the number of
devices that can be connected are limited by a maximum bus capacitance of 400pF.
The interrupt vector is 6Bh.
Mnemonic
Description
Direct
Bit 7
Bit 6
Bit 5
IIC function
Bit 4
Bit 3
IICCTL
IIC control register
F9h
IICEN
MSS
MAS
AB_EN
BF_E
N
IICS
IIC status register
F8h
-
MPIF
LAIF
RXIF
TXIF
IICA1
IICA2
IICRWD
IICEBT
IIC Address 1
register
IIC Address 2
register
IIC Read/Write
register
IIC Enaable Bus
Transaction
FAh
IICA1[7:1]
FBh
IICA2[7:1]
FCh
FDh
Mnemonic: IICCTL
7
6
5
IICEN
MSS
MAS
Bit 2
Bit 1
Bit 0
RESET
IICBR[2:0]
RXAK
TXAK
RW,B
B
MATCH1
or RW1
MATCH2
or RW2
IICRWD[7:0]
FU_EN
4
AB_EN
2
1
IICBR[2:0]
00H
A0H
60H
00H
-
3
BF_EN
04H
00H
Address: F9h
0
Reset
04h
IICEN: Enable IIC module
IICEN = 1 is Enable
IICEN = 0 is Disable.
MSS: Master or slave mode select.
MSS = 1 is master mode.
MSS = 0 is slave mode.
*The software must set this bit before setting others register.
MAS: Master address select (master mode only)
MAS = 0 is to use IICA1.
MAS = 1 is to use IICA2.
AB_EN: Arbitration lost enable bit. (Master mode only)
If set AB_EN bit, the hardware will check arbitration lost. Once arbitration lost occurred,
hardware will return to IDLE state. If this bit is cleared, hardware will not care arbitration lost
condition. Set this bit when multi-master and slave connection. Clear this bit when single master
to single slave.
BF_EN: Bus busy enable bit. (Master mode only)
If set BF_EN bit, hardware will not generate a start condition to bus until BF=0. Clear this bit will
always generate a start condition to bus when MStart is set. Set this bit when multi-master and
slave connection. Clear this bit when single master to single slave.
IICBR[2:0]: Baud rate selection (master mode only), where Fosc is the external crystal or oscillator
frequency. The default is Fosc/512 for users’ convenience.
IICBR[2:0]
Baud rate
000
Fosc/32
001
Fosc/64
010
Fosc/128
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M055
37
Ver.E SM39R4051 09/2011
SM39R4051/SM39R2051
8-Bit Micro-controller
4KB/2KB with ISP Flash
& 256B RAM embedded
011
100
101
110
111
Mnemonic: IICS
7
6
MPIF
Fosc/256
Fosc/512
Fosc/1024
Fosc/2048
Fosc/4096
5
LAIF
4
RXIF
3
TXIF
2
RXAK
1
TxAK
Address: F8H
0
Reset
RW
00H
MPIF: The Stop condition Interrupt Flag
The stop condition occurred and this bit will be set. Software need to clear this bit
LAIF: Arbitration lost bit. (Master mode only)
The Arbitration Interrupt Flag, the bus arbitration lost occurred and this bit will be set.
Software need to clear this bit
RxIF: The data Receive Interrupt Flag (RXIF) is set after the IICRWD (IIC Read Write Data
Buffer) is loaded with a newly receive data.
TxIF: The data Transmit Interrupt Flag (TXIF) is set when the data of the IICRWD (IIC Read
Write Data Buffer) is downloaded to the shift register.
RxAK: The Acknowledge Status indicate bit. When clear, it means an acknowledge signal has
been received after the complete 8 bits data transmit on the bus.
TxAK: The Acknowledge status transmit bit. When received complete 8 bits data, this bit will
set (NoAck) or clear (Ack) and transmit to master to indicate the receive status.
RW: Master Mode:
Bus busy bit
If detect scl=0 or sda=0 or bus start, this bit will be set. If detect stop,this bit will be
cleared. This bit can be cleared by software to return ready state.
Slave Mode:
The slave mode read (received) or wrote (transmit) on the IIC bus. When this bit is clear,
the slave module received data on the IIC bus (SDA).(Slave mode only)
Fig. 11-1: Acknowledgement bit in the 9th bit of a byte transmission
Mnemonic: IICA1
7
6
5
4
IICA1[7:1]
R/W
3
2
1
Address: FAH
0
Reset
Match1 or
A0H
RW1
R or R/W
Slave mode:
IICA1[7:1]: IIC Address registers
This is the first 7-bit address for this slave module. It will be checked when an address (from
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M055
38
Ver.E SM39R4051 09/2011
SM39R4051/SM39R2051
8-Bit Micro-controller
4KB/2KB with ISP Flash
& 256B RAM embedded
master) is received
Match1: When IICA1 matches with the received address from the master side, this bit will set to 1 by
hardware. When IIC bus gets or send first data, this bit will clear automatically.
Master mode:
IICA1[7:1]: IIC Address registers
This 7-bit address indicates the slave with which it wants to communicate.
RW1: This bit will be sent out as RW of the slave side if the module has set the MStart or RStart bit. It
appears at the 8th bit after the IIC address as shown in Fig. 14-2. It is used to tell the salve the
direction of the following communication. If it is 1, the module is in master receive mode. If 0, the
module is in master transmit mode.
Fig. 11-2: RW bit in the 8th bit after IIC address
Mnemonic: IICA2
7
6
5
Address: FBh
4
IICA2[7:1]
R/W
3
2
1
0
Match2 or RW2
R or R/W
Reset
60h
Slave mode:
IICA2[7:1]: IIC Address registers
This is the second 7-bit address for this slave module.
It will be checked when an address (from master) is received
Match2: When IICA2 matches with the received address from the master side, this bit will set to 1 by
hardware. When IIC bus gets or send first data, this bit will clear automatically.
Master mode:
IICA2[7:1]: IIC Address registers
This 7-bit address indicates the slave with which it wants to communicate.
RW2: This bit will be sent out as RW of the slave side if the module has set the MStart or RStart bit. It is
used to tell the salve the direction of the following communication. If it is 1, the module is in
master receive mode. If 0, the module is in master transmit mode.
Mnemonic: IICRWD
7
6
5
Address: FCh
4
3
2
1
0
Reset
IICRWD[7:0]
00h
IICRWD[7:0]: IIC read write data buffer.
In receiving (read) mode, the received byte is stored here.
In transmitting mode, the byte to be shifted out through SDA stays here.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M055
39
Ver.E SM39R4051 09/2011
SM39R4051/SM39R2051
8-Bit Micro-controller
4KB/2KB with ISP Flash
& 256B RAM embedded
Mnemonic: IICEBT
7
6
FU_EN
5
-
4
-
3
-
2
-
1
-
Address: FDH
0
Reset
00H
Master Mode：
00: reserved
01: IIC bus module will enable read/write data transfer on SDA and SCL.
10: IIC bus module generate a start condition on the SDA/SCL, then send out
address which is stored in the IICA1/IICA2(selected by MAS control bit)
11: IIC bus module generate a stop condition on the SDA/SCL.
Slave mode:
01: FU_EN[7:6] should be set as 01 only. The other value is inhibited.
Notice:
1. FU_EN[7:6] should be set as 01 before read/write data transfer for bus
release; otherwise, SCL will be locked(pull low).
2. FU_EN[7:6] should be set as 01 after read/write data transfer for receiving
a stop condition from bus master.
3. In transmit data mode(slave mode), the output data should be filled into
IICRWD before setting FU_EN[7:6] as 01.
4. FU_EN[7:6] will be auto-clear by hardware, so setting FU_EN[7:6]
repeatedly is necessary.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M055
40
Ver.E SM39R4051 09/2011
SM39R4051/SM39R2051
8-Bit Micro-controller
4KB/2KB with ISP Flash
& 256B RAM embedded
12. LVI – Low Voltage Interrupt
The interrupt vector 63h.
Mnemonic: LVC
7
6
LVI_EN LVI_VS
5
LVRXE
4
LVSIF
3
-
2
-
1
EPSIF
Address: E6h
0
Reset
20H
LVI_EN: Low voltage interrupt function enable bit.
0: disable low voltage detect function.
1: enable low voltage detect function.
LVI_VS: Low Voltage Interrupt level Selection
0 :The level of voltage is set at Low-level
1 :The level of voltage is set at Hi-Level
LVRXE: External low voltage reset function enable bit.
0: disable external low voltage reset function.
1: enable external low voltage reset function.
LVSIF Low Voltage Status Flag
1:the VDD voltage under LVI voltage
0:the VDD voltage above LVI voltage
ESPIF MCU External Voltage Status Flag
1: means less than 3.8V(external power)
0: means more than 3.9V(external power)
Hi-level：
Symbol
VLVI
VLVR
Notes:
Parameter
Low Voltage Interrupt Voltage Level
Low Voltage Reset Voltage Level
Typ
3.7
3.5
Max
4.0
3.8
Units
V
V
Min
2.1
1.9
Typ
2.3
2.1
Max
2.5
2.3
Units
V
V
The VLVI always above VLVR about 0.2V.
Low-level：
Symbol
Parameter
VLVI
Low Voltage Interrupt Voltage Level
VLVR
Low Voltage Reset Voltage Level
Notes:
Min
3.4
3.2
The VLVI always above VLVR about 0.2V.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M055
41
Ver.E SM39R4051 09/2011
SM39R4051/SM39R2051
8-Bit Micro-controller
4KB/2KB with ISP Flash
& 256B RAM embedded
13. In-System Programming (Internal ISP)
The SM39R4051 can generate flash control signal by internal hardware circuit. Users utilize flash control register, flash
address register and flash data register to perform the ISP function without removing the SM39R4051 from the system.
The SM39R4051 provides internal flash control signals which can do flash program/chip erase/page erase/protect
functions. User need to design and use any kind of interface which SM39R4051 can input data. User then utilize ISP
service program to perform the flash program/chip erase/page erase/protect functions.
13.1. ISP service program
The ISP service program is a user developed firmware program which resides in the ISP service program space.
After user developed the ISP service program, user then determine the size of the ISP service program. User need
to program the ISP service program in the SM39R4051 for the ISP purpose.
The ISP service programs were developed by user so that it should includes any features which relates to the flash
memory programming function as well as communication protocol between SM39R4051 and host device which
output data to the SM39R4051. For example, if user utilize UART interface to receive/transmit data between
SM39R4051 and host device, the ISP service program should include baud rate, checksum or parity check or any
error-checking mechanism to avoid data transmission error.
The ISP service program can be initiated under SM39R4051 active or idle mode. It can not be initiated under power
down mode.
13.2. Lock Bit (N)
The Lock Bit N has two functions: one is for service program size configuration and the other is to lock the ISP
service program space from flash erase function.
The ISP service program space address range $C00 to $FFF. It can be divided as blocks of N*256 byte. (N=0 to 4).
When N=0 means no ISP function, all of 4K byte flash memory can be used as program memory. When N=1 means
ISP service program occupies 256 byte while the rest of 3.75K byte flash memory can be used as program memory.
The maximum ISP service program allowed is 1K byte when N=4. Under such configuration, the usable program
memory space is 3K byte.
After N determined, SM39R4051 will reserve the ISP service program space downward from the top of the program
address $FFF. The start address of the ISP service program located at $0C00. Please see section 3.1 program
memory diagram for this ISP service program space structure.
The lock bit N function is different from the flash protect function. The flash erase function can erase all of the flash
memory except for the locked ISP service program space. If the flash not has been protected, the content of ISP
service program still can be read. If the flash has been protected, the overall content of flash program memory space
including ISP service program space can not be read.
N
0
1
2
3
4
Table 13.1 ISP code area.
ISP service program address
No ISP service program
256 bytes ($F00h ~ $FFFh)
512 bytes ($E00h ~ $FFFh)
768 bytes ($D00h ~ $FFFh)
1.0 K bytes ($C00h ~ $FFFh)
ISP service program configurable in N*256 byte (N= 0 ~ 4)
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M055
42
Ver.E SM39R4051 09/2011
SM39R4051/SM39R2051
8-Bit Micro-controller
4KB/2KB with ISP Flash
& 256B RAM embedded
13.3. Program the ISP Service Program
After Lock Bit N is set and ISP service program been programmed, the ISP service program memory will be
protected (locked) automatically. The lock bit N has its own program/erase timing. It is different from the flash
memory program/erase timing so the locked ISP service program can not be erased by flash erase function. If user
needs to erase the locked ISP service program, he can do it by writer only. User can not change ISP service program
when SM39R4051 was in system.
13.4. Initiate ISP Service Program
To initiate the ISP service program is to load the program counter (PC) with start address of ISP service program and
execute it. There are four ways to do so:
(1) Blank reset. Hardware reset with first flash address blank ($0000=#FFH) will load the PC with start
address of ISP service program. The hardware reset includes MAX810 (power on reset) and external
pad reset. The hardware will issue a strobe window about 256us after hardware reset.
(2) Execute jump instruction can load the start address of the ISP service program to PC.
(3) Enter’s ISP service program by hardware setting. User can force SM39R4051 enter ISP service
program by setting P1.5, “active low” during hardware reset period. The hardware reset includes
MAX810 (power on reset) and external pad reset. The hardware will issue a strobe window about
256us after hardware reset. In application system design, user should take care of the setting of P1.5,
at reset period to prevent SM39R4051 from entering ISP service program.
(4) Enter’s ISP service program by hardware setting, the P3.0 will be detected the two clock signals
during hardware reset period. The hardware reset includes MAX810 (power on reset) and external
pad reset. The hardware will issue a 256us strobe window to detect 2 clock signals after hardware
reset.
During the strobe window, the hardware will detect the status of P1.5 and P3.0. If they meet one of above conditions,
chip will switch to ISP mode automatically. After ISP service program executed, user need to reset the SM39R4051,
either by hardware reset or by WDT, or jump to the address $0000 to re-start the firmware program.
There are 6 kinds of entry mechanisms for user different applications. This entry method will select on the writer or
ISP.
(1) First Address Blank. i.e. $0000 = 0xFF. And triggered by Internal reset signal.
(2) First Address Blank. i.e. $0000 = 0xFF. And triggered by PAD reset signal.
(3) P1.5=0. And triggered by Internal reset signal.
(4) P1.5=0. And triggered by PAD reset signal.
(5) P3.0 input 2 clocks. And triggered by Internal reset signal.
(6) P3.0 input 2 clocks. And triggered by PAD reset signal.
13.5. ISP register – TAKEY, IFCON, ISPFAH, ISPFAL, ISPFD and ISPFC
Mnemonic
TAKEY
IFCON
ISPFAH
ISPFAL
ISPFD
Description
Time Access Key
register
Interface Control
register
ISP Flash
Address - High
register
ISP Flash
Address - Low
register
ISP Flash Data
register
Direct
Bit 7
Bit 6
Bit 5
ISP function
F7h
8Fh
E1h
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESET
TAKEY [7:0]
-
CDPR
-
-
-
-
00H
-
-
ISPE
ISPFAH [3:0]
00H
FFH
E2h
ISPFAL [7:0]
FFH
E3h
ISPFD [7:0]
FFH
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M055
43
Ver.E SM39R4051 09/2011
SM39R4051/SM39R2051
8-Bit Micro-controller
4KB/2KB with ISP Flash
& 256B RAM embedded
ISPFC
ISP Flash Control
register
E4h
EMF1
EMF2
EMF3
EMF4
-
ISPF.2
ISPF.1
ISPF.0
00H
Address: F7H
Mnemonic: TAKEY
7
6
5
4
3
TAKEY [7:0]
2
1
0
Reset
00H
ISP enable bit (ISPE) is read-only by default, software must write three specific values 55h, AAh and 5Ah
sequentially to the TAKEY register to enable the ISPE bit write attribute. That is:
MOV TAKEY, #55h
MOV TAKEY, #AAh
MOV TAKEY, #5Ah
Mnemonic: IFCON
7
6
CDPR
5
-
4
-
3
-
2
-
Address: 8FH
0
Reset
ISPE
00H
1
-
The bit 0 (ISPE) of IFCON is ISP enable bit. User can enable overall SM39R4051 ISP function by setting ISPE
bit to 1, to disable overall ISP function by set ISPE to 0. The function of ISPE behaves like a security key. User
can disable overall ISP function to prevent software program be erased accidentally. ISP registers ISPFAH,
ISPFAL, ISPFD and ISPFC are read-only by default. Software must be set ISPE bit to 1 to enable these 4
registers write attribute.
Mnemonic: ISPFAH
7
6
-
5
-
4
-
Address: E1H
3
2
1
0
Reset
ISPFAH3 ISPFAH2 ISPFAH1 ISPFAH0
FFH
ISPFAH [3:0]: Flash address-high for ISP function
Mnemonic: ISPFAL
7
6
ISPFAL7 ISPFAL6
5
ISPFAL5
4
ISPFAL4
3
ISPFAL3
2
ISPFAL2
1
ISPFAL1
Address: E2H
0
Reset
ISPFAL0
FFH
ISPFAL [7:0]: Flash address-Low for ISP function
The ISPFAH & ISPFAL provide the 12-bit flash memory address for ISP function. The flash memory address
should not include the ISP service program space address. If the flash memory address indicated by ISPFAH
& ISPFAL registers overlay with the ISP service program space address, the flash program/page erase of ISP
function executed thereafter will have no effect.
Mnemonic: ISPFD
7
6
ISPFD7
ISPFD6
5
ISPFD5
4
ISPFD4
3
ISPFD3
2
ISPFD2
1
ISPFD1
Address: E3H
0
Reset
ISPFD0
FFH
ISPFD [7:0]: Flash data for ISP function.
The ISPFD provide the 8-bit data register for ISP function.
Mnemonic: ISPFC
7
6
5
EMF1
EMF2
EMF3
4
EMF4
3
-
2
ISPF[2]
1
ISPF[1]
Address: E4H
0
Reset
ISPF[0]
00H
EMF1: Entry mechanism (1) flag, clear by reset. (Read only)
EMF2: Entry mechanism (2) flag, clear by reset. (Read only)
EMF3: Entry mechanism (3) flag, clear by reset. (Read only)
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M055
44
Ver.E SM39R4051 09/2011
SM39R4051/SM39R2051
8-Bit Micro-controller
4KB/2KB with ISP Flash
& 256B RAM embedded
EMF4: Entry mechanism (4) flag, clear by reset. (Read only)
ISPF [2:0]: ISP function select bit.
ISPF[2:0]
ISP function
000
Byte program
001
Chip protect
010
Page erase
011
Chip erase
100
Write option
101
Read option
110
Erase option
111
Finish Flag
One page of flash memory is 256 byte
The Option function can access the XTAL1 and XTAL2 configured to I/O pins
select(description in section 1.2)、Internal reset time select(description in section
1.4.1)、clock source select(description in section 1.5)、Reset configured to I/O pins
function select(description in section 5)、WDTEN control bit(description in section 8)、
or ISP entry mechanisms select(description in section 13)。
When chip protected or no ISP service, option can only read.
The choice ISP function will start to execute once the software write data to ISPFC register.
To perform byte program/page erases ISP function, user need to specify flash address at first. When
performing page erase function, SM39R4051 will erase entire page which flash address indicated by ISPFAH
& ISPFAL registers located within the page.
e.g. flash address: $YMN
page erase function will erase from $Y00 to $YFF
To perform the chip erase ISP function, SM39R4051 will erase all the flash program memory except the ISP
service program space. To perform chip protect ISP function, the SM39R4051 flash memory content will be
read #00H.
e.g. ISP service program to do the byte program - to program #22H to the address $0105H
MOV TAKEY, #55h
MOV TAKEY, #AAh
MOV TAKEY, #5Ah
MOV IFCON, #01H
MOV ISPFAH, #01H
MOV ISPFAL, #05H
MOV ISPFD, #22H
MOV ISPFC, #00H
; enable ISPE write attribute
; enable SM39R4051 ISP function
; set flash address-high, 01H
; set flash address-low, 05H
; set flash data to be programmed, data = 22H
; start to program #22H to the flash address $0105H
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M055
45
Ver.E SM39R4051 09/2011
SM39R4051/SM39R2051
8-Bit Micro-controller
4KB/2KB with ISP Flash
& 256B RAM embedded
Operating Conditions
Symbol
Description
Min.
Typ.
Max.
Unit.
Remarks
TA
Operating temperature
-40
25
85
℃
Ambient temperature under bias
VCC
Supply voltage
2.7
5.5
V
23MHz(Max)
VCC
Supply voltage
3.0
5.5
V
25MHz(Max)
DC Characteristics
TA = -40℃ to 85℃, VCC = 5.0V
Symbol
Parameter
Valid
Min
Max
Units
-0.5
0.8
V
0
0.8
V
2.0
VCC + 0.5
V
70%Vcc
VCC + 0.5
V
0.4
V
IOL=5.0mA
VIL1
Input Low-voltage
Port 1,3,4
VIL2
Input Low-voltage
RES, XTAL1
VIH1
Input High-voltage
Port 1,3,4
VIH2
Input High-voltage
RES, XTAL1
VOL
Output Low-voltage
Output High-voltage
using Strong Pull-up(1)
Output High-voltage
using Weak Pull-up(2)
Logic 0 Input Current
Logical Transition
Current
Input Leakage Current
Reset Pull-down
Resistor
Pin Capacitance
Port 1,3,4
VOH1
VOH2
IIL
ITL
ILI
RRST
CIO
ICC
Notes：
Conditions
Vcc=5V
Port 1,3,4
2.4
V
IOH= -16mA
Port 1,3,4
2.4
V
IOH= -280uA
Port 1,3,4
-75
uA
Vin= 0.45V
Port 1,3,4
-650
uA
Vin= 2.0V
Port 1,3,4
±10
uA
0.45V<Vin<Vcc
300
kΩ
10
pF
11
mA
10
mA
3
uA
RES
Power Supply Current VDD
50
Vcc=5V
Freq= 1MHz, Ta= 25℃
Active mode,
12MHz, Vcc=5V, 25 ℃
Idle mode,
12MHz, Vcc=5V, 25 ℃
Power down mode
Vcc=5V, 25 ℃
1. Port in Push-Pull Output Mode
2. Port in Quasi-Bidirectional Mode
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M055
46
Ver.E SM39R4051 09/2011
SM39R4051/SM39R2051
8-Bit Micro-controller
4KB/2KB with ISP Flash
& 256B RAM embedded
TA = -40℃ to 85℃, VCC = 3.0V
Symbol
Parameter
Valid
Min
Max
Units
-0.5
0.8
V
0
0.8
V
2.0
VCC + 0.5
V
70%Vcc
VCC + 0.5
V
0.4
V
IOL=3.0mA
VIL1
Input Low-voltage
Port 1,3,4
VIL2
Input Low-voltage
RES, XTAL1
VIH1
Input High-voltage
Port 1,3,4
VIH2
Input High-voltage
RES, XTAL1
VOL
Output Low-voltage
Output High-voltage
using Strong Pull-up(1)
Output High-voltage
using Weak Pull-up(2)
Logic 0 Input Current
Logical Transition
Current
Input Leakage Current
Reset Pull-down
Resistor
Pin Capacitance
Port 1,3,4
VOH1
VOH2
IIL
ITL
ILI
RRST
CIO
ICC
Notes：
Conditions
Vcc=3.0V
Port 1,3,4
2.4
V
IOH= -3.2mA
Port 1,3,4
2.4
V
IOH= -55uA
Vcc=3.0V
Port 1,3,4
-75
uA
Vin= 0.45V
Port 1,3,4
-650
uA
Vin=1.5V
Port 1,3,4
±10
uA
0.45V<Vin<Vcc
300
kΩ
10
pF
10
mA
9
mA
2
uA
RES
Power Supply Current VDD
50
Freq= 1MHz, Ta= 25℃
Active mode,
12MHz, Vcc=3.0V, 25 ℃
Idle mode,
12MHz, Vcc=3.0V, 25 ℃
Power down mode,
Vcc=3.0V, 25 ℃
1. Port in Push-Pull Output Mode
2. Port in Quasi-Bidirectional Mode
Suggest circuit connect：
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Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M055
47
Ver.E SM39R4051 09/2011