GPIO

GPIO 功能使用方法
GPIO 功能使用方法
1
适用产品：
1.1 SM59R16A2/SM59R08A2
1.2 SM59R16A5/SM59R09A5/SM59R05A5/SM59R16A3/SM59R09A3/SM59R05A3
1.3 SM59R04A2/SM59R04A1/SM59R03A1/SM59R02A1
2
以下说明仅适用：SM59R16A2/ SM59R08A2
2.1 P0 开源极之 I/O 型态[Open drain]，和标准 8051 相同。
2.2 P1~P5 皆有拉升电阻到 VDDIO，(1)当 VDDIO 浮接时，P1~P5 则视同 Open drain，(2)当 VDDIO
接至 VDD 时，P1~P5 则视同标准 51 之 I/O 型态[Quasi-bidirectional (pull-up)]。
3
以下说明适用：SM59R16A5/ SM59R09A5/ SM59R05A5/ SM59R16A3/ SM59R09A3/ SM59R05A3/
SM59R04A2/ SM59R04A1/ SM59R03A1/ SM59R02A1
原 I/O 名称
OCI_SCL
ALE
OCI_SDA
RESET
Xtal2
Xtal1
可设定为 GPIO 之对照表
SM59R16A5/SM59R09A5/
SM59R04A2/SM59R04A1/
SM59R05A5/SM59R16A3/
SM59R03A1/SM59R02A1
SM59R09A3/SM59R05A3
P4.4
P4.4
P4.5
P4.5
P4.6
P4.6
P4.7
P4.7
P5.4
无
P5.5
无
3.1 GPIO 使用概述：
3.2 于 40-pin PDIP 包装最高可提供 38 个 I/O，于 44-pin PLCC and PQFP 包装最高可提供 42 个 I/O，
于 48-pin LQFP 包装最高更可提供达 46 个 I/O 供客户使用。(于 SM59R16A5/SM59R09A5/
SM59R05A5/SM59R16A3/SM59R09A3/SM59R05A3 可多规划出 P5.4 及 P5.5)
3.3 于特殊功能使用时(如 SPI，Two UART，IIC，KBI，CCU，PWM)，可弹性定义使用之 I/O。
3.4 每一个 I/O 可分别定义为以下 4 种 I/O 型态之任一种：
3.4.1 标准51之I/O型态[Quasi-bidirectional (pull-up)]。
3.4.2 推挽式之I/O型态[Push-pull]。
3.4.3 仅为输入之I/O型态[Input only (high-impedance)]。
3.4.4 开源极之I/O型态[Open drain]。
Specifications subject to change without notice, contact your sales representatives for the most recent information.
ISSFA-0194
1
Ver A 2010/06
GPIO 功能使用方法
3.5 GPIO 相关的特殊缓存器 [GPIO Special Function Register] (SFR)
For SM59R04A2/SM59R04A1/SM59R03A1/SM59R02A1 used：
Mnemonic
Port 5
Port 4
Port 3
Port 2
Port 1
Port 0
Mnemonic
P0M0
P0M1
P1M0
P1M1
P2M0
P2M1
P3M0
P3M1
P4M0
P4M1
P5M0
P5M1
Mnemonic
AUX
Description
Port 5
Port 4
Port 3
Port 2
Port 1
Port 0
Direct
Bit 7
Bit 6
Bit 5
Ports
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESET
D8h
E8h
B0h
A0h
90h
80h
P4.7
P3.7
P2.7
P1.7
P0.7
P4.6
P3.6
P2.6
P1.6
P0.6
P4.5
P3.5
P2.5
P1.5
P0.5
P4.4
P3.4
P2.4
P1.4
P0.4
P5.3
P4.3
P3.3
P2.3
P1.3
P0.3
P5.2
P4.2
P3.2
P2.2
P1.2
P0.2
P5.1
P4.1
P3.1
P2.1
P1.1
P0.1
P5.0
P4.0
P3.0
P2.0
P1.0
P0.0
0Fh
FFh
FFh
FFh
FFh
FFh
Description
Direct
Port 0 output mode 0
Port 0 output mode 1
Port 1 output mode 0
Port 1 output mode 1
Port 2 output mode 0
Port 2 output mode 1
Port 3 output mode 0
Port 3 output mode 1
Port 4 output mode 0
Port 4 output mode 1
Port 5 output mode 0
Port 5 output mode 1
Description
Auxiliary register
D2h
D3h
D4h
D5h
D6h
D7h
DAh
DBh
DCh
DDh
DEh
DFh
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
I/O port function register
P0M0 [7:0]
P0M1[7:0]
P1M0[7:0]
P1M1[7:0]
P2M0[7:0]
P2M1[7:0]
P3M0[7:0]
P3M1[7:0]
P4M0[7:0]
P4M1[7:0]
-
Direct
Bit 7
Bit 6
91h
BGRS
P4CC
Bit 5
AUX
P4SPI
Bit 2
Bit 1
Bit 0
RESET
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
P5M0[3:0]
P5M1[3:0]
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESET
P4UR1
P4IIC
P0KBI
-
DPS
00H
Specifications subject to change without notice, contact your sales representatives for the most recent information.
ISSFA-0194
2
Ver A 2010/06
GPIO 功能使用方法
For SM59R16A5/SM59R09A5/SM59R05A5/SM59R16A3/SM59R09A3/SM59R05A3 used：
Mnemonic
Description
Port 5
Port 4
Port 3
Port 2
Port 1
Port 0
Port 5
Port 4
Port 3
Port 2
Port 1
Port 0
Mnemonic
P0M0
P0M1
P1M0
P1M1
P2M0
P2M1
P3M0
P3M1
P4M0
P4M1
P5M0
P5M1
Direct
Bit 7
Bit 6
D8h
E8h
B0h
A0h
90h
80h
P4.7
P3.7
P2.7
P1.7
P0.7
P4.6
P3.6
P2.6
P1.6
P0.6
Description
Direct
Port 0 output mode 0
Port 0 output mode 1
Port 1 output mode 0
Port 1 output mode 1
Port 2 output mode 0
Port 2 output mode 1
Port 3 output mode 0
Port 3 output mode 1
Port 4 output mode 0
Port 4 output mode 1
Port 5 output mode 0
Port 5 output mode 1
D2h
D3h
D4h
D5h
D6h
D7h
DAh
DBh
DCh
DDh
DEh
DFh
Mnemonic
Description
Direct
Bit 7
AUX
AUX2
Auxiliary register
Auxiliary register2
91h
92h
BGRS
-
Bit 5
Ports
P5.5
P4.5
P3.5
P2.5
P1.5
P0.5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESET
P5.4
P4.4
P3.4
P2.4
P1.4
P0.4
P5.3
P4.3
P3.3
P2.3
P1.3
P0.3
P5.2
P4.2
P3.2
P2.2
P1.2
P0.2
P5.1
P4.1
P3.1
P2.1
P1.1
P0.1
P5.0
P4.0
P3.0
P2.0
P1.0
P0.0
3Fh
FFh
FFh
FFh
FFh
FFh
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
I/O port function register
P0M0 [7:0]
P0M1[7:0]
P1M0[7:0]
P1M1[7:0]
P2M0[7:0]
P2M1[7:0]
P3M0[7:0]
P3M1[7:0]
P4M0[7:0]
P4M1[7:0]
P5M0[5:0]
P5M1[5:0]
Bit 6
Bit 5
Bit 4
AUX & AUX2
P4SPI
P4UR1
-
Bit 1
Bit 0
RESET
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
Bit 3
Bit 2
Bit 1
P4IIC
-
P0KBI
-
P2PWM
Bit 0
DPS
P42CC[1:0]
3.6 Port 0 至 Port 5 4 种 I/O 型态选择方式：
PxM1.y
0
0
1
1
PxM0.y
0
1
0
1
Port output mode
Quasi-bidirectional (standard 8051 port outputs) (pull-up)
Push-pull
Input only (high-impedance)
Open drain
3.7 特殊功能使用之 I/O 选择方式：
Mnemonic: AUX
7
BRGS
6
P4CC
5
P4SPI
Address: 91h
4
P4UR1
3
P4IIC
2
P0KBI
1
-
0
DPS
Reset
00H
P4CC: (Only SM59R04A2/SM59R04A1/SM59R03A1/SM59R02A1 have)
P4CC = 0 – Capture/Compare function on P1.
Specifications subject to change without notice, contact your sales representatives for the most recent information.
ISSFA-0194
3
Ver A 2010/06
RESET
00H
GPIO 功能使用方法
P4CC = 1 – Capture/Compare function on P4.
P4CC
0
1
CC0
P1.0
P4.0
CC1
P1.1
P4.1
CC2
P1.3
P4.2
CC3
P1.4
P4.3
P4SPI: P4SPI = 0 – SPI function on P1.
P4SPI = 1 – SPI function on P4.
P4SPI
0
1
SS
P1.4
P4.0
MOSI
P1.5
P4.1
MISO
P1.6
P4.2
SPI_CLK
P1.7
P4.3
P4UR1: P4UR1 = 0 – Serial interface 1 function on P1.
P4UR1 = 1 – Serial interface 1 function on P4.
P4UR1
0
1
RXD1
P1.2
P4.2
TXD1
P1.3
P4.3
P4IIC: P4IIC = 0 – IIC function on P1.
P4IIC = 1 – IIC function on P4.
P4IIC
0
1
IIC_SCL
P1.6
P4.0
IIC_SDA
P1.7
P4.1
P0KBI: P0KBI = 0 – KBI function on P2.
P0KBI = 1 – KBI function on P0.
P0KBI
0
1
KBI0
P2.0
P0.0
KBI1
P2.1
P0.1
KBI2
P2.2
P0.2
KBI3
P2.3
P0.3
KBI4
P2.4
P0.4
KBI5
P2.5
P0.5
KBI6
P2.6
P0.6
KBI7
P2.7
P0.7
于 SM59R16A5/SM59R09A5/SM59R05A5/SM59R16A3/SM59R09A3/SM59R05A3 多出以下两种：
a. PWM 可由 Port 4 输出换到 Port 2。
b. CCU 可由 Port 1 输出更换至 Port 2 或 Port 4。
Mnemonic: AUX
7
BRGS
6
5
P4SPI
Address: 91h
4
P4UR1
3
P4IIC
2
P0KBI
1
P2PWM
0
DPS
Reset
00H
P2PWM: P2PWM = 0 – PWM function on P4.
Specifications subject to change without notice, contact your sales representatives for the most recent information.
ISSFA-0194
4
Ver A 2010/06
GPIO 功能使用方法
P2PWM = 1 – PWM function on P2.
P2PWM PWM0 PWM1 PWM2 PWM3
0
P4.0
P4.1
P4.2
P4.3
1
P2.4
P2.5
P2.6
P2.7
Mnemonic: AUX2
7
6
Address: 92h
5
4
3
2
1
0
P42CC[1: 0]
Reset
00H
P42CC[1: 0] 00: Capture/Compare function on Port1.
01: Capture/Compare function on Port2
10: Capture/Compare function on Port4
11: reserved
P42CC[1:0
00
01
10
CC0
P1.0
P2.0
P4.0
CC1
P1.1
P2.1
P4.1
CC2
P1.3
P2.2
P4.2
CC3
P1.4
P2.3
P4.3
3.8 多 4 个 GPIO 之方法：
此颗 MCU 可用 ICP 或 ISP 等烧录模式将 OCI_SCL、ALE、OCI_SDA and RESET 等 I/O 定义成 P4.4、
P4.5、P4.6 and P4.7。
各种封装对应之 PIN 脚如下表：
OCI_SCL/P4.4
ALE/P4.5
OCI_SDA/P4.6
RESET/P4.7
40-PIN PDIP
29
30
31
9
44-PIN PLCC
32
33
35
10
44-PIN PQFP
26
27
29
4
48-PIN LQFP
29
30
32
5
于 SM59R16A5/SM59R09A5/SM59R05A5/SM59R16A3/SM59R09A3/SM59R05A3 更可将 Xtal2 及
Xtal1 定义成 P5.4、P5.5。
各种封装对应之 PIN 脚如下表：
Xtal2/P5.4
Xtal1/P5.5
40-PIN PDIP
18
19
44-PIN PLCC
20
21
44-PIN PQFP
14
15
48-PIN LQFP
15
16
Specifications subject to change without notice, contact your sales representatives for the most recent information.
ISSFA-0194
5
Ver A 2010/06