RENESAS 7721

To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
MITSUBISHI 16-BIT SINGLE-CHIP MICROCOMPUTER
7700 FAMILY / 7700 SERIES
7721
Group
User’s Manual
keep safety first in your circuit designs !
● Mitsubishi Electric Corporation puts the maximum effort into making semiconductor
products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury,
fire or property damage. Remember to give due consideration to safety when
making your circuit designs, with appropriate measures such as (i) placement
of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention
against any malfunction or mishap.
Notes regarding these materials
● These materials are intended as a reference to assist our customers in the
selection of the Mitsubishi semiconductor product best suited to the customer’s
application; they do not convey any license under any intellectual property rights,
or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
● Mitsubishi Electric Corporation assumes no responsibility for any damage, or
infringement of any third-party’s rights, originating in the use of any product
data, diagrams, charts or circuit application examples contained in these materials.
● All information contained in these materials, including product data, diagrams
and charts, represent information on products at the time of publication of these
materials, and are subject to change by Mitsubishi Electric Corporation without
notice due to product improvements or other reasons. It is therefore recommended
that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi
Semiconductor product distributor for the latest product information before
purchasing a product listed herein.
● Mitsubishi Electric Corporation semiconductors are not designed or manufactured
for use in a device or system that is used under circumstances in which human
life is potentially at stake. Please contact Mitsubishi Electric Corporation or an
authorized Mitsubishi Semiconductor product distributor when considering the
use of a product contained herein for any specific purposes, such as apparatus
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● Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi
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REVISION DESCRIPTION LIST
Rev.
No.
1.0
7721 Group User’s Manual
Revision Description
First Edition
Rev.
date
970926
(1/1)
Preface
This manual describes the hardware of the Mitsubishi
CMOS 16-bit microcomputers 7721 Group. After
reading this manual, the user will be able to understand
the functions, so that their capabilities can fully be
utilized.
BEFORE USING THIS MANUAL
1. Constitution
This user’s manual consists of the following chapters. Refer to the chapters relevant to the products.
● Chapter 1. DESCRIPTION through Chapter 16. APPLICATION
Functions which are common to the M37721S1BFP and the M37721S2BFP are explained, using the
M37721S2BFP as an example.
Differences between the M37721S1BFP and the M37721S2BFP are described as notes.
● Appendix
Practical information for using the 7721 Group is described.
2. Remark
● Product expansion
Refer to the latest catalog and data book, or contact the appropriate office, as listed in “CONTACT
ADDRESSES FOR FURTHER INFORMATION” on the last page.
● Electrical characteristics
Refer to the latest data book.
● Software
Refer to “7700 Family Software Manual.”
● Development support tools
Refer to the latest data book of the development support tools.
3. Signal levels in Figure
As a rule, signal levels in each operation example and timing diagram are as follows.
• Signal levels
The upper line indicates “1,” and the lower line indicates “0.”
• Input/output levels of pin
The upper line indicates “H,” and the lower line indicates “L.”
For the exception, the level is shown on the left side of a signal.
1
4. Register structure
Below is the structure diagram for all registers:
✽1
b7
b6
b5
b4
b3
b2
b1
b0
XXX register (Address XX16)
✕ 0
Bit
✽2
Bit name
Functions
✽3
At reset
RW
0
RW
Undefined
WO
0
RO
0
... select bit
0 : ...
1 : ...
1
... select bit
0 : ...
1 : ...
The value is “0” at reading.
2
... flag
0 : ...
1 : ...
3
Fix this bit to “0.”
0
RW
4
This bit is invalid in ... mode.
0
RW
Undefined
–
7 to 5 Nothing is assigned.
✽4
✽1
Blank
0
1
✕
: Set to “0” or “1” according to the usage.
: Set to “0” at writing.
: Set to “1” at writing.
: Invalid depending on the mode or state. It may be “0” or “1.”
: Nothing is assigned.
✽2
0
1
Undefined
: “0” immediately after reset.
: “1” immediately after reset.
: Undefined immediately after reset.
✽3
RW
RO
WO
—
2
: It is possible to read the bit state at reading. The written value becomes valid.
: It is possible to read the bit state at reading. The written value becomes invalid. Accordingly, the written
value may be “0” or “1.”
: The written value becomes valid. It is impossible to read the bit state. The value is undefined at reading.
However, when [“0” at reading”] is indicated in the “Function” or “Note” column, the bit is always “0” at
reading. (See ✽4 above.)
: It is impossible to read the bit state. The value is undefined at reading.
However, when [“0” at reading”] is indicated in the “Function” or “Note” column, the bit is always “0” at
reading. (See ✽4 above.)
The written value becomes invalid. Accordingly, the written value may be “0” or “1.”
Table of contents
Table of contents
CHAPTER 1 DESCRIPTION
1.1
1.2
1.3
1.4
Performance overview..........................................................................................................
Pin configuration...................................................................................................................
Pin description ......................................................................................................................
Block diagram ........................................................................................................................
1-2
1-3
1-4
1-7
CHAPTER 2 CENTRAL PROCESSING UNIT (CPU)
2.1 Central processing unit ....................................................................................................... 2-2
2.1.1 Accumulator (Acc) ......................................................................................................... 2-3
2.1.2 Index register X (X) ....................................................................................................... 2-3
2.1.3 Index register Y (Y) ....................................................................................................... 2-3
2.1.4 Stack pointer (S) ............................................................................................................ 2-4
2.1.5 Program counter (PC) ................................................................................................... 2-5
2.1.6 Program bank register (PG) ......................................................................................... 2-5
2.1.7 Data bank register (DT) ................................................................................................ 2-5
2.1.8 Direct page register (DPR) ........................................................................................... 2-6
2.1.9 Processor status register (PS) ..................................................................................... 2-7
2.2 Bus interface unit ................................................................................................................. 2-9
2.2.1 Overview ......................................................................................................................... 2-9
2.2.2 Functions of bus interface unit (BIU) ........................................................................ 2-11
2.2.3 Operation of bus interface unit (BIU)........................................................................ 2-13
2.3 Access space ....................................................................................................................... 2-15
2.3.1 Banks ............................................................................................................................ 2-16
2.3.2 Direct page ................................................................................................................... 2-16
2.4 Memory assignment ........................................................................................................... 2-17
2.4.1 Memory assignment in internal area ......................................................................... 2-17
2.4.2 External area ................................................................................................................ 2-18
2.5 Bus access right ................................................................................................................. 2-23
CHAPTER 3 CONNECTION WITH EXTERNAL DEVICES
3.1 Signals required for accessing external devices .......................................................... 3-2
3.1.1 Descriptions of signals .................................................................................................. 3-2
3.1.2 Operation of bus interface unit (BIU).......................................................................... 3-5
3.2 Software Wait ......................................................................................................................... 3-8
3.3 Ready function .................................................................................................................... 3-10
3.3.1 Operation description .................................................................................................. 3-11
3.4 Hold function ....................................................................................................................... 3-12
3.4.1 Operation description .................................................................................................. 3-12
[Precautions for Hold function] ............................................................................................ 3-16
7721 Group User’s Manual
i
Table of contents
CHAPTER 4 RESET
4.1 Hardware reset ...................................................................................................................... 4-2
4.1.1 Pin state .......................................................................................................................... 4-3
4.1.2 State of CPU, SFR area, and internal RAM area..................................................... 4-4
4.1.3 Internal processing sequence
after reset ................................................................. 4-11
______
4.1.4 Time supplying “L” level to RESET pin .................................................................... 4-12
4.2 Software reset ...................................................................................................................... 4-13
CHAPTER 5 CLOCK GENERATING CIRCUIT
5.1 Oscillation circuit examples ............................................................................................... 5-2
5.1.1 Connection example using resonator/oscillator .......................................................... 5-2
5.1.2 Externally generated clock input example .................................................................. 5-2
5.2 Clocks .......................................................................................................................................5-3
5.2.1 Clocks generated in clock generating circuit ............................................................. 5-4
5.3 Stop mode .............................................................................................................................. 5-5
5.3.1 Stop mode ...................................................................................................................... 5-5
[Precautions for Stop mode] .................................................................................................. 5-8
5.4 Wait mode ............................................................................................................................... 5-9
5.4.1 Wait mode ...................................................................................................................... 5-9
[Precautions for Wait mode] ................................................................................................. 5-11
CHAPTER 6 INPUT/OUTPUT PINS
6.1 Overview ..................................................................................................................................6-2
6.2 Programmable I/O ports ...................................................................................................... 6-2
6.2.1 Direction register ............................................................................................................ 6-3
6.2.2 Port register .................................................................................................................... 6-4
6.3 Examples of handling unused pins .................................................................................. 6-7
CHAPTER 7 INTERRUPTS
7.1 Overview ..................................................................................................................................7-2
7.2 Interrupt sources ................................................................................................................... 7-4
7.3 Interrupt control .................................................................................................................... 7-5
7.3.1 Interrupt disable flag (I) ................................................................................................ 7-7
7.3.2 Interrupt request bit ....................................................................................................... 7-7
7.3.3 Interrupt priority level select bits and processor interrupt priority level (IPL) ....... 7-7
7.4 Interrupt priority level .......................................................................................................... 7-9
7.5 Interrupt priority level detection circuit ........................................................................ 7-10
7.6 Interrupt priority level detection time ............................................................................ 7-12
7.7 Sequence from acceptance of interrupt request until execution of interrupt
routine .................................................................................................................................... 7-13
7.7.1 Change in IPL at acceptance of interrupt request .................................................. 7-14
7.7.2 Push operation for registers ....................................................................................... 7-15
7.8 Return from interrupt routine........................................................................................... 7-16
7.9 Multiple interrupts ...............................................................................................................
7-16
____
7.10 External interrupts
(INTi interrupt) ............................................................................... 7-18
____
7.10.1 Functions of ____
INTi interrupt request bit .................................................................... 7-20
7.10.2 Switching of INTi interrupt request occurrence factor .......................................... 7-21
7.11 Precautions for interrupts ............................................................................................... 7-22
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7721 Group User’s Manual
Table of contents
CHAPTER 8 TIMER A
8.1 Overview ..................................................................................................................................8-2
8.2 Block description .................................................................................................................. 8-3
8.2.1 Counter and reload register (timer Ai register) ......................................................... 8-4
8.2.2 Count start register........................................................................................................ 8-5
8.2.3 Timer Ai mode register ................................................................................................. 8-6
8.2.4 Timer Ai interrupt control register ............................................................................... 8-7
8.2.5 Port P5 direction register ............................................................................................. 8-8
8.3 Timer mode ............................................................................................................................ 8-9
8.3.1 Setting for timer mode ................................................................................................ 8-11
8.3.2 Count source ................................................................................................................ 8-13
8.3.3 Operation in timer mode ............................................................................................. 8-14
8.3.4 Selectable functions .................................................................................................... 8-15
[Precautions for timer mode] ................................................................................................ 8-17
8.4 Event counter mode ........................................................................................................... 8-18
8.4.1 Setting for event counter mode ................................................................................. 8-21
8.4.2 Operation in event counter mode .............................................................................. 8-23
8.4.3 Switching between countup and countdown ............................................................ 8-24
8.4.4 Selectable functions .................................................................................................... 8-25
[Precautions for event counter mode] ................................................................................. 8-28
8.5 One-shot pulse mode ......................................................................................................... 8-29
8.5.1 Setting for one-shot pulse mode ............................................................................... 8-31
8.5.2 Count source ................................................................................................................ 8-33
8.5.3 Trigger ........................................................................................................................... 8-34
8.5.4 Operation in one-shot pulse mode ............................................................................ 8-35
[Precautions for one-shot pulse mode] ............................................................................... 8-37
8.6 Pulse width modulation (PWM) mode ............................................................................ 8-38
8.6.1 Setting for PWM mode ............................................................................................... 8-40
8.6.2 Count source ................................................................................................................ 8-42
8.6.3 Trigger ........................................................................................................................... 8-42
8.6.4 Operation in PWM mode ............................................................................................ 8-43
[Precautions for PWM mode] ............................................................................................... 8-47
CHAPTER 9 TIMER B
9.1 Overview ..................................................................................................................................9-2
9.2 Block description .................................................................................................................. 9-2
9.2.1 Counter and reload register (timer Bi register) ......................................................... 9-3
9.2.2 Count start register........................................................................................................ 9-4
9.2.3 Timer Bi mode register ................................................................................................. 9-5
9.2.4 Timer Bi interrupt control register ............................................................................... 9-6
9.2.5 Port P5 direction register ............................................................................................. 9-7
9.3 Timer mode ............................................................................................................................ 9-8
9.3.1 Setting for timer mode ................................................................................................ 9-10
9.3.2 Count source ................................................................................................................ 9-11
9.3.3 Operation in timer mode ............................................................................................. 9-12
[Precautions for timer mode] ................................................................................................ 9-13
9.4 Event counter mode ........................................................................................................... 9-14
9.4.1 Setting for event counter mode ................................................................................. 9-16
9.4.2 Operation in event counter mode .............................................................................. 9-17
[Precautions for event coutner mode] ................................................................................. 9-18
7721 Group User’s Manual
iii
Table of contents
9.5 Pulse period/Pulse width measurement mode ............................................................. 9-19
9.5.1 Setting for pulse period/pulse width measurement mode ...................................... 9-21
9.5.2 Count source ................................................................................................................ 9-22
9.5.3 Operation in pulse period/pulse width measurement mode ................................... 9-23
[Precautions for pulse period/pulse width measurement mode] ...................................... 9-25
CHAPTER 10 REAL-TIME OUTPUT
10.1 Overview ............................................................................................................................. 10-2
10.2 Block description .............................................................................................................. 10-4
10.2.1 Real-time output control register ............................................................................. 10-4
10.2.2 Pulse output data registers 0 and 1 ....................................................................... 10-5
10.2.3 Port P6 direction register ......................................................................................... 10-6
10.2.4 Timers A0 and A1 ..................................................................................................... 10-6
10.3 Setting of real-time output ............................................................................................. 10-7
10.4 Real-time output operation ........................................................................................... 10-10
CHAPTER 11 SERIAL I/O
11.1 Overview ............................................................................................................................. 11-2
11.2 Block description .............................................................................................................. 11-3
11.2.1 UARTi transmit/receive mode register .................................................................... 11-4
11.2.2 UARTi transmit/receive control register 0 .............................................................. 11-6
11.2.3 UARTi transmit/receive control register 1 .............................................................. 11-7
11.2.4 UARTi transmit register and UARTi transmit buffer register ............................... 11-9
11.2.5 UARTi receive register and UARTi receive buffer register ................................ 11-11
11.2.6 UARTi baud rate register (BRGi) .......................................................................... 11-13
11.2.7 UARTi transmit interrupt control and UARTi receive interrupt control registers ......................... 11-14
11.2.8 Port P8 direction register ....................................................................................... 11-15
11.3 Clock synchronous serial I/O mode ........................................................................... 11-16
11.3.1 Transfer clock (Synchronizing clock) .................................................................... 11-17
11.3.2 Method of transmission ........................................................................................... 11-18
11.3.3 Transmit operation ................................................................................................... 11-21
11.3.4 Method of reception ................................................................................................ 11-23
11.3.5 Receive operation .................................................................................................... 11-27
11.3.6 Processing on detecting overrun error ................................................................. 11-29
[Precautions for clock synchronous serial I/O mode] ..................................................... 11-30
11.4 Clock asynchronous serial I/O (UART) mode .......................................................... 11-31
11.4.1 Transfer rate (Frequency of transfer clock) ......................................................... 11-32
11.4.2 Transfer data format ............................................................................................... 11-33
11.4.3 Method of transmission ........................................................................................... 11-34
11.4.4 Transmit operation ................................................................................................... 11-38
11.4.5 Method of reception ................................................................................................ 11-41
11.4.6 Receive operation .................................................................................................... 11-44
11.4.7 Processing on detecting error ................................................................................ 11-46
11.4.8 Sleep mode .............................................................................................................. 11-47
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7721 Group User’s Manual
Table of contents
CHAPTER 12 A-D CONVERTER
12.1 Overview ............................................................................................................................. 12-2
12.2 Block description .............................................................................................................. 12-3
12.2.1 A-D control register ................................................................................................... 12-4
12.2.2 A-D sweep pin select register ................................................................................. 12-6
12.2.3 A-D register i (i = 0 to 7) ......................................................................................... 12-7
12.2.4 A-D conversion interrupt control register ................................................................ 12-8
12.2.5 Port P7 direction register ......................................................................................... 12-9
12.3 A-D conversion method ................................................................................................. 12-10
12.4 Absolute accuracy and differential non-linearity error .......................................... 12-12
12.4.1 Absolute accuracy ................................................................................................... 12-12
12.4.2 Differential non-linearity error................................................................................. 12-13
12.5 One-shot mode ................................................................................................................ 12-14
12.5.1 Settings for one-shot mode .................................................................................... 12-14
12.5.2 One-shot mode operation description ................................................................... 12-16
12.6 Repeat mode .................................................................................................................... 12-17
12.6.1 Settings for repeat mode ........................................................................................ 12-17
12.6.2 Repeat mode operation description ...................................................................... 12-19
12.7 Single sweep mode ........................................................................................................ 12-20
12.7.1 Settings for single sweep mode ............................................................................ 12-20
12.7.2 Single sweep mode operation description ............................................................ 12-22
12.8 Repeat sweep mode ....................................................................................................... 12-24
12.8.1 Settings for repeat sweep mode ........................................................................... 12-24
12.8.2 Repeat sweep mode operation description .......................................................... 12-26
12.9 Precautions for A-D converter ..................................................................................... 12-28
CHAPTER 13 DMA CONTROLLER
13.1 Overview ............................................................................................................................. 13-2
13.1.1 Performance overview ............................................................................................... 13-2
13.1.2 Bus use priority levels .............................................................................................. 13-3
13.1.3 Modes .......................................................................................................................... 13-3
13.2 Block description .............................................................................................................. 13-6
13.2.1 Bus access control circuit ........................................................................................ 13-7
13.2.2 DMAC control register L ......................................................................................... 13-10
13.2.3 DMAC control register H ........................................................................................ 13-11
13.2.4 Source address register i (SARi) .......................................................................... 13-12
13.2.5 Destination address register i (DARi) ................................................................... 13-12
13.2.6 Transfer counter register i (TCRi) ......................................................................... 13-12
13.2.7 Incrementer/Decrementer ........................................................................................ 13-13
13.2.8 Decrementer ............................................................................................................. 13-13
13.2.9 DMA latch ................................................................................................................. 13-13
13.2.10 DMAi mode register L ........................................................................................... 13-14
13.2.11 DMAi mode register H .......................................................................................... 13-15
13.2.12 DMAi control register ............................................................................................ 13-16
13.2.13 DMAi interrupt control register ............................................................................. 13-17
13.2.14 Port P9 direction register ..................................................................................... 13-18
[Precautions for DMAC] ...................................................................................................... 13-18
7721 Group User’s Manual
v
Table of contents
13.3 Control ............................................................................................................................... 13-19
13.3.1 DMA enabling ........................................................................................................... 13-19
13.3.2 DMA requests .......................................................................................................... 13-20
13.3.3 Channel priority levels ............................................................................................ 13-21
13.3.4 Processing from DMA request until DMA transfer execution ............................ 13-23
13.3.5 Termination of DMA transfer .................................................................................. 13-25
13.3.6 DMA transfer restart after termination .................................................................. 13-28
13.4 Operation .......................................................................................................................... 13-30
13.4.1 2-bus cycle transfer ................................................................................................. 13-30
[Precautions for 2-bus cycle transfer] ............................................................................... 13-37
13.4.2 1-bus cycle transfer ................................................................................................. 13-38
[Precautions for 1-bus cycle transfer] ............................................................................... 13-47
13.4.3 Burst transfer mode................................................................................................. 13-48
[Precautions for burst transfer mode] ............................................................................... 13-50
13.4.4 Cycle-steal transfer mode ....................................................................................... 13-51
[Precautions for cycle-steal transfer mode] ...................................................................... 13-52
13.5 Single transfer mode...................................................................................................... 13-54
13.5.1 Setting of single transfer mode ............................................................................. 13-56
13.5.2 Operation in single transfer mode ......................................................................... 13-59
13.6 Repeat transfer mode .................................................................................................... 13-61
13.6.1 Setting of repeat transfer mode ............................................................................ 13-63
13.6.2 Operation in repeat transfer mode ........................................................................ 13-66
13.7 Array chain transfer mode ............................................................................................ 13-68
13.7.1 Transfer parameter memory in array chain transfer mode ................................ 13-70
13.7.2 Setting of array chain transfer mode .................................................................... 13-72
13.7.3 Operation in array chain transfer mode ............................................................... 13-75
[Precautions for array chain transfer mode] .................................................................... 13-79
13.8 Link array chain transfer mode ................................................................................... 13-80
13.8.1 Transfer parameter memory in link array chain transfer mode ......................... 13-82
13.8.2 Setting of link array chain transfer mode ............................................................. 13-84
13.8.3 Operation in link array chain transfer mode ........................................................ 13-87
[Precautions for link array chain transfer mode] ............................................................. 13-97
13.9 DMA transfer time ........................................................................................................... 13-98
13.9.1 Cycle-steal transfer mode ....................................................................................... 13-98
13.9.2 Burst transfer mode............................................................................................... 13-101
CHAPTER 14 DRAM CONTROLLER
14.1 Overview ............................................................................................................................. 14-2
14.2 Block description .............................................................................................................. 14-2
14.2.1 DRAM control register ............................................................................................... 14-3
14.2.2 Refresh timer .............................................................................................................. 14-5
14.2.3 ____
Address comparator
.................................................................................................. 14-6
____
14.2.4 RAS and CAS generating circuit ............................................................................. 14-6
14.2.5 Address multiplexer ................................................................................................... 14-6
14.3 Setting for DRAMC ........................................................................................................... 14-7
14.4 DRAMC operation ............................................................................................................. 14-8
14.4.1 Waveform example of DRAM control signals ........................................................ 14-8
14.4.2 Refresh request ....................................................................................................... 14-10
14.5 Precautions for DRAMC ................................................................................................ 14-12
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7721 Group User’s Manual
Table of contents
CHAPTER 15 WATCHDOG TIMER
15.1 Block description .............................................................................................................. 15-2
15.1.1 Watchdog timer .......................................................................................................... 15-3
15.1.2 Watchdog timer frequency select register .............................................................. 15-3
15.2 Operation description ...................................................................................................... 15-4
15.2.1 Basic operation .......................................................................................................... 15-4
15.2.2 Stop period ................................................................................................................. 15-6
15.2.3 Operation in Stop mode ........................................................................................... 15-6
15.3 Precautions for Watchdog timer ................................................................................... 15-7
CHAPTER 16 APPLICATION
16.1 Memory connection .......................................................................................................... 16-2
16.1.1 Memory connection model ........................................................................................ 16-2
16.1.2 How to calculate timing ............................................................................................ 16-4
16.1.3 Example of memory connection ............................................................................ 16-20
16.1.4 Example of I/O expansion ...................................................................................... 16-40
16.2 Examples of using DMA controller ............................................................................. 16-43
16.2.1 Example of Centronics interface configuration .................................................... 16-43
16.2.2 Example of stepping motor control ....................................................................... 16-48
16.2.3 Example of dynamic lighting for LED ................................................................... 16-53
16.3 Comparison of sample program execution rate ...................................................... 16-56
16.3.1 Differences depending on data bus width and software Wait ........................... 16-56
16.3.2 Comparison between software Wait (f(X IN) = 20 MHz) and software Wait + Ready (f(X IN) = 25 MHz) .... 16-58
APPENDIX
Appendix
Appendix
Appendix
Appendix
Appendix
Appendix
Appendix
Appendix
Appendix
Appendix
Appendix
Appendix
1. Memory assignment of 7721 Group ............................................................... 17-2
2. Memory assignment in SFR area ................................................................... 17-3
3. Control registers ................................................................................................. 17-9
4. Package outline ................................................................................................ 17-40
5. Examples of handling unused pins ............................................................. 17-41
6. Machine instructions ....................................................................................... 17-42
7. Hexadecimal instruction code table ............................................................. 17-56
8. Countermeasure against noise ...................................................................... 17-59
9. 7721 Group Q & A ........................................................................................... 17-65
10. Differences between 7721 Group and 7720 Group ................................. 17-79
11. Electrical characteristics .............................................................................. 17-80
12. Standard characteristics ............................................................................. 17-107
GLOSSARY
7721 Group User’s Manual
vii
Table of contents
MEMORANDUM
viii
7721 Group User’s Manual
CHAPTER 1
DESCRIPTION
1.1
1.2
1.3
1.4
Performance overview
Pin configuration
Pin description
Block diagram
DESCRIPTION
1.1 Performance overview
1.1 Performance overview
Table 1.1.1 lists the performance overview of the M37721.
Table 1.1.1 M37721 performance overview
Functions
Parameters
Number of basic instructions
103
Instruction execution time
160 ns (the minimum instruction at f(XIN) = 25 MHz)
External clock input frequency f(XIN)
ROM
Memory sizes
25 MHz (maximum)
External
RAM
M37721S2BFP
1024 bytes
M37721S1BFP
512 bytes
Programmable Input/Output
P5–P10
8 bits ✕ 6
ports
P4
5 bits ✕ 1
Multifunctional timers
TA0–TA4
Serial I/O
TB0–TB2
UART0, UART1
16 bits ✕ 5
16 bits ✕ 3
(UART or clock synchronous serial I/O) ✕ 2
A-D converter
Watchdog timer
8-bit successive approximation method ✕ 1 (8 channels)
DMA controller
4 channels
12 bits ✕ 1
Maximum transfer rate : 12.5 Mbytes/sec.
(at f(X IN) = 25 MHz, 1-bus cycle transfer)
Maximum transfer rate : 6.25 Mbytes/sec.
(at f(X IN) = 25
MHz, 2-bus cycle transfer)
____
____
DRAM controller
CAS before RAS refreshing method
Real-time output
4 bits ✕ 2 channels
or 6 bits ✕ 1 channel + 2 bits ✕ 1 channel
Interrupts
3 external, 20 internal (priority levels 0 to 7 can
be set for each interrupt with software)
Clock generating circuit
Built-in (externally connected to a ceramic
resonator or a quartz-crystal oscillator)
Supply voltage
5 V ±10 %
Power dissipation
135 mW (at f(X IN) = 25 MHz, typ.)
Port Input/Output
characteristics
Memory expansion
Input/Output withstand voltage 5 V
5 mA
Output current
Maximum 16 Mbytes
Operating temperature range
–20°C to 85°C
Device structure
CMOS high-performance silicon gate process
Package
100-pin plastic molded QFP
1–2
7721 Group User’s Manual
DESCRIPTION
1.2 Pin configuration
1.2 Pin configuration
Figure 1.2.1 shows the M37721S2BFP pin configuration.
P86/RXD1
P85/CLK1
P84/CTS1/RTS1
P83/TXD0
P82/RXD0
P81/CLK0
P80/CTS0/RTS0
VCC
AVCC
VREF
AVSS
VSS
P77/AN7/ADTRG
P76/AN6
P75/AN5
P74/AN4
P73/AN3
P72/AN2
P71/AN1
P70/AN0
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
13
14
15
16
17
18
19
20
M37721S2BFP
P67/RTP13
P66/RTP12
P65/RTP11
P64/RTP10
P63/RTP03
P62/RTP02
P61/RTP01
P60/RTP00
P57/TB1IN
P56/TB0IN
P55/TA4IN
P54/TA4OUT
P53/TA3IN
P52/TA3OUT
P51/TA2IN
P50/TA2OUT
P107/MA9
P106/MA8
P105/RAS
P104/CAS
P103/TC
P102/INT2
P101/INT1
P100/INT0
P47
P46
P45
P44
P43
69
68
67
66
65
64
63
62
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
P87/TXD1
P90/DMAACK0
P91/DMAREQ0
P92/DMAACK1
P93/DMAREQ1
P94/DMAACK2
P95/DMAREQ2
P96/DMAACK3
P97/DMAREQ3
A0/MA0
A1/MA1
A2/MA2
A3/MA3
A4/MA4
A5/MA5
A6/MA6
A7/MA7
A8/D8
A9/D9
A10/D10
A11/D11
A12/D12
A13/D13
A14/D14
A15/D15
A16/D0
A17/D1
A18/D2
A19/D3
A20/D4
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A21/D5
A22/D6
A23/D7
R/W
BHE
BLE
ALE
ST0
ST1
VCC
VSS
E
XOUT
XIN
RESET
RESETOUT
CNVSS
BYTE
HOLD
RDY
Outline 100P6S-A
Fig. 1.2.1 M37721S2BFP pin configuration (top view)
7721 Group User’s Manual
1–3
DESCRIPTION
1.3 Pin description
1.3 Pin description
Tables 1.3.1 to 1.3.3 list the pin description.
Table 1.3.1 Pin description (1)
Pin
Name
Vcc, Vss
Power supply
CNVss
CNVss
Input/Output
Functions
Supply 5 V ±10 % to Vcc pin and 0 V to Vss pin.
Reset input
Input
Input
RESETOUT
Reset output
Output
When input to RESET pin is “L,” this pin outputs “L.”
Output from this pin returns “H” after the release of
reset. When writing “1” to the software reset bit, this
pin outputs “L.”
XIN
Clock input
Input
XOUT
Clock output
Output
These are I/O pins of the internal clock generating
circuit. Connect a ceramic resonator or quartz-crystal
oscillator between pins X IN and X OUT. When using an
E
Enable output
Output
BYTE
Exernal data bus width Input
selection input
ST0
Status signal output
______
RESET
________
_
Output
1–4
Data/instruction code read or data write is performed
when output from this pin is “L” level.
Input level to this pin determines whether the external
data bus has a 16-bit width or an 8-bit width. The
width is 16 bits when the level is “L”, and 8 bits when
the level is “H”.
The bus use state is output in 2-bit code.
ST1 ST0 Bus use state
0
0
DRAM refresh
0
1
Hold
1
1
0
DMA
1
CPU
Analog supply input
The power supply pin for the A-D converter. Connect
AVcc to Vcc pin. Connect AVss to Vss pin.
Reference voltage input Input
This is a reference voltage input pin for the A-D converter.
AVss
VREF
The microcomputer is reset when supplying “L” level
to this pin.
______
external clock, the clock source should be input to X IN
pin and X OUT pin should be left open.
ST1
AVcc
Connect to Vss or Vcc pin.
7721 Group User’s Manual
DESCRIPTION
1.3 Pin description
Table 1.3.2 Pin description (2)
Pin
A7/MA7
Name
Input/Output
Address low-order/ Output
DRAM address
A8/D8–
Address middle-order/
A15/D15
data high-order
A0/MA0–
Functions
Low-order 8 bits (A0 –A 7) of the address are output.
When the DRAM is accessed, the row and column
addresses are output with the time-sharing.
●External data bus width = 8 bits (When the BYTE
pin is “H” level)
I/O
Middle-order 8 bits (A8–A15) of the address are output.
●External data bus width = 16 bits (When the BYTE
pin is “L” level)
Data (D8–D15) input/output and output of the middleorder 8 bits (A 8–A 15) of the address are performed
with the time-sharing.
A16/D0–
Address high-order/
A23/D 7
data low-order
Data (D0–D7) input/output and output of the high-order
8 bits (A16–A 23) of the address are performed with the
time-sharing.
__
I/O
__
R/W,
____
BHE,
____
Memory control signal Output
output
●R/W
The Read/Write signal indicates the data bus state.
The state is read while this signal is “H” level, and
write
while this signal is “L” level.
____
BLE,
ALE
●BHE
“L” level is output when an odd-numbered address is
accessed.
____
●BLE
“L” level is output when an even-numbered address
is accessed.
●ALE
This is used to obtain only the address from address
and data multiplex signals.
_____
HOLD
Hold input
Input
The microcomputer
is in Hold state while “L” level is
_____
RDY
Ready input
Input
input to the HOLD pin.
The microcomputer
is in Ready state while “L” level is
____
input to the RDY pin.
φ1
Clock φ 1 output
Output
This is the φ1 output pin.
____
7721 Group User’s Manual
1–5
DESCRIPTION
1.3 Pin description
Table 1.3.3 Pin description (3)
Pin
Input/Output
P43–P4 7
Name
I/O port P4
I/O
Functions
Port P4 is a 5-bit CMOS I/O port. This port has an
I/O direction register and each pin can be programmed
for input or output.
P50–P5 7
I/O port P5
I/O
Port P5 is an 8-bit I/O port with the same function as
P4. These pins can be programmed as I/O pins for
Timers A2–A4 and I/O pins for Timers B0, B1.
P60–P6 7
I/O port P6
I/O
Port P6 is an 8-bit I/O port with the same function as
P4. These pins can be programmed as output pins for
the real-time output.
P70–P7 7
I/O port P7
I/O
Port P7 is an 8-bit I/O port with the same function as
P4. These pins can be programmed as input pins for
A-D converter.
P80–P8 7
I/O port P8
I/O
Port P8 is an 8-bit I/O port with the same function as
P4. These pins can be programmed as I/O pins for
Serial I/O.
P90–P9 7
I/O port P9
I/O
P100–
P10 7
I/O port P10
I/O
Port P9 is an 8-bit I/O port with the same function as
P4. These pins can be programmed as I/O pins for
DMA controller.
Port P10 is an 8-bit I/O port with the same function __
as
P4. These pins can be programmed as I/O pin for TC
and output pins for DRAM controller.
___
___
P100–P102 also function as input pins for INT0–INT 2.
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7721 Group User’s Manual
1
Clock 1
output
Enable
output
E
Reset
input
RESET
Reset
output
RESETOUT
CNVss
Input Buffer Register IB (16)
Processor Status Register PS (11)
Direct Page Register DPR (16)
Index Register Y (16)
Stack Pointer S (16)
Index Register X (16)
Accumulator B (16)
Accumulator A (16)
Arithmetic Logic
Unit (16)
7721 Group User’s Manual
UART1 (9)
UART0 (9)
P6 (8)
Input/Output
port P6
Timer TB1 (16)
Timer TB0 (16)
P7 (8)
Input/Output
port P7
Timer TA1 (16)
Timer TA0 (16)
Input/Output
port P8
Data Bank Register DT (8)
Input/Output
port P9
Program Bank Register PG (8)
Input/Output
port P10
Program Counter PC (16)
Timer TB2 (16)
Input/Output
port P4
P4 (5)
DRAM Controller
BLE
Address/Data
Address/Data (16)
DMA0 (16)
DMA1 (16)
Instruction Queue Buffer Q0 (8)
Input/Output
port P5
P5 (8)
A-D Converter (8)
DMA2 (16)
DMA3 (16)
Instruction Queue Buffer Q1 (8)
P8 (8)
Incrementer/Decrementer (24)
Timer TA2 (16)
Data Address Register DA (24)
Watchdog Timer
BHE
Instruction Register (8)
R/W
Instruction Queue Buffer Q2 (8)
Timer TA3 (16)
Program Address Register PA (24)
Bus
Interface
Unit
(BIU)
HOLD
Status signal
output
ST0
ST1
ALE
Memory control signal
output
Address (8)
Data Bus (Odd)
P9 (8)
AVCC
Reference External data bus width
voltage input
selection input
VREF
BYTE
RDY
Incrementer (24)
Central Processing Unit (CPU)
(0V)
AVSS
Data Buffer DBL (8)
Timer TA4 (16)
VCC
(0V)
VSS
Data Buffer DBH (8)
P10 (8)
ROM
1024 Bytes
Clock Generating Circuit
Clock input Clock output
XIN
XOUT
DESCRIPTION
1.4 Block diagram
1.4 Block diagram
Figure 1.4.1 shows the M37721 block diagram.
Data Bus (Even)
Address Bus
Note: For the M37721S1BFP, the RAM size is 512 bytes.
Fig. 1.4.1 M37721 block diagram
1–7
DESCRIPTION
1.4 Block diagram
MEMORANDUM
1–8
7721 Group User’s Manual
CHAPTER 2
CENTRAL
PROCESSING UNIT
(CPU)
2.1
2.2
2.3
2.4
2.5
Central processing unit
Bus interface unit
Access space
Memory assignment
Bus access right
CENTRAL PROCESSING UNIT (CPU)
2.1 Central processing unit
2.1 Central processing unit
The CPU (Central Processing Unit) has the ten registers as shown in Figure 2.1.1.
b15
b0
b8 b7
AH
b15
b0
b8 b7
BH
Accumulator B (B)
BL
b15
b0
b8 b7
XH
Index register X (X)
XL
b15
b0
b8 b7
YH
YL
b15
Index register Y (Y)
b0
b8 b7
SH
b7
Accumulator A (A)
AL
Stack pointer (S)
SL
b0
Data bank register (DT)
DT
b16 b15
b23
PG
b8 b7
b0
PCH
b7
Program counter (PC)
PCL
b0
Program bank register (PG)
b15
b0
b8 b7
DPRH
DPRL
b15
b0
b8 b7
PSH
b15
0
b10
0
0
0
0
Direct page register (DPR)
b8 b7 b6
IPL
Processor status register (PS)
PSL
N V
b5 b4 b3 b2
b1
b0
m
Z
C
x
D
I
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Index register length flag
Data length flag
Overflow flag
Negative flag
Processor interrupt priority level
Fig. 2.1.1 CPU registers structure
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7721 Group User’s Manual
CENTRAL PROCESSING UNIT (CPU)
2.1 Central processing unit
2.1.1 Accumulator (Acc)
Accumulators A and B are available.
(1) Accumulator A (A)
Accumulator A is the main register of the microcomputer. The transaction of data such as calculation,
data transfer, and input/output are performed mainly through accumulator A. It consists of 16 bits,
and the low-order 8 bits can also be used separately. The data length flag (m) determines whether
the register is used as a 16-bit register or as an 8-bit register. When an 8-bit register is selected,
only the low-order 8 bits of accumulator A are used and the contents of the high-order 8 bits is
unchanged.
(2) Accumulator B (B)
Accumulator B is a 16-bit register with the same function as accumulator A. Accumulator B can be
used instead of accumulator A. The use of accumulator B, however except for some instructions,
requires more instruction bytes and execution cycles than that of accumulator A. Accumulator B is
also controlled by the data length flag (m) just as in accumulator A.
2.1.2 Index register X (X)
Index register X consists of 16 bits and the low-order 8 bits can also be used separately. The index register
length flag (x) determines whether the register is used as a 16-bit register or as an 8-bit register. When
an 8-bit register is selected, only the low-order 8 bits of index register X are used and the contents of the
high-order 8 bits is unchanged.
In an addressing mode in which index register X is used as an index register, the address obtained by
adding the contents of this register to the operand’s contents is accessed.
In the MVP or MVN instruction, a block transfer instruction, the contents of index register X indicate the
low-order 16 bits of the source address. The third byte of the instruction is the high-order 8 bits of the
source address.
Note: Refer to “7700 Family Software Manual” for addressing modes.
2.1.3 Index register Y (Y)
Index register Y is a 16-bit register with the same function as index register X. Just as in index register
X, the index register length flag (x) determines whether this register is used as a 16-bit register or as an
8-bit register.
In the MVP or MVN instruction, a block transfer instruction, the contents of index register Y indicate the
low-order 16 bits of the destination address. The second byte of the instruction is the high-order 8 bits of
the destination address.
7721 Group User’s Manual
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CENTRAL PROCESSING UNIT (CPU)
2.1 Central processing unit
2.1.4 Stack pointer (S)
The stack pointer (S) is a 16-bit register. It is used for a subroutine call or an interrupt. It is also used when
addressing modes using the stack are executed. The contents of S indicate an address (stack area) for
storing registers during subroutine calls and interrupts. Stack area is selected by the stack bank select bit
described later (bit 7 at address 5E16). The stack area is specified to bank 016 when the stack bank select
bit is “0,” and the stack area is specified to bank FF 16 when it is “1.”
When an interrupt request is accepted, the microcomputer stores the contents of the program bank register
(PG) at the address indicated by the contents of S and decrements the contents of S by 1. Then the
contents of the program counter (PC) and the processor status register (PS) are stored. The contents of
S after accepting an interrupt request is equal to the contents of S decremented by 5 before the accepting
of the interrupt request. (Refer to “Figure 2.1.2.”)
When completing the process in the interrupt routine and returning to the original routine, the contents of
registers stored in the stack area are restored into the original registers in the reverse sequence (PS→PC→PG)
by executing the RTI instruction. The contents of S is returned to the state before accepting an interrupt
request.
The same operation is performed during a subroutine call, however, the contents of PS is not automatically
stored. (The contents of PG may not be stored. This depends on the addressing mode.)
The user should store registers other than those described above with software when the user needs them
during interrupts or subroutine calls.
Additionally, initialize S at the beginning of the program because its contents are undefined at reset. The
stack area changes when subroutines are nested or when multiple interrupt requests are accepted. Therefore,
make sure of the subroutine’s nesting depth not to destroy the necessary data.
Note: Refer to “7700 Family Software Manual” for addressing modes.
Stack area
Address
S–5
S–4
Processor status register’s low-order byte (PSL)
S–3 Processor status register’s high-order byte (PSH)
S–2
Program counter’s low-order byte (PCL)
S–1
Program counter’s high-order byte (PCH)
S
Program bank register (PG)
● “S” is the initial address that the stack pointer (S)
indicates at accepting an interrupt request.
The S’s contents become “S–5” after storing the
above registers.
Fig. 2.1.2 Stored registers of the stack area
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7721 Group User’s Manual
CENTRAL PROCESSING UNIT (CPU)
2.1 Central processing unit
2.1.5 Program counter (PC)
The program counter is a 16-bit counter that indicates the low-order 16 bits of the address (24 bits) at
which an instruction to be executed next (in other words, an instruction to be read out from an instruction
queue buffer next) is stored. The contents of the high-order program counter (PCH) become “FF16,” and the
low-order program counter (PCL) becomes “FE16” at reset. The contents of the program counter becomes
the contents of the reset’s vector address (addresses FFFE 16, FFFF 16) immediately after reset.
Figure 2.1.3 shows the program counter and the program bank register.
(b23)
b7
(b16)
b0 b15
b8 b7
PCH
PG
b0
PCL
Fig. 2.1.3 Program counter and program bank register
2.1.6 Program bank register (PG)
The access space is divided in units of 64 Kbytes. This unit is called “bank.” (Refer to section “2.3 Access
space.”)
The program bank register is an 8-bit register. This register indicates the high-order 8 bits (bank) of the
address (24 bits) at which an instruction to be executed next (in other words, an instruction to be read out
from an instruction queue buffer next) is stored. These 8 bits are called bank.
When a carry occurs after adding the contents of the program counter or adding the offset value to the
contents of the program counter in the branch instruction and others, the contents of the program bank
register is automatically incremented by 1. When a borrow occurs after subtracting the contents of the
program counter, the contents of the program bank register is automatically decremented by 1. Accordingly,
there is no need to consider bank boundaries in programming, usually.
This register is cleared to “00 16” at reset.
2.1.7 Data bank register (DT)
The data bank register is an 8-bit register. In the following addressing modes using the data bank register,
the contents of this register is used as the high-order 8 bits (bank) of a 24-bit address to be accessed.
Use the LDT instruction to set a value to this register.
This register is cleared to “00 16” at reset.
●Addressing modes using data bank register
•Direct indirect
•Direct indexed X indirect
•Direct indirect indexed Y
•Absolute
•Absolute bit
•Absolute indexed X
•Absolute indexed Y
•Absolute bit relative
•Stack pointer relative indirect indexed Y
7721 Group User’s Manual
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CENTRAL PROCESSING UNIT (CPU)
2.1 Central processing unit
2.1.8 Direct page register (DPR)
The direct page register is a 16-bit register. The contents of this register indicate the direct page area
which is allocated in bank 016 or in the space across banks 016 and 116. The following addressing modes
use the direct page register.
The contents of the direct page register indicate the base address (the lowest address) of the direct page
area. The space which extends to 256 bytes above that address is specified as a direct page.
The direct page register can contain a value from “000016” to “FFFF16.” When it contains a value equal to
or more than “FF0116,” the direct page area spans the space across banks 016 and 1 16.
When the contents of low-order 8 bits of the direct page register is “0016,” the number of cycles required
to generate an address is 1 cycle smaller than the number when its contents are not “00 16.” Accordingly,
the access efficiency can be enhanced in this case.
This register is cleared to “000016” at reset.
Figure 2.1.4 shows a setting example of the direct page area.
●Addressing modes using direct page register
•Direct
•Direct bit
•Direct indexed X
•Direct indexed Y
•Direct indirect
•Direct indexed X indirect
•Direct indirect indexed Y
•Direct indirect long
•Direct indirect long indexed Y
•Direct bit relative
016
016
FF16
12316
Bank 016
22216
FF1016
FFFF16
1000016
Direct page area when DPR =
“000016”
Direct page area when DPR =
“012316”(Note 1)
Direct page area when DPR =
“FF1016” (Note 2)
1000F16
Bank 116
Notes 1: The number of cycles required to generate an address is 1 cycle smaller when the
low-order 8 bits of the DPR are “0016.”
2: The direct page area spans the space across banks 0 16 and 1 16 when the DPR is
“FF0116” or more.
Fig. 2.1.4 Setting example of direct page area
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7721 Group User’s Manual
CENTRAL PROCESSING UNIT (CPU)
2.1 Central processing unit
2.1.9 Processor status register (PS)
The processor status register is an 11-bit register.
Figure 2.1.5 shows the structure of the processor status register.
b15 b14 b13 b12 b11 b10 b9
0
0
0
0
0
IPL
b8
b7
b6
b5
b4
b3
b2
b1
b0
N
V
m
x
D
I
Z
C
Processor status
register (PS)
Note: Bits 11–15 is always “0” at reading.
Fig. 2.1.5 Processor status register structure
(1) Bit 0: Carry flag (C)
It retains a carry or a borrow generated in the arithmetic and logic unit (ALU) during an arithmetic
operation. This flag is also affected by shift and rotate instructions. When the BCC or BCS instruction
is executed, this flag’s contents determine whether the program causes a branch or not.
Use the SEC or SEP instruction to set this flag to “1,” and use the CLC or CLP instruction to clear
it to “0.”
(2) Bit 1: Zero flag (Z)
It is set to “1” when a result of an arithmetic operation or data transfer is “0,” and cleared to “0” when
otherwise. When the BNE or BEQ instruction is executed, this flag’s contents determine whether the
program causes a branch or not.
Use the SEP instruction to set this flag to “1,” and use the CLP instruction to clear it to “0.”
Note: This flag is invalid in the decimal mode addition (the ADC instruction).
(3) Bit 2: Interrupt disable flag (I)
It disables all maskable interrupts (interrupts other than watchdog timer, the BRK instruction, and
zero division). Interrupts are disabled when this flag is “1.” When an interrupt request is accepted,
this flag is automatically set to “1” to avoid multiple interrupts. Use the SEI or SEP instruction to set
this flag to “1,” and use the CLI or CLP instruction to clear it to “0.” This flag is set to “1” at reset.
(4) Bit 3: Decimal mode flag (D)
It determines whether addition and subtraction are performed in binary or decimal. Binary arithmetic
is performed when this flag is “0.” When it is “1,” decimal arithmetic is performed with 8 bits treated
as two digits decimal (the data length flag (m) = “1”) or 16 bits treated as four digits decimal (the
data length flag (m) = “0”). Decimal adjust is automatically performed. Decimal operation is possible
only with the ADC and SBC instructions. Use the SEP instruction to set this flag to “1,” and use the
CLP instruction to clear it to “0.” This flag is cleared to “0” at reset.
(5) Bit 4: Index register length flag (x)
It determines whether each of index register X and index register Y is used as a 16-bit register or
an 8-bit register. That register is used as a 16-bit register when this flag is “0,” and as an 8-bit
register when it is “1.” Use the SEP instruction to set this flag to “1,” and use the CLP instruction
to clear it to “0.” This flag is cleared to “0” at reset.
Note: When transferring data between registers which are different in bit length, the data is transferred
with the length of the destination register, but except for the TXA, TYA, TXB, TYB, and TXS
instructions. Refer to “7700 Family Software Manual” for details.
7721 Group User’s Manual
2–7
CENTRAL PROCESSING UNIT (CPU)
2.1 Central processing unit
(6) Bit 5: Data length flag (m)
It determines whether to use a data as a 16-bit unit or as an 8-bit unit. A data is treated as a 16bit unit when this flag is “0,” and as an 8-bit unit when it is “1.”
Use the SEM or SEP instruction to set this flag to “1,” and use the CLM or CLP instruction to clear
it to “0.” This flag is cleared to “0” at reset.
Note: When transferring data between registers which are different in bit length, the data is transferred
with the length of the destination register, but except for the TXA, TYA, TXB, TYB, and TXS
instructions. Refer to “7700 Family Software Manual” for details.
(7) Bit 6: Overflow flag (V)
It is used when adding or subtracting with a word regarded as signed binary. When the data length
flag (m) is “0,” the overflow flag is set to “1” when the result of addition or subtraction exceeds the
range between –32768 and +32767, and cleared to “0” in all other cases. When the data length flag
(m) is “1,” the overflow flag is set to “1” when the result of addition or subtraction exceeds the range
between –128 and +127, and cleared to “0” in all other cases.
The overflow flag is also set to “1” when a result of division exceeds the register length to be stored
in a division instruction DIV.
When the BVC or BVS instruction is executed, this flag’s contents determine whether the program
causes a branch or not.
Use the SEP instruction to set this flag to “1,” and use the CLV or CLP instruction to clear it to “0.”
Note: This flag is invalid in the decimal mode.
(8) Bit 7: Negative flag (N)
It is set to “1” when a result of arithmetic operation or data transfer is negative. (Bit 15 of the result
is “1” when the data length flag (m) is “0,” or bit 7 of the result is “1” when the data length flag (m)
is “1.”) It is cleared to “0” in all other cases. When the BPL or BMI instruction is executed, this flag
determines whether the program causes a branch or not. Use the SEP instruction to set this flag to
“1,” and use the CLP instruction to clear it to “0.”
Note: This flag is invalid in the decimal mode.
(9) Bits 10 to 8: Processor interrupt priority level (IPL)
These three bits can determine the processor interrupt priority level to one of levels 0 to 7. The
interrupt is enabled when the interrupt priority level of a required interrupt, which is set in each
interrupt control register, is higher than IPL. When an interrupt request is accepted, IPL is stored in
the stack area, and IPL is replaced by the interrupt priority level of the accepted interrupt request.
There are no instruction to directly set or clear the bits of IPL. IPL can be changed by storing the
new IPL into the stack area and updating the processor status register with the PUL or PLP instruction.
The contents of IPL is cleared to “000 2” at reset.
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CENTRAL PROCESSING UNIT (CPU)
2.2 Bus interface unit
2.2 Bus interface unit
A bus interface unit (BIU) is built-in between the central processing unit (CPU) and memory•I/O devices.
BIU’s function and operation are described below.
When externally connecting devices, refer to “CHAPTER 3. CONNECTION WITH EXTERNAL DEVICES.”
2.2.1 Overview
Transfer operation between the CPU and memory•I/O devices is always performed via the BIU.
➀ The BIU reads an instruction from the memory before the CPU executes it.
➁ When the CPU reads data from the memory•I/O device, the CPU first specifies the address from which
data is read to the BIU. The BIU reads data from the specified address and passes it to the CPU.
➂ When the CPU writes data to the memory•I/O device, the CPU first specifies the address to which data
is written to the BIU and write data. The BIU writes the data to the specified address.
➃ To perform the above operations ➀ to ➂, the BIU inputs and outputs the control signals, and control the
bus.
Figure 2.2.1 shows the bus and bus interface unit (BIU).
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(BIU)
(CPU)
Fig. 2.2.1 Bus and bus interface unit (BIU)
7721 Group User’s Manual
Internal control signal
Internal bus A0 to A23
Internal bus D0 to D7
Internal bus D8 to D15
Internal bus
Bus
conversion
circuit
Internal
peripheral
device
(SFR)
Internal
memory
External bus
Control signals
A16/D0 to A23/D7
A8/D8 to A15/D15
A0 to A7
Notes 1: The CPU bus, internal bus, and external bus are independent of one another.
2: Refer to “CHAPTER 3. CONNECTION WITH EXTERNAL DEVICES” about control signals
of the external bus.
SFR : Special Function Register
Bus
interface
unit
CPU bus
Central
processing
unit
M37721
External
device
CENTRAL PROCESSING UNIT (CPU)
2.2 Bus interface unit
CENTRAL PROCESSING UNIT (CPU)
2.2 Bus interface unit
2.2.2 Functions of bus interface unit (BIU)
The bus interface unit (BIU) consists of four registers shown in Figure 2.2.2. Table 2.2.1 lists the functions
of each register.
b0
b23
Program address register
PA
b0
b7
Q0
Instruction queue buffer
Q1
Q2
b23
b0
Data address register
DA
b15
DBH
b0
DB L
Data buffer
Fig. 2.2.2 Register structure of bus interface unit (BIU)
Table 2.2.1 Functions of each register
Name
Functions
Program address register
Indicates the storage address for the instruction which is next taken into the
instruction queue buffer.
Instruction queue buffer
Temporarily stores the instruction which has been taken in.
Data address register
Indicates the address for the data which is next read from or written to.
Data buffer
Temporarily stores the data which is read from the memory•I/O device by the
BIU or which is written to the memory•I/O device by the CPU.
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CENTRAL PROCESSING UNIT (CPU)
2.2 Bus interface unit
The CPU and the bus send or receive data via BIU because each operates based on different clocks
(Note). The BIU allows the CPU to operate at high speed without waiting for access to the memory • I/O
devices that require a long access time.
The BIU’s functions are described bellow.
φCPU. The period of φCPU is normally
the same as that of φ. The internal
Note: The CPU operates based on _
_
bus operates based on the E signal. The period of the E signal is twice that of φ at a minimum.
(1) Reading out instruction (Instruction prefetch)
When the CPU does not require to read or write data, that is, when the bus is not in use, the BIU
reads instructions from the memory and stores them in the instruction queue buffer. This is called
instruction prefetch.
The CPU reads instructions from the instruction queue buffer and executes them, so that the CPU
can operate at high speed without waiting for access to the memory which requires a long access
time.
When the instruction queue buffer becomes empty or contains only 1 byte of an instruction, the BIU
performs instruction prefetch. The instruction queue buffer can store instructions up to 3 bytes.
The contents of the instruction queue buffer is initialized when a branch or jump instruction is
executed, and the BIU reads a new instruction from the destination address.
When instructions in the instruction queue buffer are insufficient for the CPU’s needs, the BIU
extends the pulse duration of clock φCPU in order to keep the CPU waiting until the BIU fetches the
required number of instructions or more.
(2) Reading data from memory•I/O device
The CPU specifies the storage address of data to be read to the BIU’s data address register, and
requires data. The CPU waits until data is ready in the BIU.
The BIU outputs the address received from the CPU onto the address bus, reads contents at the
specified address, and takes it into the data buffer.
The CPU continues processing, using data in the data buffer.
However, if the BIU uses the bus for instruction prefetch when the CPU requires to read data, the
BIU keeps the CPU waiting.
(3) Writing data to memory•I/O device
The CPU specifies the address of data to be written to the BIU’s data address register. Then, the
CPU writes data into the data buffer. The BIU outputs the address received from the CPU onto the
address bus and writes data in the data buffer into the specified address.
The CPU advances to the next processing without waiting for completion of BIU’s write operation.
However, if the BIU uses the bus for instruction prefetch when the CPU requires to write data, the
BIU keeps the CPU waiting.
(4) Bus control
To perform the above operations (1) to (3), the BIU inputs and outputs the control signals, and
controls the address bus and the data bus. The cycle in which the BIU controls the bus and accesses
the memory•I/O device is called the bus cycle.
Refer to “CHAPTER 3. CONNECTION WITH EXTERNAL DEVICES” about the bus cycle at accessing
the external devices.
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CENTRAL PROCESSING UNIT (CPU)
2.2 Bus interface unit
2.2.3 Operation of bus interface unit (BIU)
Figure 2.2.3 shows the basic operating waveforms of the bus interface unit (BIU).
About signals which are input/output externally when accessing external devices, refer to “CHAPTER 3.
CONNECTION WITH EXTERNAL DEVICES.”
(1) When fetching instructions into the instruction queue buffer
➀ When the instruction which is next fetched is located at an even address, the BIU fetches 2 bytes
at a time with the timing of waveform (a).
However, when accessing an external device which is connected with the 8-bit external data bus
width (BYTE = “H”), only 1 byte of the instruction is fetched.
➁ When the instruction which is next fetched is located at an odd address, the BIU fetches only 1
byte with the timing of waveform (a). The contents at the even address are not taken into the
instruction queue buffer.
(2) When reading or writing data to and from the memory•I/O device
➀ When accessing a 16-bit data which begins at an even address, waveform (a) is applied. The 16
bits of data are accessed at a time.
➁ When accessing a 16-bit data which begins at an odd address, waveform (b) is applied. The 16
bits of data are accessed separately in 2 operations, 8 bits at a time. Invalid data is not fetched
into the data buffer.
➂ When accessing an 8-bit data at an even address, waveform (a) is applied. The data at the odd
address is not fetched into the data buffer.
➃ When accessing an 8-bit data at an odd address, waveform (a) is applied. The data at the even
address is not fetched into the data buffer.
For instructions that are affected by the data length flag (m) and the index register length flag (x),
operation ➀ or ➁ is applied when flag m or x = “0”; operation ➂ or ➃ is applied when flag m or x
= “1.”
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CENTRAL PROCESSING UNIT (CPU)
2.2 Bus interface unit
(a)
E
Internal address bus (A0
to A23)
to D7)
Data (Even address)
to D15)
Data (Odd address)
Internal data bus (D0
Internal data bus (D8
Address
(b)
E
to A23)
Internal address bus (A0
Invalid data
Data (Even address)
to D15)
Data (Odd address)
Invalid data
Fig. 2.2.3 Basic operating waveforms of bus interface unit (BIU)
2–14
Address (Even address)
to D7)
Internal data bus (D0
Internal data bus (D8
Address (Odd address)
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CENTRAL PROCESSING UNIT (CPU)
2.3 Access space
2.3 Access space
Figure 2.3.1 shows the M37721’s access space.
By combination of the program counter (PC), which is 16 bits of structure, and the program bank register
(PG), a 16-Mbyte space from addresses 016 to FFFFFF16 can be accessed. For details about access of an
external area, refer to “CHAPTER 3. CONNECTION WITH EXTERNAL DEVICES.”
The memory and I/O devices are assigned in the same access space. Accordingly, it is possible to perform
transfer and arithmetic operations using the same instructions without discrimination of the memory from
I/O devices.
00000016
00007F16
00008016
SFR area
Internal RAM area
00047F16
Bank 016
001FC016
001FFF16
SFR area
00FFFF16
01000016
Bank 116
02000016
:
:
:
:
FE000016
Bank FE16
: Indicates the memory assignment
of the internal areas.
FF000016
Bank FF16
: Indicates that nothing is assigned.
FFFFFF16
Note : Memory assignment of internal RAM area varies according to the type of microcomputer.
This figure shows the case of the M37721S2BFP.
Refer to “Figure 2.4.1” for the M37721S1BFP.
SFR : Special Function Register
Fig. 2.3.1 M37721’s access space
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CENTRAL PROCESSING UNIT (CPU)
2.3 Access space
2.3.1 Banks
The access space is divided in units of 64 Kbytes. This unit is called “bank.” The high-order 8 bits of
address (24 bits) indicate a bank, which is specified by the program bank register (PG) or data bank
register (DT). Each bank can be accessed efficiently by using an addressing mode that uses the data bank
register (DT).
If the program counter (PC) overflows at a bank boundary, the contents of the program bank register (PG)
is incremented by 1. If a borrow occurs in the program counter (PC) as a result of subtraction, the contents
of the program bank register (PG) is decremented by 1. Normally, accordingly, the user can program
without concern for bank boundaries.
SFR (Special Function Register) and internal RAM are assigned in bank 016. For details, refer to section
“2.4 Memory assignment.”
2.3.2 Direct page
A 256-byte space specified by the direct page register (DPR) is called “direct page.” A direct page is
specified by setting the base address (the lowest address) of the area to be specified as a direct page into
the direct page register (DPR).
By using a direct page addressing mode, a direct page can be accessed with less instruction cycles than
otherwise.
Note: Refer also to section “2.1 Central processing unit.”
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CENTRAL PROCESSING UNIT (CPU)
2.4 Memory assignment
2.4 Memory assignment
This section describes the internal area’s memory assignment. For more information about the external
area, refer also to “CHAPTER 3. CONNECTION WITH EXTERNAL DEVICES.”
Figure 2.4.1 shows the memory assignment.
2.4.1 Memory assignment in internal area
SFR (Special Function Register) and internal RAM are assigned in the internal area.
(1) SFR area
The registers for setting internal peripheral devices are assigned at addresses 016 to 7F16 and 1FC016
to 1FFF16. This area is called SFR. Figures 2.4.2 and 2.4.3 show the SFR area’s memory assignment.
For each register in the SFR area, refer to each functional description in this manual.
For the state of the SFR area immediately after reset, refer to section “4.1.2 State of CPU, SFR
area, and internal RAM area.”
(2) Internal RAM area
The M37721S2BFP (Note 1) assigns the 1024-byte static RAM at addresses 8016 to 47F16. 512 bytes
of that can be selected either it is used as the internal RAM or it is used as the external area. (Note
2)
The internal RAM area is used as a stack area (Note 3), as well as an area to store data. Accordingly,
note that set the nesting depth of a subroutine and multiple interrupts’ level not to destroy the
necessary data.
Notes 1: The M37721S1BFP assigns the 512-byte static RAM at addresses 8016 to 27F 16.
2: The internal RAM area becomes 512 bytes after reset because the internal RAM area
select bit is “0.”
3: Either bank 0 16 or bank FF16 can be selected as the stack area by the stack bank select
bit (bit 7 at address 5E 16).
Figure 2.4.4 shows the structure of the processor mode registers 0, 1.
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CENTRAL PROCESSING UNIT (CPU)
2.4 Memory assignment
2.4.2 External area
Table 2.4.1 lists the external area. When connecting the external device, follow the procedure described
bellow:
•Connect the ROM to addresses FFCE 16 to FFFF 16 because they are interrupt vector table.
•Stack area can be assigned to bank 016 or bank FF16. Select the stack area by the stack bank select bit
(bit 7 at address 5E 16). (Refer to “Figure 2.4.4.”)
•When using the DRAM controller, DRAM area can be selected from address FFFFFF16 toward the loworder address in a unit of 1 Mbytes. (Refer to “CHAPTER 14. DRAM CONTROLLER.”)
In the case connecting an external device to the area where overlaps the internal area, when reading out
the overlapping area, the central processing unit (CPU) take in data of the internal area and do not take
in data of the external area.
When writing to the overlapping area, data is written to the internal area. The signal is output to the
external at the same timing when data is written to the internal area.
Table 2.4.1 External area
M37721S2BFP
Type name
Internal RAM area select bit
External area
1
M37721S1BFP
0
216–916
480 16–1FBF 16
28016–1FBF 16
2000 16–FFFFFF16
Internal RAM area select bit : bit 1 at address 5F16
2–18
“0” (Fix this bit to “0.”)
2 16–9 16
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200016–FFFFFF16
CENTRAL PROCESSING UNIT (CPU)
2.4 Memory assignment
M37721S2BFP
M37721S1BFP
SFR area (Note 1)
SFR area (Note 1)
00000016
00007F16
00008016
00027F16
00FFCE16
00FFD016
00FFD216
00FFD416
00FFD616
00FFD816
00FFDA16
00FFDC16
00FFDE16
00FFE016
00FFE216
00FFE416
00FFE616
00FFE816
00FFEA16
00FFEC16
00FFEE16
00FFF016
00FFF216
00FFF416
00FFF616
00FFF816
00FFFA16
00FFFC16
00FFFE16
Interrupt vector table
L
DMA3
H
L
DMA2
H
L
DMA1
H
L
DMA0
H
A-D conversion L
H
L
UART1 transmit
H
L
UART1 receive H
UART0 transmit L
H
UART0 receive L
H
L
Timer B2 H
L
Timer B1 H
L
Timer B0 H
L
Timer A4 H
L
Timer A3 H
L
Timer A2 H
L
Timer A1 H
L
Timer A0 H
L
INT2
H
L
INT1
H
L
INT0
H
L
Watchdog timer H
L
DBC (Note 3) H
BRK instruction L
H
L
zero divide
H
L
RESET
H
AA
(512 bytes)
Case of Internal RAM
area select bit = “0”
Internal RAM
area
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
(512 bytes)
Case of Internal RAM
area select bit = “1”
00047F16
001FC016
SFR area
001FFF16
00FFCE16
00FFFF16
FFFFFF16
: The internal memory is not assigned.
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
Internal RAM area
(512 bytes) (Note 2)
SFR area
SFR area: Refer to “Figure 2.4.2” and “Figure 2.4.3.”
Notes 1: Addresses 216 to 916 are the external memory area.
2: For the M37721S1BFP, fix the internal RAM area select bit to “0.”
3: DBC is an interrupt only for debugging; do not use this interrupt.
Fig. 2.4.1 Memory assignment
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CENTRAL PROCESSING UNIT (CPU)
2.4 Memory assignment
Address
00000016
00000116
00000216
00000316
00000416
00000516
00000616
00000716
00000816
00000916
00000A16 Port P4 register
00000B16 Port P5 register
00000C16 Port P4 direction register
00000D16 Port P5 direction register
00000E16 Port P6 register
00000F16 Port P7 register
00001016 Port P6 direction register
00001116 Port P7 direction register
00001216 Port P8 register
00001316 Port P9 register
00001416 Port P8 direction register
00001516 Port P9 direction register
00001616 Port P10 register
00001716
00001816 Port P10 direction register
00001916
00001A16 Pulse output data register 0
00001B16
00001C16 Pulse output data register 1
00001D16
00001E16 A-D control register
00001F16 A-D sweep pin select register
00002016 A-D register 0
00002116
00002216 A-D register 1
00002316
00002416 A-D register 2
00002516
00002616 A-D register 3
00002716
00002816 A-D register 4
00002916
00002A16 A-D register 5
00002B16
00002C16 A-D register 6
00002D16
00002E16 A-D register 7
00002F16
00003016 UART0 transmit/receive mode register
00003116 UART0 baud rate register (BRG0)
00003216 UART0 transmit buffer register
00003316
00003416 UART0 transmit/receive control register 0
00003516 UART0 transmit/receive control register 1
00003616 UART0 receive buffer register
00003716
00003816 UART1 transmit/receive mode register
00003916 UART1 baud rate register (BRG1)
00003A16
UART1 transmit buffer register
00003B16
00003C16 UART1 transmit/receive control register 0
00003D16 UART1 transmit/receive control register 1
00003E16
UART1 receive buffer register
00003F16
Address
00004016 Count start register
00004116
00004216 One-shot start register
00004316
00004416 Up-down register
00004516
00004616 Timer A0 register
00004716
00004816 Timer A1 register
00004916
00004A16 Timer A2 register
00004B16
00004C16 Timer A3 register
00004D16
00004E16 Timer A4 register
00004F16
00005016 Timer B0 register
00005116
00005216 Timer B1 register
00005316
00005416 Timer B2 register
00005516
00005616 Timer A0 mode register
00005716 Timer A1 mode register
00005816 Timer A2 mode register
00005916 Timer A3 mode register
00005A16 Timer A4 mode register
00005B16 Timer B0 mode register
00005C16 Timer B1 mode register
00005D16 Timer B2 mode register
00005E16 Processor mode register 0
00005F16 Processor mode register 1
00006016 Watchdog timer register
00006116 Watchdog timer frequency select register
00006216 Real-time output control register
00006316
00006416 DRAM control register
00006516
00006616 Refresh timer
00006716
00006816 DMAC control register L
00006916 DMAC control register H
00006A16
00006B16
00006C16 DMA0 interrupt control register
00006D16 DMA1 interrupt control register
00006E16 DMA2 interrupt control register
00006F16 DMA3 interrupt control register
00007016 A-D conversion interrupt control register
00007116 UART0 transmit interrupt control register
00007216 UART0 receive interrupt control register
00007316 UART1 transmit interrupt control register
00007416 UART1 receive interrupt control register
00007516 Timer A0 interrupt control register
00007616 Timer A1 interrupt control register
00007716 Timer A2 interrupt control register
00007816 Timer A3 interrupt control register
00007916 Timer A4 interrupt control register
00007A16 Timer B0 interrupt control register
00007B16 Timer B1 interrupt control register
00007C16 Timer B2 interrupt control register
00007D16 INT0 interrupt control register
00007E16 INT1 interrupt control register
00007F16 INT2 interrupt control register
Fig. 2.4.2 SFR area’s memory map (1)
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CENTRAL PROCESSING UNIT (CPU)
2.4 Memory assignment
Address
001FC016
001FC116
001FC216
001FC316
001FC416
001FC516
001FC616
001FC716
001FC816
001FC916
001FCA16
001FCB16
001FCC16
001FCD16
001FCE16
001FCF16
001FD016
001FD116
001FD216
001FD316
001FD416
001FD516
001FD616
001FD716
001FD816
001FD916
001FDA16
001FDB16
001FDC16
001FDD16
001FDE16
001FDF16
001FE016
001FE116
001FE216
001FE316
001FE416
001FE516
001FE616
001FE716
001FE816
001FE916
001FEA16
001FEB16
001FEC16
001FED16
001FEE16
001FEF16
001FF016
001FF116
001FF216
001FF316
001FF416
001FF516
001FF616
001FF716
001FF816
001FF916
001FFA16
001FFB16
001FFC16
001FFD16
001FFE16
001FFF16
Source address register 0
L
M
H
Destination address register 0
L
M
H
Transfer counter register 0
L
M
H
DMA0 mode register L
DMA0 mode register H
DMA0 control register
Source address register 1
L
M
H
Destination address register 1
L
M
H
Transfer counter register 1
L
M
H
DMA1 mode register L
DMA1 mode register H
DMA1 control register
Source address register 2
L
M
H
Destination address register 2
L
M
H
Transfer counter register 2
L
M
H
DMA2 mode register L
DMA2 mode register H
DMA2 control register
Source address register 3
L
M
H
Destination address register 3
L
M
H
Transfer counter register 3
L
M
H
DMA3 mode register L
DMA3 mode register H
DMA3 control register
Fig. 2.4.3 SFR area’s memory map (2)
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2.4 Memory assignment
b7
b6
b5
b4
b3
b2
b1
0
b0
0
Processor mode register 0 (Address 5E16)
Bit
Bit name
Functions
At reset
RW
0
Fix this bit to “0.”
0
RW
1
Nothing is assigned.
The value is “1” at reading.
1
–
2
Wait bit
0 : Software Wait is inserted when
accessing external area.
1 : No software Wait is inserted
when accessing external area.
0
RW
3
Software reset bit
The microcomputer is reset by
writing “1” to this bit. The value is
“0” at reading.
0
WO
4
Interrupt priority detection time
select bits
0
RW
0
RW
0
RW
0
RW
5
6
Fix this bit to “0.”
7
Stack bank select bit
b5 b4
0 0 : 7 cycles of
0 1 : 4 cycles of
1 0 : 2 cycles of
1 1 : Do not select.
0 : Bank 016
1 : Bank FF16
: Bits 0 to 6 are not used for the memory assignment.
b7
b6
b5
b4
b3
b2
b1
b0
Processor mode register 1 (Address 5F16)
Bit
Functions
Bit name
0
Nothing is assigned.
1
Internal RAM area select bit
(Notes 1, 2)
0 : 512 bytes (addresses 8016 to 27F16)
1 : 1024 bytes (addresses 8016 to 47F16)
7 to 2 Nothing is assigned.
Notes 1: For the M37721S1BFP, fix bit 1 to “0.”
2: For the M37721S2BFP, set bit 1 before setting the stack pointer.
Fig. 2.4.4 Structure of processor mode registers 0, 1
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At reset
RW
Undefined
–
0
RW
Undefined
–
CENTRAL PROCESSING UNIT (CPU)
2.5 Bus access right
2.5 Bus access right
The M37721’s bus is used for DRAMC, Hold function, and DMAC besides CPU. When the bus requests of
two or more source are detected at the same timing, the highest bus access priority levels get the access
right.
The bus priority levels are fixed by hardware. Additionally the bus use state is output from the status signal
output pins ST0 and ST1. Table 2.5.1 lists the bus use priority levels and the status signals depending on
the bus use state.
Table 2.5.1 Bus use priority levels and status signals depending on bus use state
Bus use priority levels
Bus use state
Status signal
ST1
0
ST0
0
Hold
0
1
3
DMAC
1
0
4 (Lowest)
CPU (Including the term that CPU does not use the bus
during calculation etc.)
1
1
1 (Highest)
DRAM refresh
2
For details, refer to section “13.2.1 Bus access control circuit” and chapter for each peripheral devices.
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2.5 Bus access right
MEMORANDUM
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CHAPTER 3
CONNECTION WITH
EXTERNAL DEVICES
3.1 Signals required for accessing
external devices
3.2 Software Wait
3.3 Ready function
3.4 Hold function
[Precautions for Hold function]
CONNECTION WITH EXTERNAL DEVICES
3.1 Signals required for accessing external devices
3.1 Signals required for accessing external devices
The functions and operations of the signals which are required for accessing the external devices are
described below.
When connecting an external device that requires long access time, refer to sections “3.2 Software Wait,”
“3.3 Ready function,” and “3.4 Hold function,” as well as this section. When the external DRAM is
controlled by using DRAM controller, refer to “CHAPTER 14. DRAM CONTROLLER.”
3.1.1 Descriptions of signals
Figure 3.1.1 shows the pin configurations when the external data bus width is 16 bits and 8 bits.
(1) External buses (A0–A7, A 8/D8–A15/D15, A16/D 0–A23/D7)
The external area is specified by the address (A 0–A 23) output.
The A 8–A 23 pins of the external address bus and the D0 –D 15 pins of the external data bus are
assigned to the same pins.
When the BYTE pin level, described later, is “L” (external data bus width is 16 bits), the A8/D 8–
A 15/D 15 and A16/D 0–A23/D 7 pins perform address output and data input/output with time-sharing.
When the BYTE pin level is “H” (external data bus width is 8 bits), the A16/D 0–A 23/D 7 pins perform
address output and data input/output with time-sharing, and the A8–A15 pins output the address.
(2) External data bus width switching signal (BYTE pin level)
This signal is used to select the external data bus width from 8 bits and 16 bits. The width is 16 bits
when the level is “L,” and 8 bits when the level is “H.” Fix this signal to either “H” or “L” level. This
signal is valid only for the external area. (When accessing the internal area, the data bus width is
always 16 bits.)
__
(3) Enable signal (E)
This signal becomes “L” level while reading or writing data from and to the data bus. (Refer to
“Table 3.1.1.”)
__
(4) Read/Write signal (R/W)
This signal indicates the state of the data bus. This signal becomes “L” level
while writing
data to
__
__
the data bus. Table 3.1.1 lists the state of the data bus indicated with the E and R/W signals.
_
Table 3.1.1 State
of data bus indicated with E and
__
R/W signals
__
__
State of data bus
E
R/W
H
H
Not used
L
L
H
L
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Read data
Write data
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P67/RTP13
P66/RTP12
P65/RTP11
P64/RTP10
P63/RTP03
P62/RTP02
P61/RTP01
P60/RTP00
P57/TB1IN
P56/TB0IN
P55/TA4IN
P54/TA4OUT
P53/TA3IN
P52/TA3OUT
P51/TA2IN
P50/TA2OUT
P107/MA9
P106/MA8
P105/RAS
P104/CAS
P103/TC
P102/INT2
P101/INT1
P100/INT0
P47
P46
P45
P44
P43
P86/RXD1
P85/CLK1
P84/CTS1/RTS1
P83/TXD0
P82/RXD0
P81/CLK0
P80/CTS0/RTS0
VCC
AVCC
VREF
AVSS
VSS
P77/AN7/ADTRG
P76/AN6
P75/AN5
P74/AN4
P73/AN3
P72/AN2
P71/AN1
P70/AN0
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P87/TXD1
P90/DMAACK0
P91/DMAREQ0
P92/DMAACK1
P93/DMAREQ1
P94/DMAACK2
P95/DMAREQ2
P96/DMAACK3
P97/DMAREQ3
A0/MA0
A1/MA1
A2/MA2
A3/MA3
A4/MA4
A5/MA5
A6/MA6
A7/MA7
A8
A9
A10
A11
A12
A13
A14
A15
A16/D0
A17/D1
A18/D2
A19/D3
A20/D4
1
P67/RTP13
P66/RTP12
P65/RTP11
P64/RTP10
P63/RTP03
P62/RTP02
P61/RTP01
P60/RTP00
P57/TB1IN
P56/TB0IN
P55/TA4IN
P54/TA4OUT
P53/TA3IN
P52/TA3OUT
P51/TA2IN
P50/TA2OUT
P107/MA9
P106/MA8
P105/RAS
P104/CAS
P103/TC
P102/INT2
P101/INT1
P100/INT0
P47
P46
P45
P44
P43
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P86/RXD1
P85/CLK1
P84/CTS1/RTS1
P83/TXD0
P82/RXD0
P81/CLK0
P80/CTS0/RTS0
VCC
AVCC
VREF
AVSS
VSS
P77/AN7/ADTRG
P76/AN6
P75/AN5
P74/AN4
P73/AN3
P72/AN2
P71/AN1
P70/AN0
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P87/TXD1
P90/DMAACK0
P91/DMAREQ0
P92/DMAACK1
P93/DMAREQ1
P94/DMAACK2
P95/DMAREQ2
P96/DMAACK3
P97/DMAREQ3
A0/MA0
A1/MA1
A2/MA2
A3/MA3
A4/MA4
A5/MA5
A6/MA6
A7/MA7
A8/D8
A9/D9
A10/D10
A11/D11
A12/D12
A13/D13
A14/D14
A15/D15
A16/D0
A17/D1
A18/D2
A19/D3
A20/D4
CONNECTION WITH EXTERNAL DEVICES
3.1 Signals required for accessing external devices
●External data bus width = 16 bits (BYTE = “L”)
A21/D5
A22/D6
A23/D7
R/W
BHE
BLE
ALE
ST0
ST1
VCC
VSS
E
XOUT
XIN
RESET
RESETOUT
CNVSS
BYTE
HOLD
RDY
: External address bus, external data bus,
bus control signal
●External data bus width = 8 bits (BYTE = “H”)
A21/D5
A22/D6
A23/D7
R/W
BHE
BLE
ALE
ST0
ST1
VCC
VSS
E
XOUT
XIN
RESET
RESETOUT
CNVSS
BYTE
HOLD
RDY
: External address bus, external data bus,
bus control signal
Note: For the DRAM control signals, refer to “CHAPTER 14. DRAM CONTROLLER.”
Fig. 3.1.1 Pin configurations when external data bus width is 16 bits and 8 bits (top view)
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CONNECTION WITH EXTERNAL DEVICES
3.1 Signals required for accessing external devices
____
____
(5) Byte____
low enable signal (BLE), Byte high enable signal (BHE)
The BLE signal indicates the access to an even address. This signal becomes “L” level when
accessing
only an even address or when simultaneously accessing both an even and an odd address.
____
The BHE signal indicates the access to an odd address. This signal becomes “L” level when accessing
only an odd address or when simultaneously accessing both an odd and an even address.
These signals are used to connect memories or I/O devices of which
data bus
width is 8 bits when
____
____
the external data bus width is 16 bits. Table 3.1.2 lists levels of the BLE and BHE signals and access
addresses.
____
____
Table 3.1.2 Levels of BLE and BHE signals and access addresses
Even and odd addresses
Even address
Odd address
(Simultaneous 2-byte access)
(1-byte access)
(1-byte access)
BLE
L
L
H
BHE
L
H
L
Access address
____
____
(6) Address latch enable signal (ALE)
This signal is used to latch the address from the multiplexed signal, which consists of the address
and data. (This multiplexed signal is input to or output from the A8/D8–A15/D15 and A16/D0–A23/D7 pins.)
When the ALE signal is “H,” latch the address and simultaneously output the addresses. When this
signal is “L,” retain the latched address.
____
(7) Ready function-related signal (RDY)
This is the signal to use Ready function (Refer to section “3.3 Ready function.”)
_____
(8) Hold function-related signal (HOLD)
This is the signal to use Hold function. (Refer to section “3.4 Hold function.”)
(9) Status signals (ST0, ST1)
These signals indicate the bus use status. Table 3.1.3 lists the bus use status indicated by the ST0
and ST1 signals.
(10) Clock φ 1
This signal has the same period as φ .
Table 3.1.3 Bus use status indicated by ST0 and
ST1 signals
ST1
ST0
L
L
H
DRAM refresh
Hold
L
DMA
H
CPU
L
H
H
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Bus use status
CONNECTION WITH EXTERNAL DEVICES
3.1 Signals required for accessing external devices
3.1.2 Operation of bus interface unit (BIU)
Figures 3.1.2 and 3.1.3 show the examples of operating waveforms of the signals input from or output to
the external when accessing external devices. The following explains these waveforms, being compared
with the basic operating waveform. (Refer to section “2.2.3 Operation of bus interface unit (BIU).”)
(1) When fetching instructions into instruction queue buffer
➀ When the instruction which is next fetched is located at an even address
When the external data bus width is 16 bits, the BIU fetches 2 bytes of the instruction at a time
with waveform (a). When the external data bus width is 8 bits, the BIU fetches only 1 byte of the
instruction with the first half of waveform (e).
➁ When the instruction which is next fetched is located at an odd address
When the external data bus width is 16 bits, the BIU fetches only 1 byte of the instruction with
waveform (d). When the external data bus width is 8 bits, the BIU fetches only 1 byte of the
instruction with the first half of waveform (f).
When a branch to an odd address is caused by a branch instruction etc. with the 16-bit external data
bus width, the BIU first fetches 1 byte of the instruction with waveform (d), and after that, fetches
instructions in a unit of 2 bytes with waveform (a).
(2) When reading or writing data from and to memories or I/O devices
➀ When accessing 16-bit data which begins at an even address, waveform (a) or (e) is applied.
➁ When accessing 16-bit data which begins at an odd address, waveform (b) or (f) is applied.
➂ When accessing 8-bit data at an even address, waveform (c) or the first half of (e) is applied.
➃ When accessing 8-bit data at an odd address, waveform (d) or the first half of (f) is applied.
For instructions that are affected by the data length flag (m) and the index register length flag (x),
operation ➀ or ➁ is applied when flag m or x = “0”; operation ➂ or ➃ is applied when flag m or x
= “1.”
The setup of flags m and x and the selection of the external data bus width do not affect each other.
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CONNECTION WITH EXTERNAL DEVICES
3.1 Signals required for accessing external devices
● External data bus width = 16 bits (BYTE = “L”)
<16-bit data access>
(a) Access beginning at even address
E
ALE
A0 to A7
Address
A8/D8 to A15/D15
Address
Data(odd)
A16/D0 to A23/D7
Address
Data(even)
BLE
BHE
(b) Access beginning at odd address
E
ALE
A0 to A7
Address
A8/D8 to A15/D15
Address
A16/D0 to A23/D7
Address
Address
Data(odd)
Address
Address
Data(even)
BLE
BHE
<8-bit data access>
(c) Access to even address
(d) Access to odd address
E
E
ALE
ALE
A0 to A7
A0 to A7
Address
A8/D8 to A15/D15
Address
A16/D0 to A23/D7
Address
Data(even)
Address
A8/D8 to A15/D15
Address
A16/D0 to A23/D7
Address
BLE
BLE
BHE
BHE
Data(odd)
Fig. 3.1.2 Examples of operating waveforms of signals input from or output to the external (1)
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CONNECTION WITH EXTERNAL DEVICES
3.1 Signals required for accessing external devices
● External data bus width = 8 bits (BYTE = “H”)
<8/16-bit data access>
(e) Access beginning at even address
E
ALE
A0 to A7
Address
Address
A8 to A15
Address
Address
A16/D0 to A23/D7
Address
Data
Address
Data
BLE
BHE
8-bit data access
16-bit data access
(f) Access beginning at odd address
E
ALE
A0 to A7
Address
Address
A8 to A15
Address
Address
A16/D0 to A23/D7
Address
Data
Address
Data
BLE
BHE
8-bit data access
16-bit data access
Note: When accessing 16-bit data, 2 times of access are performed;
the low-order 8 bits are accessed first, and after that, the highorder 8 bits are accessed.
Fig. 3.1.3 Examples of operating waveforms of signals input from or output to the external (2)
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CONNECTION WITH EXTERNAL DEVICES
3.2 Software Wait
3.2 Software Wait
Software Wait provides a function to facilitate access to external devices that require long access time. To
select the software Wait, use the wait bit (bit 2 at address 5E16 ). Figure 3.2.1 shows the structure of
processor mode register 0 (address 5E 16). Figure 3.2.2 shows examples of bus timing when software Wait
is used.
Software Wait is valid only for the eternal area. The internal area is always accessed with no Wait.
b7
b6
0
b5
b4
b3
b2
b1
b0
0
Processor mode register 0 (Address 5E16)
Bit
Bit name
Functions
RW
0
Fix this bit to “0.”
0
RW
1
Nothing is assigned.
The value is “1” at reading.
1
–
2
Wait bit
0 : Software Wait is inserted when
accessing external area.
1 : No software Wait is inserted
when accessing external area.
0
RW
3
Software reset bit
The microcomputer is reset by
writing “1” to this bit. The value is
“0” at reading.
0
WO
4
Interrupt priority detection time
select bits
0
RW
0
RW
0
RW
0
RW
5
6
Fix this bit to “0.”
7
Stack bank select bit
b5 b4
0 0 : 7 cycles of
0 1 : 4 cycles of
1 0 : 2 cycles of
1 1 : Do not select.
0 : Bank 016
1 : Bank FF16
: Bits 0, 1, and 3 to 6 are not used for accessing external area.
Fig. 3.2.1 Structure of processor mode register 0
3–8
At reset
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CONNECTION WITH EXTERNAL DEVICES
3.2 Software Wait
<No Wait>
1 bus cycle
Clock
1
E
ALE
A0—A7
Address
Address
(Note)
A8/D8—A15/D15, A16/D0—A23/D7
Address
Data
Address
Data
●Internal areas are always accessed with this waveform.
<Wait>
1 bus cycle
Clock
1
E
ALE
A0—A7
Address
Address
(Note)
A8/D8—A15/D15, A16/D0—A23/D7
Address
Data
Address
Data
Note: When the external data bus is 8 bits wide (BYTE = “H”), A8/D8 to A15/D15 operate with the same bus timing as A0 to A7.
Fig. 3.2.2 Examples of bus timing when software Wait is used (BYTE = “L”)
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CONNECTION WITH EXTERNAL DEVICES
3.3 Ready function
3.3 Ready function
Ready function provides the function to facilitate access to external____
devices that require long access time.
The microcomputer
enters Ready state by input of “L” level to the RDY pin and retains this state while the
____
level of the RDY pin is at “L.” Table 3.3.1 lists the microcomputer’s state in Ready state.
In Ready state, the oscillator’s oscillation does not stop. Accordingly, the internal peripheral devices can
operate. Ready function is valid for the internal and external areas.
Table 3.3.1 Microcomputer’s state in Ready state
Item
Oscillation
State
Operating
Stopped at “L”
φ CPU, φ
_
__
Pins A0 to A7, A8/D8 to A15/D15, A16/D0 to A23/D7, E, R/W, Retain the state when Ready request was accepted.
____ ____
BHE, BLE, ST0, ST1, ALE
Pins P4 3 to P4 7, P5 to P10 (Note)
Outputs clock φ 1.
Pin φ 1
Watchdog timer
Operating
Note: This applies when this functions as a programmable I/O port.
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CONNECTION WITH EXTERNAL DEVICES
3.3 Ready function
3.3.1 Operation description
____
The input level of the RDY pin is judged at the falling edge of clock φ 1. When “L” level is detected at this
point, the microcomputer enters Ready
state. (This is called “Acceptance of Ready request.”)
____
In Ready state, the input level of the RDY pin is judged at every falling edge of clock φ 1. When “H” level
is detected at this point, the microcomputer terminates Ready state at the next rising edge of clock φ 1.
Figure 3.3.1 shows timing of acceptance of Ready request and termination of Ready state. Refer also to
section “16.1 Memory connection” for usage of Ready function.
<No Wait>
RDY pin input level ➀
sampling timing
Clock
➃
➁
➂
➃
1
➀ The “L” level which is input to the RDY pin is
accepted, so that E stops at “H ” level for 1 cycle of
clock 1 (indicated by
), and CPU stops
at “L” level.
CPU
➁ The “L” level which is input to the RDY pin is not
E
accepted, however CPU stops at “L” level.
➂ The “L” level which is input to th e RDY pin is
ALE
accepted, so that E stops at “L” level for 1 cycle of
clock 1 (indicated by
), and CPU stops
at “L” level.
RDY
Bus not in use
Bus in use
➃ Ready state is terminated.
➄ The “L” level which is input to the RDY pin is not
accepted because it is sampled immediately before
Wait by software Wait (indicated by
),
however CPU stops at “L” level.
<Wait>
RDY pin input level
sampling timing
Clock
➄
➂
➃
1
CPU
E
ALE
RDY
Bus in use
Fig. 3.3.1 Timing of acceptance of Ready request and termination of Ready state
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CONNECTION WITH EXTERNAL DEVICES
3.4 Hold function
3.4 Hold function
When composing the external circuit which accesses the bus without using the central processing unit
(CPU), Hold function is used to generate a timing for transferring the right to use the bus from the CPU to
the external circuit.
_____
The microcomputer
enters Hold state by input of “L” level to the HOLD pin and retains this state while the
_____
level of the HOLD pin is at “L.” Table 3.4.1 lists the microcomputer’s state in Hold state.
In Hold state, the oscillation of the oscillator does not stop. Accordingly, the internal peripheral devices can
operate. However, Watchdog timer stops operating.
Table 3.4.1 Microcomputer’s state in Hold state
Item
Oscillation
State
Operating
Operating
φ
Stopped at “L”
φ_CPU
Stopped at “H”
E
__
Pins
A 0 to A 7, A 8/D 8 to A 15/D 15, A 16/D 0 to A 23/D 7, R/W, Floating
___ ____
BHE, BLE
Output “L” level.
Pins ALE, ST1
Pin ST0
Outputs “H” level.
Pin φ 1
Outputs clock φ 1.
Pins P4 3 to P4 7, P5 to P10 (Note)
Retain the state when Hold request was accepted.
Watchdog timer
Stopped
Note: This applies when this functions as a programmable I/O port.
3.4.1 Operation _____
description
Judgment of the HOLD pin input level is performed at every falling edge of φ 1. When “L” level is detected
at judgment of the input level, bus request (Hold) becomes “1,” when “H” level is detected, bus request
(Hold) becomes “0.”
Bus request (Hold) is sampled within a period when the bus request sampling signal is “1” and bus request
is accepted when there is no bus request (DRAMC). (This is called “Acceptance of Hold request.”) For bus
request, refer to section “13.2.1 Bus access control circuit.”
When Hold request is accepted, φCPU stops at “L” level at the next rising edge of φ and the ST0 pin’s level
becomes “H,” the ST1 pin’s level becomes
“L.” When 1 cycle of φ has passed after the levels of the ST0
__ ____ ____
and ST1 pins are changed, the R/W, BHE, BLE pins and the external bus enter the floating state.
_____
In Hold state, when the HOLD pin’s input level becomes “H,” the ST0 and ST1 pins’ levels are changed
at the next rising edge of φ . When 1 cycle of φ has passed after the levels of the ST0 and ST1 pins are
changed, the microcomputer terminates Hold state.
Figures 3.4.1 to 3.4.3 show timing of acceptance of Hold request and termination of Hold state.
Note: φ has the same polarity and the same frequency as clock φ 1.
request, or executing the STP or WIT instruction. Accordingly,
However, φ stops by acceptance of Ready
_____
judgment of the input level of the HOLD pin is not performed during Ready state.
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CONNECTION WITH EXTERNAL DEVICES
3.4 Hold function
<When inputting “L” level to HOLD pin while bus is unused>
● State when inputting “L” level to HOLD pin
External data bus
Unused
Clock
1
Data length
External data bus width
8
8, 16
16
8, 16
(Note 1)
ALE
E
Floating
R/W
➀
External address bus /
External data bus
Floating
Address B
Address A
Floating
External address bus
BLE, BHE
HOLD
Bus request (Hold)
(Note 2)
Bus request sampling
(Note 2)
ST1
ST0
Hold state
Bus not in use
Transfer of right to use bus
Bus in use
Transfer of right to use bus
➀ This is the period in which the bus is not used, so that not a new
address but the address which was output immediately before is
output again.
Notes 1: Clock 1 has the same polarity and the same frequency as .
Timing of signals to be input from or output to the external is ordained on the basis
of clock 1.
2: Bus request (Hold) and bus request sampling are internal signals.
Fig. 3.4.1 Timing of acceptance of Hold request and termination of Hold state (1)
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CONNECTION WITH EXTERNAL DEVICES
3.4 Hold function
<When inputting “L” level to HOLD pin while bus is used; when data access is
completed with 1-bus cycle>
● State when inputting “L” level to HOLD pin
External data bus
Data length
External data bus width
8
8, 16
16
16 (Access beginning at even address)
Used
Clock
1
(Note 2)
ALE
E
Floating
R/W
Address A ➀
Address A
Floating
External address bus /
External data bus
Address B
Data
Floating
External address bus
BLE, BHE
HOLD
Bus request (Hold)
(Note 3)
Bus request sampling
(Note 3)
ST1
ST0
Hold state
Bus in
use
Bus in use
Transfer of
right to use bus
Transfer of
right to use bus
➀ When a Hold request is accepted, not a new address but the address
which was output immediately before is output again.
Notes 1: The above diagram shows the case of no Wait.
2: Clock 1 has the same polarity and the same frequency as .
Timing of signals to be input from or output to the external is
ordained on the basis of clock 1.
3: Bus request (Hold) and bus request sampling are internal signals.
Fig. 3.4.2 Timing of acceptance of Hold request and termination of Hold state (2)
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CONNECTION WITH EXTERNAL DEVICES
3.4 Hold function
<When inputting “L” level to HOLD pin while bus is used; when data access is
completed with continuous 2-bus cycle>
● State when inputting “L” level to HOLD pin
External data bus
Data length
Used
16
External data bus width
8
16 (Access beginning at odd address)
Clock
1
(Note 2)
ALE
E
Floating
R/W
Address A
External address bus /
External data bus
Address A + 1
Data
➀➀
Floating
Data
Address B
Floating
External address bus
BLE, BHE
HOLD
Bus request (Hold)
(Note 3)
Bus request sampling
(Note 3)
ST1
ST0
Hold state
Bus in use
Bus in use
Transfer of right
to use bus
Transfer of right
to use bus
➀ When a Hold request is accepted, not a new address but the address which was output
immediately before is output again.
Notes 1: The above diagram shows the case of 2- access in low-speed running.
2: Clock 1 has the same polarity and the same frequency as .
Timing of signals to be input from or output to the external is ordained on the basis
of clock 1.
3: Bus request (Hold) and bus request sampling are internal signals.
Fig. 3.4.3 Timing of acceptance of Hold request and termination of Hold state (3)
7721 Group User’s Manual
3–15
CONNECTION WITH EXTERNAL DEVICES
3.4 Hold function
[Precautions for Hold function]
When a DRAM refresh request occurs in Hold state, DRAM refresh is performed immediately because the
bus use priority level of DRAM refresh is higher than that of Hold function.
3–16
7721 Group User’s Manual
CHAPTER 4
RESET
4.1 Hardware reset
4.2 Software reset
RESET
4.1 Hardware reset
4.1 Hardware reset
When the power source voltage satisfies the microcomputer’s
recommended operating conditions, the
______
microcomputer is reset by supplying “L” level to the RESET pin. This is called a hardware reset. Figure 4.1.1
shows an example of hardware reset timing.
RESET
2 µs or more
4 to 5 cycles of
Internal processing
sequence after
reset
➁
➂
Program is executed.
➃
➀
Note: When the clock is stably supplied. (Refer to section “4.1.4 Time supplying “L” level to
RESET pin.”)
Fig. 4.1.1 Example of hardware reset timing
The following explains how the microcomputer operates in periods ➀ to ➃ above.
______
➀ After supplying “L” level to the RESET pin, the microcomputer initializes pins within a period of several
ten ns. (Refer
to “Table 4.1.1.”)
______
______
➁ While the RESET pin is “L” level and within a period of 4 to 5 cycles of φ after the RESET pin goes from
“L” to “H,” the microcomputer initializes the central processing unit (CPU) and SFR area. At this time,
the contents of the internal RAM area become undefined (except when Stop or Wait mode is terminated).
(Refer to “Figures 4.1.3 to 4.1.9.”)
➂ After ➁, the microcomputer performs “Internal processing sequence after reset.” (Refer to “Figure 4.1.10.”)
➃ The microcomputer executes a program beginning with the address set into the reset vector addresses
(FFFE16 and FFFF 16).
4–2
7721 Group User’s Manual
RESET
4.1 Hardware reset
4.1.1 Pin state
______
Table
4.1.1 lists the microcomputer’s pin state while RESET pin is at “L” level. Figure 4.1.2 shows the
________
RESETOUT output retaining timing.
______
Table 4.1.1 Pin state while RESET pin is at “L” level
Pin (Bus, Port) name
____ ____
A0/MA 0–A 7/MA7, A8/D8–A 15/D 15, A 16/D0–A 23/D7, BHE, BLE
__
Pin state
Outputs “H” or “L” level.
Outputs “H” level.
_
R/W, E, ST0, ST1
_________
ALE, RESET OUT
Outputs “L” level.
φ1
_____
____
HOLD, RDY, P43–P47, P5–P10
Outputs φ 1.
Floating.
When RESET pin input level goes from “L” to “H” in this period
1
RESET
3.5 cycles of
1
RESETOUT
________
Fig. 4.1.2 RESETOUT output retaining timing
7721 Group User’s Manual
4–3
RESET
4.1 Hardware reset
4.1.2 State of CPU, SFR area, and internal RAM area
Figure 4.1.3 shows the state of the CPU registers immediately after reset. Figures 4.1.4 to 4.1.9 show the
state of the SFR and internal RAM areas immediately after reset.
: Always “0” at reading.
0
0 : “0” immediately after reset.
1 : “1” immediately after reset.
? : Undefined immediately after reset.
Register name
State immediately after reset
b15
b8
Accumulator A (A)
b7
b0
?
?
b15
b8
Accumulator B (B)
b7
b0
?
?
b15
b8
Index register X (X)
b7
b0
?
?
b15
b8
Index register Y (Y)
b7
b0
?
?
b15
b8
Stack pointer (S)
b7
b0
?
?
b7
b0
Data bank register (DT)
0016
b7
b0
Program bank register (PG)
0016
b15
Program counter (PC)
b8
Contents at address FFFF16
b15
b0
0016
0
0
0
0
0
b8
b7
0
?
?
0
0
0
1
?
?
N
V
m
x
D
I
Z
C
0
0
IPL
Fig. 4.1.3 State of CPU registers immediately after reset
4–4
b7
0016
b15
Processor status register (PS)
b0
Contents at address FFFE16
b8
Direct page register (DPR)
b7
7721 Group User’s Manual
b0
RESET
4.1 Hardware reset
●SFR area (016 to 7F16, 1FC016 to 1FFF16)
Access characteristics
R W : It is possible to read the bit state at reading. The written value becomes valid.
RO : It is possible to read the bit state at reading. The written value becomes invalid.
WO : The written value becomes valid. It is impossible to read the bit state.
: Nothing is assigned. It is impossible to read the bit state. The written value becomes invalid.
State immediately after reset
0 : “0” immediately after reset.
1 : “1” immediately after reset.
? : Underfined immediately after
reset.
Address Register name
016
116
216
316
416
516
616
716
816
916
Port P4 register
A16
Port
P5 register
B16
C16 Port P4 direction register
D16 Port P5 direction register
Port P6 register
E16
Port P7 register
F16
1016 Port P6 direction register
1116 Port P7 direction register
1216
Port P8 register
Port P9 register
1316
1416 Port P8 direction register
1516 Port P9 direction register
Port P10 register
1616
1716
1816 Port P10 direction register
1916
1A16 Pulse output data register 0
1B16
1C16 Pulse output data register 1
1D16
1E16 A-D control register
1F16 A-D sweep pin select register
b7
0
: Always “0” at reading.
1
?
: Always “1” at reading.
: Always undefined at reading.
0
: “0” immediately after reset. Fix this bit to “0.”
Access characteristics
b0
State immediately after reset
b0
b7
?
?
?
?
?
?
?
?
?
?
?
RW
0
0
0
0
0
0
?
?
?
1
?
1
?
RW
RW
0
0
0
0
?
0
?
0
?
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
WO
WO
RW
RW
0 0
0016
?
?
0016
0016
?
?
0016
0016
?
?
0016
?
?
?
?
?
0 0
? ?
Fig. 4.1.4 State of SFR and internal RAM areas immediately after reset (1)
7721 Group User’s Manual
4–5
RESET
4.1 Hardware reset
Address
2016
2116
2216
2316
2416
2516
2616
2716
2816
2916
2A16
2B16
2C16
2D16
2E16
2F16
3016
3116
3216
3316
3416
3516
3616
3716
3816
3916
3A16
3B16
3C16
3D16
3E16
3F16
Register name
b7
Access characteristics
A-D register 0
RO
A-D register 1
RO
A-D register 2
RO
A-D register 3
RO
A-D register 4
RO
A-D register 5
RO
A-D register 6
RO
A-D register 7
RO
UART0 transmit/receive mode register
UART0 transmit buffer register
RO
UART0 transmit/receive control register 0
RO
?
0
?
0
?
0
RO
0
0
0
WO
RW
RW RO RW
?
0
?
0
?
0
RO
0
0
0
RW
WO
WO
UART1 transmit/receive mode register
UART1 baud rate register
UART1 transmit buffer register
RO
UART1 transmit/receive control register 0
UART1 receive buffer register
WO
RW
RW RO RW
RO
UART0 receive buffer register
UART1 transmit/receive control register 1
State immediately after reset
b7
RW
WO
WO
UART0 baud rate register
UART0 transmit/receive control register 1
b0
RO
RO
Fig. 4.1.5 State of SFR and internal RAM areas immediately after reset (2)
4–6
7721 Group User’s Manual
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
0016
?
?
?
? 1
0 0
?
0 0
0016
?
?
?
? 1
0 0
?
0 0
b0
0
0
0
1
0
0
0
0
?
0
0
0
1
0
0
0
0
?
RESET
4.1 Hardware reset
Address
b0
b7
Count start register
4016
4116
4216 One-shot start register
4316
Up-down register
4416
4516
4616
Timer A0 register
4716
4816
Timer A1 register
4916
4A16
Timer A2 register
4B16
4C16
Timer A3 register
4D16
4E16
Timer A4 register
4F16
5016
Timer B0 register
5116
5216
Timer B1 register
5316
5416
Timer B2 register
5516
5616 Timer A0 mode register
5716 Timer A1 mode register
5816 Timer A2 mode register
5916 Timer A3 mode register
5A16 Timer A4 mode register
5B16 Timer B0 mode register
5C16 Timer B1 mode register
5D16 Timer B2 mode register
5E16 Processor mode register 0
5F16 Processor mode register 1
State immediately after reset
Access characteristics
Register name
b0
b7
0016
?
0 0
?
0 0
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
0 0
0 0
0016
0016
0016
? 0
? 0
? 0
0 0
RW
?
WO
WO
RW
RW
RW
RW
RW
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
(Note 3)
(Note 3)
(Note 3)
RW
RW
RW
RW
WO RW
RW
RW
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
?
?
?
0
?
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
?
(Note 4)
Notes 1: The access characteristics at addresses 4A16 to 4F16 vary according to Timer A’s operating
mode. (Refer to “CHAPTER 8. TIMER A.”)
2: The access characteristics at addresses 5016 to 5316 vary according to Timer B’s operating
mode. (Refer to “CHAPTER 9. TIMER B.”)
3: The access characteristics for bit 5 at addresses 5B16 and 5C16 vary according to Timer B’s
operating mode. Bit 5 at address 5D16 is invalid. (Refer to “CHAPTER 9. TIMER B.”)
4: Bit 1 at address 5F16 becomes “0” immediately after reset. For the M37721S1BFP, fix this bit to
“0.”
Fig. 4.1.6 State of SFR and internal RAM areas immediately after reset (3)
7721 Group User’s Manual
4–7
RESET
4.1 Hardware reset
Address
Register name
Watchdog timer register
6016
Watchdog
timer frequency select register
6116
6216
Real-time output control register
6316
DRAM control register
6416
6516
Refresh timer
6616
6716
DM AC control register L
6816
DM
AC control register H
6916
6A16
6B16
DM A0 interrupt control register
6C16
DM A1 interrupt control register
6D16
DM A2 interrupt control register
6E16
DM A3 interrupt control register
6F16
7016 A-D conversion interrupt control register
7116 UART0 transmit interrupt control register
7216 UART0 receive interrupt control register
7316 UART1 transmit interrupt control register
7416 UART1 receive interrupt control register
Timer A0 interrupt control register
7516
Timer A1 interrupt control register
7616
Timer A2 interrupt control register
7716
Timer A3 interrupt control register
7816
Timer A4 interrupt control register
7916
Timer B0 interrupt control register
7A16
Timer B1 interrupt control register
7B16
Timer B2 interrupt control register
7C16
INT0 interrupt control register
7D16
INT1 interrupt control register
7E16
INT2 interrupt control register
7F16
b7
Access characteristics
b0
State immediately after reset
b7
(Note 5)
RW
RW
RW
RW
0 0
RW
0 0
0
0
WO
RW
(Note 7)
RW
WO
0
0
0
0
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
0
0
?
?
?
0
0
0
?(Note 6)
?
0 0
?
0 0
?
?
?
0 ?
0 0
?
?
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 0
0 0
0 0
b0
0
0
0
0
0
0
0
?
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Notes 5: By writing dummy data to address 6016, the value “FFF16” is set to the watchdog timer.
The dummy data is not retained anywhere.
6: The value “FFF16” is set to the watchdog timer. (Refer to “CHAPTER 15. WATCHDOG TIMER.”)
7: It is possible to read the bit state at reading. When writing “0” to this bit, this bit becomes “0.”
But when writing “1” to this bit, this bit does not change.
Fig. 4.1.7 State of SFR and internal RAM areas immediately after reset (4)
4–8
7721 Group User’s Manual
RESET
4.1 Hardware reset
Address
1FC016
1FC116
1FC216
1FC316
1FC416
1FC516
1FC616
1FC716
1FC816
1FC916
1FCA16
1FCB16
1FCC16
1FCD16
1FCE16
1FCF16
1FD016
1FD116
1FD216
1FD316
1FD416
1FD516
1FD616
1FD716
1FD816
1FD916
1FDA16
1FDB16
1FDC16
1FDD16
1FDE16
1FDF16
Register name
Source address register 0
b7
Access characteristics
RW
RW
RW
Transfer counter register 0
RW
RW
RW
DMA0 mode register H
RW
Source address register 1
RW
RW
RW
Destination address register 1
RW
RW
RW
Transfer counter register 1
RW
RW
RW
DMA1 mode register H
DMA1 control register
b0
?
?
?
?
?
?
?
?
?
?
?
?
RW
RW
DMA0 control register
DMA1 mode register L
State immediately after reset
b7
RW
RW
RW
Destination address register 0
DMA0 mode register L
b0
0
0
?
0
0
?
0
0
0
0
0
0
AA
AA
AAAA
AA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
?
?
?
?
?
?
?
?
?
?
?
?
?
RW
RW
RW
0
0
?
0
0
?
0
0
0
0
0
0
AA
AA
AAAA
AA
0
0
0
0
0
0
?
Fig. 4.1.8 State of SFR and internal RAM areas immediately after reset (5)
7721 Group User’s Manual
4–9
RESET
4.1 Hardware reset
Address
1FE016
1FE116
1FE216
1FE316
1FE416
1FE516
1FE616
1FE716
1FE816
1FE916
1FEA16
1FEB16
1FEC16
1FED16
1FEE16
1FEF16
1FF016
1FF116
1FF216
1FF316
1FF416
1FF516
1FF616
1FF716
1FF816
1FF916
1FFA16
1FFB16
1FFC16
1FFD16
1FFE16
1FFF16
Register name
b7
Access characteristics
b0
State immediately after reset
b7
RW
RW
RW
Source address register 2
RW
RW
RW
Destination address register 2
RW
RW
RW
Transfer counter register 2
RW
RW
DMA2 mode register L
DMA2 mode register H
RW
DMA2 control register
Source address register 3
RW
RW
RW
Destination address register 3
RW
RW
RW
Transfer counter register 3
RW
RW
RW
DMA3 mode register H
RW
DMA3 control register
0
0
?
0
0
?
0
0
0
AAA
AAA
AAAAA
AA
0
0
0
0
0
0
0
0
0
0
0
?
0
0
?
0
0
0
AAA
AAA
AAAAA
AA
0
0
0
0
0
0
0
0
0
?
✽
●Internal RAM area (addresses 8016 to 27F16)
•At hardware reset
(Except the case where Stop or Wait mode is terminated)............................................... Undefined.
•At software reset.............................................................. Retains the state immediately before reset
•At termination of Stop or Wait mode
(Hardware reset is used to terminate it.)............... Retains the state immediately before the STP or
WIT instruction is executed
✽ For the M37721S2BFP, the internal RAM area can be assigned to addresses 8016 to 47F16 by
setting the internal RAM area select bit (bit 1 at address 5F16). (Refer to section “2.4 Memory
assignment.”)
Fig. 4.1.9 State of SFR and internal RAM areas immediately after reset (6)
4–10
0
0
0
0
0
0
0
0
0
0
0
0
?
?
?
?
?
?
?
?
?
?
?
?
?
RW
RW
DMA3 mode register L
b0
?
?
?
?
?
?
?
?
?
?
?
?
7721 Group User’s Manual
RESET
4.1 Hardware reset
4.1.3 Internal processing sequence after reset
Figure 4.1.10 shows the internal processing sequence after reset.
●External bus width = 16 bits (BYTE = “L”)
CPU
A0–A7
ADL
FE16
0016
A8/D8–A15/D15
0016
0016
FF16
A16/D0–A23/D7
0016
0016
0016
(ADH)
(ADL)
ADH
0016
(Next op-code or
operand)
(Next op-code)
E
“H”
R/W
ALE
●External bus width = 8 bits (BYTE = “H”)
CPU
A0–A7
0016
FE16
FF16
ADL
A8–A15
0016
FF16
FF16
ADH
A16/D0–A23/D7
0016
0016
0016
(ADL)
0016
( ADH)
0016
(Next op-code)
E
“H”
R/W
ALE
Fig. 4.1.10 Internal processing sequence after reset
7721 Group User’s Manual
4–11
RESET
4.1 Hardware reset
______
4.1.4 Time supplying “L” level______
to RESET pin
Time supplying “L” level to the RESET pin varies according to the state of the clock oscillation circuit.
●When the oscillator is stably oscillating or a stable clock is input from the X IN pin, supply “L” level for
2 µ s or more.
●When the oscillator is not stably oscillating (including the case at power-on reset or in Stop mode), supply
“L” level until the oscillation is stabilized.
The time required for stabilizing oscillation varies according to the oscillator. For details, contact the
oscillator manufacturer.
Figure 4.1.11 shows the power-on reset conditions. Figure 4.1.12 shows an example of a power-on reset
circuit.
✽ For details about Stop mode, refer to section “5.3 Stop mode.” For details about clocks, refer to
“CHAPTER 5. CLOCK GENERATING CIRCUIT.”
Powered on here
4.5V
Vcc
0V
RESET
0.9V
0V
Fig. 4.1.11 Power-on reset conditions
5V
M37721
1 M51957AL
Vcc
Vcc
27 k
2
10 k
IN
OUT
5
Delay 4
capacity
GND
3
RESET
47
Vss
Cd
SW
GND
✽ The delay time is about 11 ms when Cd = 0.033 µF.
td ≈ 0.34 ✕ Cd [ µs], Cd: [ pF ]
Fig. 4.1.12 Example of power-on reset circuit
4–12
7721 Group User’s Manual
RESET
4.2 Software reset
4.2 Software reset
When the power source voltage satisfies the microcomputer’s recommended operating conditions, the
microcomputer is reset by writing “1” to the software reset bit (bit 3 at address 5E 16). (This is called “
Software reset.”) In this case, the microcomputer initializes pins, CPU, and SFR area just as in the case of
a hardware reset. However, the microcomputer retains the contents of the internal RAM area. (Refer to
“Table 4.1.1” and “Figures 4.1.3 to 4.1.9.”) Figure 4.2.1 shows the structure of the processor mode
register 0 (address 5E16).
After completing initialization, the microcomputer performs “internal processing sequence after reset.” (Refer
to “Figure 4.1.10.”) After that, it executes a program beginning from the address set into the reset vector
addresses (FFFE16 and FFFF 16) .
b7
b6
0
b5
b4
b3
b2
b1
b0
0
Processor mode register 0 (Address 5E16)
Bit
Functions
Bit name
At reset
RW
RW
0
Fix this bit to “0”
0
1
Nothing is assigned.
This bit is “1” at reading.
1
2
Wait bit
0 : Software Wait is inserted when
accessing external area.
1 : No software Wait is inserted
i accessing external area.
when
0
RW
3
Software reset bit
The microcomputer is reset by
writing “1” to this bit.
The value of this bit is “0” at
reading.
0
WO
4
Interrupt priority detection
time select bits
0
RW
0
RW
0
RW
0
RW
5
6
Fix this bit to “ 0”
7
Stack bank select bit
b5 b4
0 0 : 7 cycles of
0 1 : 4 cycles of
1 0 : 2 cycles of
1 1 : Do not select.
0 : Bank 016
1 : Bank FF16
: Bits 0 to 2 and bits 4 to 7 are not used for software reset.
Fig. 4.2.1 Structure of processor mode register 0
7721 Group User’s Manual
4–13
RESET
4.2 Software reset
________
When the software reset bit is set to “1,” the RESETOUT pin’s output
level becomes “L.” In a period of 4.5
________
cycles of clock φ 1________
after the software reset bit is set to “1,” the RESET OUT pin’s output level is “L.” Figure
4.2.2 shows the RESET OUT output timing at software reset.
Set software reset bit to “1”
1
E
RESETOUT
________
Fig. 4.2.2 RESET OUT output timing
4–14
7721 Group User’s Manual
CHAPTER 5
CLOCK GENERATING
CIRCUIT
5.1 Oscillation circuit examples
5.2 Clocks
5.3 Stop mode
[Precautions for Stop mode]
5.4 Wait mode
[Precautions for Wait mode]
CLOCK GENERATING CIRCUIT
5.1 Oscillation circuit examples
5.1 Oscillation circuit examples
To the oscillation circuit, a ceramic resonator or a quartz-crystal oscillator can be connected, or the clock
which is externally generated can be input. Oscillation circuit examples are shown below.
5.1.1 Connection example using resonator/oscillator
Figure 5.1.1 shows an example when connecting a ceramic resonator/quartz-crystal oscillator between pins
X IN and X OUT.
The circuit constants such as Rf, R d , CIN, and COUT (shown in “Figure 5.1.1”) depend on the resonator/
oscillator. These values shall be set to the values
recommended by the resonator/oscillator
manufacturer.
5.1.2 Externally generated clock input example
Figure 5.1.2 shows an input example of the clock
which is externally generated. The external clock
must be input from the X IN pin, and the X OUT pin
must be left open.
M37721
XIN
XOUT
Rf
Rd
CIN
COUT
Fig. 5.1.1 Connection example using resonator/oscillator
M37721
XIN
XOUT
Open
Externally generated clock
Vcc
Vss
Fig. 5.1.2 Externally generated clock input example
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7721 Group User’s Manual
CLOCK GENERATING CIRCUIT
5.2 Clocks
5.2 Clocks
Figure 5.2.1 shows the clock generating circuit block diagram.
f2
XIN
XOUT
f16
1
f64
Interrupt request
S
Q
1/2
1/8
1/2
1/2
1/8
f512
f512 “0”
STP instruction
R
Operation clock for
internal peripheral devices
Watchdog timer
frequency select bit
f32
“1”
S
WIT instruction
Watchdog
timer
Q
R
(Note)
Ready request
Reset
S
R
Q
CPU
CPU wait request
from BIU
Bus request
DRAMC
Hold
DMAC
CPU : Central Processing Unit
BIU : Bus Interface Unit
Watchdog timer frequency select bit : Bit 0 at address 6116
Note: This signal is generated when the watchdog timer’s most significant bit becomes “0.”
Fig. 5.2.1 Clock generating circuit block diagram
7721 Group User’s Manual
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CLOCK GENERATING CIRCUIT
5.2 Clocks
5.2.1 Clocks generated in clock generating circuit
(1) φ
It is the operation clock of BIU. It is also the clock source of φ CPU.
φ stops by acceptance of Ready request or execution of the STP or WIT instruction. It is not stopped
by acceptance of bus request.
(2) φCPU
It is the operation clock of CPU. φ CPU stops by the following:
•Execution of the STP or WIT instruction,
____
•Acceptance of Ready request; “L” level input to the RDY pin
•CPU wait request from BIU; Acceptance of bus request is included.
(3) Clock φ 1
It has the same period as φ and is output to the external from the φ 1 pin. Clock φ1 stops by execution
of the STP instruction.
It is not stopped by acceptance of Ready or bus request, or execution of the WIT instruction.
(4) f 2 to f 512
Each of them is the internal peripheral devices’ operation clock.
Note: Refer to each functional description for details:
•Execution of STP instruction ............. “5.3 Stop mode”
•Execution of WIT instruction .............. “5.4 Wait mode”
•Ready ..................................................... “3.3 Ready function”
•Bus request ........................................... “13.2.1 Bus access control circuit”
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CLOCK GENERATING CIRCUIT
5.3 Stop mode
5.3 Stop mode
Stop mode is used to stop oscillation when there is no need to operate the central processing unit (CPU).
The microcomputer enters Stop mode when the STP instruction is executed.
Stop mode can be terminated by an interrupt request occurrence or the hardware reset.
5.3.1 Stop mode
When the STP instruction is executed, the oscillator stops oscillating. This state is called “Stop mode.”
In Stop mode, the contents of the internal RAM can be retained intact when Vcc (power source voltage)
is 2 V or more. Additionally, the microcomputer’s power consumption is lowered. It is because the CPU and
all internal peripheral devices using clocks f 2 to f 512 stop the operation.
Table 5.3.1 lists the microcomputer’s state and operation in and after Stop mode.
Table 5.3.1 Microcomputer’s state and operation in and after Stop mode
Item
State in
State and Operation
Oscillation
Stopped
φ CPU, φ
Clock φ 1 , f 2 to f 512
Can operate only in event counter mode
Timers A, B
Can operate only when an external clock is selected
Serial I/O
A-D converter
Stopped
DMA controller
Stopped (Note)
DRAM controller
Stopped
Watchdog timer
Retains the same state in which the STP instruction was executed
Pins
Operation
By interrupt request
Supply of φ CPU and φ starts after a certain time measured by
after terminating occurrence
Watchdog timer has passed.
Stop mode
By hardware reset
Operates in the same way as hardware reset
Note: DRAM refresh is not performed because the refresh timer also stops.
Internal peripheral
devices
Stop mode
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CLOCK GENERATING CIRCUIT
5.3 Stop mode
(1) Termination by interrupt request occurrence
When terminating Stop mode by interrupt request occurrence, instructions are executed after a
certain time measured by the watchdog timer has passed.
➀ When an interrupt request occurs, the oscillator starts oscillating. Simultaneously, supply of clock
φ 1, f 2 to f 512 starts.
➁ The watchdog timer starts counting owing to the oscillation start. The watchdog timer counts f32
regardless of the watchdog timer frequency select bit’s (bit 0 at address 61 16) contents.
➂ When the watchdog timer’s MSB becomes “0,” supply of φ CPU and φ starts. At the same time, the
watchdog timer’s count source returns to f32 or f512 that is selected by the watchdog timer frequency
select bit.
➃ The interrupt request which occurred in ➀ is accepted.
Table 5.3.2 lists the interrupts used to terminate Stop mode.
Table 5.3.2 Interrupts used to terminate Stop mode
Interrupt
Conditions for using each function to generate interrupt request
____
INT i interrupt (i = 0 to 2)
Timer Ai interrupt (i = 2 to 4)
In event counter mode
Timer Bi interrupt (i = 0, 1)
UARTi transmit interrupt (i = 0, 1)
When external clock is selected
UARTi receive interrupt (i = 0, 1)
Notes 1: Since the oscillator has stopped oscillating, interrupts not listed above cannot be used. Also, even
the interrupts listed above cannot be used when the above conditions are not satisfied. The
A-D converter does not operate, also.
2: When multiple interrupts listed above are enabled, Stop mode is terminated by the interrupt
request which occurs first.
3: Refer to “CHAPTER 7. INTERRUPTS” and the description of each internal peripheral device for
details about each interrupt.
Before executing the STP instruction, interrupts used to terminate Stop mode must be enabled.
In addition, the interrupt priority level of the interrupt used to terminate Stop mode must be higher
than the processor interrupt priority level (IPL) of the routine where the STP instruction is executed.
When multiple interrupts in Table 5.3.2 are enabled, Stop mode is terminated by the first interrupt
request.
There is a possibility that any of all interrupt requests occurs after the oscillation starts in ➀ and until
supply of φCPU and φ starts in ➂. The interrupt requests which occur during this period are accepted
in order of priority after the watchdog timer’s MSB becomes “0.”
For interrupts not to be accepted, set their interrupt priority levels to level 0 (interrupt disabled)
before executing the STP instruction.
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CLOCK GENERATING CIRCUIT
5.3 Stop mode
Stop mode
f(XIN)
1
CPU ,
Interrupt request
used to terminate
Stop mode
(Interrupt request bit)
f32 ✕ 2048 counts
“FFF16”
Value of Watchdog timer
“7FF16”
CPU
Operating
Stopped
Stopped
Operating
Internal peripheral devices
Operating
Stopped
Operating
Operating
●STP instruction
is executed
●Interrupt request used to
terminate Stop mode
occurs.
●Oscillation starts.(When
an external clock is input
from the XIN pin, clock
input starts.)
●Watchdog timer starts
counting.
●Watchdog timer’s MSB = “0”
(However, watchdog timer interrupt
request does not occur.)
●Supply of CPU, starts.
●Interrupt request which has been used
to terminate Stop mode is accepted.
Fig. 5.3.1 Stop mode terminating sequence by interrupt request occurrence
(2) Termination by hardware
reset
______
Supply “L” level to the RESET pin by using the external circuit until the oscillation of the oscillator
is stabilized.
The CPU and the SFR area are initialized in the same way as system reset. However, the internal
RAM area retains the same contents as that before executing the STP instruction. The terminating
sequence is the same as the internal processing sequence which is performed after reset.
Refer to “CHAPTER 4. RESET” for details about reset.
7721 Group User’s Manual
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CLOCK GENERATING CIRCUIT
5.3 Stop mode
[Precautions for Stop mode]
When executing the STP instruction after writing to an internal area or an external area, three NOP instructions
must be inserted to complete the write operation before the STP instruction is executed. (Refer to “Figure
5.3.2.”)
STA A, ✕✕✕✕ ; Write instruction
NOP
; NOP instruction inserted
NOP
;
NOP
;
STP
; STP instruction
Fig. 5.3.2 NOP instruction insertion example
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CLOCK GENERATING CIRCUIT
5.4 Wait mode
5.4 Wait mode
Wait mode is used to stop φ CPU and φ when there is no need to operate the central processing unit (CPU).
The microcomputer enters Wait mode when the WIT instruction is executed.
Wait mode can be terminated by an interrupt request occurrence or the hardware reset.
5.4.1 Wait mode
When the WIT instruction is executed, φCPU and φ stop. The oscillator’s oscillation is not stopped. This state
is called “Wait mode.”
In Wait mode, the microcomputer’s power consumption is lowered though Vcc (power source voltage) is
maintained.
Table 5.4.1 lists the microcomputer’s state and operation in and after Wait mode.
Internal peripheral devices
Table 5.4.1 Microcomputer’s state and operation in and after Wait mode
Item
State and Operation
State in
Operating
Oscillation
Stopped
Wait mode φ CPU, φ
Operating
Clock φ 1 , f 2 to f 512
Timer A
Timer B
Serial I/O
Operating
A-D converter
Stopped
Stopped (Note)
DRAM controller
Operating
Watchdog timer
Retains the same state in which the WIT instruction was executed
Pins
Operation after By interrupt request occurrence Supply of φ CPU and φ starts just after the termination.
terminating
Operates in the same way as hardware reset.
By hardware reset
Wait mode
DMA controller
Note: The refresh timer operates, but DRAM refresh is not performed because the bus request (DRAMC)
does not occur. (Refer to section “Appendix 9. 7721 Group Q & A.”)
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CLOCK GENERATING CIRCUIT
5.4 Wait mode
(1) Termination by interrupt request occurrence
➀ When an interrupt request occurs, supply of φ CPU and φ starts.
➁ The interrupt request which occurred in ➀ is accepted.
The following interrupts are used to terminate Wait mode.
When a watchdog timer interrupt request occurs, Wait mode is also terminated.
___
•INTi interrupt (i = 0 to 2)
•Timer Ai interrupt (i = 0 to 4)
•Timer Bi interrupt (i = 0 to 2)
•UARTi transmit interrupt (i = 0, 1)
•UARTi receive interrupt (i = 0, 1)
•A-D converter interrupt
Note: Refer to “CHAPTER 7. INTERRUPTS” and each functional description about interrupts.
Before executing the WIT instruction, interrupts used to terminate Wait mode must be enabled.
In addition, the interrupt priority level of the interrupt used to terminate Wait mode must be higher
than the processor interrupt priority level (IPL) of the routine where the WIT instruction is executed.
When multiple interrupts listed above are enabled, Wait mode is terminated by the interrupt request
which occurs first.
(2) Termination by hardware reset
The CPU and the SFR area are initialized in the same way as system reset. However, the internal
RAM area retains the same contents as that before executing the WIT instruction. The terminating
sequence is the same as the internal processing sequence which is performed after reset.
Refer to “CHAPTER 4. RESET” for details about reset.
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CLOCK GENERATING CIRCUIT
5.4 Wait mode
[Precautions for Wait mode]
When executing the WIT instruction after writing to an internal area or an external area, three NOP instructions
must be inserted to complete the write operation before the WIT instruction is executed. (Refer to “Figure
5.4.1.”)
STA A, ✕✕✕✕ ; Write instruction
NOP
; NOP instruction inserted
NOP
;
NOP
;
WIT
; WIT instruction
Fig. 5.4.1 NOP instruction insertion example
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CLOCK GENERATING CIRCUIT
5.4 Wait mode
MEMORANDUM
5–12
7721 Group User’s Manual
CHAPTER 6
INPUT/OUTPUT
PINS
6.1 Overview
6.2 Programmable I/O ports
6.3 Examples of handling unused pins
INPUT/OUTPUT PINS
6.1 Overview, 6.2 Programmable I/O ports
6.1 Overview
Input/output pins (hereafter called I/O pins) have functions as programmable I/O ports, internal peripheral
devices’s I/O pins, external buses, etc.
For the basic functions of each I/O pin, refer to section “1.3 Pin description.” For the I/O functions of the
internal peripheral devices, refer to relevant sections of each internal peripheral device. For the external
address bus, external data bus, bus control signals, etc., refer to “CHAPTER 3. CONNECTION WITH
EXTERNAL DEVICES.”
This chapter describes the programmable I/O ports and examples of handling unused pins.
6.2 Programmable I/O ports
The programmable I/O ports have direction registers and port registers in the SFR area. Figure 6.2.1 shows
the memory map of direction registers and port registers.
Addresses
A16
Port P4 register
B16
Port P5 register
C16
Port P4 direction register
D16
Port P5 direction register
E16
Port P6 register
F16
Port P7 register
1016
Port P6 direction register
1116
Port P7 direction register
1216
Port P8 register
1316
Port P9 register
1416
Port P8 direction register
1516
Port P9 direction register
1616
Port P10 register
1716
1816
Port P10 direction register
Fig. 6.2.1 Memory map of direction registers and port registers
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7721 Group User’s Manual
INPUT/OUTPUT PINS
6.2 Programmable I/O ports
6.2.1 Direction register
This register determines the I/O direction of programmable I/O ports. Each bit of this register corresponds
one for one to each pin of the microcomputer.
Figure 6.2.2 shows the structure of port Pi (i = 4 to 10) direction register.
b7
b6
b5
b4
b3
b2
b1
b0
Port Pi direction register (i = 4 to 10)
(Addresses C16, D16, 1016, 1116, 1416, 1516, 1816)
Bit
Bit name
Functions
At reset
RW
0
RW
0
RW
0
RW
0
Port Pi0 direction bit
1
Port Pi1 direction bit
2
Port Pi2 direction bit
3
Port Pi3 direction bit
0
RW
4
Port Pi4 direction bit
0
RW
5
Port Pi5 direction bit
0
RW
6
Port Pi6 direction bit
0
RW
7
Port Pi7 direction bit
0
RW
0 : Input mode
(The port functions as an input port)
1 : Output mode
(The port functions as an output port)
Note: For bits 0 to 2 of the port P4 direction register, nothing is assigned and these bits are fixed to “0” at
reading.
Fig. 6.2.2 Structure of port Pi (i = 4 to 10) direction register
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INPUT/OUTPUT PINS
6.2 Programmable I/O ports
6.2.2 Port register
Data is input from or output to the external by writing/reading data to/from a port register. A port register
consists of a port latch which holds the output data and a circuit which reads the pin state. Each bit of the
port register corresponds one for one to each pin of the microcomputer. Figure 6.2.3 shows the structure
of the port Pi (i = 4 to 10) register.
● When outputting data from programmable I/O port set to output mode
➀ By writing data to the corresponding bit of the port register, the data is written into the port latch.
➁ The data is output from the pin according to the contents of the port latch.
By reading the port register of a port set to the output mode, the contents of the port latch is read
out, instead of the pin state. Accordingly, the output data is correctly read without being affected by
an external load, etc. (Refer to “Figures 6.2.4 and 6.2.5.”)
● When inputting data from programmable I/O port set to input mode
➀ A pin which is set to the input mode enters the floating state.
➁ By reading the corresponding bit of the port register, the data which is input from the pin can be
read out.
By writing data to the port register of a programmable I/O port set to the input mode, the data is written
only into the port latch and is not output to the external (Note). The pin remains floating.
Note: When executing a read-modify-write instruction (CLB, SEB, INC, DEC, ASL, ASR, LSR, ROL,
ROR) to the port register of a programmable I/O port set to the input mode, the instruction is
executed to the data which is input from the pin and the result is written into the port register.
b7
b6
b5
b4
b3
b2
b1
b0
Port Pi register (i = 4 to 10)
(Addresses A16, B16, E16, F16, 1216, 1316, 1616)
Bit
Bit name
Functions
At reset
RW
Data is input from or output to a pin
by reading from or writing to the
corresponding bit.
Undefined
RW
Undefined
RW
Undefined
RW
Undefined
RW
0
Port Pi0’s pin
1
Port Pi1’s pin
2
Port Pi2’s pin
3
Port Pi3’s pin
4
Port Pi4’s pin
Undefined
RW
5
Port Pi5’s pin
Undefined
RW
6
Port Pi6’s pin
Undefined
RW
7
Port Pi7’s pin
Undefined
RW
0 : “L” level
1 : “H” level
Note: For bits 0 to 2 of the port P4 register, nothing is assigned and these bits are fixed to “0” at reading.
Fig. 6.2.3 Structure of port Pi (i = 4 to 10) register
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INPUT/OUTPUT PINS
6.2 Programmable I/O ports
Figures 6.2.4 and 6.2.5 show the port peripheral circuits.
[Inside dotted-line not included]
Ports P43 to P46
Direction register
Data bus
[Inside dotted-line included]
Ports P47, P51/TA2 IN, P53/TA3IN,
P55/TA4IN, P56/TB0IN, P57/TB1IN,
P82/RxD0, P86/RxD1,
P91/DMAREQ0, P93/DMAREQ1,
P95/DMAREQ2, P97/DMAREQ3,
P100/INT0, P101/INT1, P102/INT2,
(There is no hysteresis for P82/RxD0 and P86/RxD1.)
Port latch
[Inside dotted-line not included]
Ports P83/TxD0, P87/TxD1,
P90/DMAACK0, P92/DMAACK1,
P94/DMAACK2, P96/DMAACK3,
P104/CAS, P105/RAS,
P106/MA8, P107/MA9
Direction register
“1”
Output
Data bus
AA
A
(internal peripheral device)
Port latch
[Inside dotted-line included]
Ports P50/TA2OUT, P52/TA3OUT, P54/TA4OUT
Ports P60/RTP00 to P67/RTP13
Direction register
Data bus
Port latch
Latch
Timer underflow signal
T
Q
CK
Fig. 6.2.4 Port peripheral circuits (1)
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6–5
INPUT/OUTPUT PINS
6.2 Programmable I/O ports
[Inside dotted-line not included]
Ports P70/AN0 to P76/AN6
Direction register
[Inside dotted-line included]
Port P77/AN7/ADTRG
Data bus
Port latch
Analog input
Ports P80/CTS0/RTS0, P81/CLK0,
P84/CTS1/RTS1, P85/CLK1
“0”
“1”
Direction register
Output
Data bus
Port P103/TC
Port latch
Direction register
“0”
Data bus
Port latch
E output pin
Fig. 6.2.5 Port peripheral circuits (2)
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7721 Group User’s Manual
AA
(internal peripheral device)
Output
(TC)
AA
AA
INPUT/OUTPUT PINS
6.3 Examples of handling unused pins
6.3 Examples of handling unused pins
When unusing an I/O pin, some handling is necessary for the pin. Examples of handling unused pins are
described below.
The following are just examples. The user shall modify them according to the user’s actual application and
test them.
Table 6.3.1 Examples of handling unused pins
Pin name
P4 3 to P4 7, P5 to P10
___
Handling example
Set these pins to the input mode and connect each
pin to Vcc or Vss via a resistor; or set these pins to
the output mode and leave them open (Notes 1 and 2).
___
BLE, BHE, ALE, φ 1, ST0, ST1
XOUT (Note 3)
Leave them open.
HOLD, RDY
CNVss
Connect these pins to Vcc via a resistor (pull-up) (Note 2).
Connect this pin to Vcc or Vss.
AVcc
Connect this pin to Vcc.
AVss, V REF
Connect these pins to Vss.
_____
____
Notes 1: When leaving these pins open after they are set to the output mode, note the following: these pins
function as input ports from reset until they are switched to the output mode by software. Therefore,
voltage levels of these pins are undefined and the power source current may increase while these
pins function as input ports. After reset, immediately set these ports to the output mode.
Software reliability can be enhanced by setting the contents of the above ports’ direction registers
periodically. This is because these contents may be changed by noise, a program runaway which
occurs owing to noise, etc.
2: For unused pins, use the shortest possible wiring (within 20 mm from the microcomputer’s pins).
3: This applies when a clock externally generated is input to the XIN pin.
● When setting ports to input mode
● When setting ports to output mode
P43–P47, P5–P10
P43–P47, P5–P10
Left open
ST0
ST1
BLE
BHE
ALE
ST0
ST1
BLE
BHE
ALE
Left open
Left open
XOUT
M37721
M37721
1
Left open
VCC
1
XOUT
HOLD
RDY
HOLD
RDY
AVCC
AVCC
CNVSS✽
AVSS
VREF
CNVSS✽
AVSS
VREF
VSS
Left open
VCC
VSS
✽ CNVSS can be connected to V CC, too.
Fig. 6.3.1 Examples of handling unused pins
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INPUT/OUTPUT PINS
6.3 Examples of handling unused pins
MEMORANDUM
6–8
7721 Group User’s Manual
CHAPTER 7
INTERRUPTS
7.1
7.2
7.3
7.4
7.5
7.6
7.7
Overview
Interrupt sources
Interrupt control
Interrupt priority level
Interrupt priority level detection circuit
Interrupt priority level detection time
Sequence from acceptance of interrupt
request until execution of interrupt routine
7.8 Return from interrupt routine
7.9 Multiple interrupts ____
7.10 External interrupts (INTi interrupt)
7.11 Precautions for interrupts
INTERRUPTS
7.1 Overview
7.1 Overview
The M37721 provides 23 interrupt sources to generate interrupt requests.
Figure 7.1.1 shows the interrupt processing sequence.
When an interrupt request is accepted, a branch is made to the start address of the interrupt routine set
in the interrupt vector table (addresses FFCE16 to FFFF 16). Set the start address of each interrupt routine
to the corresponding interrupt vector address in the interrupt vector table.
Routine in progress
ress
add
art .
t
s
o
e
es t utin
nch rupt ro
a
r
B
ter
of in
Interrupt request is accepted.
Interrupt routine
Interrupt processing
Processing is suspended.
Retu
rns t
Processing is resumed.
o ori
ginal
routi
Fig. 7.1.1 Interrupt processing sequence
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7721 Group User’s Manual
ne.
RTI instruction
INTERRUPTS
7.1 Overview
When an interrupt request is accepted, the following registers’ contents just before acceptance of an interrupt
request are automatically pushed onto the stack area ➀→➁→➂ in that order.
➀ Program bank register (PG)
➁ Program counter (PC L, PC H)
➂ Processor status register (PSL, PS H)
Figure 7.1.2 shows the state of the stack area just before entering the interrupt routine.
Execute the RTI instruction at the end of this interrupt routine to return to the routine that the microcomputer
was executing before the interrupt request was accepted. By executing the RTI instruction, the register
contents pushed onto the stack area are pulled ➂→➁→➀ in that order. Then, the suspended processing is
resumed from where it left off.
Stack area
Address
[S] – 5
[S] – 4
Processor status register’s low-order byte (PSL)
[S] – 3 Processor status register’s high-order byte (PSH)
[S] – 2
Program counter’s low-order byte (PCL)
[S] – 1
Program counter’s high-order byte (PCH)
[S]✽
Program bank register (PG)
✽ [S] is an initial address that the stack pointer (S) indicates
when an interrupt request is accepted. The S’s contents
become “[S] – 5” after all of the above registers are pushed.
Fig. 7.1.2 State of stack area just before entering interrupt routine
7721 Group User’s Manual
7–3
INTERRUPTS
7.2 Interrupt sources
7.2 Interrupt sources
Table 7.2.1 lists the interrupt sources and the interrupt vector addresses. When programming, set the start
address of each interrupt routine at the vector addresses listed in this table.
Table 7.2.1 Interrupt sources and interrupt vector addresses
Remarks
Interrupt source
Interrupt vector addresses
Reference
High-order
address
Low-order
address
FFFF16
FFFE16
FFFD 16
FFFC 16
DBC (Note)
FFFB16
FFF916
FFFA16
FFF816
4. RESET
Non-maskable software interrupt 7700 Family Software
Non-maskable software interrupt Manual
Do not use.
Watchdog timer
FFF716
FFF616
Non-maskable interrupt
INT0
____
FFF516
FFF416
INT1
INT2
FFF316
FFF216
FFF116
FFF016
Timer A0
Timer A1
FFEF16
FFED16
FFEE 16
FFEC16
Timer A2
FFEB 16
FFEA 16
Timer A3
FFE916
FFE816
Timer A4
Timer B0
FFE716
FFE616
FFE516
FFE416
Timer B1
Timer B2
FFE316
FFE116
FFE216
FFE016
UART0 receive
FFDF 16
FFDE16
UART0 transmit
FFDD16
FFDC 16
UART1 receive
FFDB16
FFDA16
UART1 transmit
FFD916
FFD816
A-D conversion
DMA0
FFD716
FFD516
FFD616
FFD416
DMA1
FFD316
FFD216
DMA2
FFD116
FFD016
FFCF 16
FFCE16
Reset
Zero division
BRK instruction
____
____
Non-maskable
15. WATCHDOG TIMER
Maskable external interrupts 7.10 External interrupts
____
____
DMA3
(INTi interrupt)
Maskable internal interrupts 8. TIMER A
Maskable internal interrupts 9. TIMER B
Maskable internal interrupts 11. SERIAL I/O
Maskable internal interrupt 12. A-D CONVERTER
Maskable internal interrupts 13. DMA CONTROLLER
____
Note: The DBC interrupt is used exclusively for debugger control.
●Maskable interrupt: An interrupt of which request’s acceptance can be disabled by software.
●Non-maskable interrupt (including Zero division, BRK instruction, Watchdog timer interrupts):
An interrupt which is certain to be accepted when its request occurs. These interrupts do not have their
interrupt control registers and are not affected by the interrupt disable flag (I).
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INTERRUPTS
7.3 Interrupt control
7.3 Interrupt control
The maskable interrupts are controlled by the following :
•Interrupt request bit
Assigned to the interrupt control register of each interrupt.
•Interrupt priority level select bits
•Processor interrupt priority level (IPL)
Assigned to the processor status register (PS).
•Interrupt disable flag (I)
}
}
Figure 7.3.1 shows the memory assignment of the interrupt control registers, and Figure 7.3.2 shows their
structures.
Address
6C16
DMA0 interrupt control register
6D16
DMA1 interrupt control register
6E16
DMA2 interrupt control register
6F16
DMA3 interrupt control register
7016
A-D conversion interrupt control register
7116
UART0 transmit interrupt control register
7216
UART0 receive interrupt control register
7316
UART1 transmit interrupt control register
7416
UART1 receive interrupt control register
7516
Timer A0 interrupt control register
7616
Timer A1 interrupt control register
7716
Timer A2 interrupt control register
7816
Timer A3 interrupt control register
7916
Timer A4 interrupt control register
7A16
Timer B0 interrupt control register
7B16
Timer B1 interrupt control register
7C16
Timer B2 interrupt control register
7D16
INT0 interrupt control register
7E16
INT1 interrupt control register
7F16
INT2 interrupt control register
Fig. 7.3.1 Memory assignment of interrupt control registers
7721 Group User’s Manual
7–5
INTERRUPTS
7.3 Interrupt control
b7
b6
b5
b4
b3
b2
b1
b0
DMA0 to DMA3, A-D conversion, UART0 and 1 transmit, UART0 and 1 receive, timers A0 to A4, timers B0 to B2
interrupt control registers (Addresses 6C16 to 7C16)
Bit
0
Interrupt priority level
select bits
1
2
3
Functions
Bit name
Interrupt request bit
At reset
RW
0 0 0 : Level 0 (Interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
0
RW
0
RW
0
RW
0 : No interrupt requested
1 : Interrupt requested
0
RW
Undefined
–
At reset
RW
0
RW
0
RW
0
RW
b2 b1 b0
7 to 4 Nothing is assigned.
b7
b6
b5
b4
b3
b2
b1
b0
INT0 to INT2 interrupt control registers (Addresses 7D16 to 7F16)
Bit
0
Functions
Bit name
Interrupt priority level
select bits
1
2
b2 b1 b0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
:
:
:
:
:
:
:
:
Level
Level
Level
Level
Level
Level
Level
Level
0 (Interrupt disabled)
1
2
3
4
5
6
7
3
Interrupt request bit (Note)
0 : No interrupt requested
1 : Interrupt requested
0
RW
4
Polarity select bit
0 : Interrupt request bit is set to “1”
at “H” level when level sense is
selected; this bit is set to “1” at
falling edge when edge sense is
selected.
1 : Interrupt request bit is set to “1”
at “L” level when level sense is
selected; this bit is set to “1” at
rising edge when edge sense is
selected.
0
RW
5
Level sense/Edge sense
select bit
0 : Edge sense
1 : Level sense
0
RW
Undefined
–
7, 6
Nothing is assigned.
Note: The interrupt request bits of INT0 to INT2 interrupts are invalid when the level sense is selected.
Fig. 7.3.2 Structures of interrupt control register
7–6
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INTERRUPTS
7.3 Interrupt control
7.3.1 Interrupt disable flag (I)
All maskable interrupts can be disabled by this flag. When this flag is set to “1,” all maskable interrupts
are disabled; when this flag is cleared to “0,” those interrupts are enabled. Because this flag is set to “1”
at reset, clear this flag to “0” when enabling interrupts.
7.3.2 Interrupt request bit
When an interrupt request occurs, this bit is set to “1.” This bit remains set to “1” until the interrupt request
is accepted; it is cleared to “0” when the interrupt request is accepted.
This ____
bit can also be set to “0” or “1” by software.
____
The INT i interrupt request bit (i = 0 to 2) is ignored when the INTi interrupt is used with level sense.
7.3.3 Interrupt priority level select bits and processor interrupt priority level (IPL)
The interrupt priority level select bits are used to determine the priority level of each interrupt.
When an interrupt request occurs, its interrupt priority level is compared with the processor interrupt priority
level (IPL). The requested interrupt is enabled only when the comparison result meets the following condition.
Accordingly, an interrupt can be disabled by setting its interrupt priority level to 0.
Each interrupt priority level > Processor interrupt priority level (IPL)
Table 7.3.1 lists the setting of interrupt priority level, and Table 7.3.2 lists the interrupt enabled level
corresponding to IPL contents.
The interrupt disable flag (I), interrupt request bit, interrupt priority level select bits, and processor interrupt
priority level (IPL) are independent of one another; they do not affect one another. Interrupt requests are
accepted only when the following conditions are satisfied.
•Interrupt disable flag (I) = “0”
•Interrupt request bit = “1”
•Interrupt priority level > Processor interrupt priority level (IPL)
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INTERRUPTS
7.3 Interrupt control
Table 7.3.1 Setting of interrupt priority level
Interrupt priority level select bits
b0
b1
b2
0
0
0
Interrupt priority level
Level 0 (Interrupt disabled)
0
0
0
1
1
0
0
1
1
Level 2
Level 3
1
1
0
0
Level 4
0
1
Level 5
1
1
0
Level 6
1
1
1
Level 7
Level 1
—
Low
High
Table 7.3.2 Interrupt enabled level corresponding to IPL contents
IPL2
0
IPL1
IPL0
0
0
Enabled interrupt priority level
Enable level 1 and above interrupts.
0
0
1
Enable level 2 and above interrupts.
0
1
0
Enable level 3 and above interrupts.
0
1
1
Enable level 4 and above interrupts.
1
0
0
Enable level 5 and above interrupts.
1
1
0
1
1
0
Enable level 6 and level 7 interrupts.
Enable only level 7 interrupt.
1
1
1
Disable all maskable interrupts.
IPL 0: Bit 8 in processor status register (PS)
IPL 1: Bit 9 in processor status register (PS)
IPL 2: Bit 10 in processor status register (PS)
7–8
Priority
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INTERRUPTS
7.4 Interrupt priority level
7.4 Interrupt priority level
When the interrupt disable flag (I) = “0” (interrupts enabled) and more than one interrupt request is detected
at the same sampling timing, which means a timing to check whether an interrupt request exists or not, they
are accepted in order of priority levels. In other words, the interrupt request with the highest priority level
is accepted first.
Among a total of 23 interrupt sources, the user can set the desired priority levels for 20 interrupt sources
except software interrupts (zero division and BRK instruction interrupts) and the watchdog timer interrupt.
Use the interrupt priority level select bits to set their priority levels. Priority levels of reset, which is handled
as the interrupt request with the highest priority, and the watchdog timer interrupt are set by hardware.
Figure 7.4.1 shows the interrupt priority set by hardware.
Note that software interrupts are not affected by the interrupt priority levels. Whenever the instruction is
executed, a program certainly branches to the interrupt routine.
Reset
Watchdog
timer
Priority levels determined by hardware
••••••••••••••••••
20 interrupt sources except software interrupts
and watchdog timer interrupt
The user can set the desired priority levels inside of the dotted line.
Low
Priority level
High
Fig. 7.4.1 Interrupt priority level set by hardware
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INTERRUPTS
7.5 Interrupt priority level detection circuit
7.5 Interrupt priority level detection circuit
The interrupt priority level detection circuit selects the interrupt with the highest priority level when more than
one interrupt request occurs at the same sampling timing. Figure 7.5.1 shows the interrupt priority level
detection circuit.
Interrupt priority level
Level 0 (initial value)
DMA3
DMA2
DMA1
DMA0
Interrupt priority level
A-D conversion
Timer A4
UART1 transmit
Timer A3
UART1 receive
Timer A2
UART0 transmit
Timer A1
UART0 receive
Timer A0
Timer B2
INT2
Timer B1
INT1
Timer B0
INT0
Interrupt with the highest priority level
IPL
Processor interrupt priority level
Interrupt
disable flag (I)
Watchdog timer interrupt
Reset
Fig. 7.5.1 Interrupt priority level detection circuit
7–10
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Accepting of interrupt request
INTERRUPTS
7.5 Interrupt priority level detection circuit
The following explains the operation of the interrupt priority detection circuit using Figure 7.5.2.
The interrupt priority level of a requested interrupt (Y in Figure 7.5.2) is compared with the resultant priority
level which is sent from the preceding comparator (X in Figure 7.5.2); the interrupt with the higher priority
level is sent to the next comparator (Z in Figure 7.5.2). (Initial comparison value of “X” is “0.”) For an
interrupt which is not requested, the comparison is not performed and the priority level which is sent from
the preceding comparator is forwarded to the next comparator as it is. When the two priority levels are found
the same by comparison, the priority level which is sent from the preceding comparator is forwarded to the
next comparator. Accordingly, when the same priority level is set by software, the interrupt priority levels are
handled as follows:
DMA3 > DMA2 > DMA1 > DMA0 > A-D conversion > UART1 transmit > UART1 receive > UART0 transmit
> UART0
receive
> Timer
B2 > Timer B1 > Timer B0 > Timer A4 > Timer A3 > Timer A2 > Timer A1 > Timer
____
____
____
A0 > INT 2 > INT 1 > INT 0
Among the multiple interrupt requests sampled at the same time, one request with the highest priority level
is detected by the above comparison.
Then, this highest interrupt priority level is compared with the processor interrupt priority level (IPL). When
this interrupt priority level is higher than the processor interrupt priority level (IPL) and the interrupt disable
flag (I) is “0,” the interrupt request is accepted. A interrupt request which is not accepted here is held until
it is accepted or its interrupt request bit is cleared to “0” by software.
The interrupt priority is detected when the CPU fetches an op code, which is called the CPU’s op-code fetch
cycle. However, when an op-code fetch cycle starts during detection of an interrupt priority, a new interrupt
priority detection does not start. (Refer to “Figure 7.6.1.”) Since the state of the interrupt request bit and
interrupt priority levels are latched during the interrupt priority detection, even if they change, the interrupt
priority detection is performed for the previous state before the change occurred.
The interrupt priority level is detected when the CPU fetches an op code. Therefore, in the following
execution or states, after the execution or state is terminated, no interrupt request is accepted until the CPU
fetches the op code of the next instruction.
•Execution of an instruction which requires many cycles, such as the MVN or MVP instruction
•During DRAM refreshment
•During Hold state
•During DMA transfer
X
Y
Time
Interrupt source Y
Comparator
(Priority level
comparison)
X : Priority level sent from the preceding
comparator (Highest priority at this point)
Y : Priority level of interrupt source Y
Z : Highest priority at this point
Z
●When X
●When X
Y then Z = X
Y then Z = Y
Fig. 7.5.2 Interrupt priority level detection model
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INTERRUPTS
7.6 Interrupt priority level detection time
7.6 Interrupt priority level detection time
When the interrupt priority level detection time has passed after sampling starts, an interrupt request is
accepted. The interrupt priority level detection time can be selected by software. Figure 7.6.1 shows the
interrupt priority level detection time. Usually, select “2 cycles of φ” as the interrupt priority level detection
time.
(1) Interrupt priority detection time select bits
b7
b6
b5
b4
b3
b2
b1
b0
Processor mode register 0 (Address 5E16)
0
Processor mode bits
Wait bit
Software reset bit
b5, b4
Interrupt priority detection time select bits
00
7 cycles of
[(a) shown below]
01
4 cycles of
[(b) shown below]
10
2 cycles of
[(c) shown below]
11
Do not select.
Must be fixed to “0.”
Clock
1
output select bit
(2) Interrupt priority level detection time
Op-code fetch cycle
(Note)
Sampling pulse
(a) 7 cycles
Interrupt priority level
detection time (b) 4 cycles
(c) 2 cycles
Note: The pulse resides when “2 cycles of
” is selected.
Fig. 7.6.1 Interrupt priority level detection time
7–12
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INTERRUPTS
7.7 Sequence from acceptance of interrupt request until execution of interrupt routine
7.7 Sequence from acceptance of interrupt request until execution of interrupt routine
The sequence from the acceptance of interrupt request until the execution of the interrupt routine is described
below.
When an interrupt request is accepted, the interrupt request bit of the accepted interrupt is cleared to “0.”
And then, the interrupt processing starts from the cycle just after the completion of the instruction which was
executed at accepting the interrupt request. Figure 7.7.1 shows the sequence from acceptance of interrupt
request to execution of interrupt routine. After execution of an instruction at accepting the interrupt request
is completed, an INTACK (Interrupt Acknowledge) sequence is executed, and a branch is made to the start
address of the interrupt routine allocated in addresses 0 16 to FFFF16.
The INTACK sequence is automatically performed in the following order.
➀ The contents of the program bank register (PG) just before performing the INTACK sequence are pushed
onto stack.
➁ The contents of the program counter (PC) just before performing the INTACK sequence are pushed onto
stack.
➂ The contents of the processor status register (PS) just before performing the INTACK sequence is
pushed onto stack.
➃ The interrupt disable flag (I) is set to “1.”
➄ The interrupt priority level of the accepted interrupt is set into the processor interrupt priority level (IPL).
➅ The contents of the program bank register (PG) are cleared to “0016,” and the contents of the interrupt
vector address are set into the program counter (PC).
Performing the INTACK sequence requires at least 13 cycles of internal clock φ . Figure 7.7.2 shows the
INTACK sequence timing. After the INTACK sequence is completed, the instruction execution starts from the
start address of the interrupt routine.
Interrupt request is accepted.
Interrupt request occurs.
@
@
Instruction Instruction
1
2
➀
➁
INTACK sequence
Time
Instructions in interrupt routine
➂
Interrupt response time
@ : Interrupt priority level detection time
➀ Time from the occurrence of an interrupt request until the instruction execution which is in progress
at that time is completed.
➁ Time from when execution of an instruction next to ➀ begins (Note) until the instruction execution
which is in progress at completion of interrupt priority level detection.
Note: At this time, detection of interrupt priority level begins.
➂ Time required to execute the INTACK sequence (13 cycles of at minimum)
Fig. 7.7.1 Sequence from acceptance of interrupt request until execution of interrupt routine
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INTERRUPTS
7.7 Sequence from acceptance of interrupt request until execution of interrupt routine
●When stack pointer (S)’s contents are even and no Wait
Internal
clock
CPU
AP
PG
00
00
AH
PCH
00
[S]H
AL
PCL
00
[S]L
DH
FF16
DL
XX16
00
00
00
([S]–1)H ([S]–2)H ([S]–3)H ([S]–4)H ([S]–5)H ([S]–5)H
FF16
ADH
([S]–1)L ([S]–2)L ([S]–3)L ([S]–4)L ([S]–5)L ([S]–5)L
XX16
ADL
PG
00
00
00
00
00
PCH
PSH
ADH
Op-code
PCL
PSL
ADL
Op-code
Interrupt
disable
flag (I)
INTACK sequence
CPU
AP
AH
AL
DH
DL
: CPU standard clock
: High-order 8 bits of CPU internal address bus
: Middle-order 8 bits of CPU internal address bus
: Low-order 8 bits of CPU internal address bus
: CPU internal data bus for odd address
: CPU internal data bus for even address
: Not used
[S] : Contents of stack pointer (S)
XX16 : Low-order 8 bits of vector address
AD H : Contents of vector address (High-order address)
AD L : Contents of vector address (Low-order address)
Fig. 7.7.2 INTACK sequence timing (at minimum)
7.7.1 Change in IPL at acceptance of interrupt request
When an interrupt request is accepted, the processor interrupt priority level (IPL) is replaced with the
interrupt priority level of the accepted interrupt. This results in easy control of the processing for multiple
interrupts. (Refer to section “7.9 Multiple interrupts.”)
At reset or when a watchdog timer interrupt or a software interrupt is accepted, a value listed in Table 7.7.1
is set into the IPL.
Table 7.7.1 Change in IPL at acceptance of interrupt request
Change in IPL
Interrupts
Reset
Level 0 (“0002”) is set.
Watchdog timer
Zero division
Level 7 (“1112”) is set.
Not changed.
BRK instruction
Not changed.
Other interrupts
Accepted interrupt priority level is set.
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INTERRUPTS
7.7 Sequence from acceptance of interrupt request until execution of interrupt routine
7.7.2 Push operation for registers
The push operation for registers performed in the INTACK sequence depends on whether the contents of
the stack pointer (S) at acceptance of an interrupt request are even or odd.
When the contents of the stack pointer (S) are even, the contents of the program counter (PC) and the
processor status register (PS) are simultaneously pushed in a unit of 16 bits. When the contents of the
stack pointer (S) are odd, each of these registers is pushed in a unit of 8 bits. Figure 7.7.3 shows the push
operation for registers.
In the INTACK sequence, only the contents of the program bank register (PG), program counter (PC), and
processor status register (PS) are pushed onto the stack area. The other necessary registers must be
pushed by software at the start of the interrupt routine.
By using the PSH instruction, all CPU registers except the stack pointer (S) can be pushed.
(1) When contents of stack pointer (S) are even
Address
[S] – 5 (odd)
Order for push
[S] – 4 (even)
Low-order byte of processor status register (PSL)
[S] – 3 (odd)
High-order byte of processor status register (PSH)
[S] – 2 (even)
Low-order byte of program counter (PCL)
[S] – 1 (odd)
High-order byte of program counter (PCH)
[S] (even)
➂ Pushed in a unit of 16 bits.
➁ Pushed in a unit of 16 bits.
➀
Program bank register (PG)
Pushed in 3 times.
(2) When contents of stack pointer (S) are odd
Address
Order for push
[S] – 5 (even)
[S] – 4 (odd)
Low-order byte of processor status register (PSL)
➃
[S] – 3 (even)
High-order byte of processor status register (PSH)
➄
[S] – 2 (odd)
Low-order byte of program counter (PCL)
➁
[S] – 1 (even)
High-order byte of program counter (PCH)
➂
Program bank register (PG)
➀
[S] (odd)
Pushed in a unit of 8 bits.
Pushed in 5 times.
✽ [S] is an initial address that the stack pointer (S) indicates when an interrupt request is accepted.
The S’s contents become “[S] – 5” after all of the above registers are pushed.
Fig. 7.7.3 Push operation for registers
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INTERRUPTS
7.8 Return from interrupt routine, 7.9 Multiple interrupts
7.8 Return from interrupt routine
When the RTI instruction is executed at the end of the interrupt routine, the contents of the program bank
register (PG), program counter (PC), and processor status register (PS) which were pushed onto the stack
area just before the INTACK sequence, are automatically pulled. After this, the control returns to the original
routine. And then, the suspended processing, which was in progress before the acceptance of the interrupt
request, is resumed.
Before the RTI instruction is executed, pull registers which were pushed by software in the interrupt routine,
using the PUL instruction, etc.
7.9 Multiple interrupts
Just after a branch is made to an interrupt routine, the following occur:
•Interrupt disable flag (I) = “1” (Interrupts are disabled)
•Interrupt request bit of accepted interrupt = “0”
•Processor interrupt priority level (IPL) = Interrupt priority level of accepted interrupt
Accordingly, as long as the IPL remains unchanged, an interrupt request whose priority level is higher than
that of the interrupt which is in progress can be accepted by clearing the interrupt disable flag (I) to “0” in
an interrupt routine. In this way, multiple interrupts are processed.
Figure 7.9.1 shows the processing for multiple interrupts.
An interrupt request which has not been accepted because its priority level is lower is held. When the RTI
instruction is executed, the interrupt priority level of the routine which was in progress at acceptance of an
interrupt request is pulled into the IPL. Therefore, if the following relationship is satisfied when interrupt
priority level detection is performed next, the held interrupt request is accepted.
Held interrupt request’s priority level > Processor interrupt priority level (IPL)
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INTERRUPTS
7.9 Multiple interrupts
Interrupt request
generated
Time
Reset
Nesting
Main routine
I=1
Interrupt 1
IPL = 0
I=0
Interrupt priority level=3
Interrupt 1
I=1
IPL = 3
Interrupt 2
Multiple interrupts
I=0
Interrupt priority level=5
Interrupt 2
I=1
IPL = 5
Interrupt 3
RTI
Interrupt priority level=2
I=0
IPL = 3
Interrupt 3
RTI
This request cannot be accepted
because its priority level is lower
than the interrupt 1’s one.
I=0
IPL = 0
The instruction in the main routine is
not executed.
Interrupt 3
I=1
IPL = 2
RTI
I=0
I : Interrupt disable flag
IPL = 0
IPL : Processor interrupt priority level
: They are automatically set.
: They must be set by software.
Fig. 7.9.1 Processing for multiple interrupts
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INTERRUPTS
___
7.10 External interrupts (INTi interrupt)
____
7.10 External interrupts (INTi interrupt)
____
An external interrupt request occurs by an input signal to the INTi (i = 0 to 2) pin. The occurrence factor
of the interrupt request can be selected by the level sense/edge sense select bit and the polarity select bit
(bits 5 and 4 at addresses 7D16 to 7F 16) shown in Figure 7.10.1. Table 7.10.1 lists the occurrence factor of
____
INT i interrupt request.
____
____
When using P10 0/INT 0 to P102/INT 2 pins as input pins of external interrupts, set the corresponding bits at
register) to “0.” (Refer to “Figure 7.10.2.”)
address 1816 (port P10 direction
____
The signals input to the INT i pin require “H”-____
or “L”- level____
width of 250 ns or more, independent of f(XIN).
Additionally, even when using the pins P100/INT 0 to P10 2/INT 2 as the input pins of external interrupts, the
user can obtain the pin’s state by reading bits 0 to 2 at address 16 16 (port P10 register).
Note: When selecting an input signal’s falling or “L” level as the occurrence factor of an interrupt request,
make sure that the input signal is held “L” for 250 ns or more. When selecting an input signal’s rising
or “H” level as that, make sure that the input signal is held “H” for 250 ns or more.
___
Table 7.10.1 Occurrence factor of INT i interrupt request
___
b5
b4
INT i interrupt request occurrence___
factor
0
0
Interrupt request occurs at the falling edge of a signal input to pin ___
INTi (Edge sense).
0
1
Interrupt request occurs at the rising edge of a signal input to pin INTi (Edge sense).
___
1
0
Interrupt request occurs when pin INT
i is at “H” level (Level sense).
___
1
1
Interrupt request occurs when pin INTi is at “L” level (Level sense).
___
___
The INT i interrupt ___
request occurs by detecting
the state of pin INTi all the time. Therefore, when the user
___
does not use the INT i interrupt, set the INT i interrupt’s priority level to level 0.
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INTERRUPTS
___
7.10 External interrupts (INTi interrupt)
b7
b6
b5
b4
b3
b2
b1
b0
INT0 to INT2 interrupt control registers (Addresses 7D16 to 7F16)
Bit
Bit name
0
Interrupt priority level select bits
1
2
Functions
At reset
RW
0 0 0 : Level 0 (Interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
0
RW
0
RW
0
RW
b2 b1 b0
3
Interrupt request bit (Note)
0 : No interrupt requested
1 : Interrupt requested
0
RW
4
Polarity select bit
0 : Interrupt request bit is set to “1”
at “H” level when level sense is
selected; this bit is set to “1” at
falling edge when edge sense is
selected.
1 : Interrupt request bit is set to “1”
at “L” at level when level sense is
selected; this bit is set to “1” at
rising edge when edge sense is
selected.
0
RW
5
Level sense/Edge sense
select bit
0 : Edge sense
1 : Level sense
0
RW
Undefined
–
7, 6
Nothing is assigned.
Note: The interrupt request bits of INT0 to INT2 interrupts are invalid when the level sense is selected.
___
Fig. 7.10.1 Structure of INT i (i=0 to 2) interrupt control register
b7
b6
b5
b4
b3
b2
b1
b0
Port P10 direction register (Address 1816)
Bit
Corresponding pin
0
INT0 pin
1
INT1 pin
Functions
0 : Input mode
1 : Output mode
When using a pin as an input pin
for an external interrupt,clear the
corresponding bit to “0.”
At reset
RW
0
RW
0
RW
0
RW
0
RW
2
INT2 pin
3
TC pin
4
CAS pin
0
RW
5
RAS pin
0
RW
6
MA8 pin
0
RW
7
MA9 pin
0
RW
: Bits 3 to 7 are not used for external interrupts.
Fig. 7.10.2 Relationship between port P10 direction register and input pins of external interrupt
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INTERRUPTS
___
7.10 External interrupts (INTi interrupt)
____
7.10.1 Functions of INT i interrupt request bit
(1) Functions when edge sense is selected
The interrupt request bit has the same functions as that of an internal interrupt. That is, when an
interrupt request occurs, the interrupt request bit is set to “1” and retains this state until the interrupt
request is accepted. When this bit is cleared to “0” by software, the interrupt request is cancelled;
when this bit is set to “1” by software, the interrupt request can be generated.
(2) Functions
when level sense is selected
___
The INTi interrupt request bit is ignored.
___
___
Interrupt requests continuously occur while the level of the INT i pin is the valid
level✽1; when the INTi
___
pin’s level changes from the valid level to the invalid level✽2 before the INT i interrupt request is
accepted, this interrupt request is not retained. (Refer to “Figure 7.10.4.”)
Valid level✽1: This means the level selected by the polarity select bit (bit 4 at addresses 7D16 to 7F16)
Invalid level✽2: This means the reversed level of “valid level”
Data bus
Edge detection
circuit
INTi pin
Interrupt request bit
“0”
Level sense/Edge sense
select bit
Interrupt request
“1”
___
Fig. 7.10.3 INTi Interrupt request
Interrupt request is accepted.
When the INTi pin’s level changes
to the invalid level before an interrupt
request is accepted, the interrupt
request is not retained.
Return to main routine.
Valid
INTi pin level
Invalid
Main routine
Main routine
First interrupt routine
Second interrupt
routine
Third interrupt
routine
____
Fig. 7.10.4 Occurrence of INTi interrupt request when level sense is selected
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7721 Group User’s Manual
INTERRUPTS
___
7.10 External interrupts (INTi interrupt)
___
7.10.2 Switching
of INTi interrupt request occurrence factor
___
When the INT i interrupt request occurrence factor is switched in one of the following ways, the interrupt
request bit may be set to “1”:
•Switching the level sense to the edge sense
•Switching polarity
Therefore, after this switching, make sure to____
clear the interrupt request bit to “0.” Figure 7.10.5 shows an
example of the switching procedure for the INT i interrupt request occurrence factor.
(1) Switching level sense to edge sense
(2) Switching polarity
Set the interrupt priority level to level 0
or set the interrupt disable flag (I) to “1.”
(INTi interrupt is disabled. )
Set the interrupt priority level to level 0
or set the interrupt disable flag (I) to “1.”
(INTi interrupt is disabled. )
Set the polarity select bit.
Clear the level sense/edge sense select bit to “0.”
( Edge sense is selected. )
Clear the interrupt request bit to “0.”
Clear the interrupt request bit to “0.”
Set the interrupt priority level to one of levels 1–7
or clear the interrupt disable flag (I) to “0.”
(INTi interrupt request is acceptable.)
Set the interrupt priority level to one of levels 1–7
or clear the interrupt disable flag (I) to “0.”
(INTi interrupt request is acceptable.)
Note: The above settings must be done separately.
Multiple settings must not be done at the same time, in other words, they must not be done
only by 1 instruction.
___
Fig. 7.10.5 Example of switching procedure for INT i interrupt request occurrence factor
7721 Group User’s Manual
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INTERRUPTS
7.11 Precautions for interrupts
7.11 Precautions for interrupts
When changing the interrupt priority level select bits (bits 0 to 2 at addresses 6C16 to 7F16), 2 to 7 cycles
of φ are required until the interrupt priority level is changed. Therefore, when the interrupt priority level of
a certain interrupt source is repeatedly changed in a very short time, which consists of a few instructions,
it is necessary to reserve the time required for the change by software. Figure 7.11.1 shows a program
example to reserve the time required for the change. Note that the time required for the change depends
on the contents of the interrupt priority detection time select bits (bits 4 and 5 at address 5E16). Table 7.11.1
lists the correspondence between the number of instructions inserted in Figure 7.11.1 and the interrupt
priority detection time select bits.
:
LDM.B #0XH, 00XXH
NOP
NOP
NOP
LDM.B #0XH, 00XXH
:
; Write instruction for the interrupt priority level select bits
; Inserted NOP instruction (Note)
;
;
; Write instruction for the interrupt priority level select bits
Note: Except the write instruction for address XX16, any instruction which has the same
cycles as the NOP instruction can also be inserted.
For the number of inserted NOP instructions, refer to “Table 7.11.1.”
XX: any of 6C to 7F
Fig. 7.11.1 Program example to reserve time required for change of interrupt priority level
Table 7.11.1 Correspondence between number of instructions to be inserted in Figure 7.11.1 and
interrupt priority detection time select bits
Interrupt priority detection time select bits (Note)
b5
b4
0
0
0
1
Interrupt priority level
Number of inserted
detection time
NOP instructions
7 cycles of φ
4 cycles of φ
4 or more
2 or more
1 or more
1
0
2 cycles of φ
1
1
Do not select.
Note: We recommend [b5 = “1”, b4 = “0”].
7–22
7721 Group User’s Manual
CHAPTER 8
TIMER A
8.1 Overview
8.2 Block description
8.3 Timer mode
[Precautions for timer mode]
8.4 Event counter mode
[Precautions for event counter mode]
8.5 One-shot pulse mode
[Precautions for one-shot pulse mode]
8.6 Pulse width modulation (PWM) mode
[Precautions for pulse width modulation
(PWM) mode]
TIMER A
8.1 Overview
8.1 Overview
Timer
to A4
Timer
A2 to
A consists of five counters, Timers A0 to A4, each equipped with a 16-bit reload function. Timers A0
operate independently of one another.
A has four operating modes listed below. Timers A0 and A1 operate in the timer mode only. Timers
A4 have selective four operating modes listed below.
(1) Timer mode (Timers A0 to A4)
The timer counts an internally generated count source. For Timers A2 to A4, the following functions
can be used in this mode:
•Gate function
•Pulse output function
(2) Event counter mode (Timers A2 to A4)
The timer counts an external signal. The following functions can be used in this mode:
•Pulse output function
•Two-phase pulse signal processing function
(3) One-shot pulse mode (Timers A2 to A4)
The timer outputs a pulse which has an arbitrary width once.
(4) Pulse width modulation (PWM) mode (Timers A2 to A4)
Timer outputs pulses which have an arbitrary width in succession. The counter functions as one of
the following pulse width modulators:
•16-bit pulse width modulator
•8-bit pulse width modulator
In this chapter, Timer Ai (i = 0 to 4) indicates Timers A0 to A4. Timer Aj (j = 2 to 4) indicates Timers A2
to A4; this is applies when the timer A’s input/output pins are used etc. (Hereafter, input/output pins are
called I/O pins.)
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TIMER A
8.2 Block description
8.2 Block description
Figure 8.2.1 shows the block diagram of Timer A. Explanation of registers relevant to Timer A is described
below.
f2
Count source
select bits
Data bus (odd)
f 16
f 64
Data bus (even)
f 512
(Low-order 8 bits)
Timer mode
One-shot pulse mode
PWM mode
Timer Ai reload register (16)
Timer mode
(Gate function)
TAj IN
Polarity
switching
(High-order 8 bits)
Timer Ai counter (16)
Event counter mode
Count start bit
Trigger
Timer Ai
interrupt
request bit
Countup/Countdown
switching
(Always “count down” except
for event counter mode)
Countdown
Up-down bit
Pulse output
function select bit
TAj OUT
Toggle
F.F.
i = 0–4, j = 2–4
Fig. 8.2.1 Block diagram of Timer A
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8–3
TIMER A
8.2 Block description
8.2.1 Counter and reload register (timer Ai register)
Each of timer Ai counter and reload register consists of 16 bits.
Countdown in the counter is performed each time the count source is input. In the event counter mode,
it can also function as an up-counter.
The reload register is used to store the initial value of the counter. When a counter underflow or overflow
occurs, the reload register’s contents are reloaded into the counter.
A value is set to the counter and reload register by writing the value to the timer Ai register. Table 8.2.1
lists the memory assignment of the timer Ai register.
The value written into the timer Ai register while counting is not in progress is set to the counter and reload
register. The value written into the timer Ai register while counting is in progress is set only to the reload
register. In this case, the reload register’s updated contents are transferred to the counter at the next
reload time. The value obtained when reading out the timer Ai register varies according to the operating
mode. Table 8.2.2 lists reading from and writing to the timer Ai register.
Table 8.2.1 Memory assignment of timer Ai register
Timer Ai register
Timer A0 register
High-order byte
Address 47 16
Low-order byte
Address 4616
Timer A1 register
Address 49 16
Address 4816
Timer A2 register
Address 4B 16
Address 4A 16
Timer A3 register
Timer A4 register
Address 4D16
Address 4F 16
Address 4C16
Address 4E 16
Note: At reset, the contents of the timer Ai
register are undefined.
Table 8.2.2 Reading from and writing to timer Ai register
Operating mode
Timer mode
Event counter mode
One-shot pulse mode
Pulse width modulation (PWM) mode
Read
Counter value is read out.
(Note 1)
Undefined value is read out.
Write
<While counting>
Written only to reload register.
<While not counting>
Written to both of the counter
and reload register.
Notes 1: Also refer to “[Precautions for timer mode]” and “[Precautions for event counter mode].”
2: When reading from and writing to the timer Ai register, perform it in a unit of 16 bits.
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7721 Group User’s Manual
TIMER A
8.2 Block description
8.2.2 Count start register
This register is used to start and stop counting. Each bit of this register corresponds to each timer. Figure
8.2.2 shows the structure of the count start register.
b7
b6
b5
b4
b3
b2
b1
b0
Count start register (Address 4016)
Bit
Bit name
Functions
0 : Stop counting
1 : Start counting
At reset
RW
0
RW
0
Timer A0 count start bit
1
Timer A1 count start bit
0
RW
2
Timer A2 count start bit
0
RW
3
Timer A3 count start bit
0
RW
4
Timer A4 count start bit
0
RW
5
Timer B0 count start bit
0
RW
6
Timer B1 count start bit
0
RW
7
Timer B2 count start bit
0
RW
: Bits 5 to 7 are not used for Timer A.
Fig. 8.2.2 Structure of count start register
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8–5
TIMER A
8.2 Block description
8.2.3 Timer Ai mode register
Figure 8.2.3 shows the structure of the timer Ai mode register. The operating mode select bits are used
to select the operating mode of Timer Ai. Bits 2 to 7 have different functions according to the operating
mode. These bits are described in the paragraph of each operating mode.
b7
b6
b5
b4
b3
b2
b1
b0
Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16)
Bit
Bit name
Functions
At reset
RW
0
RW
0
RW
0
RW
3
0
RW
4
0
RW
5
0
RW
6
0
RW
7
0
RW
0
Operating mode select bits
1
2
b1 b0
0 0 : Timer mode
0 1 : Event counter mode
1 0 : One-shot pulse mode
1 1 : Pulse width modulation (PWM) mode
These bits have different functions according to the operating mode.
Fig. 8.2.3 Structure of timer Ai mode register
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7721 Group User’s Manual
TIMER A
8.2 Block description
8.2.4 Timer Ai interrupt control register
Figure 8.2.4 shows the structure of the timer Ai interrupt control register. For details about interrupts, refer
to “CHAPTER 7. INTERRUPTS.”
b7
b6
b5
b4
b3
b2
b1
b0
Timer Ai interrupt control register (i = 0 to 4) (Addresses 7516 to 7916)
Bit
0
Interrupt priority level
select bits
1
2
3
Functions
Bit name
Interrupt request bit
At reset
RW
0 0 0 : Level 0 (Interrupt disabled)
0 0 1 : Level 1
Low level
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
High level
0
RW
0
RW
0
RW
0 : No interrupt requested
1 : Interrupt requested
0
RW
Undefined
–
b2 b1 b0
7 to 4 Nothing is assigned.
Fig. 8.2.4 Structure of timer Ai interrupt control register
(1) Interrupt priority level select bits (bits 2 to 0)
These bits select a timer Ai interrupt’s priority level. When using timer Ai interrupts, select one of the
priority levels (1 to 7). When a timer Ai interrupt request occurs, its priority level is compared with
the processor interrupt priority level (IPL). The requested interrupt is enabled only when its priority
level is higher than the IPL. (However, this applies when the interrupt disable flag (I) = “0.”) To
disable timer Ai interrupts, set these bits to “0002” (level 0).
(2) Interrupt request bit (bit 3)
This bit is set to “1” when a timer Ai interrupt request occurs. This bit is automatically cleared to “0”
when the timer Ai interrupt request is accepted. This bit can be set to “1” or cleared to “0” by
software.
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TIMER A
8.2 Block description
8.2.5 Port P5 direction register
The I/O pins of Timers A2 to A4 are multiplexed with port P5. When using these pins as Timer Aj’s input
pins, set the corresponding bits of the port P5 direction register to “0” to set these port pins for the input
mode. When used as Timer Aj’s output pins, these pins are forcibly set to the output pins of Timer Aj
regardless of the direction registers’s contents. Figure 8.2.5 shows the relationship between the port P5
direction register and the Timer Aj’s I/O pins.
b7
b6
b5
b4
b3
b2
b1
b0
Port P5 direction register (Address D16)
Bit
Bit name
0
TA2OUT pin
1
TA2IN pin
Functions
0 : Input mode
1 : Output mode
When using these pins as Timer Aj’
s input pins, set the corresponding
bits to “0.”
RW
0
RW
0
RW
0
RW
0
RW
2
TA3OUT pin
3
TA3IN pin
4
TA4OUT pin
0
RW
5
TA4IN pin
0
RW
6
TB0IN pin
0
RW
7
TB1IN pin
0
RW
: Bits 6 and 7 are not used for Timer A.
Fig. 8.2.5 Relationship between port P5 direction register and Timer Aj’s I/O pins
8–8
At reset
7721 Group User’s Manual
TIMER A
8.3 Timer mode
8.3 Timer mode
In this mode, the timer counts an internally generated count source. (Refer to “Table 8.3.1.”) Figure 8.3.1
shows the structures of the timer Ai mode register and timer Ai register in the timer mode.
Table 8.3.1 Specifications of timer mode
Specifications
Item
Count source
f 2, f 16, f 64, or f 512
Count operation
• Countdown
• When a counter underflow occurs, reload register’s contents are reloaded,
and counting continues.
Division ratio
1
(n + 1)
n : Timer Ai register’s set value
Count start condition
When the count start bit is set to “1.”
Count stop condition
When the count start bit is cleared to “0.”
Interrupt request occurrence timing When a counter underflow occurs.
TAj IN pin’s function
Programmable I/O port or gate input
TAj OUT pin’s function
Programmable I/O port or pulse output
Read from timer Ai register
Counter value can be read out.
Write to timer Ai register
● While counting is stopped
When a value is written to the timer Ai register, it is written to both
of the reload register and counter.
● While counting is in progress
When a value is written to the timer Ai register, it is written only to
the reload register. (Transferred to the counter at the next reload
timing.)
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TIMER A
8.3 Timer mode
b7
b6
b5
b4
b3
b2
b1
b0
Timer A0 mode register (Address 5616)
Timer A1 mode register (Address 5716)
0 0 0 0 0 0
Bit
Bit name
Functions
At reset
RW
0
RW
1
0
RW
2
0
RW
3
0
RW
4
0
RW
5
0
RW
0
RW
0
RW
0
6
Fix these bits to “0.”
Count source select bits
b7 b6
0 0 : f2
0 1 : f16
1 0 : f64
1 1 : f512
7
b7 b6
b5 b4 b3 b2
b1 b0
0
0 0
Timer Aj mode register (j = 2 to 4) (Addresses 5816 to 5A16)
Bit
0
Bit name
Functions
Operating mode select bits
b1 b0
0 0 : Timer mode
1
0
RW
0
RW
Pulse output function select bit
0 : No pulse output
(TAjOUT pin functions as a programmable
I/O port.)
1 : Pulse output
(TAjOUT pin functions as a pulse output
pin.)
0
RW
3
Gate function select bits
b4 b3
0
RW
0
RW
0
RW
0
RW
0
RW
0 0 : No gate function
0 1 : (TAjIN pin functions as a programmable I/O port.)
1 0 : Counter counts only while TAj IN
pin’s input signal is at “L” level.
1 1 : Counter counts only while TAj IN
pin’s input signal is at “H” level.
5
Fix this bit to “0” in timer mode.
6
Count source select bits
7
(b8)
b0 b7
RW
2
4
(b15)
b7
At reset
b7 b6
0 0 : f2
0 1 : f16
1 0 : f64
1 1 : f512
Timer A0 register (Addresses 4716, 4616)
Timer A1 register (Addresses 4916, 4816)
Timer A2 register (Addresses 4B16, 4A16)
Timer A3 register (Addresses 4D16, 4C16)
Timer A4 register (Addresses 4F16, 4E16)
b0
Bit
Functions
15 to 0 These bits can be set to “000016” to “FFFF16.”
Assuming that the set value = n, the counter
divides the count source frequency by (n + 1).
When reading, the register indicates the
counter value.
At reset
RW
Undefined
RW
Note: Read from or write to this register in a unit of 16 bits.
Fig. 8.3.1 Structures of timer Ai mode register and timer Ai register in timer mode
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7721 Group User’s Manual
TIMER A
8.3 Timer mode
8.3.1 Setting for timer mode
Figures 8.3.2 and 8.3.3 show an initial setting example for registers relevant to the timer mode.
Note that when using interrupts, set up to enable the interrupts. For details, refer to section “CHAPTER
7. INTERRUPTS.”
Selecting timer mode and each function
b7
b0
0
0 0
Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16)
Selection of timer mode
Pulse output function select bit
0: No pulse output.
1: Pulses output.
Gate function select bits
b4 b3
0 0:
No gate function
0 1:
1 0: Gate function (Counter counts only while TAjIN pin’s input signal is at “L” level.)
1 1: Gate function (Counter counts only while TAjIN pin’s input signal is at “H” level.)
Count source select bits
b7 b6
0 0: f2
0 1: f16
1 0: f64
1 1: f512
Note: For Timers A0 and A1, set bits 0 to 5 to “0.”
Setting division ratio
(b15)
b7
(b8)
b0 b7
b0
Timer A0 register (Addresses 4716, 4616)
Timer A1 register (Addresses 4916, 4816)
Timer A2 register (Addresses 4B16, 4A16)
Timer A3 register (Addresses 4D16, 4C16)
Timer A4 register (Addresses 4F16, 4E16)
Can be set to “000016” to “FFFF16” (n).
Note: The counter divides the count source frequency by (n + 1).
Continue to Figure 8.3.3 on next page.
Fig. 8.3.2 Initial setting example for registers relevant to timer mode (1)
7721 Group User’s Manual
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TIMER A
8.3 Timer mode
From preceding Figure 8.3.2.
Setting interrupt priority level
b7
b0
Timer Ai interrupt control register (i = 0 to 4)
(Addresses 7516 to 7916)
Interrupt priority level select bits
When using interrupts, set these bits to one of levels
1 to 7.
When disabling interrupts, set these bits to level 0.
Setting port P5 direction register
b7
b0
Port P5 direction register (Address D16)
TA2IN pin
TA3IN pin
TA4IN pin
When gate function is selected, set the bit corresponding to the TAjIN pin to “0.”
Setting count start bit to “1.”
b7
b0
Count start register (Address 4016)
Timer A0 count start bit
Timer A1 count start bit
Timer A2 count start bit
Timer A3 count start bit
AAAA
AAAA
AAAA
Timer A4 count start bit
Count starts
Fig. 8.3.3 Initial setting example for registers relevant to timer mode (2)
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TIMER A
8.3 Timer mode
8.3.2 Count source
In the timer mode, the count source select bits (bits 6 and 7 at addresses 5616 to 5A16) select the count
source. Table 8.3.2 lists the count source frequency.
Table 8.3.2 Count source frequency
Count source
select bits
Count
source
Count source frequency
f(X IN) = 8 MHz
f(X IN) = 16 MHz
f(XIN) = 25 MHz
8 MHz
12.5 MHz
f16
4 MHz
500 kHz
1 MHz
1.5625 MHz
0
f64
125 kHz
250 kHz
390.625 kHz
1
f 512
15625 Hz
31250 Hz
48.8281 kHz
b7
b6
0
0
f2
0
1
1
1
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8–13
TIMER A
8.3 Timer mode
8.3.3 Operation in timer mode
➀ When the count start bit is set to “1,” the counter starts counting of the count source.
➁ When a counter underflow occurs, the reload register’s contents are reloaded, and counting continues.
➂ The timer Ai interrupt request bit is set to “1” at the underflow in ➁. The interrupt request bit remains
set to “1” until the interrupt request is accepted or the interrupt request bit is cleared to “0” by software.
Figure 8.3.4 shows an example of operation in the timer mode.
n = Reload register’s contents
Counter contents (Hex.)
FFFF16
Starts counting.
1 / fi ✕ (n+1)
Stops counting.
n
Restarts counting.
000016
Time
Set to “1” by software.
Cleared to “0” by software.
Set to “1” by software.
Count start bit
Timer Ai interrupt
request bit
fi = frequency of count source
(f2, f16, f64, f512)
Cleared to “0” when interrupt request is
accepted or cleared by software.
Fig. 8.3.4 Example of operation in timer mode (without pulse output and gate functions)
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7721 Group User’s Manual
TIMER A
8.3 Timer mode
8.3.4 Selectable functions
The following describes the selectable gate function for Timers A2 to A4 and pulse output function.
(1) Gate function
The gate function is selected by setting the gate function select bits (bits 4 and 3 at addresses 5816
to 5A16 ) to “102” or “112.” The gate function makes it possible to start or stop counting depending on
the TAjIN pin’s input signal. Table 8.3.3 lists the count valid levels. Figure 8.3.5 shows an example
of operation with the gate function selected.
When selecting the gate function, set the port P5 direction registers’ bits which correspond to the
TAjIN pin for the input mode. Additionally, make sure that the TAjIN pin’s input signal has a pulse width
equal to or more than two cycles of the count source.
Table 8.3.3 Count valid levels
Gate function select bits
b3
b4
0
1
Count valid level (Duration while counter counts)
While TAj IN pin’s input signal is at “L” level
While TAj IN pin’s input signal is at “H” level
1
1
Note: The counter does not count while the TAjIN pin’s input signal is not at the count valid level.
FFFF16
n = Reload register’s contents
➀ Starts counting.
Counter contents (Hex.)
n
➁ Stops counting.
000016
Set to “1” by software.
Time
Count start bit
TAjIN pin’s
input signal
Count valid
level
Invalid level
Timer Aj interrupt
request bit
➀ The counter counts when the count start bit = “1” and the TAjIN pin’s input signal is at the count valid
level.
➁ The counter stops counting while the TAjIN pin’s input signal is not at the count valid level, and the
counter value is retained.
Cleared to “0” when
interrupt request is
accepted or cleared
by software.
Fig. 8.3.5 Example of operation selecting gate function
7721 Group User’s Manual
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TIMER A
8.3 Timer mode
(2) Pulse output function
The pulse output function is selected by setting the pulse output function select bit (bit 2 at addresses
58 16 to 5A 16) to “1.” When this function is selected, the TAjOUT pin is forcibly set for the pulse output
pin regardless of the corresponding bits of the port P5 direction register. The TAj OUT pin outputs
pulses of which polarity is inverted each time a counter underflow occurs.
When the count start bit (address 4016) is “0” (count stopped), the TAjOUT pin outputs “L” level. Figure
8.3.6 shows an example of operation with the pulse output function selected.
n = Reload register’s contents
FFFF16
Counter contents (Hex.)
Starts counting.
Starts counting.
n
Restarts
counting.
000016
Time
Set to “1” by software.
Cleared to “0” by software.
Set to “1” by software.
Count start bit
Pulse output from
TAjOUT pin
Timer Aj interrupt
request bit
Cleared to “0” when interrupt request is accepted or cleared by software.
Fig. 8.3.6 Example of operation selecting pulse output function
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TIMER A
8.3 Timer mode
[Precautions for timer mode]
By reading the timer Ai register, the counter value can be read out at any timing. However, if the timer Ai
register is read at the reload timing shown in Figure 8.3.7, the value “FFFF16” is read out. If reading is
performed in the period from when a value is set into the timer Ai register with the counter stopped until
the counter starts counting, the set value is correctly read out.
Reload
Counter value
(Hex.)
2
1
0
Read value
(Hex.)
2
1
0
n
n–1
FFFF n – 1
n = Reload register’s contents
Time
Fig. 8.3.7 Reading timer Ai register
7721 Group User’s Manual
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TIMER A
8.4 Event counter mode
8.4 Event counter mode
In this mode, the timer counts an external signal. (Refer to “Tables 8.4.1 and 8.4.2.”) Timers A2 to A4 can
be used in this mode. Figure 8.4.1 shows the structures of the timer Aj mode register and timer Aj register
in the event counter mode.
Table 8.4.1 Specifications of event counter mode (when not using two-phase pulse signal processing function)
Item
Specifications
Count source
● External signal input to the TAj IN pin
Count operation
● The count source’s valid edge can be selected from the falling edge
and the rising edge by software.
● Countup or countdown can be switched by external signal or software.
● When a counter overflow or underflow occurs, reload register’s contents
are reloaded, and counting continues.
Division ratio
● For countdown
● For countup
1
(n + 1)
n : Timer Aj register’s set value
1
(FFFF 16 – n + 1)
Count start condition
When the count start bit is set to “1.”
Count stop condition
When the count start bit is cleared to “0.”
Interrupt request occurrence timing When a counter overflow or underflow occurs.
Count source input
TAj IN pin’s function
TAj OUT pin’s function
Programmable I/O port, pulse output, or countup/countdown switch signal
input
Read from timer Aj register
Counter value can be read out.
● While counting is stopped
Write to timer Aj register
When a value is written to the timer Aj register, it is written to both
of the reload register and counter.
● While counting is in progress
When a value is written to the timer Aj register, it is written only to
the reload register. (Transferred to the counter at the next reload
time.)
8–18
7721 Group User’s Manual
TIMER A
8.4 Event counter mode
Table 8.4.2 Specifications of event counter mode (when using two-phase pulse signal processing function)
Item
Specifications
Count source
External signal (two-phase pulse) input to the TAjIN or TAjOUT pin
Count operation
● Countup or countdown can be switched by external signal (twophase pulse).
Division ratio
● When a counter overflow or underflow occurs, reload register’s contents
are reloaded, and counting continues.
1
● For countdown
(n + 1) n : Timer Aj register’s set value
● For countup
Count start condition
1
(FFFF 16 – n + 1)
When the count start bit is set to “1.”
Count stop condition
When the count start bit is cleared to “0.”
Interrupt request occurrence timing When a counter overflow or underflow occurs.
TAj IN, TAj OUT pin function
Two-phase pulse input
Read from timer Aj register
Counter value can be read out.
Write to timer Aj register
● While counting is stopped
When a value is written to the timer Aj register, it is written to both
of the reload register and counter.
● While counting is in progress
When a value is written to the timer Aj register, it is written only to
the reload register. (Transferred to the counter at the next reload
time.)
7721 Group User’s Manual
8–19
TIMER A
8.4 Event counter mode
b7
b6
b5
✕ ✕ 0
b4
b3
b2
b1
b0
0 1
Timer Aj mode register (j = 2 to 4) (Addresses 5816 to 5A16)
Bit
0
Bit name
Functions
Operating mode select bits
b1 b0
0 1 : Event counter mode
1
(b8)
b0 b7
RW
0
RW
0
RW
2
Pulse output function select bit
0 : No pulse output (TAjOUT pin functions
as a programmable I/O port.)
1 : Pulse output (TAjOUT pin functions
as a pulse output pin.)
0
RW
3
Count polarity select bit
0 : Counts at falling edge of external signal
1 : Counts at rising edge of external signal
0
RW
4
Up-down switching factor select
bit
0 : Contents of up-down register
1 : Input signal to TAjOUT pin
0
RW
5
Fix this bit to “0” in event counter mode.
0
RW
6
These bits are invalid in event counter mode.
0
RW
0
RW
At reset
RW
Undefined
RW
7
(b15)
b7
At reset
b0
Timer A2 register (Addresses 4B16, 4A16)
Timer A3 register (Addresses 4D16, 4C16)
Timer A4 register (Addresses 4F16, 4E16)
Bit
Functions
15 to 0 These bits can be set to “000016” to “FFFF16.”
Assuming that the set value = n, the counter
divides the count source frequency by (n + 1)
during countdown, or by (FFFF16 – n + 1)
during countup.
When reading, the register indicates the
counter value.
Note: Read from or write to this register in a unit of 16 bits.
Fig. 8.4.1 Structures of timer Aj mode register and timer Aj register in event counter mode
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7721 Group User’s Manual
TIMER A
8.4 Event counter mode
8.4.1 Setting for event counter mode
Figures 8.4.2 and 8.4.3 show an initial setting example for registers relevant to the event counter mode.
Note that when using interrupts, set up to enable the interrupts. For details, refer to “CHAPTER 7.
INTERRUPTS.”
Selecting event counter mode and each function
b7
b0
✕ ✕ 0
0 1
Timer Aj mode register (j = 2 to 4)
(Addresses 5816 to 5A16)
Selection of event counter mode
Pulse output function select bit
0: No pulse output
1: Pulse output
Count polarity select bit
0: Counts at falling edge of external signal.
1: Counts at rising edge of external signal.
Up-down switching factor select bit
0: Contents of up-down register
1: Input signal to TAjOUT pin
✕ : It may be either “0” or “1.”
Setting up-down register
b7
b0
0 0
Up-down register (Address 4416)
Timer A2 up-down bit
Timer A3 up-down bit
Timer A4 up-down bit
Set the corresponding up-down bit when the contents of
the up-down register are selected as the up-down
switching factor.
0: Countdown
1: Countup
Timer A2 two-phase pulse signal processing select bit
Timer A3 two-phase pulse signal processing select bit
Timer A4 two-phase pulse signal processing select bit
Set the corresponding bit to “1” when the two-phase pulse
signal processing function is selected for timers A2 to A4.
0: Two-phase pulse signal processing
function disabled
1: Two-phase pulse signal processing
function enabled
Setting division ratio
(b15)
b7
(b8)
b0 b7
b0
Timer A2 register (Addresses 4B16, 4A16)
Timer A3 register (Addresses 4D16, 4C16)
Timer A4 register (Addresses 4F16, 4E16)
Can be set to “000016” to “FFFF16” (n).
✻ The counter divides the count source frequency by (n + 1)
when counting down, or by (FFFF16 – n + 1) when counting up.
Continue to Figure 8.4.3 on next page.
Fig. 8.4.2 Initial setting example for registers relevant to event counter mode (1)
7721 Group User’s Manual
8–21
TIMER A
8.4 Event counter mode
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AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAA
AAAAA
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AAA
AAA
AAA
From preceding Figure 8.4.2.
Setting interrupt priority level
b7
b0
Timer Aj interrupt control register (j = 2 to 4)
(Addresses 7716 to 7916)
Interrupt priority level select bits
When using interrupts, set these bits
to one of levels 1 to 7.
When disabling interrupts, set these
bits to level 0.
Setting port P5 direction register
b7
b0
Port P5 direction register (Address D16)
TA2OUT pin
TA2IN pin
TA3OUT pin
TA3IN pin
TA4OUT pin
TA4IN pin
Clear the bit corresponding to the TAjIN pin to “0.”
When selecting the TAjOUT pin’s input signal as the up-down switching factor, set
the bit corresponding to the TAjOUT pin to “0.”
When selecting the two-phase pulse signal processing function, set the bit
corresponding to the TAjOUT pin to “0.”
Setting the count start bit to “1”
b7
b0
Count start register
(Address 4016)
Timer A2 count start bit
Timer A3 count start bit
Timer A4 count start bit
Count starts
Fig. 8.4.3 Initial setting example for registers relevant to event counter mode (2)
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7721 Group User’s Manual
TIMER A
8.4 Event counter mode
8.4.2 Operation in event counter mode
➀ When the count start bit is set to “1,” the counter starts counting of the count source’s valid edges.
➁ When a counter underflow or overflow occurs, the reload register’s contents are reloaded, and counting
continues.
➂ The timer Aj interrupt request bit is set to “1” at the underflow or overflow in ➁.
The interrupt request bit remains set to “1” until the interrupt request is accepted or the interrupt request
bit is cleared to “0” by software.
Figure 8.4.4 shows an example of operation in the event counter mode.
n = Reload register’s contents
FFFF16
Counter contents (Hex.)
Starts counting.
n
000016
Time
Set to “1” by software.
Count start bit
Set to “1” by software.
Up-down bit
Timer Aj interrupt
request bit
Cleared to “0” when interrupt request is accepted or cleared by software.
Note: The above applies when the up-down bit’s contents are selected as the up-down switching factor (i.e., up-down
switching factor select bit = “0” ).
Fig. 8.4.4 Example of operation in event counter mode (without pulse output and two-phase pulse
signal processing functions)
7721 Group User’s Manual
8–23
TIMER A
8.4 Event counter mode
8.4.3 Switching between countup and countdown
The up-down register (address 4416) or the input signal from the TAjOUT pin is used to switch countup from
and to countdown. This switching is performed by the up-down bit when the up-down switching factor select
bit (bit 4 at addresses 5816 to 5A 16) is “0,” and by the input signal from the TAjOUT pin when the up-down
switching factor select bit is “1.”
When the switching between countup and countdown is set while counting is in progress, this switching is
actually performed when the count source’s next valid edge is input.
(1) Switching by up-down bit
Countdown is performed when the up-down bit is “0,” and countup is performed when the up-down
bit is “1.” Figure 8.4.5 shows the structure of the up-down register.
(2) Switching by TAj OUT pin’s input signal
Countdown is performed when the TAjOUT pin’s input signal is at “L” level, and countup is performed
when the TAj OUT pin’s input signal is at “H” level.
When using the TAjOUT pin’s input signal to switch countup from and to countdown, set the port P5
direction register’s bit which corresponds to the TAj OUT pin for the input mode.
b7
b6
b5
b4
b3
b2
b1
b0
0 0
Up-down register (Address 4416)
Bit
0
Functions
Bit name
Fix these bits to “0.”
1
0 : Countdown
1 : Countup
This function is valid when the contents of
the up-down register is selected as the updown switching factor.
2
Timer A2 up-down bit
3
Timer A3 up-down bit
4
Timer A4 up-down bit
5
Timer A2 two-phase pulse signal 0 : Two-phase pulse signal
processing function disabled
processing select bit
(Note)
1 : Two-phase pulse signal
processing function enabled
Timer A3 two-phase pulse signal
6
processing select bit
7
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
WO
0
WO
0
WO
(Note)
When not using the two-phase pulse
signal processing function, set the bit
Timer A4 two-phase pulse signal
to “0.”
processing select bit (Note)
The value is “0” at reading.
Note: Use the LDM or STA instruction for writing to bits 5 to 7.
Fig. 8.4.5 Structure of up-down register
8–24
At reset
7721 Group User’s Manual
TIMER A
8.4 Event counter mode
8.4.4 Selectable functions
The following describes the selectable pulse output, and two-phase pulse signal processing functions.
(1) Pulse output function
The pulse output function is selected by setting the pulse output function select bit (bit 2 at addresses
5816 to 5A16) to “1.” When this function is selected, the TAjOUT pin is forcibly set for the pulse output
pin regardless of the corresponding bit of the port P5 direction register. The TAjOUT pin outputs pulses
of which polarity is inverted each time a counter underflow or overflow occurs. (Refer to “Figure
8.3.6.”)
When the count start bit (address 40 16) is “0” (count stopped), the TAj OUT pin outputs “L” level.
7721 Group User’s Manual
8–25
TIMER A
8.4 Event counter mode
(2) Two-phase pulse signal processing function
The two-phase pulse signal processing function is selected by setting the two-phase pulse signal
processing select bits (bits 5 to 7 at address 44 16) to “1.” (Refer to “Figure 8.4.5.”) Figure 8.4.6
shows the timer Aj mode registers when the two-phase pulse signal processing function is selected.
For timers with the two-phase pulse signal processing function selected, the timer counts two kinds
of pulses of which phases differ by 90 degrees. There are two types of the two-phase pulse signal
processing: normal processing and quadruple processing. In Timers A2 and A3, normal processing
is performed; in timer A4, quadruple processing is performed.
For some bits of the port P5 direction register correspond to pins used for two-phase pulse input, set
these bits for the input mode.
b7
b6
b5
b4
b3
b2
b1
b0
✕ ✕ 0 1 0 0 0 1
Timer A2 mode register (Address 5816)
Timer A3 mode register (Address 5916)
Timer A4 mode register (Address 5A16)
✕ : It may be either “0” or “1.”
Fig. 8.4.6 Timer Aj mode registers when two-phase pulse signal processing function is selected
●Normal processing
Countup is performed at the rising edges input to the TAkIN pin when the phase has the relationship
that the TAkIN pin’s input signal level goes from “L” to “H” while the TAkOUT (k = 2 and 3) pin’s input
signal is at “H” level.
Countdown is performed at the falling edges input to the TAk IN pin when the phase has the
relationship that the TAkIN pin’s input signal level goes from “H” to “L” while the TAkOUT pin’s input
signal is at “H” level. (Refer to “Figure 8.4.7.”)
TAkOUT
TAkIN
(k=2, 3)
Counted
Up
up
count
Counted
up
Counted
up
Counted
down
Counted
down
+1
+1
+1
–1
–1
Fig. 8.4.7 Normal processing
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7721 Group User’s Manual
Counted
down
–1
TIMER A
8.4 Event counter mode
●Quadruple processing
Countup is performed at all rising and falling edges input to the TA4OUT and TA4IN pins when the
phase has the relationship that the TA4IN pin’s input signal level goes from “L” to “H” while the
TA4OUT pin’s input signal is at “H” level.
Countdown is performed at all rising and falling edges input to the TA4 OUT and TA4IN pins when
the phase has the relationship that the TA4IN pin’s input signal level goes from “H” to “L” while the
TA4 OUT pin’s input signal is at “H” level. (Refer to “Figure 8.4.8.”)
Table 8.4.3 lists the relationship between the input signals to the TA4OUT and TA4IN pins and count
operation when the quadruple processing is selected.
TA4OUT
Counted up at all edges
+1
+1
+1
+1
Counted down at all edges
–1
+1
–1
–1
–1
–1
TA4IN
Counted up at all edges
+1
+1
+1
+1
+1
Counted down at all edges
–1
–1
–1
–1
–1
Fig. 8.4.8 Quadruple processing
Table 8.4.3 Relationship between input signals to TA4OUT
and TA4 IN pins and count operation when
quadruple processing is selected
Input signal to TA4OUT pin Input signal to TA4IN pin
Up-count
Down-count
“H” level
“L” level
Rising edge
Falling edge
“H” level
“L” level
Rising edge
Falling edge
Rising edge
Falling edge
“L” level
“H” level
Falling edge
Rising edge
“H” level
“L” level
7721 Group User’s Manual
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TIMER A
8.4 Event counter mode
[Precautions for event counter mode]
1. While counting is in progress, by reading the timer Aj register, the counter value can be read out at any
timing. However, if the timer Aj register is read at the reload timing shown in Figure 8.4.9, the value
“FFFF16” (at an underflow) or “000016 ” (at an overflow) is read out. If reading is performed in the period
from when a value is set into the timer Aj register with the counter stopped until the counter starts
counting, the set value is correctly read out.
(1) For countdown
(2) For countup
Reload
Reload
Counter value
(Hex.)
2
1
0
Read value
(Hex.)
2
1
0
n
n–1
FFFF n – 1
Counter value
(Hex.)
Read value
(Hex.)
FFFD FFFE FFFF
n+1
FFFD FFFE FFFF 0000 n + 1
Time
n = Reload register’s contents
n
Time
n = Reload register’s contents
Fig. 8.4.9 Reading timer Aj register
2. The TAjOUT pin is used for all functions listed below. Accordingly, only one of these functions can be
selected for each timer.
•Switching between countup and countdown by TAj OUT pin’s input signal
•Pulse output function
•Two-phase pulse signal processing function
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7721 Group User’s Manual
TIMER A
8.5 One-shot pulse mode
8.5 One-shot pulse mode
In this mode, the timer outputs a pulse which has an arbitrary width once. (Refer to “Table 8.5.1.”) Timers
A2 to A4 can be used in this mode. When a trigger occurs, the timer outputs “H” level from the TAjOUT pin
for an arbitrary time. Figure 8.5.1 shows the structures of the timer Aj mode register and timer Aj register
in the one-shot pulse mode.
Table 8.5.1 Specifications of one-shot pulse mode
Item
Count source
Count operation
Output pulse width (“H”)
Specifications
f 2 , f16, f 64, or f512
● Countdown
● When the counter value becomes “000016 ,” reload register’s contents are reloaded, and counting stops.
● If a trigger occurs during counting, reload register’s contents are
reloaded, and counting continues.
n
fi
[S]
n : Timer Aj register’s set value
● When a trigger occurs. (Note)
● Internal or external trigger can be selected by software.
,
● When the counter value becomes “0000 16 ”
Count stop condition
● When the count start bit is cleared to “0”
Interrupt request occurrence timing When counting stops.
Programmable I/O port or trigger input
TAj IN pin’s function
One-shot pulse output
TAj OUT pin’s function
An undefined value is read out.
Read from timer Aj register
● While counting is stopped
Write to timer Aj register
When a value is written to the timer Aj register, it is written to both
of the reload register and counter.
● While counting is in progress
When a value is written to the timer Aj register, it is written only to
the reload register. (Transferred to the counter at the next reload
time.)
Note: The trigger is generated with the count start bit = “1.”
Count start condition
7721 Group User’s Manual
8–29
TIMER A
8.5 One-shot pulse mode
b7
b6
b5
0
b4
b3
b2
b1
b0
1 1 0
Timer Aj mode register (j = 2 to 4) (Addresses 5816 to 5A16)
Bit
0
Bit name
Functions
Operating mode select bits
b1 b0
1 0 : One-shot pulse mode
1 @
2
3
Fix this bit to “1” in one-shot pulse mode.
b4 b3
Trigger select bits
0 0 : Writing “1” to one-shot start register
0 1 : (TAjIN pin functions as a programmable I/O port.)
1 0 : Falling edge of TAjIN pin’s input signal
1 1 : Rising edge of TAjIN pin’s input signal
4
5
6
Fix this bit to “0” in one-shot pulse mode.
Count source select bits
7
(b15)
b7
(b8)
b0 b7
b7 b6
0 0 : f2
0 1 : f16
1 0 : f64
1 1 : f512
At reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
b0
Timer A2 register (Addresses 4B16, 4A16)
Timer A3 register (Addresses 4D16, 4C16)
Timer A4 register (Addresses 4F16, 4E16)
Bit
Functions
15 to 0 These bits can be set to “000116” to “FFFF16.”
Assuming that the set value = n, the “H” level
width of the one-shot pulse output from the
TAjOUT pin is expressed as follows : n
fi.
At reset
RW
Undefined
WO
fi: Frequency of count source (f2, f16, f64, or f512)
Note: Use the LDM or STA instruction for writing to this register.
Read from or write to this register in a unit of 16 bits.
Fig. 8.5.1 Structures of timer Aj mode register and timer Aj register in one-shot pulse mode
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7721 Group User’s Manual
TIMER A
8.5 One-shot pulse mode
8.5.1 Setting for one-shot pulse mode
Figures 8.5.2 and 8.5.3 show an initial setting example for registers relevant to the one-shot pulse mode.
Note that when using interrupts, set up to enable the interrupts. For details, refer to “CHAPTER 7.
INTERRUPTS.”
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AAAAAAAAAAAAAA
Selecting one-shot pulse mode and each function
b7
b0
0
1 1 0
Timer Aj mode register (j = 2 to 4) (Addresses 5816 to 5A16)
Selection of one-shot pulse mode
Trigger select bits
b4 b3
00:
Writing “1” to one-shot start bit: Internal trigger
01:
1 0 : Falling edge of TAjIN pin’s input signal: External trigger
1 1 : Rising edge of TAjIN pin’s input signal: External trigger
Count source select bits
b7 b6
0 0 : f2
0 1 : f16
1 0 : f64
1 1 : f512
Setting “H” level width of one-shot pulse
(b15)
b7
(b8)
b0 b7
b0
Timer A2 register (Addresses 4B16, 4A16)
Timer A3 register (Addresses 4D16, 4C16)
Timer A4 register (Addresses 4F16, 4E16)
Can be set to “000116” to “FFFF16” (n).
n
fi
fi: Frequency of count source
Note. “H” level width =
Setting interrupt priority level
b7
b0
Timer Aj interrupt control register (j = 2 to 4)
(Addresses 7716 to 7916)
Interrupt priority level select bits
When using interrupts, set these bits to one of levels 1 to 7.
When disabling interrupts, set these bits to level 0.
Continue to Figure 8.5.3.
Fig. 8.5.2 Initial setting example for registers relevant to one-shot pulse mode (1)
7721 Group User’s Manual
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TIMER A
8.5 One-shot pulse mode
From preceding Figure 8.5.2.
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AA
A
AA
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AAAAAAAAAA
AA
A
AA
AAAAAAAAAA
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AAAAA
AAAAA
AAA
AAA
AAA
When external trigger
is selected
When internal trigger
is selected
Setting port P5 direction register
b7
Setting count start bit to “1”
b0
Port P5 direction register
(Address D16)
b7
b0
Count start register (Address 4016)
Timer A2 count start bit
TA2IN pin
TA3IN pin
TA4IN pin
Timer A3 count start bit
Timer A4 count start bit
Set the corresponding bit to “0.”
Setting count start bit to “1”
Setting one-shot start bit to “1”
b7
b7
b0
Count start register (Address 4016)
b0
0 0
One-shot start register (Address
4216)
Timer A2 one-shot start bit
Timer A3 one-shot start bit
Timer A4 one-shot start bit
Timer A2 count start bit
Timer A3 count start bit
Timer A4 count start bit
Trigger input to TAjIN pin
Trigger generated
Count starts
Fig. 8.5.3 Initial setting example for registers relevant to one-shot pulse mode (2)
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7721 Group User’s Manual
TIMER A
8.5 One-shot pulse mode
8.5.2 Count source
In the one-shot pulse mode, the count source select bits (bits 6 and 7 at addresses 5816 to 5A 16) select
the count source. Table 8.5.2 lists the count source frequency.
Table 8.5.2 Count source frequency
Count source
select bits
Count source frequency
f2
f(X IN) = 8 MHz
4 MHz
f(X IN) = 16 MHz
8 MHz
f(X IN) = 25 MHz
12.5 MHz
f 16
500 kHz
1 MHz
1.5625 MHz
0
f 64
125 kHz
250 kHz
390.625 kHz
1
f 512
15625 Hz
31250 Hz
48.8281 kHz
b7
b6
0
0
1
1
1
0
Count
source
7721 Group User’s Manual
8–33
TIMER A
8.5 One-shot pulse mode
8.5.3 Trigger
The counter is enabled for counting when the count start bit (address 40 16) is set to “1.” The counter starts
counting when a trigger is generated after counting has been enabled. An internal or external trigger can
be selected as that trigger.
An internal trigger is selected when the trigger select bits (bits 4 and 3 at addresses 58 16 to 5A 16) are “00 2”
or “012”; an external trigger is selected when the bits are “102” or “11 2.”
If a trigger is generated during counting, the reload register’s contents are reloaded and the counter
continues counting. If generating a trigger during counting, make sure that a certain time which is equivalent
to one cycle of the timer’s count source or more has passed between the previously generated trigger and
a new trigger.
(1) When selecting internal trigger
A trigger is generated when writing “1” to the one-shot start bit (bits 2 to 4 at address 42 16). Figure
8.5.4 shows the structure of the one-shot start register.
(2) When selecting external trigger
A trigger is generated at the falling edge of the TAjIN pin’s input signal when bit 3 at addresses 5816
to 5A 16 is “0,” or at its rising edge when bit 3 is “1.”
When using an external trigger, set the port P5 direction registers’ bits which correspond to the TAjIN
pins for the input mode.
b7
b6
b5
b4
b3
b2
b1
b0
0 0
.
One-shot start register (Address 4216)
Bit
0
Bit name
Functions
Fix these bits to “0.” The value is “0” at reading.
1
2
Timer A2 one-shot start bit
3
Timer A3 one-shot start bit
4
Timer A4 one-shot start bit
1 : Start outputting one-shot pulse
(valid when internal trigger is
selected.)
The value is “0” at reading.
7 to 5 Nothing is assigned.
Fig. 8.5.4 Structure of one-shot start register
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7721 Group User’s Manual
At reset
RW
0
WO
0
WO
0
WO
0
WO
0
WO
Undefined
–
TIMER A
8.5 One-shot pulse mode
8.5.4 Operation in one-shot pulse mode
➀ When the one-shot pulse mode is selected with the operating mode select bits, the TAj OUT pin outputs
“L” level.
➁ When the count start bit is set to “1,” the counter is enabled for counting. After that, counting starts when
a trigger is generated.
➂ When the counter starts counting, the TAj OUT pin outputs “H” level.
➃ When the counter value becomes “000016,” the output from the TAjOUT pin becomes “L” level. Additionally,
the reload register’s contents are reloaded and the counter stops counting there.
➄ Simultaneously with ➃, the timer Aj interrupt request bit is set to “1.”
This interrupt request bit remains set to “1” until the interrupt request is accepted or the interrupt request
bit is cleared to “0” by software.
Figure 8.5.5 shows an example of operation in the one-shot pulse mode.
When a trigger is generated after ➃ above, the counter and TAj OUT pin perform the same operations
beginning from ➁ again. Furthermore, if a trigger is generated during counting, the counter performs
countdown once after this new trigger is generated, and it continues counting with the reload register’s
contents reloaded. If generating a trigger during counting, make sure that a certain time which is equivalent
to one cycle of the timer’s count source or more has passed between the previously generated trigger and
a new trigger.
The one-shot pulse output from the TAjOUT pin can be disabled by clearing the timer Aj mode register’s bit
2 to “0.” Accordingly, Timer Aj can be also used as an internal one-shot timer that does not perform the
pulse output. In this case, the TAjOUT pin functions as a programmable I/O port.
7721 Group User’s Manual
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TIMER A
8.5 One-shot pulse mode
Counter contents (Hex.)
FFFF16
n = Reload register’s contents
Starts counting.
Stops
counting.
Stops counting.
Starts counting.
n
Reloaded
Reloaded
000116
Time
Set to “1” by software.
➀ Count start bit
➁ Trigger during counting
TAjIN pin
input signal
1 / fi ✕ (n)
1 / fi ✕ (n+1)
One-shot pulse
output from
TAjOUT pin
Timer Aj interrupt
request bit
fi = Frequency of count source
(f2, f16, f64, or f512)
Cleared to “0” when interrupt request is accepted
or cleared by software.
➀ When the count start bit = “0” (counting stopped), the TAjOUT pin outputs “L” level.
➁ When a trigger is generated during counting, the counter counts the count source (n + 1) times after a new trigger is generated.
Note: The above applies when an external trigger (rising of TAjIN pin’s input signal) is selected.
Fig. 8.5.5 Example of operation in one-shot pulse mode (selecting external trigger)
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7721 Group User’s Manual
TIMER A
8.5 One-shot pulse mode
[Precautions for one-shot pulse mode]
1. If the
•The
•The
•The
count start bit is cleared to “0” during counting, the counter becomes as follows:
counter stops counting, and the reload register’s contents are reloaded into the counter.
TAjOUT pin’s output level becomes “L.”
timer Aj interrupt request bit is set to “1.”
2. A one-shot pulse is output synchronously with an internally generated count source. Accordingly, when
selecting an external trigger, there will be a delay equivalent to one cycle of the count source at maximum
from when a trigger is input to the TAjIN pin until a one-shot pulse is output.
Trigger input
TAjIN pin’s
input signal
Count
source
One-shot pulse
output from
TAjOUT pin
Starts outputting of one-shot pulse
Note: The above applies when an external trigger (falling edge of TAjIN pin’s input signal) is selected.
Fig. 8.5.6 Output delay in one-shot pulse output
3. When the timer’s operating mode is set by one of the following procedures, the timer Aj interrupt request
bit is set to “1.”
●When the one-shot pulse mode is selected after reset
●When the operating mode is switched from the timer mode to the one-shot pulse mode
●When the operating mode is switched from the event counter mode to the one-shot pulse mode
Accordingly, when using the timer Aj interrupt (interrupt request bit), be sure to clear the timer Aj interrupt
request bit to “0” after the above setting.
4. Don not set “0000 16 ” to the timer Aj register.
7721 Group User’s Manual
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TIMER A
8.6 Pulse width modulation (PWM) mode
8.6 Pulse width modulation (PWM) mode
In this mode, the timer continuously outputs pulses which have an arbitrary width. (Refer to “Table 8.6.1.”)
Timers A2 to A4 can be used in this mode. Figure 8.6.1 shows the structures of the timer Aj mode registers
and timer Aj registers in the PWM mode.
Table 8.6.1 Specifications of PWM mode
Specifications
Item
f 2, f 16, f 64, or f 512
Count source
● Countdown (operating as an 8-bit or 16-bit pulse width modulator)
Count operation
● Reload register’s contents are reloaded at rising edge of PWM pulse,
and counting continues.
● A trigger generated during counting does not affect the counting.
PWM period/“H” level width
Count start condition
Count stop condition
<16-bit pulse width modulator>
(2 16–1)
[s]
Period =
n : Timer Aj register’s set value
fi
n
[s]
“H” level width =
fi
<8-bit pulse width modulator>
m : Timer Aj register low-order 8 bits’
(m + 1)(2 8–1)
set value
[s]
Period =
fi
n
:
Timer
Aj register high-order 8
n(m + 1)
“H” level width =
[s]
bits’
set
value
fi
● When a trigger is generated. (Note)
● Internal or external trigger can be selected by software.
When the count start bit is cleared to “0.”
Interrupt request occurrence timing At falling edge of PWM pulse
Programmable I/O port or trigger input
TAj IN pin’s function
TAj OUT pin’s function
Read from timer Aj register
PWM pulse output
An undefined value is read out.
Write to timer Aj register
● While counting is stopped
When a value is written to the timer Aj register, it is written to both
of the reload register and counter.
● While counting is in progress
When a value is written to the timer Aj register, it is written only to
the reload register. (Transferred to the counter at the next reload
time.)
Note: The trigger is generated with the count start bit = “1.”
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TIMER A
8.6 Pulse width modulation (PWM) mode
b7
b6
b5
b4
b3
b2
b1
b0
1 1 1
Timer Aj mode register (j = 2 to 4) (Addresses 5816 to 5A16)
Bit
0
Functions
Bit name
At reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
b1 b0
Operating mode select bits
1 1 : PWM mode
1
2
3
Fix this bit to “1” in PWM mode.
b4 b3
Trigger select bits
0 0 : Writing “1” to count start register
0 1 : (TAj IN pin functions as a programmable I/O port.)
1 0 : Falling edge of TAjIN pin’s input signal
1 1 : Rising edge of TAjIN pin’s input signal
4
5
16/8-bit PWM mode select bit
0 : 16-bit pulse width modulator
1 : 8-bit pulse width modulator
0
RW
6
Count source select bits
b7 b6
0
RW
0
RW
0 0 : f2
0 1 : f16
1 0 : f64
1 1 : f512
7
<When operating as a 16-bit pulse width modulator>
(b15)
b7
(b8)
b0 b7
b0
Timer A2 register (Addresses 4B16, 4A16)
Timer A3 register (Addresses 4D16, 4C16)
Timer A4 register (Addresses 4F16, 4E16)
Bit
Functions
At reset
RW
15 to 0 These bits can be set to “000016” to “FFFE16.” Undefined WO
Assuming that the set value = n, the “H” level
width of the PWM pulse output from the
n
TAjOUT pin is expressed as follows:
fi
16 – 1
n
(PWM pulse period =
fi
fi: Frequency of count source (f2, f16, f64, or f512)
Note: Use the LDM or STA instruction for writing to this register.
Read from or write to this register in a unit of 16 bits.
)
<When operating as an 8-bit pulse width modulator>
(b15)
b7
(b8)
b0 b7
b0
Timer A2 register (Addresses 4B16, 4A16)
Timer A3 register (Addresses 4D16, 4C16)
Timer A4 register (Addresses 4F16, 4E16)
Functions
Bit
At reset
RW
7 to 0 These bits can be set to “0016” to “FF16.”
Assuming that the set value = m, PWM
pulse’s period output from the TAjOUT pin is
8
expressed as follows: (m + 1)(2 – 1)
fi
Undefined
WO
15 to 8 These bits can be set to “0016” to “FE16.”
Assuming that the set value = n, the “H” level
width of the PWM pulse output from the
TAjOUT pin is expressed as follows:
n(m + 1)
Undefined
WO
fi
fi: Frequency of count source (f2, f16, f64, or f512)
Note: Use the LDM or STA instruction for writing to this register.
Read from or write to this register in a unit of 16 bits.
Fig. 8.6.1 Structures of timer Aj mode registers and timer Aj registers in PWM mode
7721 Group User’s Manual
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TIMER A
8.6 Pulse width modulation (PWM) mode
8.6.1 Setting for PWM mode
Figures 8.6.2 and 8.6.3 show an initial setting example for registers relevant to the PWM mode.
Note that when using interrupts, set up to enable the interrupts. For details, refer to “CHAPTER 7.
INTERRUPTS.”
Selecting PWM mode and each function
b7
b0
1 1 1
Timer Aj mode register (j = 2 to 4) (Addresses 5816 to 5A16)
Selection of PWM mode
Trigger select bits
b4 b3
00:
0 1 : Writing “1” to count start bit: Internal trigger
1 0 : Falling edge of TAjIN pin’s input signal : External trigger
1 1 : Rising edge of TAjIN pin’s input signal : External trigger
16/8-bit PWM mode select bit
0 : Operates as 16-bit pulse width modulator
1 : Operates as 8-bit pulse width modulator
Count source select bits
b7 b6
0 0 : f2
0 1 : f16
1 0 : f64
1 1 : f512
Setting PWM pulse’s period and “H” level width
● When operating as 16-bit pulse width modulator
(b15)
b7
(b8)
b0 b7
b0
Timer A2 register (Addresses 4B16, 4A16)
Timer A3 register (Addresses 4D16, 4C16)
Timer A4 register (Addresses 4F16, 4E16)
Can be set to “000016” to “FFFE16” (n)
● When operating as 8-bit pulse width modulator
(b15)
b7
(b8)
b0 b7
b0
Timer A2 register (Addresses 4B16, 4A16)
Timer A3 register (Addresses 4D16, 4C16)
Timer A4 register (Addresses 4F16, 4E16)
Can be set to “0016” to “FF16” (m)
Can be set to “0016” to “FE16” (n)
Note: When operating as 8-bit pulse width modulator
Period =
(m+1) (28 –1 )
Note: When operating as 16-bit pulse width modulator
Period =
fi
“H” level width =
216 – 1
fi
“H” level width =
n(m+1)
fi
fi : Frequency of count source
n
fi
fi : Frequency of count source
However, if n = “0016”, the pulse width modulator
does not operate and the TAjOUT pin outputs “L”
level. At this time, no timer Aj interrupt request
occurs.
However, if n = “000016”, the pulse width modulator does
not operate and the TAjOUT pin outputs “L” level. At this time,
no timer Aj interrupt request occurs.
Continue to Figure 8.6.3.
Fig. 8.6.2 Initial setting example for registers relevant to PWM mode (1)
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7721 Group User’s Manual
TIMER A
8.6 Pulse width modulation (PWM) mode
AAAAAAAAAAAAA
AAAAAAAAAAAAA
AA
AA
AAAAAAAAAAAAA
AA
AA
AAAAAAAAAAAAA
AAAAAAAAAAAAA
AAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAA
AAAA
From preceding Figure 8.6.2.
Setting interrupt priority level
b7
b0
Timer Aj interrupt control register (j = 2 to 4)
(Addresses 7716 to 7916)
Interrupt priority level select bits
When using interrupts, set these bits to one of
levels 1 to 7.
When disabling interrupts, set these bits to
level 0.
When external trigger is selected
When internal trigger is selected
Setting port P5 direction register
b7
Setting count start bit to “1”
b0
b7
Port P5 direction register
(Address D16)
b0
Count start register (Address 4016)
TA2IN pin
TA3IN pin
TA4IN pin
Timer A2 count start bit
Timer A3 count start bit
Timer A4 count start bit
Clear the corresponding bit to “0.”
Setting count start bit to “1”
b7
b0
Count start register (Address 4016)
Timer A2 count start bit
Timer A3 count start bit
Timer A4 count start bit
Trigger input
to TAjIN pin
AAA
AAA
Trigger generated
Count
t t
Fig. 8.6.3 Initial setting example for registers relevant to PWM mode (2)
7721 Group User’s Manual
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TIMER A
8.6 Pulse width modulation (PWM) mode
8.6.2 Count source
In the PWM mode, the count source select bits (bits 6 and 7 at addresses 5816 to 5A16 ) select the count
source. Table 8.6.2 lists the count source frequency.
Table 8.6.2 Count source frequency
Count source
select bits
Count
source
Count source frequency
f(X IN) = 8 MHz
0
b6
0
f2
4 MHz
f(X IN) = 16 MHz
8 MHz
f(X IN) = 25 MHz
12.5 MHz
0
1
f 16
500 kHz
1 MHz
1.5625 MHz
1
1
0
f 64
125 kHz
250 kHz
390.625 kHz
1
f 512
15625 Hz
31250 Hz
48.8281 kHz
b7
8.6.3 Trigger
When a trigger is generated, the TAjOUT pin starts outputting PWM pulses. An internal or an external trigger
can be selected as that trigger.
An internal trigger is selected when the trigger select bits (bits 4 and 3 at addresses 58 16 to 5A 16) are “002”
or “01 2”; an external trigger is selected when the bits are “102” or “112.”
A trigger generated during outputting of PWM pulses is invalid and it does not affect the pulse output
operation.
(1) When selecting internal trigger
A trigger is generated when “1” is written to the count start bit (address 4016).
(2) When selecting external trigger
A trigger is generated at the falling edge of the TAjIN pin’s input signal when bit 3 at addresses 5816
to 5A16 is “0,” or at its rising edge when bit 3 is “1.” However, the trigger input is accepted only when
the count start bit is “1.”
When using an external trigger, set the port P5 direction registers’ bits which correspond to the TAjIN
pins for the input mode.
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7721 Group User’s Manual
TIMER A
8.6 Pulse width modulation (PWM) mode
8.6.4 Operation in PWM mode
➀ When the PWM mode is selected with the operating mode select bits, the TAjOUT pin outputs “L” level.
➁ When a trigger is generated, the counter (pulse width modulator) starts counting and the TAjOUT pin
outputs a PWM pulse (Notes 1 and 2).
➂ The timer Aj interrupt request bit is set to “1” each time the PWM pulse level goes from “H” to “L.”
The interrupt request bit remains set to “1” until the interrupt request is accepted or the interrupt request
bit is cleared to “0” by software.
➃ Each time a PWM pulse has been output for one period, the reload register’s contents are reloaded and
the counter continues counting.
The following explains operations of the pulse width modulator.
(1) 16-bit pulse width modulator
When the 16/8-bit PWM mode select bit is set to “0,” the counter operates as a 16-bit pulse width
modulator. Figures 8.6.4 and 8.6.5 show operation examples of the 16-bit pulse width modulator.
(2) 8-bit pulse width modulator
When the 16/8-bit PWM mode select bit is set to “1,” the counter is divided into 8-bit halves. Then,
the high-order 8 bits operate as an 8-bit pulse width modulator, and the low-order 8 bits operate as
an 8-bit prescaler. Figures 8.6.6 and 8.6.7 show operation examples of the 8-bit pulse width modulator.
Notes 1: If a value “0000 16” is set into the timer Aj register when the counter operates as a 16-bit
pulse width modulator, the pulse width modulator does not operate and the output from the
TAjOUT pin remains “L” level. The timer Aj interrupt request does not occur. Similarly, if a
value “00 16” is set into the high-order 8 bits of the timer Aj register when the counter
operates as an 8-bit pulse width modulator, the same is performed.
2: When the counter operates as an 8-bit pulse width modulator, after a trigger is generated,
the TAjOUT pin outputs “L” level which has the same width as “H” level width of the PWM
pulse, which was set. After that, the PWM pulse output starts from the TAjOUT pin.
7721 Group User’s Manual
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TIMER A
8.6 Pulse width modulation (PWM) mode
1 / fi ✕ (216 – 1)
Count source
TAjIN pin’s input signal
Trigger is not generated by this signal.
1 / fi ✕ (n)
PWM pulse output
from TAjOUT pin
Timer Aj interrupt
request bit
fi: Frequency of count source
(f2, f16, f64, or f512)
Cleared to “0” when interrupt request is accepted
or cleared by software.
Note: The above applies when reload register (n) = “000316” and an external trigger (rising edge of
TAjIN pin’s input signal) is selected.
Fig. 8.6.4 Operation example of 16-bit pulse width modulator
n = Reload register’s contents
Counter contents (Hex.)
(1 / fi) ✕ (216 –1)
(1 / fi) ✕ (2 16–1)
(1 / fi) ✕ (216 –1)
FFFE16
200016
(216 –1) – n
n
000116
Stops
counting.
Restarts counting.
Time
TAjIN pin’s
input signal
➀
PWM pulse
output from
TAjOUT pin
fi: Frequency of count source
(f2, f16, f64, or f512)
“FFFE16” is set to timer Aj
register.
“000016” is set to timer Aj
register.
“200016” is set to timer Aj
register.
➀ When an arbitrary value is set to the timer Aj register after setting “000016” to it, the timing at which the PWM pulse goes “H”
depends on the timing at which the new value is set.
Note: The above applies when an external trigger (rising edge of TAjIN pin’s input signal) is selected.
Fig. 8.6.5 Operation example of 16-bit pulse width modulator (when counter value is updated during
pulse output)
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7721 Group User’s Manual
TIMER A
8.6 Pulse width modulation (PWM) mode
1 / fi ✕ (m+1) ✕ (28 –1)
➀ Count source
TAjIN pin’s
input signal
1 / fi ✕ (m+1)
➁ 8-bit prescaler’s
underflow signal
1 / fi ✕ (m+1) ✕ (n)
PWM pulse output
from TAjOUT pin
Timer Aj interrupt
request bit
fi: Frequency of count source
(f2, f16, f64, or f512)
Cleared to “0” when interrupt request is accepted or cleared by software.
➀ The 8-bit prescaler counts the count source.
➁ The 8-bit pulse width modulator counts the 8-bit prescaler’s underflow signal.
Note: The above applies when the reload register’s high-order 8 bits (n) = “0216”
and low-order 8 bits (m) = “0216” and an external trigger (falling edge of TAjIN pin
input signal) is selected.
Fig. 8.6.6 Operation example of 8-bit pulse width modulator
7721 Group User’s Manual
8–45
Prescaler's
contents (Hex.)
7721 Group User’s Manual
0116
0416
0A16
0016
0216
“040216” is set to timer Aj register.
Restarts
counting.
(1 / fi) ✕ (m + 1) ✕ (28 –1)
“0A0216” is set to timer Aj register.
➀
Stops
counting.
m: Contents of reload register’s low-order 8 bits
“000216” is set to timer Aj register.
(1 / fi) ✕ (m+1) ✕ (28 –1)
Note: The above applies when an external trigger (falling edge of TAjIN pin’s input signal) is selected.
➀ When an arbitrary value is set to the timer Aj register after setting “0016” to it, the timing at which the PWM pulse level goes “H” depends on the timing at which the new value is set.
fi: Frequency of count source (f2, f16, f64, or f512)
PWM pulse output
from TAjOUT pin
Counter’s contents (Hex.)
8–46
TAjIN pin’s input
signal
Count source
(1 / fi) ✕ (m+1) ✕ (28 –1)
Time
Time
TIMER A
8.6 Pulse width modulation (PWM) mode
Fig. 8.6.7 Operation example of 8-bit pulse width modulator (when counter value is updated during
pulse output)
TIMER A
8.6 Pulse width modulation (PWM) mode
[Precautions for PWM mode]
1. If the count start bit is cleared to “0” while outputting PWM pulses, the counter stops counting. When the
TAj OUT pin was outputting “H” level at that time, the output level becomes “L” and the timer Aj interrupt
request bit is set to “1.” When the TAjOUT pin was outputting “L” level, the output level does not change
and a timer Aj interrupt request does not occur.
2. When the timer’s operating mode is set by one of the following procedures, the timer Aj interrupt request
bit is set to “1.”
●When the PWM mode is selected after reset
●When the operating mode is switched from the timer mode to the PWM mode
●When the operating mode is switched from the event counter mode to the PWM mode
Accordingly, when using the timer Aj interrupt (interrupt request bit), be sure to clear the timer Aj interrupt
request bit to “0” after the above setting.
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TIMER A
8.6 Pulse width modulation (PWM) mode
MEMORANDUM
8–48
7721 Group User’s Manual
CHAPTER 9
TIMER B
9.1 Overview
9.2 Block description
9.3 Timer mode
[Precautions for timer mode]
9.4 Event counter mode
[Precautions for event counter mode]
9.5 Pulse period/Pulse width measurement mode
[Precautions for pulse period/pulse
width measurement (PWM) mode]
TIMER B
9.1 Overview 9.2 Block description
9.1 Overview
Timer B consists of three counters, Timers B0 to B2, each equipped with a 16-bit reload function. Timers
B0 to B2 operate independently of one another.
Timer B has three operating modes listed below. Timers B0 and B1 have selective three operating modes
listed below. Timer B2 operates only in the timer mode.
(1) Timer mode (Timers B0 to B2)
The timer counts an internally generated count source.
(2) Event counter mode (Timers B0 and B1)
The timer counts an external signal.
(3) Pulse period/Pulse width measurement mode (Timers B0 and B1)
The timer measures an external signal’s pulse period or pulse width.
In this chapter, Timer Bi (i = 0 to 2) indicates Timers B0 to B2. Timer Bj (j = 0, 1) indicates Timers B0 and
B1; this is used when the timer B’s input/output pins are used etc. (Hereafter, input/output pins are called
I/O pins.)
9.2 Block description
Figure 9.2.1 shows the block diagram of Timer B. Explanation of registers relevant to Timer B is described
below.
Data bus (odd)
Count source select bits
f2
f 16
f 64
Data bus (even)
(Low-order 8 bits)
f 512
Timer mode
Pulse period/Pulse width measurement mode
TBj IN
Polarity switching
and edge pulse
generating circuit
(High-order 8 bits)
Timer Bi reload register (16)
Event counter
mode
Timer Bi
interrupt
request bit
Timer Bi counter (16)
Timer Bj
overflow
flag
Count start bit
(Valid in pulse period/pulse width
measurement mode)
Counter reset circuit
i = 0–2, j = 0, 1
Fig. 9.2.1 Block diagram of Timer B
9–2
7721 Group User’s Manual
TIMER B
9.2 Block description
9.2.1 Counter and reload register (timer Bi register)
Each of timer Bi counter and reload register consists of 16 bits and has the following functions.
(1) Functions in timer mode and event counter mode
Countdown in the counter is performed each time the count source is input. The reload register is
used to store the initial value of the counter. When a counter underflow occurs, the reload register’s
contents are reloaded into the counter.
A value is set to the counter and reload register by writing the value to the timer Bi register. Table
9.2.1 lists the memory assignment of the timer Bi register.
The value written into the timer Bi register when the counting is not in progress is set to the counter
and reload register. The value written into the timer Bi register when the counting is in progress is
set only to the reload register. In this case, the reload register’s updated contents are transferred to
the counter when the next underflow occurs. The counter value is read out by reading out the timer
Bi register.
Note: When reading from or writing to the timer Bi register, perform it in a unit of 16 bits. For more
information about the value obtained by reading the timer Bi register, refer to “[Precautions
for timer mode]” and “[Precautions for event counter mode].”
(2) Functions in pulse period/pulse width measurement mode
Countup in the counter is performed each time the count source is input. The reload register is used
to retain the pulse period or pulse width measurement result. When a valid edge is input to the TBjIN
pin, the counter value is transferred to the reload register. In this mode, the value obtained by
reading the timer Bj register is the reload register’s contents, so that the measurement result is
obtained.
Note: When reading from the timer Bj register, perform it in a unit of 16 bits.
Table 9.2.1 Memory assignment of timer Bi registers
Timer Bi register
Timer B0 register
Timer B1 register
Timer B2 register
High-order byte
Address 5116
Address 5316
Address 5516
Low-order byte
Address 5016
Address 5216
Address 5416
Note: At reset, the contents of the timer Bi
register are undefined.
7721 Group User’s Manual
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TIMER B
9.2 Block description
9.2.2 Count start register
This register is used to start and stop counting. Each bit of this register corresponds to each timer.
Figure 9.2.2 shows the structure of the count start register.
b7
b6
b5
b4
b3
b2
b1
b0
Count start register (Address 4016)
Bit
Bit name
Functions
0 : Stop counting
1 : Start counting
RW
0
RW
0
Timer A0 count start bit
1
Timer A1 count start bit
0
RW
2
Timer A2 count start bit
0
RW
3
Timer A3 count start bit
0
RW
4
Timer A4 count start bit
0
RW
5
Timer B0 count start bit
0
RW
6
Timer B1 count start bit
0
RW
7
Timer B2 count start bit
0
RW
: Bits 0 to 4 are not used for Timer B.
Fig. 9.2.2 Structure of count start register
9–4
At reset
7721 Group User’s Manual
TIMER B
9.2 Block description
9.2.3 Timer Bi mode register
Figure 9.2.3 shows the structure of the timer Bi mode register. The operating mode select bits are used
to select the operating mode of Timer Bi. Bits 2, 3, and bits 5 to 7 have different functions according to
the operating mode. These bits are described in the paragraph of each operating mode.
b7 b6 b5
b4
b3 b2 b1 b0
Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16)
Bit
0
Bit name
Operating mode select bits
1
2
Functions
b1 b0
0 0 : Timer mode
0 1 : Event counter mode
1 0 : Pulse period/Pulse width
measurement mode
1 1 : Do not select.
These bits have different functions according to the operating mode.
3
At reset
RW
0
RW
0
RW
0
RW
0
RW
Nothing is assigned.
Undefined
–
These bits have different functions according to the operating mode.
Undefined
RO
(Note)
6
0
RW
7
0
RW
4
5
Note: Bit 5 is invalid in the timer and event counter modes; its value is undefined at reading.
Fig. 9.2.3 Structure of timer Bi mode register
7721 Group User’s Manual
9–5
TIMER B
9.2 Block description
9.2.4 Timer Bi interrupt control register
Figure 9.2.4 shows the structure of the timer Bi interrupt control register. For details about interrupts, refer
to “CHAPTER 7. INTERRUPTS.”
b7
b6
b5
b4
b3
b2
b1
b0
Timer Bi interrupt control register (i = 0 to 2) (Addresses 7A16 to 7C16)
Bit
Bit name
0
Interrupt priority level select bits
1
2
3
Interrupt request bit
7 to 4
Nothing is assigned.
Functions
At reset
RW
0 0 0 : Level 0 (Interrupt disabled)
0 0 1 : Level 1
Low level
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
High level
0
RW
0
RW
0
RW
0 : No interrupt requested
1 : Interrupt requested
0
RW
Undefined
–
b2 b1 b0
Fig. 9.2.4 Structure of timer Bi interrupt control register
(1) Interrupt priority level select bits (bits 2 to 0)
These bits select a timer Bi interrupt’s priority level. When using timer Bi interrupts, select one of the
priority levels (1 to 7). When a timer Bi interrupt request occurs, its priority level is compared with
the processor interrupt priority level (IPL). The requested interrupt is enabled only when its priority
level is higher than the IPL. (However, this applies when the interrupt disable bit (I) = “0.”) To disable
timer Bi interrupts, set these bits to “000 2” (level 0).
(2) Interrupt request bit (bit 3)
This bit is set to “1” when a timer Bi interrupt request occurs. This bit is automatically cleared to “0”
when the timer Bi interrupt request is accepted. This bit can be set to “1” or cleared to “0” by
software.
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TIMER B
9.2 Block description
9.2.5 Port P5 direction register
Input pins of Timer Bj are multiplexed with port P5. When using these pins as Timer Bj’s input pins, set
the corresponding bits of the port P5 direction register to “0” to set these port pins for the input mode.
Figure 9.2.5 shows the relationship between port P5 direction register and the Timer Bj’s input pins.
b7
b6
b5
b4
b3
b2
b1
b0
Por t P5 direction register (Address D16)
Bit
Corresponding pin name
0
TA2 OUT pin
1
TA2 IN pin
Functions
0 : Input mode
1 : Output mode
When using these pins as
Timer Bj' s input pins, set the
corresponding bits to "0 ."
At reset
RW
0
RW
0
RW
0
RW
0
RW
2
TA3 OUT pin
3
TA3 IN pin
4
TA4 OUT pin
0
RW
5
TA4 IN pin
0
RW
6
TB0 IN pin
0
RW
7
TB1 IN pin
0
RW
: Bits 0 to 5 are not used for Timer B.
Fig. 9.2.5 Relationship between port P5 direction register and Timer Bj’s input pins
7721 Group User’s Manual
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TIMER B
9.3 Timer mode
9.3 Timer mode
In this mode, the timer counts an internally generated count source. (Refer to “Table 9.3.1.”) Figure 9.3.1
shows the structures of the timer Bi mode register and timer Bi register in the timer mode.
Table 9.3.1 Specifications of timer mode
Item
f 2, f 16, f 64, or f 512
Count source
Count operation
Division ratio
Count start condition
Count stop condition
Specifications
•Countdown
•When a counter underflow occurs, reload register’s contents are reloaded,
and counting continues.
1
n : Timer Bi register’s set value
(n + 1)
When the count start bit is set to “1.”
When the count start bit is cleared to “0.”
Interrupt request occurrence timing When a counter underflow occurs.
TBj IN pin’s function
Programmable I/O port
Read from timer Bi register
Counter value can be read out.
Write to timer Bi register
● While counting is stopped
When a value is written to the timer Bi register, it is written to both
of the reload register and counter.
● While counting is in progress
When a value is written to the timer Bi register, it is written only to
the reload register. (Transferred to the counter at the next reload
time.)
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TIMER B
9.3 Timer mode
b7
b6
b5
✕
b4
b3
b2
b1
b0
✕ ✕ 0 0
Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16)
Bit
0
Bit name
Functions
Operating mode select bits
b1 b0
0 0 : Timer mode
1
2
These bits are invalid in timer mode.
3
(b8)
b0 b7
RW
0
RW
0
RW
0
RW
0
RW
4
Nothing is assigned.
Undefined
–
5
This bit is invalid in timer mode; its value is undefined at reading.
Undefined
RO
6
Count source select bits
0
RW
0
RW
At reset
RW
7
(b15)
b7
At reset
b0
b7 b6
0 0 : f2
0 1 : f16
1 0 : f64
1 1 : f512
Timer B0 register (Addresses 5116, 5016)
Timer B1 register (Addresses 5316, 5216)
Timer B2 register (Addresses 5516, 5416)
Bit
Functions
15 to 0 These bits can be set to “000016” to “FFFF16.” Undefined RW
Assuming that the set value = n, the counter
divides the count source frequency by (n + 1).
When reading, the register indicates the
counter value.
Note: Read from or write to this register in a unit of 16 bits.
Fig. 9.3.1 Structures of timer Bi mode register and timer Bi register in timer mode
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TIMER B
9.3 Timer mode
9.3.1 Setting for timer mode
Figure 9.3.2 shows an initial setting example for registers relevant to the timer mode.
Note that when using interrupts, set up to enable the interrupts. For details, refer to “CHAPTER 7.
INTERRUPTS.”
Selecting timer mode and count source
b7
b0
✕
✕ ✕ 0 0
Timer Bi mode register (i = 0 to 2)
(Addresses 5B16 to 5D16)
Selection of timer mode
Count source select bits
b7 b6
0 0 : f2
0 1 : f16
1 0 : f64
1 1 : f512
✕: It may be either “0” or “1.”
Setting division ratio
(b15)
b7
(b8)
b0 b7
b0
Timer B0 register (Addresses 5116, 5016)
Timer B1 register (Addresses 5316, 5216)
Timer B2 register (Addresses 5516, 5416)
Can be set to “000016” to “FFFF16” (n).
Note: The counter divides the count source by (n + 1).
Setting interrupt priority level
b7
b0
Timer Bi interrupt control register (i = 0 to 2)
(Addresses 7A16 to 7C16)
Interrupt priority level select bits
When using interrupts, set these bits to one of levels 1 to 7.
When disabling interrupts, set these bits to level 0.
Setting count start bit to “1”
b7
b0
Count start register (Address 4016)
Timer B0 count start bit
Timer B1 count start bit
Timer B2 count start bit
Count Starts
Fig. 9.3.2 Initial setting example for registers relevant to timer mode
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TIMER B
9.3 Timer mode
9.3.2 Count source
In the timer mode, the count source select bits (bits 6 and 7 at addresses 5B 16 to 5D 16) select the count
source. Table 9.3.2 lists the count source frequency.
Table 9.3.2 Count source frequency
Count source
select bits
Count
source
f(X IN) = 8 MHz
4 MHz
f(X IN) = 16 MHz
8 MHz
f(X IN) = 25 MHz
12.5 MHz
500 kHz
1 MHz
1.5625 MHz
f 64
125 kHz
250 kHz
390.625 kHz
f 512
15625 Hz
31250 Hz
48.8281 kHz
0
b6
0
f2
0
1
f 16
1
1
0
1
b7
Count source frequency
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TIMER B
9.3 Timer mode
9.3.3 Operation in timer mode
➀ When the count start bit is set to “1,” the counter starts counting of the count source.
➁ When a counter underflow occurs, the reload register’s contents are reloaded, and counting continues.
➂ The timer Bi interrupt request bit is set to “1” at the underflow in ➁. The interrupt request bit remains
set to “1” until the interrupt request is accepted or the interrupt request bit is cleared to “0” by software.
Figure 9.3.3 shows an example of operation in the timer mode.
n = Reload register’s contents
Counter contents (Hex.)
FFFF16
Starts counting.
1 / fi ✕ (n+1)
Stops counting.
n
Restarts counting.
000016
Time
Set to “1” by software.
Cleared to “0” by software.
Count start bit
Timer Bi interrupt
request bit
fi = frequency of count source
(f2, f16, f64, f512)
Cleared to “0” when interrupt request is
accepted or cleared by software.
Fig. 9.3.3 Example of operation in timer mode
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Set to “1” by software.
TIMER B
9.3 Timer mode
[Precautions for timer mode]
While counting is in progress, by reading the timer Bi register, the counter value can be read out at any
timing. However, if the timer Bi register is read at the reload timing shown in Figure 9.3.4, the value
“FFFF16” is read out. If reading is performed in the period from when a value is set into the timer Bi register
with the counter stopped until the counter starts counting, the set value is correctly read out.
Reload
Counter value
(Hex.)
2
1
0
Read value
(Hex.)
2
1
0
n
n–1
FFFF n – 1
n = Reload register’s contents
Time
Fig. 9.3.4 Reading timer Bi register
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TIMER B
9.4 Event counter mode
9.4 Event counter mode
In this mode, the timer counts an external signal. (Refer to “Table 9.4.1.”) Figure 9.4.1 shows the structures
of the timer Bj mode register and the timer Bj register in the event counter mode.
Table 9.4.1 Specifications of event counter mode
Specifications
Item
•External signal input to the TBjIN pin
Count source
•The count source’s valid edge can be selected from the falling edge,
the rising edge, and both of the falling and rising edges by software.
Count operation
•Countdown
•When a counter underflow occurs, reload register’s contents are reloaded,
and counting continues.
Division ratio
1
(n + 1)
n : Timer Bj register’s set value
Count start condition
When the count start bit is set to “1.”
Count stop condition
When the count start bit is cleared to “0.”
Interrupt request occurrence timing When a counter underflow occurs.
Count source input
TBj IN pin’s function
Read from timer Bj register
Counter value can be read out.
Write to timer Bj register
● While counting is stopped
When a value is written to the timer Bj register, it is written to both
of the reload register and counter.
● While counting is in progress
When a value is written to the timer Bj register, it is written only to
the reload register. (Transferred to the counter at the next reload
time.)
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TIMER B
9.4 Event counter mode
b7
b6
b5
✕ ✕ ✕
b4
b3
b2
b1
b0
0 1
Timer Bj mode register (j = 0, 1) (Addresses 5B16, 5C16)
Bit
0
Bit name
Functions
Operating mode select bits
b1 b0
0 1 : Event counter mode
1
2
Count polarity select bits
b3 b2
0 0 : Count at falling edge of external signal
0 1 : Count at rising edge of external signal
1 0 : Counts at both falling and rising edges
of external signal
1 1 : Do not select.
3
(b8)
b0 b7
RW
0
RW
0
RW
0
RW
0
RW
4
Nothing is assigned.
Undefined
—
5
This bit is invalid in event counter mode; its value is undefined at
reading.
Undefined
RO
6
These bits are invalid in event counter mode.
0
RW
0
RW
At reset
RW
Undefined
RW
7
(b15)
b7
At reset
b0
Timer B0 register (Addresses 5116, 5016)
Timer B1 register (Addresses 5316, 5216)
Bit
Functions
15 to 0 These bits can be set to “000016” to “FFFF16.”
Assuming that the set value = n, the counter
divides the count source frequency by (n + 1).
When reading, the register indicates the
counter value.
Note: Read from or write to this register in a unit of 16 bits.
Fig. 9.4.1 Structures of timer Bj mode register and timer Bj register in event counter mode
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TIMER B
9.4 Event counter mode
9.4.1 Setting for event counter mode
Figure 9.4.2 shows an initial setting example for registers relevant to the event counter mode.
Note that when using interrupts, set up to enable the interrupts. For details, refer to “CHAPTER 7.
INTERRUPTS.”
Selecting event counter mode and count polarity
b7
b0
✕ ✕ ✕
0 1
Timer Bj mode register (j = 0, 1) (Addresses 5B16, 5C16)
Selection of event counter mode
Count polarity select bits
b3 b2
0
0
1
1
0 : Counts at falling edge of external signal.
1 : Counts at rising edge of external signal.
0 : Counts at both of falling and rising edges of external signal.
1 : Do not select.
✕: It may be “0” or “1.”
Setting division ratio
(b15)
b7
(b8)
b0 b7
b0
Timer B0 register (Addresses 5116, 5016)
Timer B1 register (Addresses 5316, 5216)
Can be set to “000016” to “FFFF16” (n).
Note: The counter divides the count source by (n + 1).
Setting interrupt priority level
b7
b0
Timer Bj interrupt control register (j = 0, 1)
(Addresses 7A16, 7B16)
Interrupt priority level select bits
When using interrupts, set these bits to one of levels 1 to 7.
When disabling interrupts, set these bits to level 0.
Setting port P5 direction register
b7
b0
Port P5 direction register (Address D16)
TB0IN pin
Clear the corresponding bit to “0.”
TB1IN pin
Setting count start bit to “1”
b7
b0
Count start register (Address 4016)
Count starts
Timer B0 count start bit
Timer B1 count start bit
Fig. 9.4.2 Initial setting example for registers relevant to event counter mode
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TIMER B
9.4 Event counter mode
9.4.2 Operation in event counter mode
➀ When the count start bit is set to “1,” the counter starts counting of the count source’s valid edges.
➁ When a counter underflow occurs, the reload register’s contents are reloaded, and counting continues.
➂ The timer Bj interrupt request bit is set to “1” at the underflow in ➁.
The interrupt request bit remains set to “1” until the interrupt request is accepted or the interrupt request
bit is cleared to “0” by software.
Figure 9.4.3 shows an example of operation in the event counter mode.
n = Reload register’s contents
Counter contents (Hex.)
FFFF16
Starts counting.
Stops counting.
n
Restarts counting .
000016
Time
Set to “1” by software.
Cleared to “0” by
software.
Set to “1” by software.
Count start bit
Timer Bj interrupt
request bit
Cleared to “0” when interrupt request is accepted or cleared by software.
Fig. 9.4.3 Example of operation in event counter mode
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TIMER B
9.4 Event counter mode
[Precautions for event counter mode]
While counting is in progress, by reading the timer Bj register, the counter value can be read out at any
timing. However, if the timer Bj register is read at the reload timing shown in Figure 9.4.4, the value
“FFFF16” is read out. If reading is performed in the period from when a value is set into the timer Bj register
with the counter stopped until the counter starts counting, the set value is correctly read out.
Reload
Counter value
(Hex.)
2
1
0
Read value
(Hex.)
2
1
0
n
FFFF n – 1
n = Reload register’s contents
Fig. 9.4.4 Reading timer Bj register
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Time
TIMER B
9.5 Pulse period/Pulse width measurement mode
9.5 Pulse period/Pulse width measurement mode
In this mode, the timer measures an external signal’s pulse period or pulse width. (Refer to “Table 9.5.1.”)
Timers B0 and B1 can be used in this mode. Figure 9.5.1 shows the structures of the timer Bj mode register
and timer Bj register in the pulse period/pulse width measurement mode.
● Pulse period measurement
The timer measures the pulse period of the external signal that is input to the TBjIN pin.
● Pulse width measurement
The timer measures the pulse width (“L” level and “H” level widths) of the external signal that is input
to the TBj IN pin.
Table 9.5.1 Specifications of pulse period/pulse width measurement mode
Item
Specifications
Count source
f 2 , f 16, f64 , or f512
Count operation
● Countup
● Counter value is transferred to the reload register at valid edge of
measurement pulse, and counting continues after clearing the counter
value to “000016.”
Count start condition
When the count start bit is set to “1.”
Count stop condition
When the count start bit is cleared to “0.”
Interrupt request occurrence timing ● When valid edge of measurement pulse is input (Note 1).
TBjIN pin’s function
Read from timer Bj register
Write to timer Bj register
● When a counter overflow occurs (Timer Bj overflow flag✽ is set to
“1” simultaneously.)
Measurement pulse input
The value obtained by reading timer Bj register is the reload register’s
contents (Measurement result) (Note 2).
Invalid
Timer Bj overflow flag✽: The bit used to identify the source of an interrupt request occurrence.
Notes 1: No interrupt request occurs when the first valid edge is input after the counter starts counting.
2: The value read out from the timer Bj register is undefined after the counter starts counting until
the second valid edge is input.
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TIMER B
9.5 Pulse period/Pulse width measurement mode
b7
b6
b5
b4
b3
b2
b1
b0
1 0
Timer Bj mode register (j = 0, 1) (Addresses 5B16, 5C16)
Bit
0
Bit name
Functions
Operating mode select bits
b1 b0
Measurement mode select bits
b3 b2
1
2
3
1 0 : Pulse period/Pulse width
measurement mode
0 0 : Pulse period measurement
(Interval between falling edges
of measurement pulse)
0 1 : Pulse period measurement
(Interval between rising edges
of measurement pulse)
1 0 : Pulse width measurement
(Interval from a falling edge to a rising
edge, and from a rising edge to a
falling edge of measurement pulse)
1 1 : Do not select.
4
Nothing is assigned.
5
Timer Bj overflow flag
(Note)
0 : No overflow
1 : Overflowed
6
Count source select bits
b7 b6
7
0 0 : f2
0 1 : f16
1 0 : f64
1 1 : f512
At reset
RW
0
RW
0
RW
0
RW
0
RW
Undefined
–
Undefined
RO
0
RW
0
RW
Note: The timer Bj overflow flag is cleared to “0” at the next count timing of the count source
when a value is written to the timer Bj mode register with the count start bit = “1.”
(b15)
b7
(b8)
b0 b7
b0
Timer B0 register (Addresses 5116, 5016)
Timer B1 register (Addresses 5316, 5216)
Bit
Functions
15 to 0 The measurement result of pulse period or
pulse width is read out.
At reset
RW
Undefined
RO
Note: Read from this register in a unit of 16 bits.
Fig. 9.5.1 Structures of timer Bj mode register and timer Bj register in pulse period/pulse width
measurement mode
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TIMER B
9.5 Pulse period/Pulse width measurement mode
9.5.1 Setting for pulse period/pulse width measurement mode
Figure 9.5.2 shows an initial setting example for registers relevant to the pulse period/pulse width measurement
mode.
Note that when using interrupts, set up to enable the interrupts. For details, refer to “CHAPTER 7.
INTERRUPTS.”
Selecting pulse period/pulse width measurement mode and each function
b7
b0
1 0
Timer Bj mode register (i = 0, 1) (Addresses 5B16, 5C16)
Selection of pulse period/pulse width measurement mode
Measurement mode select bits
b3 b2
0 0 : Pulse period measurement (Interval between falling edges
of measurement pulse)
0 1 : Pulse period measurement (Interval between rising edges
of measurement pulse)
1 0 : Pulse width measurement
1 1 : Do not select.
Timer Bj overflow flag (Note)
0: No overflow
1: Overflowed
Count source select bits
b7 b6
0
0
1
1
0 : f2
1 : f16
0 : f64
1 : f512
Setting interrupt priority level
b7
b0
Timer Bj interrupt control register (j = 0, 1)
(Addresses 7A16, 7B16)
Interrupt priority level select bits
When using interrupts, set these bits to one of levels
1 to 7.
When disabling interrupts, set these bits to level 0.
Setting port P5 direction register
b7
b0
Port P5 direction register (Address D16)
TB0IN pin
TB1IN pin
Clear the corresponding bit to “0.”
Setting count start bit to “1”
b7
b0
Count start register (Address 4016)
Timer B0 count start bit
Timer B1 count start bit
AAAA
AAAA
Count starts
AAAA
AAAA
Note: The timer Bj overflow flag is a read-only bit. This bit is undefined after reset. When a value is written to the timer Bj mode register with
the count start bit = “1,” this bit is cleared to “0” at the next count timing of the count source.
Fig. 9.5.2 Initial setting example for registers relevant to pulse period/pulse width measurement mode
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TIMER B
9.5 Pulse period/Pulse width measurement mode
9.5.2 Count source
In the pulse period/pulse width measurement mode, the count source select bits (bits 6 and 7 at addresses
5B16 and 5C16) select the count source.
Table 9.5.2 lists the count source frequency.
Table 9.5.2 Count source frequency
Count source
select bits
Count source frequency
f(X IN) = 8 MHz
f(X IN) = 16 MHz
f2
4 MHz
8 MHz
12.5 MHz
500 kHz
1 MHz
1.5625 MHz
0
f 16
f 64
250 kHz
390.625 kHz
1
f 512
125 kHz
15625 Hz
31250 Hz
48.8281 kHz
b7
b6
0
0
0
1
1
1
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Count
source
7721 Group User’s Manual
f(X IN) = 25 MHz
TIMER B
9.5 Pulse period/Pulse width measurement mode
9.5.3 Operation in pulse period/pulse width measurement mode
➀ When the count start bit is set to “1,” the counter starts counting of the count source.
➁ The counter value is transferred to the reload register when an valid edge of the measurement pulse
is detected. (Refer to section “(1) Pulse period/Pulse width measurement.”)
➂ The counter value is cleared to “0000 16” after the transfer in ➁, and the counter continues counting.
➃ The timer Bj interrupt request bit is set to “1” when the counter value is cleared to “000016” in ➂ (Note).
The interrupt request bit remains set to “1” until the interrupt request is accepted or the interrupt request
bit is cleared to “0” by software.
➄ The timer repeats operations ➁ to ➃ above.
Note: No timer Bj interrupt request occurs when the first valid edge is input after the counter starts counting.
(1) Pulse period/Pulse width measurement
The measurement mode select bits (bits 2 and 3 at addresses 5B 16 and 5C16) specify whether the
pulse period of an external signal is measured or its pulse width is done. Table 9.5.3 lists the
relationship between the measurement mode select bits and the pulse period/pulse width measurements.
Make sure that the measurement pulse interval from the falling edge to the rising edge, and vice
versa are two cycles of the count source or more. Additionally, use software to identify whether the
measurement result indicates the “H” level or the “L” level width.
Table 9.5.3 Relationship between measurement mode select bits and pulse period/pulse width measurements
b3
b2
Pulse period/Pulse width measurement
0
0
0
1
Pulse period measurement
From falling edge to falling edge (Falling edges)
From rising edge to rising edge (Rising edges)
1
0
Pulse width measurement
From falling edge to rising edge, and vice versa
Measurement interval (Valid edges)
(Falling and rising edges)
(2) Timer Bj overflow flag
A timer Bj interrupt request occurs when a measurement pulse’s valid edge is input or a counter
overflow occurs. The timer Bj overflow flag is used to identify the cause of the interrupt request, that
is, whether it is an overflow occurrence or a valid edge input.
The timer Bj overflow flag is set to “1” by an overflow. Accordingly, the cause of the interrupt request
occurrence is identified by checking the timer Bj overflow flag in the interrupt routine. When a value
is written to the timer Bj mode register with the count start bit = “1,” the timer Bj overflow flag is
cleared to “0” at the next count timing of the count source
The timer Bj overflow flag is a read-only bit.
Use the timer Bi interrupt request bit to detect the overflow timing. Do not use the timer Bi overflow
flag for this detection.
Figure 9.5.3 shows the operation during pulse period measurement. Figure 9.5.4 shows the operation
during pulse width measurement.
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TIMER B
9.5 Pulse period/Pulse width measurement mode
Count source
Measurement pulse
Transferred
(undefined value)
Reload register
Counter
Transfer timing
Transferred
(measured value)
➀
➁
➀
Timing at which counter is
cleared to “000016”
Count start bit
Timer Bj interrupt
request bit
Timer Bj overflow flag
Cleared to “0” when interrupt request is accepted or
cleared by software.
➀ Counter is initialized by completion of measurement.
➁ Counter overflow.
Note: The above applies when measurement is performed for an interval from one falling edge to the next
falling edge of the measurement pulse.
Fig. 9.5.3 Operation during pulse period measurement
Count source
Measurement pulse
Reload register
Counter
Transfer timing
Transferred
(undefined
value)
Transferred
Transferred (measured
(measured
value)
value)
➀
➀
➀
Transferred
(measured
value)
➀
Timing at which counter is
cleared to “000016”
Count start bit
Timer Bj interrupt
request bit
Timer Bj overflow flag
Cleared to “0” when interrupt request is accepted or
cleared by software.
➀ Counter is initialized by completion of measurement.
➁ Counter overflow.
Fig. 9.5.4 Operation during pulse width measurement
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➁
TIMER B
9.5 Pulse period/Pulse width measurement mode
[Precautions for pulse period/pulse width measurement mode]
1. A timer Bj interrupt request is generated by the following sources:
● Input of measured pulse’s valid edge
● Counter overflow
When the overflow generates the interrupt request, the timer Bj overflow flag is set to “1.”
2. After reset, the timer Bj overflow flag is undefined. When a value is written to the timer Bj mode register
with the count start bit = “1,” this flag is cleared to “0” at the next count timing of the count source.
3. An undefined value is transferred to the reload register when the first valid edge is input after the counter
starts counting. In this case, no timer Bj interrupt request occurs.
4. The counter value at start of counting is undefined. Accordingly, a timer Bj interrupt request may be
generated by an overflow immediately after the counter starts counting.
5. If the contents of the measurement mode select bits are changed after the counter starts counting, the
timer Bj interrupt request bit is set to “1.” When the same value which has been set in these bits are
written again, the timer Bj interrupt request bit is not changed, that is, the bit retains the state.
6. If the input signal to the TBjIN pin is affected by noise, etc., the counter may not perform the exact
measurement. We recommend to verify, by software, that the measurement values are within a constant
range.
7721 Group User’s Manual
9–25
TIMER B
9.5 Pulse period/Pulse width measurement mode
MEMORANDUM
9–26
7721 Group User’s Manual
CHAPTER 10
REAL-TIME
OUTPUT
10.1
10.2
10.3
10.4
Overview
Block description
Setting of real-time output
Real-time output operation
REAL-TIME OUTPUT
10.1 Overview
10.1 Overview
The real-time output has the function of changing the output level of several pins simultaneously at every
period of the timer. Figure 10.1.1 shows the block diagram of real-time output per bit. Real-time output has
two operating modes described below.
(1) Pulse mode 0
The 8-bit pulse output pins serve for two independent 4-bit outputs. Figure 10.1.2 shows the configuration
of real-time output in the pulse mode 0.
(2) Pulse mode 1
The 8-bit pulse output pins serve for a 2-bit and a 6-bit outputs. Figure 10.1.3 shows the configuration
of real-time output in the pulse mode 1.
Timer Aj
underflow signal
Data bus
Pulse output data register j
Bit i of port P6 direction register
T
D
1
Q
Flip-flop
P6i/RTP0k, P6i/RTP1k
Port P6i latch
0
Waveform output select bit j
• i = 0–7
• j = 0, 1
• k = 0–3
Fig. 10.1.1 Block diagram of real-time output per bit
10–2
7721 Group User’s Manual
REAL-TIME OUTPUT
10.1 Overview
Pulse output data register 0
b7
b0
Timer A0
Port P6i direction register
1
a
a
a
a
DTQ
T
DQ
T
DQ
DTQ
Data bus (even)
a
P60/RTP00
Port P6i latch
P61/RTP01
P62/RTP02
P63/RTP03
(i = 0–7)
0
Bit 0 of waveform output select bits
Pulse output data register 1
b7
b0
Timer A1
T
DQ
DTQ
P64/RTP10
P65/RTP11
P66/RTP12
P67/RTP13
a
a
a
a
T
DQ
T
DQ
Bit 1 of waveform output select bits
Fig. 10.1.2 Configuration of real-time output in pulse mode 0
Pulse output data register 0
b7
b0
Timer A0
Data bus (even)
T
DQ
T
DQ
a
a
P60/RTP00
P61/RTP01
Bit 0 of waveform output select bits
Pulse output data register 1
b7
b0
Timer A1
a
T
DQ
T
DQ
T
DQ
T
DQ
T
DQ
T
DQ
a
a
a
a
a
a
P62/RTP02
P63/RTP03
P64/RTP10
P65/RTP11
P66/RTP12
P67/RTP13
Port P6i direction register
1
Port P6i latch
(i = 0–7)
0
Bit 1 of waveform output select bits
Fig. 10.1.3 Configuration of real-time output in pulse mode 1
7721 Group User’s Manual
10–3
REAL-TIME OUTPUT
10.2 Block description
10.2 Block description
Relevant registers to real-time output are described below.
10.2.1 Real-time output control register
Figure 10.2.1 shows the structure of the real-time output control register.
b7
b6
b5
b4
b3
b2
b1
b0
Real-time output control register (Address 6216)
Bit
Bit name
Functions
0
Waveform output select bits
See the following Table.
1
2
0 : Pulse mode 0
1 : Pulse mode 1
Pulse output mode select bit
7 to 3 Nothing is assigned.
The value is “0” at reading.
At reset
RW
0
RW
0
RW
0
RW
Undefined
–
Note: When using the P60–P67 pins as the pulse output pins for real-time output, set the
corresponding bits of the port P6 direction register (address 1016) to “1.”
b1 b0
When pulse mode 0
is selected
When pulse mode 1
is selected
01
00
P67/RTP13
P66/RTP12
P65/RTP11
P64/RTP10
P63/RTP03
P62/RTP02
P61/RTP01
P60/RTP00
10
Port
P67/RTP13
P66/RTP12
P65/RTP11
P64/RTP10
RTP
P63/RTP03
P62/RTP02
P61/RTP01
P60/RTP00
Port
P67/RTP13
P66/RTP12
P65/RTP11
P64/RTP10
P63/RTP03
P62/RTP02
Port
P61/RTP01
P60/RTP00
Port
P67/RTP13
P66/RTP12
P65/RTP11
P64/RTP10
Port
P63/RTP03
P62/RTP02
P61/RTP01
P60/RTP00
P67/RTP13
P66/RTP12
P65/RTP11
P64/RTP10
P63/RTP03
P62/RTP02
P61/RTP01
P60/RTP00
RTP
P67/RTP13
P66/RTP12
P65/RTP11
P64/RTP10
RTP
Port
P63/RTP03
P62/RTP02
P61/RTP01
P60/RTP00
RTP
Port
P67/RTP13
P66/RTP12
P65/RTP11
P64/RTP10
P63/RTP03
P62/RTP02
RTP
P67/RTP13
P66/RTP12
P65/RTP11
P64/RTP10
P63/RTP03
P62/RTP02
RTP
RTP
P61/RTP01
P60/RTP00
Port
P61/RTP01
P60/RTP00
RTP
Port : This functions as a programmable I/O port.
RTP : This functions as a pulse output pin.
Fig. 10.2.1 Structure of real-time output control register
10–4
11
7721 Group User’s Manual
REAL-TIME OUTPUT
10.2 Block description
10.2.2 Pulse output data registers 0 and 1
Figure 10.2.2 shows the structure of the pulse output data registers 0 and 1. The bit position of the RTP0 2
and RTP03 pulse output data bits differs according to the pulse mode. Before setting the pulse output data
registers 0 and 1, set of the pulse output mode select bit (bit 2 at address 6216).
The data written into the pulse output data registers 0 and 1 is output from the corresponding pulse output
pins every underflow of Timers A0 and A1.
b7
b6
b5
b4
b3
b2
b1
b0
Pulse output data register 0 (Address 1A16)
Bit
Bit name
Functions
0 : “L” level output
1 : “H” level output
At reset
RW
Undefined
WO
Undefined
WO
0
RTP00 pulse output data bit
1
RTP01 pulse output data bit
2
RTP02 pulse output data bit
(Valid in pulse mode 0)
Undefined
WO
3
RTP03 pulse output data bit
(Valid in pulse mode 0)
Undefined
WO
Nothing is assigned.
Undefined
7 to 4
Note: Use the LDM or STA instruction for writing to this register
b7
b6
b5
b4
b3
b2
b1
b0
Pulse output data register 1 (Address 1C16)
Bit
Bit name
0, 1
Nothing is assigned.
2
RTP02 pulse output data bit
(Valid in pulse mode 1)
3
Functions
At reset
RW
Undefined
0 : “L” level output
1 : “H” level output
Undefined
WO
RTP03 pulse output data bit
(Valid in pulse mode 1)
Undefined
WO
4
RTP10 pulse output data bit
Undefined
WO
5
RTP11 pulse output data bit
Undefined
WO
6
RTP12 pulse output data bit
Undefined
WO
7
RTP13 pulse output data bit
Undefined
WO
Note: Use the LDM or STA instruction for writing to this register.
Fig. 10.2.2 Structure of pulse output data registers 0 and 1
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10–5
REAL-TIME OUTPUT
10.2 Block description
10.2.3 Port P6 direction register
The pulse output pins are shared with port P6. When using these pins as pulse output pins of real-time
output, set the corresponding bits of the port P6 direction register to “1” to set these ports for the output
mode. Figure 10.2.3 shows the relationship between the port P6 direction register and the pulse output
pins.
b7
b6
b5
b4
b3
b2
b1
b0
Port P6 direction register (Address 1016)
Bit
Bit name
0
RTP00 pin
1
RTP01 pin
Functions
0 : Input mode
1 : Output mode
When using these pins as pulse
output pins, set the corresponding
bits to “0.”
At reset
RW
0
RW
0
RW
0
RW
0
RW
2
RTP02 pin
3
RTP03 pin
4
RTP10 pin
0
RW
5
RTP11 pin
0
RW
6
RTP12 pin
0
RW
7
RTP13 pin
0
RW
Note: When setting these bits to “0,” the corresponding pins serve as input port
(floated) regardless of the state of the waveform output select bits (bits 0 and 1
at address 6216).
Fig. 10.2.3 Relationship between port P6 direction register and pulse output pins
After reset, the state of the port P6 pins are floated since these pins are in the input mode. The output
levels of the pulse output pins are undefined until Timer A0 or A1 underflows first after the data for the
timer is written. Because the pulse output data registers 0 and 1 are undefined after reset.
When these conditions should be avoided, follow the procedure “Processing of avoiding undefined output
before starting pulse output” in Figures 10.3.1 and 10.3.2.
When reading the port P6 register (address E 16), the output values of the real time output pins can be read
out.
10.2.4 Timers A0 and A1
The data written into the pulse output registers 0 and 1 is output from the pulse output pins every
underflow of Timer A0 or A1. Refer to section “8.3 Timer mode” for the setting of Timers A0 and A1.
10–6
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REAL-TIME OUTPUT
10.3 Setting of real-time output
10.3 Setting of real-time output
Figures 10.3.1 to 10.3.3 show an initial setting example for registers relevant to the real-time output. Note
that when using interrupts, set up to enable the interrupts. For details, refer to “CHAPTER 7. INTERRUPTS.”
Processing of avoiding undefined output before starting pulse output (Note)
b7
b0
Port P6 register (Address E16)
RTP00
RTP01
RTP02
RTP03
RTP10
RTP11
RTP12
RTP13
Note: This processing can be neglected
if the system is not affected by
undefined output.
Set to initial output level
of real-time output
0 : “L” level
1 : “H” level
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Setting port P6 direction register
b7
b0
Port P6 direction register (Address 1016)
RTP00
RTP01
RTP02
RTP03
RTP10
RTP11
RTP12
RTP13
Set the bits corresponding to the
selected pulse output pins to “1.”
Setting pulse output mode
b7
b0
Real-time output control register (Address 6216)
0 0
P60–P67 pins functions as the programmable I/O port.
Pulse output mode select bit
0 : Pulse mode 0
1 : Pulse mode 1
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When pulse mode 0
is selected
When pulse mode 1
is selected
Setting output data
Setting output data
b7
b0
b7
Pulse output data register 0
(Address 1A16)
RTP00
RTP01
RTP02
RTP03
0 : “L” level
1 : “H” level
b7
b7
b0
✕
✕
Pulse output data register 1
(Address 1C16)
RTP10
RTP11
RTP12
RTP13
b0
✕
0 : “L” level
1 : “H” level
✕ : It may be either “0” or “1.”
✕
Pulse output data register 0
(Address 1A16)
RTP00
0 : “L” level
RTP01
1 : “H” level
✕ : It may be either “0” or “1.”
b0
Pulse output data register 1
(Address 1C16)
RTP02
RTP03
RTP10
RTP11
RTP12
RTP13
0 : “L” level
1 : “H” level
Continue to “Figure 10.3.2”
Fig. 10.3.1 Initial setting example for registers relevant to real-time output (1)
7721 Group User’s Manual
10–7
REAL-TIME OUTPUT
10.3 Setting of real-time output
From preceding “Figure 10.3.1”
Processing of avoiding undefined output before starting pulse output (Note)
b7
0 0
b0
0
0
0
0
0
Timer A0 mode register (Address 5616)
Timer A1 mode register (Address 5716)
0
Select of count source f2
(b15)
b7
(b8)
b0 b7
b0
0016
Timer A0 register (Addresses 4716, 4616)
Timer A1 register (Addresses 4916, 4816)
0016
Set to “000016”
b7
b0
0
0
0
Timer A0 interrupt control register (Address 7516)
Timer A1 interrupt control register (Address 7616)
0
Interrupt disabled
No interrupt request
b7
b0
Count start register (Address 4016)
Timer A0 count start bit
1 : Start counting
Timer A1 count start bit
✽ When Timer A0 or A1 underflows, the contents of the pulse output data register 0 or 1 are output from the flip-flop.
b7
b0
Count start register (Address 4016)
Timer A0 count start bit
0 : Stop counting
Timer A1 count start bit
Note: This processing can be neglected if the system is not
affected by undefined output.
Setting Timers A0, A1
b7
b0
0
0
0
0
0
Timer A0 mode register (Address 5616)
Timer A1 mode register (Address 5716)
0
Count source select bits
b7 b6
0
0
1
1
(b15)
b7
0 : f2
1 : f16
0 : f64
1 : f512
(b8)
b0 b7
0016
b0
0016
Timer A0 register (Addresses 4716, 4616)
Timer A1 register (Addresses 4916, 4816)
Can be set to “000016”–“FFFF16” (n)
b7
b0
0
Timer A0 interrupt control register (Address 7516)
Timer A1 interrupt control register (Address 7616)
Interrupt priority level select bits
When using interrupts, set these bits to one of levels 1 to 7.
When disabling interrupts, set these bits to level 0.
Continue to “Figure 10.3.3”
Fig. 10.3.2 Initial setting example for registers relevant to real-time output (2)
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REAL-TIME OUTPUT
10.3 Setting of real-time output
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AAAAAAAAAAAA
AAA
AAA
AAA
Continue to “Figure 10.3.2”
When pulse mode 0
is selected
When pulse mode 1
is selected
Setting real-time output port
b7
Setting real-time output port
b0
0
b7
Real-time output control register
(Address 6216)
b0
1
Waveform output select bits
Real-time output control register
(Address 6216)
Waveform output select bits
b1 b0
b1 b0
0 1 : RTP00–RTP03
1 0 : RTP10–RTP13
1 1 : RTP00–RTP03 and
RTP10–RTP13
0 1 : RTP00, RTP01
1 0 : RTP02, RTP03 and
RTP10–RTP13
1 1 : RTP00–RTP03 and
RTP10–RTP13
Pulse mode 0
Pulse mode 1
Setting count start bit to “1”
b7
b0
Count start register (Address 4016)
Timer A0 count start bit
Timer A1 count start bit
Pulse output starts after overflow of Timer A0 or A1
Fig. 10.3.3 Initial setting example for registers relevant to real-time output (3)
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10–9
REAL-TIME OUTPUT
10.4 Real-time output operation
10.4 Real-time output operation
➀ When the timer Ai (i = 0, 1) count start bit is set to “1,” the counter starts counting of the count source.
➁ The contents of pulse output data register i are output from the pulse output pins at every underflow of
Timer Ai. The timer is reloaded with the contents of the reload register and continues counting.
➂ The timer Ai interrupt request bit is set to “1” when the counter underflows in ➁. The interrupt request
bit retains “1” until the interrupt request is accepted or it is cleared by software.
➃ Write the next output data into the pulse output data register i during the timer Ai interrupt routine or after
the recognition of the timer Ai interrupt request occurrence.
Counter contents
(Hex.)
Figure 10.4.1 shows an example of real-time output operation.
Starts counting
Starts pulse outputting
000316
000016
Contents of bits 3–0 of pulse
output data register 0
✽1
Undefined
✽1
00112
RTP03 output
Undefined
✽2
RTP02 output
Undefined
✽2
RTP01 output
Undefined
✽2
RTP00 output
Undefined
✽2
Timer A0 interrupt
request bit
✽1
01102
✽3
✽1
11002
✽3
✽1
10012
✽3
✽1
00112
✽3
✽3
✽1 : Written by software
✽2 : To avoid undefined output for these terms, follow the procedure “Processing of
avoiding undefined output before starting pulse output” in Figures 10.3.1 and 10.3.2.
✽3 : Cleared to “0” when interrupt request is accepted or cleared by software.
The above figure shows an example of he following conditions:
•Pulse mode 0 selected
•RTP00–RTP03 selected
•Timer A0 register set value n = 000316
Fig. 10.4.1 Example of real-time output operation
10–10
7721 Group User’s Manual
CHAPTER 11
SERIAL I/O
11.1 Overview
11.2 Block description
11.3 Clock synchronous serial I/O mode
[Precautions for clock synchronous
serial I/O mode]
11.4 Clock asynchronous serial I/O
(UART) mode
SERIAL I/O
11.1 Overview
11.1 Overview
Serial I/O consists of 2 channels: UART0 and UART1. They each have a transfer clock generating timer for
the exclusive use of them and can operate independently. UART0 and UART1 have the same functions.
UARTi (i = 0 and 1) has the following 2 operating modes:
(1) Clock synchronous serial I/O mode
Transmitter and receiver use the same clock as the transfer clock. Transfer data has a length of 8
bits.
(2) Clock asynchronous serial I/O (UART) mode
Transfer rate and transfer data format can arbitrarily be set. The user can select a transfer data
length of 7 bits, 8 bits, or 9 bits.
Figure 11.1.1 shows the transfer data formats in each operating mode.
●Clock synchronous serial I/O mode
Transfer data length of 8 bits
●UART mode
Transfer data length of 7 bits
Transfer data length of 8 bits
Transfer data length of 9 bits
Fig. 11.1.1 Transfer data formats in each operating mode
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SERIAL I/O
11.2 Block description
11.2 Block description
Figure 11.2.1 shows the block diagram of Serial I/O. Registers relevant to Serial I/O are described below.
Data bus (odd)
Data bus (even)
0
0
0
RxDi
0
0
0
0
D8 D 7 D 6 D5 D 4 D 3 D2 D 1 D 0
UARTi receive
buffer register
UARTi receive register
f2
f16
f64
f512
UART
1/16
BRG count source
select bits
BRGi
1 / (n+1)
Clock
synchronous
Clock
synchronous
Clock synchronous
(internal clock selected)
Transfer clock
Transmit control
circuit
Transfer clock
UART
1/16
1/2
Receive
control circuit
Clock synchronous
(internal clock selected)
UARTi transmit register
Clock synchronous
(external clock selected)
D8 D 7 D 6 D 5 D4 D 3 D 2 D1 D0
CLKi
CTSi / RTSi
TxDi
UARTi transmit
buffer register
Data bus (odd)
n: Values set in UARTi baud rate register (BRGi)
Data bus (even)
Fig. 11.2.1 Block diagram of Serial I/O
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SERIAL I/O
11.2 Block description
11.2.1 UARTi transmit/receive mode register
Figure 11.2.2 shows the structure of UARTi transmit/receive mode register. The serial I/O mode select bits
are used to select a UARTi’s operating mode. Bits 4 to 6 are described in section “11.4.2 Transfer data
format,” and bit 7 is done in section “11.4.8 Sleep mode.”
b7
b6
b5
b4
b3
b2
b1
b0
UART0 transmit/receive mode register (Address 3016)
UART1 transmit/receive mode register (Address 3816)
Bit
0
Functions
At reset
RW
0 0 0 : Serial I/O disabled
(P8 functions as a programmable
I/O port.)
0 0 1 : Clock synchronous serial I/O
mode
0 1 0 : Do not select.
0 1 1 : Do not select.
1 0 0 : UART mode
(Transfer data length = 7 bits)
1 0 1 : UART mode
(Transfer data length = 8 bits)
1 1 0 : UART mode
(Transfer data length = 9 bits)
1 1 1 : Do not select.
0
RW
0
RW
0
RW
Bit name
Serial I/O mode select bits
1
2
b2 b1 b0
3
Internal/External clock select bit
0 : Internal clock
1 : External clock
0
RW
4
Stop bit length select bit
(Valid in UART mode) (Note)
0 : One stop bit
1 : Two stop bits
0
RW
5
Odd/Even parity select bit
(Valid in UART mode when
parity enable bit is “1”) (Note)
0 : Odd parity
1 : Even parity
0
RW
6
Parity enable bit
(Valid in UART mode) (Note)
0 : Parity disabled
1 : Parity enabled
0
RW
7
Sleep select bit
(Valid in UART mode) (Note)
0 : Sleep mode terminated (Invalid)
1 : Sleep mode selected
0
RW
Note: Bits 4 to 6 are invalid in the clock synchronous serial I/O mode. (They may be either “0”
or “1.”) Additionally, fix bit 7 to “0.”
Fig. 11.2.2 Structure of UARTi transmit/receive mode register
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SERIAL I/O
11.2 Block description
(1) Internal/External clock select bit (bit 3)
■ Clock synchronous serial I/O mode
By clearing this bit to “0” in order to select an internal clock, the clock which is selected with the
BRG count source select bits (bits 0 and 1 at addresses 34 16, 3C16) becomes the count source of
the BRGi (described later). The BRGi’s output divided by 2 becomes the transfer clock. Additionally,
the transfer clock is output from the CLK i pin.
By setting this bit to “1” in order to select an external clock, the clock input to the CLKi pin
becomes the transfer clock.
■ UART mode
By clearing this bit to “0” in order to select an internal clock, the clock which is selected with the
BRG count source select bits (bits 0 and 1 at addresses 34 16, 3C16) becomes the count source of
the BRGi (described later). Then, the CLKi pin functions as a programmable I/O port.
By setting this bit to “1” in order to select an external clock, the clock input to the CLKi pin
becomes the count source of BRGi.
Always in the UART mode, the BRGi’s output divided by 16 becomes the transfer clock.
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SERIAL I/O
11.2 Block description
11.2.2 UARTi transmit/receive control register 0
Figure 11.2.3 shows the structure of UARTi transmit/receive control register 0. For bits 0 and 1, refer to
section “11.2.1 (1) Internal/External clock select bit (bit 3).”
b7
b6
b5
b4
b3
b2
b1
b0
UART0 transmit/receive control register 0 (Address 3416)
UART1 transmit/receive control register 0 (Address 3C16)
Bit
0
Functions
Bit name
BRG count source select bits
1
b1 b0
0 0 : f2
0 1 : f16
1 0 : f64
1 1 : f512
At reset
RW
0
RW
0
RW
2
CTS/RTS select bit
0 : CTS function selected
1 : RTS function selected
0
RW
3
Transmit register empty flag
0 : Data present in transmit register
(During transmission)
1 : No data present in transmit register
(Transmission completed)
1
RO
Undefined
–
7 to 4
Nothing is assigned.
Fig. 11.2.3 Structure of UARTi transmit/receive control register 0
____ ____
(1) CTS/RTS select bit (bit 2)
____
____
By clearing this bit to “0” in order to select the CTS function, pins P80 and P84 function as CTS input
pins, and the input signal of “L” level to these____
pins becomes one of the transmission conditions.
____
By setting this bit to “1” in order to select the RTS function, pins P80 and P8 4 become RTS output
____
pins. When the receive enable bit (bit 2 at addresses 3516, 3D16) is “0” (reception disabled), the RTS
output pin outputs “H” level.
____
In the clock synchronous serial I/O mode, the output level of the RTS pin becomes “L” when reception
conditions are satisfied, and it becomes “H” when reception
starts. Note that, when an internal clock
____
is selected____
(bit 3 at addresses 3016, 38 16 = “0”), the RTS output is undefined. Accordingly, do not
select the RTS function.
____
In the clock asynchronous serial I/O mode, the output level of the RTS pin becomes “L” when the
receive enable bit is set to “1.” It becomes “H” when reception starts and it becomes “L” when
reception is completed.
(2) Transmit register empty flag (bit 3)
This flag is cleared to “0” when the UARTi transmit buffer register’s contents are transferred to the
UARTi transmit register. When transmission is completed and the UARTi transmit register becomes
empty, this flag is set to “1.”
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SERIAL I/O
11.2 Block description
11.2.3 UARTi transmit/receive control register 1
Figure 11.2.4 shows the structure of UARTi transmit/receive control register 1. For bits 4 to 7, refer to
section “11.3.6 Processing on detecting overrun error” and “11.4.7 Processing on detecting error.”
b7
b6
b5
b4
b3
b2
b1
b0
UART0 transmit/receive control register 1 (Address 3516)
UART1 transmit/receive control register 1 (Address 3D16)
Bit
Functions
Bit name
At reset
RW
0
Transmit enable bit
0 : Transmission disabled
1 : Transmission enabled
0
RW
1
Transmit buffer empty flag
0 : Data present in transmit buffer
register
1 : No data present in transmit
buffer register
1
RO
2
Receive enable bit
0 : Reception disabled
1 : Reception enabled
0
RW
3
Receive complete flag
0 : No data present in receive
buffer register
1 : Data present in receive buffer
register
0
RO
4
Overrun error flag
(Note 1) 0 : No overrun error
1 : Overrun error detected
0
RO
5
Framing error flag (Notes 1, 2) 0 : No framing error
1 : Framing error detected
(Valid in UART mode)
0
RO
6
(Notes 1, 2) 0 : No parity error
Parity error flag
(Valid in UART mode)
1 : Parity error detected
0
RO
7
(Notes 1, 2) 0 : No error
Error sum flag
1 : Error detected
(Valid in UART mode)
0
RO
Notes 1: Bit 4 is cleared to “0” when the receive enable bit is cleared to “0” or when the serial
I/O mode select bits (bits 2 to 0 at addresses 3016, 3816) are cleared to “0002.”
Bits 5 and 6 are cleared to “0” when one of the following is performed:
•Clearing the receive enable bit to “0”
•Reading the low-order byte of the UARTi receive buffer register (addresses 3616, 3E16)
out
•Clearing the serial I/O mode select bits (bits 2 to 0 at addresses 3016, 3816) to “0002”
Bit 7 is cleared to “0” when all of bits 4 to 6 become “0.”
2: Bits 5 to 7 are invalid in the clock synchronous serial I/O mode.
Fig. 11.2.4 Structure of UARTi transmit/receive control register 1
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SERIAL I/O
11.2 Block description
(1) Transmit enable bit (bit 0)
By setting this bit to “1,” UARTi enters the transmission enable state. By clearing this bit to “0” during
transmission, UARTi enters the transmission disable state after the transmission which is in progress
at that time is completed.
(2) Transmit buffer empty flag (bit 1)
This flag is set to “1” when data set in the UARTi transmit buffer register is transferred from the
UARTi transmit buffer register to the UARTi transmit register. This flag is cleared to “0” when data
is set in the UARTi transmit buffer register.
(3) Receive enable bit (bit 2)
By setting this bit to “1,” UARTi enters the reception enable state. By clearing this bit to “0” during
reception, UARTi quits the reception immediately and enters the reception disable state.
(4) Receive complete flag (bit 3)
This flag is set to “1” when data is ready in the UARTi receive register and that is transferred to the
UARTi receive buffer register (i.e., when reception is completed). This flag is cleared to “0” when one
of the following is performed:
•Reading the low-order byte of the UARTi receive buffer register out
•Clearing the receive enable bit (bit 2) to “0”
•Clearing the serial I/O mode select bits (bits 2 to 0 at addresses 3016, 38 16 ) to “0002.”
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SERIAL I/O
11.2 Block description
11.2.4 UARTi transmit register and UARTi transmit buffer register
Figure 11.2.5 shows the block diagram for the transmitter; Figure 11.2.6 shows the structure of UARTi
transmit buffer register.
Data bus (odd)
Data bus (even)
D8
D7
D6
D5
D4
D3
D2
D1
SP : Stop bit
PAR : Parity bit
Parity
enabled
2SP
SP
SP
9-bit UART
Parity
disabled
UARTi transmit
buffer register
8-bit UART
9-bit UART
Clock sync.
UART
TxDi
PAR
1SP
D0
Clock sync.
7-bit UART
8-bit UART
Clock sync.
7-bit UART
UARTi transmit register
“0”
Fig. 11.2.5 Block diagram for transmitter
(b15)
(b8)
b7
b0
b7
b0
UART0 transmit buffer register (Addresses 3316, 3216)
UART1 transmit buffer register (Addresses 3B16, 3A16)
Bit
Functions
At reset
RW
8 to 0 Transmit data is set.
Undefined
WO
15 to 9 Nothing is assigned.
Undefined
–
Note: Use the LDM or STA instruction for writing to this register.
Fig. 11.2.6 Structure of UARTi transmit buffer register
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SERIAL I/O
11.2 Block description
Transmit data is set into the UARTi transmit buffer register. Set the transmit data into the low-order byte
of this register when the microcomputer operates in the clock synchronous serial I/O mode or when a 7bit or 8-bit length of transfer data is selected in the UART mode. When a 9-bit length of transfer data is
selected in the UART mode, set the transmit data into the UARTi transmit buffer register as follows:
•Bit 8 of the transmit data into bit 0 of high-order byte of this register.
•Bits 7 to 0 of the transmit data into the low-order byte of this register.
The transmit data which is set in the UARTi transmit buffer register is transferred to the UARTi transmit
register when the transmission conditions are satisfied, and then it is output from the TxDi pin synchronously
with the transfer clock. The UARTi transmit buffer register becomes empty when the data which is set in
the UARTi transmit buffer register is transferred to the UARTi transmit register. Accordingly, the user can
set the next transmit data.
When quitting the transmission which is in progress and setting the UARTi transmit buffer register again,
follow the procedure described bellow:
➀ Clear the serial I/O mode select bits (bits 2 to 0 at addresses 30 16, 38 16) to “000 2” (Serial I/O disabled).
➁ Set the serial I/O mode select bits again.
➂ Set the transmit enable bit (bit 0 at addresses 3516, 3D 16) to “1” (transmission enabled) and set transmit
data in the UARTi transmit buffer register.
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SERIAL I/O
11.2 Block description
11.2.5 UARTi receive register and UARTi receive buffer register
Figure 11.2.7 shows the block diagram for the receiver; Figure 11.2.8 shows the structure of UARTi receive
buffer register.
Data bus (odd)
Data bus (even)
0
0
0
SP : Stop bit
PAR : Parity bit
0
Parity
enabled
2SP
RxDi
0
SP
SP
UART
0
D8
9-bit UART
D7
D6
D5
D4
D3
D2
D1
D0
UARTi receive
buffer register
8-bit UART
9-bit UART
Clock sync.
PAR
Parity
disabled
1SP
0
Clock sync.
7-bit UART
8-bit UART
Clock sync.
7-bit UART
UARTi receive register
Fig. 11.2.7 Block diagram for receiver
(b15)
(b8)
b7
b0
b7
b0
UART0 receive buffer register (Addresses 3716, 3616)
UART1 receive buffer register (Addresses 3F16, 3E16)
Bit
Functions
8 to 0 Receive data is read out from here.
15 to 9 Nothing is assigned.
The value is “0” at reading.
At reset
RW
Undefined
RO
0
–
Fig. 11.2.8 Structure of UARTi receive buffer register
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SERIAL I/O
11.2 Block description
The UARTi receive register is used to convert serial data which is input to the RxDi pin into parallel data.
This register takes in the signal input to the RxDi pin in a unit of 1 bit synchronously with the transfer clock.
The UARTi receive buffer register is used to read out receive data. When reception is completed, the
receive data which is taken in the UARTi receive register is automatically transferred to the UARTi receive
buffer register. Note that the contents of the UARTi receive buffer register is updated when the next data
is ready in the UARTi receive register before the data which has been transferred to the UARTi receive
buffer register is read out. (i.e., an overrun error occurs.)
The UARTi receive buffer register is initialized by setting the receive enable bit (bit 2 at addresses 3516,
3D 16 ) to “1” after clearing it to “0.”
Figure 11.2.9 shows the contents of the UARTi receive buffer register when reception is completed.
Low-order byte
(addresses 3616, 3E16)
High-order byte
(addresses 3716, 3F16)
b7
In UART mode
(Transfer data length : 9 bits)
In clock synchronous
serial I/O mode
In UART mode
(Transfer data length : 8 bits)
In UART mode
(Transfer data length : 7 bits)
0
b0
0
0
0
0
0
b7
b0
0
Receive data (9 bits)
0
0
0
0
0
0
0
Same value as bit
7 in low-order byte
0
0
0
0
0
0
Receive data (8 bits)
0
Same value as bit
6 in low-order byte
Receive data (7 bits)
Fig. 11.2.9 Contents of UARTi receive buffer register when reception is completed
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SERIAL I/O
11.2 Block description
11.2.6 UARTi baud rate register (BRGi)
The UARTi baud rate register (BRGi) is an 8-bit timer exclusively used for UARTi to generate a transfer
clock. It has a reload register. Assuming that the value set in the BRGi is “n” (n = “0016” to “FF16”), the BRGi
divides the count source frequency by (n + 1).
In the clock synchronous serial I/O mode, the BRGi is valid when an internal clock is selected, and the
BRGi’s output divided by 2 becomes the transfer clock. In the UART mode, the BRGi is always valid, and
the BRGi’s output divided by 16 becomes the transfer clock.
The data which is written to the UARTi baud rate register (BRGi) is written to both the timer and the reload
register whether transmission/reception is in progress or not. Accordingly, writing to these register must be
performed while transmission/reception is stopped.
Figure 11.2.10 shows the structure of the UARTi baud rate register (BRGi); Figure 11.2.11 shows the block
diagram of transfer clock generating section.
b7
b0
UART0 baud rate register (Address 3116)
UART1 baud rate register (Address 3916)
Bit
Functions
7 to 0 Can be set to “0016” to “FF16.”
Assuming that the set value = n, BRGi
divides the count source frequency by (n + 1).
At reset
RW
Undefined
WO
Note: Writing to this register must be performed while the transmission/reception halts.
Use the LDM or STA instruction for writing to this register.
Fig. 11.2.10 Structure of UARTi baud rate register (BRGi)
<Clock synchronous serial I/O mode>
fi
1/2
BRGi
fEXT
Transmit control circuit
Transfer clock for transmit operation
Receive control circuit
Transfer clock for receive operation
<UART mode>
fi
fEXT
1/16
Transmit control circuit
Transfer clock for transmit operation
1/16
Receive control circuit
Transfer clock for receive operation
BRGi
fi : Clock selected by BRG count source select bits (f2, f16, f64, or f512)
fEXT : Clock input to CLKi pin (external clock)
Fig. 11.2.11 Block diagram of transfer clock generating section
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SERIAL I/O
11.2 Block description
11.2.7 UARTi transmit interrupt control and UARTi receive interrupt control registers
When using UARTi, 2 types of interrupts, which are UARTi transmit and UARTi receive interrupts, can be
used. Each interrupt has its corresponding interrupt control register. Figure 11.2.12 shows the structure of
UARTi transmit interrupt control and UARTi receive interrupt control registers.
For details about interrupts, refer to “CHAPTER 7. INTERRUPTS.”
b7
b6
b5
b4
b3
b2
b1
b0
UART0 transmit interrupt control register (Address 7116)
UART0 receive interrupt control register (Address 7216)
UART1 transmit interrupt control register (Address 7316)
UART1 receive interrupt control register (Address 7416)
Bit
Bit name
0
Interrupt priority level select bits
1
2
3
Interrupt request bit
Functions
At reset
RW
0 0 0 : Level 0 (Interrupt disabled)
0 0 1 : Level 1
Low level
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
High level
0
RW
0
RW
0
RW
0 : No interrupt requested
1 : Interrupt requested
0
RW
Undefined
–
b2 b1 b0
7 to 4 Nothing is assigned.
Fig. 11.2.12 Structure of UARTi transmit interrupt control and UARTi receive interrupt control registers
(1) Interrupt priority level select bits (bits 0 to 2)
These bits select a priority level of the UARTi transmit interrupt or UARTi receive interrupt. When
using UARTi transmit/receive interrupts, select one of the priority levels (1 to 7). When a UARTi
transmit/receive interrupt request occurs, its priority level is compared with the processor interrupt
priority level (IPL). The requested interrupt is enabled only when its priority level is higher than the
IPL. (However, this applies when the interrupt disable flag (I) = “0.”) To disable UARTi
transmit/receive interrupts, set these bits to “0002” (level 0).
(2) Interrupt request bit (bit 3)
The UARTi transmit interrupt request bit is set to “1” when data is transferred from the UARTi
transmit buffer register to the UARTi transmit register. The UARTi receive interrupt request bit is set
to “1” when data is transferred from the UARTi receive register to the UARTi receive buffer register.
(However, when an overrun error occurs, it does not change.)
Each interrupt request bit is automatically cleared to “0” when its corresponding interrupt request is
accepted. This bit can be set to “1” or “0” by software.
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SERIAL I/O
11.2 Block description
11.2.8 Port P8 direction register
I/O pins of UARTi are multiplexed with port P8. When using pins P82 and P8 6 as serial data input pins
to “0” to set these pins for the input
(RxD i), set the corresponding bits of the port P8 direction register
____ ____
mode. When using pins P8 0, P81, P83 to P85 and P8 7 as I/O pins (CTSi/RTSi, CLKi, TxD i) of UARTi, these
pins are forcibly set as I/O pins of UARTi regardless of the port P8 direction register’s contents. Figure
11.2.13 shows the relationship between the port P8 direction register and UARTi’s I/O pins. For details,
refer to the description of each operating mode.
b7
b6
b5
b4
b3
b2
b1
b0
Port P8 direction register (Address 1416)
Bit
Corresponding pin
0
CTS0/RTS0 pin
1
CLK0 pin
Functions
0 : Input mode
1 : Output mode
When using pins P82 and P86 as
serial data input pins (RxD0, RxD1),
set the corresponding bits to “0.”
At reset
RW
0
RW
0
RW
0
RW
0
RW
2
RxD0 pin
3
TxD0 pin
4
CTS1/RTS1 pin
0
RW
5
CLK1 pin
0
RW
6
RxD1 pin
0
RW
7
TxD1 pin
0
RW
Fig. 11.2.13 Relationship between port P8 direction register and UARTi’s I/O pins
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SERIAL I/O
11.3 Clock synchronous serial I/O mode
11.3 Clock synchronous serial I/O mode
Table 11.3.1 lists the performance overview in the clock synchronous serial I/O mode, and Table 11.3.2 lists
the functions of I/O pins in this mode.
Table 11.3.1 Performance overview in clock synchronous serial I/O mode
Item
Functions
Transfer data format
Transfer data has a length of 8 bits.
LSB first
Transfer rate When selecting internal clock
BRGi’s output divided by 2
When selecting external clock
Transmit/Receive control
____
Maximum 5 Mbps
____
CTS function or RTS function can be selected by software.
Table 11.3.2 Functions of I/O pins in clock synchronous serial I/O mode
Pin name
TxD i (P83, P8 7)
(Dummy data is output when performing only reception.)
(Note)
RxD i (P82, P8 6)
Method of selection
Functions
Serial data output
Serial data input
Port P8 direction register ✼1’s corresponding bit = “0”
(Can be used as an I/O port when performing only transmission.)
CLK i (P81, P8 5)
___
___
CTS i/RTSi
(P8 0, P8 4)
Transfer clock output
Transfer clock input
____
Internal/External clock select bit✼2 = “0”
Internal/External clock select bit = “1”
____ ____
CTS input
CTS/RTS select bit✼3 = “0”
____
____ ____
RTS output
CTS/RTS select bit = “1”
✼1
Port P8 direction register : address 1416
Internal/External clock select bit✼2: bit 3 at addresses 3016 , 3816
____ ____
CTS/RTS select bit✼3: bit 2 at addresses 3416, 3C 16
Note: The TxDi pin outputs “H” level until transmission starts after UARTi’s operating mode is selected.
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SERIAL I/O
11.3 Clock synchronous serial I/O mode
11.3.1 Transfer clock (Synchronizing clock)
Data transfer is performed synchronously with the transfer clock. For the transfer clock, the user can select
whether to generate the transfer clock internally or to input it from the external.
The transfer clock is generated by operation of the transmit control circuit. Accordingly, even when performing
only reception, set the transmit enable bit to “1,” and set dummy data in the UARTi transmit buffer register
in order to make the transmit control circuit active.
(1) Internal generation of transfer clock
The count source selected with the BRG count source select bits is divided by the BRGi, and the
BRGi output is further divided by 2. This is the transfer clock. The transfer clock is output from the
CLK i pin.
[Setting for relevant registers]
•Select an internal clock (bit 3 at addresses 3016, 38 16 = “0”).
•Select the BRGi’s count source (bits 0 and 1 at addresses 3416 , 3C 16)
•Set “division value – 1” (= n; 0016 to FF 16) to the BRGi (addresses 3116, 39 16 ).
Transfer clock’s frequency =
fi
2 (n+1)
f i: Frequency of BRGi’s count source (f2, f 16, f64 , f512)
•Enable transmission (bit 0 at addresses 3516, 3D 16 = “1”).
•Set data to the UARTi transmit buffer register (addresses 32 16, 3A 16)
[Pin’s state]
•A transfer clock is output from the CLKi pin.
•Serial data is output from the TxDi pin. (Dummy data is output when performing only reception.)
(2) Input of transfer clock from the external
A clock input from the CLK i pin is the transfer clock.
[Setting for relevant registers]
•Select an external clock (bit 3 at addresses 3016, 38 16 = “1”).
•Enable transmission (bit 0 at addresses 3516, 3D 16 = “1”).
•Set data to the UARTi transmit buffer register (addresses 3216, 3A 16).
[Pin’s state]
•A transfer clock is input from the CLK i pin.
•Serial data is output from the TxDi pin. (Dummy data is output when performing only reception.)
7721 Group User’s Manual
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SERIAL I/O
11.3 Clock synchronous serial I/O mode
11.3.2 Method of transmission
Figure 11.3.1 shows an initial setting example for relevant registers when transmitting. Transmission is
started when all of the following conditions (➀ to ➂) are satisfied. When an external clock is selected,
satisfy conditions ➀ to ➂ with the following precondition satisfied.
<Precondition>
The CLK i pin’s input is at “H” level
Note: When an internal clock is selected, the above precondition is ignored.
➀ Transmission is enabled (transmit enable bit = “1”).
➁ Transmit
data is present in the UARTi transmit____
buffer register (transmit buffer empty flag = “0”)
_____
➂ The CTSi pin’s input
is
at
“L”
level
(when
the
CTS
function selected).
____
Note: When the CTS function is not selected, condition ➂ is ignored.
____
____
By connecting the RTSi pin (receiver side) and CTSi pin (transmitter side), the timing of transmission and
that of reception can be matched. For details, refer to section “11.3.5 Receive operation.”
When using interrupts, it is necessary to set the relevant registers to enable interrupts. For details, refer
to “CHAPTER 7. INTERRUPTS.”
Figure 11.3.2 shows writing data after start of transmission, and Figure 11.3.3 shows detection of transmit
completion.
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SERIAL I/O
11.3 Clock synchronous serial I/O mode
UART0 transmit/receive mode register (Address 3016)
UART1 transmit/receive mode register (Address 3816)
b7
b0
0 ✕ ✕ ✕
0 0 1
Clock synchronous serial I/O mode
UART0 transmit buffer register (Address 3216)
UART1 transmit buffer register (Address 3A16)
Internal/External clock select bit
0: Internal clock
1: External clock
b7
b0
✕: It may be “0” or “1.”
Transmit data is set.
UART0 transmit/receive control register 0 (Address 3416)
UART1 transmit/receive control register 0 (Address 3C16)
b7
b0
UART0 transmit/receive control register 1 (Address 3516)
UART1 transmit/receive control register 1 (Address 3D16)
b7
b0
1
BRG count source select bits
b1 b0
Transmit enable bit
1: Transmission enabled
0 0 : f2
0 1 : f16
1 0 : f64
1 1 : f512
CTS / RTS select bit
0: CTS function selected
1: RTS function selected (CTS function disabled)
Transmission starts.
UART0 baud rate register (BRG0) (Address 3116)
UART1 baud rate register (BRG1) (Address 3916)
b7
(In the case of selecting the CTS function, transmission starts
when the CTSi pin’s input level is “L.”)
b0
Can be set to “0016” to “FF16.”
✽ Necessary only when internal clock is
selected.
UART0 transmit interrupt control register (Address 7116)
UART1 transmit interrupt control register (Address 7316)
b7
b0
Interrupt priority level select bits
When using interrupts, set these bits to one of
levels 1 to 7. When disabling interrupts, set
these bits to level 0.
Fig. 11.3.1 Initial setting example for relevant registers when transmitting
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SERIAL I/O
11.3 Clock synchronous serial I/O mode
[When using interrupts]
[When not using interrupts]
A UARTi transmit interrupt request occurs
when the UARTi transmit buffer register
becomes empty.
AAAAA
AAAAA
AAAAA
AAAAA
Checking state of UARTi transmit buffer register
UART0 transmit/receive control register 1 (Address 3516 )
UART1 transmit/receive control register 1 (Address 3D16 )
b7
b0
UARTi transmit interrupt
b0
1
Transmit buffer empty flag
0: Data present in transmit buffer register
1: No data present in transmit buffer register
(Writing of next transmit data is possible.)
Writing of next transmit data
UART0 transmit buffer register (Address 3216)
UART1 transmit buffer register (Address 3A16)
b7
Note : This figure shows the bits and registers required
for processing.
Refer to “Figures 11.3.5 and 11.3.6” for the
change of flag state and the occurrence timing of
an interrupt request.
b0
Set transmit data here.
Fig. 11.3.2 Writing data after start of transmission
[When using interrupts]
[When not using interrupts]
A UARTi transmit interrupt request
occurs when the transmission starts.
AAAAA
AAAAA
AAAAA
AAAAA
Checking start of transmission
UART0 transmit interrupt control register (Address 7116)
UART1 transmit interrupt control register (Address 7316)
b7
UARTi transmit interrupt
b0
Interrupt request bit
0: No interrupt requested
1: Interrupt requested
(Transmission has started.)
Checking completion of transmission
UART0 transmit/receive control register 0 (Address 3416)
UART1 transmit/receive control register 0 (Address 3C16)
AA
AA
b7
b0
Note :This figure shows the bits and registers required
for processing.
Refer to “Figures 11.3.5 and 11.3.6” for the
change of flag state and the occurrence timing of an
interrupt request.
Transmit register empty flag
0: During transmitting
1: Transmitting completed
Processing at completion of transmission
Fig. 11.3.3 Detection of transmit completion
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SERIAL I/O
11.3 Clock synchronous serial I/O mode
11.3.3 Transmit operation
When the transmit conditions described in section “11.3.2 Method of transmission” are satisfied in the
case of selecting an internal clock, a transfer clock is generated and the following operations are automatically
performed after 1 cycle of the transfer clock has passed. When the transmit conditions are satisfied and
the external clock is input to the CLKi pin in the case of selecting an external clock, the following operations
are automatically performed.
•The UARTi transmit buffer register’s contents are transferred to the UARTi transmit register.
•The transmit buffer empty flag is set to “1.”
•The transmit register empty flag is cleared to “0.”
•8 transfer clocks are generated (when an internal clock is selected).
•A UARTi transmit interrupt request occurs, and the interrupt request bit is set to “1.”
The transmit operations are described below:
➀ Data in the UARTi transmit register is transmitted from the TxD i pin synchronously with the falling edge
of the transfer clock.
➁ This data is transmitted bit by bit sequentially beginning with the least significant bit.
➂ When 1-byte data has been transmitted, the transmit register empty flag is set to “1.” This indicates the
completion of transmission.
Figure 11.3.4 shows the transmit operation.
When an internal clock is selected, when the transmit conditions for the next data are satisfied at completion
of the transmission, the transfer clock is generated continuously. Accordingly, when performing transmission
continuously, set the next transmit data to the UARTi transmit buffer register during transmission (when the
transmit register empty flag = “0”). When the transmit conditions for the next data are not satisfied, the
transfer clock stops at “H” level.
Figures 11.3.5 and 11.3.6 show examples of transmit timing.
b7
b0
Transmit data
UARTi transmit buffer register
MSB
UARTi transmit register
Transfer clock
LSB
D 7 D6
D5 D4 D3 D 2
D7 D 6
D1 D0
D5 D4 D 3 D2
D7 D6 D5 D 4
D1
D0
D3 D2
D1
D7 D6 D 5 D4
D3
D2
• • •
• • •
D7
Fig. 11.3.4 Transmit operation
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SERIAL I/O
11.3 Clock synchronous serial I/O mode
Tc
Transfer clock
Transmit enable bit
Data is set in UARTi transmit buffer register.
Transmit buffer
empty flag
UARTi transmit register
UARTi transmit buffer register.
TCLK
CTSi
Stopped because transmit enable bit = “0.”
Stopped because CTSi = “H.”
CLKi
TENDi
D0 D1 D2 D 3 D 4 D5 D6 D7
TxDi
D0 D1 D 2 D 3 D4 D5 D 6 D7
D0 D1 D 2 D3 D 4 D5 D6 D 7
Transmit register
empty flag
UARTi transmit
interrupt request bit
Cleared to “0” when interrupt request is accepted or cleared by software.
The above timing diagram applies when
the following conditions are satisfied:
● Internal clock selected
● CTS function selected
TENDi: Next transmit conditions are examined when this signal level is “H.”
(TENDi is an internal signal. Accordingly, it cannot be read from the external.)
Tc = TCLK = 2(n+1) /fi
fi: BRGi count source frequency (f 2, f16, f64, f512)
n: Value set in BRGi
____
Fig. 11.3.5 Example of transmit timing (when selecting internal clock, selecting CTS function)
Tc
Transfer clock
Transmit enable bit
Data is set in UARTi transmit buffer register.
Transmit buffer
empty flag
UARTi transmit register
UARTi transmit buffer register.
TCLK
Stopped because transmit enable bit = “0.”
CLKi
TENDi
TxDi
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4
D5 D6
D7
D0 D1 D2 D3 D4 D5 D6 D7
Transmit register
empty flag
UARTi transmit
interrupt request bit
Cleared to “0” when interrupt request is accepted or cleared by software.
The above timing diagram applies
when the following conditions are
satisfied:
● Internal clock selected
● CTS function not selected
TENDi: Next transmit conditions are examined when this signal level is “H.”
(TENDi is an internal signal. Accordingly, it cannot be read from the external.)
Tc = TCLK = 2(n+1) /fi
fi: BRGi count source frequency (f 2, f16, f64, f512)
n: Value set in BRGi
____
Fig. 11.3.6 Example of transmit timing (when selecting internal clock, not selecting CTS function)
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SERIAL I/O
11.3 Clock synchronous serial I/O mode
11.3.4 Method of reception
Figures 11.3.7 and 11.3.8 show initial setting examples for relevant registers when receiving. Reception is
started when all of the following conditions (➀ to ➂) are satisfied. When an external clock is selected,
satisfy conditions ➀ to ➂ with the following precondition satisfied.
<Precondition>
The CLK i pin’s input is at “H” level.
Note: When an internal clock is selected, the above precondition is ignored.
➀ Reception is enabled (receive enable bit = “1”).
➁ Transmission is enabled (transmit enable bit = “1”).
➂ Dummy data is present in the UARTi transmit buffer register (transmit buffer empty flag = “0”)
____
____
By connecting the RTSi pin (receiver side) and CTSi pin (transmitter side), the timing of transmission and
that of reception can be matched. For details, refer to section “11.3.5 Receive operation.”
When using interrupts, it is necessary to set the relevant registers to enable interrupts. For details, refer
to “CHAPTER 7. INTERRUPTS.”
Figure 11.3.9 shows processing after receive completion.
7721 Group User’s Manual
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SERIAL I/O
11.3 Clock synchronous serial I/O mode
UART0 transmit/receive mode register (Address 3016)
UART1 transmit/receive mode register (Address 3816)
b7
b0
0 ✕ ✕ ✕
0 0 1
Clock synchronous serial I/O mode
Internal/External clock select bit
0: Internal clock
1: External clock
✕: It may be “0” or “1.”
UART0 transmit/receive control register 0 (Address 3416)
UART1 transmit/receive control register 0 (Address 3C16)
b7
b0
BRG count source select bits
b1 b0
0 0 : f2
0 1 : f16
1 0 : f64
1 1 : f512
CTS / RTS select bit
0: CTS function selected
1: RTS function selected
UART0 baud rate register (BRG0) (Address 3116)
UART1 baud rate register (BRG1) (Address 3916)
b7
b0
Can be set to 0016 to FF16 .
✽ Necessary only when an internal clock is selected.
Continued to Figure 11.3.8 on next page.
Fig. 11.3.7 Initial setting example for relevant registers when receiving (1)
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SERIAL I/O
11.3 Clock synchronous serial I/O mode
From preceding Figure 11.3.7
Port P8 direction register (Address 1416)
b7
b0
0
0
RXD0 pin
RXD1 pin
UART0 receive interrupt control register (Address 7216)
UART1 receive interrupt control register (Address 7416)
b7
b0
Interrupt priority level select bits
When using interrupts, set these bits to one of levels 1 to 7.
When disabling interrupts, set these bits to level 0.
UART0 transmit buffer register (Address 3216)
UART1 transmit buffer register (Address 3A16)
b7
b0
Set dummy data here.
UART0 transmit/receive control register 1 (Address 3516)
UART1 transmit/receive control register 1 (Address 3D16)
b7
b0
1
1
Transmit enable bit
1 : Transmission enabled
Receive enable bit
1 : Reception enabled
AAA
AAA
AAA
Note: Set the receive enable bit and the transmit enable bit
to “1” simultaneously.
Reception starts.
Fig. 11.3.8 Initial setting example for relevant registers when receiving (2)
7721 Group User’s Manual
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SERIAL I/O
11.3 Clock synchronous serial I/O mode
[When using interrupts]
[When not using interrupts]
AAA
AAA
AAA
A UARTi receive interrupt request occurs
when reception is completed.
Checking completion of reception
UART0 transmit/receive control register 1 (Address 3516)
UART1 transmit/receive control register 1 (Address 3D16)
b7
UARTi receive interrupt
b0
1
1
Receive complete flag
0: Reception not completed
1: Reception completed
Reading of receive data
UART0 receive buffer register (Address 3616)
UART1 receive buffer register (Address 3E16)
b0
b7
Receive data is read out from here.
Checking error
UART0 transmit/receive control register 1 (Address 3516)
UART1 transmit/receive control register 1 (Address 3D16)
b0
b7
1
1
Overrun error flag
0: No overrun error
1: Overrun error detected
Processing after reading out receive data
Note : This figure shows the bits and registers required
for processing.
Refer to “Figure 11.3.12” for the change of flag
state and the occurrence timing of an interrupt
request.
Fig. 11.3.9 Processing after receive completion
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SERIAL I/O
11.3 Clock synchronous serial I/O mode
11.3.5 Receive operation
In the case of selecting an internal clock, when the receive conditions described in section “11.3.4 Method
of reception” are satisfied, a transfer clock is generated and the reception is started after 1 cycle of the
transfer clock has passed.
In the case of selecting an external clock, when the receive conditions are satisfied, the UARTi enters the
receive enable state and reception is started by ____
input of an external clock to the CLKi pin.
In the case
of selecting an external clock and the RTS function, when the UARTi enters the receive enable
____
state, the RTSi pin’s output
level becomes “L” to inform the transmitter side that reception is enabled.
When
____
____
reception
is
started,
the
RTS
i
pin’s
output
level
becomes
“H.”
Accordingly,
by
connecting
the
RTS
i
pin
to
____
the CTSi pin of the transmitter side, the timing
of
transmission
and
that
of
reception
can
be
matched.
When
____
____
an internal clock is selected, do not use the RTS function. It is because the RTS output becomes undefined.
Figure 11.3.10 shows a connection example.
The receive operations are described below:
➀ The input signal of the RxD i pin is taken into the most significant bit of the UARTi receive register
synchronously with the rising edge of the transfer clock.
➁ The contents of the UARTi receive register are shifted by 1 bit to the right.
➂ Steps ➀ and ➁ are repeated at each rising edge of the transfer clock.
➃ When 1-byte data is prepared in the UARTi receive register, the contents of this register are transferred
to the UARTi receive buffer register.
➄ Simultaneously with step ➃, the receive complete flag is set to “1,” and a UARTi receive interrupt request
occurs and its interrupt request bit is set to “1.”
The receive complete
flag is cleared to “0” when the low-order byte of the UARTi receive buffer register
____
is read
out. The RTSi pin outputs “H” level until the receive conditions are next satisfied (when selecting
____
the RTS function). Figure 11.3.11 shows the receive operation, and Figure 11.3.12 shows an example of
receive timing (when selecting an external clock).
Transmitter side
Receiver side
TxDi
TxDi
RxDi
RxDi
CLKi
CLKi
CTSi
RTSi
Fig. 11.3.10 Connection example
7721 Group User’s Manual
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SERIAL I/O
11.3 Clock synchronous serial I/O mode
LSB
MSB
UARTi receive register
Transfer clock
D0
D1 D0
D 2 D1
D0
•
•
•
•
•
•
D7 D6
D5 D4 D3 D2
b7
D1 D0
b0
UARTi receive buffer register
Receive data
Fig. 11.3.11 Receive operation
Receive enable bit
Transmit enable bit
Dummy data is set to UARTi transmit buffer register.
Transmit buffer
empty flag
UARTi transmit register¨← UARTi transmit buffer register
RTSi
1/fEXT
CLKi
Received data taken in
RxDi
D0 D1 D2 D3 D4 D5 D6 D7
D0
D1 D2 D3
UARTi receive register → UARTi receive buffer register
D4 D5
UARTi receive buffer register is read out.
Receive complete flag
UARTi receive
interrupt request bit
The above timing diagram applies when the following
setting conditions are satisfied:
● External clock selected
● RTS function selected
fEXT: Frequency of external clock
Cleared to “0” when interrupt request is accepted or
cleared by software.
: When the CLKi pin’s input level is “H,” satisfy the
following conditions:
● Transmit enable bit → “1”
● Receive enable bit → “1”
● Writing of dummy data to UARTi transmit
buffer register
Fig. 11.3.12 Example of receive timing (when selecting external clock)
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SERIAL I/O
11.3 Clock synchronous serial I/O mode
11.3.6 Processing on detecting overrun error
In the clock synchronous serial I/O mode, an overrun error can be detected.
An overrun error occurs when the next data is prepared in the UARTi receive register with the receive
complete flag = “1” (data is present in the UARTi receive buffer register) and next data is transferred to
the UARTi receive buffer register, in other words, when the next data is prepared before reading out the
contents of the UARTi receive buffer register. When an overrun error occurs, the next receive data is
written into the UARTi receive buffer register, and the UARTi receive interrupt request bit is not changed.
An overrun error is detected when data is transferred from the UARTi receive register to the UARTi receive
buffer register and the overrun error flag is set to “1.” The overrun error flag is cleared to “0” by clearing
the serial I/O mode select bits to “0002” or clearing the receive enable bit to “0.”
When an overrun error occurs during reception, initialize the overrun error flag and the UARTi receive
buffer register before performing reception again. When it is necessary to perform retransmission owing to
an overrun error which occurs in the receiver side, set the UARTi transmit buffer register again before
starting transmission again.
The method of initializing the UARTi receive buffer register and that of setting the UARTi transmit buffer
register again are described below.
(1) Method of initializing UARTi receive buffer register
➀ Clear the receive enable bit to “0” (Reception disabled).
➁ Set the receive enable bit to “1” again (Reception enabled).
(2) Method of setting UARTi transmit buffer register again
➀ Clear the serial I/O mode select bits to “000 2” (Serial I/O invalid).
➁ Set the serial I/O mode select bits to “001 2” again.
➂ Set the transmit enable bit to “1” (Transmission enabled), and set the transmit data to the UARTi
transmit buffer register.
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SERIAL I/O
11.3 Clock synchronous serial I/O mode
[Precautions for clock synchronous serial I/O mode]
1. The transfer clock is generated by operation of the transmit control circuit. Accordingly, even when
performing only reception, transmit operation (setting for transmission) must be performed. In this case,
dummy data is output from the TxD i pin.
2. When receiving, simultaneously set the receive enable bit and the transmit enable bit to “1.”
3. When receiving data, write dummy data to the low-order byte of the UARTi transmit buffer register for
each reception of 1-byte data.
4. When selecting an external clock, satisfy the following 3 conditions with the input to the CLKi pin = “H”
level.
<When transmitting>
➀ Set the transmit enable bit to “1.”
➁ Write transmit data to____
the UARTi transmit buffer register.
____
➂ Input “L” level to the CTS i pin (when selecting the CTS function).
<When receiving>
➀ Set the receive enable bit to “1.”
➁ Set the transmit enable bit to “1.”
➂ Write dummy data to the UARTi transmit buffer register.
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SERIAL I/O
11.4 Clock asynchronous serial I/O (UART) mode
11.4 Clock asynchronous serial I/O (UART) mode
Table 11.4.1 lists the performance overview in the UART mode, and Table 11.4.2 lists the functions of
I/O pins in this mode.
Table 11.4.1 Performance overview in UART mode
Item
Functions
Transfer data
Start bit
1 bit
format
Character bit (Transfer data)
Parity bit
7 bits, 8 bits, or 9 bits
Stop bit
1 bit or 2 bits
When selecting internal clock
When selecting external clock
BRGi’s output divided by 16
Transfer rate
Error detection
0 bit or 1 bit (Odd or even can be selected.)
Maximum 312.5 kbps
4 types (Overrun, Framing, Parity, and Summing)
Presence of error can be detected only by checking error sum flag.
Table 11.4.2 Functions of I/O pins in UART mode
Functions
Pin name
Method of selection
TxDi (P83, P87) (Note 1) Serial data output
(Cannot be used as a programmable I/O port even when
performing only reception.)
RxD i (P8 2, P8 6)
Serial data input
Port P8 direction register ✼1’s corresponding bit = “0”
(Can be used as a programmable I/O port when performing
only transmission.)
CLKi (P8 1, P8 5)
____ ____
CTSi/ RTSi (P8 0, P8 4)
(Note 2)
Programmable I/O port Internal/External clock select bit ✼2 = “0”
Internal/External
clock select bit = “1”
BRGi’s count source input ____
____
____
CTS input
____
RTS output
CTS/RTS function select bit ✼3 = “0”
CTS/RTS function select bit = “1”
____ ____
Port P8 direction register ✼1: address 14 16
Internal/External clock select bit✼2: bit 3 at addresses 3016, 38 16
____ ____
CTS/RTS select bit✼3: bit 2 at addresses 34 16, 3C 16
Notes 1: The TxDi pin outputs “H” level while transmission is not performed after selecting UARTi’s operating
mode.____ ____
2: The CTS
i /RTS i pin can be used as___
an input port when performing only reception and not using
___
the RTS function (when selecting CTS function).
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SERIAL I/O
11.4 Clock asynchronous serial I/O (UART) mode
11.4.1 Transfer rate (Frequency of transfer clock)
The transfer rate is determined by the BRGi (addresses 3116, 39 16).
When setting “n” into BRGi, BRGi divides the count source frequency by (n + 1). The BRGi’s output is
further divided by 16, and the resultant clock becomes the transfer clock. Accordingly, “n” is expressed by
the following formula.
n =
F
16 ✕ B
n: Value set in BRGi (0016 to FF 16)
F: BRGi’s count source frequency (Hz)
B: Transfer rate (bps)
— 1
An internal clock or an external clock can be selected as the BRGi’s count source with the internal/external
clock select bit (bit 3 at addresses 30 16, 38 16). When an internal clock is selected, the clock selected with
the BRG count source select bits (bits 0 and 1 at addresses 34 16, 3C16) becomes the BRGi’s count source.
When an external clock is selected, the clock input to the CLK i pin becomes the BRGi’s count source.
Set the same transfer rate for both transmitter and receiver sides. Tables 11.4.3 and 11.4.4 list the setting
examples of transfer rate.
Table 11.4.3 Setting examples of transfer rate (1)
f(X IN) = 24.576 MHz
Transfer
Actual time
BRGi’s set
BRGi’s
rate (bps)
(bps)
value : n
count source
BRGi’s
count source
f(X IN) = 25 MHz
BRGi’s set
Actual time
value : n
(bps)
80 (50 16)
301.41
f 64
79 (4F 16)
300.00
f 64
600
f 16
159 (9F 16)
600.00
f 16
162 (A2 16)
599.12
1200
f 16
f 16
79 (4F 16)
1200.00
f 16
80 (50 16)
1205.63
39 (2716)
2400.00
f 16
40 (28 16)
2381.86
4800
9600
f2
159 (9F16)
4792.94
79 (4F 16)
f2
f2
162 (A2 16)
f2
4800.00
9600.00
80 (50 16)
9645.06
14400
f2
52 (3416)
14490.57
f2
53 (35 16)
19200
f2
39 (2716)
19200.00
f2
40 (28 16)
14467.59
19054.58
f2
24 (18 16)
31250.00
300
2400
31250
38400
f2
19 (1316)
38400.00
Table 11.4.4 Setting examples of transfer rate (2)
Transfer
rate (bps)
300
600
f(X IN) = 22.1184 MHz
Actual time
BRGi’s set
value : n
(bps)
count source
300.00
71 (4716)
f 64
BRGi’s
f 16
143 (8F16)
600.00
1200
f 16
71 (4716)
1200.00
2400
f 16
35 (2316)
2400.00
4800
f2
143 (8F16)
4800.00
9600
f2
f2
71 (4716)
47 (2F 16)
9600.00
14400.00
f2
35 (2316)
19200.00
28800
f2
23 (1716)
28800.00
31250
f2
21 (1516)
31418.18
38400
f2
17 (1116)
38400.00
57600
f2
f2
11 (0B 16)
5 (05 16)
57600.00
115200.00
f2
2 (02 16)
230400.00
14400
19200
115200
230400
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SERIAL I/O
11.4 Clock asynchronous serial I/O (UART) mode
11.4.2 Transfer data format
The transfer data format can be selected from formats shown in Figure 11.4.1. Bits 4 to 6 at addresses
3016 and 3816 select the transfer data format. (Refer to “Figure 11.2.2.”) Set the same transfer data format
for both transmitter and receiver sides.
Figure 11.4.2 shows an example of transfer data format. Table 11.4.5 lists each bit in transmit data.
Transfer data length of 7 bits
1ST—7DATA
1SP
1ST—7DATA
2SP
1ST—7DATA—1PAR— 1SP
1ST—7DATA—1PAR— 2SP
Transfer data length of 8 bits
1ST—8DATA
1SP
1ST—8DATA
2SP
1ST—8DATA—1PAR— 1SP
1ST—8DATA—1PAR— 2SP
Transfer data length of 9 bits
1ST—9DATA
1SP
1ST—9DATA
2SP
1ST—9DATA—1PAR— 1SP
1ST—9DATA—1PAR— 2SP
ST
DATA
PAR
SP
: Start bit
: Character bit (Transfer data)
: Parity bit
: Stop bit
Fig. 11.4.1 Transfer data format
•For the case where 1ST–8DATA–1PAR–1SP
Time
Transmit/Receive data
Next transmit/receive data
(When continuously
transferring)
DATA (8 bits)
ST
LSB
MSB PAR
SP
ST
Fig. 11.4.2 Example of transfer data format
Table 11.4.5 Each bit in transmit data
Name
ST
Functions
Start bit
“L” signal equivalent to 1 character bit which is added immediately before the
character bits. It indicates start of data transmission.
DATA
Transmit data which is set in the UARTi transmit buffer register.
Character bit
PAR
Parity bit
SP
Stop bit
A signal that is added immediately after the character bits in order to improve data
reliability. The level of this signal changes according to selection of odd/even parity
in such a way that the sum of “1”s in this bit and character bits is always an odd
or even number.
“H” level signal equivalent to 1 or 2 character bits which is added immediately after
the character bits (or parity bit when parity is enabled). It indicates finish of data
transmission.
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SERIAL I/O
11.4 Clock asynchronous serial I/O (UART) mode
11.4.3 Method of transmission
Figure 11.4.3 shows an initial setting example for relevant registers when transmitting.
The difference due to selection of transfer data length (7 bits, 8 bits, or 9 bits) is only that data length.
When selecting a 7- or 8-bit data length, set the transmit data into the low-order byte of the UARTi transmit
buffer register. When selecting a 9-bit data length, set the transmit data into the low-order byte and bit 0
of the high-order byte.
Transmission is started when all of the following conditions (➀ to ➂) are satisfied:
➀ Transmit is enabled (transmit enable bit = “1”).
➁ Transmit
data is present in the UARTi transmit____
buffer register (transmit buffer empty flag = “0”).
____
➂ The CTSi pin’s input
is at “L” level (when the CTS function selected).
____
Note: When the CTS function is not selected, condition ➂ is ignored.
____
____
By connecting the RTSi pin (receiver side) and CTSi pin (transmitter side), the timing of transmission and
that of reception can be matched. For details, refer to section “11.4.6 Receive operation.”
When using interrupts, it is necessary to set the relevant registers to enable interrupts. For details, refer
to “CHAPTER 7. INTERRUPTS.”
Figure 11.4.4 shows writing data after start of transmission, and Figure 11.4.5 shows detection of transmit
completion.
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SERIAL I/O
11.4 Clock asynchronous serial I/O (UART) mode
UART0 transmit/receive mode register (Address 3016)
UART1 transmit/receive mode register (Address 3816)
b7
b0
UART0 baud rate register (BRG0) (Address 3116)
UART1 baud rate register (BRG1) (Address 3916
1
b7
b2 b1 b0
b0
1 0 0: UART mode (7 bits)
1 0 1: UART mode (8 bits)
1 1 0: UART mode (9 bits)
Can be set to 0016 to FF16.
Internal/External clock select bit
0: Internal clock
1: External clock
Stop bit length select bit
0: 1 stop bit
1: 2 stop bits
UART0 transmit interrupt control register (Address 7116)
UART1 transmit interrupt control register (Address 7316)
b7
b0
Odd/Even parity select bit
0: Odd parity
1: Even parity
Interrupt priority level select bits
When using interrupts, set these bits
to one of levels 1 to 7.
When disabling interrupts, set these
bits to level 0.
Parity enable bit
0: Parity disabled
1: Parity enabled
Sleep select bit
0: Sleep mode terminated (Invalid)
1: Sleep mode selected
UART0 transmit buffer register (Addresses 3316, 3216)
UART1 transmit buffer register (Addresses 3B16, 3A16)
b15
b8 b7
b0
UART0 transmit/receive control register 0 (Address 3416)
UART1 transmit/receive control register 0 (Address 3C16)
b7
Set transmit data here.
b0
BRG count source select bits
b1 b0
0
0
1
1
UART0 transmit/receive control register 1 (Address 3516)
UART1 transmit/receive control register 1 (Address 3D16)
0: f2
1: f16
0: f64
1: f512
b7
b0
1
CTS/RTS select bit
0: CTS function selected
1: RTS function selected (CTS
function disabled)
Transmit enable bit
1: Transmission enabled
Transmission starts.
(In the case of selecting the CTS function, transmission
starts when the CTSi pin’s input level is “L.”)
Fig. 11.4.3 Initial setting example for relevant registers when transmitting
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SERIAL I/O
11.4 Clock asynchronous serial I/O (UART) mode
[When using interrupts]
[When not using interrupts]
A UARTi transmit interrupt request occurs
when the UARTi transmit buffer register
becomes empty.
AAAA
AAAA
AAAA
Checking state of UARTi transmit buffer register
UART0 transmit/receive control register 1 (Address 3516)
UART1 transmit/receive control register 1 (Address 3D16)
b7
b0
UARTi transmit interrupt
b0
1
Transmit buffer empty flag
0: Data present in transmit buffer register
1: No data present in transmit buffer register
(Writing of next transmit data is possible.)
Writing of next transmit data
UART0 transmit buffer register (Addresses 3316, 3216)
UART1 transmit buffer register (Addresses 3B16, 3A16)
b15
b8 b7
Note : This figure shows the bits and registers
required for processing.
Refer to “Figures 11.4.6 to 11.4.8” for the
change of flag state and the occurrence
timing of an interrupt request.
b0
Set transmit data here.
Fig. 11.4.4 Writing data after start of transmission
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SERIAL I/O
11.4 Clock asynchronous serial I/O (UART) mode
[When using interrupts]
[When not using interrupts]
A UARTi transmit interrupt request
occurs when transmission starts.
AAA
AAA
Checking start of transmission
UART0 transmit interrupt control register (Address 7116)
UART1 transmit interrupt control register (Address 7316)
b7
UARTi transmit interrupt
b0
Interrupt request bit
0: No interrupt requested
1: Interrupt requested
(Transmission has started.)
Checking completion of transmission.
UART0 transmit/receive control register 0 (Address 3416)
UART1 transmit/receive control register 0 (Address 3C16)
b7
b0
Note : This figure shows the bits and registers required
for processing.
Refer to “Figures 11.4.6 to 11.4.8” for the
change of flag state and the occurrence timing
of an interrupt request.
Transmit register empty flag
0: During transmission
1: Transmission completed
Processing at completion of transmission
Fig. 11.4.5 Detection of transmit completion
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SERIAL I/O
11.4 Clock asynchronous serial I/O (UART) mode
11.4.4 Transmit operation
When the receive conditions described in section “11.4.3 Method of transmission” are satisfied, a transfer
clock is generated and the following operations are automatically performed after 1 cycle of the transfer
clock has passed.
•The UARTi transmit buffer register’s contents are transferred to the UARTi transmit register.
•The transmit buffer empty flag is set to “1.”
•The transmit register empty flag is cleared to “0.”
•A UARTi transmit interrupt request occurs and the interrupt request bit is set to “1.”
The transmit operations are described below:
➀ Data in the UARTi transmit register is transmitted from the TxD i pin.
➁ This data is transmitted bit by bit sequentially in order of ST→DATA (LSB)→•••→DATA (MSB)→PAR
→SP according to the transfer data format.
➂ The transmit register empty flag is set to “1” at the center of the stop bit (or the second stop bit when
selecting 2-stop bits), indicating completion of transmission. Additionally, whether the transmit conditions
for the next data are satisfied or not is examined.
When the transmit conditions for the next data are satisfied in step ➂, the start bit is generated following
the stop bit, and the next data is transmitted. When performing transmission continuously, set the next
transmit data in the UARTi transmit buffer register during transmission (when the transmit register empty
flag = “0”). When the transmit conditions for the next data are not satisfied, the TxDi pin outputs “H” level
and the transfer clock stops.
Figures 11.4.6 and 11.4.7 show examples of transmit timing when the transfer data length = 8 bits, and
Figure 11.4.8 shows an example of transmit timing when the transfer data length = 9 bits.
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11.4 Clock asynchronous serial I/O (UART) mode
Tc
Transfer clock
Transmit enable bit
Data is set in UARTi transmit buffer register.
Transmit buffer
empty flag
UARTi transmit register
UARTi transmit buffer register
TENDi
Stopped because transmit enable bit = “0”
Parity bit Stop bit
Start bit
TxDi
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP ST D0 D1 D2 D3 D4 D5 D6 D7
P
ST D0 D1
SP
Transmit register
empty flag
UARTi transmit
interrupt request bit
Cleared to “0” when interrupt request is accepted or cleared by software.
The above timing diagram applies when
the following conditions are satisfied:
● Parity enabled
● 1 stop bit
● CTS function not selected
TENDi: Next transmit conditions are examined when this signal level is “H.”
(TENDi is an internal signal. Accordingly, it cannot be read from the external.)
Tc: 16(n + 1)/fi or 16(n + 1)/fEXT
fi: BRGi’s count source frequency (f2, f16, f64, f512)
fEXT: BRGi’s count source frequency (external clock)
n: Value set in BRGi
Fig. 11.4.6 Example of transmit timing when ____
transfer data length = 8 bits (when parity enabled,
selecting 1 stop bit, not selecting CTS function)
Tc
Transfer clock
Transmit enable bit
Data is set in UARTi transmit buffer register.
Transmit buffer
empty flag
UARTi transmit register
UARTi transmit buffer register
CTSi
TENDi
Start bit
TxDi
Parity Stop
bit bit
ST D0 D1 D2 D3 D4 D5 D6 D7
P SP
Stopped because transmit
enable bit = “0”
Stopped because CTS = “H”
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
ST D0 D1
Transmit register
empty flag
UARTi transmit
interrupt request bit
Cleared to “0” when interrupt request is accepted or cleared by software.
The above timing diagram applies
when the following conditions are
satisfied:
● Parity enabled
● 1 stop bit
● CTS function selected
TENDi: Next transmit conditions are examined when this signal level is “H.”
(TENDi is an internal signal. Accordingly, it cannot be read from the external.)
Tc = 16(n + 1)/fi or 16(n + 1)/fEXT
fi: BRGi’s count source frequency (f2, f16, f64, f512)
fEXT: BRGi’s count source frequency (external clock)
n: Value set in BRGi
Fig. 11.4.7 Example of transmit timing when
transfer data length = 8 bits (when parity enabled,
____
selecting 1 stop bit, selecting CTS function)
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SERIAL I/O
11.4 Clock asynchronous serial I/O (UART) mode
Tc
Transfer clock
Transmit enable bit
Data is set in UARTi transmit buffer register.
Transmit buffer
empty flag
UARTi transmit register
UARTi transmit buffer register
TENDi
Start bit
TxDi
Stop bit Stop bit
Stopped because transmit enable bit = “0”
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP
ST D0 D1
Transmit register
empty flag
UARTi transmit
interrupt request bit
Cleared to “0” when interrupt request is accepted or cleared by software.
The above timing diagram applies when
the following conditions are satisfied:
● Parity disabled
● 2 stop bits
● CTS function disabled
TENDi: Next transmit conditions are examined when this signal level is “H.”
(TENDi is an internal signal. Accordingly, it cannot be read from the external.)
Tc = 16(n + 1)/fi or 16(n + 1)/fEXT
fi: BRGi count source frequency (f2, f16, f64, f512)
fEXT: BRGi count source frequency (external clock)
n: Value set in BRGi
Fig. 11.4.8 Example of transmit timing when transfer
data length = 9 bits (when parity disabled,
____
selecting 2 stop bits, not selecting CTS function)
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SERIAL I/O
11.4 Clock asynchronous serial I/O (UART) mode
11.4.5 Method of reception
Figure 11.4.9 shows an initial setting example for relevant registers when receiving. Reception is started
when all of the following conditions (➀ and ➁) are satisfied:
➀ Reception is enabled (receive enable bit = “1”).
➁ The start bit is detected.
____
____
By connecting the RTSi pin (receiver side) and CTSi pin (transmitter side), the timing of transmission and
that of reception can be matched. For details, refer to section “11.4.6 Receive operation.”
When using interrupts, it is necessary to set the relevant registers to enable interrupts. For details, refer
to “CHAPTER 7. INTERRUPTS.”
Figure 11.4.10 shows processing after receive completion.
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SERIAL I/O
11.4 Clock asynchronous serial I/O (UART) mode
UART0 transmit/receive mode register (Address 3016)
UART1 transmit/receive mode register (Address 3816)
b7
b0
1
UART0 baud rate register (BRG0) (Address 3116)
UART1 baud rate register (BRG1) (Address 3916)
b2b1b0
1 0 0: UART mode (7 bits)
1 0 1: UART mode (8 bits)
1 1 0: UART mode (9 bits)
b7
b0
Internal/External clock select bit
0: Internal clock
1: External clock
Can be set to 0016 to FF16.
Stop bit length select bit
0: 1 stop bit
1: 2 stop bits
Port P8 direction register (Address 1416)
b7
b0
0
0
Odd/Even parity select bit
0: Odd parity
1: Even parity
RxD0 pin
RxD1 pin
Parity enable bit
0: Parity disabled
1: Parity enabled
Sleep select bit
0: Sleep mode terminated (Invalid)
1: Sleep mode selected
UART0 receive interrupt control register (Address 7216)
UART1 receive interrupt control register (Address 7416)
b7
b0
Note: Set the transfer data format in
the same way as set on the
transmitter side.
Interrupt priority level select bits
When using interrupts, set these bits to
one of levels 1 to 7.
When disabling interrupts, set these bits
to level 0.
UART0 transmit/receive control register 0 (Address 34 16 )
UART1 transmit/receive control register 0 (Address 3C16 )
b7
b0
BRG count source select bits
b1b0
0 0 : f2
0 1 : f16
1 0 : f64
1 1 : f512
UART0 transmit/receive control register 1 (Address 3516)
UART1 transmit/receive control register 1 (Address 3D16)
b7
b0
1
Receive enable bit
1: Reception enabled
CTS/RTS select bit
0 : CTS function selected
1 : RTS function selected
Reception starts when the start
bit is detected.
Fig. 11.4.9 Initial setting example for relevant registers when receiving
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11.4 Clock asynchronous serial I/O (UART) mode
[When not using interrupts]
[When using interrupts]
AAA
AAA
A UARTi receive interrupt request
occurs when reception is completed.
Checking completion of reception
UART0 transmit/receive control register 1 (Address 3516)
UART1 transmit/receive control register 1 (Address 3D16)
b7
UARTi receive interrupt
b0
1
Receive complete flag
0 : Reception not completed
1 : Reception completed
Checking error
UART0 transmit/receive control register 1 (Address 3516)
UART1 transmit/receive control register 1 (Address 3D16)
b0
b7
1
Framing error flag
Parity error flag
Error sum flag
0 : No error
1 : Error detected
Reading of receive data
UART0 receive buffer register (Addresses 3716, 3616)
UART1 receive buffer register (Addresses 3F16, 3E16)
b15
b8 b7
b0
0 0 0 0 0 0 0
Read out receive data.
Checking error
UART0 transmit/receive control register 1 (Address 3516)
UART1 transmit/receive control register 1 (Address 3D16)
b0
b7
1
Overrun error flag
0 : No overrun error
1 : Overrun error detected
Processing after reading out receive data
Note : This figure shows the bits and registers required
for processing.
Refer to “Figure 11.4.12” for the change of flag
state and the occurrence timing of an interrupt
request.
Fig. 11.4.10 Processing after receive completion
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SERIAL I/O
11.4 Clock asynchronous serial I/O (UART) mode
11.4.6 Receive operation
When the receive enable bit is set to “1,” the UARTi enters the receive enable state. After this, reception
starts when ST is detected and
a transfer clock is generated.
____
____
In the case of selecting the RTS function, when the reception is enabled, the RTSi pin’s output level
____
becomes “L” to inform the transmitter side that reception is enabled.
When
reception
is
started,
the
RTSi
____
____
pin’s output level becomes “H.” Accordingly, by connecting the RTSi pin to the CTS i pin of the transmitter
side, the timing of transmission and that of reception can be matched. Figure 11.4.11 shows an connection
example.
The receive operation is described below.
➀ The input signal of the RxD i pin is taken into the most significant bit of the UARTi receive register
synchronously with the transfer clock’s rising edge.
➁ The contents of the UARTi receive register are shifted by 1 bit to the right.
➂ Steps ➀ and ➁ are repeated at each rising edge of the transfer clock.
➃ When one set of data has been prepared, in other words, when the shift has been performed several
times according to the selected data format, the UARTi receive register’s contents are transferred to the
UARTi receive buffer register.
➄ Simultaneously with step ➃, the receive complete flag is set to “1.” Additionally, a UARTi receive
interrupt request occurs and its interrupt request bit is set to “1.”
The receive complete
flag is cleared to “0” when the low-order byte of the UARTi receive buffer register
____
____
is read out. The RTSi pin’s output level becomes “L” simultaneously with step ➄ (when selecting the RTS
function). Figure 11.4.12 shows an example of receive timing when the transfer data length = 8 bits.
Transmitter side
Receiver side
TxDi
TxDi
RxDi
RxDi
CTSi
RTSi
Fig. 11.4.11 Connection example
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SERIAL I/O
11.4 Clock asynchronous serial I/O (UART) mode
BRGi count
source
Receive enable bit
Stop bit
RxDi
Start bit
D1
D0
Sampled “L”
D7
Received data taken in
Transfer clock
Receive
complete flag
At falling edge of start bit, transfer clock
is generated and reception started.
UARTi receive register
UARTi receive buffer register
RTSi
UARTi receive interrupt
request bit
The above timing diagram applies when the
following conditions are satisfied:
● Parity disabled
● 1 stop bit
● RTS function selected
Cleared to “0” when interrupt request is accepted
or cleared by software.
Fig. 11.4.12 Example of receive timing when
transfer data length = 8 bits (when parity disabled,
____
selecting 1 stop bit, selecting RTS function)
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SERIAL I/O
11.4 Clock asynchronous serial I/O (UART) mode
11.4.7 Processing on detecting error
In the UART mode, 3 types of errors can be detected. Each error can be detected when the data in the
UARTi receive register is transferred to the UARTi receive buffer register, and the corresponding error flag
is set to “1.” When any error occurs, the error sum flag is set to “1.” Accordingly, presence of errors can
be judged by using the error sum flag.
Table 11.4.6 lists conditions for setting each error flag to “1” and method for clearing it to “0.”
Table 11.4.6 Conditions set to “1” and method cleared to “0” for each error flag
Conditions for being set to “1”
Error flag
Method for being cleared to “0”
Overrun error flag
When the next data is prepared in the •Clear the serial I/O mode select bits to
UARTi receive register with the receive “000 2.”
complete flag = “1” (i.e., data is present •Clear the receive enable bit to “0.”
in the UARTi receive buffer register). In
other words, when the next data is
prepared before the contents of the UARTi
receive buffer register are read out. (Note)
[UARTi receive interrupt request bit is not
changed.]
Framing error flag
Parity error flag
Error sum flag
When the number of detected stop bits •Clear the serial I/O mode select bits to
does not match the set number of stop “000 2.”
bits.
•Clear the receive enable bit to “0.”
[UARTi receive interrupt request bit is set •Read out the low-order byte of the UARTi
to “1.”]
receive buffer register.
When the sum of “1”s in the parity bit •Clear the serial I/O mode select bits to
and character bits does not match the “000 2.”
set number of “1”s.
•Clear the receive enable bit to “0.”
[UARTi receive interrupt request bit is set •Read out the low-order byte of the UARTi
to “1.”]
receive buffer register.
When 1 or more errors listed above occur. •Clear the all error flags, which are overrun,
framing and parity error flags.
Note: The next data is written into the UARTi receive buffer register.
When an error occurs during reception, initialize the error flag and the UARTi receive buffer register, and
then perform reception again. When it is necessary to perform retransmission owing to an error which occurs
in the receiver side during transmission, set the UARTi transmit buffer register again, and then restarts
transmission.
The method of initializing the UARTi receive buffer register and that of setting the UARTi transmit buffer
register again are described below.
(1) Method of initializing UARTi receive buffer register
➀ Clear the receive enable bit to “0” (reception disabled).
➁ Set the receive enable bit to “1” again (reception enabled).
(2) Method of setting UARTi transmit buffer register again
➀ Clear the serial I/O mode select bits to “000 2” (serial I/O invalid).
➁ Set the serial I/O mode select bits again.
➂ Set the transmit enable bit to “1” (transmission enabled), and set the transmit data to the UARTi
transmit buffer register.
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11.4 Clock asynchronous serial I/O (UART) mode
11.4.8 Sleep mode
This mode is used to transfer data between the specified microcomputers, which are connected by using
UARTi. The sleep mode is selected by setting the sleep select bit (bit 7 at addresses 3016, 3816) to “1” when
receiving.
In the sleep mode, receive operation is performed when the MSB (D 8 when the transfer data is 9 bits
length, D7 when it is 8 bits length, D6 when it is 7 bits length) of the receive data is “1.” Receive operation
is not performed when the MSB is “0.” (The UARTi receive register’s contents are not transferred to the
UARTi receive buffer register. Additionally, the receive complete flag and error flags do not change and
a UARTi receive interrupt request does not occur.)
The following shows an usage example of the sleep mode when the transfer data is 8 bits length.
➀ Set the same transfer data format for the master and slave microcomputers. Select the sleep mode for
the slave microcomputers.
➁ Transmit data, which has “1” in bit 7 and the address of the slave microcomputer to be communicated
in bits 0 to 6, from the master microcomputer to all slave microcomputers.
➂ All slave microcomputers receive data of step ➁. (At this time, a UARTi receive interrupt request occurs.)
➃ For all slave microcomputers, check in the interrupt routine whether bits 0 to 6 in the receive data match
their own addresses.
➄ For the slave microcomputer of which address matches bits 0 to 6 in the receive data, terminate the
sleep mode. (Do not terminate the sleep mode for the other slave microcomputers.)
By performing steps ➁ to ➄, “ the microcomputer which performs transfer” is specified.
➅ Transmit data, which has “0” in bit 7, from the master microcomputer. (Only the microcomputer specified
in steps ➁ to ➄ can receive this data. The other microcomputers do not receive this data.)
➆ By repeating step ➅, transfer can be performed between two specific microcomputers continuously.
When communicating with another microcomputer, perform steps ➁ to ➄ in order to specify the new
slave microcomputer.
Master
Slave A
Slave B
Data is transferred between the master
microcomputer and one specific slave microcomputer
selected from multiple slave microcomputers.
Slave C
Slave D
Fig. 11.4.13 Sleep mode
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11.4 Clock asynchronous serial I/O (UART) mode
MEMORANDUM
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CHAPTER 12
A-D CONVERTER
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
12.9
Overview
Block description
A-D conversion method
Absolute accuracy and differential
non-linearity error
One-shot mode
Repeat mode
Single sweep mode
Repeat sweep mode
Precautions for A-D converter
A-D CONVERTER
12.1 Overview
12.1 Overview
Table 12.1.1 lists the performance specifications of the A-D converter.
Table 12.1.1 Performance specifications of A-D converter
Item
Performance specifications
A-D conversion method
Successive approximation conversion method
Resolution
8 bits
Absolute accuracy
±3 LSB
Analog input pin
8 pins (AN 0 to AN 7) (Note)
Conversion rate per analog input pin
57 φ AD✽ cycles
φ AD✽: A-D converter’s operation clock
The A-D converter has the 4 operation modes listed below.
•One-shot mode
This mode is used to perform the operation once for a voltage input from one selected analog input pin.
•Repeat mode
This mode is used to perform the operation repeatedly for a voltage input from one selected analog input
pin.
•Single sweep mode
This mode is used to perform the operation for voltages input from multiple selected analog input pins, one
at a time.
•Repeat sweep mode
This mode is used to perform the operation repeatedly for voltages input from multiple selected analog
input pins.
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A-D CONVERTER
12.2 Block description
12.2 Block description
Figure 12.2.1 shows the block diagram of the A-D converter. Registers relevant to the A-D converter are
described below.
AD
f2
VREF
AVSS
1/2
1/2
Vref
Resistor
ladder network
Successive
approximation
register
A-D sweep pin select register
A-D control register
A-D register 0
A-D register 1
A-D register 2
A-D register 3
Decoder
A-D register 4
A-D register 5
A-D register 6
A-D register 7
Data bus (even)
Comparator
AN0
AN1
AN2
AN3
VIN
AN4
AN5
AN6
AN7/ADTRG
Selector
Fig. 12.2.1 Block diagram of A-D converter
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A-D CONVERTER
12.2 Block description
12.2.1 A-D control register
Figure 12.2.2 shows the structure of the A-D control register. The A-D operation mode select bit selects
the operation mode of the A-D converter. The other bits are described below.
b7
b6
b5
b4
b3
b2
b1
b0
A-D control register (Address 1E16)
Bit
0
Analog input select bits
(Valid in one-shot and repeat
modes) (Note 1)
1
2
3
Functions
Bit name
A-D operation mode select bits
0 0 0 : AN0 selected
0 0 1 : AN1 selected
0 1 0 : AN2 selected
0 1 1 : AN3 selected
1 0 0 : AN4 selected
1 0 1 : AN5 selected
1 1 0 : AN6 selected
1 1 1 : AN7 selected (Note 2)
b4 b3
0 0 : One-shot mode
0 1 : Repeat mode
1 0 : Single sweep mode
1 1 : Repeat sweep mode
4
At reset
RW
Undefined
RW
Undefined
RW
Undefined
RW
0
RW
0
RW
b2 b1 b0
5
Trigger select bit
0 : Internal trigger
1 : External trigger
0
RW
6
A-D conversion start bit
0 : Stop A-D conversion
1 : Start A-D conversion
0
RW
7
A-D conversion frequency
( AD) select bit
0 : f2 divided by 4
1 : f2 divided by 2
0
RW
Notes 1: These bits are ignored in the single sweep and repeat sweep mode. (They may be
either “0” or “1.”)
2: When an external trigger is selected, the AN7 pin cannot be used as an analog input
pin.
3: Writing to each bit (except bit 6) of the A-D control register must be performed while
the A-D converter halts.
Fig. 12.2.2 Structure of A-D control register
(1) Analog input select bits (bits 2 to 0)
These bits are used to select an analog input pin in the one-shot mode and repeat mode. Pins which
are not selected as analog input pins function as programmable I/O ports.
These bits must be set again when the user switches the A-D operation mode to the one-shot mode
or repeat mode after A-D conversion is performed in the single sweep mode or repeat sweep mode.
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A-D CONVERTER
12.2 Block description
(2) Trigger select bit (bit 5)
This bit is used to select the source of trigger occurrence. (Refer to section “(3) A-D conversion
start bit.”)
(3) A-D conversion start bit (bit 6)
● When internal trigger is selected
Setting this bit to “1” generates a trigger, causing the A-D converter to start operating. Clearing
this bit to “0” causes the A-D converter to stop operating.
In the one-shot mode or single sweep mode, this bit is cleared to “0” after the operation is
completed. In the repeat mode or repeat sweep mode, the A-D converter continues operating until
this bit is cleared to “0” by software.
● When external
trigger is selected
______
When the ADTRG pin level goes from “H” to “L” with this bit = “1,” a trigger occurs, causing the
A-D converter to start operating. The A-D converter stops when this bit is cleared to “0.”
In the one-shot mode or single sweep mode, this bit remains set to “1” even after the operation
is completed. In the repeat mode or repeat sweep mode, the A-D converter continues operating
until this bit is cleared to “0” by software.
(4) A-D conversion frequency (φ AD) select bit (bit 7)
As listed in Table 12.2.1, the conversion time of the A-D converter varies depending on the operating
clock ( φ AD) selected by this bit.
Since the A-D converter’s comparator consists of capacity coupling amplifiers, keep that φ AD ≥ 250
kHz during A-D conversion.
Table 12.2.1 Conversion time per one analog input pin (unit: µ s)
0
A-D conversion frequency (φ AD) select bit
f2/4
φ AD
f 2/2
f(X IN) = 8 MHz
57.0
28.5
f(X IN) = 16 MHz
28.5
18.24
14.25
9.12
Conversion time
f(X IN) = 25 MHz
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A-D CONVERTER
12.2 Block description
12.2.2 A-D sweep pin select register
Figure 12.2.3 shows the structure of the A-D sweep pin select register.
b7
b6
b5
b4
b3
b2
b1
b0
A-D sweep pin select register (Address 1F16)
Bit
0
A-D sweep pin select bits
(Valid in single sweep and repeat
sweep mode ) (Note 1)
1
7 to 2
Functions
Bit name
Nothing is assigned.
b1 b0
0 0 : AN0, AN1 (2 pins)
0 1 : AN0 to AN3 (4 pins)
1 0 : AN0 to AN5 (6 pins)
1 1 : AN0 to AN7 (8 pins) (Note 2)
At reset
RW
1
RW
1
RW
Undefined
–
Notes 1: These bits are invalid in the one-shot and repeat modes. (They may be either “0” or
“1.”)
2: When selecting an external trigger, the AN7 pin cannot be used as an analog input pin.
3: Writing to each bit of the A-D sweep pin select register must be performed while the
A-D converter halts.
Fig. 12.2.3 Structure of A-D control register 1
(1) A-D sweep pin select bits (bits 1 and 0)
These bits are used to select analog input pins in the single sweep mode or repeat sweep mode.
In the single sweep mode and repeat sweep mode, pins which are not selected as analog input pins
function as programmable I/O ports.
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A-D CONVERTER
12.2 Block description
12.2.3 A-D register i (i = 0 to 7)
Figure 12.2.4 shows the structure of the A-D register i. When the A-D conversion is completed, the
conversion result (contents of the successive approximation register) is stored into this register. Each AD register i corresponds to an analog input pin (AN i).
b7
b6
b5
b4
b3
b2
b1
A-D register 0 (Addresses 2016)
A-D register 1 (Addresses 2216)
A-D register 2 (Addresses 2416)
A-D register 3 (Addresses 2616)
A-D register 4 (Addresses 2816)
A-D register 5 (Addresses 2A16)
A-D register 6 (Addresses 2C16)
A-D register 7 (Addresses 2E16)
b0
Bit
Functions
7 to 0 Reads an A-D conversion result.
At reset
RW
Undefined
RO
Fig. 12.2.4 Structure of A-D register i
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A-D CONVERTER
12.2 Block description
12.2.4 A-D conversion interrupt control register
Figure 12.2.5 shows the structure of the A-D conversion interrupt control register. For details about interrupts,
refer to “CHAPTER 7. INTERRUPTS.”
b7
b6
b5
b4
b3
b2
b1
b0
A-D conversion interrupt control register (Address 7016)
Bit
Bit name
0
Interrupt priority level select bits
1
2
3
Interrupt request bit
7 to 4
Nothing is assigned.
Functions
At reset
RW
0 0 0 : Level 0 (Interrupt disabled)
0 0 1 : Level 1
Low level
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
High level
0
RW
0
RW
0
RW
0 : No interrupt requested
1 : Interrupt requested
0
RW
Undefined
–
b2 b1 b0
Fig. 12.2.5 Structure of A-D conversion interrupt control register
(1) Interrupt priority level select bits (bits 2 to 0)
These bits select an A-D conversion interrupt’s priority level. When using A-D conversion interrupts,
select one of the priority levels (1 to 7). When an A-D conversion interrupt request occurs, its priority
level is compared with the processor interrupt priority level (IPL). The requested interrupt is enabled
only when its priority level is higher than the IPL. (However, this applies when the interrupt disable
flag (I) = “0.”)
To disable A-D conversion interrupts, set these bits to “000 2” (level 0).
(2) Interrupt request bit (bit 3)
This bit is set to “1” when an A-D conversion interrupt request occurs. This bit is automatically
cleared to “0” when the A-D conversion interrupt request is accepted. This bit can be set to “1” or
cleared to “0” by software.
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A-D CONVERTER
12.2 Block description
12.2.5 Port P7 direction register
Input pins of the A-D converter are multiplexed with port P7. When using these pins as A-D converter’s
input pins, set the corresponding bits of the port P7 direction register to “0” to set these port pins for the
input mode. Figure 12.2.6 shows the relationship between the port P7 direction register and A-D converter’s
input pins.
b7
b6
b5
b4
b3
b2
b1
b0
Port P7 direction register (Address 1116)
Bit
Corresponding pin
0
AN0 pin
1
AN1 pin
Functions
0 : Input mode
1 : Output mode
When using these pins as A-D
converter’s input pins, set the
corresponding bits to “0.”
At reset
RW
0
RW
0
RW
0
RW
0
RW
2
AN2 pin
3
AN3 pin
4
AN4 pin
0
RW
5
AN5 pin
0
RW
6
AN6 pin
0
RW
7
AN7/ADTRG pin
0
RW
Fig. 12.2.6 Relationship between port P7 direction register and A-D converter’s input pins
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A-D CONVERTER
12.3 A-D conversion method
12.3 A-D conversion method
The A-D converter compares the comparison voltage (Vref), which is internally generated according to the
contents of the successive approximation register, with the analog input voltage (VIN), which is input from
the analog input pin (ANi). By reflecting the comparison result on the successive approximation register, VIN
is converted into a digital value. When a trigger is generated, the A-D converter performs the following
processing:
➀
Determining bit 7 of the successive approximation register
The A-D converter compares Vref with VIN. At this time, the contents of the successive approximation
register is “10000000 2” (initial value).
Bit 7 of the successive approximation register changes according to the comparison result as follows:
When V ref < V IN, bit 7 = “1”
When V ref > V IN, bit 7 = “0”
➁
Determining bit 6 of the successive approximation register
After setting bit 6 of the successive approximation register to “1,” the A-D converter compares Vref
with V IN. Bit 6 changes according to the comparison result as follows:
When V ref < V IN, bit 6 = “1”
When V ref > V IN, bit 6 = “0”
➂
Determining bits 5 to 0 of the successive approximation register
Operations in ➁ are performed for bits 5 to 0.
When bit 0 is determined, the contents (conversion result) of the successive approximation register
is transferred to the A-D register i.
The comparison voltage (V ref) is generated according to the latest contents of the successive approximation
register. Table 12.3.1 lists the relationship between the successive approximation register’s contents and
Vref. Table 12.3.2 lists changes of the successive approximation register and V ref during the A-D conversion.
Figure 12.3.1 shows the ideal A-D conversion characteristics.
Table 12.3.1 Relationship between successive approximation register’s contents and Vref
Successive approximation register’s contents: n
V ref (V)
0
0
VREF✽
1 to 255
256
VREF✽: Reference voltage
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✕ (n – 0.5)
A-D CONVERTER
12.3 A-D conversion method
Table 12.3.2 Change in successive approximation register and V ref during A-D conversion
Successive approximation register
b7
Change of Vref
b0
A-D converter halt
1 0 0 0 0 0 0 0
VREF [V]
2
1st comparison
1 0 0 0 0 0 0 0
VREF – VREF [V]
512
2
2nd comparison
n7 1 0 0 0 0 0 0
VREF ± VREF – VREF [V]
4
2
512
1st comparison result
3rd comparison
n7 n6 1 0 0 0 0 0
n 7 n6 n5 n 4 n 3 n2 n1 1
Conversion complete
n 7 n6 n 5 n 4 n 3 n2 n 1 n0
4
•n6=1
•n6=0
VREF
8
VREF
– 8
+
:
:
:
:
8th comparison
•n7=0
+ VREF
4
VREF
–
VREF ± VREF ± VREF – VREF [V]
8
512
4
2
2nd comparison result
:
:
•n7=1
VREF ± VREF ± VREF ± ...... ± VREF – VREF [V]
4
8
256
512
2
A-D conversion result
ldeal A-D conversion characteristics
FF16
FE16
FD16
0316
0216
0116
0016
0
VREF
✕1
256
VREF
✕2
256
VREF
✕3
256
VREF
✕253
256
VREF
256 ✕0.5
VREF
✕254
256
VREF
✕255
256
VREF
Analog input voltage
Fig. 12.3.1 Ideal A-D conversion characteristics
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A-D CONVERTER
12.4 Absolute accuracy and differential non-linearity error
12.4 Absolute accuracy and differential non-linearity error
The A-D converter’s accuracy is described below. Refer to section “Appendix 12.3 A-D converter standard
characteristics,” also.
12.4.1 Absolute accuracy
The absolute accuracy is the difference expressed in the LSB between the actual A-D conversion result
and the output code of an A-D converter with ideal characteristics. The analog input voltage when measuring
the accuracy is assumed to be the mid point of the input voltage width that outputs the same output code
from an A-D converter with ideal characteristics. For example, when VREF = 5.12 V, 1 LSB width is 20 mV,
and 0 mV, 20 mV, 40 mV, 60 mV, 80 mV, ... are selected as the analog input voltages.
The absolute accuracy = ±3 LSB indicates that when the analog input voltage is 100 mV, the output code
expected from an ideal A-D conversion characteristics is “00516,” however the actual A-D conversion result
is between “002 16” to “00816.”
The absolute accuracy includes the zero error and the full-scale error.
The absolute accuracy is degraded when V REF is lowered. Any of the output codes for analog input voltages
from V REF to AV CC is “FF 16.”
Output code
(A-D conversion result)
0B16
0A16
0916
+3 LSB
0816
Ideal A-D conversion
characteristics
0716
0616
0516
0416
0316
0216
–3 LSB
0116
0016
0
20
40
60
80
100
120
140
Analog input voltage (mV)
Fig. 12.4.1 Absolute accuracy of A-D converter
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160
180
200
220
A-D CONVERTER
12.4 Absolute accuracy and differential non-linearity error
12.4.2 Differential non-linearity error
The differential non-linearity error indicates the difference between the 1 LSB step width (the ideal analog
input voltage width while the same output code is expected to output) of an A-D converter with ideal
characteristics and the actual measured step width (the actual analog input voltage width while the same
output code is output). For example, when VREF = 5.12 V, the 1 LSB width of an A-D converter with ideal
characteristics is 20 mV, however when the differential non-linearity error is ±1 LSB, the actual measured
1 LSB width is 0 to 40 mV.
Output code
(A-D conversion result)
0916
1 LSB width with ideal
A-D conversion characteristics
0816
0716
0616
0516
0416
0316
0216
0116
Differential non-linearity error
0016
0
20
40
60
80
100
120
140
160
180
Analog input voltage (mV)
Fig. 12.4.2 Differential non-linearity error
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A-D CONVERTER
12.5 One-shot mode
12.5 One-shot mode
In the one-shot mode, the operation for the input voltage from the one selected analog input pin is performed
once, and the A-D conversion interrupt request occurs when the operation is completed.
12.5.1 Settings for one-shot mode
Figure 12.5.1 shows an initial setting example for registers relevant to the one-shot mode.
When using an interrupt, it is necessary to set the relevant registers to enable the interrupt. Refer to
“CHAPTER 7. INTERRUPTS” for more descriptions.
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A-D CONVERTER
12.5 One-shot mode
●A-D control register
b7
b0
0
0 0
A-D control register (address 1E16)
Analog input select bits
b2 b1 b0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 : AN0 selected
1 : AN1 selected
0 : AN2 selected
1 : AN3 selected
0 : AN4 selected
1 : AN5 selected
0 : AN6 selected
1 : AN7 selected
One-shot mode
Trigger select bit
0 : Internal trigger
1 : External trigger
A-D conversion start bit
0: Stop A-D conversion
A-D conversion frequency (
select bit
0 : f2 divided by 4
1 : f2 divided by 2
AD)
●Interrupt priority level
b7
b0
A-D conversion interrupt control register (address 7016)
Interrupt priority level select bits
Set to a level between 1 to 7 when using this interrupt.
Set to a level 0 when disabling this interrupt.
●Port P7 direction register
b7
b0
Port P7 direction register (address 1116)
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
●Set A-D conversion start bit to “1”
b7
b0
A-D control register (address 1E16)
1
Set the bits corresponding
to analog input pins to “0.”
Set bit 7 to “0” when
selecting external trigger.
A-D conversion start bit
When external trigger is selected
When internal trigger is selected
Input falling edge to
ADTRG pin
Note : Writing to each bit (except bit 6) of the A-D control register must be performed
while the A-D converter halts (before a trigger occurs).
Trigger occur
Operation start
Fig. 12.5.1 Initial setting example for registers relevant to one-shot mode
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A-D CONVERTER
12.5 One-shot mode
12.5.2 One-shot mode operation description
(1) When an internal trigger is selected
➀ The A-D converter starts operation when the A-D conversion start bit is set to “1.”
➁ The A-D conversion is completed after 57 cycles of φ AD. Then, the contents of the successive
approximation register (conversion result) are transferred to the A-D register i.
➂ At the same time as step ➁, the A-D conversion interrupt request bit is set to “1.”
➃ The A-D conversion start bit is cleared to “0” and the A-D converter stops operation.
(2) When an external trigger is selected
_____
➀ The A-D converter starts operation when the input level to the ADTRG pin changes from “H” to “L”
while the A-D conversion start bit is “1.”
➁ The A-D conversion is completed after 57 cycles of φ AD. Then, the contents of the successive
approximation register (conversion result) are transferred to the A-D register i.
➂ At the same time as step ➁, the A-D conversion interrupt request bit is set to “1.”
➃ The A-D conversion stops.
The A-D conversion start bit remains set to “1” after the operation is completed. Accordingly,
the
_____
operation of the A-D converter can be performed again from step ➀ when the level of the ADTRG pin
changes from “H” to “L.”
_____
When the level of the ADTRG pin changes from “H” to “L” during operation, the operation at that point
is cancelled and is restarted from step ➀.
Figure 12.5.2 shows the conversion operation in the one-shot mode.
Trigger occur
Conversion result
Convert input voltage from
ANi pin
A-D register i
A-D conversion interrupt request occurs.
A-D converter halt
Fig. 12.5.2 Conversion operation in one-shot mode
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A-D CONVERTER
12.6 Repeat mode
12.6 Repeat mode
In the repeat mode, the operation for the input voltage from the one selected analog input pin is performed
repeatedly.
In this mode, no A-D conversion interrupt request occurs. Additionally, the A-D conversion start bit (bit 6 at
address 1E 16) remains set to “1” until it is cleared to “0” by software, and the operation is performed
repeatedly while the A-D conversion start bit is “1.”
12.6.1 Settings for repeat mode
Figure 12.6.1 shows an initial setting example for registers relevant to the repeat mode.
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A-D CONVERTER
12.6 Repeat mode
●A-D control register
b7
b0
0
0 1
A-D control register (address 1E16)
Analog input select bits
b2 b1 b0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 : AN0 selected
1 : AN1 selected
0 : AN2 selected
1 : AN3 selected
0 : AN4 selected
1 : AN5 selected
0 : AN6 selected
1 : AN7 selected
Repeat mode
Trigger select bit
0 : Internal trigger
1 : External triggeer
A-D conversion start bit
0: Stop A-D conversion
A-D conversion frequency (
select bit
0 : f2 divided by 4
1 : f2 divided by 2
AD)
●Port P7 direction register
b7
b0
Port P7 direction register (address 1116)
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Set the bits corresponding
to analog input pins to “0.”
Set bit 7 to “0” when
selecting external trigger.
●Set A-D conversion start bit to “1”
b7
b0
1
A-D control register (address 1E16)
A-D conversion start bit
When external trigger is selected
When internal trigger is
selected
Input falling edge to
ADTRG pin
Trigger occur
Operation start
Note : Writing to each bit (except bit 6) of the A-D control register must be performed while the A-D
converter halts (before a trigger occurs).
Fig. 12.6.1 Initial setting example for registers relevant to repeat mode
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A-D CONVERTER
12.6 Repeat mode
12.6.2 Repeat mode operation description
(1) When an internal trigger is selected
➀ The A-D converter starts operation when the A-D conversion start bit is set to “1.”
➁ The first A-D conversion is completed after 57 cycles of φAD. Then, the contents of the successive
approximation register (conversion result) are transferred to the A-D register i.
➂ The A-D converter repeats operation until the A-D conversion start bit is cleared to “0” by software.
The conversion result is transferred to the A-D register i each time the conversion is completed.
(2) When an external trigger is selected
____
➀ The A-D converter starts operation when the input level to the ADTRG pin changes from “H” to “L”
while the A-D conversion start bit is “1.”
➁ The first A-D conversion is completed after 57 cycles of φAD. Then, the contents of the successive
approximation register (conversion result) are transferred to the A-D register i.
➂ The A-D converter repeats operation until the A-D conversion start bit is cleared to “0” by software.
The conversion result is transferred to the A-D register i each time the conversion is completed.
_____
When the level of the ADTRG pin changes from “H” to “L” during operation, the operation at that point
is cancelled and is restarted from step ➀.
Figure 12.6.2 shows the conversion operation in the repeat mode.
Trigger occur
Conversion result
Convert input voltage from
ANi pin
A-D register i
Fig. 12.6.2 Conversion operation in repeat mode
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A-D CONVERTER
12.7 Single sweep mode
12.7 Single sweep mode
In the single sweep mode, the operation for the input voltage from multiple selected analog input pins is
performed, one at a time. The A-D converter is operated in ascending sequence from the AN0 pin. The
A-D conversion interrupt request occurs when the operation for all selected input pins are completed.
12.7.1 Settings for single sweep mode
Figure 12.7.1 shows an initial setting example for registers relevant to the single sweep mode.
When using an interrupt, it is necessary to set the relevant registers to enable the interrupt. Refer to
“CHAPTER 7. INTERRUPTS” for more information.
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A-D CONVERTER
12.7 Single sweep mode
●A-D control register and A-D sweep pin select register
b7
b0
0
b7
b0
1 0 ✕ ✕ ✕ A-D control register (address 1E16)
A-D sweep pin select register (address 1F16)
A-D sweep pin select bits
Single sweep mode
b1 b0
0
0
1
1
Trigger select bit
0 : Internal trigger
1 : External trigger
0 : AN0, AN1 (2 pins)
1 : AN0–AN3 (4 pins)
0 : AN0–AN5 (6 pins)
1 : AN0–AN7 (8 pins)
A-D conversion start bit
0: Stop A-D conversion
A-D conversion frequency (
select bit
0 : f2 divided by 4
1 : f2 divided by 2
AD)
✕ : “0” or “1”
●Interrupt priority level
b7
b0
A-D conversion interrupt control register (address 7016)
Interrupt priority level select bits
Set to a level between 1 to 7 when using this interrupt.
Set to a level 0 when disabling this interrupt.
●Port P7 direction register
b7
b0
Port P7 direction register (address 1116)
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Set the bits corresponding
to analog input pins to “0.”
Set bit 7 to “0” when
selecting external trigger.
●Set A-D conversion start bit to “1”
b7
b0
A-D control register (address 1E16)
1
A-D conversion start bit
When external trigger is selected
When internal trigger is
selected
Input falling edge to
ADTRG pin
Trigger occur
Operation start
Note : Writing to each bit (except bit 6) of the A-D control register and each bit of the A-D sweep pin
select register must be performed while the A-D converter halts (before a trigger occurs).
Fig. 12.7.1 Initial setting example for registers relevant to single sweep mode
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A-D CONVERTER
12.7 Single sweep mode
12.7.2 Single sweep mode operation description
(1) When an internal trigger is selected
➀ The operation for the input voltage from the AN0 pin starts when the A-D conversion start bit is
set to “1.”
➁ The A-D conversion of the input voltage from the AN0 pin is completed after 57 cycles of φAD. Then,
the contents of the successive approximation register (conversion result) are transferred to the
A-D register 0.
➂ For all of the selected analog input pins, the A-D conversion is performed.
The conversion result is transferred to the A-D register i each time each pin is converted.
➃ When step ➂ is completed, the A-D conversion interrupt request bit is set to “1.”
➄ The A-D conversion start bit is cleared to “0” and the A-D converter stops operation.
(2) When an external trigger is selected
➀ The_____
A-D converter starts operation for the input voltage from the AN 0 pin when the input level to
the ADTRG pin changes from “H” to “L” while the A-D conversion start bit is “1.”
➁ The A-D conversion of the input voltage from the AN0 pin is completed after 57 cycles of φAD. Then,
the contents of the successive approximation register (conversion result) are transferred to the
A-D register 0.
➂ For all of the selected analog input pins, the A-D conversion is performed.
The conversion result is transferred to the A-D register i each time each pin is converted.
➃ When step ➂ is completed, the A-D conversion interrupt request bit is set to “1.”
➄ The A-D conversion stops.
The A-D conversion start bit remains set to “1” after the operation is completed. Accordingly,
the
_____
operation of the A-D converter can be performed again from step ➀ when the level of the ADTRG pin
changes from “H” to “L.”
_____
When the level of the ADTRG pin changes from “H” to “L” during operation, the operation at that point
is cancelled and is restarted from step ➀.
Figure 12.7.2 shows the conversion operation in the single sweep mode.
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A-D CONVERTER
12.7 Single sweep mode
Trigger occur
Convert input voltage from Conversion result
AN0 pin
A-D register 0
Convert input voltage from Conversion result
AN1 pin
A-D register 1
Convert input voltage from Conversion result
ANi pin
A-D register i
A-D conver ter interrupt
request occur
A-D converter halt
Fig. 12.7.2 Conversion operation in single sweep mode
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A-D CONVERTER
12.8 Repeat sweep mode
12.8 Repeat sweep mode
In the repeat sweep mode, the operation for the input voltages from the multiple selected analog input pins
is performed repeatedly. The A-D converter is operated in ascending sequence from the AN 0 pin.
In this mode, no A-D conversion interrupt request occurs. Additionally, the A-D conversion start bit (bit 6 at
address 1E 16 ) remains set to “1” until it is cleared to “0” by software, and the operation is performed
repeatedly while the A-D conversion start bit is “1.”
12.8.1 Settings for repeat sweep mode
Figure 12.8.1 shows an initial setting example for registers relevant to the repeat sweep mode.
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A-D CONVERTER
12.8 Repeat sweep mode
●A-D control register and A-D sweep pin select register
b7
b0
0
b7
b0
1 1 ✕ ✕ ✕ A-D control register (address 1E16)
A-D sweep pin select register (address 1F16)
Repeat sweep mode
A-D sweep pin select bits
Trigger select bit
0 : Internal trigger
1 : External trigger
0
0
1
1
b1 b0
0 : AN0, AN1 (2 pins)
1 : AN0–AN3 (4 pins)
0 : AN0–AN5 (6 pins)
1 : AN0–AN7 (8 pins)
A-D conversion start bit
0: Stop A-D conversion
A-D conversion frequency (
select bit
0 : f2 divided by 4
1 : f2 divided by 2
AD)
✕ : “0” or “1”
●Port P7 direction register
b7
b0
Port P7 direction register (address 1116)
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Set the bits corresponding
to analog input pins to “0.”
Set bit 7 to “0” when
selecting external trigger.
●Set A-D conversion start bit to “1”
b7
b0
1
A-D control register (address 1E16)
A-D conversion start bit
When external trigger is selected
When internal trigger
is selected
Input falling edge to
ADTRG pin
Trigger occur
Operation start
Note : Writing to each bit (except bit 6) of the A-D control register and each bit of the A-D sweep
pin select register must be performed while the A-D converter halts (before a trigger
occurs).
Fig. 12.8.1 Initial setting example for registers relevant to repeat sweep mode
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A-D CONVERTER
12.8 Repeat sweep mode
12.8.2 Repeat sweep mode operation description
(1) When an internal trigger is selected
➀ The operation for the input voltage from the AN0 pin starts when the A-D conversion start bit is
set to “1.”
➁ The A-D conversion of the input voltage from the AN0 pin is completed after 57 cycles of φAD. Then,
the contents of the successive approximation register (conversion result) are transferred to the
A-D register 0.
➂ For all of the selected analog input pins, the A-D conversion is performed.
The conversion result is transferred to the A-D register i each time each pin is converted.
➃ For all of the selected analog input pins, the A-D conversion is performed again.
➄ The operation is performed repeatedly until the A-D conversion start bit is cleared to “0” by
software.
(2) When an external trigger is selected
➀ The______
A-D converter starts operation for the input voltage from the AN 0 pin when the input level to
the ADTRG pin changes from “H” to “L” while the A-D conversion start bit is “1.”
➁ The A-D conversion of the input voltage from the AN0 pin is completed after 57 cycles of φAD. Then,
the contents of the successive approximation register (conversion result) are transferred to the
A-D register 0.
➂ For all of the selected analog input pins, the A-D conversion is performed.
The conversion result is transferred to the A-D register i each time each pin is converted.
➃ For all of the selected analog input pins, the A-D conversion is performed again.
➄ The operation is performed repeatedly until the A-D conversion start bit is cleared to “0” by
software.
______
When the level of the ADTRG pin changes from “H” to “L” during operation, the operation at that point
is cancelled and is restarted from step ➀.
Figure 12.8.2 shows the conversion operation in the repeat sweep mode.
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A-D CONVERTER
12.8 Repeat sweep mode
Trigger occur
Conversion result
Convert input voltage from AN0 pin
Convert input voltage from AN1 pin
Convert input voltage from ANi pin
Conversion result
Conversion result
A-D register 0
A-D register 1
A-D register i
Fig. 12.8.2 Conversion operation in repeat sweep mode
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A-D CONVERTER
12.9 Precautions for A-D converter
12.9 Precautions for A-D converter
1. Writing to the following must be performed before a trigger occurs (while the A-D converter halts).
•Each bit (except bit 6) of the A-D control register
•Each bit of the A-D sweep pin select register
_____
2. When an external trigger is selected, the AN7/ADTRG pin is disconnected from the comparator. Therefore,
this pin cannot be used as an analog input pin.
When the AN 7 pin is selected as an analog input pin while an external trigger is selected, the A-D
converter operates, however, an undefined value is stored into the A-D register 7.
3. Refer to “Appendix. 8 Countermeasure against noise” when using the A-D converter.
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CHAPTER 13
DMA
CONTROLLER
13.1 Overview
13.2 Block description
[Precautions for DMAC]
13.3 Control
13.4 Operation
[Precautions for 2-bus cycle
transfer]
[Precautions for 1-bus cycle
transfer]
[Precautions for burst transfer
mode]
[Precautions for cycle-steal transfer
mode]
13.5 Single transfer mode
13.6 Repeat transfer mode
13.7 Array chain transfer mode
[Precautions for array chain transfer
mode]
13.8 Link array chain transfer mode
[Precautions for link array chain
transfer mode]
13.9 DMA transfer time
DMA CONTROLLER
13.1 Overview
13.1 Overview
The DMA controller (hereafter called DMAC) transfers data using the bus and bypassing the CPU. DMAC
of the M37721 provides four independent channels of DMA0–DMA3, which have the same function each.
In this chapter, the source and destination of each DMA transfer are represented as follows.
● Memory
A device which needs its own address to be specified
Examples: Internal RAM and SFRs, external memory, and memory-mapped I/Os
● I/O
A device which does not need its own address to be specified
Example: External I/O devices
13.1.1 Performance overview
Table 13.1.1 lists the performance overview.
Table 13.1.1 DMAC performance overview
Item
Performance specifications
Number of channels 4 channels
Transfer space
16 Mbytes (between arbitrary spaces)
Number of transfer Maximum of 16 Mbytes
bytes
DMA request source Internal 14 sources and External 1 source
Channel priority
Fixed or Rotating
Transfer rate
Maximum of 12.5 Mbytes/sec (at f(XIN) = 25 MHz, 1-bus cycle transfer)
Maximum of 6.25 Mbytes/sec (at f(XIN) = 25 MHz, 2-bus cycle transfer)
Data transfer
method
1-bus cycle or 2-bus cycle transfer
Transfer unit
8 or 16 bits
Address direction of Fixed, Forward, or Backward
transfer
(Directions of source and destination are independently selectable.)
Transfer mode
Burst transfer or Cycle-steal transfer mode
Continuous transfer Single transfer, Repeat transfer, Array chain transfer, or Link array chain transfer
mode
mode
13-2
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DMA CONTROLLER
13.1 Overview
13.1.2 Bus use priority levels
The bus use priority levels are fixed by hardware as follows:
DRAMC > Hold function > DMAC > CPU
(DRAM refresh)
Because DMAC has the third priority, it actually operates as follows:
• When DRAM refresh request or Hold request is generated during DMA transfer
After the transfer of one transfer unit (8-bit or 16-bit data), which is being performed at that time, is
complete, DMAC relinquishes the bus to a DRAM refresh or a Hold function.
When DMAC regains the right to use bus after the DRAM refresh ends or the Hold state is removed,
DMA transfer is restarted at the following address.
• When DMA request is generated during DRAM refresh or in Hold state
DMAC gains the right to use bus after the DRAM refresh ends or the Hold state is removed.
• When DMA request is generated while CPU uses bus
Upon end of the bus cycle, DMAC gains the right to use bus if any DRAM refresh request or Hold
request is not generated at that time.
If a DRAM refresh request or a Hold request is generated when the bus cycle ends, DMAC gains
the right to use bus after the DRAM refresh ends or the Hold state is removed.
For details, refer to section “13.2.1 Bus access control circuit” and bus request sampling signals in
timing diagrams.
13.1.3 Modes
DMAC has the following transfer methods and modes. Because these methods and modes are independent
each other, any combination between them is selectable.
(1) Data transfer method
■ 2-bus cycle transfer
This is a method used to transfer data between memories. A DMA transfer consumes 2 cycles: a
read and a write cycle of data.
For details, refer to section “13.4.1 2-bus cycle transfer.”
■ 1-bus cycle transfer
This is a method used to transfer data between a memory and an I/O. A read and write of data
is carried out at the same time (in 1-bus cycle), so that high-speed transfer can be accomplished.
For details, refer to section “13.4.2 1-bus cycle transfer.”
(2) Transfer unit
■ 8-bit transfer
A minimum unit of DMA transfer is 8 bits; that is, an 8-bit data is transferred for one DMA request
in the cycle-steal transfer mode.
In the burst transfer
mode, if a DRAM refresh request or a Hold request is generated during DMA
___
transfer, or if TC input is driven from “H” to “L” to force DMA transfer into termination, DMAC
relinquishes the bus after completion of 8-bit data transfer which is being performed at that time.
■ 16-bit transfer
A minimum unit of DMA transfer is 16 bits; that is, a 16-bit data is transferred for one DMA request
in the cycle-steal transfer mode.
In the burst transfer
mode, if a DRAM refresh request or a Hold request is generated during DMA
___
transfer, or if TC input is driven from “H” to “L” to force DMA transfer into termination, DMAC
relinquishes the bus after completion of 16-bit data transfer which is being performed at that time.
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DMA CONTROLLER
13.1 Overview
(3) Transfer modes
■ Burst transfer mode
When once a DMA request is accepted in this mode, an entire batch of data is transferred. Neither
is the right to use bus returned to the CPU, nor the DMA request of the channel with
the higher
________
priority is accepted until the transfer is complete. However, if an external source (DMAREQi ) is
selected
as a DMA request source with the level sense selected, DMA transfer is performed when
_________
the
DMAREQi pin’s input level is “L,” and the right to use bus is returned to the CPU when the
_________
DMAREQi pin’s input level is “H.” Even in this case, any DMA request of the other channels is not
accepted until the entire batch of data has been transferred.
For details, refer to section “13.4.3 Burst transfer mode.”
■ Cycle-steal transfer mode
For each DMA request, 1 transfer unit of data is transferred. (Hereafter, transferring 1-transfer-unit
data, which is 8-bit or 16-bit data in the M37721, is called “1-unit transfer.”)
When 1-unit transfer is complete and another DMA request (including that of other channels) is not
generated, the DMAC relinquishes the right to use bus to the CPU.
In the cycle-steal transfer mode, all of the DMA request sources are available.
For details, refer to section “13.4.4 Cycle-steal transfer mode.”
Figure 13.1.1 shows the outline of the DMA transfer modes.
■ Burst transfer mode (Edge sense)
DMAi request is accepted.
Right to use bus
CPU
DMAi
CPU
(Transfer of entire batch of data)
■ Burst transfer mode (External source (DMAREQi), level sense)
DMAREQi input
Right to use bus
CPU
DMAi
CPU
DMAi
■ Cycle-steal transfer mode
DMA0 request is accepted.
DMA0 request is accepted.
DMA1 request is accepted.
Right to use bus
CPU
DMA0
(One transfer unit)
CPU
DMA0 DMA1
(One transfer unit)
Fig. 13.1.1 Outline of DMA transfer modes
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7721 Group User’s Manual
(One transfer unit)
CPU
DMA CONTROLLER
13.1 Overview
(4) Continuous transfer mode
■ Single transfer mode
1 block of data is transferred once.
For details, refer to section “13.5 Single transfer mode.”
■ Repeat transfer mode
1 block of data is transferred repeatedly.
For details, refer to section “13.6 Repeat transfer mode.”
■ Array chain transfer mode
Several blocks of data are transferred.
The transfer parameters (transfer source and destination addresses, the number of transfer bytes)
of each block must be located on the memory in series.
For details, refer to section “13.7 Array chain transfer mode.”
■ Link array chain transfer mode
Several blocks of data are transferred.
Transfer parameters for each block can be located on the memory in separate, in a unit of 1block’s parameters.
For details, refer to section “13.8 Link array chain transfer mode.”
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DMA CONTROLLER
13.2 Block description
13.2 Block description
Figures 13.2.1 and 13.2.2 show the DMAC block diagrams, and relevant registers are described below.
Address bus
Incrementer/Decrementer
Source address register 0 (SAR0)
Destination address register 0 (DAR0)
Source address register 1 (SAR1)
Decrementer
Destination address register 1 (DAR1)
Transfer counter register 0 (TCR0)
Source address register 2 (SAR2)
Transfer counter register 1 (TCR1)
Destination address register 2 (DAR2)
Transfer counter register 2 (TCR2)
Source address register 3 (SAR3)
Transfer counter register 3 (TCR3)
Destination address register 3 (DAR3)
DMA latch high-order
DMA latch low-order
Data bus (Even)
Data bus (Odd)
: Microcomputer’s internal bus
: DMAC’s internal bus
Fig. 13.2.1 DMAC block diagram (1)
DRAMC
Refresh timer
f16
DRAM refresh
request
Hold function
Hold request
HOLD
BUS REQUEST (DRAMC)
BIU
CPU wait
request
BUS REQUEST (Hold)
DMAC
Array state
Enable
Channel 1
Channel 2
Channel 3
Bus access
control circuit
Fig. 13.2.2 DMAC block diagram (2)
13-6
ST0
ST1
BUS REQUEST
(DMAC)
Acknowledge signal
generation
Request
Channel priority
level determination
Request source
selection
Channel 0
DMAREQ0
Software
Timer A0
TImer A1
7721 Group User’s Manual
DMAACK0
DMAACK1
DMAACK2
DMAACK3
DMA CONTROLLER
13.2 Block description
13.2.1 Bus access control circuit
In the M37721, the bus is used by DRAMC, Hold function, DMAC, and CPU.
When each request of DRAM refresh, Hold, and DMA is generated, each of DRAMC, Hold function, and
DMAC issues its bus request to the bus access control circuit in DMAC. (Refer to “Figure 13.2.2.”)
Table 13.2.1 lists the bus request generating sources.
Table 13.2.1 Bus request generating sources
Bus request generating source
Bus request
BUS REQUEST
(DRAMC)
DRAM refresh request
BUS REQUEST
(Hold)
Hold request
(Generated by “L”-level input to the HOLD pin.)
BUS REQUEST
(DMAC)
DMA request
(Generated by a DMA request source.)
(Generated by an underflow of the refresh timer.)
_____
The bus access control circuit relinquishes the right to use bus to the function with the highest priority
among functions, which issue bus requests when the BUS REQUEST signal is sampled. This is the bus
request acceptance. If any bus request is not generated at bus request sampling, the CPU gains the right
to use bus.
The bus use priority levels are fixed by hardware, and the bus status is reported by status signal outputs
ST0 and ST1. Table 13.2.2 lists the relationship between the bus use priority level, bus status, and status
signals.
Table 13.2.2 Relationship between bus use priority level, bus status, and status signals
Bus status
Bus use
priority level
1 (Highest)
DRAM refresh
2
Hold
DMAC
3
4 (Lowest)
CPU (Including the term while the CPU does not use the bus; for
example, the term when the CPU is calculating and does not use
the bus)
7721 Group User’s Manual
Status signals
ST1
0
ST0
0
0
1
1
1
0
1
13-7
DMA CONTROLLER
13.2 Block description
The BUS REQUEST signal is sampled at a break in bus use. Table 13.2.3 and Figure 13.2.3 shows the
timings of bus request sampling. Also, bus request sampling signals are shown in them.
Table 13.2.3 Bus request sampling timing
Bus user
DRAM refresh
Bus request sampling timing
After completion of a DRAM refresh cycle
Hold
Every 1 cycle of φ
DMAC
All except the following
S/R
(Note 1) At the end of each block
After completion of 1-unit transfer
After 1-unit transfer and terminate-processing (3 cycles
of φ ) etc. are performed sequentially
Array/
All except the following
Link
At the end of each block
(Note 1) (except the last block)
After completion of 1-unit transfer
■ During transfer in burst transfer mode
After the last 1-unit transfer of 1 block, the subsequent
3 cycles of φ , and a read of the first 2 bytes in the
array state of the next block are performed sequentially
■ During transfer in cycle-steal transfer mode
After the last 1-unit transfer of 1 block and the
subsequent 3 cycles of φ are performed sequentially
At the end of the last block
After 1-unit transfer and terminate-processing (3 cycles
of φ ) are performed sequentially
CPU
At an array state
After a read of 2 bytes of a transfer parameter
When an instruction is
After completion of 1 bus cycle
fetched into queue buffer
At a read from or a write into After completion of 1 bus cycle, or after completion of
the second bus cycle if a 16-bit data is accessed in a
memory
unit of 8 bits (Note 2).
While CPU does not use bus Every 1 cycle of φ
Notes 1: S = Single transfer mode, R = Repeat transfer mode, Array = Array chain transfer mode, Link
= Link array chain transfer mode
2: This applies when the data bus width is 8 bits or when memory is accessed starting at an odd
address.
If a DRAM refresh request or a Hold request is generated during a data transfer in the burst transfer mode,
the request is accepted at the above-mentioned bus request sampling. Another DMA request (including that
of other channels) cannot be accepted until the DMA transfer which is in progress normally terminates or
is forced into termination.
If a DRAM refresh request, a Hold request or another DMA request (including that of other channels) is
generated during a data transfer in the cycle-steal transfer mode, the bus request with the highest priority
is accepted at the above-mentioned bus request sampling. (If only several DMA requests are generated,
the request of the channel whose priority is highest is accepted.)
If any bus request is not generated at the above-mentioned bus sampling, the right to use bus is relinquished
to the CPU.
Note that no DMA request is accepted in array states.
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DMA CONTROLLER
13.2 Block description
■ DRAM refresh
E
This is the term in which the bus is not
used so that sampi ng is performed every
1 cycle of .
Sampling is performed after completion of
a refresh cycle.
Sampling is performed after completion of
1 bus cycle.
H
Refresh request
BUS REQUEST(DRAMC)
Bus request sampling
(0, 0)
(1, 1)
ST1, ST0
(1, 1)
Refresh
Transition of right
to use bus
Transition of right
to use bus
(0, 0)
(1, 1)
Refresh
Bus used by
CPU Transition of right
to use bus
Transition of right
to use bus
■ Hold
E
This is the term in which the bus is not
used so that sampling is performed every
1 cycle of .
This is at Holol state so that sampling is
performed every 1 cycle of .
Sampling is performed after completion of
1 bus cycle.
H
HOLD
BUS REQUEST (Hold)
Bus request sampling
(0, 1)
(1, 1)
ST1, ST0
(1, 1)
Hold state
Transition of right
to use bus
Transition of right
to use bus
(1, 1)
(0, 1)
Bus used by
CPU Transition of right
to use bus
(1, 1)
Hold state
Transition of right
to use bus
■ DMA transfer
This is the term in which the bus is not
used so that sampling is performed every
1 cycle of .
Sampling is performed after completion of
1-unit transfer.
Sampling is performed after completion of
1 bus cycle.
H
E
DMAREQi
DMAi request bit
BUS REQUEST (DMAC)
Bus request sampling
ST1, ST0
(1, 1)
(1, 0)
(1, 1)
DMA transfer
Transition of right
to use bus
Transition of right
to use bus
(1, 1)
(1, 0)
(1, 1)
DMA transfer
Bus used
by CPU Transition of right
Transition of right
to use bus
to use bus
The above applies on the following conditions:
•Cycle-steal transfer mode
•DMA request source = external request (DMAREQi)
•1-bus cycle transfer
•No Wait
■ CPU
This is the term in which the bus is not
used so that sampling is performed every
1 cycle of .
Sampling is performed after completion of
1 bus cycle.
16-bit data is accessed in a unit of 8 bits,
so that sampling is performed after
completion of the second bus cycle.
E
Bus request sampling
ST1, ST0
(1, 1)
Bus used by CPU
When access When 16-bit data is accessed
is complete in in a unit of 8 bits
1 bus cycle
Fig. 13.2.3 Timing of bus request sampling
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DMA CONTROLLER
13.2 Block description
13.2.2 DMAC control register L
Figure 13.2.4 shows the structure of DMAC control register L. Bit 0 is described in section “13.3.3 Channel
priority levels,” and bits 4–7 are also in section “13.3.2 DMA requests.”
___
(1) TC pin validity bit (Bit 1)
___
___
When this bit is set to “1,” port P103 functions as the TC pin. The TC pin is of an N-channel opendrain type and provides the following functions:
● Terminal count signal output
When the transfer of an entire batch of data is normally terminated, the pin outputs “L” for 1
cycle of φ. (Refer to section “13.3.5 (1) Normal termination.”)
● Forced termination signal input
___
When the TC pin’s input level goes from “H” to “L” during DMA transfer, this DMA transfer is forced
into termination. (Refer to section “13.3.5 (2) Forced termination.”)
b7
b6
b5
b4
b3
b2
b1
b0
DMAC control register L (Address 6816)
Bit
Bit name
Functions
At reset
RW
0
Priority select bit
0 : Fixed
1 : Rotating
0
RW
1
TC pin validity bit
0 : Invalid
(P103 pin functions as a
programmable I/O port (CMOS).)
1 : Valid
(P103 pin functions as TC pin (Nchannel open-drain).)
0
RW
Undefined
–
0
RW
0
RW
3, 2
Nothing is assigned.
4
DMA0 request bit
5
DMA1 request bit
6
DMA2 request bit
0
RW
7
DMA3 request bit
0
RW
0 : No request
1 : Requested (Note 1)
Notes 1: The state of bits 4 to 7 is not changed when writing “1” to these bits.
2: • When writing to this register while any of DMAi enable bits (bits 4 to 7 at address
6916) is “1,” use the LDM or STA instruction in m flag = “1.” When DMAi request bit
(bits 4 to 7 at address 6816) must not be changed, set DMAi request bit to “1.”
• When writing to this register while all of DMAi enable bits (bits 4 to 7 at address 6916)
are “0,” m flag may be “0” or “1.” Use the LDM or STA instruction for writing to this
register. When DMAi request bit (bits 4 to 7 at address 68 16) must not be changed,
set DMAi request bit to “1.”
Fig. 13.2.4 Structure of DMAC control register L
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DMA CONTROLLER
13.2 Block description
13.2.3 DMAC control register H
Figure 13.2.5 shows the structure of DMAC control register H. Each of bits 0–3 is a software DMAi (i =
0 to 3) request bit, which corresponds to each channel. When a software DMA source is selected as a DMA
request source, each of these bits is valid. (Refer to “13.3.2 DMA requests.”) Bits 4–7 are described in
section “13.3.1 DMA enabling.”
b7
b6
b5
b4
b3
b2
b1
b0
DMAC control register H (Address 6916)
Bit
Bit name
Functions
At reset
RW
1 : DMA request
(Valid when software DMA source
is selected.)
The value is “0” at reading.
0
WO
0
WO
0
Software DMA0 request bit
1
Software DMA1 request bit
2
Software DMA2 request bit
0
WO
3
Software DMA3 request bit
0
WO
4
DMA0 enable bit
0
RW
5
DMA1 enable bit
0
RW
6
DMA2 enable bit
0
RW
7
DMA3 enable bit
0
RW
0 : Disabled
1 : Enabled
Note: When any of bits 4 to 7 is set to “1,” use the CLB or SEB instruction for writing to this
register.
Fig. 13.2.5 Structure of DMAC control register H
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DMA CONTROLLER
13.2 Block description
13.2.4 Source address register i (SARi)
Source address register i (hereafter called SARi) is a 24-bit register with a latch.
SARi indicates the transfer source address of the data to be transferred next.
The SARi latch has the following functions:
• Maintains the value written to the address of SARi (in the single transfer and repeat transfer modes).
• Indicates the start address of the transfer parameter memory of the next block (in the array chain
transfer and link array chain transfer modes).
When a value is written into the address of SARi, the same value is written into SARi and the SARi latch.
When writing a value to the address of SARi, all 24 bits must be written.
The contents of SARi can be read by reading the address of SARi; however, the value of the SARi latch
cannot be read. (Refer to “Tables 13.2.4 and 13.2.5.”)
13.2.5 Destination address register i (DARi)
Destination address register i (hereafter called DARi) is a 24-bit register with a latch.
DARi indicates the transfer destination address of the data to be transferred next.
The DARi latch maintains the value written to the address of DARi.
When a value is written into the address of DARi, the same value is written into DARi and the DARi latch.
When writing a value to the address of DARi, all 24 bits must be written.
The contents of DARi can be read by reading the address of DARi; however, the value of the DARi latch
cannot be read. (Refer to “Tables 13.2.4 and 13.2.5.”)
13.2.6 Transfer counter register i (TCRi)
Transfer counter register i (hereafter called TCRi) is a 24-bit register with a latch.
TCRi indicates the number of remaining bytes of the block under transfer.
The TCRi latch has the following functions:
• Maintains the value written to the address of TCRi (in the single transfer and repeat transfer modes).
• Indicates the number of remaining blocks (in the array chain transfer mode).
When a value is written into the address of TCRi, the same value is written into TCRi and the TCRi latch.
When writing a value to the address of TCRi, all 24 bits must be written.
The contents of TCRi can be read by reading the address of TCRi; however, the value of the TCRi latch
cannot be read. (Refer to “Tables 13.2.4 and 13.2.5.”)
Table 13.2.4 Addresses of SARi, DARi, and TCRi
13-12
Transfer counter register i
(TCRi)
1FCA16–1FC816
1FDA16–1FD816
0
Source address register i
(SARi)
1FC216–1FC0 16
1
1FD2 16–1FD016
Destination address
register i (DARi)
1FC6 16–1FC416
1FD6 16–1FD416
2
1FE216–1FE016
1FE616–1FE416
1FEA16–1FE816
3
1FF216–1FF016
1FF616–1FF416
1FFA16–1FF816
Channel
7721 Group User’s Manual
DMA CONTROLLER
13.2 Block description
Table 13.2.5 Functions of SARi, DARi, and TCRi
Mode Single transfer mode Repeat transfer mode Array chain transfer
mode
Register
SARi
SARi
Link array chain
transfer mode
Indicates the transfer source address of the data to be transferred next.
SARi latch Maintains the transfer start address of the Indicates the start address of the transfer
source.
parameter memory of the next block.
DARi
DARi
Indicates the transfer destination address of the data next to be transferred
DARi latch Maintains the transfer start address of the
destination.
TCRi
TCRi
(Not used)
(Not used)
Indicates the number of remaining bytes of the block under transfer.
TCRi latch Maintains the byte number of the transfer Indicates the number (Not used) (Note)
of remaining blocks.
data.
Note: Any value other than 0 (00000116–FFFFFF 16) must be written before DAM transfer.
13.2.7 Incrementer/Decrementer
The incrementer/decrementer is a 24-bit register. After every 1-unit transfer, that increments (adds) or
decrements (subtract) the contents of SARi and DARi.
Table 13.2.6 lists the increment/decrement values.
Table 13.2.6 Increment/Decrement values
Address directions
Transfer unit
Forward
Backward
8 bits
+ 1
– 1
16 bits
+ 2
– 2
13.2.8 Decrementer
The decrementer is a 24-bit register. After every 1-unit transfer, that decrements the contents of TCRi by
1 when the transfer unit is 8 bits, and by 2 when 16 bits.
In the array chain transfer mode, every time a transfer parameter is read, the contents of the TCRi latch
are also decremented by 1.
13.2.9 DMA latch
The DMA latch is a 16-bit latch.
In 2-bus cycle transfer mode, the DMA latch maintains the value read from the transfer source memory with
a read cycle until this value is written into the transfer destination memory.
In 1-bus cycle transfer mode, the DMA latch is used to copy data. For copy, refer to section “13.4.2 1-bus
cycle transfer.”
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DMA CONTROLLER
13.2 Block description
13.2.10 DMAi mode register L
Figure 13.2.6 shows the structure of DMAi mode register L. For bit 0, refer to section “13.1.3 (2) Transfer
unit.” For bit 1, refer to section “13.4.1 2-bus cycle transfer” and section “13.4.2 1-bus cycle transfer”;
for bit 2, refer to section “13.4.3 Burst transfer mode” and section “13.4.4 Cycle-steal transfer mode.”
(1) Transfer source address direction select bits (bits 4 and 5) and Transfer destination address
direction select bits (bits 6 and 7)
Address direction means an order of accessing memory in DMA transfer and is defined as follows:
• Fixed direction: an address does not move.
• Forward direction: an address moves upward from the specified start address.
• Backward direction: an address moves downward from the specified start address.
For details, refer to section “13.4.1 (3) Address directions in 2-bus cycle transfer” and section
“13.4.2 (3) Address directions in 1-bus cycle transfer.”
b7
b6
b5
b4
b3
0
b2
b1
b0
DMA0 mode register L (Address 1FCC16)
DMA1 mode register L (Address 1FDC16)
DMA2 mode register L (Address 1FEC16)
DMA3 mode register L (Address 1FFC16)
Bit
Functions
Bit name
At reset
RW
0
Number-of-unit-transfer-bits
select bit (Note)
0 : 16 bits
1 : 8 bits
0
RW
1
Transfer method select bit
0 : 2-bus cycle transfer
1 : 1-bus cycle transfer
0
RW
2
Transfer mode select bit
0 : Burst transfer mode
1 : Cycle-steal transfer mode
0
RW
3
Fix this bit to “0.”
0
RW
4
Transfer source address
direction select bits
0
RW
0
RW
0
RW
0
RW
5
6
Transfer destination address
direction select bits
7
b5b4
0 0 : Fixed
0 1 : Forward
1 0 : Backward
1 1 : Do not select.
b7b6
0 0 : Fixed
0 1 : Forward
1 0 : Backward
1 1 : Do not select.
Note: When the external data bus has a width of 8 bits and 1-bus cycle transfer is selected, set
bit 0 to “1.”
Fig. 13.2.6 Structure of DMAi mode register L
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DMA CONTROLLER
13.2 Block description
13.2.11 DMAi mode register H
Figure 13.2.7 shows the structure of DMAi mode register H. Bits 0 and 1 are used in 1-bus cycle transfer.
For details, refer to section “13.4.2 1-bus cycle transfer.” Bits 6 and 7 are the bits for selecting the
continuous transfer mode. For details, refer to section “13.5 Single transfer mode” through section “13.8
Link array chain transfer mode.”
(1) Transfer source wait bit and Transfer destination wait bit (bits 4 and 5)
When each of these bits is set to “1,” 1-bus cycle in a DMA transfer consumes 3 cycles of φ , and
when cleared to “0,” 2 cycles of φ .
These bits are valid for the internal and external areas. In the DRAM area, however, 1-bus cycle
consumes 3 cycles of φ regardless of the states of these bits. (Refer to “CHAPTER 14. DRAM
CONTROLLER.”)
The wait bit (bit 2 at address 5E16) is invalid in DMA transfer. However, Ready function is still valid
in DMA transfer.
b7
b6
b5
b4
b3
b2
b1
b0
0 0
DMA0 mode register H (Address 1FCD16)
DMA1 mode register H (Address 1FDD16)
DMA2 mode register H (Address 1FED16)
DMA3 mode register H (Address 1FFD16)
0
Functions
At reset
RW
0 : From memory to I/O
0
RW
Refer to below.
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
Bit name
Bit
Transfer direction select bit
(Used in 1-bus cycle transfer)(Note 1) 1 : From I/O to memory
1
I/O connection select bit
(Valid in 1-bus cycle transfer)
2
Fix these bits to “0.”
3
4
5
6
Transfer source wait bit (Note 2) 0 : Wait
1 : No Wait
Transfer destination wait bit
(Note 2)
Continuous transfer mode select
bits
b7b6
7
0 0 : Single transfer
0 1 : Repeat transfer
1 0 : Array chain transfer
1 1 : Link array chain transfer
Notes 1: Set bit 0 to “0” in 2-bus cycle transfer.
2: Bits 4 and 5 are valid to the external and internal areas. However, DRAM area is
always handled with “Wait” regardless of the contents of these bits.
The wait bit (bit 2 at address 5E16) is invalid in DMA transfer.
Setting for I/O connection select bit
Transfer method
I/O connection
External data bus width
2-bus cycle transfer
1-bus cycle transfer
Setting for I/O connection select bit
It may be either “0” or “1.”
8 bits
D0–D7
0
16 bits
D0–D15
(16-bit I/0 ✕ 1 or 8-bit I/O ✕ 2)
0
D0–D7
(8-bit I/O)
0
D8–D15
(8-bit I/O)
1
Fig. 13.2.7 Structure of DMAi mode register H
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DMA CONTROLLER
13.2 Block description
13.2.12 DMAi control register
Figure 13.2.8 shows the structure of the DMAi control register. For bits 0–4, refer to section “13.3.2
(1) DMA request sources.”
_________
(1) DMAACKi validity bit (bit 5)
_________
When this bit is set to “1,” the corresponding pin of port P9 serves as the DMAACKi pin and
outputs “L” during a DMA transfer. For details, refer to each timing diagram of section “13.5
Single transfer mode” through section “13.8 Link array chain transfer mode.”
b7
b6
b5
b4
b3
b2
b1
b0
DMA0 control register (Address 1FCE16)
DMA1 control register (Address 1FDE16)
DMA2 control register (Address 1FEE16)
DMA3 control register (Address 1FFE16)
Bit
Bit name
0
DMA request source select bits
(Note)
1
2
3
Functions
b3b2b1b0
0 0 0 0 : Do not select.
0 0 0 1 : External source (DMAREQi)
0 0 1 0 : Software DMA source
0 0 1 1 : Timer A0
0 1 0 0 : Timer A1
0 1 0 1 : Timer A2
0 1 1 0 : Timer A3
0 1 1 1 : Timer A4
1 0 0 0 : Timer B0
1 0 0 1 : Timer B1
1 0 1 0 : Timer B2
1 0 1 1 : UART0 receive
1 1 0 0 : UART0 transmit
1 1 0 1 : UART1 receive
1 1 1 0 : UART1 transmit
1 1 1 1 : A-D conversion
At reset
RW
0
RW
0
RW
0
RW
0
RW
4
Edge sense/Level sense select
bit (Used when external source
and burst transfer mode are
selected) (Note)
0 : Edge sense (Falling edge)
1 : Level sense (“L” level)
0
RW
5
DMAACKi validity bit
0 : Invalid (The pin functions as a
programmable I/O port.)
1 : Valid
(The pin functions as DMAACKi.)
0
RW
7, 6
Nothing is assigned.
Undefined
–
Note: When a certain source other than an external source is selected by bits 0 to 3 or when
the cycle-steal transfer mode is selected, set bit 4 to “0.”
Level sense can be selected only when both of the external source and the burst
transfer mode are selected.
Fig. 13.2.8 Structure of DMAi control register
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DMA CONTROLLER
13.2 Block description
13.2.13 DMAi interrupt control register
Figure 13.2.9 shows the structure of the DMAi interrupt control register. For details about interrupts, refer
to “CHAPTER 7. INTERRUPTS.”
b7
b6
b5
b4
b3
b2
b1
b0
DMAi interrupt control register (i = 0 to 3) (Addresses 6C16 to 6F16)
Bit
0
Interrupt priority level
select bits
1
2
3
Functions
Bit name
Interrupt request bit
At reset
RW
0 0 0 : Level 0 (Interrupt disabled)
0 0 1 : Level 1
Low level
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
High level
1 1 1 : Level 7
0
RW
0
RW
0
RW
0 : No interrupt requested
1 : Interrupt requested
0
RW
Undefined
–
b2 b1 b0
7 to 4 Nothing is assigned.
Fig. 13.2.9 Structure of DMAi interrupt control register
(1) Interrupt priority level select bits (bits 2 to 0)
These bits select a DMAi interrupt’s priority level. When using DMAi interrupts, select one of the
priority levels (1 to 7). When a DMAi interrupt request occurs, its priority level is compared with the
processor interrupt priority level (IPL). The requested interrupt is enabled only when its priority level
is higher than the IPL. (However, this applies when the interrupt disable flag (I) = “0.”)
To disable DMAi interrupts, set these bits to “0002” (level 0).
(2) Interrupt request bit (bit 3)
This bit is set to “1” when a DMAi interrupt request occurs after the DMA transfer is complete. This
bit is automatically cleared to “0” when the DMAi interrupt request is accepted. This bit can be set
to “1” or cleared to “0” by software.
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DMA CONTROLLER
13.2 Block description
13.2.14 Port P9 direction register
_________
I/O pins of DMAi are multiplexed with port P9. When using these pins as the DMAREQi input pins, set the
corresponding bits of the _________
port P9 direction register to “0” to set these port pins for the
input mode. When
_________
using these pins as the DMAACKi output pins, these pins are forcibly set to the DMAACKi output pins
regardless of the direction register’s contents. Figure 13.2.10 shows the relationship between the port P9
direction register and DMAi’s I/O pins.
b7
b6
b5
b4
b3
b2
b1
b0
Port P9 direction register (Address 1516)
Bit
Corresponding pin
0
DMAACK0 pin
1
DMAREQ0 pin
Functions
0 : Input mode
1 : Output mode
At reset
RW
0
RW
0
RW
0
RW
0
RW
DMAACK2 pin
0
RW
5
DMAREQ2 pin
0
RW
6
DMAACK3 pin
0
RW
7
DMAREQ3 pin
0
RW
2
DMAACK1 pin
3
DMAREQ1 pin
4
When using pins P91, P93, P95 and
P97 as DMAREQi input pins,set the
corresponding bits to “0.”
Fig. 13.2.10 Relationship between port P9 direction register and DMAi’s I/O pins
[Precautions for DMAC]
Do not access the registers relevant to DMAC by using DMA transfers; the address of the accessing register
collides with that of the accessed one on the DMAC internal bus.
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DMA CONTROLLER
13.3 Control
13.3 Control
The conditions for performing DMA transfer of DMAi (i = 0–3) are as follows:
• Neither a DRAM refresh request nor a Hold request is generated.
• A request of the channel with a higher priority than that of DMAi is not generated; or the request is
disabled though it has been generated.
• DMAi is enabled (DMAi enable bit = “1”).
• A DMAi request is generated (DMAi request bit = “1”).
The control method for each channel is described below.
13.3.1 DMA enabling
Each of DMA channels 0–3 has a DMAi enable bit (bits 4–7 at address 69 16 ). Table 13.3.1 lists the
conditions for changing each DMAi enable bit.
Table 13.3.1 Conditions for changing DMAi enable bit
DMAi enable bit
Conditions for bit change
Is set to “1.”
A write of “1” to the DMAi enable bit
Is cleared to “0.”
• A write of “0” to the DMAi enable bit
• Transfer of an entire batch of data is complete (normal termination).
___
• A change of TC input level from “H” to “L” during a DMA transfer of DMAi (Note)
___
(Forced termination, when TC pin is valid.)
Note: In the burst transfer mode (level sense), however, the term from the DMA transfer start until the
transfer completion of an entire batch of data is applied. (It is also valid while the CPU has the right
to use bus.)
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DMA CONTROLLER
13.3 Control
13.3.2 DMA requests
(1) DMA request sources
DMA request sources are specified by the DMA request source select bits and the edge sense/level
sense select bit. (Refer to “Figure 13.2.8.”)
Table 13.3.2 lists the conditions for generating a DMA request.
Table 13.3.2 Conditions for generating DMA request
DMA request sources
Condition for generating DMA request
_________
External source
________
DMAREQi
Level sense “L”-level input to the DMAREQi pin (only in the burst transfer mode)
_________
Edge sense Change of the DMAREQi input pin’s level from “H” to “L”
Software DMAi request
Timers A0–A4,
Timers B0–B2,
UART0, UART1,
A-D converter
A write of “1” to the software DMAi request bit (each of bits 0–3 at address 6916;
refer to “Figure 13.2.5.”)
When the interrupt request bit of each peripheral is set to “1” by the activity of
peripherals (If “1” is written to any of these interrupt request bits by software,
the DMAi request bit does not change. Also, whatever value within 0–7 an
interrupt priority level takes, this does not affect DMA requests.)
(2) Change of DMAi request bit
A read of the DMAi request bits (each of bits 4–7 at address 6816) indicates whether the corresponding
channel (0–3) is generating its DMA request or not. The DMAi request bit changes synchronized with
the falling edge of φ1. Table 13.3.3 lists the conditions for changing the DMAi request bit.
For the timing of changing the DMAi request bit, refer to “Figures 13.3.2 and 13.3.3.”
Table 13.3.3 Conditions for changing DMAi request bit
DMAi
Mode
request bit
Burst transfer mode
Edge sense
Level sense
Is set to “1.”
Generation of DMAi request Generation of DMAi request
(Refer to “Table 13.3.2.”)
(Note)
(“L”-level input to the
_________
DMAREQi pin)
Is cleared to “0.” • Normal termination
• “H”-level input to the
___
• Change of the TC pin’s input _________
DMAREQi pin___
level from “H ”to “L” during
___ • Change of the TC pin’s input
DMA transfer (when the TC
level___
from “H” to “L” (when
pin is valid)
the TC pin is valid)
Cycle-steal transfer mode
Generation of DMAi request
(Refer to “Table 13.3.2.”)
• Start of 1-unit transfer
___
• Change of the TC pin’s input
level from “H” to “L” during
___
DMA transfer (when the TC
pin is valid)
• A write of “0” to the DMAi • A write of “0” to the DMAi
request bit
request bit
• A write of “0” to the DMAi • A write of “0” to the DMAi
enable bit
enable bit
Note: While the DMAi enable bit is “0,” the DMAi request bit is not set to “1” even if a DMA request is
generated. When the DMAi enable bit is cleared to “0,” also the DMAi request bit is cleared to “0.”
However, the DMA request generated while the DMAi enable bit = “0” is maintained; and when the
DMAi enable bit is set to “1,” the DMAi request bit is also set to “1,” except for the burst transfer mode
(level sense).
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DMA CONTROLLER
13.3 Control
13.3.3 Channel priority levels
When the DMA enable bits of several channels are “1” and their DMA request bits are set to “1,” the
request of the channel with the highest priority is accepted first.
The fixed or rotating channel priority can be selected by the priority select bit (bit 0 at address 68 16). The
priority levels themselves cannot be specified arbitrary.
The channel priority levels are determined after the DMA requests are determined.
(1) Fixed priority
The fixed priority is selected when the priority select bit (bit 0 at address 6816) = “0.”
In the fixed priority, the channel priority levels are as follows:
channel 0 > channel 1 > channel 2 > channel 3.
(2) Rotating priority
The rotating priority is selected when the priority select bit = “1.”
After reset, the priority levels are the same descending order as in the fixed priority:
channel 0 > channel 1 > channel 2 > channel 3.
Then, after every normal termination of a DMA transfer, the priority levels rotate in such a way that
the lowest priority is given to the channel having been performed.
When DMA transfer is forced into termination, the channel priority levels does not rotate.
Figure 13.3.1 shows an example of determining the channel priority levels.
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DMA CONTROLLER
13.3 Control
● Priority level: Fixed priority
Bus request sampling
DMA0 request bit
DMA1 request bit
DMA2 request bit
DMA3 request bit
Channel priority level
:0>1>2>3
AAA
AA
AA
AA
AAA
AAAA
AA
AAAA
AA
AA
AAA
AAAA
AAAAA
AAAA
AAAAAAAAAAAAA
AAAAAAA
DMA transfer execution
channel
1
2
0
1
3
(Nothing)
0
2
1
1
0
3
● Priority level: Rotating priority
Bus request sampling
DMA0 request bit
DMA1 request bit
DMA2 request bit
DMA3 request bit
Channel priority level
AAA
AA
AA
AA
AAA
AAAA
AA
AAAA
AA
AA
AAA
AAAA
AAAAA
AAAA
AAAAAAAAAAAAA
AAAAAAA
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7721 Group User’s Manual
3
0>1>2>3
Fig. 13.3.1 Example of determining channel priority levels
2
2>3>0>1
The above timing diagram applies on the following conditions:
• No DRAM refresh request, no Hold request
• All of DMAi enable bits are “1.”
0
0>1>2>3
(Nothing)
3>0>1>2
3
1>2>3>0
1
0>1>2>3
3
0>1>2>3
2
2>3>0>1
1
0>1>2>3
3>0>1>2
2>3>0>1
0>1>2>3
DMA transfer execution
channel
1
3
3
DMA CONTROLLER
13.3 Control
13.3.4 Processing from DMA request until DMA transfer execution
DMA requests are sampled at every falling edge of φ1; when requested, the DMAi request bit is set to “1.”
Then, the channel priority levels and bus use priority levels are determined, and BUS REQUEST (DMAC)
goes “1” if any DRAM refresh request or Hold request is not generated (Note).
BUS REQUEST (DMAC) signal is sampled while the bus request sampling signal is “1” and is accepted
(DMA request acceptance).
Figure 13.3.2 shows an example of timing from the determination of a DMA request until the DMA transfer
execution.
Refer to section “13.9 DMA transfer time” for the time from DMA request generation until the CPU’s
regaining the right to use bus via DMA transfer.
Note: In the following cases, BUS REQUEST (DMAC) does not go “1.” However, the DMAi request bit
remains set to “1.” Accordingly, after completion of each state, the channel priority levels and bus
use priority levels are determined, and BUS REQUEST (DMAC) goes “1” if any DRAM refresh
request or Hold request is not generated.
● When a DMA request is generated during a burst transfer or in an array state
(However, if a DRAM refresh request or Hold request is generated during this term, its BUS
REQUEST goes “1.”)
● When a DMA request is not accepted with a DRAM refresh request or Hold request generated
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DMA CONTROLLER
13.3 Control
When DMAi request is
sampled at this point
Transition of right
to use bus
✽
1-unit transfer
Read cycle
Write cycle
✽: Channel priority level determination and bus
use priority level determination (1.5 cycles of φ)
φ1
ALE
E
R/W
Address
Address/Data
PC
SAR
DAR
PC,PG
SAR Data
DAR Data
1
DMAi enable bit
DMAREQi
When Burst transfer mode (edge sense) selected
When Burst transfer mode (level sense) selected
When Cycle-steal transfer mode selected
DMAi request bit
BUS REQUEST(DMAC)
Bus request sampling
DMAACKi
TC
H
ST1
ST0
DMAi interrupt
request bit 0
The above timing diagram applies on the following conditions:
• Single transfer mode, or Repeat transfer mode
• 2-bus cycle transfer
• No Wait
• DMAACKi valid, TC valid
• External source (DMAREQi)
• After DMAi request occurs (“L” is input to the DMAREQi pin.), the right to use bus is relinquished to DMAC
at the shortest time.
Fig. 13.3.2 Example of timing from determination of DMA request until DMA transfer execution
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DMA CONTROLLER
13.3 Control
13.3.5 Termination of DMA transfer
As the methods of terminating DMA transfer, normal and forced termination are used.
(1) Normal termination
All of the DMAi transfers terminate and DMAC stops. This method is used in the single transfer, array
chain transfer, and link array chain transfer modes. In the repeat transfer mode, however, normal
termination cannot be applied to terminating transfer; then, forced termination must be used. (Refer
to “(2) Forced termination” of this section.)
Table 13.3.4 lists the states of DMAC at normal termination.
Table 13.3.4 States of DMAC at normal termination
State
Item
DMAi interrupt request bit
1
DMAi request bit
In the burst transfer mode (edge sense): 0
In the burst transfer mode (level sense): not changed
In the cycle-steal transfer mode: not changed (Note)
DMAi enable bit
___
0
___
TC output
Outputs “L” (when the TC pin is valid)
Channel priority levels
Rotating (when the rotating priority is selected)
Note: In the cycle-steal transfer mode, the DMAi request bit is cleared to “0” when a DMA request is
accepted. This bit is does not change at normal termination.
At normal termination, the CPU regains the right to use bus after the terminate processing (3 cycles
of φ ) via the transition of the right to use bus (1 cycle of φ ). Figure 13.3.3 shows a timing example
at normal termination.
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DMA CONTROLLER
13.3 Control
Transition of
right to use bus
Terminate processing
1
ALE
L
E
R/W
Address
SAR ± 1
Address/Data
SAR ± 1
DMAi enable bit
DMAi request bit
When Burst transfer mode (edge sense) selected
When Burst transfer mode (level sense) selected
When Cycle-steal transfer mode selected
0
BUS REQUEST (DMAC)
0
Bus request sampling
DMAACKi
TC
ST1
ST0
DMAi interrupt request
bit
The above timing diagram applies on the following conditions:
• DMAACKi valid, TC valid
• External source (DMAREQi)
Fig. 13.3.3 Timing example at normal termination
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DMA CONTROLLER
13.3 Control
(2) Forced termination
The methods of
terminating DMAC other than normal termination are as follows: ___
___
• Drives the TC pin’s input level from “H” to “L” during a DMA transfer (when the TC pin is valid).
• Writes “0” to the DMAi enable bit.
Table 13.3.5 lists the states of DMAC at forced termination.
Table 13.3.5 States of DMAC at forced termination
State
Item
DMAi interrupt request bit
Not changed.
DMAi request bit
0
DMAi enable bit
0
___
TC output
Not changed.
Channel priority levels
Not changed.
___
___
When the TC pin is used for
forced termination, select “ TC pin valid” (bit 1 at address 68 16 = “1”).
___
Forced termination by the TC input is valid in the following cases:
• During a DMA transfer in the burst transfer mode (edge sense)
• During the term from the DMA transfer start until the transfer completion of an entire batch of
data in the burst transfer mode with the level sense selected. (It is also valid while the CPU has
the right to use bus).
___
• During a DMA transfer in the cycle-steal transfer mode (Forced termination by the TC input is
invalid while the CPU has the right to use bus.)
___
The TC pin’s input is determined at the falling edge of φ 1, and DMAC will relinquish the right to use
bus to the CPU upon completion of the 1-unit transfer under execution at that time.
_
At the forced termination by the DMAi enable bit, “0” is written to this bit at the rising edge of E of
a write cycle to the DMAi enable bit. Accordingly, DMAi is disabled after this write.
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DMA CONTROLLER
13.3 Control
13.3.6 DMA transfer restart after termination
(1) Restarting the same DMA transfer as the previous one from the beginning
At normal and forced termination, the latches of SARi, DARi, and TCRi maintain their values written
before the transfer start. (Refer to “Figure 13.3.4-a.”) Therefore, DMA transfer must be restarted
according to the following procedures:
● In single or repeat transfer mode
Set the DMAi enable bit to “1.” It is not necessary to re-set the values of SARi, DARi, and TCRi
by software. (Refer to “Figure 13.3.4-b.”)
● In array chain or link array chain transfer mode
Re-set the values of SARi and TCRi.
Set the DMAi enable bit to “1.”
(2) Restarting transfer of data subsequent to one which has been transferred just before forced
termination
When reading values at the addresses of SARi, DARi, and TCRi after forced termination, the values
of these registers (counters) can be read. These read values are the transfer source address, the
transfer destination address which were to be transferred subsequently, and the number of remaining
bytes.
When writing these read values to the addresses of SARi, DARi, and TCRi respectively, the same
values are also written to their latches. When setting the DMAi enable bit to “1” under this condition,
transfer of data subsequent to one which has been transferred just before forced termination is
restarted. (Refer to “Figure 13.3.4-c.”)
● In single transfer mode
The remaining data can be transferred by the following procedure:
Read the values at addresses of SARi, DARi and TCRi. Then, rewrite these values into these
addresses.
Set the DMAi enable bit to “1.”
● In repeat transfer, array chain transfer, and link array chain transfer modes
The remaining data of the block that was interrupted by forced termination can be transferred by
the following procedure:
Switch over the current mode to the single transfer mode.
Read the values at addresses of SARi, DARi and TCRi. Then, rewrite these values into these
addresses.
Set the DMAi enable bit to “1.” (Refer to “Figure 13.3.4-c.”)
In order to transfer the next block, switch over the current mode to the previous mode after the
above-mentioned transfer is normally terminated. Then, re-set the values of SARi, DARi, and
TCRi.
In the array chain or the link array chain transfer mode, information such as the next transfer
parameters etc. cannot be read from each latch.
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DMA CONTROLLER
13.3 Control
a. State at forced termination
Latch
Previously written values
Register
Addresses which were to be
transferred subsequently or the
number of remaining bytes
b. When setting DMAi enable bit to “1” without rewriting values at addresses of SARi, DARi, and TCRi
A value read from each latch is used by hardware only at the first 1-unit transfer.
The contents updated by the incrementer/decrementer and the decrementer are loaded in each register.
Values are used by reading them from registers at the second and the following 1-unit transfers.
Latch
Previously written values
Transfer source/destination address is specified.
Contents are updated by incrementer/decrementer and
decrementer.
Register
Addresses which were to be
transferred subsequently or the
number of remaining bytes
Updated contents are written.
c. When reading values at addresses of SARi, DARi, and TCRi after forced termination and rewriting them
Latch
Previously written values
Written by software
Register
Addresses which were to be
transferred subsequently or the
number of remaining bytes
Addresses which were to be
transferred subsequently or the
number of remaining bytes
Read by software
Fig.13.3.4 States of SARi, DARi, TCRi after forced termination
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DMA CONTROLLER
13.4 Operation
13.4 Operation
Operation of 1-unit transfer varies according to the data transfer method (2-bus cycle or 1-bus cycle transfer).
In addition, how many units of transfer data are transferred for a DMA request varies according to the
transfer mode (burst transfer or cycle-steal transfer mode).
These data transfer methods and modes are described below.
13.4.1 2-bus cycle transfer
When the transfer method select bit (Refer to “Figure 13.2.6.”) = “0,” 2-bus cycle transfer is selected. 2bus cycle transfer is the method used to transfer data between memories. Since this method has a read
and a write cycle, it consumes a minimum of 2 bus cycles for 1-unit transfer.
Figure 13.4.1 shows an example of connecting external memories in 2-bus cycle transfer.
M37721
Address bus
Data bus D8–D15
Data bus D0–D7
Transfer destination
memory
(Odd address)
Transfer destination
memory
(Even address)
Transfer source
memory
(Odd address)
Transfer source
memory
(Even address)
E
BHE
BLE
R/W
Note. The external circuit such as an address latch is disregarded.
Fig. 13.4.1 Example of connecting external memories in 2-bus cycle transfer
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DMA CONTROLLER
13.4 Operation
(1) Register operation in 2-bus cycle transfer
Figure 13.4.2 shows a basic operation of registers for 1-unit transfer in 2-bus cycle transfer.
For register values to be specified, refer to section “13.5 Single transfer mode” through
section “13.8 Link array chain transfer mode.” It is because that these values vary according
to continuous transfer modes.
In 2-bus cycle transfer, the data read at a read cycle is maintained temporarily in the DMA
latch, and the contents of this latch are written to a memory at a write cycle.
(1) Read cycle
Memory
DMAC
SARi
SARi latch
Incrementer/
Decrementer
DARi
DARi latch
TCRi
TCRi latch
(Transfer
source)
Decrementer
Transfer source address is specified by SARi
(Note).
Contents of TCRi are updated by decrementer
(Note) ; when value read from TCRi is “0,” transfer
of 1 data block is terminated.
Contents of SARi are updated by incrementer/
decrementer.
Data is read from memory and maintained in DMA
latch.
(Transfer
destination)
DMA latch
(2) Write cycle
DMAC
Memory
SARi
SARi latch
Incrementer/
Decrementer
DARi
DARi latch
TCRi
(Transfer
source)
Transfer destination address is specified by DARi
(Note).
Contents of DARi are updated by incrementer/
decrementer.
Contents of DMA latch are written to memory.
Decrementer
TCRi latch
DMA latch
(Transfer
destination)
✽ When the transfer unit is 16 bits
• When an even address is accessed with 16-bit external data bus width, data can be read or written at 1-bus
cycle. Accordingly, the incrementer/decrementer and the decrementer increment or decrement by 2, and
sequences through are performed once.
• When an odd address is accessed with 16-bit external data bus width or when 8 bits is used as external data
bus width, data is read or written at 2-bus cycles, and sequences through or through are repeated
twice. The incrementer/decrementer and the decrementer increment or decrement by 1 every time sequences
through or through are performed once.
Note: In the single transfer mode and repeat transfer mode, only at the first transfer of the block, the values read
from SARi latch, DARi latch, and TCRi latch are used. (The results obtained by increment or decrement are
written to SARi, DARi, and TCRi. Except for the first transfer of the block, the values read from SARi, DARi,
and TCRi are used.)
Fig. 13.4.2 Basic operation of registers for 1-unit transfer in 2-bus cycle transfer
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DMA CONTROLLER
13.4 Operation
(2) Bus operation in 2-bus cycle transfer
The time required for 1-unit transfer in 2-bus cycle transfer is given by the following formula:
Transfer time per 1-unit transfer = (Read cycle) + (Write cycle)
Since any area can be specified as a transfer source or a transfer destination, a read cycle varies
with the conditions of a transfer source, and a write cycle with that of a transfer destination.
Table 13.4.1 lists the time required for a read or write cycle per 1-unit transfer in 2-bus cycle transfer,
and Figure 13.4.3 shows the bus-cycle operation waveforms in 2-bus cycle transfer.
Table 13.4.1 Time required for a read or write cycle per
External
Transfer
Address directions
Data’s start
bus width
unit
address
16 bits
16 bits
Fixed/Forward
Even
(including
Odd
internal
Backward
Even
bus)
Odd
8 bits
8 bits
16 bits
Fixed/Forward/
Backward
Fixed/Forward/
Backward
1-unit transfer in 2-bus cycle transfer
Read/Write cycle (Unit: φ cycle)
With Wait DRAM
3 (d)
Formula
1 + i
No Wait
2 (a)
2 + 2i
4 (c)
2 + 2i
4 (c)
2 + i
3 (b)
Even/Odd
1 + i
2 (a)
3 (d)
Even/Odd
2 + 2i
4 (c)
6 (f)
area
6 (f)
6 (f)
4 (e)
4 (e)
(Note)
3 (d)
F i x e d / F o r w a r d / Even/Odd
2 (a)
1 + i
Backward
Address directions: Refer to section “13.4.1 (3) Address directions in 2-bus cycle transfer.”
_
i: A term of E = “L” in 1-bus cycle; i = 1 at “No Wait”, and i = 2 at “With Wait” or “DRAM area”.
When Ready function is used (Refer to section “3.3 Ready function.”), the number of cycles extended
by Ready must be added.
( ): Indicates the corresponding waveform in Figure 13.4.3.
8 bits
Note: When a transfer destination applies to this condition, 2-bus cycle transfer cannot be performed. When
a transfer source applies to this condition and a transfer destination is in the DRAM area, 2-bus cycle
transfer cannot also be performed.
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DMA CONTROLLER
13.4 Operation
Internal clock
A/D
(a)
A
D
A
A–1
D
A
D
A±1
E
ALE
A/D
(b)
E
ALE
A/D
(c)
D
E
ALE
A/D
(d)
A
D
E
ALE
A/D
(e)
A
A–1
D
E
ALE
A/D
(f)
A
D
A±1
D
E
ALE
A: Address, D : Data
: Read or write term per 1-unit transfer
Fig. 13.4.3 Bus-cycle operation waveforms in 2-bus cycle transfer
7721 Group User’s Manual
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DMA CONTROLLER
13.4 Operation
(3) Address directions in 2-bus cycle transfer
In 2-bus cycle transfer, the address direction of a transfer source and that of a transfer destination
each can be selected independently. (Refer to “Figure 13.2.6.”) Addresses move in the specified
direction by the transfer unit. Tables 13.4.2 through 13.4.4 list address directions in 2-bus cycle
transfer and examples of transfer result.
Tables 13.4.2 Address directions in 2-bus cycle transfer and examples of transfer result (1)
External data bus width : 16 bits or 8 bits
Address direction
Transfer unit : 8 bits
Transfer unit : 16 bits
Data arrangement
Data arrangement on Data arrangement
Data arrangement on
Transfer Transfer on transfer source Transfer
on transfer source Transfer
transfer destination
transfer destination
source destination
sequence
sequence
memory
memory
memory (transfer result)
memory (transfer result)
Fixed
Fixed
Fixed
Forward
✽
Low order
Data
High order
Low order ✽
Data
High order
✽
Low order
Data
High order
Low order ✽
Data
High order
Low order
Data
High order
Fixed
Data
Data
Data
✽
✽
Data
Data
✽
Data
Data
Low order
Data
High order
Data
Low order
Data
High order
Data
Data
Backward
✽
Low order
Data
High order
Low order
Data
High order
Low order
Data
High order ✽
✽ : Transfer start address
13-34
✽
7721 Group User’s Manual
Data
Data
✽
Data
Data
Data
Data
✽
DMA CONTROLLER
13.4 Operation
Tables 13.4.3 Address directions in 2-bus cycle transfer and examples of transfer result (2)
External data bus width : 16 bits or 8 bits
Address direction
Transfer unit : 8 bits
Transfer unit : 16 bits
Data arrangement
Data arrangement on Data arrangement
Data arrangement on
Transfer Transfer on transfer source Transfer
on transfer source Transfer
transfer destination
transfer destination
source destination
sequence
sequence
memory
memory
memory (transfer result)
memory (transfer result)
Forward
Fixed
✽
Forward
Low order ✽
Data
1–3
High order
✽
Data 1
Data 2
Low order
Data 2
High order
Data 3
Low order
Data 3
High order
Data 5
Data 1–6
✽
Data 1
Data 1
✽
Data 2
Data 2
Data 4
Data 6
Forward
✽
Forward
Low order
Data 1
High order
Low order
Data 1
High order
Low order ✽
Data 1
High order
Low order
Data 2
High order
Low order
Data 2
High order
Data 3
Data 3
Data 4
Data 4
Low order
Data 3
High order
Low order
Data 3
High order
Data 5
Data 5
Data 6
Data 6
Low order
Data 1
High order
Low order
Data 3
High order
Data 1
Data 6
Data 2
Data 5
Low order
Data 2
High order
Low order
Data 2
High order
Data 3
Data 4
Data 4
Data 3
Low order
Data 3
High order
Low order
Data 1
High order ✽
Data 5
Data 2
Data 6
Data 1
✽
Backward
✽
✽
✽
Note: The position relationship between loworder byte and high-order byte is not
reversed.
✽ : Transfer start address
7721 Group User’s Manual
13-35
DMA CONTROLLER
13.4 Operation
Tables 13.4.4 Address directions in 2-bus cycle transfer and examples of transfer result (3)
External data bus width : 16 bits or 8 bits
Address direction
Transfer unit : 16 bits
Transfer unit : 8 bits
Data arrangement
Data arrangement on Data arrangement
Data arrangement on
Transfer Transfer on transfer source Transfer
on transfer source Transfer
transfer destination
transfer destination
source destination
sequence
sequence
memory
memory
memory (transfer result)
memory (transfer result)
Backward
Fixed
Low order
Data 3
High order
✽
Backward
Forward
✽
Low order
✽
Data
1–3
High order
Data 6
Data 5
Low order
Data 2
High order
Data 4
Low order
Data 1
High order
Data 2
Data 1–6
✽
Data 6
Data 1
✽
Data 5
Data 2
Data 3
✽
Data 1
Low order
Data 3
High order
Low order
Data 1
High order
Low order
Data 2
High order
Low order
Data 2
High order
Data 4
Data 3
Data 3
Data 4
Low order
Data 1
High order
Low order
Data 3
High order
Data 2
Data 5
Data 1
Data 6
Low order
Data 3
High order
Low order
Data 3
High order
Data 6
Data 6
Data 5
Data 5
Low order
Data 2
High order
Low order
Data 2
High order
Data 4
Data 4
Data 3
Data 3
Low order
Data 1
High order
Low order
Data 1
High order ✽
Data 2
Data 2
Data 1
Data 1
✽
✽
Backward Backward
✽
✽ : Transfer start address
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7721 Group User’s Manual
✽
✽
DMA CONTROLLER
13.4 Operation
[Precautions for 2-bus cycle transfer]
When the 16-bit external data bus width = 16 bits and the transfer unit = 16 bits under the following
conditions, 2-bus cycle transfer cannot be performed. (Refer to “Table 13.4.1.”)
• Conditions for transfer destination
Transfer destination = DRAM area, Address direction = Backward, Data’s start address = Odd
address
• Conditions for transfer source and destination
Transfer source = DRAM area, Address direction = Backward, Data’s start address = Odd address
Transfer destination = DRAM area
7721 Group User’s Manual
13-37
DMA CONTROLLER
13.4 Operation
13.4.2 1-bus cycle transfer
When the transfer method select bit (Refer to “Figure 13.2.6.”) = “1,” 1-bus cycle transfer is selected.
1-bus cycle transfer is the method used to transfer data between a memory and an I/O. In this method,
a read and write of
1-tansfer-unit data are simultaneously performed during 1-bus cycle. The address bus,
____ ____
__
BHE , BLE, and R/ W indicate the states of memory.
Figure 13.4.4 shows an example of connecting external memories and I/Os in 1-bus cycle transfer.
M37721
Address bus
Data bus (D8–D15)
Data bus (D0–D7)
Memory
(Odd address)
Memory
(Even address)
I/O
I/O
E
BHE
BLE
R/W
DMAACKi
DMAREQi
Note. The external circuit such as an address latch is disregarded.
Fig. 13.4.4 Example of connecting external memories and I/Os in 1-bus cycle transfer
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7721 Group User’s Manual
DMA CONTROLLER
13.4 Operation
In 1-bus cycle transfer, the following considerations must be taken in designing the system:
• Achieve the condition that 1-transfer-unit data can be accessed in 1-bus cycle. (Refer to “Table
13.4.5.”)
• Specify the transfer address direction and I/O connections. (Refer to “Figure 13.2.7.”)
• Compose the read and write signal generating circuit externally. (These signals are for I/Os.)
The M37721 outputs signals to the memory. Accordingly, make sure to compose the circuit which
generates write signals for I/Os when the M37721 outputs read signals; which generates read
signals for I/Os when the M37721 outputs write signals. Figure 13.4.5 shows an example of the
circuit generating a write signal and a read signal for I/Os.
M37721
I/O
Generating circuit for read and write signals to I/Os
R/W
Read
DMAACKi
Write
E
DMA
acknowledge
DMA request
DMAREQi
Fig. 13.4.5 Example of circuit generating write signal and read signal for I/Os
7721 Group User’s Manual
13-39
DMA CONTROLLER
13.4 Operation
(1) Register operation in 1-bus cycle transfer
Figure 13.4.6 shows a basic operation of registers for 1-unit transfer in 1-bus cycle transfer. For
register values to be specified, refer to section “13.5 Single transfer mode” through section “13.8
Link array chain transfer mode.” It is because these values vary depending on each continuous
transfer mode. In 1-bus cycle transfer, a read and write of 1-transfer-unit data are simultaneously
performed during 1-bus cycle.
●When transferring from memory to I/O
Memory
DMAC
SARi
SARi latch
Incrementer/
Decrementer
DARi
DARi latch
TCRi
TCRi latch
DMA latch
(Transfer
source)
Decrementer
I/O
DMAACKi
Transfer source address is specified by SARi
(Note).
Contents of TCRi are updated by decrementer
(Note); when value read from TCRi is “0,” transfer
of 1 data block is terminated.
Contents of SARi are updated by incrementer/
decrementer.
I/O is specified by DMAACKi.
Data is output from memory and is written to I/O
simultaneously (R/W = H level).
(Transfer
destination)
●When transferring from I/O to memory
Memory
DMAC
SARi
SARi latch
Incrementer/
Decrementer
DARi
DARi latch
TCRi
TCRi latch
DMA latch
(Transfer
destination)
Decrementer
Transfer source address is specified by DARi (Note).
Contents of TCRi are updated by decrementer (Note);
when value read from TCRi is “0,” transfer of 1 data
block is terminated.
Contents of DARi are updated by incrementer/
decrementer.
I/O is specified by DMAACKi.
Data is output from I/O and is written to memory
simultaneously (R/W = L level).
I/O
DMAACKi
(Transfer
source)
✽ When the transfer unit is 16 bits, the incrementer/decrementer and the decrementer increment or decrement by 2.
Note: In the single transfer mode and repeat transfer mode, only at the first transfer of the block, the values read
from SARi latch, DARi latch, and TCRi latch are used. (The results obtained by increment or decrement are
written to SARi, DARi, and TCRi. Except for the first transfer of the block, the values read from SARi, DARi,
and TCRi are used.)
Fig. 13.4.6 Basic operation of registers for 1-unit transfer in 1-bus cycle transfer
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7721 Group User’s Manual
DMA CONTROLLER
13.4 Operation
(2) Bus operation in 1-bus cycle transfer
The time required for 1-unit transfer in 1-bus cycle transfer is given by the following formulas:
• Transfer from memory to I/O: Transfer time per 1-unit transfer = (Read cycle of memory)
• Transfer from I/O to memory: Transfer time per 1-unit transfer = (Write cycle of memory)
In 1-bus cycle transfer, 1-transfer-unit data is accessed in 1-bus cycle, so that limitations are imposed
on the transfer conditions to be applied. Table 13.4.5 lists the conditions of 1-bus cycle transfer and
the transfer time per 1-unit transfer, and Figure 13.4.7 shows the bus-cycle operation waveforms in
1-bus cycle transfer.
Table 13.4.5 Conditions of 1-bus cycle transfer and Transfer time per 1-unit transfer
Address directions
External
Transfer
Read/Write cycle (Unit: φ cycle)
Data’s start
bus width
unit
address
No Wait With Wait DRAM
Formula
3 (c)
16 bits
16 bits
Fixed/Forward
2 (a)
1 + i
Even
(including
internal
bus)
8 bits
area
Odd
Backward
Even
Odd
2 + i
3 (b)
1 + i
2 (a)
8 bits
Fixed/Forward/
Backward
Even/Odd
16 bits
Fixed/Forward/
Backward
Even/Odd
4 (d)
3 (c)
3 (c)
F i x e d / F o r w a r d / Even/Odd
2 (a)
1 + i
Backward
Address directions: Refer to section “13.4.2 (3) Address directions in 1-bus cycle transfer.”
There is no address direction on the I/O side.
_
i: A term of E = ‘L” in 1-bus cycle; i = 1 at “No Wait”, and i = 2 at “With Wait” or “DRAM area”.
When Ready function is used (Refer to section “3.3 Ready function.”), the number of cycles extended
by Ready must be added.
( ): Indicates the corresponding waveform in Figure 13.4.7.
/: 1-bus cycle transfer cannot be performed.
8 bits
When the external data bus width = 16 bits and the transfer unit = 8 bits are selected, the data bus
which the memory uses and the data bus to which I/O is connected may be different. In such a case,
data is copied from the data bus of a transfer source to that of a transfer destination by using the
DMA latch. For the combination that data copy may occur, data copy delay time td(data) must be taken
into consideration.
Table 13.4.6 lists the data flows on the data bus in 1-bus cycle transfer, and Table 13.4.7 lists the
outputs of the address bus, the data bus, and the bus control signals in 1-bus cycle transfer.
7721 Group User’s Manual
13-41
DMA CONTROLLER
13.4 Operation
Internal clock
A/D
A
D
A
A–1
E
(a)
ALE
A/D
(b)
D
E
ALE
A/D
(c)
A
D
E
ALE
A/D
(d)
A
A–1
D
E
ALE
A : Address, D : Data
: Transfer term per 1-unit transfer
Fig. 13.4.7 Bus-cycle operation waveforms in 1-bus cycle transfer
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DMA CONTROLLER
13.4 Operation
Table 13.4.6 Data flows on data bus in 1-bus cycle transfer
External data
Transfer
I/O
bus width
unit
connection
Read/Write address
of memory
Data flow
M37721
16 bits
Data bus
D0–D7
and
D8–D15
16 bits
Data bus D8–D15
Even address
and
Odd address
Data bus D0–D7
Memory
Memory
I/O
I/O
M37721
Data bus D8–D15
Data bus D0–D7
Even address
Memory
16 bits
Data bus
D0–D7
8 bits
Memory
I/O
M37721
Data bus D8–D15
(Note)
Data bus D0–D7
Odd address
Memory
Memory
I/O
Note: Data is copied from data bus D0–D7 to D8–D15 or from data bus D8–D15 to
D0–D7 in the M37721’s DMAC. Note the data copy delay time td(data).
M37721
Data bus D8–D15
(Note)
Even address
16 bits
Data bus
D8–D15
Data bus D0–D7
Memory
Memory
I/O
Note: Data is copied from data bus D0–D7 to D8–D15 or from data bus D8–D15 to
D0–D7 in the M37721’s DMAC. Note the data copy delay time td(data).
8 bits
M37721
Data bus D8–D15
Data bus D0–D7
Odd address
Memory
I/O
Memory
M37721
8 bits
Data bus
D0–D7
8 bits
Even address
and
Odd address
Data bus D0–D7
Memory
I/O
Note: When the memory is the internal memory or SFR, the above case for external data bus width = 16 bits
applies.
7721 Group User’s Manual
13-43
DMA CONTROLLER
13.4 Operation
Table 13.4.7 Outputs of address bus, data bus, and bus control signals in 1-bus cycle transfer
Output of address bus, data bus, and bus control signals
External
data bus
width
I/O
Transfer
connection
unit
Read/Write
address of
memory
Transferred from memory to I/O
Transferred from I/O to memory
E
R/W
H
L
16 bits
Data bus
D0–D7
and
D8–D15
16 bits
Even
address
and
Odd address
A8/D8–A15/D15
Transfer source
address
Odd address
data
Transfer destination
address
A16/D0–A23/D7
Transfer source
address
Even address
data
Transfer destination
address
BHE
L
L
L
L
BLE
Even
address
A8/D8–A15/D15
Transfer source
address
Invalid data
Transfer destination
address
A16/D0–A23/D7
Transfer source
address
Even address
data
Transfer destination
address
H
H
L
L
Invalid data
BHE
BLE
16 bits
Data bus
D0–D7
8 bits
Odd
address
A8/D8–A15/D15
Transfer source
address
Copy
Transfer destination
address
I/O data
A16/D0–A23/D7
Transfer source
address
Odd address data
Transfer destination
address
Copy
BHE
L
H
L
H
BLE
Even
address
16 bits
Data bus
D8–D15
A8/D8–A15/D15
Transfer source
address
Even address
data
Transfer destination
address
A16/D0–A23/D7
Transfer source
address
Copy
Transfer destination
address
H
H
L
L
Copy
I/O data
BHE
BLE
8 bits
Odd
address
A8/D8–A15/D15
Transfer source
address
Odd address data
Transfer destination
address
A16/D0–A23/D7
Transfer source
address
Invalid data
Transfer destination
address
BHE
L
H
Invalid data
L
H
BLE
8 bits
Data bus
D0–D7
8 bits
Even
address
and
Odd address
A8–A15
A16/D0–A23/D7
Transfer source address
Transfer source
address
Data
Transfer destination address
Transfer destination
address
: When the memory is the internal memory or SFR, data is output. When the memory is the external
memory, it enters a floating state.
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7721 Group User’s Manual
DMA CONTROLLER
13.4 Operation
(3) Address directions in 1-bus cycle transfer
In 1-bus cycle transfer, the transfer source and destination address directions of memory are selectable.
(Refer to “Figure 13.2.6.”) Addresses move in the specified direction by the transfer unit.
Tables 13.4.8 and 13.4.9 list address directions in 1-bus cycle transfer and examples of transfer
results.
Table 13.4.8 Address directions in 1-bus cycle transfer and examples of transfer results (1)
External data bus width : 16 bits or 8 bits
External data bus width : 16 bits
Address direction
Transfer unit : 16 bits
Transfer unit : 8 bits
Transfer Transfer Data arrangement
Data arrangement Transfer
source destination on transfer source Transfer Transfer destination on transfer source sequence Transfer destination
I/O
I/O
sequence
memory
memory
memory
I/O
Fixed
—
✽
Forward
Low order
Data
High order
✽
Data
Low order
Data 1
High order
Low order
Data
1–3
High order
✽
Data 1
Data
—
✽
Backward
Low order
Data
High order
Data 2
Low order
Data 2
High order
Data 3
Low order
Data 3
High order
Data 5
Data 1–6
Data 4
Data 6
—
Low order
Data 3
High order
✽
Low order
Data
1–3
High order
Data 6
Data 5
Low order
Data 2
High order
Data 4
Low order
Data 1
High order
Data 2
Data 1–6
Data 3
✽
Data 1
✽ : Transfer start
dd
7721 Group User’s Manual
13-45
DMA CONTROLLER
13.4 Operation
Table 13.4.9 Address directions in 1-bus cycle transfer and examples of transfer results (2)
External data bus width : 16 bits or 8 bits
External data bus width : 16 bits
Address direction
Transfer unit : 8 bits
Transfer unit : 16 bits
Transfer Transfer
source destination
I/O
memory
—
—
Transfer source
I/O
Data arrangement on
Transfer
transfer destination
sequence memory (transfer result)
Transfer source
I/O
Fixed
Low order
Data
High order
Low order ✽
Data
High order
Low order
Data
High order
Low order ✽
Data
High order
Forward
Low order
Data
High order
—
✽
Data
Data
✽
Data
✽
Data
Data
Data
Data
Low order
Data
High order
Data
Low order
Data
High order
Data
Data
Backward
Low order
Data
High order
Low order
Data
High order
Low order
Data
High order ✽
✽ : Transfer start
dd
13-46
Data arrangement on
Transfer
transfer destination
sequence memory (transfer result)
7721 Group User’s Manual
Data
Data
Data
Data
Data
Data
✽
DMA CONTROLLER
13.4 Operation
[Precautions for 1-bus cycle transfer]
1. The area that overlaps with internal RAM and SFRs must not be assigned to an external memory.
When the contents in the overlapped area are read, the data of internal RAM or SFRs and that of external
memory are simultaneously placed on the data bus; and they collide with each other.
2. For the system that transfers data with 16-bit external data bus width from an external memory to an
8-bit I/O, the external memory must be composed to be read in a unit of 8 bits.
If the external memory cannot be read in a unit of 8 bits, the data read from the external memory at data
copy collides with the copied data on the data bus.
3. Under the following conditions, 1-bus cycle transfer cannot be performed. (Refer to “Table 13.4.5.”):
● External data bus width = 16 bits, Transfer unit = 16 bits, Address direction of memory = Fixed or
Forward, Data’s start address of memory = Odd
● External data bus width = 16 bits, Transfer unit = 16 bits, Address direction of memory = Backward,
Data’s start address of memory = Even
● External data bus width = 16 bits, Transfer unit = 16 bits, Target memory of DMA transfer = DRAM
area, Address direction of memory = Backward, Data’s start address of memory = Odd
● External data bus width = 8 bits, Transfer unit = 16 bits
7721 Group User’s Manual
13-47
DMA CONTROLLER
13.4 Operation
13.4.3 Burst transfer mode
The burst transfer mode can operate in either edge sense or level sense mode.
(1) Burst transfer mode (edge sense)
When the transfer mode select bit = “0” and the edge sense/level sense select bit = “0,” this mode
is selected. (Refer to “Figures 13.2.6 and 13.2.8.”)
In this mode, all of the DMA request sources are available.
Figure 13.4.8 shows a transfer example in the burst transfer mode (edge sense).
When once a DMA request is accepted in this mode, an entire batch of data is transferred: the right
to use bus is not returned to the CPU until the transfer is complete.
During a burst transfer, any DMA request (including that of other channels) cannot be accepted.
However, the BUS REQUEST signal is sampled basically at every completion of 1-unit transfer.
(Refer to “Table 13.2.3.”) When a DRAM refresh request or Hold request is generated at this time,
the right to use bus is not returned to the CPU, and the request is accepted.
When the transfer of an entire batch of data is complete, the DMAC relinquishes the right to use bus
to the CPU. When the next DMA request is generated, the right is once returned to the CPU to
sample the DMA request.
(2) Burst transfer mode (level sense)
When the transfer mode select bit = “0” and the edge sense/level sense select bit = “1 ,” this mode
is selected. (Refer to “Figures 13.2.6 and 13.2.8.”)
In this mode, only the external source is used as a DMA request source. Set the DMA request source
select bits to “00012.” (Refer to “Figure 13.2.8.”)
Figure 13.4.9
shows a transfer example in the burst transfer mode (level sense).
_________
When the DMAREQi pin’s input level = “L,” the DMAi request bit is cleared to “0”; when this pin’s input
level = “L,” the DMAi request bit is set to “1.”
_________
Therefore, when _________
the DMAREQi pin’s input level is “L” with the DMAi enable bit = “1,” a DMA transfer
starts. When the DMAREQi pin’s input level goes from “L” to “H,” the right to use bus will
be returned
_________
to the CPU at completion of 1-unit transfer under execution at that time. When the DMAREQi pin’s
input level goes “L” again, the DMA transfer restarts at the next address.
Once a DMAi
transfer starts, any DMA request (including that of other channels) cannot be accepted,
_________
even if the DMAREQi pin’s input level is “H,” until the transfer is terminated normally or forcibly.
However, the BUS REQUEST signal is sampled basically at every completion of 1-unit transfer.
(Refer to “Table 13.2.3.”) When a DRAM refresh request or Hold request is generated at this time,
the right to use bus is not returned to the CPU, and the request is accepted.
When the transfer of an entire batch of data is complete, the DMAC relinquishes the right to the CPU.
If the next DMA request is generated, the right is once returned to the CPU to sample the DMA
request.
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DMA CONTROLLER
13.4 Operation
DMAREQ0
DMA0 request bit
DMA0 enable bit
DMAREQ1
DMA1 request bit
DMA1 enable bit
DRAM refresh request
Right to use bus
CPU
DMA1
DRAM
refresh
DMA1
CPU
Channel 1 Entire data transfer
DMA0
CPU
Channel 0 Entire data transfer
This example applies on the following conditions:
• Both of DMA0 and DMA1 request sources are external sources.
• Channel priority level: Fixed (Channel 0 > Channel 1)
Fig. 13.4.8 Transfer example in the burst transfer mode (edge sense)
DMAREQ0
DMA0 request bit
DMA0 enable bit
DMAREQ1
DMA1 request bit
DMA1 enable bit
DRAM refresh request
Right to use bus
CPU
DMA1
DRAM
refresh
CPU
DMA1
CPU
Channel 1 Entire data transfer
DMA0
CPU
Channel 0 Entire data transfer
This example applies on the following conditions:
• Channel priority level: Fixed (Channel 0 > Channel 1)
Fig. 13.4.9 Transfer example in the burst transfer mode (level sense)
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DMA CONTROLLER
13.4 Operation
[Precautions for burst transfer mode]
1. In the burst transfer mode (edge sense), the DMAi request bit is cleared to “0” when the transfer of an
entire batch of data is complete or the transfer is forced into termination. Therefore, another DMA request
of the same channel i is invalid if generated during DMAi transfer.
1-unit transfer
Termination processing
Transition of right to use bus
(from DMAC to CPU)
E
DMAi request bit is set to “0.”
Fig. 13.4.10 Timing when clearing DMAi request bit to “0” in burst transfer mode
2. Because interrupt priority levels are determined while the CPU fetches an operation code, interrupt
requests are not accepted during a DMA transfer. In the burst transfer mode (edge sense), therefore,
interrupt requests cannot be accepted until the transfer of an entire batch of data is complete or the
transfer is forced into termination.
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DMA CONTROLLER
13.4 Operation
13.4.4 Cycle-steal transfer mode
When the transfer mode select bit = “1” and the edge sense/level sense select bit = “0,” this mode is
selected. (Refer to “Figures 13.2.6 and 13.2.8.”)
In this mode, all of the DMA request sources are available.
Figure 13.4.11 shows a transfer example in the cycle-steal transfer mode
1-transfer-unit data is transferred for each DMA request.
The BUS REQUEST signal is sampled basically at every completion of 1-unit transfer. (Refer to “Table
13.2.3.”) When a DRAM refresh request or Hold request is generated at this time, the right to use bus is
not returned to the CPU, and the request is accepted. When several DMA requests are generated, the
request of the channel which has the highest priority among them is accepted, and DMA transfer is
performed without returning the right to use bus to the CPU. When any request is not generated, the CPU
gains the right.
DMAREQ0
DMA0 request bit
DMA0 enable bit
DMAREQ1
DMA1 request bit
DMA1 enable bit
DRAM refresh request
Right to use bus
CPU DMA1 DMA0
CPU
DMA1 DMA1 DMA0
DRAM
refresh
DMA1 CPU
This example applies on the following conditions:
• Both of DMA0 and DMA1 request sources are external sources
• Channel priority level: Fixed (Channel 0 > Channel 1)
Fig. 13.4.11 Transfer example in cycle-steal transfer mode
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DMA CONTROLLER
13.4 Operation
[Precautions for cycle-steal transfer mode]
1. When DMA transfers of the same channel are continuously performed
In the cycle-steal transfer mode, the DMAi request bit is cleared to “0” in every 1-unit transfer. Also, it
takes 1.5 cycles of φ from the generation of a DMA request until that of a BUS REQUEST (DMAC).
Therefore, if another DMA request of the same channel i is generated during a DMAi transfer in the cyclesteal transfer mode, any one of the following three cases occurs depending on the timing of request
generation:
• The DMA request becomes invalid.
• The DMA transfer continues without returning the right to use bus.
• After returning the right to use bus to the CPU, the DMAC regains the right and restarts the DMA
transfer.
1-unit transfer
φ
E
(✽)
Bus request
sampling
DMAi request bit is cleared to
“0” during this term.
DMAi request is invalid
even when DMAi request
bit becomes “1.”
DMA transfers are
continuously performed if
DMAi request bit becomes “1”
during this term (on condition
that DMAi request bit
becomes “1” at the timing
satisfying tsu(DRQ – φ1)).
After returning the right to use bus
to CPU, DMAC regains the right and
restarts DMA transfer if DMAi request
bit becomes “1” during this term.
When a DMAi request is generated at the following timings, it is not in time to the next bus request sampling (✽).
Therefore, DMAC returns the right to use bus to the CPU. Then, DMAC regains the right and restarts the DMA transfer.
• Except for the last 1-unit transfer, 1-bus cycle transfer is selected without Wait.
• Except for the last 1-unit transfer, 1-bus cycle transfer is selected with Wait. In addition, a time of 0.5 cycle of φ is
less than tsu(DRQ – φ 1).
Fig. 13.4.12 Conditions for performing DMA transfers of the same channel continuously
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DMA CONTROLLER
13.4 Operation
2. When a DMA transfer of another channel is subsequently performed
In the cycle-steal transfer mode, it takes 1.5 cycles of φ from the generation of a DMA request until that
of a BUS REQUEST (DMAC).
Therefore, if a DMA request of another channel is generated during a DMAi transfer in the cycle-steal
mode, either one of the following two cases occurs depending on its timing of request generation:
• The DMAC performs the DMA transfer subsequently without returning the right to use bus.
• After returning the right to use bus to the CPU once, the DMAC regains the right and performs the
DMA transfer.
1-unit transfer
φ
E
(✽)
Bus request
sampling
DMA transfer is subsequently performed if DMAi
request bit of another channel becomes “1” during
this term (on condition that DMAi request bit of
another channel becomes “1” at the timing
satisfying tsu(DRQ – φ1)).
After returning the right to use bus to
CPU once, DMAC regains the right and
restarts DMA transfer if DMAi request
bit of another channel becomes “1”
during this term.
When a DMA request is generated at the following timing, it is not in time to the next bus request sampling (✽).
Therefore, DMAC returns the right to use bus to the CPU. Then, the DMAC regains the right and restarts DMA transfer.
• Except for the last 1-unit transfer is selected without Wait. In addition, a time of 0.5 cycle of φ is less than tsu(DRQ – φ1).
Fig. 13.4.13 Conditions for performing DMA transfers of another channel subsequently
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DMA CONTROLLER
13.5 Single transfer mode
13.5 Single transfer mode
This mode is used to transfer a block of data once.
Table 13.5.1 lists the specifications of the single transfer mode, and Figure 13.5.1 shows the register
structures of SARi, DARi, and TCRi in this mode.
Table 13.5.1 Specifications of single transfer mode
Item
Performance specifications
Transfer parameter memory
Not required.
Condition of normal termination
TCRi = 0
Conditions of forced termination
● Falling edge of the TC pin’s input from “H” to “L”
___
___
(when the TC pin validity bit =“1”)
● Write “0” to the DMAi enable bit
Interrupt request generation timing At normal termination
Functions of registers
SARi latch: Indicates the transfer start address of data block at the
transfer source.
SARi: Indicates the address of the next transfer source.
DARi latch: Indicates the transfer start address of data block at the
transfer destination.
DARi: Indicates the address of the next transfer destination.
TCRi latch: Indicates the number of transfer bytes.
TCRi: Indicates the number of remaining transfer bytes.
___
TC pin validity bit: Bit 1 at address 6816
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DMA CONTROLLER
13.5 Single transfer mode
b23
b16 b15
b8 b7
b0
Source address register 0 (Addresses 1FC216 to 1FC016) (SAR0)
Source address register 1 (Addresses 1FD216 to 1FD016) (SAR1)
Source address register 2 (Addresses 1FE216 to 1FE016) (SAR2)
Source address register 3 (Addresses 1FF216 to 1FF016) (SAR3)
Bit
Functions
23 to 0 [Write]
Set the transfer start address of the source.
These bits can be set to “00000016” to “FFFFFF16.”
[Read]
The read value indicates the source address of data
which is next transferred.
At reset
RW
Undefined
RW
Note: When writing to this register, write to all 24 bits.
b23
b16 b15
b8 b7
b0
Destination address register 0 (Addresses 1FC616 to 1FC416) (DAR0)
Destination address register 1 (Addresses 1FD616 to 1FD416) (DAR1)
Destination address register 2 (Addresses 1FE616 to 1FE416) (DAR2)
Destination address register 3 (Addresses 1FF616 to 1FF416) (DAR3)
Bit
Functions
23 to 0 [Write]
Set the transfer start address of the destination.
These bits can be set to “00000016” to “FFFFFF16.”
[Read]
The read value indicates the destination address of
data which is next transferred.
At reset
RW
Undefined
RW
Note: When writing to this register, write to all 24 bits.
b23
b16 b15
b8 b7
b0
Transfer counter register 0 (Addresses 1FCA16 to 1FC816) (TCR0)
Transfer counter register 1 (Addresses 1FDA16 to 1FD816) (TCR1)
Transfer counter register 2 (Addresses 1FEA16 to 1FE816) (TCR2)
Transfer counter register 3 (Addresses 1FFA16 to 1FF816) (TCR3)
Bit
Functions
23 to 0 [Write]
Set the byte number of the transfer data.
These bits can be set to “00000116” to “FFFFFF16.”
[Read]
The read value indicates remaining byte number of
the transfer data.
At reset
RW
Undefined
RW
Note: When writing to this register, write to all 24 bits.
Do not set this register to “00000016.”
Fig. 13.5.1 Register structures of SARi, DARi, and TCRi in single transfer mode
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DMA CONTROLLER
13.5 Single transfer mode
13.5.1 Setting of single transfer mode
Figures 13.5.2 through 13.5.4 show an initial setting example for registers relevant to the single transfer
mode.
In addition, when timer A, timer B, UART, or the A-D converter is selected as a DMA request source, the
setting for the peripheral is required. For details of the setting, refer to the chapter of each peripheral
function.
When a DMAi interrupt is used, the setting for enabling the interrupt is also required. For details, refer to
“CHAPTER 7. INTERRUPTS.”
When external DMA source is selected
When internal DMA source is selected
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Setting port P9 direction register
b7
b0
Port P9 direction register (Address 1516)
DMAREQ0 pin
DMAREQ1 pin
DMAREQ2 pin
DMAREQ3 pin
Clear the corresponding bit to “0.”
Setting interrupt priority level
b7
b0
DMAi interrupt control register (i = 0 to 3)
(Addresses 6C16 to 6F16)
Interrupt priority level select bits
When using interrupts, set these bits to one of
levels 1 to 7.
When disabling interrupts, set these bits to
level 0.
Continue to “Figure 13.5.3” on next page.
Fig. 13.5.2 Initial setting example for registers relevant to single transfer mode (1)
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DMA CONTROLLER
13.5 Single transfer mode
From preceding “Figure 13.5.2”
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Selection of transfer mode and each function
b7
b0
0
DMA0 mode register L (Address 1FCC16)
DMA1 mode register L (Address 1FDC16)
DMA2 mode register L (Address 1FEC16)
DMA3 mode register L (Address 1FFC16)
b7
b0
Number-of-unit-transfer-bits select bit
0 : 16 bits
1 : 8 bits
DMA request source select bits
0 0 0 0 : Do not select.
0 0 0 1 : External source (DMAREQi)
0 0 1 0 : Software DMA source
0 0 1 1 : Timer A0
0 1 0 0 : Timer A1
0 1 0 1 : Timer A2
0 1 1 0 : Timer A3
0 1 1 1 : Timer A4
Transfer method select bit
0 : 2-bus cycle transfer
1 : 1-bus cycle transfer
Transfer mode select bit
0 : Burst transfer mode
1 : Cycle-steal transfer mode
b7
b0
0 0
0 0
1 0 0 0 : Timer B0
1 0 0 1 : Timer B1
1 0 1 0 : Timer B2
1 0 1 1 : UART0 receive
1 1 0 0 : UART0 transmit
1 1 0 1 : UART1 receive
1 1 1 0 : UART1 transmit
1 1 1 1 : A-D conversion
Edge sense/Level sense select bit (Note)
0 : Edge sense
1 : Level sense
Transfer source address direction select bits
0 0 : Fixed
0 1 : Forward
1 0 : Backward
1 1 : Do not select.
Transfer destination address direction select bits
0 0 : Fixed
0 1 : Forward
1 0 : Backward
1 1 : Do not select.
DMA0 control register (Address 1FCE16)
DMA1 control register (Address 1FDE16)
DMA2 control register (Address 1FEE16)
DMA3 control register (Address 1FFE16)
DMAACKi validity bit
0 : Invalid
1 : Valid
Note: When an external source (DMAREQi)
is selected or when the cycle-steal
transfer mode is selected, set this bit
to “0.”
DMA0 mode register H (Address 1FCD16)
DMA1 mode register H (Address 1FDD16)
DMA2 mode register H (Address 1FED16)
DMA3 mode register H (Address 1FFD16)
Continue to “Figure 13.5.4” on next page.
Transfer direction select bit (Used in 1-bus cycle transfer)
0 : From memory to I/O
1 : From I/O to memory
I/O connection select bit (Valid in 1-bus cycle transfer)
0 : Data bus D0–D7 or D0–D15
1 : Data bus D8–D15
Transfer source wait bit (Valid in DMA transfer)
0 : Wait
1 : No wait
Transfer destination wait bit (Valid in DMA transfer)
0 : Wait
1 : No wait
Selection of single transfer mode
(b23)
b7
(b16)(b15)
b0 b7
(b8)
b0 b7
b0
Source address register 0 (Addresses 1FC216 to 1FC016) (SAR0)
Source address register 1 (Addresses 1FD216 to 1FD016) (SAR1)
Source address register 2 (Addresses 1FE216 to 1FE016) (SAR2)
Source address register 3 (Addresses 1FF216 to 1FF016) (SAR3)
Set the transfer start address of transfer source.
These bits can be set to “00000016” to “FFFFFF16.”
(b23)
b7
(b16)(b15)
b0 b7
(b8)
b0 b7
b0
Destination address register 0 (Addresses 1FC616 to 1FC416) (DAR0)
Destination address register 1 (Addresses 1FD616 to 1FD416) (DAR1)
Destination address register 2 (Addresses 1FE616 to 1FE416) (DAR2)
Destination address register 3 (Addresses 1FF616 to 1FF416) (DAR3)
Set the transfer start address of destination.
These bits can be set to “00000016” to “FFFFFF16.”
(b23)
b7
(b16)(b15)
b0 b7
(b8)
b0 b7
b0
Transfer counter register 0 (Addresses 1FCA16 to 1FC816) (TCR0)
Transfer counter register 1 (Addresses 1FDA16 to 1FD816) (TCR1)
Transfer counter register 2 (Addresses 1FEA16 to 1FE816) (TCR2)
Transfer counter register 3 (Addresses 1FFA16 to 1FF816) (TCR3)
Set the byte number of transfer data.
These bits can be set to “00000116” to “FFFFFF16.”
Notes 1: When writing to these registers,
write to all 24 bits.
2: Do not write “00000016” to TCRi.
Note 3: When data is transferred from memory to I/O in 1-bus
cycle transfer, it is unnecessary to set DARi.
When data is transferred form I/O to memory in 1-bus
cycle transfer, it is unnecessary to set SARi.
Fig. 13.5.3 Initial setting example for registers relevant to single transfer mode (2)
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DMA CONTROLLER
13.5 Single transfer mode
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AAAAA
AAAAA
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AAA
AAA
AAA
From preceding “Figure 13.5.3”
Selection of priority level and TC pin, and setting DMAi request bit to “0”
b7
b0
0 0 0 0
DMAC control register L (Address 6816)
Priority select bit
0 : Fixed
1 : Rotating
TC pin validity bit
0 : Invalid
(P103 pin functions as a programmable I/O port.)
1 : Valid
(P103 pin functions as TC pin.)
DMA0 request bit
DMA1 request bit
DMA2 request bit
DMA3 request bit
b7
0 : No request
b0
DMAC control register H (Address 6916)
Software DMAi request bit
(Valid in software DMA source selected)
Bit 0 : Channel 0
Bit 1 : Channel 1
Bit 2 : Channel 2
Bit 3 : Channel 3
DMA0 enable bit
DMA1 enable bit
DMA2 enable bit
DMA3 enable bit
When selecting external
DMA source
0 : Disabled
1 : Enabled
When selecting internal DMA
source except software
When selecting internal
DMA source
When selecting software
DMA request
Inputting DMA request
signal to DMAREQi pin
b7
b0
DMAC control register H (Address 6916)
Software DMA0 request bit
Software DMA1 request bit
Software DMA2 request bit
Software DMA3 request bit
Interrupt request of
each peripheral
function occurs
0 : No request
1 : Requested
When writing “1,” DMA request is generated.
DMA transfer starts
Fig. 13.5.4 Initial setting example for registers relevant to single transfer mode (3)
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13.5 Single transfer mode
13.5.2 Operation in single transfer mode
Figure 13.5.5 shows the operation flowchart of the single transfer mode, and Figure 13.5.6 shows a timing
diagram of the single transfer mode (burst transfer mode).
For the cycle-steal transfer mode, refer to the following:
• All transfers except for the last 1-unit transfer: Figure 13.8.12
• Last 1-unit transfer: Figure 13.8.14
Also, refer to section “13.2.1 Bus access control circuit” for the bus request sampling during transfer.
DMAi request bit ← 0
(Only in cycle-steal transfer mode)
1-unit transfer
(Refer to section “13.4 Operation.”)
Transfer completion of
1 block ?
N
Y
1
Burst·Edge
Burst·Level·L
Cycle-steal·Requested
DMAi request bit ?
TC “L” output (Note)
DMAi interrupt request bit ← 1
DMAi enable bit ← 0
0
Burst·Level·H
Cycle-Steal·No request
Note: When TC pin validity bit is “1”
DMAi request bit ← 0
(Only burst·edge)
Burst·Edge
Burst·Level·L
Burst·Level·H
Cycle-steal·Requested
Cycle-steal·No request
: In burst transfer mode (edge sense)
: In burst transfer mode (level sense) with DMAREQi pin’s input level = L
: In burst transfer mode (level sense) with DMAREQi pin’s input level = H
: In cycle-steal transfer mode with any request of DMA0–3
: In cycle-steal transfer mode wit h no request of DMA0–3
Fig. 13.5.5 Operation flowchart of single transfer mode
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PG
A16/D0–A23/D7
(sar+2) L
(dar+2) L
(sar+4) L
(dar+4) L
1, 0 (DMAC)
Fig. 13.5.6 Timing diagram of single transfer mode (burst transfer mode)
● The Bus request caused by DRAM refresh or Hold is sampled while the bus
request sampling signal is “1,” and is accepted.
sar+5
sar
Data 2
Data 1
Data 0
H
L
H
L
H
L
Memory
Data 0L (sar+2) H Data 1L (dar+2) H Data 1L (sar+4) H Data 2L (dar+4) H Data 2L
Data 0H (sar+2) M Data 1H (dar+2) M Data 1H (sar+4) M Data 2H (dar+4) M Data 2H
Write cycle
dar H
1-unit transfer
Read cycle
Data 0L
dar M
darL
● This example applies on the following conditions:
External data bus width
: 16 bits
Transfer unit
: 16 bits
Transfer method
: 2-bus cycle transfer
Transfer mode
: Burst
Transfer source address direction
: Forward
Transfer destination address direction : Forward
Transfer source Wait
: No
Transfer destination Wait
: No
sar
: The value which is set to SARi (even)
dar
: The value which is set to DARi (even)
TCR set value
:6
Right to use bus
: CPU → DMAC → CPU
ST1, ST0
TC
DMAACKi
sar H
Data 0H
sarL
sar M
Transition of
right to use bus
PC H
A8/D8–A15/D15
Bus request sampling
PCL
A0–A7
R/W
E
ALE
φ
PG
(sar+6) L
Transfer
dar+5
dar
Transition of
right to use bus
Terminate processing
PC H
(sar+6) M
1, 1 (CPU)
PCL
(sar+6) L
DMA CONTROLLER
13.5 Single transfer mode
DMA CONTROLLER
13.6 Repeat transfer mode
13.6 Repeat transfer mode
This mode is used to transfer one block of data repeatedly. Table 13.6.1 lists the specifications of the repeat
transfer mode, and Figure 13.6.1 shows the register structures of SARi, DARi, and TCRi in this mode.
Table 13.6.1 Specifications of repeat transfer mode
Item
Performance specifications
Transfer parameter memory
Not required
Condition of normal termination
Conditions of forced termination
— (No normal termination)
___
● Falling edge of the TC pin’s input from “H” to “L”
___
(when the TC pin validity bit = “1”)
● Write “0” to the DMAi enable bit
Interrupt request generation timing No request is generated.
Functions of registers
SARi latch: Indicates the transfer start address of data block at the
transfer source.
SARi: Indicates the address of the next transfer source.
DARi latch: Indicates the transfer start address of data block at the
transfer destination.
DARi: Indicates the address of the next transfer destination.
TCRi latch: Indicates the number of transfer bytes.
TCRi: Indicates the number of remaining bytes being transferred.
___
TC pin validity bit: Bit 1 at address 68 16
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DMA CONTROLLER
13.6 Repeat transfer mode
b23
b16 b15
b8 b7
b0
Source address register 0 (Addresses 1FC216 to 1FC016) (SAR0)
Source address register 1 (Addresses 1FD216 to 1FD016) (SAR1)
Source address register 2 (Addresses 1FE216 to 1FE016) (SAR2)
Source address register 3 (Addresses 1FF216 to 1FF016) (SAR3)
Bit
Functions
23 to 0 [Write]
Set the transfer start address of the source.
These bits can be set to “00000016” to “FFFFFF16.”
[Read]
The read value indicates the source address of data
which is next transferred.
At reset
RW
Undefined
RW
Note: When writing to this register, write to all 24 bits.
b23
b16 b15
b8 b7
b0
Destination address register 0 (Addresses 1FC616 to 1FC416) (DAR0)
Destination address register 1 (Addresses 1FD616 to 1FD416) (DAR1)
Destination address register 2 (Addresses 1FE616 to 1FE416) (DAR2)
Destination address register 3 (Addresses 1FF616 to 1FF416) (DAR3)
Bit
Functions
23 to 0 [Write]
Set the transfer start address of the destination.
These bits can be set to “00000016” to “FFFFFF16.”
[Read]
The read value indicates the destination address of
data which is next transferred.
At reset
RW
Undefined
RW
Note: When writing to this register, write to all 24 bits.
b23
b16 b15
b8 b7
b0
Transfer counter register 0 (Addresses 1FCA16 to 1FC816) (TCR0)
Transfer counter register 1 (Addresses 1FDA16 to 1FD816) (TCR1)
Transfer counter register 2 (Addresses 1FEA16 to 1FE816) (TCR2)
Transfer counter register 3 (Addresses 1FFA16 to 1FF816) (TCR3)
Bit
Functions
23 to 0 [Write]
Set the byte number of transfer data.
These bits can be set to “00000116” to “FFFFFF16.”
[Read]
The read value indicates the remaining byte number
of the block which is being transferred.
Note: When writing to this register, write to all 24 bits.
Do not write “00000016” to this register.
Fig. 13.6.1 Register structures of SARi, DARi, and TCRi in repeat transfer mode
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At reset
RW
Undefined
RW
DMA CONTROLLER
13.6 Repeat transfer mode
13.6.1 Setting of repeat transfer mode
Figures 13.6.2 through 13.6.4 show an initial setting example for registers relevant to the repeat transfer
mode. In addition, when timer A, timer B, UART, or the A-D converter is selected as a DMA request source,
the setting for the peripheral is required. For details of the setting, refer to the chapter of each peripheral
function.
In this mode, only the forced termination can terminate the DMA transfer. (Refer to section “13.3.5 (2)
Forced termination.” Therefore, in the burst transfer mode (edge sense selected), be sure to validate the
___
TC pin.
When external DMA source is selected
When internal DMA source is selected
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Setting port P9 direction register
b7
b0
Port P9 direction register (Address 1516)
DMAREQ0 pin
DMAREQ1 pin
DMAREQ2 pin
DMAREQ3 pin
Clear the corresponding bit to “0.”
Continue to “Figure 13.6.3” on next page.
Fig. 13.6.2 Initial setting example for registers relevant to repeat transfer mode (1)
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DMA CONTROLLER
13.6 Repeat transfer mode
From preceding “Figure 13.6.2”
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Selection of transfer mode and each function
b7
b0
0
DMA0 mode register L (Address 1FCC16)
DMA1 mode register L (Address 1FDC16)
DMA2 mode register L (Address 1FEC16)
DMA3 mode register L (Address 1FFC16)
b7
b0
Number-of-unit-transfer-bits select bit
0 : 16 bits
1 : 8 bits
DMA request source select bits
1 0 0 0 : Timer B0
0 0 0 0 : Do not select.
0 0 0 1 : External source (DMAREQi) 1 0 0 1 : Timer B1
0 0 1 0 : Software DMA source
1 0 1 0 : Timer B2
0 0 1 1 : Timer A0
1 0 1 1 : UART0 receive
0 1 0 0 : Timer A1
1 1 0 0 : UART0 transmit
0 1 0 1 : Timer A2
1 1 0 1 : UART1 receive
0 1 1 0 : Timer A3
1 1 1 0 : UART1 transmit
0 1 1 1 : Timer A4
1 1 1 1 : A-D conversion
Transfer method select bit
0 : 2-bus cycle transfer
1 : 1-bus cycle transfer
Transfer mode select bit
0 : Burst transfer mode
1 : Cycle-steal transfer mode
Edge sense/Level sense select bit (Note)
0 : Edge sense
1 : Level sense
Transfer source address direction select bits
0 0 : Fixed
0 1 : Forward
1 0 : Backward
1 1 : Do not select.
Transfer destination address direction select bits
0 0 : Fixed
0 1 : Forward
1 0 : Backward
1 1 : Do not select.
b7
b0
0 1
0 0
DMA0 mode register H (Address 1FCD16)
DMA1 mode register H (Address 1FDD16)
DMA2 mode register H (Address 1FED16)
DMA3 mode register H (Address 1FFD16)
DMA0 control register (Address 1FCE16)
DMA1 control register (Address 1FDE16)
DMA2 control register (Address 1FEE16)
DMA3 control register (Address 1FFE16)
DMAACKi validity bit
0 : Invalid
1 : Valid
Note: When an external source (DMAREQi)
is selected or when the cycle-steal
transfer mode is selected, set this bit
to “0.”
Continue to “Figure 13.6.4” on next page.
Transfer direction select bit (Used in 1-bus cycle
transfer)
0 : From memory to I/O
1 : From I/O to memory
I/O connection select bit (Valid in 1-bus cycle
transfer)
0 : Data bus D0–D7 or D0–D15
1 : Data bus D8–D15
Transfer source wait bit (Valid in DMA
transfer)
0 : Wait
1 : No wait
Transfer destination wait bit (Valid in DMA
transfer)
0 : Wait
1 : No wait
Selection of repeat transfer mode
(b23)
b7
(b16)(b15)
b0 b7
(b8)
b0 b7
b0
Source address register 0 (Addresses 1FC216 to 1FC016) (SAR0)
Source address register 1 (Addresses 1FD216 to 1FD016) (SAR1)
Source address register 2 (Addresses 1FE216 to 1FE016) (SAR2)
Source address register 3 (Addresses 1FF216 to 1FF016) (SAR3)
Set the transfer start address of transfer source.
These bits can be set to “00000016” to “FFFFFF16.”
(b23)
b7
(b16)(b15)
b0 b7
(b8)
b0 b7
b0
Destination address register 0 (Addresses 1FC616 to 1FC416) (DAR0)
Destination address register 1 (Addresses 1FD616 to 1FD416) (DAR1)
Destination address register 2 (Addresses 1FE616 to 1FE416) (DAR2)
Destination address register 3 (Addresses 1FF616 to 1FF416) (DAR3)
Set the transfer start address of destination.
These bits can be set to “00000016” to “FFFFFF16.”
(b23)
b7
(b16)(b15)
b0 b7
(b8)
b0 b7
b0
Transfer counter register 0 (Addresses 1FCA16 to 1FC816) (TCR0)
Transfer counter register 1 (Addresses 1FDA16 to 1FD816) (TCR1)
Transfer counter register 2 (Addresses 1FEA16 to 1FE816) (TCR2)
Transfer counter register 3 (Addresses 1FFA16 to 1FF816) (TCR3)
Set the byte number of transfer data.
These bits can be set to “00000116” to “FFFFFF16.”
Notes 1: When writing to these registers,
write to all 24 bits.
2: Do not write “00000016” to TCRi.
Note 3: When data is transferred from memory to I/O in 1-bus
cycle transfer, it is unnecessary to set DARi.
When data is transferred form I/O to memory in 1-bus
cycle transfer, it is unnecessary to set SARi.
Fig. 13.6.3 Initial setting example for registers relevant to repeat transfer mode (2)
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DMA CONTROLLER
13.6 Repeat transfer mode
From preceding “Figure 13.6.3”
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Selection of priority level and TC pin, and setting DMAi request bit to “0”
b7
b0
0 0 0 0
DMAC control register L (Address 6816)
Priority select bit
0 : Fixed
1 : Rotating
TC pin validity bit
0 : Invalid
(P103 pin functions as a programmable I/O port.)
1 : Valid
(P103 pin functions as TC pin.)
DMA0 request bit
DMA1 request bit
DMA2 request bit
DMA3 request bit
0 : No request
Note: When the burst transfer mode (edge sense) is selected, set bit 1 to “1.”
b7
b0
DMAC control register H (Address 6916)
Software DMAi request bit
(Valid in software DMA source selected)
Bit 0 : Channel 0
Bit 1 : Channel 1
Bit 2 : Channel 2
Bit 3 : Channel 3
DMA0 enable bit
DMA1 enable bit
DMA2 enable bit
DMA3 enable bit
When selecting external
DMA source
0 : Disabled
1 : Enabled
When selecting internal DMA
source except software
When selecting internal
DMA source
When selecting software
DMA request
Inputting DMA request
signal to DMAREQi pin
b7
b0
DMAC control register H (Address 6916)
Software DMA0 request bit
Software DMA1 request bit
Software DMA2 request bit
Software DMA3 request bit
Interrupt request of
each peripheral
function occurs
0 : No request
1 : Requested
When writing “1,” DMA request is generated.
DMA transfer starts
Fig. 13.6.4 Initial setting example for registers relevant to repeat transfer mode (3)
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DMA CONTROLLER
13.6 Repeat transfer mode
13.6.2 Operation in repeat transfer mode
Figure 13.6.5 shows the operation flowchart of the repeat transfer mode, and Figure 13.6.6 shows a timing
diagram of the repeat transfer mode (burst transfer mode).
For the cycle-steal transfer mode, refer to the following:
• All transfers except for the last 1-unit transfer: Figure 13.8.12
• Last 1-unit transfer: Figure 13.8.13
Also, refer to section “13.2.1 Bus access control circuit” for the bus request sampling during transfer.
DMAi request bit ← 0
(Only in cycle-steal transfer mode)
1-unit transfer
(Refer to section “13.4 Operation.”)
1
Burst·Edge
Burst·Level·L
Cycle-steal·Requested
DMAi request bit ?
0
Burst·Edge
Burst·Level·L
Burst·Level·H
Cycle-steal·Requested
Cycle-steal·No request
Burst·Level·H
Cycle-steal·No request
: In burst transfer mode (edge sense)
: In burst transfer mode (level sense) with DMAREQi pin’s input level = L
: In burst transfer mode (level sense) with DMAREQi pin’s input level = H
: In cycle-steal transfer mode with any request of DMA0–3
: In cycle-steal transfer mode with no request of DMA0–3
Fig. 13.6.5 Operation flowchart of repeat transfer mode
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darH
Data0L
Data0H
(dar+4)H
Data2L
1, 0 (DMAC)
(sar+4)H Data2 L
Data2H
(dar+4) L
(sar+4)M Data2H (dar+4)M
(sar+4) L
Transfer of entire batch of data (first)
1-unit transfer
Data0L
sar H
darM
dar L
● The Bus request caused by DRAM refresh or Hold is sampled while the bus
request sampling signal is “1,” and is accepted.
● This example applies on the following conditions:
External data bus width
: 16 bits
Transfer unit
: 16 bits
Transfer method
: 2-bus cycle transfer
Transfer mode
: Burst
Transfer source address direction
: Forward
Transfer destination address direction : Forward
Transfer source Wait
: No
Transfer destination Wait
: No
sar
: The value which is set to SARi (even)
dar
: The value which is set to DARi (even)
TCR set value
:6
Right to use bus
: CPU → DMAC
ST1, ST0
TC
DMAACKi
Data0H
sar L
sar M
Transition of
right to use bus
PG
A16/D0–A23/D7
H
PCH
A8/D8–A15/D15
Bus request sampling
PCL
A0–A7
R/W
E
ALE
φ
sarH
(sar+6) L
Data0L
Data0H
dar H
dar M
dar L
sar+5
sar
Data 2
Data 1
Data 0
H
L
H
L
H
L
Memory
Transfer
dar+5
dar
Transfer of entire batch of data (second)
sarM
sar L
(sar+6) M
(sar+6) L
DMA CONTROLLER
13.6 Repeat transfer mode
Fig. 13.6.6 Timing diagram of repeat transfer mode (burst transfer mode)
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DMA CONTROLLER
13.7 Array chain transfer mode
13.7 Array chain transfer mode
This mode is used to transfer several blocks of data. According to the information of each block stored in
memory area (Note), several blocks of data are transferred. All of the transfer parameters must be located
in series. Table 13.7.1 lists the specifications of the array chain transfer mode, and Figure 13.7.1 shows the
register structures of SARi, DARi, and TCRi in this mode.
Note: Each of the following information is called “transfer parameter”: transfer start addresses of transfer
source and destination, and transfer data’s byte number.
Table 13.7.1 Specifications of array chain transfer mode
Item
Performance specifications
Transfer parameter memory
Required.
● In 2-bus cycle transfer: 12 bytes per one block
(transfer source’s transfer start address, transfer destination’s transfer
start address, transfer data’s byte number)
● In 1-bus cycle transfer: 8 bytes per one block
(from memory to I/O: transfer source’s transfer start address, transfer
data’s byte number)
(from I/O to memory: transfer destination’s transfer start address,
transfer data’s byte number)
Condition of normal termination
TCRi latch = 0 and TCRi = 0
Conditions of forced termination
● Falling edge of the TC pin’s input from “H” to “L”
___
___
(when the TC pin validity bit = “1”)
● Write “0” to the DMAi enable bit
Interrupt request generation timing At normal termination
SARi latch: Indicates the transfer parameter memory’s start address of
Functions of registers
the next block.
SARi: Indicates the address of the next transfer source.
DARi latch: Not used.
DARi: Indicates the address of the next transfer destination.
TCRi latch: Indicates the number of remaining transfer blocks.
TCRi: Indicates the number of remaining transfer bytes.
___
TC pin validity bit: Bit 1 at address 6816
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13.7 Array chain transfer mode
b23
b16 b15
b8 b7
b0
Source address register 0 (Addresses 1FC216 to 1FC016) (SAR0)
Source address register 1 (Addresses 1FD216 to 1FD016) (SAR1)
Source address register 2 (Addresses 1FE216 to 1FE016) (SAR2)
Source address register 3 (Addresses 1FF216 to 1FF016) (SAR3)
Bit
Functions
23 to 0 [Write]
Set the start address of transfer parameter memory.
These bits can be set to “00000016” to “FFFFFF16.”
[Read]
• After a value is written to this register and until
transfer starts, the read value indicates the written
value (the start address of the transfer parameter
memory).
• After transfer starts, the read value indicates the
source address of data which is next transferred.
At reset
RW
Undefined
RW
Note: When writing to this register, write to all 24 bits.
b23
b16 b15
b8 b7
b0
Destination address register 0 (Addresses 1FC616 to 1FC416) (DAR0)
Destination address register 1 (Addresses 1FD616 to 1FD416) (DAR1)
Destination address register 2 (Addresses 1FE616 to 1FE416) (DAR2)
Destination address register 3 (Addresses 1FF616 to 1FF416) (DAR3)
Bit
Functions
23 to 0 Need not to be set.
[Read]
After transfer starts, the read value indicates the
destination address of data which is next transferred.
b23
b16 b15
b8 b7
At reset
RW
Undefined
RW
b0
Transfer counter register 0 (Addresses 1FCA16 to 1FC816) (TCR0)
Transfer counter register 1 (Addresses 1FDA16 to 1FD816) (TCR1)
Transfer counter register 2 (Addresses 1FEA16 to 1FE816) (TCR2)
Transfer counter register 3 (Addresses 1FFA16 to 1FF816) (TCR3)
Bit
Functions
23 to 0 [Write]
Set the number of transfer blocks.
These bits can be set to “00000116” to “FFFFFF16.”
[Read]
• After a value is written to this register and until
transfer starts, the read value indicates the written
value (the transfer block number) .
• After transfer starts, the read value indicates the
remaining byte number of the block which is being
transferred.
At reset
RW
Undefined
RW
Note: When writing to this register, write to all 24 bits.
Do not write “00000016” to this register.
Fig. 13.7.1 Register structures of SARi, DARi, and TCRi in array chain transfer mode
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DMA CONTROLLER
13.7 Array chain transfer mode
13.7.1 Transfer parameter memory in array chain transfer mode
The transfer parameters required for each transfer method are described below. These parameters must
be located in series starting at an even addresses.
Figure 13.7.2 shows a transfer parameter memory map in the array chain transfer mode.
(1) In 2-bus cycle transfer
All of the following transfer parameters are required for each block of data; that is, a transfer
parameter memory consumes 12 bytes for each block.
• Transfer source’s transfer start address (24 bits) + Dummy data (8 bits)
• Transfer destination’s transfer start address (24 bits) + Dummy data (8 bits)
• Transfer data’s byte number (24 bits) + Dummy data (8 bits)
(2) In 1-bus cycle transfer from memory to I/O
All of the following transfer parameters are required for each block of data; that is, a transfer
parameter memory consumes 8 bytes for each block.
• Transfer source’s transfer start address (24 bits) + Dummy data (8 bits)
• Transfer data’s byte number (24 bits) + Dummy data (8 bits)
(3) In 1-bus cycle transfer from I/O to memory
All of the following transfer parameters are required for each block of data; that is, a transfer
parameter memory consumes 8 bytes for each block.
• Transfer destination’s transfer start address (24 bits) + Dummy data (8 bits)
• Transfer data’s byte number (24 bits) + Dummy data (8 bits)
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13.7 Array chain transfer mode
(1) 2-bus cycle transfer
Transfer source’s transfer start address 1
4 bytes
Transfer destination’s transfer start address 1
4 bytes
Transfer data’s byte number 1
L Even address
source’s transfer M
start address
H
Transfer
Dummy data
Transfer source’s transfer start address 2
Transfer destination’s transfer start address 2
Transfer data’s byte number 2
Transfer source’s transfer start address 3
L Even address
destination’s transfer M
H
start address
Transfer
Transfer destination’s transfer start address 3
Dummy data
Transfer data’s byte number 3
Transfer source’s transfer start address 4
L
Even address
Transfer data’s
M
byte number
Transfer parameters for 1 block
4 bytes
H
Transfer destination’s transfer start address 4
Transfer data’s byte number 4
Dummy data
✽ The above applies when 4-block transfer
is performed.
(2) 1-bus cycle transfer
4 bytes
Transfer source’s transfer start address 1
Transfer
Transfer data’s byte number 1
source’s transfer M
Transfer source’s transfer start address 2
start address
Even address
H
Dummy data
Transfer data’s byte number 2
L
Transfer source’s transfer start address 3
Transfer data’s byte number 3
L
Transfer data’s
M
byte number
H
Transfer source’s transfer start address 4
Transfer data’s byte number 4
Dummy data
Even address
Transfer parameters for 1 block
4 bytes
✽ The above applies on the following conditions:
•When data is transferred from memory to I/O
(When transferring from I/O to memory, replace all the above mentioned “Transfer source’s
transfer start address” with “Transfer destination’s transfer start address.”)
•4-block transfer
Fig. 13.7.2 Transfer parameter memory map in array chain transfer mode
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DMA CONTROLLER
13.7 Array chain transfer mode
13.7.2 Setting of array chain transfer mode
Figures 13.7.3 through 13.7.5 show an initial setting example for registers relevant to the array chain
transfer mode.
In addition, when timer A, timer B, UART, or the A-D converter is selected as a DMA request source, the
setting for the peripheral is required. For details of the setting, refer to the chapter of each peripheral
function.
When a DMAi interrupt is used, the setting for enabling the interrupt is also required. For details, refer to
“CHAPTER 7. INTERRUPTS.”
When external DMA source is selected
When internal DMA source is selected
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Setting port P9 direction register
b7
b0
Port P9 direction register (Address 1516)
DMAREQ0 pin
DMAREQ1 pin
DMAREQ2 pin
DMAREQ3 pin
Clear the corresponding bit to “0.”
Setting interrupt priority level
b7
b0
DMAi interrupt control register (i = 0 to 3)
(Addresses 6C16 to 6F16)
Interrupt priority level select bits
When using interrupts, set these bits to one of
levels 1 to 7.
When disabling interrupts, set these bits to
level 0.
Continue to “Figure 13.7.4” on next page.
Fig. 13.7.3 Initial setting example for registers relevant to array chain transfer mode (1)
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DMA CONTROLLER
13.7 Array chain transfer mode
From preceding “Figure 13.7.3”
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Selection of transfer mode and each function
b7
b0
0
DMA0 mode register L (Address 1FCC16)
DMA1 mode register L (Address 1FDC16)
DMA2 mode register L (Address 1FEC16)
DMA3 mode register L (Address 1FFC16)
b7
Number-of-unit-transfer-bits select bit
0 : 16 bits
1 : 8 bits
Transfer mode select bit
0 : Burst transfer mode
1 : Cycle-steal transfer mode
b0
1 0
0 0
1 0 0 0 : Timer B0
1 0 0 1 : Timer B1
1 0 1 0 : Timer B2
1 0 1 1 : UART0 receive
1 1 0 0 : UART0 transmit
1 1 0 1 : UART1 receive
1 1 1 0 : UART1 transmit
1 1 1 1 : A-D conversion
Edge sense/Level sense select bit (Note)
0 : Edge sense
1 : Level sense
Transfer source address direction select bits
0 0 : Fixed
0 1 : Forward
1 0 : Backward
1 1 : Do not select.
b7
DMA0 control register (Address 1FCE16)
DMA1 control register (Address 1FDE16)
DMA2 control register (Address 1FEE16)
DMA3 control register (Address 1FFE16)
DMA request source select bits
0 0 0 0 : Do not select.
0 0 0 1 : External source (DMAREQi)
0 0 1 0 : Software DMA source
0 0 1 1 : Timer A0
0 1 0 0 : Timer A1
0 1 0 1 : Timer A2
0 1 1 0 : Timer A3
0 1 1 1 : Timer A4
Transfer method select bit
0 : 2-bus cycle transfer
1 : 1-bus cycle transfer
Transfer destination address direction select bits
0 0 : Fixed
0 1 : Forward
1 0 : Backward
1 1 : Do not select.
b0
DMAACKi validity bit
0 : Invalid
1 : Valid
Note: When an external source (DMAREQi)
is selected or when the cycle-steal
transfer mode is selected, set this bit
to “0.”
DMA0 mode register H (Address 1FCD16)
DMA1 mode register H (Address 1FDD16)
DMA2 mode register H (Address 1FED16)
DMA3 mode register H (Address 1FFD16)
Continue to “Figure 13.7.5” on next page.
Transfer direction select bit (Used in 1-bus cycle transfer)
0 : From memory to I/O
1 : From I/O to memory
I/O connection select bit (Valid in 1-bus cycle transfer)
0 : Data bus D0–D7 or D0–D15
1 : Data bus D8–D15
Transfer source wait bit (Valid in DMA transfer)
0 : Wait
1 : No wait
Transfer destination wait bit (Valid in DMA transfer)
0 : Wait
1 : No wait
Selection of array chain transfer mode
(b23)
b7
(b16)(b15)
b0 b7
(b8)
b0 b7
b0
Source address register 0 (Addresses 1FC216 to 1FC016) (SAR0)
Source address register 1 (Addresses 1FD216 to 1FD016) (SAR1)
Source address register 2 (Addresses 1FE216 to 1FE016) (SAR2)
Source address register 3 (Addresses 1FF216 to 1FF016) (SAR3)
Set the start address of transfer parameter memory.
These bits can be set to “00000016” to “FFFFFF16.”
(b23)
b7
(b16)(b15)
b0 b7
(b8)
b0 b7
b0
Transfer counter register 0 (Addresses 1FCA16 to 1FC816) (TCR0)
Transfer counter register 1 (Addresses 1FDA16 to 1FD816) (TCR1)
Transfer counter register 2 (Addresses 1FEA16 to 1FE816) (TCR2)
Transfer counter register 3 (Addresses 1FFA16 to 1FF816) (TCR3)
Set the number of transfer blocks.
These bits can be set to “00000116” to “FFFFFF16.”
Notes 1: When writing to these registers,
write to all 24 bits.
2: Do not write “00000016” to TCRi.
Fig. 13.7.4 Initial setting example for registers relevant to array chain transfer mode (2)
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DMA CONTROLLER
13.7 Array chain transfer mode
From preceding “Figure 13.7.4”
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Selection of priority level and TC pin, and setting DMAi request bit to “0”
b7
b0
0 0 0 0
DMAC control register L (Address 6816)
Priority select bit
0 : Fixed
1 : Rotating
TC pin validity bit
0 : Invalid
(P103 pin functions as a programmable I/O port.)
1 : Valid
(P103 pin functions as TC pin.)
DMA0 request bit
DMA1 request bit
DMA2 request bit
DMA3 request bit
b7
0 : No request
b0
DMAC control register H (Address 6916)
Software DMAi request bit
(Valid in software DMA source selected)
Bit 0 : Channel 0
Bit 1 : Channel 1
Bit 2 : Channel 2
Bit 3 : Channel 3
DMA0 enable bit
DMA1 enable bit
DMA2 enable bit
DMA3 enable bit
When selecting external
DMA source
0 : Disabled
1 : Enabled
When selecting internal DMA
source except software
When selecting internal
DMA source
When selecting software
DMA request
Inputting DMA request
signal to DMAREQi pin
b7
b0
DMAC control register H (Address 6916)
Software DMA0 request bit
Software DMA1 request bit
Software DMA2 request bit
Software DMA3 request bit
Interrupt request of
each peripheral
function occurs
0 : No request
1 : Requested
When writing “1,” DMA request is generated.
DMA transfer starts
Fig. 13.7.5 Initial setting example for registers relevant to array chain transfer mode (3)
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13.7 Array chain transfer mode
13.7.3 Operation in array chain transfer mode
Figure 13.7.6 shows the operation flowchart of the array chain transfer mode, and Figures 13.7.7 and
13.7.8 show timing diagrams of the array chain transfer mode (burst transfer mode).
For the cycle-steal transfer mode, refer to the following:
• Transfer of transfer parameters in an array state: Figures 13.8.10 and 13.8.11
• All transfers except in an array state and except the last 1-unit transfer of each block: Figure 13.8.12
• Last 1-unit transfer of each block except the last block: Figure 13.8.13
• Last 1-unit transfer of the last block: Figure 13.8.14
The processing performed in the array chain transfer mode consists of an array state and a transfer state.
(1) Array state
In an array state, transfer parameters are read from the transfer parameter memory in a unit of 2
bytes and transferred to registers SARi, DARi, and TCRi and their latches. As shown in Figure
13.7.2, a transfer parameter consists of 4 bytes (24 bits of data + 8 bits of dummy data).
One bus cycle always consumes
3 cycles of φ.
_________
During an array state, the DMAACKi pin outputs “H” level.
For the bus request sampling in an array state, refer to section “13.2.1 Bus access control circuit.”
(2) Transfer state
Data is transferred in a transfer state.
For the bus request sampling in a transfer state, refer to section “13.2.1 Bus access control
circuit.”
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13.7 Array chain transfer mode
First of 1 block ?
On and after
second
First
SARi ← Transfer parameter (Note)
(Transfer source’s transfer start address)
DARi ← Transfer parameter (Note)
(Transfer destination’s transfer start address)
TCRi ← Transfer parameter
(Byte number of transfer data)
TCRi latch ← TCRi latch – 1
DMAi request bit ← 0
(Only in cycle-steal transfer mode)
1-unit transfer
Burst•Edge
Burst·Level·L
Cycle-steal·Requested
(Refer to section “13.4 Operation.”)
Transfer completion
of 1 block ?
Burst·Edge
Burst·Level·L
Cycle-steal·Requested
Y
N
N
DMAi request bit ?
Transfer
completion of all blocks ?
TCRi latch = 0 ?
1
0 Burst·Level·H
Cycle-steal·No request
Y. Completion
1
DMAi request bit ?
0
TC “L” output (Note)
DMAi interrupt request bit ← 1
DMAi enable bit ← 0
Note: When TC pin validity bit is “1”
Burst·Level·H
Cycle-steal·No request
DMAi request bit ← 0
(Only in burst transfer mode (edge sense))
Burst·Edge
: In burst transfer mode (edge sense)
Burst·Level·L
: In burst transfer mode (level sense) with DMAREQi pin = L
Burst·Level·H
: In burst transfer mode (level sense) with DMAREQi pin = H
Cycle-steal·Requested
: In cycle-steal transfer mode with any request of DMA0–3
Cycle-steal·No request
: In cycle-steal transfer mode with no request of DMA0–3
SARi latch indicates the start address of the transfer parameter memory of the next block.
TCRi latch indicates the number of remaining transfer blocks.
Note: The above figure applies when 2-bus cycle transfer is performed.
When data is transferred from memory to I/O in 1-bus cycle transfer, there is no “DARi ← Transfer parameter.”
When data is transferred from I/O to memory in 1-bus cycle transfer, there is no “SARi ← Transfer parameter.”
Fig. 13.7.6 Operation flowchart of array chain transfer mode
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H
H
H
tpH
PG
Transition of
right to use bus
tp M
PCH
PCL
(tp+2)H
(tp+2)M
sa1H
Dummy data
(tp+2) L
Transfer of 1 transfer parameter
sa1L
sa1M
tpL
(tp+4)H
(tp+4)M
(tp+6)H
(tp+6)M
1, 0 (DMAC)
da1H
Dummy data
(tp+6) L
●The Bus request caused by DRAM refresh or Hold is sampled while the bus request sampling signal
is “1,” and is accepted.
sa2
da2
n
tp+20
m
tp+8
tp+16
da1
tp+4
tp+12
sa1
Memory
tp
Array state
Transfer of transfer parameters
da1L
da1M
(tp+4) L
●This example applies on the following conditions:
External data bus width
: 16 bits
Transfer unit
: 16 bits
Transfer method
: 2-bus cycle transfer
Transfer mode
: Burst
Transfer source address direction
: Forward
Transfer destination address direction : Forward
Transfer source Wait
: No
Transfer destination Wait
: No
sa1, sa2, da1, da2
: Transfer parameters (even)
tp
: Start address of first block’s transfer parameter memory
TCR set value
:6
Right to use bus
: CPU → DMAC → CPU
ST1, ST0
TC
DMAACKi
Bus request sampling
A16/D0–A23/D7
A8/D8–A15/D15
A0–A7
R/W
E
ALE
φ1
mL
mM
Second block’s
transfer parameters
First block’s transfer
parameters
(tp+8)H
(tp+8)M
(tp+8) L
sa2+n–1
sa2+n
sa2
sa1+m–1
sa1+m
sa1
(tp+10)H
Memory
mH
(tp+12)H
(tp+12)M
(tp+12)L
sa1L
da1 L
Second block transfer
da2+n–1
da2+n
da2
da1+m–1
da1+m
da1
Memory
Transfer state
Transfer of data
1-unit transfer
sa1H DataL da1H DataL
sa1 M DataH da1 M DataH
First block transfer
(tp+10) M Dummy data
(tp+10) L
Continue to “Figure 13.7.8” on next page.
DMA CONTROLLER
13.7 Array chain transfer mode
Fig. 13.7.7 Timing diagram of array chain transfer mode (burst transfer mode) (1)
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Transfer of data
ST1, ST0
TC
DMAACKi
Transfer state
1, 0 (DMAC)
(tp+12)H
(sa1+m) H
DataL
A16/D0–A23/D7
Bus request sampling
(tp+12)M
(sa1+m) M
(sa1+m) L
DataH
(da1+m–2)L
A8/D8–A15/D15
A0–A7
R/W
E
ALE
φ1
nH
sa2 L
Array state
Dummy data
(tp+22)L
sa2M
(tp+12)L
From proceeding “ Figure 13.7.7”
(tp+24)H
(tp+24)M
(tp+24)L
sa2H
DataL
sa2M DataH
sa2L
(sa2+n) H
(sa2+n) M
(sa2+n) L
1, 1 (CPU)
PG
PCH
PCL
Transition of
right to use bus
Terminate processing
Transfer state
DataL
DataH
(da2+n–2) L
DMA CONTROLLER
13.7 Array chain transfer mode
Fig. 13.7.8 Timing diagram of array chain transfer mode (burst transfer mode) (2)
DMA CONTROLLER
13.7 Array chain transfer mode
[Precautions for array chain transfer mode]
If the following two conditions are satisfied when the transfer unit is 16 bits and the address direction of
transfer source or destination is fixed, the array chain transfer mode can be used:
• The external data bus width = 16 bits or the internal memory is used.
• The transfer start address on the address-direction-fixed side is an even address.
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13.8 Link array chain transfer mode
13.8 Link array chain transfer mode
This mode is used to transfer several blocks of data. According to the information of each block stored in
memory area (Note), several blocks of data are transferred. Transfer parameters can be located in separate
memory locations, in a unit of one block’s parameters. Table 13.8.1 lists the specifications of the link array
chain transfer mode, and Figure 13.8.1 shows the register structures of SARi, DARi, and TCRi in this mode.
Note: Each of the following information is called “transfer parameter”: transfer start addresses of transfer
source and destination, and transfer data’s byte number.
Table 13.8.1 Specifications of link array chain transfer mode
Performance specifications
Item
Transfer parameter memory
Required.
● In 2-bus cycle transfer: 16 bytes per one block
(transfer source’s transfer start address, transfer destination’s transfer
start address, transfer data’s byte number, next transfer parameter
memory’s start address)
● In 1-bus cycle transfer: 12 bytes per one block
(from memory to I/O: transfer source’s transfer start address, transfer
data’s byte number, next transfer parameter memory’s start address)
(from I/O to memory: transfer destination’s transfer start address,
transfer data’s byte number, next transfer parameter memory’s start
address)
Condition of normal termination
SARi latch = 0 and TCRi = 0
Conditions of forced termination
●Falling edge of TC pin’s input from “H” to “L”
___
___
(when the TC pin validity bit = “1”)
●Write “0” to the DMAi enable bit
Interrupt request generation timing At normal termination
SARi latch: Indicates the transfer parameter memory’s start address of
Functions of registers
the next block.
SARi: Indicates the address of the next transfer source.
DARi latch: Not used.
DARi: Indicates the address of the next transfer destination.
TCRi latch: Not used.
TCRi: Indicates the number of remaining bytes being transferred.
TC pin validity bit: Bit 1 at address 6816
___
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DMA CONTROLLER
13.8 Link array chain transfer mode
b23
b16 b15
b8 b7
b0
Source address register 0 (Addresses 1FC216 to 1FC016) (SAR0)
Source address register 1 (Addresses 1FD216 to 1FD016) (SAR1)
Source address register 2 (Addresses 1FE216 to 1FE016) (SAR2)
Source address register 3 (Addresses 1FF216 to 1FF016) (SAR3)
Bit
Functions
23 to 0 [Write]
Set the start address of transfer parameter memory
of block which is first transferred.
These bits can be set to “00000016” to “FFFFFF16.”
[Read]
• After a value is written to this register and until
transfer starts, the read value indicates the written
value (the start address of the transfer parameter
memory of block which is first transferred).
• After transfer starts, the read value indicates the
source address of data which is next transferred.
At reset
RW
Undefined
RW
Note: When writing to this register, write to all 24 bits.
b23
b16 b15
b8 b7
b0
Destination address register 0 (Addresses 1FC616 to 1FC416) (DAR0)
Destination address register 1 (Addresses 1FD616 to 1FD416) (DAR1)
Destination address register 2 (Addresses 1FE616 to 1FE416) (DAR2)
Destination address register 3 (Addresses 1FF616 to 1FF416) (DAR3)
Bit
Functions
23 to 0 Need not to be set.
[Read]
After transfer starts, the read value indicates the
destination address of data which is next transferred.
b23
b16 b15
b8 b7
At reset
RW
Undefined
RW
b0
Transfer counter register 0 (Addresses 1FCA16 to 1FC816) (TCR0)
Transfer counter register 1 (Addresses 1FDA16 to 1FD816) (TCR1)
Transfer counter register 2 (Addresses 1FEA16 to 1FE816) (TCR2)
Transfer counter register 3 (Addresses 1FFA16 to 1FF816) (TCR3)
Bit
Functions
23 to 0 [Write]
Set the dummy data.
These bits can be set to “00000116” to “FFFFFF16.”
[Read]
• After a value is written to this register and until
transfer starts, the read value indicates the written
value (dummy data).
• After transfer starts, the read value indicates the
remaining byte number of the block which is being
transferred.
At reset
RW
Undefined
RW
Note: When writing to this register, write to all 24 bits.
Do not write “00000016” to this register.
Fig. 13.8.1 Register structures of SARi, DARi, and TCRi in link array chain transfer mode
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DMA CONTROLLER
13.8 Link array chain transfer mode
13.8.1 Transfer parameter memory in link array chain transfer mode
The transfer parameters required for each transfer method are described below. These parameters can be
located in separate memory locations, in a unit of one block’s parameters. However, these parameters
must be located starting at an even address.
Figure 13.8.2 shows a transfer parameter memory map in the link array chain transfer mode.
(1) In 2-bus cycle transfer
All of the following transfer parameters are required for each block of data; that is, a transfer
parameter memory consumes 16 bytes for each block.
• Transfer source’s transfer start address (24 bits) + Dummy data (8 bits)
• Transfer destination’s transfer start address (24 bits) + Dummy data (8 bits)
• Transfer data’s byte number (24 bits) + Dummy data (8 bits)
• Start address of next transfer parameter memory (24 bits) (Note) + Dummy data (8 bits)
(2) In 1-bus cycle transfer from memory to I/O
All of the following transfer parameters are required for each block of data; that is, a transfer
parameter memory consumes 12 bytes for each block.
• Transfer source’s transfer start address (24 bits) + Dummy data (8 bits)
• Transfer data’s byte number (24 bits) + Dummy data (8 bits)
• Start address of next transfer parameter memory (24 bits) (Note) + Dummy data (8 bits)
(3) In 1-bus cycle transfer from I/O to memory
All of the following transfer parameters are required for each block of data; that is, a transfer
parameter memory consumes 12 bytes for each block.
• Transfer destination’s transfer start address (24 bits) + Dummy data (8 bits)
• Transfer data’s byte number (24 bits) + Dummy data (8 bits)
• Start address of next transfer parameter memory (24 bits) (Note) + Dummy data (8 bits)
Note: For the last block of data, write “00000016” as the start address of the next transfer parameter
memory.
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DMA CONTROLLER
13.8 Link array chain transfer mode
(1) 2-bus cycle transfer
4 bytes
Transfer source’s transfer start address 1 Transfer parameter address 1
Transfer destination’s transfer start address 1
Transfer data’s byte number 1
Transfer source’s transfer start address 4 Transfer parameter
address 4 (last block)
Transfer destination’s transfer start address 4
Transfer data’s byte number 4
“00000016”
Transfer source’s transfer start address 3 Transfer parameter address 3
Transfer destination’s transfer start address 3
Transfer data’s byte number 3
Next transfer parameter memory’s start address 4
destination’s transfer M
H
start address
Dummy data
L Even address
Transfer data’s
M
byte number
H
Dummy data
L Even address
Next transfer
parameter memory’s M
start address
H
Dummy data
Transfer parameters for 1 block
Next transfer parameter memory’s start address 2
Transfer source’s L Even address
M
transfer start
H
address
Dummy data
L Even address
Transfer
Transfer source’s transfer start address 2 Transfer parameter address 2
Transfer destination’s transfer start address 2
Transfer data’s byte number 2
Next transfer parameter memory’s start address 3
✽ The above figure applies when 4-block transfer is performed.
(2) 1-bus cycle transfer
4 bytes
Transfer source’s transfer start address 1 Transfer parameter address 1
Transfer data’s byte number 1
Transfer source’s transfer start address 3 Transfer parameter
address 3
Transfer data’s byte number 3
Next transfer parameter memory’s start address 4
Transfer source’s transfer start address 2 Transfer parameter address 2
Transfer data’s byte number 2
Next transfer parameter memory’s start address 3
Even address
L
Next transfer
parameter memory’s M
start address
H
Dummy data
Even address
Even address
Transfer parameters for 1 block
Next transfer parameter memory’s start address 2
Transfer source’s L
M
transfer start
H
address
Dummy data
L
Transfer data’s
M
byte number
H
Dummy data
Transfer source’s transfer start address 4 Transfer parameter
address 4 (last block)
Transfer data’s byte number 4
“00000016”
✽ The above applies on the following conditions:
•When data is transferred from memory to I/O
(When transferring from I/O to memory, replace all the above mentioned “Transfer source’s
transfer start address” with “Transfer destination’s transfer start address.”
•4-block transfer
Fig. 13.8.2 Transfer parameter memory map in link array chain transfer mode
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DMA CONTROLLER
13.8 Link array chain transfer mode
13.8.2 Setting of link array chain transfer mode
Figures 13.8.3 through 13.8.5 show an initial setting example for registers relevant to the link array chain
transfer mode.
In addition, when timer A, timer B, UART, or the A-D converter is selected as a DMA request source, the
setting for the peripheral is required. For details of the setting, refer to the chapter of each peripheral
function.
When a DMAi interrupt is used, the setting for enabling the interrupt is also required. For details, refer to
“CHAPTER 7. INTERRUPTS.”
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAAA
AAAAAAAAAAAAA
AAAAAAAAAAAAA
AAAAAAAAAAAAA
AAAAAAAAAAAAA
When external DMA source is selected
When internal DMA source is selected
Setting port P9 direction register
b7
b0
Port P9 direction register (Address 1516)
DMAREQ0 pin
DMAREQ1 pin
DMAREQ2 pin
DMAREQ3 pin
Clear the corresponding bit to “0.”
Setting interrupt priority level
b7
b0
DMAi interrupt control register (i = 0 to 3)
(Addresses 6C16 to 6F16)
Interrupt priority level select bits
When using interrupts, set these bits to one of
levels 1 to 7.
When disabling interrupts, set these bits to
level 0.
Continue to “Figure 13.8.4” on next page.
Fig. 13.8.3 Initial setting example for registers relevant to link array chain transfer mode (1)
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DMA CONTROLLER
13.8 Link array chain transfer mode
From preceding “Figure 13.8.3”
Selection of transfer mode and each function
b7
b0
0
DMA0 mode register L (Address 1FCC16)
DMA1 mode register L (Address 1FDC16)
DMA2 mode register L (Address 1FEC16)
DMA3 mode register L (Address 1FFC16)
b7
b0
Number-of-unit-transfer-bits select bit
0 : 16 bits
1 : 8 bits
DMA request source select bits
0 0 0 0 : Do not select.
0 0 0 1 : External source (DMAREQi)
0 0 1 0 : Software DMA source
0 0 1 1 : Timer A0
0 1 0 0 : Timer A1
0 1 0 1 : Timer A2
0 1 1 0 : Timer A3
0 1 1 1 : Timer A4
Transfer method select bit
0 : 2-bus cycle transfer
1 : 1-bus cycle transfer
Transfer mode select bit
0 : Burst transfer mode
1 : Cycle-steal transfer mode
Transfer destination address direction select bits
0 0 : Fixed
0 1 : Forward
1 0 : Backward
1 1 : Do not select.
b0
1 1
0 0
1 0 0 0 : Timer B0
1 0 0 1 : Timer B1
1 0 1 0 : Timer B2
1 0 1 1 : UART0 receive
1 1 0 0 : UART0 transmit
1 1 0 1 : UART1 receive
1 1 1 0 : UART1 transmit
1 1 1 1 : A-D conversion
Edge sense/Level sense select bit (Note)
0 : Edge sense
1 : Level sense
Transfer source address direction select bits
0 0 : Fixed
0 1 : Forward
1 0 : Backward
1 1 : Do not select.
b7
DMA0 control register (Address 1FCE16)
DMA1 control register (Address 1FDE16)
DMA2 control register (Address 1FEE16)
DMA3 control register (Address 1FFE16)
DMAACKi validity bit
0 : Invalid
1 : Valid
Note: When an external source (DMAREQi)
is selected or when the cycle steal
transfer mode is selected, set this bit
to “0.”
DMA0 mode register H (Address 1FCD16)
DMA1 mode register H (Address 1FDD16)
DMA2 mode register H (Address 1FED16)
DMA3 mode register H (Address 1FFD16)
Continue to “Figure 13.8.5” on next page.
Transfer direction select bit (Used in 1-bus cycle transfer)
0 : From memory to I/O
1 : From I/O to memory
I/O connection select bit (Valid in 1-bus cycle transfer)
0 : Data bus D0–D7 or D0–D15
1 : Data bus D8–D15
Transfer source wait bit (Valid in DMA transfer)
0 : Wait
1 : No wait
Transfer destination wait bit (Valid in DMA transfer)
0 : Wait
1 : No wait
Selection of link array chain transfer mode
(b23)
b7
(b16)(b15)
b0 b7
(b8)
b0 b7
b0
Source address register 0 (Addresses 1FC216 to 1FC016) (SAR0)
Source address register 1 (Addresses 1FD216 to 1FD016) (SAR1)
Source address register 2 (Addresses 1FE216 to 1FE016) (SAR2)
Source address register 3 (Addresses 1FF216 to 1FF016) (SAR3)
Set the start address of transfer parameter memory
of block which is first transferred.
These bits can be set to “00000016” to “FFFFFF16.”
(b23)
b7
(b16)(b15)
b0 b7
(b8)
b0 b7
b0
Transfer counter register 0 (Addresses 1FCA16 to 1FC816) (TCR0)
Transfer counter register 1 (Addresses 1FDA16 to 1FD816) (TCR1)
Transfer counter register 2 (Addresses 1FEA16 to 1FE816) (TCR2)
Transfer counter register 3 (Addresses 1FFA16 to 1FF816) (TCR3)
Set the dummy data.
These bits can be set to “00000116” to “FFFFFF16.”
Notes 1: When writing to these registers,
write to all 24 bits.
2: Do not write “00000016” to TCRi.
Fig. 13.8.4 Initial setting example for registers relevant to link array chain transfer mode (2)
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DMA CONTROLLER
13.8 Link array chain transfer mode
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAA
AAAAAAAAAAA
AAAA
AAAAAAAAAAAAAAAA
AAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAA
AAA
AAA
From preceding “Figure 13.8.4”
Selection of priority level and TC pin, and setting DMAi request bit to “0”
b7
b0
0 0 0 0
DMAC control register L (Address 6816)
Priority select bit
0 : Fixed
1 : Rotating
TC pin validity bit
0 : Invalid
(P103 pin functions as a programmable I/O port.)
1 : Valid
(P103 pin functions as TC pin.)
DMA0 request bit
DMA1 request bit
DMA2 request bit
DMA3 request bit
b7
0 : No request
b0
DMAC control register H (Address 6916)
Software DMAi request bit
(Valid in software DMA source selected)
Bit 0 : Channel 0
Bit 1 : Channel 1
Bit 2 : Channel 2
Bit 3 : Channel 3
DMA0 enable bit
DMA1 enable bit
DMA2 enable bit
DMA3 enable bit
When selecting external
DMA source
0 : Disabled
1 : Enabled
When selecting internal DMA
source except software
When selecting internal
DMA source
When selecting software
DMA request
Inputting DMA request
signal to DMAREQi pin
b7
b0
DMAC control register H (Address 6916)
Software DMA0 request bit
Software DMA1 request bit
Software DMA2 request bit
Software DMA3 request bit
Interrupt request of
each peripheral
function occurs
0 : No request
1 : Requested
When writing “1,” DMA request is generated.
DMA transfer starts
Fig. 13.8.5 Initial setting example for registers relevant to link array chain transfer mode (3)
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DMA CONTROLLER
13.8 Link array chain transfer mode
13.8.3 Operation in link array chain transfer mode
Figure 13.8.6 shows the operation flowchart of the link array chain transfer mode, and Figures 13.8.7 and
13.8.8 show timing diagrams of the link array chain transfer mode (burst transfer mode). In addition, Figure
13.8.9 shows the conditions necessary for timings shown in Figures 13.8.7, 13.8.8, and 13.8.10 through
13.8.14.
For the cycle-steal transfer mode, refer to the following:
• Transfer of transfer parameters in an array state: Figures 13.8.10 and 13.8.11
• All transfers except for that in an array state and except for the last 1-unit transfer of each block: Figure
13.8.12
• Last 1-unit transfer of each block except for the last block: Figure 13.8.13
• Last 1-unit transfer of the last block: Figure 13.8.14
The processing performed in the link array chain transfer mode consists of an array state and a transfer
state.
(1) Array state
In an array state, transfer parameters are read from the transfer parameter memory in a unit of 2
bytes and transferred to registers SARi, DARi, and TCRi and their latches. As shown in Figure
13.8.2, a transfer parameter consists of 4 bytes (24 bits of data + 8 bits of dummy data).
One bus cycle always consumes 3 cycles of φ .
_________
During an array state, the DMAACKi pin outputs “H” level.
For the bus request sampling in an array state, refer to section “13.2.1 Bus access control circuit.”
(2) Transfer state
Data is transferred in a transfer state.
For the bus request sampling in a transfer state, refer to section “13.2.1 Bus access control
circuit.”
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DMA CONTROLLER
13.8 Link array chain transfer mode
First of each block ?
On and after
second
First
SARi ← Transfer parameter (Note)
(Transfer source’s transfer start address)
DARi ← Transfer parameter (Note)
(Transfer destination’s transfer start address)
TCRi ← Transfer parameter
(Byte number of transfer data)
SARi latch ← Transfer parameter (Start address of
next transfer parameter memory)
DMAi request bit ← 0
(Only in cycle-steal transfer mode)
1-unit transfer
Burst·Edge
Burst·Level·L
Cycle-steal·Requested
(Refer to section “13.4 Operation.”)
Transfer completion
of 1 block ?
Burst·Edge
Burst·Level·L
Cycle-steal·Requested
N
Y
N
DMAi request bit ?
Transfer
completion of all blocks ?
SARi latch = 0 ?
1
0 Burst·Level·H
Cycle-steal·No request
Y. Completion
1
DMAi request bit ?
0
TC “L” output (Note)
DMAi interrupt request bit ← 1
DMAi enable bit ← 0
Note: When TC pin validity bit is “1”
Burst·Level·H
Cycle-steal·No request
DMAi request bit ← 0
(Only in burst transfer mode (edge sense))
Burst·Edge
: In burst transfer mode (edge sense)
Burst·Level·L
: In burst transfer mode (level sense) with DMAREQi pin’s input level = L
Burst·Level·H
: In burst transfer mode (level sense) with DMAREQi pin’s input level = H
Cycle-steal·Requested
: In cycle-steal transfer mode with any request of DMA0–3
Cycle-steal·No request
: In cycle-steal transfer mode with no request of DMA0–3
SARi latch indicates the start address of the transfer parameter memory of the next block.
Note: The above figure applies when 2-bus cycle transfer is performed.
When data is transferred from memory to I/O in 1-bus cycle transfer, there is no “DARi← Transfer parameter.”
When data is transferred from I/O to memory in 1-bus cycle transfer, there is no “SARi← Transfer parameter.”
Fig. 13.8.6 Operation flowchart of link array chain transfer mode
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ST1, ST0
TC
DMAACKi
Transition of
right to use bus
PG
A16/D0–A23/D7
H
tp1H
PCH
A8/D8–A15/D15
Bus request sampling
tp1M
PC L
H
H
A0–A7
R/W
E
ALE
φ1
(tp1+2)H
sa1L
sa1H
Dummy data
(tp1+2) L
(tp1+4)H
(tp1+4)M
(tp1+6)M
(tp1+6)H
da1M
da1L
(tp1+4) L
(tp1+8)H
da1 H
(tp1+10)M
(tp1+10)H
mL
Array state
(tp1+12)M
(tp1+12)H
mH
tp2L
tp2M
(tp1+12) L
Dummy data
(tp1+10) L
mM
(tp1+8) L
Transfer of transfer parameters
1, 0 (DMAC)
(tp1+8)M
Dummy data
(tp1+6) L
●The Bus request caused by DRAM refresh or Hold is sampled while the bus request sampling signal is “1,” and is accepted.
Transfer of 1 transfer parameter
(tp1+2)M
sa1 M
tp1L
(tp1+14)H
(tp1+14)M
tp2H
Dummy data
(tp1+14) L
Continue to “Figure 13.8.8.”
DMA CONTROLLER
13.8 Link array chain transfer mode
Fig. 13.8.7 Timing diagram of link array chain transfer mode (burst transfer mode) (1)
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ST1, ST0
TC
DMAACKi
Bus request sampling
Array state
DataL
Data H
(da1+m-2) L
Transfer state
Transfer of data
1-unit transfer
sa1 H DataL da1 H
tp2H
A16/D0–A23/D7
DataL
sa1M Data H da1 M Data H
tp2M
da1 L
A8/D8–A15/D15
sa1 L
tp2L
A0–A7
R/W
E
ALE
φ1
From preceding “ Figure 13.8.7”
tp2H
(sa1+m) H
1,0 (DMAC)
tp2M
(sa1+m) M
(sa1+m) L
sa2H
sa2M
tp2L
Array state
0016
Dummy data
(tp2+14) L
0016
0016
0016
sa2 H
DataL
sa2M DataH
sa2 L
Transfer state
DataL
Data H
(da2+n–2) L
1, 1 (CPU)
PG
PCH
PCL
Transition of
right to use bus
Terminate processing
(sa2+n) H
(sa2+n) M
(sa2+n) L
DMA CONTROLLER
13.8 Link array chain transfer mode
Fig. 13.8.8 Timing diagram of link array chain transfer mode (burst transfer mode) (2)
DMA CONTROLLER
13.8 Link array chain transfer mode
Figure 13.8.9 shows the conditions necessary for timings shown in Figures 13.8.7, 13.8.8, and 13.8.10
through 13.8.14.
External data bus width
Transfer unit
Transfer method
Transfer mode
Transfer source address direction
Transfer destination address direction
Transfer source Wait
Transfer destination Wait
sa1, sa2, da1, da2
tp1
Transfer block’s number
Right to use bus
: 16 bits
: 16 bits
: 2-bus cycle transfer
: Burst (“Figure 13.8.7” and “Figure 13.8.8”)
: Cycle-steal (“Figure 13.8.10” through “Figure 13.8.14”)
: Forward
: Forward
: No
: No
: Transfer parameter (even)
: Start address of first block’s transfer parameter memory
:2
: CPU → DMAC → CPU
Memory
Memory
tp1
sa1
tp1+4
da1
tp1+8
m
tp1+12
tp2
tp2
sa2
tp2+4
da2
tp2+8
n
Memory
sa1
da1
First block transfer
First block’s transfer
parameter
sa1+m–1
sa1+m
da1+m–1
da1+m
sa2
da2
Second block transfer
sa2+n–1
sa2+n
da2+n–1
da2+n
Second block’s
transfer parameter
tp2+12 00000016
Fig. 13.8.9 Conditions necessary for timings shown in Figures 13.8.7, 13.8.8, and 13.8.10 through
13.8.14
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Fig. 13.8.10 Timing diagram of cycle-steal transfer mode (1)
7721 Group User’s Manual
Transition of right to
use bus
H
sa1L
sa1M
tp1L
(tp1+2)H
(tp1+2)M
sa1H
da1L
da1 M
1, 0 (DMAC)
(tp1+4)H
(tp1+4)M
(tp1+4)L
(tp1+6)H
(tp1+6)M
Array state
Transfer of transfer parameters
Dummy data
(tp1+2)L
da1H
(tp1+8)H
Dummy data (tp1+8)M
(tp1+6)L
mL
mM
(tp1+8)L
● The above figure is the example of initial term for processing the first block in “Figure 13.8.9.”
● The Bus request caused by DRAM refresh or Hold is sampled while the bus request sampling signal is “1,” and is accepted.
● The Bus request caused by DMA is sampled while the bus request sampling signal (✽1) is “1” in the transition of the right to use bus, and is accepted.
The DMA requests of the other channels are not accepted in an array state.
ST1, ST0
TC
DMAACKi
Bus request sampling
tp1H
PG
A16/D0–A23/D7
✽1
tp1M
PCL
PCH
H
H
A8/D8–A15/D15
A0–A7
R/W
E
ALE
1
Continue to “Figure 13.8.11.”
● Initial term for processing each block in array chain and link array chain transfer modes
The operation from an array state to the first 1-unit transfer is continuously performed by one DMAi request.
DMA CONTROLLER
13.8 Link array chain transfer mode
7721 Group User‘s Manual
H
(tp1+10)H
(tp1+10)M
mH
Dummy data
(tp1+10)L
tp2L
tp2M
Array state
✽2
tp2H
Dummy data
1, 0 (DMAC)
(tp1+14)H
(tp1+14)M
(tp1+14)L
Transfer of transfer parameters
(tp1+12)H
(tp1+12)M
(tp1+12)L
tp2L
tp2M
tp2H
da1L
Data L
da1H
First 1-unit transfer
sa1H
1, 1 (CPU)
✽1
PG
PCH
PCL
Transition of right
to use bus
Data L
sa1M DataH da1 M Data H
sa1L
● The above figure is the example of initial term for processing the first block in “Figure 13.8.9.” When the array chain transfer mode is selected,
there is not the term of ✽2.
● The Bus request caused by DRAM refresh or Hold is sampled while the bus request sampling signal is “1,” and is accepted.
● The Bus request caused by DMA is sampled while the bus request sampling signal (✽1) is “1” in transition of the right to use bus, and is accepted.
The DMA requests of the other channels are not accepted in an array state.
ST1, ST0
TC
DMAACKi
Bus request sampling
A16/D0–A23/D7
A8/D8–A15/D15
A0–A7
R/W
E
ALE
1
From preceding “Figure 13.8.10”
DMA CONTROLLER
13.8 Link array chain transfer mode
Fig. 13.8.11 Timing diagram of cycle-steal transfer mode (2)
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DMA CONTROLLER
13.8 Link array chain transfer mode
● 1-unit transfer
1-unit transfer is performed with a DMAi request on the following conditions:
• Single transfer mode (except for the last 1-unit transfer)
• Repeat transfer mode (except for the last 1-unit transfer of block)
• Array chain transfer mode (except for the first and last 1-unit transfers of each block)
• Link array chain transfer mode (except for the first and last 1-unit transfers of each block)
1
ALE
E
R/W
A0–A7
PCL
A8/D8–A15/D15
PCH
(sa1+2)M
Data H
(da1+2)M
Data H
PCH
A16/D0–A23/D7
PG
(sa1+2)H
DataL
(da1+2)H
DataL
PG
(sa1+2)L
(da1+2)L
PCL
Bus request sampling
DMAACKi
TC
H
ST1, ST0
1, 0 (DMAC)
1, 1 (CPU)
1-unit transfer
Transition of right
to use bus
Transition of right
to use bus
● The above figure is the example of the second 1-unit transfer for processing the first block in “Figure 13.8.9.”
● The Bus request caused by DRAM refresh, Hold, or DMA is sampled while the Bus request sampling signal is
“H,” and is accepted.
Fig. 13.8.12 Timing diagram of cycle-steal transfer mode (3)
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DMA CONTROLLER
13.8 Link array chain transfer mode
● Last transfer of each block
At the last term (except for the last block) for processing of each block in the repeat, array chain,
and link array chain transfer modes, 1-unit transfer is performed with one DMAi request, and the
right to use bus is relinquished after 3 cycles of .
1
ALE
E
R/W
A0–A7
PCL
A8/D8–A15/D15
PCH
(sa1+m-2)M
DataH
A16/D0–A23/D7
PG
(sa1+m-2)H
DataL
(sa1+m–2)L
(da1+m–2)L
(sa1+m)L
PCL
(da1+m-2)M
DataH
(sa1+m)M
PCH
(da1+m-2)H
DataL
(sa1+m)H
PG
Bus request sampling
DMAACKi
TC
H
1, 0 (DMAC)
ST1, ST0
1, 1 (CPU)
1-unit transfer
Transition of right
to use bus
Transition of right
to use bus
● The above figure is the example of the last term for processing the first block in “Figure 13.8.9.”
● The Bus request caused by DRAM refresh, Hold, or DMA is sampled while the bus request sampling signal is “H,” and
is accepted.
Fig. 13.8.13 Timing diagram of cycle-steal transfer mode (4)
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DMA CONTROLLER
13.8 Link array chain transfer mode
● Last transfer of last block
At the last term for processing the last block in the single, array chain, and link array chain
transfer modes, 1-unit transfer and terminate processing are subsequently performed with
one DMAi request.
1
ALE
E
R/W
A0–A7
PCL
A8/D8–A15/D15
PCH
(sa2+n-2) M
DataH
(da2+n-2)M
A16/D0–A23/D7
PG
(sa2+n-2)H
DataL
(da2+n-2)H
(sa2+n-2)L
(sa2+n)L
PCL
DataH
(sa2+n)M
PCH
Data L
(sa2+n)H
PG
(da2+n-2)L
Bus request sampling
DMAACKi
TC
H
1, 0 (DMAC)
ST1, ST0
1-unit transfer
1, 1 (CPU)
Terminate processing
Transition of
right to use bus
Transition of
right to use bus
● The above figure is the example of the last term for processing the second block in “Figure 13.8.9.”
● The Bus request caused by DRAM refresh, Hold, or DMA is sampled while the bus request sampling
signal is “H,” and is accepted.
Fig. 13.8.14 Timing diagram of cycle-steal transfer mode (5)
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DMA CONTROLLER
13.8 Link array chain transfer mode
[Precautions for link array chain transfer mode]
If the following two conditions are satisfied when the transfer unit is 16 bits and the address direction of
transfer source or destination is fixed, the link array chain transfer mode can be used:
• The external data bus width = 16 bits or the internal memory is used.
• The transfer start address on the address-direction-fixed side is an even address.
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DMA CONTROLLER
13.9 DMA transfer time
13.9 DMA transfer time
Calculation of time from the CPU’s relinquishing the right to use bus until its regaining the right under the
following conditions is described with reference to cycles of φ :
• A DMAi request is generated while the CPU holds the right to use bus.
• The above right is returned to the CPU after completion of DMA transfer for one DMA request.
For the time per 1-unit transfer, refer to section “13.4.1 (2) Bus operation in 2-bus cycle transfer” and
section “13.4.2 (2) Bus operation in 1-bus cycle transfer.”
Also, for the time from DMA request generation until the start of the DMA transfer, refer to section “13.3.4
Processing from DMA request until DMA transfer execution”: and for that from issuing instructions for
forced termination until returning the right to use bus to the CPU, refer to section “13.3.5 (2) Forced
termination.”
13.9.1 Cycle-steal transfer mode
(1) 1-unit transfer
In the following cases, 1-unit transfer is performed at one DMAi transfer. (Refer to “Figure 13.8.12.”)
• Single transfer mode: except for the last 1-unit transfer
• Repeat transfer mode: except for the last 1-unit transfer of a block
• Array chain transfer mode: except for the first and last 1-unit transfers of each block
• Link array chain transfer mode: except for the first and last 1-unit transfers of each block
Right to use
bus
CPU
DMAC
Transition
➀
Transfer
➁
CPU
Transition
➂
Fig. 13.9.1 1-unit transfer
➀ Transition of the right to use bus from CPU to DMAC: 1 cycle
➁ DMA transfer per 1-transfer unit:
• In 2-bus cycle transfer···Read cycle + Write cycle
(Add a value which satisfies the read/write conditions. Refer to “Table 13.4.1.”)
• In 1-bus cycle transfer···Refer to “Table 13.4.5.”
➂ Transition of the right to use bus from DMAC to CPU: 1 cycle
[Example]
2-bus cycle transfer, transfer unit =16 bits, external data bus width = 16 bits, and under the following
conditions:
• Transfer source: address direction = forward, start address of data = even, with Wait
• Transfer destination: address direction = backward, start address of data = even, without
Wait
➀ + ➁ + ➂ = 1 + (3 + 4) + 1 = 9 cycles
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DMA CONTROLLER
13.9 DMA transfer time
(2) Last transfer of each block
In the following cases, 1-unit transfer and the processing for 3 cycles are performed sequentially.
(Refer to “Figures 13.8.13 and 13.8.14.”)
• Single transfer mode: the last 1-unit transfer
• Repeat transfer mode: the last 1-unit transfer of a block
• Array chain transfer mode: the last 1-unit transfer of each block (including the last block)
• Link array chain transfer mode: the last 1-unit transfer of each block (including the last block)
Right to use
bus
CPU
DMAC
Transition
➀
Transfer
➁
CPU
TerminationTransition
etc.
➂
➃
Fig. 13.9.2 Last transfer of each block
➀ Transition of the right to use bus from CPU to DMAC: 1 cycle
➁ DMA transfer per 1-unit transfer:
• In 2-bus cycle transfer···Read cycle + Write cycle
(Add a value which satisfies the read/write conditions. Refer to “Table 13.4.1.”)
• In 1-bus cycle transfer···Refer to “Table 13.4.5.”
➂ Terminate processing or the last processing of each block: 3 cycles
➃ Transition of the right to use bus from DMAC to CPU: 1 cycle
[Example]
2-bus cycle transfer, transfer unit =16 bits, external data bus width = 16 bits, and under the following
conditions:
• Transfer source: address direction = forward, start address of data = even, with Wait
• Transfer destination: address direction = backward, start address of data = even, without Wait
➀ + ➁ + ➂ + ➃ = 1 + (3 + 4) + 3 + 1 = 12 cycles
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DMA CONTROLLER
13.9 DMA transfer time
(3) Transfer of array state
In the following cases, the processing in an array state and the first 1-unit transfer are performed
sequentially. (Refer to “Figures 13.8.10 and 13.8.11.”)
• Array chain transfer mode: the first transfer of each block
• Link array chain transfer mode: the first transfer of each block
Right to use
bus
CPU
DMAC
Transition Array state
➁
➀
CPU
Transfer Transition
➂
➃
Fig. 13.9.3 Transfer of array state
➀ Transition of the right to use bus from CPU to DMAC: 1 cycle
➁ Array state:
The number of transfer parameters × the number of reads of a transfer parameter × the number
of bus cycles for a read + 1 cycle (Refer to “Table 13.9.1.”)
➂ DMA transfer per 1-unit transfer:
• In 2-bus cycle transfer···Read cycle + Write cycle
(Add a value which satisfies the read/write conditions. Refer to “Table 13.4.1.”)
• In 1-bus cycle transfer···Refer to “Table 13.4.5.”
➃ Transition of the right to use bus from DMAC to CPU: 1 cycle
[Example]
Link array chain transfer mode, external data bus width = 16 bits, 2-bus cycle transfer, transfer unit
=16 bits, and under the following conditions:
• Transfer source: address direction = forward, start address of data = even, with Wait
• Transfer destination: address direction = backward, start address of data =odd, with Wait
➀ + ➁ + ➂ + ➃ = 1 + 25 + (3 + 4) + 1 = 34 cycles
Table 13.9.1 Time required for processing in array state
Number of transfer
External data
Mode
Transfer method
parameters
bus width
Array chain
transfer mode
16 bits
(Including internal bus)
8 bits
Link array chain
transfer mode
16 bits
(Including internal bus)
8 bits
13-100
Number of reads of
Time required for
a transfer parameter
processing in array state
(Unit: φ cycle)
2-bus cycle transfer
1-bus cycle transfer
2-bus cycle transfer
3
2
2
2
3 × 2 × 3 + 1 = 19
2 × 2 × 3 + 1 = 13
3
4
3 × 4 × 3 + 1 = 37
1-bus cycle transfer
2
4
2 × 4 × 3 + 1 = 25
2-bus cycle transfer
1-bus cycle transfer
4
2
4 × 2 × 3 + 1 = 25
3
2
3 × 2 × 3 + 1 = 19
2-bus cycle transfer
1-bus cycle transfer
4
3
4
4
4 × 4 × 3 + 1 = 49
3 × 4 × 3 + 1 = 37
7721 Group User’s Manual
DMA CONTROLLER
13.9 DMA transfer time
13.9.2 Burst transfer mode
(1) Single transfer mode
Right to use
bus
CPU
DMAC
Transition
➀
Transfer
➁
CPU
TerminationTransition
➂
➃
Fig. 13.9.4 Single transfer mode (burst transfer mode selected)
➀ Transition of the right to use bus from CPU to DMAC: 1 cycle
➁ DMA transfer per an entire batch of data:
• In 2-bus cycle transfer···(Read cycle + Write cycle ❈1) × the number of transfers ❈2
❈1: Add a value which satisfies the read/write conditions. Refer to “Table 13.4.1.”
❈2: When the transfer unit is 16 bits, the number of transfers = the number of transfer
bytes/2
When the transfer unit is 8 bits, the number of transfers = the number of transfer bytes
• In 1-bus cycle transfer···Refer to “Table 13.4.5.”
➂ Terminate processing: 3 cycles
➃ Transition of the right to use bus from DMAC to CPU: 1 cycle
[Example]
External data bus width = 16 bits, 2-bus cycle transfer, transfer unit =16 bits, the number of the
transfer bytes = 10 bytes, and under the following conditions:
• Transfer source: address direction = forward, start address of data = even, with Wait
• Transfer destination: address direction = backward, start address of data = even, without Wait
➀ + ➁ + ➂ + ➃ = 1 + 5 (3 + 4) + (3 + 1) = 40 cycles
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DMA CONTROLLER
13.9 DMA transfer time
(2) Repeat transfer mode
In the repeat transfer mode of burst ___
transfer (edge sense), the method of terminating DMA transfer
is only the forced termination by the TC input. Therefore, the time from ___
the CPU’s relinquishing the
right to use bus until regaining the right depends on the timing of the TC input.
TC input
Right to use
bus
CPU
DMAC
Transition Transfer
➁
➀
Transfer
➂
➁
CPU
➂
Transfer
➃
Transition
➂
➄
1 block
Fig. 13.9.5 Repeat transfer mode (burst transfer mode and edge sense selected)
➀ Transition of the right to use bus from CPU to DMAC: 1 cycle
➁ DMA transfer per 1 block:
• In 2-bus cycle transfer···(Read cycle + Write cycle ❈1) × the number of transfers ❈2
❈1: Add a value which satisfies the read/write conditions. Refer to “Table 13.4.1.”
❈2: When the transfer unit is 16 bits, the number of transfers = the number of transfer
bytes/2
When the transfer unit is 8 bits, the number of transfers = the number of transfer bytes
• In 1-bus cycle transfer···Refer to “Table 13.4.5.”
➂ Terminate processing: 3 cycles
___
➃ DMA transfer of the block at the TC input: above ➁
The number of transfers
is assumed to be up to the DMA transfer of 1-unit transfer which was in
___
progress at the TC input.
➄ Transition of the right to use bus from DMAC to CPU: 1 cycle
[Example]
External data bus width = 16 bits, 2-bus cycle transfer, transfer unit =16 bits, the number of the
transfer bytes = 10 bytes, and under the following conditions:
• Transfer source: address direction = forward, start address of data = even, with Wait
• ___
Transfer destination: address direction = backward, start address of data = even, without Wait
• TC is input when the “m”th byte (m = even) of the “n”th block is in transfer.
➀ + (n – 1) (➁ + ➂) + ➃ + ➄ = 1 + (n – 1){5(3 + 4) + 3} + m/2 + 1 = 38n + m/2 – 36 cycles
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DMA CONTROLLER
13.9 DMA transfer time
(3) Array chain transfer mode and Link array chain transfer mode
Right to use
bus
CPU
DMAC
CPU
Transition Array state Transfer
Array state Transfer Termination Transition
➂
➂
➁
➁
➂
➀
➅
➄
➃
1 block
Fig 13.9.6 Array chain transfer mode and Link array chain transfer mode
➀ Transition of the right to use bus from CPU to DMAC: 1 cycle
➁ Array state:
The number of transfer parameters × the number of reads of a transfer parameter× the number
of bus cycles for a read + 1 cycle (Refer to “Table 13.9.1.”)
➂ DMA transfer per an entire batch of data:
• In 2-bus cycle transfer···(Read cycle + Write cycle ❈1) × the number of transfers ❈2
❈1: Add a value which satisfies the read/write conditions. Refer to “Table 13.4.1.”
❈2: When the transfer unit is 16 bits, the number of transfers = the number of transfer
bytes/2
When the transfer unit is 8 bits, the number of transfers = the number of transfer bytes
• In 1-bus cycle transfer···Refer to “Table 13.4.5.”
➃ Last processing of each block: 3 cycles
➄ Terminate processing: 3 cycles
➅ Transition of the right to use bus from DMAC to CPU: 1 cycle
[Example]
Array chain transfer mode, external data bus width = 16 bits, 2-bus cycle transfer, transfer unit =16
bits, the number of transfer blocks = 3, and under the following conditions:
• Transfer source: address direction = forward, without Wait
• Transfer destination: address direction = backward, without Wait
• First block: transfer source’s data start address = even, transfer destination’s data start address
= even, the number of transfer bytes =10 bytes
• Second block: transfer source’s data start address = even, transfer destination’s data start address
=odd, the number of transfer bytes =12 bytes
• Third block: transfer source’s data start address =odd, transfer destination’s data start address
=odd, the number of transfer bytes =14 bytes
➀+➁+➂+➃+➁+➂+➃+➁+➂+➄+➅
= 1 + 19 + 5(2 + 4) + 3 + 19 + 6(2 + 3) + 3 + 19 + 7(4 + 3) + 3 + 1 = 177 cycles
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DMA CONTROLLER
13.9 DMA transfer time
MEMORANDUM
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CHAPTER 14
DRAM
CONTROLLER
14.1
14.2
14.3
14.4
14.5
Overview
Block description
Setting for DRAMC
DRAMC operation
Precautions for DRAMC
DRAM CONTROLLER
14.1 Overview, 14.2 Block description
14.1 Overview
Table 14.1.1 lists the performance specifications of DRAM controller (hereafter called DRAMC).
Table 14.1.1 Performance specifications of DRAMC
Item
Performance specifications
DRAM area
0 to 15 Mbytes;
programmable in a unit of 1 Mbyte
____
____
Refreshing method
CAS before RAS; dispersive refreshing
Refresh timer
8 bits
10
Multiplexed address pins
14.2 Block description
Figure 14.2.1 shows the block diagram of DRAMC. Registers relevant to DRAMC are described below.
f(XIN)
Refresh request
1/16
Bus Access
controller
f16
RAS and CAS
generating circuit
Refresh timer
1/(n+1)
RAS
CAS
Bits 0–3
DRAM
control register
Address comparator
A20–A23
A0–A20
Address
Address multiplexer
Fig. 14.2.1 Block diagram of DRAMC
14-2
7721 Group User’s Manual
MA0–MA9
DRAM CONTROLLER
14.2 Block description
14.2.1 DRAM control register
Figure 14.2.2 shows the structure of the DRAM control register.
b7
b6
b5
b4
b3
b2
b1
b0
DRAM control register (Address 6416)
Bit
Bit name
Functions
At reset
RW
0 0 0 0 : No DRAM area
0 0 0 1 : F0000016–FFFFFF16 (1 Mbyte)
0 0 1 0 : E0000016–FFFFFF16 (2 Mbytes)
0 0 1 1 : D0000016–FFFFFF16 (3 Mbytes)
0 1 0 0 : C0000016–FFFFFF16 (4 Mbytes)
0 1 0 1 : B0000016–FFFFFF16 (5 Mbytes)
0 1 1 0 : A0000016–FFFFFF16 (6 Mbytes)
0 1 1 1 : 90000016–FFFFFF16 (7 Mbytes)
1 0 0 0 : 80000016–FFFFFF16 (8 Mbytes)
1 0 0 1 : 70000016–FFFFFF16 (9 Mbytes)
1 0 1 0 : 60000016–FFFFFF16 (10 Mbytes)
1 0 1 1 : 50000016–FFFFFF16 (11 Mbytes)
1 1 0 0 : 40000016–FFFFFF16 (12 Mbytes)
1 1 0 1 : 30000016–FFFFFF16 (13 Mbytes)
1 1 1 0 : 20000016–FFFFFF16 (14 Mbytes)
1 1 1 1 : 10000016–FFFFFF16 (15 Mbytes)
0
RW
0
RW
0
RW
0
RW
0
–
0
RW
b3 b2 b1 b0
0
DRAM area select bits
1
2
3
6 to 4
7
Nothing is assigned.
The value is “0” at reading.
DRAM validity bit (Note)
0 : Invalid (P104–P107 pins function
as programmable input ports. A0–
A7 pins function as address
output pins. Refresh timer stops
counting.)
1 : Valid (P104–P107 pins function as
CAS, RAS, MA8, and MA9. A0–A7
function as MA0–MA7. Refresh
timer starts counting.)
Note: Set the refresh timer (address 6616) before setting this bit to “1.”
Fig. 14.2.2 Structure of DRAM control register
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DRAM CONTROLLER
14.2 Block description
(1) DRAM area select bits (bits 0 to 3)
These 4 bits specify a DRAM area of 15 Mbytes maximum in a unit of 1 Mbyte. Figure 14.2.3 shows
setting examples of DRAM areas.
1 Mbyte
00000016
4 Mbytes
00000016
8 Mbytes
00000016
15 Mbytes
00000016
10000016
80000016
Maximum
C0000016
F0000016
FFFFFF16
DRAM area
select bits
(Bits 3–0)
Minimum
FFFFFF16
(00012)
FFFFFF16
(01002)
FFFFFF16
(11112)
(10002)
DRAM area
Fig. 14.2.3 Setting examples of DRAM areas
(2) DRAM validity bit (bit 7)
When this bit is set to “1,” pin functions for DRAM control become valid, and the refresh timer starts
counting. Table 14.2.1 lists the pin functions for DRAM control.
Table 14.2.1 Pin functions for DRAM control
Pins
DRAM
validity bit
Operation
_______
A 0/MA 0
P106/MA8,
P10 4/CAS,
–A 7/MA7
P10 7/MA9
P10 5/RAS
_______
_______
Accessing
DRAM area
MA 0–MA 7
MA8, MA 9
CAS, RAS
DRAM refresh
A 8/D
8–A 15/D 15,
__ _______ _______
___
R/W, E, BLE, BHE
A16/D0–A23/D7,
ST0, ST1
A8/D__8–A
15 /D 15,
_______ ________
A0–A 7
MA8, MA 9
_______
CAS, RAS
R/W, E, BLE, BHE
A16/D0–A23/D7,
A8/D
8–A 15 /D 15
__
_______ ________
___
_______
Other than
ST0, ST1
___
_______
1
_______
A16/D0–A23/D7,
A0–A 7
MA8, MA 9
_______
CAS, RAS
the above
R/W, E, BLE, BHE
A16/D0–A23/D7,
ST0, ST1
([0,0] is
output.)
ST0, ST1
A8/D__8–A
15 /D 15,
_______ ________
___
R/W, E, BLE, BHE
A0–A 7
0
P10 6, P107
P104,P10 5
—
A16/D0–A23/D7,
A8/D
8–A 15 /D 15
___
__
_______ ________
R/W, E, BLE, BHE
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7721 Group User’s Manual
ST0, ST1
DRAM CONTROLLER
14.2 Block description
14.2.2 Refresh timer
The refresh timer is an 8-bit timer with a reload register and is used to generate refresh requests for DRAM
data. Assuming that the set value of the refresh timer = “n,” the refresh timer counts f16 (n + 1) times. Figure
14.2.4 shows the structure of the refresh timer, and the following formula gives the value to be written to
the refresh timer.
n = {m [ µ s] ✕
f(X IN)
} – 1
16
n: a set value of the refresh timer (n = 01 16–FF 16)
m: a refresh interval
Examples of “m”: an average of 15.625 µ s for 512 refresh cycles at 8-ms intervals
an average of 125 µ s for 512 refresh cycles at 64-ms intervals
b7
b0
Refresh timer (Address 6616)
Bit
Functions
7 to 0 These bits can be set to “0116” to “FF16.”
Assuming that the set value = n, this register divides f16 by
(n + 1).
At reset
RW
Undefined
WO
Note: Use the LDM or STA instruction for writing to this register.
Do not set this register to “0016.”
Fig. 14.2.4 Structure of refresh timer
7721 Group User’s Manual
14-5
DRAM CONTROLLER
14.2 Block description
14.2.3 Address comparator
The address comparator examines whether the address to be accessed
is____
within the DRAM area. When
____
this address is within DRAM area, control signals are sent to the RAS and CAS generating circuit and the
address multiplexer.
____
____
14.2.4
RAS and CAS generating circuit
____
____
The RAS signal (a timing signal to latch a row address) and the CAS signal (a timing signal to latch a
column address) are generated by a control signal from the address comparator.
14.2.5 Address multiplexer
Address data is time-shared by the control signal from the address comparator and is output to the MA0–
MA 9 pins. The time-sharing method depends on the external bus width. Table 14.2.2 lists the time-sharing
method for the address at DRAM access. When the 8-bit external bus width is selected, A 0–A 19 are timeshared and are output; when the 16-bit external bus width is selected, A1–A 20 are time-shared and are
output.
Table 14.2.2 Time-sharing method for address at DRAM access
Output signal
Pin name
8-bit external Row address
bus width
Column address
16-bit external Row address
bus width
14-6
Column address
A0/MA0 A1/MA1 A2/MA2 A3/MA3 A4/MA4 A5/MA5 A6/MA6 A7/MA7 P106/MA8 P107/MA9
A0
A1
A2
A3
A4
A5
A6
A7
A16
A18
A8
A9
A10
A11
A12
A13
A14
A15
A17
A19
A16
A1
A2
A3
A4
A5
A6
A7
A18
A20
A8
A9
A10
A11
A12
A13
A14
A15
A17
A19
7721 Group User’s Manual
DRAM CONTROLLER
14.3 Setting for DRAMC
14.3 Setting for DRAMC
Figure 14.3.1 shows an initial setting example for registers relevant to DRAMC.
Division ratio setting for refresh timer
b7
b0
Refresh timer (Address 6616)
Can be set to “0016” to “FF16” (n).
Refresh timer divides f16 by (n+1).
DRAM area setting and DRAM validity selection
b7
1
b0
DRAM control register [Address 6416]
DRAM area select bits
b3 b2 b1 b0
0 0 0 0: No DRAM area
0 0 0 1: Addresses F0000016–FFFFFF16 (1 Mbyte)
0 0 1 0: Addresses E0000016–FFFFFF16 (2 Mbytes)
0 0 1 1: Addresses D0000016–FFFFFF16 (3 Mbytes)
0 1 0 0: Addresses C0000016–FFFFFF16 (4 Mbytes)
0 1 0 1: Addresses B0000016–FFFFFF16 (5 Mbytes)
0 1 1 0: Addresses A0000016–FFFFFF16 (6 Mbytes)
0 1 1 1: Addresses 90000016–FFFFFF16 (7 Mbytes)
1 0 0 0: Addresses 80000016–FFFFFF16 (8 Mbytes)
1 0 0 1: Addresses 70000016–FFFFFF16 (9 Mbytes)
1 0 1 0: Addresses 60000016–FFFFFF16 (10 Mbytes)
1 0 1 1: Addresses 50000016–FFFFFF16 (11 Mbytes)
1 1 0 0: Addresses 40000016–FFFFFF16 (12 Mbytes)
1 1 0 1: Addresses 30000016–FFFFFF16 (13 Mbytes)
1 1 1 0: Addresses 20000016–FFFFFF16 (14 Mbytes)
1 1 1 1: Addresses 10000016–FFFFFF16 (15 Mbytes)
DRAM is valid.
(P104–P107 pins function as CAS,RAS, MA8, and MA9.
A0–A7 function as MA0–MA7 when accessing the DRAM
area. Refresh timer starts counting.)
•During DRAM area access, CAS, RAS, and MA0–MA9 are output.
•Each time an underflow of the refresh timer occurs, CAS and RAS for refresh are output.
•During refresh, ST0 and ST1 output “L” level.
Fig. 14.3.1 Initial setting example for registers relevant to DRAMC
7721 Group User’s Manual
14-7
DRAM CONTROLLER
14.4 DRAMC operation
14.4 DRAMC operation
14.4.1 Waveform example of DRAM control signals
Figure 14.4.1 shows a waveform example of the DRAM
control signals. When DRAM is accessed, the bus
__
cycle is always with “wait” (the low-level width of E is equivalent to 2 cycles of φ). It is not affected by the
wait bit, the wait bit of the transfer source, and the wait bit of the transfer destination.
(1) Read Cycle
____
____
In the read cycle, the CAS signal falls with a delay of 0.5 cycle of φ after the RAS signal has changed
from “H” to “L.” The address
bus signal ____
changes from “row address” to “column address” within a
____
period from a fall of RAS until a fall of CAS.
Pins A16/D0–A23/D 7 and A8/D8–A15/D15 output addresses and input data in the same way as in reading
external devices other than DRAM.
(2) Write Cycle
____
____
In the write cycle, the CAS signal falls with a delay of 1 cycle of φ after the RAS signal has changed
from “H” to “L.”
The address bus ____
signal changes “row address” to “column address” within a period
____
from a fall of RAS until a fall of CAS.
Pins A16/D0–A23/D7 and A8/D8–A15/D15 output addresses and data in the same way as in writing external
devices other than DRAM.
(3) Refresh Cycle
____
____
In the refresh cycle, the RAS signal falls with a delay of 0.5 cycle of φ after the CAS signal has
changed
from “H” to “L.”
__
R/W is undefined.
One refresh request requires 5 cycle of φ , including the time for passing the right to use buses.
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7721 Group User’s Manual
DRAM CONTROLLER
14.4 DRAMC operation
(a) At reading
E
RAS
CAS
R/W
MA0–MA9
A16/D0–A23/D7
A8/D8–A15/D15
Row address
Column address
Address
Data
Read cycle (1 bus cycle)
(b) At writing
E
RAS
CAS
R/W
MA0–MA9
A16/D0–A23/D7
A8/D8–A15/D15
Row address
Column address
Address
Data
Write cycle (1 bus cycle)
(c) At refresh
E
RAS
CAS
R/W
Undefined
MA0–MA9
Undefined
A16/D0–A23/D7
A8/D8–A15/D15
Floating
Undefined
Transition of right to use bus
Refresh cycle
Undefined
Transition of right to use bus
Fig. 14.4.1 Waveform example of DRAM control signals
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DRAM CONTROLLER
14.4 DRAMC operation
14.4.2 Refresh request
➀ When the DRAM validity bit is set to “1,” the refresh timer starts counting down. The count source is
f 16.
➁ When the contents of the refresh timer reach “0016,” a refresh request occurs. The refresh timer reloads
the contents of address 6616 and continues counting.
➂ Refresh requests are sampled as bus requests (DRAMC) by using the bus access controller.
As soon as a refresh request is acknowledged by sampling, the following ➃ is performed because DRAM
refresh has the highest priority in using the bus.
However, when the CPU or DMAC uses the bus, no bus request is sampled until the CPU or DMAC
releases the bus.
Therefore, in a period from when a refresh request occurs until DRAM refresh is performed, the delay
listed in Table 14.4.1 occurs depending on the refresh request generating timing.
Figures 14.4.2 and 14.4.3 show refresh delay time examples when CPU is operating and during DMA
transfer. For a bus request, refer to “13.2.1 Bus access control circuit.”
➃ When the refresh request is accepted, the right to use the bus is passed to DRAM refresh (1 cycle of
φ ). Both
of the output
levels of ST1 and ST0 are “L.” (The bus status is indicated as [0, 0].)
____
____
➄ The RAS and the CAS signals are output and the DRAM data is refreshed (refresh cycle: 3 cycles of
φ ).
➅ The right to use the bus is passed to the CPU, DRAM or Hold (1 cycle of φ ).
The outputs of ST1 and ST0 change.
Note: In Stop or Wait mode, DRAM refresh is not performed because no refresh request occurs.
Table 14.4.1 Delay time from when refresh request occurs until DRAM refresh is performed
Delay time (unit: φ cycle)
Source of using bus
Maximum (no Wait) Maximum (with Wait)
Minimum
4.5
6.5
1.5
CPU
Transfer (a unit of 1 transfer)
8.5
12.5
DMAC
Transfer (a unit of 1 transfer) + Complete cycle
11.5
15.5
1.5
Array state
6.5
6.5
1.5
1.5
1.5
Hold
Note: The above is applied when Ready is not used. The delay time includes the time for passing the right
to use buses to DRAM refresh (1 cycle).
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7721 Group User’s Manual
DRAM CONTROLLER
14.4 DRAMC operation
E
R/W
Refresh request
Bus request (DRAMC)
Bus request sampling
11 (CPU)
00
ST1,ST0
Delay time (Min.):
1.5 cycles of
Refresh cycle
00 (Refresh)
Delay time (Max.): 6.5 cycles of
Transition of right to use bus Transition of right to use bus
Refresh cycle
Transition of right to use bus Transition of right to use bus
The following are internal signals:
•Refresh request
•Bus request (DRAMC)
•Bus request sampling
Refresh request becomes “0” at an underflow of the refresh timer.
Fig. 14.4.2 Refresh delay time example when CPU is operating
E
R/W
Refresh request
Bus request (DRAMC)
Bus request sampling
10 (DMAC)
ST1,ST0
Delay time (Max.): 12.5 cycles of
00 (Refresh)
Refresh cycle
Transition of right to use bus
The following are internal signals:
•Refresh request
•Bus request (DRAMC)
•Bus request sampling
Refresh request becomes “0” at an underflow of the refresh timer.
Fig. 14.4.3 Refresh delay time example during DMA transfer
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14-11
DRAM CONTROLLER
14.5 Precautions for DRAMC
14.5 Precautions for DRAMC
1. Set the refresh timer (address 6616) to any of 0116–FF 16.
2. When a DRAM refresh request occurs during Hold state, a refresh cycle is activated regardless of the
bus state. It is because a bus request is always sampled during Hold state. Therefore, in order to use
the DRAMC together with the Hold function, an external circuit which is controlled depending on the
states of ST0 and ST1 is required.
3. DRAM refresh is not performed in Stop or Wait mode.
14-12
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CHAPTER 15
WATCHDOG TIMER
15.1 Block description
15.2 Operation description
15.3 Precautions for Watchdog timer
WATCHDOG TIMER
15.1 Block description
Watchdog functions as follows:
● Detects a program runaway.
● Measures a certain time from when oscillation starts owing to terminating Stop mode.
(Refer to section “5.3 Stop mode.”)
15.1 Block description
Figure 15.1.1 shows the block diagram of Watchdog timer.
f32
f512
Watchdog timer
“FFF16”
is set.
Bus request (DRAMC)
CPU wait request
Bus request (Hold)
Bus request (DMAC)
Writing to watchdog timer
register (address 6016)
RESET
STP instruction
2Vcc
detection
circuit
S
Q
R
Fig. 15.1.1 Block diagram of Watchdog timer
15–2
7721 Group User’s Manual
Watchdog timer
interrupt request
WATCHDOG TIMER
15.1 Block description
15.1.1 Watchdog timer
Watchdog timer is a 12-bit counter where the count source which is selected with the watchdog timer
frequency select bit (bit 0 at address 61 16 ) is counted down. A value “FFF 16 ” is automatically set in
Watchdog timer in the cases listed below. An arbitrary value cannot be set to Watchdog timer.
●
●
●
●
When dummy data is written to the watchdog timer register (Refer to “Figure 15.1.2.”)
When the most significant bit of Watchdog timer becomes “0”
When the STP instruction is executed (Refer to section “5.3 Stop mode.”)
At reset
b7
b0
Watchdog timer register (Address 6016)
Bit
7 to 0
Functions
Initializes Watchdog timer.
When dummy data is written to this register, Watchdog
timer’s value is initialized to “FFF16.” (Dummy data: 0016 to FF16)
At reset
RW
Undefined
–
Fig. 15.1.2 Structure of watchdog timer register
15.1.2 Watchdog timer frequency select register
This is used to select a Watchdog timer’s count source. Figure 15.1.3 shows the structure of the watchdog
timer frequency select register.
b7
b6
b5
b4
b3
b2
b1
b0
Watchdog timer frequency select register (Address 6116)
Bit
0
Bit name
Watchdog timer frequency select 0 : f512
1 : f32
bit
7 to 1 Nothing is assigned.
Functions
At reset
RW
0
RW
Undefined
–
Fig. 15.1.3 Structure of watchdog timer frequency select register
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15–3
WATCHDOG TIMER
15.2 Operation description
15.2 Operation description
15.2.1 Basic operation
➀ Watchdog timer starts counting down from “FFF16.”
➁ When the Watchdog timer’s most significant bit becomes “0” (counted 2048 times), a watchdog timer
interrupt request occurs. (Refer to “Table 15.2.1.”)
➂ When the interrupt request occurs at above ➁, a value “FFF16” is set to Watchdog timer.
The watchdog timer interrupt is a non-maskable interrupt. When the watchdog timer interrupt request is
accepted, the processor interrupt priority level (IPL) is set to “1112.”
Table 15.2.1 Occurrence interval of watchdog timer interrupt
request
Watchdog timer
frequency select bit
0
1
15–4
f(X IN) = 25 MHz
Count source Occurrence interval
f 512
41.94 ms
f 32
2.62 ms
7721 Group User’s Manual
WATCHDOG TIMER
15.2 Operation description
Write dummy data to the watchdog timer register (address 6016) before the most significant bit of Watchdog
timer becomes “0.” When Watchdog timer is used to detect a program runaway, a watchdog timer interrupt
request occurs if writing to address 60 16 is not performed owing to a program runaway and the most
significant bit of Watchdog timer becomes “0.” This means that a program runaway has occurred.
In order to reset the microcomputer when a program runaway is detected, write “1” to the software reset
bit (bit 3 at address 5E 16) in the watchdog timer interrupt routine.
Main routine
Watchdog timer register
(Address 6016)
8-bit dummy data
Watchdog timer initialized
Value of watchdog timer :
“FFF16” (Note 1)
Watchdog timer
interrupt request occur
(program runaway detected)
Watchdog timer interrupt routine
Software reset bit
(Address 5E16, b3)
“1” (Note 2)
Reset microcomputer
RTI
Notes 1: Initialize Watchdog timer before the most significant bit of Watchdog timer
becomes “0.” (Write dummy data to address 6016 before a watchdog timer
interrupt request occurs).
2: When a program runaway occurs, values of the data bank register (DT), direct
page register (DPR), etc., may be changed. When “1” is written to the software
reset bit by the addressing mode using DT, DPR, etc., set values to DT and
DPR again.
Fig. 15.2.1 Example of program runaway detection by Watchdog timer
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15–5
WATCHDOG TIMER
15.2 Operation description
15.2.2 Stop period
Watchdog timer stops operation in the following period:
➀ Hold state (Refer to section “3.4 Hold function.”)
➁ During DMAC operation (Refer to “CHAPTER 13. DMA CONTROLLER.”)
➂ During DRAM refresh (Refer to “CHAPTER 14. DRAM CONTROLLER.”)
➃ Stop mode
When states ➀ to ➂ are terminated, Watchdog timer restarts counting from the state before it stops
operation. For Watchdog timer’s operation when state ➃ is terminated, refer to section “15.2.3 Operation
in Stop mode.”
15.2.3 Operation in Stop mode
In Stop mode, Watchdog timer stops operation. Immediately after Stop mode is terminated, Watchdog timer
operates as follows. (Refer to section “5.3 Stop mode.”)
(1) When Stop mode is terminated by hardware reset
Supply of φ and φ CPU starts immediately after Stop mode is terminated, and the microcomputer
performs “operation after reset.” (Refer to “CHAPTER 4. RESET.”) The watchdog timer frequency
select bit becomes “0,” and Watchdog timer starts counting of f512 from “FFF16.”
(2) When Stop mode is terminated by interrupt request occurrence
Immediately after Stop mode is terminated, Watchdog timer starts counting of f32 from “FFF16” regardless
of the contents of watchdog timer frequency select bit (bit 0 at address 6116). Supply of φ and φCPU
starts when Watchdog timer’s most significant bit becomes “0.” (At this time, a watchdog timer
interrupt request does not occur.)
When supply of φ CPU starts, the microcomputer executes the routine of the interrupt which is used to
terminate Stop mode. Watchdog timer restarts counting of the count source (f32 or f 512), which was
counted immediately before executing the STP instruction, from “FFF16.”
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WATCHDOG TIMER
15.3 Precautions for Watchdog timer
15.3 Precautions for Watchdog timer
1. When dummy data is written to address 60 16 with the 16-bit data length, writing to address 61 16 is
simultaneously performed. Accordingly, when the user does not want to change a value of the watchdog
timer frequency select bit (bit 0 at address 6116), write the previous value to the bit simultaneously with
writing to address 60 16.
2. When the STP instruction is executed, Watchdog timer stops. (Refer to section “5.3 Stop mode.”)
3. Watchdog timer stops during DRAM refresh, hold state, and DMAC operation. (For Watchdog timer’s
structure, refer to “Figure 15.1.1.”) Accordingly, when a bus request is changed in the period which is
shorter than 1 cycle of the count source (Note), Watchdog timer’s count may gain. (Refer to “Figure
15.3.1.”)
Note: f32 or f 512, which is selected by the watchdog timer frequency select bit
f32 or f512
Bus request
Count source which is actually
counted by Watchdog timer
In case the bus request is
changed in a period which is
shorter than 1 cycle of f32 or f512
Fig. 15.3.1 Count source for Watchdog timer
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WATCHDOG TIMER
15.3 Precautions for Watchdog timer
MEMORANDUM
15–8
7721 Group User’s Manual
CHAPTER 16
APPLICATION
16.1 Memory connection
16.2 Examples of using DMA controller
16.3 Comparison of sample program
execution rate
APPLICATION
16.1 Memory connection
This chapter describes application. Application shown here is just examples. The user shall modify them
according to the actual application and test them.
16.1 Memory connection
This section shows examples for memory and I/O connection. Refer to “CHAPTER 3. CONNECTION WITH
EXTERNAL DEVICES” for details about the functions and operations of used pins when connecting a
memory or I/O. Refer to section “Appendix 11. Electrical characteristics” for timing requirements of the
microcomputer.
16.1.1 Memory connection model
For the M37721, the level of the external data bus width select signal makes it possible to select the
memory connection model from the four models listed in Table 16.1.1.
(1) Minimum model
This is a connection model of which external data bus width is 8 bits and access space is expanded
up to 64 Kbytes. It is unnecessary to connect the address latch externally, so this model gives priority
to cost and is most suitable when connecting the memory of which data bus width is 8 bits.
(2) Medium model A
This is a connection model of which external data bus width is 8 bits and access space is expanded
up to 16 Mbytes. In this model, the high-order 8 bits of the external address bus (A 16 to A 23) are
multiplexed with the external data bus. Therefore, an n-bit (n ≤ 8) address latch is required for
latching n bits of the address in A 16 to A 23 .
(3) Medium model B
This is a connection model of which external data bus width is 16 bits and access space is expanded
up to 64 Kbytes. This model gives priority to rate performance. In this model, the middle-order 8 bits
of the external address bus (A8 to A 15) are multiplexed with the external data bus. Therefore, an 8bit address latch is required for latching A8 to A15.
(4) Maximum model
This is a connection model of which external data bus width is 16 bits and access space is expanded
up to 16 Mbytes. In this model, the high- and middle-order 16 bits of the external address bus (A8
to A 23) are multiplexed with the external data bus. Therefore, an 8-bit address latch for latching A8
to A 15 and an n-bit (n ≤ 8) address latch for latching n bits of A16 to A 23 are required.
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7721 Group User’s Manual
APPLICATION
16.1 Memory connection
Table 16.1.1 Memory connection model
Access space
External data
bus width
Maximum 64 Kbytes
Maximum 16 Mbytes
M37721
M37721
BYTE
16
BYTE
A0–A15
A0–A7
8-bit width;
A8–A15
BYTE = “H”
8
Memory connection model
Minimum model
16-bit width;
BYTE = “L”
A16/D0–A23/D7
ALE
Latch n
D Q
E
8
D0–D7
Memory connection model
M37721
16
A0–A7
A8/D8–A15/D15
A0–A15+n
ALE
D0–D7
M37721
BYTE
A8–A15
A16/D0–A23/D7
A16/D0–A23/D7
16+n
A0–A7
Latch 8
BYTE
A0–A15
DQ
E
16
Medium model A
16+n
A0–A7
A8/D8–A15/D15
D Q
E
A16/D0–A23/D7
D Q
E
ALE
A0–A15+n
Latch 8
n
Latch
D0–D15
16
D0–D15
BHE
BHE
BLE
BLE
Memory connection model
Medium model B
Memory connection model
Maximum model
Notes 1: Refer to “CHAPTER 3. CONNECTION WITH EXTERNAL DEVICES” for details about the functions and
operations of used pins when connecting a memory. Refer to section “Appendix 11. Electrical characteristics”
for timing requirements.
2: Because the address bus can be expanded up to 24 bits when connecting a memory, strengthen the
M37721’s Vss and Vcc lines on the system. (Refer to section “Appendix 8. Countermeasure against noise.”)
7721 Group User’s Manual
16–3
APPLICATION
16.1 Memory connection
16.1.2 How to calculate timing
Timings at which data is read or written when connecting a memory and precautions when connecting a
memory are described below.
For timing requirements of the memory and detailed account except limits described below, also refer to
the memory’s Data book etc. When using bus buffers, various logical circuits, etc., be sure to consider the
propagation delay time etc.
(1) Timing for reading data
When reading data, the external data bus is placed in a floating state, and data _is read from the
external memory. This floating state is maintained after the
falling edge of the E signal until an
_
interval of tpzx(E–DLZ/DHZ) has passed after the rising edge of the E signal. Satisfy tsu(DL/DH-E) when inputting
data read from the external memory.
The following are described below:
•Timing for reading data from the flash memory, SRAM, and DRAM
to be satisfied
•Calculation formulas for the external
memory’s access time, which are for tsu(DL/DH-E)
___
__
The memory output enable signal (OE) is assumed to be generated from the E signal.
● Timing for reading data from flash memory and SRAM
tw(EL)
E
External memory
output enable signal
(Read signal)
External memory
chip select signal
OE
CE, S
Address output and Data input
A8/D8–A15/D15 ✽1
tpzx(E-DLZ/DHZ)
ta(OE)
Address
Address
A16/D0–A23/D7
ta(AD), tsu(A-DL/DH)
ta(CE), ta(S)
ten(OE)
✽2
tDF, tdis(OE) ✽3
ten(CE), ten(S)
External memory
data output
Data
tsu(DL/DH-E)
: Specifications of the M37721
(The others are specifications of
external memory.)
✽1: This applies when the external data bus has a width of 16 bits (BYTE = “L”).
✽2: If data is output from the external memory before the falling edge of E, there is a possibility that the tail of
address collides with the head of data. → Refer to section “(3) Precautions on memory connection.”
✽3: If one of the external memory’s specifications is greater than tpzx(E-DLZ/DHZ) , there is a possibility that the tail
of data collides wi th the head of address . → Refer to section “(3) Precautions on memory connection.”
Note: tsu(A-DL/DH) : tsu(A-DL) or tsu(A-DH)
tpzx(E-DLZ/DHZ) : tpzx(E-DLZ) or tpzx(E-DHZ)
tsu(DL/DH-E) : tsu(DL-E) or tsu(DH-E)
Fig. 16.1.1 Timing for reading data from flash memory and SRAM
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APPLICATION
16.1 Memory connection
Address access time : t a(AD) ≤ t su(A-DL/DH) – address latch delay time ✽1
OE access time : t a(OE) ≤ t w(EL) – t su(DL/DH-E)
Chip select access time : t a(S) ≤ t su(A-DL/DH) – (address decode time ✽2 + address latch delay time ✽1)
___
Address latch delay time✽1 : Delay time required when latching address (Unnecessary in minimum
model)
✽2
Address decode time : Time required for validating chip select signal after decoding address
Table 16.1.2 lists the calculation formulas and values for each parameter in Figure 16.1.1. Figure
16.1.2 shows the relationship between tsu(A-DL/DH) and f(X IN).
Table 16.1.2 Calculation formulas and Values for each
parameter in Figure 16.1.1 (unit : ns)
Calculation formulas and Values
Wait
No Wait
tw(EL)
4 ✕ 10 9
2 ✕ 10 9
–25
–25
f(X IN)
f(X IN)
tsu(A-DL)
5 ✕ 10 9
3 ✕ 10 9
–70
–70
tsu(A-DH)
f(X IN)
f(X IN)
tpzx(E-DLZ)
1 ✕ 10 9
–20
tpzx(E-DHZ)
f(X IN)
tsu(DL-E)
30
tsu(DH-E)
Data setup time with address stabilized
tsu(A–DL/DH)
[ns]
700
644
555
600
Wait
No Wait
485
500
430
384
400 358
346
314
305
300
263
230
202
200
100
287
263
242
224 207
193 180
180
168 157
160 144
147 138
130 117
130
106 96
87 80 72
66 60 55
50
0
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
[MHz]
External clock input frequency f(XIN)
Fig. 16.1.2 Relationship between t su(A-DL/DH) and f(X IN)
7721 Group User’s Manual
16–5
APPLICATION
16.1 Memory connection
● Timing for reading data from DRAM
tw(EL)
DRAM output enable signal E
(Read signal) OE
RAS
td(E-RASL)
CAS
Address output
(MA0–MA7)
td(E-CASL)
Row address
Column address
tOEA
td(E-CA)
tAA
tpzx(E–DLZ/DHZ)
tRAC
Address output and Data I/O
A8/D8–A15/D15
✽1
A16/D0–A23/D7
Address
tCLZ
tOEZ ✽2
tCAC
DRAM data output
Data
✽1 This applies when the external data bus has a width of 16 bits (BYTE = “L”).
✽2 If one of DRAM’s specifications is greater than tpzx(E–DLZ/DHZ) , there is a possibility that
the tail of data collides with the head of address. → Refer to section “(3) Precautions on
memory connection.”
Note: tpzx(E-DLZ/DHZ) : tpzx(E-DLZ) or tpzx(E-DHZ)
tsu(DL/DH-E) : tsu(DL-E) or tsu(DH-E)
tsu(DL/DH-E)
: Specifications of the M37721
(The others are specifications of DRAM.)
Fig. 16.1.3 Timing for reading data from DRAM
____
CAS access time : t CAC ≤ t w(EL) – t d(E-CASL) – t su(DL/DH-E)
RAS access time : t RAC ≤ t w(EL) – t d(E-RASL) – t su(DL/DH-E)
Column address access time : tAA ≤ t w(EL) – td(E-CA) – tsu(DL/DH-E)
___
OE access time : t OEA ≤ t w(EL) – t su(DL/DH-E)
____
Table 16.1.3 lists the calculation formula and value for each parameter in Figure 16.1.3. Figure
16.1.4 shows the relationship between t CAC, tRAC , tAA and f(X IN).
16–6
7721 Group User’s Manual
APPLICATION
16.1 Memory connection
Table 16.1.3 Calculation formula and Value for each
parameter in Figure 16.1.3 (unit : ns)
Calculation formula and Value
4 ✕ 10 9
– 25
f(X IN)
tw(EL)
td(E-RASL)
30
td(E-CASL)
1 ✕ 10 9
+ 37.5
f(X IN)
1 ✕ 10 9
+ 25
f(XIN)
1 ✕ 10 9
– 20
f(X IN)
td(E-CA)
tpzx(E-DLZ)
tpzx(E-DHZ)
tsu(DL-E)
30
tsu(DH-E)
Note: When accessing DRAM, Wait is always inserted
regardless of the contents of the Wait bit,
source’s Wait bit, and destination’s Wait bit.
[ns]
500 486
450
451
415
380
324
278
222
243
240.5
200
248
280
282.5
250
200
165
187
179.5
150
181
213
207.5
157.5
165
137.5
100
146
121.5
107.5
150
115
130
94.5
50
137
102
83.5 73.5
0
7
8
9
: tCAC
CAS access time
315
300 335.5
Access time
Column address access time : tAA
359
350
: tRAC
RAS access time
400
10
11
12
13
14
15
16
17
18
125
90
115
105
96
88
70
81
61
53
46
23
24
80
75
40
64.5 57.5
49.5 43.5
37.5 32.5 27.5
19
20
21
22
25
[MHz]
External clock input frequency f(XIN)
Fig. 16.1.4 Relationship between t CAC, tRAC, t AA and f(X IN)
7721 Group User’s Manual
16–7
APPLICATION
16.1 Memory connection
(2) Timing for writing data
When writing data, _the output data is stabilized when an interval of td(E-DLQ/DHQ) has passed after the
falling edge of the E signal. This data
is continuously output until when an interval of th(E-DLQ/DHQ) has
_
passed after the rising edge of the E signal.
Data to be written to an external memory must satisfy the data set up time (t su(D)) (for DRAM, the data
hold time (tDH)) of the external memory.
The following are described below:
•Timing for writing data to flash memory, SRAM, and DRAM
•Calculation formulas which are for tsu(D) and t DH to be satisfied
● Timing for writing data to flash memory and SRAM
tw(EL)
E
External memory
write signal
External memory
chip select signals
W
CE, S
td(E–DLQ/DHQ)
th(E-DLQ/DHQ)
Address output and Data input
A8/D8–A15/D15
✽
Data
Address
A16/D0–A23/D7
tsu(D)
Address
th(D)
: Specifications of the M37721
(The others are specifications of external memory.)
✽ This applies when the external data bus has a width of 16 bits (BYTE = “L”).
Fig. 16.1.5 Timing for writing data to flash memory and SRAM
Data setup time : tsu(D) ≤ tw(EL) – t d(E-DLQ/DHQ)
Table 16.1.4 lists the calculation formulas and values for each parameter in Figure 16.1.5, Figure
16.1.6 shows the relationship between t su(D) and f(X IN).
16–8
7721 Group User’s Manual
APPLICATION
16.1 Memory connection
Table 16.1.4 Calculation formulas and Values for each
parameter in Figure 16.1.5 (unit : ns)
Calculation formulas and Values
Wait
No Wait
4 ✕ 10 9
2 ✕ 10 9
–25
–25
f(X IN)
f(X IN)
tw(EL)
td(E-DLQ)
td(E-DHQ)
th(E-DLQ)
th(E-DHQ)
35
1 ✕ 10 9
–22
f(X IN)
[ns]
600
506
Data setup time
tsu(D)
500
435
Wait
No Wait
379
400
335
298
300
268
220
242
220
185
200
157
135
116 101
100
88
77
201
185 170
157 145
135 125
116 108 101
68 60 52
46 40 35 30
25 21 18
95
15
25
15
0
7
8
9
10
11
12
13
14
16
17
18
19
20
External clock input frequency f(XIN)
21
22
23
24
[MHz]
Fig. 16.1.6 Relationship between t su(D) and f(XIN)
7721 Group User’s Manual
16–9
APPLICATION
16.1 Memory connection
● Timing for writing data to DRAM
tw(EL)
E
RAS
CAS
td(E-CASL)
DRAM write signal W
Address output
(MA0–MA7)
Row address
Column address
td(E-DLQ/DHQ)
Address output and Data I/O
✽
A8/D8–A15/D15
A16/D0–A23/D7
Address
Data
tDH
✽ This applies when the external data bus has a width of 16 bits (BYTE = “L”).
th(E-DLQ/DHQ)
: Specifications of the M37721
(The others are specifications of DRAM.)
Fig. 16.1.7 Timing for writing data to DRAM
Data hold time : tDH ≤ t w(EL) – t d(E-CASL) + t h(E-DLQ/DHQ)
Table 16.1.5 lists the calculation formula and value for each parameter in Figure 16.1.7. Figure
16.1.8 shows the relationship between tDH and f(X IN).
16–10
7721 Group User’s Manual
APPLICATION
16.1 Memory connection
Table 16.1.5 Calculation formula and value for each
parameter in Figure 16.1.7 (unit : ns)
Calculation formula and Value
4 ✕ 10 9
–25
f(XIN)
tw(EL)
td(E-CASL)
80 to 115
td(E-DLQ)
35
td(E-DHQ)
th(E-DLQ)
1 ✕ 10 9
–22
th(E-DHQ)
f(X IN)
Note: When accessing DRAM, Wait is always inserted
regardless of the contents of the Wait bit,
source’s Wait bit, and destination’s Wait bit.
[ns]
500
486.5
415.5
400
359.5
Data hold time tDH
315.5
278.5
248.5
300
222.5
200.5
200
181.5
165.5
150.5
137.5
125.5 115.5
100
105.5 96.5
88.5 81.5
75.5
0
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
[MHz]
External clock input frequency
f(XIN)
Fig. 16.1.8 Relationship between t DH and f(X IN)
7721 Group User’s Manual
16–11
APPLICATION
16.1 Memory connection
(3) Precautions on memory connection
As described in ➀ to ➂ below, if specifications of the external memory do not match those of the
M37721, some considerations must be incorporated into circuit design:
➀ When using an external memory that requires a long access time
_
➁ When data is output from an external memory before falling edge of the E signal
➂ When
using an external memory that outputs data for more than t pzx(E-DLZ/DHZ) after rising edge of
_
the E signal
➀ When using external memory that requires long access time
If the M37721’s tsu(DL/DH-E) cannot be satisfied because the external memory requires a long access
time, try to carry out the following:
● Lower f(X IN).
● Select “software Wait is inserted.” (Refer to section “3.2 Software Wait.”)
● Use Ready function. (Refer to section “3.3 Ready function.”)
Figure 16.1.9 shows an example of using Ready function (no software Wait). Figure 16.1.10 shows
an example of using Ready function (software Wait).
Ready function is valid___
for the internal areas, so that the circuits in Figures 16.1.9 and 16.1.10 ___
use
the chip select signal (CS2) to specify areas where Ready function is valid. In these cases, the CS2
signal is externally generated.
16–12
7721 Group User’s Manual
APPLICATION
16.1 Memory connection
M37721
A8–A23
(D0–D15)
✽1
Data bus
✽2
Address
latch
circuit
Address
decode
circuit
CS1
CS2
A0–A7
✽1 to ✽3 : Make sure that the sum of
propagation delay time is within
15 ns.
✽3 to ✽5 : Make sure that the sum of
propagation delay time is within
72 ns.
Address bus
RDY
✽5
AC74
E
✽3
AC32
AC32
D Q
1
1
CK
Validate Ready function
only for areas accessed by
CS2.
AC04 ✽4
Circuit conditions : f(XIN) ≤ 15.7 MHz, no software Wait
td(E-
1)
tc
A
B
Ready request is accepted at A .
Termination request for Ready state is accepted
at B .
1
A , B : Judgement timing of RDY pin’s input
level
1
: E (“L” level) stopped by Ready function
✽ The condition satisfy tsu(RDY– 1) ≥ 55 ns is tc
≥ 63.5 ns. (This applies when AC32’s
propagation delay time is within 8.5 ns.)
Accordingly, when f(XIN) ≤ 15.7 MHz, this
circuit example satisfies tsu(RDY– 1) ≥ 55 ns.
E
CS2
Q
RDY
tsu(RDY-
1)
✽
AC32(tPHL)
Fig. 16.1.9 Example of using Ready function (no software Wait)
7721 Group User’s Manual
16–13
APPLICATION
16.1 Memory connection
M37721
A8–A23
(D0–D15)
Data bus
Address
latch
circuit
✽1 to ✽3 : Make sure that the sum of
propagation delay time is within 25
ns.
CS1
Address
decode
circuit
CS2
A0–A7
Address bus
RDY
AC32
E
✽3
AC32
AC04
1D
CLR
1Q
1CK
Validate Ready function
only for areas accessed by
CS2.
2D 2Q
2CK
✽1
AC04
1
AC74 ✽2
Circuit conditions : f(XIN) ≤ 25 MHz, software Wait
A
B
Ready request is accepted at A .
Termination request for Ready state is accepted at B .
1
A , B : Judgement timing of RDY pin’s input level
1
: E (“L” level) stopped by software Wait
E
: E (“L” level) stopped by Ready function
1Q
2Q
CS2
RDY
AC04 + AC74 + AC32’s
propagation delay time
th(
tsu(RDY-
1-RDY)
1)
Fig. 16.1.10 Example of using Ready function (software Wait)
16–14
7721 Group User’s Manual
APPLICATION
16.1 Memory connection
_
➁ When data is output from external memory before falling edge of E signal
_
Because the external memory outputs data before the falling edge of the E signal, there is a
possibility that the tail of address
collides with
the head of data. In such a case, generate the
__
_
external memory read signal (OE) by using E. (Refer to “Figure 16.1.11.”)
E
External memory
output enable signal
(Read signal)
Address output
d
OE
Address
External memory
data output
Address
Data
ta(OE) Specifications of
ten(OE) external memory
Note: Make sure that d ≥ 0 is satisfied when generating the external
memory read signal (OE).
Fig. 16.1.11 Example of making data output timing delayed
➂_
When using external memory that outputs data for more than tpzx(E-DLZ/DHZ) after rising edge of
E signal
Because
the external memory outputs data for more than t pzx(E-DLZ/DHZ) after the rising edge of the
_
E signal, there is a possibility that the tail of data collides with the head of address. In such a case,
try to carry out the following:
● Cut the tail of data output from the memory by using, for example, a bus buffer.
● Use the Mitsubishi’s memory chips that can be connected without a bus buffer.
Figures 16.1.12 to 16.1.15 show examples of using bus buffers and the timing charts. Table 16.1.6
lists the Mitsubishi’s memory chips that can be connected without a bus buffer. When using one
Accordingly,
of these memory chips, timing parameters tDF and t dis(OE) listed below are guaranteed.
___
no bus buffer is necessary for the system where the external memory’s
read
signal
(OE)
goes high
_
within tpzx(E-DLZ/DHZ)-tDF (or tdis(OE)) [ns] after the rising edge of the E signal.
Table 16.1.6 Mitsubishi’s memory chips that can be connected without bus buffers
Memory
Type
tDF/tdis(OE) (Maximum)
Flash memory
M5M28F101AP, FP, J, VP, RV-85, -10
15 ns
M5M28F102AFP, J, VP-85, -10
SRAM
(Guaranteed as kit.)
M5M5256DP, FP, KP, VP, RV-45LL, -45XL, -55LL, -55XL, (Note)
-70LL, -70XL
M5M5278DP, J-12
6 ns
M5M5278DP, FP, J-15, -15L
M5M5278DP, FP, J-20, -20L
7 ns
8 ns
Note: tDF or t dis(OE) listed above is guaranteed when these memory chips are connected with the M37721.
When the user wants specifications of these memory chips, add a comment “tDF/t dis(OE) = 15 ns,
microcomputer and kit.”
7721 Group User’s Manual
16–15
APPLICATION
16.1 Memory connection
M37721
CNVss
A0–A7
Address bus
AC573
BYTE
D
Q
LE OE
AC573
D
ALE
Q
LE OE
AC245
A8/D8–A15/D15
A
✽2
B
Data bus (odd)
DIR OC
AC245
A
A16/D0–A23/D7
✽2
B
Data bus (even)
DIR OC
✽3
E
AC32
AC04
✽1
RD
R/W
WO
BHE
WE
BLE
AC32
XIN
✽4
XOUT
Circuit condition: Software Wait
25 MHz
✽1: Make sure that the propagation delay time is within 20 ns.
✽2, ✽3: Make sure that the sum of output disable time in ✽2 and propagation delay
time in ✽3 is within 20 ns.
✽4: Make sure that the propagation delay time is within 15 ns.
Fig. 16.1.12 Example of using bus buffers (1)
16–16
7721 Group User’s Manual
APPLICATION
16.1 Memory connection
<When reading>
tw(EL) = 135 (min.)
E
tpzx(E-DLZ/DHZ) = 20 (min.)
A8/D8–A15/D15
A16/D0–A23/D7
A
A
AC32(tPHL)
AC32(tPLH)
OC(AC245), RD
AC245
(tPZH/tPZL)
Data output A from
external memory (AC245)
AC245
(tPHZ/tPLZ)
D
<When writing>
tw(EL) = 135 (min.)
E
td(E-DLQ/DHQ) = 35 (max.)
A8/D8–A15/D15
A16/D0–A23/D7
A
D
A
AC32(tPHL)
AC32(tPLH)
OC(AC245), WO, WE
AC245
(tPHL/tPLH)
Data output B from
external memory (AC245)
AC245
(tPHZ/tPLZ)
D
(Unit : ns)
Fig. 16.1.13 Timing chart for circuit example using bus buffers (1)
7721 Group User’s Manual
16–17
APPLICATION
16.1 Memory connection
M37721
CNVss
A0–A7
Address bus
AC573
BYTE
D
Q
LE OE
AC573
D
ALE
Q
LE OE
AC245
A8/D8–A15/D15
A
✽2
B
Data bus (odd)
DIR OC
AC245
A
A16/D0–A23/D7
✽2
Data bus (even)
B
DIR OC
E
These circuits make the occurrence of the
write signal’s rising edge earlier by 1/2 1,
so that the write hold time is extended.
1D 1Q
2D
1T
2T 2Q
AC04
AC74
1
1
AC04
✽1
RD
R/W
WO
BHE
WE
BLE
AC32
AC32
XIN
XOUT
Circuit condition : Software Wait
25 MHz
✽1: Make sure that the propagation delay time is within 20 ns.
✽2: Make sure that the output disable time is within 20 ns.
Fig. 16.1.14 Example for using bus buffers (2) (connecting with memory requiring long data hold time
for writing)
16–18
7721 Group User’s Manual
APPLICATION
16.1 Memory connection
<When reading>
tw(EL) = 135 (min.)
E, OC (AC245)
tpzx(E-DLZ/DHZ) = 20 (min.)
A8/D8–A15/D15
A16/D0–A23/D7
A
A
AC32(tPHL)
AC32(tPLH)
RD
AC245
(tPHZ/tPLZ)
AC245
(tPZH/tPZL)
Data output A from
external memory (AC245)
D
<When writing>
1
1
tw(EL) = 135(min.)
E, OC (AC245)
1Q (AC74)
AC04(tPLH) + AC74(tPLH)
2Q (AC74)
AC32 ✕ 2(tPLH)
WO, WE
A8/D8–A15/D15
A16/D0–A23/D7
35 (max.)
A
D
AC245
(tPHL/tPLH)
Data output B from
external memory (AC245)
AC245
(tPHZ/tPLZ)
D
Write hold time
(Unit : ns)
Fig. 16.1.15 Timing chart for circuit example using bus buffers (2)
7721 Group User’s Manual
16–19
APPLICATION
16.1 Memory connection
16.1.3 Example of memory connection
Examples of the flash memory, SRAM, and DRAM connection and the timing charts are described as
follows.
(1) Example of flash memory connection (minimum model)
M5M28F101AFP-10
M37721
BYTE
A0–A15
D0–D7
BHE
BLE
Address bus A0–A15
Data bus D0–D7
✽: Make sure that the propagation delay
time is within 25 ns.
A0–A15
D0–D7
Memory map
WE
Open
Open
OE
CE
E
XOUT
25 MHz
AC04
Internal RAM area
1FC016
✽
External ROM area
(M5M28F101AFP)
SFR area
200016
Circuit condition : Software Wait
External ROM area
(M5M28F101AFP)
FFFF16
Fig. 16.1.16 Example of flash memory connection (minimum model)
16–20
SFR area
008016
048016
R/W
XIN
000016
7721 Group User’s Manual
APPLICATION
16.1 Memory connection
<When reading>
tw(EL) = 135 (min.)
E, OE
td(AH-E) = 15 (min.)
A16/D0–A23/D7
tpzx(E-DLZ) = 20 (min.)
A
A
td(R/W-E) = 20 (min.)
RW
th(E-R/W) = 18 (max.)
ta (AD)✽, tsu (A-DL) = 130 (max.)
AC04(tPLH)
AC04(tPHL)
CE
ta(OE)✽
tDF✽ = 15 (max.)
(Guaranteed as kit.)
External ROM
data output
D
ta(CE)✽
tsu(DL-E) ≥ 30
✽ : Specifications of M5M28F101AFP-10
The others are specifications of M37721.
Fig. 16.1.17 Timing chart for flash memory connection example (minimum model)
7721 Group User’s Manual
16–21
APPLICATION
16.1 Memory connection
(2) Example of flash memory and SRAM connection (maximum model)
M37721
Address bus
A1–A7
BYTE
A8–A16
✽2
AC573 ✽1
A8/D8–A15/D15
D
AC139
A18
Q
A17
E
Y0
A
S
Y1
B
S
A0–A14
A1–A15
ALE
D8–D15
D
AC573
A1–A16
M5M28F102AFP
-10
M5M5256DP-70LL
D0–D7
DQ1–DQ8
Q
A0–A15
A1–A15
M5M5256DP-70LL
E
A16/D0–A18/D2
CE
WE
A0–A14
D0–D15
DQ1–DQ8
D0–D15
✽1
OE
W
OE
W
OE
Data bus (odd)
D3–D7
Data bus (even)
AC04✽3
AC32✽4
R/W
E
RD
WE
Memory map
BLE
WO
BHE
XIN
XOUT
000016
008016
AC32✽5
Circuit condition : Software Wait
048016
SFR area
Internal RAM area
External ROM area
(M5M28F102AFP)
1FC016
25 MHz
SFR area
200016
✽1, ✽2: Make sure that the sum of propagation delay time is within 30 ns.
✽3, ✽4: Make sure that the sum of propagation delay time is within 20 ns.
✽5: Make sure that the propagation delay time is within 5 ns.
External ROM area
(M5M28F102AFP)
1FFFF16
2000016
External RAM area
(M5M5256DP ✕ 2)
2FFFF16
Fig. 16.1.18 Example of flash memory and SRAM connection (maximum model)
16–22
7721 Group User’s Manual
APPLICATION
16.1 Memory connection
<When reading>
tw(EL) = 135 (min.)
E
td(AL-E) = 15 (min.)
A
A1–A7
A8/D8–A15/D15
A16/D0–A18/D2
D3–D7
A
A
A
tpzx(E-DLZ/DHZ) = 20 (min.)
AC573(tPHL/tPLH)+AC139(tPHL)
CE, S
ta(CE)✽, ta(S)✽✽
AC32(tPLH)
OE
AC32(tPHL)
✽
ta(OE)✽✽
tDF✽/tdis(OE)✽✽ = 15 (max.)
(Guaranteed as kit.)
External memory
data output
D
tsu(DL/DH-E) ≥ 30
tsu(A-DL/DH) = 130 (max.)
t
✽
a(AD)✽✽
+AC573(tPHL/tPLH)
<When writing>
tw(EL) = 135 (min.)
E
td(AL-E) = 15 (min.)
A
A1–A7
A8/D8–A15/D15
A16/D0–A18/D2
D3–D7
A
D
A
td (E-DLQ/DHQ) = 35 (max.)
A
tsu (D)✽✽ ≥ 30
th(E-DLQ/DHQ) = 18 (min.)
AC573(tPHL)+AC139(tPHL)
S
AC32(tPLH)
AC32(tPHL)
WE, WO
✽: Specifications of M5M28F102AFP-10
✽ ✽: Specifications of M5M5256DP-70LL
The others are specifications of M37721.
(Unit : ns)
Fig. 16.1.19 Timing chart for example of flash memory and SRAM connection (maximum model)
7721 Group User’s Manual
16–23
APPLICATION
16.1 Memory connection
(3) Example of DRAM connection (external bus width = 8 bits) ➀
M37721
M5M44800CJ-7
MA0
A0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
A1
A2
A3
A4
A5
A6
A7
A8
A9
RAS
RAS
CAS
R/W
CAS
W
✽: Make sure that the propagation delay
time is within 80 ns.
Memory map
00000016
00008016
00047F16
E
A16/D0
A17/D1
A18/D2
A19/D3
A20/D4
A21/D5
A22/D6
A23/D7
AC32
SFR area
Internal
RAM area
Not used
001FC016
001FFF16
SFR area
✽
OE
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
Not used
F0000016
DRAM area
F7FFFF16 (M5M44800CJ)
Not used
FFFFFF16
BYTE
XIN
XOUT
Circuit condition : DRAM area select bits (bits 3 to 0 at address 6416) = “00012”
25 MHz
Fig. 16.1.20 Example of M5M44800CJ (512K ✕ 8 bits) connection (external bus width = 8 bits)
16–24
7721 Group User’s Manual
APPLICATION
16.1 Memory connection
<When reading>
E
(OE)
tw(EL) = 135 (min)
tw(RASL) = 120 (min)
RAS
tw(RASH) = 60 (min)
td(E-RASL) = 30 (max)
CAS
td(E-CASL) = 77.5 (max)
td(RA-RAS) = 5 (min)
MA0–MA9
td(RAS-CAS) = 28 (min)
tw(CASL) = 92.5 (min)
td(CA-CAS) = 5 (min)
Row address
Column address
tOEA✽ = 20 (max)
td(E-CA) = 60 (max)
tAA✽ = 35 (max)
tpzx(E-DLZ) = 20 (min)
tRAC✽ = 70 (max)
A16/D0–
A23/D7
Address
Input data
tCLZ✽ = 5 (min)
tsu(DL-E) ≥ 30
tCAC✽ = 20 (max)
tOEZ✽ = 0–20
<When writing>
tw(EL) = 135 (min)
E
tw(RASH) = 60 (min)
tw(RASL) = 120 (min)
RAS
tw(CASL) = 55 (min)
CAS
td(E-CASL) = 80–115
td(R/W-E) = 20 (min)
R/W
AC32(tPHL)
AC32(tPHL)
tWCS✽ = 0 (min)
tWCH✽ = 15 (min)
W
td(RA-RAS) = 5 (min)
MA0–MA9
th(RAS-RA) = 18 (min)
Column address
Row address
td(CA-CAS) = 10 (min)
A16/D0–
A23/D7
Address
th(CAS-CA) = 60 (min)
Data
tDH✽ = 15 (min)
th(E-DLQ) = 18 (min)
✽ : Specifications of M5M44800CJ-7
The others are specifications of M37721.
(Unit : ns)
Fig. 16.1.21 Timing chart for example of M5M44800CJ (512K ✕ 8 bits) connection (external bus width
= 8 bits)
7721 Group User’s Manual
16–25
APPLICATION
16.1 Memory connection
(4) Example of DRAM connection (external bus width = 8 bits) ➁
M37721
M5M417800CJ-7
A0
MA1
MA2
MA3
A1
A2
A3
MA4
MA5
MA6
A4
A5
A6
MA7
MA8
MA9
A7
A8
A9
00000016
A10
00047F16
00008016
CAS
001FC016
W
001FFF16
A20/D4
A21/D5
A22/D6
A23/D7
ALE
AC32
AC573✽2
D0
D1
D2
D3
Q4
D4
D5
D6
OE
D7 LE
✽1
SFR area
Internal
RAM area
Not used
RAS
CAS
R/W
A16/D0
A17/D1
A18/D2
A19/D3
XIN
Memory map
RAS
E
BYTE
✽1 : Make sure that the propagation delay
time is within 80 ns.
✽2 : Make sure that the propagation delay
time is within 15 ns.
MA0
SFR area
OE
D0
D1
D2
D3
D4
D5
D6
D7
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Not used
E0000016
DRAM area
(M5M417800CJ)
DQ8
8
FFFFFF16
XOUT
Circuit condition : DRAM area select bits (bits 3 to 0 at address 6416) = “00102”
25 MHz
Fig. 16.1.22 Example of M5M417800CJ (2M ✕ 8 bits) connection (external bus width = 8 bits)
16–26
7721 Group User’s Manual
APPLICATION
16.1 Memory connection
<When reading>
E
(OE)
tw(EL) = 135 (min)
tw(RASL) = 120 (min)
RAS
tw(RASH) = 60 (min)
td(E-RASL) = 30 (max)
CAS
td(RAS-CAS) = 28 (min)
td(E-CASL) = 77.5 (max)
td(RA-RAS) = 5 (min)
tw(CASL) = 92.5 (min)
td(CA-CAS) = 5 (min)
Row address
MA0–MA9
Column address
tOEA✽ = 20 (max)
td(E-CA) = 60 (max)
A16/D0–
A23/D7
tAA✽ = 35 (max)
tpzx(E-DLZ) = 20 (min)
tRAC✽ = 70 (max)
Address
Input data
tCLZ✽ = 5 (min)
tsu(DL-E) ≥ 30
tCAC✽ = 20 (max)
td(AH-E) = 15 (min)
tOEZ✽ = 0–15
A10
(M5M417800AJ)
AC573
tASR = 0 (min)
<When writing>
tw(EL) = 135 (min)
E
tw(RASH) = 60 (min)
tw(RASL) = 120 (min)
RAS
tw(CASL) = 55 (min)
CAS
td(E-CASL) = 80–115
td(R/W-E) = 20 (min)
R/W
AC32(tPHL)
AC32(tPHL)
tWCS✽ = 0 (min)
tWCH✽ = 10 (min)
W
td(RA-RAS) = 5 (min)
MA0–MA9
th(RAS-RA) = 18 (min)
Row address
Column address
td(CA-CAS) = 10 (min)
A16/D0–
A23/D7
Address
th(CAS-CA) = 60 (min)
Data
tDH✽ = 15 (min)
th(E-DLQ) = 18 (min)
✽ : Specifications of M5M417800CJ-7
The others are specifications of M37721.
(Unit : ns)
Fig. 16.1.23 Timing chart for example of M5M417800CJ (2M ✕ 8 bits) connection (external bus width
= 8 bits)
7721 Group User’s Manual
16–27
APPLICATION
16.1 Memory connection
(5) Example of DRAM connection (external bus width = 8 bits) ➂
10
4
M37721
M5M44400CJ-7
M5M44400CJ-7
MA0
MA1
MA0
A0
MA1
MA2
MA3
A1
A2
A3
MA4
MA5
MA6
A4
A5
A6
MA7
MA8
MA9
A7
A8
A9
RAS
RAS
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
✽ : Make sure that the propagation
delay time is within 80 ns.
Memory map
00000016
00008016
00047F16
SFR area
Internal
RAM area
Not used
CAS
R/W
E
A16/D0
A17/D1
A18/D2
A19/D3
AC32 ✽
CAS
W
RAS
CAS
W
E
RAS
CAS
W
OE
001FC016
001FFF16
OE
DQ1
DQ2
DQ3
DQ4
Not used
DQ1
DQ2
DQ3
DQ4
SFR area
F0000016
DRAM area
BYTE
A20/D4
A21/D5
(M5M44400CJ
✕ 2)
A22/D6
A23/D7
XIN
FFFFFF16
XOUT
Circuit condition : DRAM area select bits (bits 3 to 0 at address 6416) = “00012”
25 MHz
Fig. 16.1.24 Example of M5M44400CJ (1M ✕ 4 bits) connection (external bus width = 8 bits)
16–28
7721 Group User’s Manual
APPLICATION
16.1 Memory connection
<When reading>
E
(OE)
tw(EL) = 135 (min)
tw(RASL) = 120 (min)
RAS
tw(RASH) = 60 (min)
td(RAS-CAS) = 28 (min)
td(E-RASL) = 30 (max)
CAS
td(E-CASL) = 77.5 (max)
td(RA-RAS) = 5 (min)
MA0–MA9
tw(CASL) = 92.5 (min)
td(CA-CAS) = 5 (min)
Row address
Column address
tOEA✽ = 20 (max)
tAA✽ = 35 (max)
td(E-CA) = 60 (max)
A16/D0–
A23/D7
tpzx(E-DLZ) = 20 (min)
tRAC✽ = 70 (max)
Address
Input data
tCLZ✽ = 5 (min)
tCAC✽ = 20 (max)
tsu(DL-E) ≥ 30
tOEZ✽ = 0–20
<When writing>
tw(EL) = 135 (min)
E
tw(RASH) = 60 (min)
tw(RASL) = 120 (min)
RAS
tw(CASL) = 55 (min)
CAS
td(E-CASL) = 80–115
td(R/W-E) = 20 (min)
R/W
AC32(tPHL)
AC32(tPHL)
tWCS✽ = 0 (min)
tWCH✽ = 15 (min)
W
td(RA-RAS) = 5 (min)
MA0–MA9
th(RAS-RA) = 18 (min)
Row address
Column address
td(CA-CAS) = 10 (min)
A16/D0–
A23/D7
Address
th(CAS-CA) = 60 (min)
Data
tDH✽ = 15 (min)
th(E-DLQ) = 18 (min)
✽ : Specifications of M5M44400CJ-7
The others are specifications of M37721.
(Unit : ns)
Fig. 16.1.25 Timing chart for example of M5M44400CJ (1M ✕ 4 bits) connection (external bus width = 8 bits)
7721 Group User’s Manual
16–29
APPLICATION
16.1 Memory connection
(6) Example of DRAM connection (external bus width = 16 bits) ➀
M5M418160CJ-7
M37721
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
RAS
RAS
AC157
1A
CAS
1B
BLE
BHE
2A
2B
ST0
E
00008016
1Y
LCAS
00047F16
2Y
UCAS
001FC016
SFR area
Internal
RAM area
Not used
001FFF16
SFR area
OE
W
R/W
A16/D0
A17/D1
A18/D2
A19/D3
A20/D4
A21/D5
A22/D6
A23/D7
A8/D8
A9/D9
A10/D10
A11/D11
A12/D12
A13/D13
A14/D14
A15/D15
Memory map
00000016
✽2
SELECT ST
ST1
✽1 : Make sure that the
propagation delay time is
within 20 ns.
✽2 : Make sure that the
propagation delay time is
within 7.5 ns.
AC32
Not used
✽1
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
E0000016
DRAM area
(M5M418160CJ)
FFFFFF16
BYTE
XIN
XOUT
25 MHz
Circuit condition : DRAM area select bits (bits 3 to 0 at address 6416) = “0010 2”
Fig. 16.1.26 Example of M5M418160CJ (1M ✕ 16 bits) connection (external bus width = 16 bits)
16–30
7721 Group User’s Manual
APPLICATION
16.1 Memory connection
<When reading>
E
(OE)
tw(EL) = 135 (min)
tw(RASL) = 120 (min)
RAS
tw(RASH) = 60 (min)
td(E-RASL) = 30 (max)
CAS
td(E-CASL) = 77.5 (max)
td(RA-RAS) = 5 (min)
MA0–MA9
td(RAS-CAS) = 28 (min)
tw(CASL) = 92.5 (min)
td(CA-CAS) = 5 (min)
Row address
Column address
tOEA✽
td(E-CA) = 60 (max)
= 20 (max)
tAA✽ = 35 (max)
tpzx(E-DLZ/DHZ) = 20 (min)
tRAC✽ = 70 (max)
A16/D0–A23/D7,
A8/D8–A15/D15
Address
Input data
tCLZ✽ = 5 (min)
+ AC157 (tPHL)
td(BLE/BHE-E) = 20 (min)
tsu(DL/DH-E) ≥ 30
tCAC✽ = 20 (max)
+ AC157 (tPHL)
tOEZ✽ = 0–15
BLE/BHE
<When writing>
tw(EL) = 135 (min)
E
tw(RASH) = 60 (min)
tw(RASL) = 120 (min)
RAS
tw(CASL) = 55 (min)
CAS
td(E-CASL) = 80–115
td(R/W-E) = 20 (min)
R/W
AC32(tPHL)
AC32(tPHL)
tWCS✽ = 0 (min)
tWCH✽ = 10 (min)
W
td(RA-RAS) = 5 (min)
MA0–MA9
th(RAS-RA) = 18 (min)
Column address
Row Address
th(CAS-CA) = 60 (min)
td(CA-CAS) = 10 (min)
A16/D0–A23/D7,
A8/D8–A15/D15
Address
Data
td(BLE/BHE-E) = 20 (min)
tDH✽ = 15 (min)
+ AC157(tPHL)
th(E-DLQ/DHQ) = 18 (min)
BLE/BHE
✽ : Specifications of M5M418160CJ-7
The others are specifications of M37721.
(Unit : ns)
Fig. 16.1.27 Timing chart for example of M5M418160CJ (1M ✕ 16 bits) connection (external bus width = 16 bits)
7721 Group User’s Manual
16–31
APPLICATION
16.1 Memory connection
(7) Example of DRAM connection (external bus width = 16 bits) ➁
M37721
M5M44170CJ-7
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
RAS
CAS
E
RAS
CAS
OE
LW
R/W
A16/D0
A17/D1
A18/D2
A19/D3
A20/D4
A21/D5
A22/D6
A23/D7
00008016
WH
AC32 ✽1
D0
D1
D2
D3
D4
D5
D6
D7
Memory map
00000016
WL
BLE
BHE
✽1 : Make sure that the
propagation delay time is
within 40 ns.
✽2 : Make sure that the
propagation delay time is
within 15 ns.
UW
D0
D1
D2
D3
D4
D5
D6
D7
Q1
Q2
OE
LE
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
00047F16
SFR area
Internal
RAM area
Not used
001FC016
001FFF16
SFR area
Not used
✽2
AC573
ALE
A8/D8
A9/D9
A10/D10
A11/D11
A12/D12
A13/D13
A14/D14
A15/D15
BYTE
XIN
8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
F0000016
F7FFFF16
DRAM area
(M5M44170CJ)
Not used
FFFFFF16
XOUT
25 MHz
Circuit condition : DRAM area select bits (bits 3 to 0 at address 6416) = “00012”
Fig. 16.1.28 Example of M5M44170CJ (256K ✕ 16 bits) connection (external bus width = 16 bits)
16–32
7721 Group User’s Manual
APPLICATION
16.1 Memory connection
<When reading>
E
(OE)
tw(EL) = 135 (min)
tw(RASL) = 120 (min)
RAS
tw(RASH) = 60 (min)
td(E-RASL) = 30 (max)
CAS
td(RAS-CAS) = 28 (min)
td(E-CASL) = 77.5 (max)
td(RA-RAS) = 5 (min)
MA0–MA7
tw(CASL) = 92.5 (min)
td(CA-CAS) = 5 (min)
Row address
Column address
tOEA✽ = 20 (max)
td(E-CA) = 60 (max)
tAA✽ = 35 (max)
tpzx(E-DLZ/DHZ) = 20 (min)
tRAC✽ = 70 (max)
A16/D0–A23/D7,
A8/D8–A15/D15
Address
Input data
tCLZ✽ = 5 (min)
td(AH-E) = 15 (min)
tsu(DL/DH-E) ≥ 30 tOEZ✽ = 0–20
tCAC✽ = 20 (max)
A8, A9
(M5M44170AJ)
AC573
tASR = 0 (min)
<When writing>
tw(EL) = 135 (min)
E
tw(RASH) = 60 (min)
tw(RASL) = 120 (min)
RAS
tw(CASL) = 55 (min)
CAS
td(E-CASL) = 80–115
td(R/W-E) = 20 (min)
R/W
AC32(tPHL) ✕ 2
AC32(tPHL) ✕ 2
tWCS✽ = 0 (min)
tWCH✽ = 15 (min)
WL/WH
td(RA-RAS) = 5 (min)
MA0–MA9
th(RAS-RA) = 18 (min)
Row address
Column address
td(CA-CAS) = 10 (min)
A16/D0–A23/D7,
A8/D8–A15/D15
Address
th(CAS-CA) = 60 (min)
Data
tDH✽ = 15 (min)
td(BLE/BHE–E) = 20 (min)
th(E-DLQ/DHQ) = 18 (min)
BLE/BHE
✽ : Specification of M5M44170CJ-7
The others are specifications of M37721.
(Unit : ns)
Fig. 16.1.29 Timing chart for example of M5M44170CJ (256K ✕ 16 bits) connection (external bus width = 16 bits)
7721 Group User’s Manual
16–33
APPLICATION
16.1 Memory connection
(8) Example of DRAM connection (external bus width = 16 bits) ➂
10
4
M37721
M5M417800CJ-7
MA0
A0
MA1
MA2
MA3
A1
A2
A3
MA4
MA5
MA6
MA7
MA8
MA9
A4
A5
A6
A7
A8
A9
RAS
CAS
E
RAS
CAS
OE
M5M417800CJ-7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A10
WL
BLE
RAS
CAS
OE
W
W
R/W
✽1 : Make sure that the
propagation delay time is
within 40 ns.
✽2 : Make sure that the
propagation delay time is
within 15 ns.
Memory map
00000016
00008016
00047F16
WH
Not used
BHE
AC32 ✽1
A16/D0
A17/D1
A18/D2
A19/D3
A20/D4
A21/D5
A22/D6
A23/D7
ALE
A8/D8
A9/D9
✽2
001FC016
AC573
D0
D1
D2
D3
Q4
D4
D5
D6
OE
D7 LE
D0
D1
DQ1
DQ2
D8
D9
D2
D3
D4
DQ3
DQ4
DQ5
D10
D11
D12
D5
D6
D7
DQ6
DQ7
DQ8
D13
D14
D15
DQ1
DQ2
XIN
001FFF16
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
SFR area
Not used
E0000016
DRAM area
8
(M5M417800CJ
✕ 2)
FFFFFF16
A10/D10
A11/D11
A12/D12
BYTE
SFR area
Internal
RAM area
A13/D13
A14/D14
A15/D15
XOUT
Circuit condition : DRAM area select bits (bits 3 to 0 at address 6416) = “00102”
25 MHz
Fig. 16.1.30 Example of M5M417800CJ (2M ✕ 8 bits) connection (external bus width = 16 bits)
16–34
7721 Group User’s Manual
APPLICATION
16.1 Memory connection
<When reading>
E
(OE)
tw(EL) = 135 (min)
tw(RASL) = 120 (min)
RAS
tw(RASH) = 60 (min)
td(E-RASL) = 30 (max)
CAS
td(RAS-CAS) = 28 (min)
td(E-CASL) = 77.5 (max)
td(RA-RAS) = 5 (min)
MA0–MA9
tw(CASL) = 92.5 (min)
td(CA-CAS) = 5 (min)
Row address
Column address
tOEA✽ = 20 (max)
tAA✽ = 35 (max)
td(E-CA) = 60 (max)
A16/D0–A23/D7,
A8/D8–A15/D15
tpzx(E-DLZ/DHZ) = 20 (min)
tRAC✽ = 70 (max)
Address
Input data
tCLZ✽ = 5 (min)
tCAC✽ = 20 (max)
td(AH-E) = 15 (min)
tsu(DL/DH-E) ≥ 30
tOEZ✽ = 0–15
A10
(M5M417800AJ)
AC573
tASR = 0 (min)
<When writing>
tw(EL) = 135 (min)
E
tw(RASH) = 60 (min)
tw(RASL) = 120 (min)
RAS
tw(CASL) = 55 (min)
CAS
td(E-CASL) = 80–115
td(R/W-E) = 20 (min)
R/W
AC32(tPHL)
AC32(tPHL)
tWCS✽ = 0 (min)
tWCH✽ = 10 (min)
W
td(RA-RAS) = 5 (min)
MA0–MA9
th(RAS-RA) = 18 (min)
Row address
Column address
td(CA-CAS) = 10 (min)
A16/D0–A23/D7,
A8/D8–A15/D15
Address
th(CAS-CA) = 60 (min)
Data
tDH✽ = 15 (min)
th(E-DLQ/DHQ) = 18 (min)
✽ : Specifications of M5M417800CJ-7
The others are specifications of M37721.
(Unit : ns)
Fig. 16.1.31 Timing chart for example of M5M417800CJ (2M ✕ 8 bits) connection (external bus width = 16 bits)
7721 Group User’s Manual
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APPLICATION
16.1 Memory connection
(9) Example of DRAM connection (external bus width = 16 bits) ➃
M5M44400CJ-7
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
A0
A1
A2
A3
A4
A5
A6
A7
A0
A1
A2
A3
A4
A5
A6
A7
A0
A1
A2
A3
A4
A5
A6
A7
A0
A1
A2
A3
A4
A5
A6
A7
MA8
MA9
A8
A9
A8
A9
A8
A9
A8
A9
RAS
CAS
OE
RAS
CAS
OE
RAS
CAS
OE
RAS
CAS
OE
W
DQ1
DQ2
DQ3
DQ4
W
DQ1
DQ2
DQ3
DQ4
M37721
✽ : Make sure that the propagation
delay time is within 40 ns.
00008016
BLE
WH
00047F16
BHE
A16/D0
A17/D1
W
DQ1
DQ2
DQ3
DQ4
WL
W
DQ1
DQ2
DQ3
DQ4
RAS
CAS
E
R/W
Memory map
00000016
✽
001FC016
001FFF16
E0000016
DRAM area
A8/D8
A9/D9
A10/D10
XIN
A12/D12
A13/D13
A14/D14
A15/D15
A8/D8
A9/D9
A10/D10
A11/D11
A20/D4
A21/D5
A22/D6
A23/D7
(M5M4400CJ
✕ 4)
A16/D0
A17/D1
A18/D2
A19/D3
BYTE
SFR area
Not used
A21/D5
A22/D6
A23/D7
A14/D14
A15/D15
Internal
RAM area
Not used
AC32
A18/D2
A19/D3
A20/D4
A11/D11
A12/D12
A13/D13
SFR area
FFFFFF16
XOUT
25 MHz
Circuit condition : DRAM area select bits (bits 3 to 0 at address 6416) = “0010 2”
Fig. 16.1.32 Example of M5M44400CJ (1M ✕ 4 bits) connection (external bus width = 16 bits)
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APPLICATION
16.1 Memory connection
<When reading>
E
(OE)
tw(EL) = 135 (min)
tw(RASL) = 120 (min)
RAS
tw(RASH) = 60 (min)
td(E-RASL) = 30 (max)
CAS
td(E-CASL) = 77.5 (max)
td(RA-RAS) = 5 (min)
MA0–MA9
td(RAS-CAS) = 28 (min)
tw(CASL) = 92.5 (min)
td(CA-CAS) = 5 (min)
Row address
Column address
tOEA✽ = 20 (max)
tAA✽ = 35 (max)
td(E-CA) = 60 (max)
A16/D0–A23/D7,
A8/D8–A15/D15
tpzx(E-DLZ/DHZ) = 20 (min)
tRAC✽ = 70 (max)
Address
Input data
tCLZ✽ = 5 (min)
tsu(DL/DH-E) ≥ 30 tOEZ✽ = 0–20
tCAC✽ = 20 (max)
<When writing>
tw(EL) = 135 (min)
E
tw(RASH) = 60 (min)
tw(RASL) = 120 (min)
RAS
tw(CASL) = 55 (min)
CAS
td(E-CASL) = 80–115
td(R/W-E) = 20 (min)
R/W
AC32(tPHL) ✕ 2
AC32(tPHL) ✕ 2
tWCS✽ = 0 (min)
tWCH✽ = 10 (min)
WL/WH
td(RA-RAS) = 5 (min)
MA0–MA9
th(RAS-RA) = 18 (min)
Row address
Column address
td(CA-CAS) = 10 (min)
A16/D0–A23/D7,
A8/D8–A15/D15
Address
th(CAS-CA) = 60 (min)
Data
tDH✽ = 15 (min)
td(BLE/BHE–E) = 20 (min)
th(E-DLQ/DHQ) = 18 (min)
BLE/BHE
✽ : Specifications of M5M44400CJ-7
The others are specifications of M37721.
(Unit : ns)
Fig. 16.1.33 Timing chart for example of M5M44400CJ (1M ✕ 4 bits) connection (external bus width = 16 bits)
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APPLICATION
16.1 Memory connection
(10) Example of DRAM connection (external bus width = 16 bits) ➄
M37721
M5M44260CJ-7
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
A0
A1
A2
A3
A4
A5
A6
A7
A8
RAS
AC157✽2
✽1 : Make sure that the
propagation delay time is
within 20 ns.
✽2 : Make sure that the
propagation delay time is
within 7.5 ns.
RAS
1A
CAS
1B
BLE
1Y
LCAS
2Y
UCAS
2A
2B
BHE
ST0
Memory map
00000016
SELECT ST
ST1
00008016
OE
E
R/W
BYTE
XIN
A16/D0
A17/D1
A18/D2
A19/D3
A20/D4
A21/D5
A22/D6
A23/D7
A8/D8
A9/D9
A10/D10
A11/D11
A12/D12
A13/D13
A14/D14
A15/D15
XOUT
00047F16
W
AC32 ✽1
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
SFR area
Internal
RAM area
Not used
001FC016
001FFF16
SFR area
Not used
F0000016
F7FFFF16
DRAM area
(M5M44260CJ)
Not used
FFFFFF16
25 MHz
Circuit condition : DRAM area select bits (bits 3 to 0 at address 6416) = “00012”
Fig. 16.1.34 Example of M5M44260CJ (256K ✕ 16 bits) connection (external bus width = 16 bits)
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7721 Group User’s Manual
APPLICATION
16.1 Memory connection
<When reading>
E
(OE)
tw(EL) = 135 (min)
tw(RASL) = 120 (min)
RAS
tw(RASH) = 60 (min)
td(E-RASL) = 30 (max)
CAS
td(E-CASL) = 77.5 (max)
td(RA-RAS) = 5 (min)
MA0–MA8
td(RAS-CAS) = 28 (min)
tw(CASL) = 92.5 (min)
td(CA-CAS) = 5 (min)
Row address
Column address
tOEA✽ = 20 (max)
td(E-CA) = 60 (max)
tAA✽ = 35 (max)
tpzx(E-DLZ/DHZ) = 20 (min)
tRAC✽ = 70 (max)
A16/D0–A23/D7,
A8/D8–A15/D15
Address
Input data
tCLZ✽ = 5 (min)
+ AC157 (tPHL)
tCAC✽ = 20 (max)
+ AC157 (tPHL)
td(BLE/BHE-E) = 20 (min)
tsu(DL/DH-E) ≥ 30
tOEZ✽ = 0–20
BLE/BHE
<When writing>
tw(EL) = 135 (min)
E
tw(RASH) = 60 (min)
tw(RASL) = 120 (min)
RAS
tw(CASL) = 55 (min)
CAS
td(E-CASL) = 80–115
td(R/W-E) = 20 (min)
R/W
AC32(tPHL)
AC32(tPHL)
tWCS✽ = 0 (min)
tWCH✽ = 15 (min)
W
td(RA-RAS) = 5 (min)
MA0–MA8
th(RAS-RA) = 18 (min)
Column address
Row Address
td(CA-CAS) = 10 (min)
A16/D0–A23/D7,
A8/D8–A15/D15
Address
th(CAS-CA) = 60 (min)
Data
tDH✽ = 15 (min)
+ AC157(tPHL)
th(E-DLQ/DHQ) = 18 (min)
td(BLE/BHE-E) = 20 (min)
BLE/BHE
✽ : Specifications of M5M44260CJ-7
The others are specification of M37721.
(Unit : ns)
Fig. 16.1.35 Timing chart for example of M5M44260CJ (256K ✕ 16 bits) connection (external bus width = 16 bits)
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APPLICATION
16.1 Memory connection
16.1.4 Example of I/O expansion
(1) Example of port expansion circuit using M66010FP
Figure 16.1.36 shows an example of a port expansion circuit using the M66010FP. Make sure that
the frequency of Serial I/O transfer clock must be 1.923 MHz or less.
About Serial I/O control in this expansion example is described below.
In this example, 8-bit data transmission/reception is performed 3 times by using UART0, so that 24bit port expansion is realized. Setting of UART0 is described below:
● Clock synchronous serial I/O mode: Transmission/Reception enable state
● Internal clock is selected. Transfer clock frequency is 1.66 MHz.
● LSB first
The control procedure is described below:
➀ Output “L” level from port P45. (Expanded I/O ports of the M66010FP enter a floating state by this
signal. )
➁ Output “H” level from port P4 5.
➂ Output “L” level from port P44.
➃ Transmit/Receive 24-bit data by using UART0.
➄ Output “H” level from port P4 4.
Figure 16.1.37 shows the serial transfer timing between the M37721 and the M66010FP.
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APPLICATION
16.1 Memory connection
M37721
BYTE
M66010FP
TxD0
DI
RxD0
DO
CLK0
CLK
P44
CS
P45
S
RTS0
Open
A0–A7
A8/D8–A15/D15
Vcc
A16/D0–A23/D7
ALE
E
1
R/W
BHE
BLE
XIN
XOUT
25 MHz
GND
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
Expanded input ports
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
Circuit conditions: •UART0 used in clock synchronous serial I/O mode
•Internal clock selected
f2
•Frequency of transfer clock =
= 1.5625 MHz
2 (3 + 1)
Fig. 16.1.36 Example of port expansion circuit using M66010FP
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16–42
CS
P44
7721 Group User’s Manual
D2
Expanded I/O port
Fig. 16.1.37 Serial transfer timing between M37721 and M66010FP
Expanded I/O port D24
to
D1
DO
RXD0
Expanded I/O port
DI
TXD0
CLK0 CLK
S
P45
DI1
DO3
DO4
DO5
DO6
DI2
DI3
DI4
DI5
DI6
DI7
DO7
DI8
DO8
DI20
DO20
DI22
DO22
DI23
DO23
DI24
DO24
DO24
DO2
DO1
: M37721’s pin name
The others are M66010FP’s pin’s names or
operations.
DI21
DO21
Data of shift register 2 is output to
expanded I/O ports.
✽ Output structure of expanded I/O ports is N-channel open-drain output.
DI24
DI2
DI1
DO2
Data of shift register 1 is output in serial.
DO1
Serial data is input to shift register 2.
Data of expanded I/O ports is output to shift register 1.
Expanded I/O ports are released from floating state.
APPLICATION
16.1 Memory connection
APPLICATION
16.2 Examples of using DMA controller
16.2 Examples of using DMA controller
16.2.1 Example of Centronics interface configuration
The following is an example of Centronics interface configurated by using DMA0, Timers A2 and A3.
(1) Specifications
•Octal
latch’s contents are transferred to the data buffer (RAM) by using DMA0. The trigger is the
____
STB signal. (Refer to____
“Figure 16.2.1.”)
•“L” level width of the ACK_________
signal is generated by using Timer A2; one-shot pulse mode; the trigger
is the rising edge of the DMAACK0 signal. (Refer
to “Figure 16.2.2.”)
____
•Timer A3 generates the time from when the ACK signal
rises until the BUSY signal falls; one-shot
_________
pulse mode; the trigger is the rising edge of the DMAACK0 signal. (Refer to “Figure 16.2.2.”)
•P4 3 is used for BUSY signal generation. When outputting “H” level, the next transfer can wait. In that
case, the contents of the preceding transfer are hold in the octal latch.
•When the data buffer is filled (in other words, DMA transfer is completed), a DMA interrupt occurs.
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APPLICATION
16.2 Examples of using DMA controller
M37721
Octal latch
Data
Data bus
AC574
OC
T
CS
RD
STB
DMAREQ0
D-F/F
Q S
BUSY
D T
TA3OUT (one-shot output)
TA3IN
DMAACK0
TA2IN
P43
ACK
TA2OUT (one-shot output)
XIN
XOUT
25 MHz
Fig. 16.2.1 Example of Centronics interface configuration
DMAACK0
T2
TA2OUT
T3
TA3OUT
ACK
T2 : Timer A2’s set time
T3 : Timer A3’s set time
BUSY
____
Fig. 16.2.2 Relationship between ACK and BUSY
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APPLICATION
16.2 Examples of using DMA controller
(2) Initial setting example for relevant register
b7
b0
1
Port P4 register (Address A16)
P43 output : H level
b7
b0
Port P5 register (Address B16)
1
TA3OUT output : H level (D-F/F initialized)
b7
b0
1
Port P4 direction register (Address C16)
P43 : Output mode
b7
b0
0
1
0
Port P5 direction register (Address D16)
TA2IN pin : Input mode
TA3OUT pin : Output mode (D–F/F initialized)
TA3IN pin : Input mode
b7
b0
0
Port P9 direction register (Address 1516)
DMAREQ0 pin : Input mode
b7
0
b0
1
0
0
0
1 0
1 DMA0 mode register L (Address 1FCC16)
Transfer unit : 8 bits
2-bus cycle transfer
Cycle-steal transfer mode
Transfer source address direction : Fixed
Transfer destination address direction : Forward
b7
0
b0
0
0
0
0
0 ✕ 0 DMA0 mode register H (Address 1FCD16)
Transfer source Wait
Transfer destination Wait
Single transfer mode
✕ : It may be “0” or “1.”
Fig. 16.2.3 Initial setting example for relevant register (1)
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APPLICATION
16.2 Examples of using DMA controller
b23
b16 b15
b8 b7
b0
Source address register 0 (Addresses 1FC216 to 1FC016)
Octal latch’s address
b23
b16 b15
b8 b7
b0
Destination address register 0 (Addresses 1FC616 to 1FC416)
Data buffer’s start address
b23
b16 b15
b8 b7
b0
Transfer counter register 0 (Addresses 1FCA16 to 1FC816)
Data buffer size (unit : byte)
b7
b0
0
1
1
1 1
0
Timer A2 mode register (Address 5816)
One-shot pulse mode
Trigger : Rising edge of TA2IN pin’s input signal
Count source
b7
b0
0
1
1
1 1
0 Timer A3 mode register (Address 5916)
One-shot pulse mode
Trigger : Rising edge of TA3IN pin’s input signal
Count source
b15
b8 b7
b0
Timer A2 register (Addresses 4B16, 4A16)
ACK signal’s “L” level time (T2 in Figure 16.2.2)
b15
b8 b7
b0
Timer A3 register (Addresses 4D16, 4C16)
Period from falling edge of ACK signal until falling edge of BUSY signal
(T3 in Figure 16.2.2)
Fig. 16.2.4 Initial setting example for relevant register (2)
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APPLICATION
16.2 Examples of using DMA controller
b7
b0
1
0
0
0 0
1
DMA0 control register (Address 1FCE16)
DMA request source : External source (DMAREQ0)
Edge sense selected
DMAACK0 pin : Valid
b7
b0
DMA0 interrupt control register (Address 6C16)
0
Interrupt priority level : any of “0012” to “1112”
b7
b0
1
Count start register (Address 4016)
1
Timer A2 count start
Timer A3 count start
b7
b0
DMAC control register L (Address 6816)
0
DMA0 request flag is set to “0.”
b7
b0
1
DMAC control register H (Address 6916)
DMA0 enabled
b7
b0
0
Port P4 register (Address A16)
P43 output : L level
Fig. 16.2.5 Initial setting example for relevant register (3)
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APPLICATION
16.2 Examples of using DMA controller
16.2.2 Example of stepping motor control
The following is an example where the slow-up or slow-down control for the stepping motor is performed
by using DMA1, DMA2, and RTP0.
(1) Specifications
•DMA1 transfers the stepping motor’s phase output data from the phase output data table to the
RTP0 pulse output data register. (Refer to “Figure 16.2.6” and “Table 16.2.1.”)
•DMA2 transfers the step time for slow up or slow down from the timer A0 set value data table to
the timer A0 register. (Refer to “Figure 16.2.6.”)
After slow up or slow down is completed, a DMA2 interrupt occurs.
•Phase output is performed by RTP0; pulse output mode 0 (Refer to “Figures 16.2.6 and 16.2.7.”)
•After slow up or slow down is completed, the motor operates with the definite rate.
M
Motor driver
M37721
ROM
Phase output
data table
RTP0
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAAAA
DMAC1
Stepping
motor
Bus
DMAC2
Timer
A0
Fig. 16.2.6 Example of stepping motor control
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7721 Group User’s Manual
Timer A0 set
value data table
APPLICATION
16.2 Examples of using DMA controller
Table 16.2.1 Example of phase output data table
1-2 phase
2-2 phase
0
0011
0011
1
1001
0001
2
1100
1001
3
0110
1000
4
0011
1001
1100
0100
1100
0110
0110
0010
5
6
7
Phase
Step
0
1
2
3
4
5
6
7
2-2 phase
RTP03
RTP02
RTP01
RTP00
1-2 phase
RTP03
RTP02
RTP01
RTP00
Fig. 16.2.7 Example of phase output
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APPLICATION
16.2 Examples of using DMA controller
(2) Initial setting example for relevant register
b7
0
b0
0
0
1 0
1 DMA1 mode register L (Address 1FDC16)
Transfer unit : 8 bits
2-bus cycle transfer
Cycle-steal transfer mode
Transfer source address direction : At regular turning ; “012” (Forward)
At reverse turning ; “102” (Backward)
Transfer destination address direction : Fixed
b7
0
b0
1
1
0
0
0 ✕ 0
DMA1 mode register H (Address 1FDD16)
Transfer source Wait
No transfer destination Wait
Repeat transfer mode
b23
b16 b15
b8 b7
b0
Source address register 1 (Addresses 1FD216 to 1FD016)
Phase output data table’s start address
b23
b16 b15
0016
b8 b7
0016
b0
Destination address register 1 (Addresses 1FD616 to 1FD416)
1A16
Pulse output data register 0’s address
b23
b16 b15
b8 b7
b0
Transfer counter register 1 (Addresses 1FDA16 to 1FD816)
Phase output data table’s data number
b7
b0
0 0
0
0
1
1 DMA1 control register (Address 1FDE16)
DMA request source : Timer A0
DMAACK1 pin : Invalid
b7
b0
0
0
0 DMA1 interrupt control register (Address 6D16)
Interrupt disabled
✕ : It may be “0” or “1.”
Fig. 16.2.8 Initial setting example for relevant register (1)
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APPLICATION
16.2 Examples of using DMA controller
b7
0
b0
0
0
0 DMA2 mode register L (Address 1FEC16)
1 0
Transfer unit : 16 bits
2-bus cycle transfer
Cycle-steal transfer mode
Transfer source address direction : At slow up; “012” (Forward)
At slow down; “102” (Backward)
Transfer destination address direction : Fixed
b7
0
b0
0
1
0
0
0 ✕ 0 DMA2 mode register H (Address 1FED16)
Transfer source Wait
No transfer destination Wait
Single transfer mode
b23
b16 b15
b8 b7
b0
Source address register 2 (Addresses 1FE216 to 1FE016)
Timer A0 set value data table’s start address
b23
b16 b15
0016
b8 b7
0016
b0
4616
Destination address register 2 (Addresses 1FE616 to 1FE416)
Timer A0 register’s address
b23
b16 b15
b8 b7
b0
Transfer counter register 2 (Addresses 1FEA16 to 1FE816)
Data number of Timer A0 set value data table
b7
b0
0 0
0
0
1
1 DMA2 control register (Address 1FEE16)
DMA request source : Timer A0
DMAACK2 pin : Invalid
b7
b0
0
DMA2 interrupt control register (Address 6E16)
Interrupt priority level : any of “0012” to “1112”
✕ : It may be “0” or “1.”
Fig. 16.2.9 Initial setting example for relevant register (2)
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APPLICATION
16.2 Examples of using DMA controller
b7
b0
1
1 1
1 Port P6 register (Address E16)
RTP00/P60–RTP03/P63 initial output : H level
b7
b0
1
1 1
1
Port P6 direction register (Address 1016)
RTP00/P60–RTP03/P63 pin : Output mode
b7
b0
Pulse output data register 0 (Address 1A16)
First phase output data
b7
b0
0
0 ✕ 0
0
0
TImer A0 mode register (Address 5616)
Count source
b7
b0
0
0
1
Real-time output control register (Address 6216)
RTP0
Pulse mode 0
b15
b8 b7
b0
Timer A0 register (Addresses 4716, 4616)
First step time
b7
b0
1 Count start register (Address 4016)
Timer A0 count start
b7
b0
0
DMAC control register L (Address 6816)
0
DMA1 request bit
DMA2 request bit
b7
are set to “0.”
b0
1
1
DMAC control register H (Address 6916)
DMA1 enabled
DMA2 enabled
✕ : It may be “0” or “1.”
Fig. 16.2.10 Initial setting example for relevant register (3)
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APPLICATION
16.2 Examples of using DMA controller
16.2.3 Example of dynamic lighting for LED
The following is an example of dynamic lighting for LED by using DMA3 and Timer B0.
(1) Specifications
•The eight 7-segment LEDs are lighted up; port P6 outputs the segment data; port P7 outputs the
digit data. (Refer to “Figure 16.2.11.”)
•The display data and the segment data are transferred from the data buffer to the port P6 and P7
registers by DMA3.
•Digit switch interval is generated by Timer B0.
•16 bytes of RAM are used as the data buffer. 1-digit display data consists of 2 bytes; the digit data
is placed in the high-order byte; the segment data is placed in the low-order byte. (Refer to “Table
16.2.2.”)
When the digit data and segment data are “0,” the LED is lighted up (ON): when they are “1,” the
light goes out (OFF).
Assuming that the segment pattern is generated by another processing.
M37721
7-segment LED ✕ 8
Data buffer
P67
LED
driver
P60
P77
LED
driver
P70
Fig. 16.2.11 Example of dynamic lighting for LED
Table 16.2.2 Data buffer
Digit data
Data buffer
Segment pattern
00000001
00000010
00000100
00001000
00010000
00100000
Segment pattern of the
contents to be displayed
in each digit
01000000
10000000
Notes 1: This applies in the following:
•when the digit data is “0,” the light goes
out.
•when the digit data is “1,” the LED is lighted
up.
2: Assuming that the segment pattern is
generated by another processing.
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APPLICATION
16.2 Examples of using DMA controller
b7
0
b0
0
0
1
0
1 0
0
DMA3 mode register L (Address 1FFC16)
Transfer unit : 16 bits
2-bus cycle transfer
Cycle-steal transfer mode
Transfer source address direction : Forward
Transfer destination address direction : Fixed
b7
0
b0
1
1
1
0
0
✕ 0
DMA3 mode register H (Address 1FFD16)
No transfer source Wait
No transfer destination Wait
Repeat transfer mode
b23
b16 b15
b8 b7
b0
Source address register 3 (Addresses 1FF216 to 1FF016)
Data buffer’s start address
b23
b16 b15
0016
b8 b7
0016
b0
Destination address register 3 (Addresses 1FF616 to 1FF416)
0E16
Port P6, P7 register’s address
b23
b16 b15
0016
b8 b7
0016
b0
1016
Transfer counter register 3 (Addresses 1FFA16 to 1FF816)
Data number (unit : byte)
b7
b0
0 0
1
0
0
0
DMA3 control register (Address 1FFE16)
DMA request source : Timer B0
DMAACK3 pin : Invalid
b7
b0
0 0 0 DMA3 interrupt control register (Address 6F16)
Interrupt disabled
✕ : It may be “0” or “1.”
Fig. 16.2.12 Initial setting example for relevant register (1)
16–54
7721 Group User’s Manual
APPLICATION
16.2 Examples of using DMA controller
b7
0
b0
0
0
0 0
0 0
0 Port P6 register (Address E16)
Output : L level (Lights go out.)
b7
0
b0
0
0
0 0
0 0
0 Port P7 register (Address F16)
Output : L level (All digits OFF)
b7
1
b0
1
1
1 1
1 1
1 Port P6 direction register (Address 1016)
Output mode
b7
1
b0
1
1
1 1
1 1
1 Port P7 direction register (Address 1116)
Output mode
b15
b8 b7
b0
Timer B0 register (Addresses 5116, 5016)
Digit switch interval
b7
b0
✕
✕ ✕ 0
0 Timer B0 mode register (Address 5B16)
Timer mode
Count source
b7
b0
0
0
0 Timer B0 interrupt control register (Address 7A16)
Interrupt disabled
b7
b0
Count start register (Address 4016)
1
Timer B0 count started
b7
b0
0
DMAC control register L (Address 6816)
DMA3 request bit : “0”
b7
1
b0
DMAC control register H (Address 6916)
DMA3 enabled
✕ : It may be “0” or “1.”
Fig. 16.2.13 Initial setting example for relevant register (2)
7721 Group User’s Manual
16–55
APPLICATION
16.3 Comparison of sample program execution rate
16.3 Comparison of sample program execution rate
Sample program execution rates are compared in this paragraph.
The execution time ratio depends on the program or the usage conditions.
16.3.1 Differences depending on data bus width and software Wait
Internal areas are always accessed with data bus of which width is 16 bits and no software Wait. In the
external areas, the external data bus width and software Wait are selectable. Table 16.3.1 lists the sample
program (Refer to “Figure 16.3.1.”) execution time ratio depending on these selection and usable memory
areas.
Table 16.3.1 Sample program execution time ratio (external data bus width and software Wait)
Memory area
External data bus
Sample program execution time ratio
Software Wait
Sample A
Sample B
ROM
width (unit : bit)
RAM
None
1.00
1.00
16
Inserted
1.17
1.10
External
Internal
None
1.19
1.08
8
Inserted
1.67
1.46
None
1.00
1.00
16
Inserted
1.25
1.17
Internal
External
None
1.19
1.13
8
Inserted
1.78
1.65
✽
Calculated value
0.92
0.90
Calculated value
16–56
✽
: The value is calculated from the shortest execution cycle number of each instruction
described in “7700 Family Software Manual.”
7721 Group User’s Manual
APPLICATION
16.3 Comparison of sample program execution rate
Sample A
SEP
LDA.B
STA
STA
STA
LDX.B
ITALIC: LDA
TAY
AND.B
STA
TYA
AND.B
ORA
STA
TYA
AND.B
ORA
STA
TYA
AND.B
ORA
STA
DEX
BPL
Sample B
M,X
A,#0
A,DEST+64
A,DEST+65
A,DEST+66
#63
A,SOUR,X
A,#00000011B
A,DEST,X
A,#00001100B
A,DEST+1,X
A,DEST+1,X
A,#00110000B
A,DEST+2,X
A,DEST+2,X
A,#11000000B
A,DEST+3,X
A,DEST+3,X
ITALIC
SEP
CLM
.DATA
.INDEX
LDY
LOOP0: LDX
LOOP1: ASL
SEM
.DATA
ROL
ROL
CLM
.DATA
ROR
DEX
DEX
DEX
BNE
STA
SEM
.DATA
STA
CLM
.DATA
DEY
DEY
DEY
BNE
X
16
8
#69
#69
SOUR,X
8
SOUR+2,X
B
16
A
LOOP1
A,DEST,Y
8
B,DEST+2,Y
16
LOOP0
✽ SOUR, DEST : Work area
(Direct page area : Access this area by using the following modes.)
•Direct addressing mode
•Direct Indexed X addressing mode
•Absolute Indexed Y addressing mode
Fig. 16.3.1 Sample program list
7721 Group User’s Manual
16–57
APPLICATION
16.3 Comparison of sample program execution rate
16.3.2 Comparison between software Wait (f(X IN) = 20 MHz) and software Wait + Ready (f(X IN) = 25 MHz)
Figure 16.3.3 shows the execution time ratio when sample programs in Figure 16.3.1 are executed on the
two conditions in Table 16.3.2. Figure 16.3.2 shows the memory assignment at execution rate comparison.
The execution time ratio depends on the program or the usage conditions.
Table 16.3.2 Comparison conditions
Condition ➀
Microprocessor mode
Microprocessor mode
f(X IN)
20 MHz
25 MHz
External data bus width
Software Wait
16 bits
Inserted
16 bits
Inserted
Invalid
Valid only for external EPROM area
External EPROM
Internal or External SRAM
External EPROM
Item
Processor mode
Ready
Program area
Work area
Condition ➁
Internal or External SRAM
M37721 memory map
SFR area
Internal SRAM
Specify either area as work area
Area where software
Wait is valid
External SRAM
Program area
External EPROM
Condition ➁ Ready valid area
Insert Wait which is equivalent to 2 cycles
of at access
(Software Wait included)
Fig. 16.3.2 Memory assignment at execution rate comparison
16–58
7721 Group User’s Manual
APPLICATION
16.3 Comparison of sample program execution rate
Figure 16.3.3 shows that there is almost no difference between conditions ➀ and ➁ about the execution
time. The bus buffers become unnecessary when using the specified memory. (Refer to “Table 16.1.6.”)
Considering this, the case where software Wait is inserted with f(XIN) = 20 MHz (condition ➀) is superior
in the cost performance.
Sample B excution time ratio
Sample A excution time ratio
1.10
1.00
1.00
1.04
1.10
1.00
1.01
0.90
0.90
0.80
0.80
0.70
0.70
0.60
0.60
0.50
0.50
0.40
0.40
0.30
0.30
0.20
0.20
0.10
0.10
0.00
1.00
1.00
1.05
1.00
1.03
0.00
Work area = Internal RAM Work area = External RAM
Work area = Internal RAM Work area = External RAM
: Condition ➁
: Condition ➀
Fig. 16.3.3 Execution time ratio
7721 Group User’s Manual
16–59
APPLICATION
16.3 Comparison of sample program execution rate
MEMORANDUM
16–60
7721 Group User’s Manual
APPENDIX
Appendix 1. Memory assignment of
7721 Group
Appendix 2. Memory assignment in SFR area
Appendix 3. Control registers
Appendix 4. Package outline
Appendix 5. E x a m p l e s o f h a n d l i n g
unused pins
Appendix 6. Machine instructions
Appendix 7. Hexadecimal instruction
code table
Appendix 8. Countermeasure against noise
Appendix 9. 7721 Group Q & A
Appendix 10. Differences between 7721
Group and 7720 Group
Appendix 11. Electrical characteristics
Appendix 12. Standard characteristics
APPENDIX
Appendix 1. Memory assignment of 7721 Group
Appendix 1. Memory assignment of 7721 Group
Microprocessor mode
00000016
00007F16
00008016
M37721S2BFP
M37721S1BFP
SFR area
SFR area
SFR area
00000216
(512 bytes)
Case of internal RAM area
select bit = “0”
00027F16 Internal RAM area
(512 bytes)
Internal RAM area
(512 bytes) (Note 2)
External area
00000916
Case of internal RAM area
select bit = “1”
00047F16
External area
External area
Bank 016
001FC016
SFR area
SFR area
External area
(Note 1)
External area
(Note 1)
001FFF16
00FFFF16
01000016
Bank 116
01FFFF16
FF000016
Bank FF16
FFFFFF16
Fig. 1 Memory assignment (microprocessor mode)
17–2
7721 Group User’s Manual
Notes 1: Interrupt vector table is assigned to
addresses FFCE16 to FFFF16.
Make sure to set a ROM to this
area.
2: For the M37721S1BFP, fix the
internal RAM area select bit to “0.”
APPENDIX
Appendix 2. Memory assignment in SFR area
Appendix 2. Memory assignment in SFR area
Access characteristics
RW : It is possible to read the bit state at reading. The written value becomes valid.
RO : It is possible to read the bit state at reading. The written value becomes invalid.
WO : The written value becomes valid. It is impossible to read the bit state.
: Nothing is assigned. It is impossible to read the bit state. The written value becomes invalid.
State immediately after reset
0 : “0” immediately after reset.
1 : “1” immediately after reset.
? : Undefined immediately after
reset.
0
: Always “0” at reading.
1
: Always “1” at reading.
: Always undefined at reading.
?
0 : “0” immediately after reset. Fix this bit to “0.”
Address Register name
016
116
216
316
416
516
616
716
816
916
Port P4 register
A16
Port P5 register
B16
C16 Port P4 direction register
D16 Port P5 direction register
Port P6 register
E16
Port P7 register
F16
1016 Port P6 direction register
1116 Port P7 direction register
1216
Port P8 register
Port P9 register
1316
1416 Port P8 direction register
1516 Port P9 direction register
Port P10 register
1616
1716
1816 Port P10 direction register
1916
1A16 Pulse output data register 0
1B16
1C16 Pulse output data register 1
1D16
1E16 A-D control register
1F16 A-D sweep pin select register
b7
Access characteristics
State immediately after reset
b0
b0
b7
?
?
?
?
?
?
?
?
?
?
?
RW
0
0
0
0
0
0
?
?
?
1
?
1
?
RW
RW
0
0
0
0
?
0
?
0
?
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
WO
WO
RW
RW
7721 Group User’s Manual
0 0
0016
?
?
0016
0016
?
?
0016
0016
?
?
0016
?
?
?
?
?
0 0
? ?
17–3
APPENDIX
Appendix 2. Memory assignment in SFR area
Access characteristics
RW : It is possible to read the bit state at reading. The written value becomes valid.
RO : It is possible to read the bit state at reading. The written value becomes invalid.
WO : The written value becomes valid. It is impossible to read the bit state.
: Nothing is assigned. It is impossible to read the bit state. The written value becomes invalid.
State immediately after a reset
0 : “0” immediately after reset.
1 : “1” immediately after reset.
? : Undefined immediately after
reset.
0 : Always “0” at reading.
: Always “1” at reading.
: Always undefined at reading.
?
1
0 : “0” immediately after reset. Fix this bit to “0.”
Address
2016
2116
2216
2316
2416
2516
2616
2716
2816
2916
2A16
2B16
2C16
2D16
2E16
2F16
3016
3116
3216
3316
3416
3516
3616
3716
3816
3916
3A16
3B16
3C16
3D16
3E16
3F16
17–4
Register name
b7
Access characteristics
A-D register 0
RO
A-D register 1
RO
A-D register 2
RO
A-D register 3
RO
A-D register 4
RO
A-D register 5
RO
A-D register 6
RO
A-D register 7
RO
UART0 transmit/receive mode register
UART0 transmit buffer register
WO
UART0 transmit/receive control register 0
RO
RO
?
0
?
0
?
0
RO
0
0
0
WO
RW
RW RO RW
?
0
?
0
?
0
RO
0
0
0
RW
WO
WO
UART1 transmit/receive mode register
UART1 baud rate register
UART1 transmit buffer register
RO
UART1 transmit/receive control register 0
UART1 receive buffer register
RW
RW RO RW
RO
UART0 receive buffer register
UART1 transmit/receive control register 1
State immediately after reset
b7
RW
WO
WO
UART0 baud rate register
UART0 transmit/receive control register 1
b0
RO
RO
7721 Group User’s Manual
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
0016
?
?
?
? 1
0 0
?
0 0
0016
?
?
?
? 1
0 0
?
0 0
b0
0
0
0
1
0
0
0
0
?
0
0
0
1
0
0
0
0
?
APPENDIX
Appendix 2. Memory assignment in SFR area
Access characteristics
RW : It is possible to read the bit state at reading. The written value becomes valid.
RO : It is possible to read the bit state at reading. The written value becomes invalid.
WO : The written value becomes valid. It is impossible to read the bit state.
: Nothing is assigned. It is impossible to read the bit state. The written value becomes invalid.
State immediately after reset
0 : “0” immediately after reset.
1 : “1” immediately after reset.
? : Undefined immediately after
reset.
0 : Always “0” at reading.
: Always “1” at reading.
? : Always undefined at reading.
1
00 : “0” immediately after reset. Fix this bit to “0.”
Address
Access characteristics
Register name
Count start register
4016
4116
4216 One-shot start register
4316
Up-down register
4416
4516
4616
Timer A0 register
4716
4816
Timer A1 register
4916
4A16
Timer A2 register
4B16
4C16
Timer A3 register
4D16
4E16
Timer A4 register
4F16
5016
Timer B0 register
5116
5216
Timer B1 register
5316
5416
Timer B2 register
5516
5616 Timer A0 mode register
5716 Timer A1 mode register
5816 Timer A2 mode register
5916 Timer A3 mode register
5A16 Timer A4 mode register
5B16 Timer B0 mode register
5C16 Timer B1 mode register
5D16 Timer B2 mode register
5E16 Processor mode register 0
5F16 Processor mode register 1
State immediately after reset
b0
b7
b0
b7
0016
?
0 0
?
0 0
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
0 0
0 0
0016
0016
0016
? 0
? 0
? 0
0 0
RW
?
WO
WO
RW
RW
RW
RW
RW
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
(Note
3)
(Note
3)
(Note
3)
RW
RW
RW
RW
WO RW
RW
RW
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
?
?
?
0
?
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
?
(Note
4)
Notes 1: The access characteristics at addresses 4A16 to 4F16 vary according to Timer A’s operating
mode. (Refer to “CHAPTER 8. TIMER A.”)
2: The access characteristics at addresses 5016 to 5316 vary according to Timer B’s operating
mode. (Refer to “CHAPTER 9. TIMER B.”)
3: The access characteristics for bit 5 at addresses 5B16 and 5C16 vary according to Timer B’s
operating mode. Bit 5 at address 5D16 is invalid. (Refer to “CHAPTER 9. TIMER B.”)
4: Bit 1 at address 5F16 becomes “0” immediately after reset. For the M37721S1BFP, fix this bit to
“0.”
7721 Group User’s Manual
17–5
APPENDIX
Appendix 2. Memory assignment in SFR area
Access characteristics
RW : It is possible to read the bit state at reading. The written value becomes valid.
R O : It is possible to read the bit state at reading. The written value becomes invalid.
WO : The written value becomes valid. It is impossible to read the bit state.
: Nothing is assigned. It is impossible to read the bit state. The written value becomes invalid.
State immediately after reset
0 : “0” immediately after reset.
1 : “1” immediately after reset.
? : Undefined immediately after
reset.
0 : Always “0” at reading.
1 : Always “1” at reading.
? : Always undefined at reading.
00 : “0” immediately after reset. Fix this bit to “0.”
Address
Register name
b7
Access characteristics
Watchdog timer register
6016
6116 Watchdog timer frequency select register
6216
Real-time output control register
6316
DRAM control register
6416
6516
Refresh timer
6616
6716
DM AC control register L
6816
DM
AC control register H
6916
6A16
6B16
DMA0 interrupt control register
6C16
DMA1 interrupt control register
6D16
DMA2 interrupt control register
6E16
DMA3 interrupt control register
6F16
7016 A-D conversion interrupt control register
7116 UART0 transmit interrupt control register
7216 UART0 receive interrupt control register
7316 UART1 transmit interrupt control register
7416 UART1 receive interrupt control register
Timer A0 interrupt control register
7516
Timer A1 interrupt control register
7616
Timer A2 interrupt control register
7716
Timer A3 interrupt control register
7816
Timer A4 interrupt control register
7916
Timer B0 interrupt control register
7A16
Timer B1 interrupt control register
7B16
Timer B2 interrupt control register
7C16
INT0 interrupt control register
7D16
INT1 interrupt control register
7E16
INT
2 interrupt control register
7F16
b0
State immediately after reset
b7
(Note 5)
RW
RW
RW
RW
0 0
RW
0 0
0
0
WO
RW
(Note 7)
RW
WO
0
0
0
0
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
0
0
?
?
?
0
0
0
?(Note 6)
?
0 0
?
0 0
?
?
?
0 ?
0 0
?
?
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 0
0 0
0 0
b0
0
0
0
0
0
0
0
?
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Notes 5: By writing dummy data to address 6016, the value “FFF16” is set to the watchdog timer.
The dummy data is not retained anywhere.
6: The value “FFF16” is set to the watchdog timer. (Refer to “CHAPTER 15. WATCHDOG TIMER.”)
7: It is possible to read the bit state at reading. When writing “0” to this bit, this bit becomes “0.”
But when writing “1” to this bit, this bit does not change.
17–6
7721 Group User’s Manual
APPENDIX
Appendix 2. Memory assignment in SFR area
Access characteristics
RW : It is possible to read the bit state at reading. The written value becomes valid.
RO : It is possible to read the bit state at reading. The written value becomes invalid.
WO : The written value becomes valid. It is impossible to read the bit state.
: Nothing is assigned. It is impossible to read the bit state. The written value becomes invalid.
State immediately after reset
0 : “0” immediately after reset.
1 : “1” immediately after reset.
? : Undefined immediately after
reset.
0 : Always “0” at reading.
1 : Always “1” at reading.
: Always undefined at reading.
?
00 : “0” immediately after reset. Fix this bit to “0.”
Address
1FC016
1FC116
1FC216
1FC316
1FC416
1FC516
1FC616
1FC716
1FC816
1FC916
1FCA16
1FCB16
1FCC16
1FCD16
1FCE16
1FCF16
1FD016
1FD116
1FD216
1FD316
1FD416
1FD516
1FD616
1FD716
1FD816
1FD916
1FDA16
1FDB16
1FDC16
1FDD16
1FDE16
1FDF16
Register name
Source address register 0
b7
Access characteristics
RW
RW
RW
Transfer counter register 0
RW
RW
RW
DMA0 mode register L
RW
Source address register 1
RW
RW
RW
Destination address register 1
RW
RW
RW
Transfer counter register 1
RW
RW
RW
DMA1 mode register H
DMA1 control register
b0
?
?
?
?
?
?
?
?
?
?
?
?
RW
RW
DMA0 control register
DMA1 mode register L
State immediately after reset
b7
RW
RW
RW
Destination address register 0
DMA0 mode register H
b0
0
0
?
0
0
?
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
?
?
?
?
?
?
?
?
?
?
?
?
?
RW
RW
RW
0
0
?
0
0
?
0
0
0
0
0
0
?
7721 Group User’s Manual
17–7
APPENDIX
Appendix 2. Memory assignment in SFR area
Access characteristics
RW : It is possible to read the bit state at reading. The written value becomes valid.
RO : It is possible to read the bit state at reading. The written value becomes invalid.
WO : The written value becomes valid. It is impossible to read the bit state.
: Nothing is assigned. It is impossible to read the bit state. The written value becomes invalid.
State immediately after reset
0 : “0” immediately after reset.
1 : “1” immediately after reset.
? : Undefined immediately after
reset.
0
: Always “0” at reading.
1
: Always “1” at reading.
: Always undefined at reading.
?
0 : “0” immediately after reset. Fix this bit to “0.”
Address
1FE016
1FE116
1FE216
1FE316
1FE416
1FE516
1FE616
1FE716
1FE816
1FE916
1FEA16
1FEB16
1FEC16
1FED16
1FEE16
1FEF16
1FF016
1FF116
1FF216
1FF316
1FF416
1FF516
1FF616
1FF716
1FF816
1FF916
1FFA16
1FFB16
1FFC16
1FFD16
1FFE16
1FFF16
17–8
Register name
Source address register 2
Destination address register 2
Transfer counter register 2
DMA2 mode register L
DMA2 mode register H
b7
Access characteristics
RW
RW
RW
RW
RW
RW
Source address register 3
Destination address register 3
RW
RW
RW
Transfer counter register 3
RW
RW
RW
DMA3 control register
b0
?
?
?
?
?
?
?
?
?
?
?
?
RW
RW
RW
RW
RW
RW
DMA3 mode register H
State immediately after reset
b7
RW
RW
RW
DMA2 control register
DMA3 mode register L
b0
0
0
?
0
0
?
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
?
?
?
?
?
?
?
?
?
?
?
?
?
RW
RW
RW
0
0
?
0
0
?
0
0
0
0
0
0
?
7721 Group User’s Manual
APPENDIX
Appendix 3. Control registers
Appendix 3. Control registers
The control registers allocated in the SFR area are shown on the following pages.
Below is the structure diagram for all registers.
✽1
b7
b6
b5
b4
b3
b2
b1
b0
XXX register (Address XX16)
✕ 0
Bit
✽2
Bit name
Functions
✽3
At reset
RW
0
RW
Undefined
WO
0
RO
0
... select bit
0 : ...
1 : ...
1
... select bit
0 : ...
1 : ...
The value is “0” at reading.
2
... flag
0 : ...
1 : ...
3
Fix this bit to “0.”
0
RW
4
This bit is invalid in ... mode.
0
RW
Undefined
–
7 to 5 Nothing is assigned.
✽4
✽1
Blank
0
1
✕
: Set to “0” or “1” according to the usage.
: Set to “0” at writing.
: Set to “1” at writing.
: Invalid depending on the mode or state. It may be “0” or “1.”
: Nothing is assigned.
✽2
0
1
Undefined
: “0” immediately after reset.
: “1” immediately after reset.
: Undefined immediately after reset.
✽3
RW
RO
WO
—
: It is possible to read the bit state at reading. The written value becomes valid.
: It is possible to read the bit state at reading. The written value becomes invalid. Accordingly, the written
value may be “0” or “1.”
: The written value becomes valid. It is impossible to read the bit state. The value is undefined at reading.
However, when [“0” is at reading”] is indicated in the “Function” or “Note” column, the bit is always “0” at
reading. (See ✽4 above.)
: It is impossible to read the bit state. The value is undefined at reading.
However, when [“0” is at reading”] is indicated in the “Function” or “Note” column, the bit is always “0” at
reading. (See ✽4 above.)
The written value becomes invalid. Accordingly, the written value may be “0” or “1.”
7721 Group User’s Manual
17–9
APPENDIX
Appendix 3. Control registers
Port Pi register
b7
b6
b5
b4
b3
b2
b1
b0
Port Pi register (i = 4 to 10)
(Addresses A16, B16, E16, F16, 1216, 1316, 1616)
Bit
Bit name
Functions
At reset
RW
Data is input from or output to a pin
by reading from or writing to the
corresponding bit.
Undefined
RW
Undefined
RW
Undefined
RW
Undefined
RW
0
Port Pi0’s pin
1
Port Pi1’s pin
2
Port Pi2’s pin
3
Port Pi3’s pin
4
Port Pi4’s pin
Undefined
RW
5
Port Pi5’s pin
Undefined
RW
6
Port Pi6’s pin
Undefined
RW
7
Port Pi7’s pin
Undefined
RW
0 : “L” level
1 : “H” level
Note: For bits 0 to 2 of the port P4 register, nothing is assigned and these bits are fixed to “0” at reading.
Port Pi direction register
b7
b6
b5
b4
b3
b2
b1
b0
Port Pi direction register (i = 4 to 10)
(Addresses C16, D16, 1016, 1116, 1416, 1516, 1816)
Bit
Bit name
Functions
At reset
RW
0
RW
0
RW
0
RW
0
Port Pi0 direction bit
1
Port Pi1 direction bit
2
Port Pi2 direction bit
3
Port Pi3 direction bit
0
RW
4
Port Pi4 direction bit
0
RW
5
Port Pi5 direction bit
0
RW
6
Port Pi6 direction bit
0
RW
7
Port Pi7 direction bit
0
RW
0 : Input mode
(The port functions as an input port)
1 : Output mode
(The port functions as an output port)
Note: For bits 0 to 2 of the port P4 direction register, nothing is assigned and these bits are fixed to “0” at
reading.
17–10
7721 Group User’s Manual
APPENDIX
Appendix 3. Control registers
Pulse output data register 0
b7
b6
b5
b4
b3
b2
b1
b0
Pulse output data register 0 (Address 1A16)
Bit
Bit name
Functions
0 : “L” level output
1 : “H” level output
At reset
RW
Undefined
WO
Undefined
WO
0
RTP00 pulse output data bit
1
RTP01 pulse output data bit
2
RTP02 pulse output data bit
(Valid in pulse mode 0)
Undefined
WO
3
RTP03 pulse output data bit
(Valid in pulse mode 0)
Undefined
WO
Nothing is assigned.
Undefined
7 to 4
Note: Use the LDM or STA instruction for writing to this register
Pulse output data register 1
b7
b6
b5
b4
b3
b2
b1
b0
Pulse output data register 1 (Address 1C16)
Bit
Bit name
0, 1
Nothing is assigned.
2
RTP02 pulse output data bit
(Valid in pulse mode 1)
3
Functions
At reset
RW
Undefined
0 : “L” level output
1 : “H” level output
Undefined
WO
RTP03 pulse output data bit
(Valid in pulse mode 1)
Undefined
WO
4
RTP10 pulse output data bit
Undefined
WO
5
RTP11 pulse output data bit
Undefined
WO
6
RTP12 pulse output data bit
Undefined
WO
7
RTP13 pulse output data bit
Undefined
WO
Note: Use the LDM or STA instruction for writing to this register.
7721 Group User’s Manual
17–11
APPENDIX
Appendix 3. Control registers
A-D control register
b7
b6
b5
b4
b3
b2
b1
b0
A-D control register (Address 1E16)
0
Functions
Bit name
Bit
b2 b1 b0
Analog input select bits
(Valid in one-shot and repeat
modes) (Note 1)
0 0 0 : AN0 selected
0 0 1 : AN1 selected
0 1 0 : AN2 selected
0 1 1 : AN3 selected
1 0 0 : AN4 selected
1 0 1 : AN5 selected
1 1 0 : AN6 selected
1 1 1 : AN7 selected (Note 2)
1
2
3
6
7
RW
Undefined
RW
Undefined
RW
Undefined
RW
0
RW
0
RW
0
RW
b4 b3
A-D operation mode select bit
0 0 : One-shot mode
0 1 : Repeat mode
1 0 : Single sweep mode
1 1 : Repeat sweep mode
0 : Internal trigger
1 : External trigger
4
5
At reset
Trigger select bit
A-D conversion start bit
0 : Stop A-D conversion
1 : Start A-D conversion
0
RW
A-D conversion frequency
( AD) select bit
0 : f2 divided by 4
1 : f2 divided by 2
0
RW
Notes 1: These bits are invalid in the single sweep and repeat sweep mode. (They may be
either “0” or “1.”)
2: When selecting an external trigger, the AN7 pin cannot be used as an analog input
pin.
3: Writing to each bit (except bit 6) of the A-D control register must be performed while
the A-D converter halts.
A-D sweep pin select register
b7
b6
b5
b4
b3
b2
b1
b0
A-D sweep pin select register (Address 1F16)
Bit
0
Functions
Bit name
A-D sweep pin select bits
(Valid in single sweep and repeat
sweep modes) (Note 1)
1
b1 b0
0 0 : AN0, AN1 (2 pins)
0 1 : AN0 to AN3 (4 pins)
1 0 : AN0 to AN5 (6 pins)
1 1 : AN0 to AN7 (8 pins) (Note 2)
7 to 2 Nothing is assigned.
At reset
RW
1
RW
1
RW
Undefined
–
Notes 1: These bits are invalid in the one-shot and repeat modes. (They may be either “0” or “1.”)
2: When selecting an external trigger, the AN7 pin cannot be used as an analog input pin.
3: Writing to each bit of the A-D sweep pin select register must be performed while the
A-D converter halts.
A-D register i
b7
b0
A-D register i (i = 0 to 7) (Addresses 2016, 2216, 2416,
2616, 2816, 2A16, 2C16, 2E16)
Bit
Functions
7 to 0 Reads an A-D conversion result.
17–12
7721 Group User’s Manual
At reset
RW
Undefined
RO
APPENDIX
Appendix 3. Control registers
UARTi transmit/receive mode register
b7
b6
b5
b4
b3
b2
b1
b0
UART0 transmit/receive mode register (Address 3016)
UART1 transmit/receive mode register (Address 3816)
Bit
0
Functions
At reset
RW
0 0 0 : Serial I/O disabled
(P8 functions as a programmable
I/O port.)
0 0 1 : Clock synchronous serial I/O
mode
0 1 0 : Do not select.
0 1 1 : Do not select.
1 0 0 : UART mode
(Transfer data length = 7 bits)
1 0 1 : UART mode
(Transfer data length = 8 bits)
1 1 0 : UART mode
(Transfer data length = 9 bits)
1 1 1 : Do not select.
0
RW
0
RW
0
RW
Bit name
Serial I/O mode select bits
1
2
b2 b1 b0
3
Internal/External clock select bit
0 : Internal clock
1 : External clock
0
RW
4
Stop bit length select bit
(Valid in UART mode) (Note)
0 : One stop bit
1 : Two stop bits
0
RW
5
Odd/Even parity select bit
(Valid in UART mode when
parity enable bit is “1”) (Note)
0 : Odd parity
1 : Even parity
0
RW
6
Parity enable bit
(Valid in UART mode) (Note)
0 : Parity disabled
1 : Parity enabled
0
RW
7
Sleep select bit
(Valid in UART mode) (Note)
0 : Sleep mode terminated (Invalid)
1 : Sleep mode selected
0
RW
Note: Bits 4 to 6 are invalid in the clock synchronous serial I/O mode. (They may be either “0”
or “1.”) Additionally, fix bit 7 to “0.”
UARTi baud rate register
b7
b0
UART0 baud rate register (Address 3116)
UART1 baud rate register (Address 3916)
Bit
Functions
7 to 0 Can be set to “0016” to “FF16.”
Assuming that the set value = n, BRGi
divides the count source frequency by (n + 1).
At reset
RW
Undefined
WO
Note: Writing to this register must be performed while the transmission/reception halts.
Use the LDM or STA instruction for writing to this register.
7721 Group User’s Manual
17–13
APPENDIX
Appendix 3. Control registers
UARTi transmit buffer register
(b15)
(b8)
b7
b0
b7
b0
UART0 transmit buffer register (Addresses 3316, 3216)
UART1 transmit buffer register (Addresses 3B16, 3A16)
Functions
Bit
At reset
RW
8 to 0 Transmit data is set.
Undefined
WO
15 to 9 Nothing is assigned.
Undefined
–
Note: Use the LDM or STA instruction for writing to this register.
UARTi transmit/receive control register 0
b7
b6
b5
b4
b3
b2
b1
b0
UART0 transmit/receive control register 0 (Address 3416)
UART1 transmit/receive control register 0 (Address 3C16)
Bit
0
BRG count source select bits
1
b1 b0
0 0 : f2
0 1 : f16
1 0 : f64
1 1 : f512
At reset
RW
0
RW
0
RW
2
CTS/RTS select bit
0 : CTS function selected
1 : RTS function selected
0
RW
3
Transmit register empty flag
0 : Data present in transmit register
(During transmission)
1 : No data present in transmit register
(Transmission completed)
1
RO
Undefined
–
7 to 4
17–14
Functions
Bit name
Nothing is assigned.
7721 Group User’s Manual
APPENDIX
Appendix 3. Control registers
UARTi transmit/receive control register 1
b7
b6
b5
b4
b3
b2
b1
b0
UART0 transmit/receive control register 1 (Address 3516)
UART1 transmit/receive control register 1 (Address 3D16)
Functions
Bit name
Bit
At reset
RW
0
Transmit enable bit
0 : Transmission disabled
1 : Transmission enabled
0
RW
1
Transmit buffer empty flag
0 : Data present in transmit buffer
register
1 : No data present in transmit
buffer register
1
RO
2
Receive enable bit
0 : Reception disabled
1 : Reception enabled
0
RW
3
Receive complete flag
0 : No data present in receive
buffer register
1 : Data present in receive buffer
register
0
RO
4
Overrun error flag
(Note 1) 0 : No overrun error
1 : Overrun error detected
0
RO
5
Framing error flag (Notes 1, 2) 0 : No framing error
1 : Framing error detected
(Valid in UART mode)
0
RO
6
(Notes 1, 2) 0 : No parity error
Parity error flag
(Valid in UART mode)
1 : Parity error detected
0
RO
7
(Notes 1, 2) 0 : No error
Error sum flag
1 : Error detected
(Valid in UART mode)
0
RO
Notes 1: Bit 4 is cleared to “0” when the receive enable bit is cleared to “0” or when the serial
I/O mode select bits (bits 2 to 0 at addresses 3016, 3816) are cleared to “0002.”
Bits 5 and 6 are cleared to “0” when one of the following is performed:
•Clearing the receive enable bit to “0”
•Reading the low-order byte of the UARTi receive buffer register (addresses 3616, 3E16)
out
•Clearing the serial I/O mode select bits (bits 2 to 0 at addresses 3016, 3816) to “0002”
Bit 7 is cleared to “0” when all of bits 4 to 6 become “0.”
2: Bits 5 to 7 are invalid in the clock synchronous serial I/O mode.
UARTi receive buffer register
(b15)
(b8)
b7
b0
b7
b0
UART0 receive buffer register (Addresses 3716, 3616)
UART1 receive buffer register (Addresses 3F16, 3E16)
Bit
Functions
8 to 0 Receive data is read out from here.
15 to 9 Nothing is assigned.
The value is “0” at reading.
7721 Group User’s Manual
At reset
RW
Undefined
RO
0
–
17–15
APPENDIX
Appendix 3. Control registers
Count start register
b7
b6
b5
b4
b3
b2
b1
b0
Count start register (Address 4016)
Bit
Bit name
Functions
0 : Stop counting
1 : Start counting
At reset
RW
0
RW
0
Timer A0 count start bit
1
Timer A1 count start bit
0
RW
2
Timer A2 count start bit
0
RW
3
Timer A3 count start bit
0
RW
4
Timer A4 count start bit
0
RW
5
Timer B0 count start bit
0
RW
6
Timer B1 count start bit
0
RW
7
Timer B2 count start bit
0
RW
At reset
RW
0
WO
0
WO
0
WO
0
WO
0
WO
Undefined
–
One-shot start register
b7
b6
b5
b4
b3
b2
b1
b0
0 0
One-shot start register (Address 4216)
Bit
0
Bit name
Functions
Fix these bits to “0.” The value is “0” at reading.
1
2
Timer A2 one-shot start bit
3
Timer A3 one-shot start bit
4
Timer A4 one-shot start bit
1 : Start outputting one-shot pulse
(valid when internal trigger is
selected.)
The value is “0” at reading.
7 to 5 Nothing is assigned.
17–16
7721 Group User’s Manual
APPENDIX
Appendix 3. Control registers
Up-down register
b7
b6
b5
b4
b3
b2
b1
b0
0 0
Up-down register (Address 4416)
Bit
0
Functions
Bit name
Fix these bits to “0.”
1
0 : Countdown
1 : Countup
This function is valid when the contents of
the up-down register is selected as the updown switching factor.
2
Timer A2 up-down bit
3
Timer A3 up-down bit
4
Timer A4 up-down bit
5
Timer A2 two-phase pulse signal 0 : Two-phase pulse signal
processing function disabled
processing select bit
(Note)
1 : Two-phase pulse signal
processing function enabled
Timer A3 two-phase pulse signal
6
processing select bit
7
At reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
WO
0
WO
0
WO
(Note)
When not using the two-phase pulse
signal processing function, set the bit
Timer A4 two-phase pulse signal
to “0.”
processing select bit (Note)
The value is “0” at reading.
Note: Use the LDM or STA instruction for writing to bits 5 to 7.
7721 Group User’s Manual
17–17
APPENDIX
Appendix 3. Control registers
Timer Ai register
(b15)
b7
(b8)
b0 b7
b0
Timer A0 register (Addresses 4716, 4616)
Timer A1 register (Addresses 4916, 4816)
Timer A2 register (Addresses 4B16, 4A16)
Timer A3 register (Addresses 4D16, 4C16)
Timer A4 register (Addresses 4F16, 4E16)
Bit
Functions
15 to 0 These bits have different functions according
to the operating mode.
At reset
RW
Undefined
RW
(Note 1)
Notes 1: The access characteristics for the timer A2 register, timer A3
register, and timer A4 register differ according to Timer A’s
operating mode.
2: Read from or write to this register in a unit of 16 bits.
Timer Ai mode register
b7
b6
b5
b4
b3
b2
b1
b0
Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16)
Bit
Functions
At reset
RW
0
RW
0
RW
0
RW
3
0
RW
4
0
RW
5
0
RW
6
0
RW
7
0
RW
0
1
2
17–18
Bit name
Operating mode select bits
b1 b0
0 0 : Timer mode
0 1 : Event counter mode
1 0 : One-shot pulse mode
1 1 : Pulse width modulation (PWM) mode
These bits have different functions according to the operating mode.
7721 Group User’s Manual
APPENDIX
Appendix 3. Control registers
Timer Mode
(b15)
b7
(b8)
b0 b7
Timer A0 register (Addresses 4716, 4616)
Timer A1 register (Addresses 4916, 4816)
Timer A2 register (Addresses 4B16, 4A16)
Timer A3 register (Addresses 4D16, 4C16)
Timer A4 register (Addresses 4F16, 4E16)
b0
Bit
Functions
15 to 0 These bits can be set to “000016” to “FFFF16.”
Assuming that the set value = n, the counter
divides the count source frequency by (n + 1).
When reading, the register indicates the
counter value.
At reset
RW
Undefined
RW
Note: Read from or write to this register in a unit of 16 bits.
b7
b6
b5
b4
b3
b2
b1
b0
0 0 0 0 0 0
Timer A0 mode register (Address 5616)
Timer A1 mode register (Address 5716)
At reset
RW
0
RW
1
0
RW
2
0
RW
3
0
RW
4
0
RW
Bit
0
Bit name
Functions
Fix these bits to “0.”
5
6
Count source select bits
b7 b6
0 0 : f2
0 1 : f16
1 0 : f64
1 1 : f512
7
b7 b6 b5
0
b4 b3 b2
0
RW
0
RW
0
RW
b1 b0
0 0
Timer Aj mode register (j = 2 to 4) (Addresses 5816 to 5A16)
Bit
0
Bit name
Functions
Operating mode select bits
b1 b0
0 0 : Timer mode
1
At reset
RW
0
RW
0
RW
2
Pulse output function select bit
0 : No pulse output
(TAjOUT pin functions as a programmable
I/O port.)
1 : Pulse output
(TAjOUT pin functions as a pulse output
pin.)
0
RW
3
Gate function select bits
b4 b3
0
RW
0
RW
0
RW
0
RW
0
RW
4
5
Fix this bit to “0” in timer mode.
6
Count source select bits
7
0 0 : No gate function
0 1 : (TAjIN pin functions as a programmable I/O port.)
1 0 : Counter counts only while TAj IN
pin’s input signal is at “L” level.
1 1 : Counter counts only while TAjIN
pin’s input signal is at “H” level.
b7 b6
0 0 : f2
0 1 : f16
1 0 : f64
1 1 : f512
7721 Group User’s Manual
17–19
APPENDIX
Appendix 3. Control registers
Event counter mode
(b15)
b7
(b8)
b0 b7
b0
Timer A2 register (Addresses 4B16, 4A16)
Timer A3 register (Addresses 4D16, 4C16)
Timer A4 register (Addresses 4F16, 4E16)
Bit
Functions
15 to 0 These bits can be set to “000016” to “FFFF16.”
Assuming that the set value = n, the counter
divides the count source frequency by (n + 1)
during countdown, or by (FFFF16 – n + 1)
during countup.
When reading, the register indicates the
counter value.
At reset
RW
Undefined
RW
Note: Read from or write to this register in a unit of 16 bits.
b7
b6
b5
✕ ✕ 0
b4
b3
b2
b1
b0
0 1
Timer Aj mode register (j = 2 to 4) (Addresses 5816 to 5A16)
Bit
0
Bit name
Operating mode select bits
Functions
b1 b0
0 1 : Event counter mode
1
RW
0
RW
0
RW
2
Pulse output function select bit
0 : No pulse output (TAjOUT pin functions
as a programmable I/O port.)
1 : Pulse output (TAjOUT pin functions
as a pulse output pin.)
0
RW
3
Count polarity select bit
0 : Counts at falling edge of external signal
1 : Counts at rising edge of external signal
0
RW
4
Up-down switching factor select
bit
0 : Contents of up-down register
1 : Input signal to TAjOUT pin
0
RW
5
Fix this bit to “0” in event counter mode.
0
RW
6
These bits are invalid in event counter mode.
0
RW
0
RW
7
17–20
At reset
7721 Group User’s Manual
APPENDIX
Appendix 3. Control registers
One-shot pulse mode
(b15)
b7
(b8)
b0 b7
b0
Timer A2 register (Addresses 4B16, 4A16)
Timer A3 register (Addresses 4D16, 4C16)
Timer A4 register (Addresses 4F16, 4E16)
Bit
Functions
15 to 0 These bits can be set to “000116” to “FFFF16.”
Assuming that the set value = n, the “H” level
width of the one-shot pulse output from the
TAjOUT pin is expressed as follows : n
fi.
At reset
RW
Undefined
WO
fi: Frequency of count source (f2 , f16, f64, or f512)
Note: Use the LDM or STA instruction for writing to this register.
Read from or write to this register in a unit of 16 bits.
b7
b6
b5
0
b4
b3
b2
b1
b0
1 1 0
Timer Aj mode register (j = 2 to 4) (Addresses 5816 to 5A16)
Bit
0
Bit name
Operating mode select bits
Functions
b1 b0
1 0 : One-shot pulse mode
1
2
3
Fix this bit to “1” in one-shot pulse mode.
Trigger select bits
4
5
6
7
b4 b3
0 0 : Writing “1” to one-shot start register
0 1 : (TAjIN pin functions as a programmable I/O port.)
1 0 : Falling edge of TAjIN pin’s input signal
1 1 : Rising edge of TAjIN pin’s input signal
Fix this bit to “0” in one-shot pulse mode.
Count source select bits
b7 b6
0 0 : f2
0 1 : f16
1 0 : f64
1 1 : f512
7721 Group User’s Manual
At reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
17–21
APPENDIX
Appendix 3. Control registers
Pulse width modulation (PWM) mode
<When operating as a 16-bit pulse width modulator>
(b15)
b7
(b8)
b0 b7
b0
Timer A2 register (Addresses 4B16, 4A16)
Timer A3 register (Addresses 4D16, 4C16)
Timer A4 register (Addresses 4F16, 4E16)
RW
At reset
Functions
Bit
15 to 0 These bits can be set to “000016” to “FFFE16.” Undefined WO
Assuming that the set value = n, the “H” level
width of the PWM pulse output from the
n
TAjOUT pin is expressed as follows:
fi
16 – 1
n
(PWM pulse period =
)
fi
fi: Frequency of count source (f2, f16, f64, or f512)
Note: Use the LDM or STA instruction for writing to this register.
Read from or write to this register in a unit of 16 bits.
<When operating as an 8-bit pulse width modulator>
(b15)
b7
(b8)
b0 b7
b0
Timer A2 register (Addresses 4B16, 4A16)
Timer A3 register (Addresses 4D16, 4C16)
Timer A4 register (Addresses 4F16, 4E16)
Functions
Bit
At reset
RW
7 to 0 These bits can be set to “0016” to “FF16.”
Assuming that the set value = m, PWM
pulse’s period output from the TAjOUT pin is
8
expressed as follows: (m + 1)(2 – 1)
fi
Undefined
WO
15 to 8 These bits can be set to “0016” to “FE16.”
Assuming that the set value = n, the “H” level
width of the PWM pulse output from the
TAjOUT pin is expressed as follows:
n(m + 1)
Undefined
WO
fi
fi: Frequency of count source (f2, f16, f64, or f512)
Note: Use the LDM or STA instruction for writing to this register.
Read from or write to this register in a unit of 16 bits.
b7
b6
b5
b4
b3
b2
b1
b0
1 1 1
Timer Aj mode register (j = 2 to 4) (Addresses 5816 to 5A16)
Bit
0
Functions
Bit name
Operating mode select bits
b1 b0
1 1 : PWM mode
1
2
3
Fix this bit to “1” in PWM mode.
b4 b3
Trigger select bits
0 0 : Writing “1” to count start register
0 1 : (TAj IN pin functions as a programmable I/O port.)
1 0 : Falling edge of TAjIN pin’s input signal
1 1 : Rising edge of TAjIN pin’s input signal
4
5
16/8-bit PWM mode select bit
0 : 16-bit pulse width modulator
1 : 8-bit pulse width modulator
6
Count source select bits
b7 b6
7
17–22
0 0 : f2
0 1 : f16
1 0 : f64
1 1 : f512
7721 Group User’s Manual
At reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
APPENDIX
Appendix 3. Control registers
Timer Bi register
(b15)
b7
(b8)
b0 b7
b0
Timer B0 register (Addresses 5116, 5016)
Timer B1 register (Addresses 5316, 5216)
Timer B2 register (Addresses 5516, 5416)
Bit
Functions
RW
At reset
15 to 0 These bits have different functions according Undefined RW
to the operating mode.
(Note 1)
Notes 1: The access characteristics for the timer B0 register and timer
B1 register differ according to Timer B’s operating mode.
2: Read from or write to this register in a unit of 16 bits.
Timer Bi mode register
b7 b6
b5 b4
b3 b2 b1 b0
Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16)
Bit
0
Bit name
Operating mode select bits
1
2
Functions
b1 b0
0 0 : Timer mode
0 1 : Event counter mode
1 0 : Pulse period/Pulse width
measurement mode
1 1 : Do not select.
These bits have different functions according to the operating mode.
3
At reset
RW
0
RW
0
RW
0
RW
0
RW
4
Nothing is assigned.
Undefined
–
5
These bits have different functions according to the operating mode.
Undefined
RO
(Note)
6
0
RW
7
0
RW
Note: Bit 5 is invalid in the timer and event counter modes; its value is undefined at reading.
7721 Group User’s Manual
17–23
APPENDIX
Appendix 3. Control registers
Timer mode
(b15)
b7
(b8)
b0 b7
b0
Timer B0 register (Addresses 5116, 5016)
Timer B1 register (Addresses 5316, 5216)
Timer B2 register (Addresses 5516, 5416)
At reset
RW
15 to 0 These bits can be set to “000016” to “FFFF16.” Undefined
Assuming that the set value = n, the counter
divides the count source frequency by (n + 1).
When reading, the register indicates the
counter value.
RW
Bit
Functions
Note: Read from or write to this register in a unit of 16 bits.
b7
b6
b5
✕
b4
b3
b2
b1
b0
✕ ✕ 0 0
Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16)
Bit
0
Bit name
Operating mode select bits
Functions
b1 b0
0 0 : Timer mode
1
2
These bits are invalid in timer mode.
3
RW
0
RW
0
RW
0
RW
0
RW
4
Nothing is assigned.
Undefined
–
5
This bit is invalid in timer mode; its value is undefined at reading.
Undefined
RO
6
Count source select bits
0
RW
0
RW
7
17–24
At reset
b7 b6
0 0 : f2
0 1 : f16
1 0 : f64
1 1 : f512
7721 Group User’s Manual
APPENDIX
Appendix 3. Control registers
Event counter mode
(b15)
b7
(b8)
b0 b7
b0
Timer B0 register (Addresses 5116, 5016)
Timer B1 register (Addresses 5316, 5216)
Bit
Functions
15 to 0 These bits can be set to “000016” to “FFFF16.”
Assuming that the set value = n, the counter
divides the count source frequency by (n + 1).
When reading, the register indicates the
counter value.
At reset
RW
Undefined
RW
Note: Read from or write to this register in a unit of 16 bits.
b7
b6
b5
✕ ✕ ✕
b4
b3
b2
b1
b0
0 1
Timer Bj mode register (j = 0, 1) (Addresses 5B16, 5C16)
Bit
0
Bit name
Operating mode select bits
Functions
b1 b0
0 1 : Event counter mode
1
2
Count polarity select bits
b3 b2
0 0 : Count at falling edge of external signal
0 1 : Count at rising edge of external signal
1 0 : Counts at both falling and rising edges
of external signal
1 1 : Do not select.
3
At reset
RW
0
RW
0
RW
0
RW
0
RW
4
Nothing is assigned.
Undefined
—
5
This bit is invalid in event counter mode; its value is undefined at
reading.
Undefined
RO
6
These bits are invalid in event counter mode.
0
RW
0
RW
7
7721 Group User’s Manual
17–25
APPENDIX
Appendix 3. Control registers
Pulse period/pulse width measurement mode
(b15)
b7
(b8)
b0 b7
b0
Timer B0 register (Addresses 5116, 5016)
Timer B1 register (Addresses 5316, 5216)
Functions
Bit
15 to 0 The measurement result of pulse period or
pulse width is read out.
At reset
RW
Undefined
RO
At reset
RW
0
RW
0
RW
0
RW
0
RW
Undefined
–
Undefined
RO
0
RW
0
RW
Note: Read from this register in a unit of 16 bits.
b7
b6
b5
b4
b3
b2
b1
b0
1 0
Timer Bj mode register (j = 0, 1) (Addresses 5B16, 5C16)
Bit
0
Bit name
Operating mode select bits
1
2
Measurement mode select bits
3
Functions
b1 b0
1 0 : Pulse period/Pulse width
measurement mode
b3 b2
0 0 : Pulse period measurement
(Interval between falling edges
of measurement pulse)
0 1 : Pulse period measurement
(Interval between rising edges
of measurement pulse)
1 0 : Pulse width measurement
(Interval from a falling edge to a rising
edge, and from a rising edge to a
falling edge of measurement pulse)
1 1 : Do not select.
4
Nothing is assigned.
5
Timer Bj overflow flag
(Note)
0 : No overflow
1 : Overflowed
6
Count source select bits
b7 b6
7
0 0 : f2
0 1 : f16
1 0 : f64
1 1 : f512
Note: The timer Bj overflow flag is cleared to “0” at the next count timing of the count source
when a value is written to the timer Bj mode register with the count start bit = “1.”
17–26
7721 Group User’s Manual
APPENDIX
Appendix 3. Control registers
Processor mode register 0
b7
b6
b5
b4
b3
b2
b1
0
b0
0
Processor mode register 0 (Address 5E16)
Bit
Bit name
Functions
At reset
RW
0
Fix this bit to “0.”
0
RW
1
Nothing is assigned.
The value is “1” at reading.
1
–
2
Wait bit
0 : Software Wait is inserted when
accessing external area.
1 : No software Wait is inserted
when accessing external area.
0
RW
3
Software reset bit
The microcomputer is reset by
writing “1” to this bit. The value is
“0” at reading.
0
WO
4
Interrupt priority detection time
select bits
0
RW
0
RW
0
RW
0
RW
5
6
Fix this bit to “0.”
7
Stack bank select bit
b5 b4
0 0 : 7 cycles of
0 1 : 4 cycles of
1 0 : 2 cycles of
1 1 : Do not select.
0 : Bank 016
1 : Bank FF16
Processor mode register 1
b7
b6
b5
b4
b3
b2
b1
b0
Processor mode register 1 (Address 5F16)
Bit
Functions
Bit name
0
Nothing is assigned.
1
Internal RAM area select bit
(Notes 1, 2)
0 : 512 bytes (addresses 8016 to 27F16)
1 : 1024 bytes (addresses 8016 to 47F16)
7 to 2 Nothing is assigned.
At reset
RW
Undefined
–
0
RW
Undefined
–
Notes 1: For the M37721S1BFP, fix bit 1 to “0.”
2: For the M37721S2BFP, set bit 1 before setting the stack pointer.
7721 Group User’s Manual
17–27
APPENDIX
Appendix 3. Control registers
Watchdog timer register
b7
b0
Watchdog timer register (Address 6016)
Bit
7 to 0
Functions
Initializes Watchdog timer.
When dummy data is written to this register, Watchdog
timer’s value is initialized to “FFF16.” (Dummy data: 0016 to FF16)
At reset
RW
Undefined
–
At reset
RW
0
RW
Watchdog timer frequency select register
b7
b6
b5
b4
b3
b2
b1
b0
Watchdog timer frequency select register (Address 6116)
Bit
0
Bit name
Watchdog timer frequency select 0 : f512
1 : f32
bit
7 to 1 Nothing is assigned.
17–28
7721 Group User’s Manual
Functions
Undefined
–
APPENDIX
Appendix 3. Control registers
Real-time output control register
b7
b6
b5
b4
b3
b2
b1
b0
Real-time output control register (Address 6216)
Bit
Bit name
Functions
0
Waveform output select bits
See the following Table.
1
2
0 : Pulse mode 0
1 : Pulse mode 1
Pulse output mode select bit
7 to 3 Nothing is assigned.
The value is “0” at reading.
At reset
RW
0
RW
0
RW
0
RW
Undefined
–
Note: When using the P60–P67 pins as the pulse output pins for real-time output, set the
corresponding bits of the port P6 direction register (address 1016) to “1.”
b1 b0
When pulse mode 0
is selected
When pulse mode 1
is selected
01
00
P67/RTP13
P66/RTP12
P65/RTP11
P64/RTP10
Port
P67/RTP13
P66/RTP12
P65/RTP11
P64/RTP10
RTP
P63/RTP03
P62/RTP02
P61/RTP01
P60/RTP00
Port
P67/RTP13
P66/RTP12
P65/RTP11
P64/RTP10
P63/RTP03
P62/RTP02
Port
P61/RTP01
P60/RTP00
Port
P67/RTP13
P66/RTP12
P65/RTP11
P64/RTP10
Port
P63/RTP03
P62/RTP02
P61/RTP01
P60/RTP00
P67/RTP13
P66/RTP12
P65/RTP11
P64/RTP10
P63/RTP03
P62/RTP02
P61/RTP01
P60/RTP00
P63/RTP03
P62/RTP02
P61/RTP01
P60/RTP00
10
11
RTP
P67/RTP13
P66/RTP12
P65/RTP11
P64/RTP10
RTP
Port
P63/RTP03
P62/RTP02
P61/RTP01
P60/RTP00
RTP
Port
P67/RTP13
P66/RTP12
P65/RTP11
P64/RTP10
P63/RTP03
P62/RTP02
RTP
P67/RTP13
P66/RTP12
P65/RTP11
P64/RTP10
P63/RTP03
P62/RTP02
RTP
RTP
P61/RTP01
P60/RTP00
Port
P61/RTP01
P60/RTP00
RTP
Port : This functions as a programmable I/O port.
RTP : This functions as a pulse output pin.
7721 Group User’s Manual
17–29
APPENDIX
Appendix 3. Control registers
DRAM control register
b7
b6
b5
b4
b3
b2
b1
b0
DRAM control register (Address 6416)
Bit
Bit name
Functions
At reset
RW
0 0 0 0 : No DRAM area
0 0 0 1 : F0000016–FFFFFF16 (1 Mbyte)
0 0 1 0 : E0000016–FFFFFF16 (2 Mbytes)
0 0 1 1 : D0000016–FFFFFF16 (3 Mbytes)
0 1 0 0 : C0000016–FFFFFF16 (4 Mbytes)
0 1 0 1 : B0000016–FFFFFF16 (5 Mbytes)
0 1 1 0 : A0000016–FFFFFF16 (6 Mbytes)
0 1 1 1 : 90000016–FFFFFF16 (7 Mbytes)
1 0 0 0 : 80000016–FFFFFF16 (8 Mbytes)
1 0 0 1 : 70000016–FFFFFF16 (9 Mbytes)
1 0 1 0 : 60000016–FFFFFF16 (10 Mbytes)
1 0 1 1 : 50000016–FFFFFF16 (11 Mbytes)
1 1 0 0 : 40000016–FFFFFF16 (12 Mbytes)
1 1 0 1 : 30000016–FFFFFF16 (13 Mbytes)
1 1 1 0 : 20000016–FFFFFF16 (14 Mbytes)
1 1 1 1 : 10000016–FFFFFF16 (15 Mbytes)
0
RW
0
RW
0
RW
0
RW
0
–
0
RW
b3 b2 b1 b0
0
DRAM area select bits
1
2
3
6 to 4
7
Nothing is assigned.
The value is “0” at reading.
0 : Invalid (P104–P107 pins function
as programmable input ports. A0–
A7 pins function as address
output pins. Refresh timer stops
counting.)
1 : Valid (P104–P107 pins function as
CAS, RAS, MA8, and MA9. A0–A7
function as MA0–MA7. Refresh
timer starts counting.)
DRAM validity bit (Note)
Note: Set the refresh timer (address 6616) before setting this bit to “1.”
Refresh timer
b7
b0
Refresh timer (Address 6616)
Bit
Functions
7 to 0 These bits can be set to “0116” to “FF16.”
Assuming that the set value = n, this register divides f16 by
(n + 1).
Note: Use the LDM or STA instruction for writing to this register.
Do not set this register to “0016.”
17–30
7721 Group User’s Manual
At reset
RW
Undefined
WO
APPENDIX
Appendix 3. Control registers
DMAC control register L
b7
b6
b5
b4
b3
b2
b1
b0
DMAC control register L (Address 6816)
Bit
Bit name
Functions
At reset
RW
0
Priority select bit
0 : Fixed
1 : Rotating
0
RW
1
TC pin validity bit
0 : Invalid
(P103 pin functions as a
programmable I/O port (CMOS).)
1 : Valid
(P103 pin functions as TC pin (Nchannel open-drain).)
0
RW
Undefined
–
0
RW
0
RW
3, 2
Nothing is assigned.
4
DMA0 request bit
5
DMA1 request bit
6
DMA2 request bit
0
RW
7
DMA3 request bit
0
RW
0 : No request
1 : Requested (Note 1)
Notes 1. The state of bits 4 to 7 are not changed when writing “1” to these bits.
2. •When writing to this register while any of DMAi enable bits (bits 4 to 7 at address
6916) is “1,” set m flag to “1” and use the LDM or STA instruction. When DMAi
request bit (bits 4 to 7 at address 6816) must not be changed, set DMAi request bit to
“1.”
•When writing to this register while all of DMAi enable bits (bits 4 to 7 at address 6916)
are “0,” m flag may be “0” or “1.” Use the LDM or STA instruction for writing to this
register. When DMAi request bit (bits 4 to 7 at address 6816) must not be changed,
set DMAi request bit to “1.”
DMAC control register H
b7
b6
b5
b4
b3
b2
b1
b0
DMAC control register H (Address 6916)
Bit
Bit name
Functions
At reset
RW
1 : DMA request
(Valid when software DMA source
is selected.)
The value is “0” at reading.
0
WO
0
WO
0
Software DMA0 request bit
1
Software DMA1 request bit
2
Software DMA2 request bit
0
WO
3
Software DMA3 request bit
0
WO
4
DMA0 enable bit
0
RW
5
DMA1 enable bit
0
RW
6
DMA2 enable bit
0
RW
7
DMA3 enable bit
0
RW
0 : Disabled
1 : Enabled
Note: When any of bits 4 to 7 is set to “1,” use the CLB or SEB instruction for writing to this
register.
7721 Group User’s Manual
17–31
APPENDIX
Appendix 3. Control registers
Interrupt control register
b7
b6
b5
b4
b3
b2
b1
b0
DMA0 to DMA3, A-D conversion, UART0 and 1 transmit, UART0 and 1 receive, timers A0 to A4, timers B0 to B2
interrupt control registers (Addresses 6C16 to 7C16)
Functions
Bit name
Bit
Interrupt priority level
select bits
0
1
2
Interrupt request bit
3
At reset
RW
0 0 0 : Level 0 (Interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
0
RW
0
RW
0
RW
0 : No interrupt requested
1 : Interrupt requested
0
RW
Undefined
–
b2 b1 b0
7 to 4 Nothing is assigned.
b7
b6
b5
b4
b3
b2
b1
b0
INT0 to INT2 interrupt control registers (Addresses 7D16 to 7F16)
Bit
0
Functions
Bit name
Interrupt priority level
select bits
1
2
At reset
RW
0 0 0 : Level 0 (Interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
0
RW
0
RW
0
RW
b2 b1 b0
3
Interrupt request bit (Note)
0 : No interrupt requested
1 : Interrupt requested
0
RW
4
Polarity select bit
0 : Interrupt request bit is set to “1”
at “H” level when level sense is
selected; this bit is set to “1” at
falling edge when edge sense is
selected.
1 : Interrupt request bit is set to “1”
at “L” level when level sense is
selected; this bit is set to “1” at
rising edge when edge sense is
selected.
0
RW
5
Level sense/Edge sense
select bit
0 : Edge sense
1 : Level sense
0
RW
Undefined
–
7, 6
Nothing is assigned.
Note: The interrupt request bits of INT0 to INT2 interrupts are invalid when the level sense is selected.
17–32
7721 Group User’s Manual
APPENDIX
Appendix 3. Control registers
Source address register i
b23
b16 b15
b8 b7
b0
Source address register 0 (Addresses 1FC216 to 1FC016)
Source address register 1 (Addresses 1FD216 to 1FD016)
Source address register 2 (Addresses 1FE216 to 1FE016)
Source address register 3 (Addresses 1FF216 to 1FF016)
Bit
Functions
23 to 0 These bits have different functions according to the
operating mode.
At reset
RW
Undefined
RW
Note: When writing to this register, write to all 24 bits.
Destination address register i
b23
b16 b15
b8 b7
b0
Destination address register 0 (Addresses 1FC616 to 1FC416)
Destination address register 1 (Addresses 1FD616 to 1FD416)
Destination address register 2 (Addresses 1FE616 to 1FE416)
Destination address register 3 (Addresses 1FF616 to 1FF416)
Bit
Functions
23 to 0 These bits have different functions according to the
operating mode.
At reset
RW
Undefined
RW
Note: When writing to this register, write to all 24 bits.
Transfer counter register i
b23
b16 b15
b8 b7
b0
Transfer counter register 0 (Addresses 1FCA16 to 1FC816)
Transfer counter register 1 (Addresses 1FDA16 to 1FD816)
Transfer counter register 2 (Addresses 1FEA16 to 1FE816)
Transfer counter register 3 (Addresses 1FFA16 to 1FF816)
Bit
Functions
23 to 0 These bits have different functions according to the
operating mode.
At reset
RW
Undefined
RW
Note: When writing to this register, write to all 24 bits.
Do not write “00000016” to this register.
7721 Group User’s Manual
17–33
APPENDIX
Appendix 3. Control registers
Single transfer mode
b23
b16 b15
b8 b7
b0
Source address register 0 (Addresses 1FC216 to 1FC016)
Source address register 1 (Addresses 1FD216 to 1FD016)
Source address register 2 (Addresses 1FE216 to 1FE016)
Source address register 3 (Addresses 1FF216 to 1FF016)
Bit
Functions
23 to 0 [Write]
Set the transfer start address of the source.
These bits can be set to “00000016” to “FFFFFF16.”
[Read]
The read value indicates the source address of data
which is next transferred.
At reset
RW
Undefined
RW
Note: When writing to this register, write to all 24 bits.
b23
b16 b15
b8 b7
b0
Destination address register 0 (Addresses 1FC616 to 1FC416)
Destination address register 1 (Addresses 1FD616 to 1FD416)
Destination address register 2 (Addresses 1FE616 to 1FE416)
Destination address register 3 (Addresses 1FF616 to 1FF416)
Bit
Functions
23 to 0 [Write]
Set the transfer start address of the destination.
These bits can be set to “00000016” to “FFFFFF16.”
[Read]
The read value indicates the destination address of
data which is next transferred.
At reset
RW
Undefined
RW
Note: When writing to this register, write to all 24 bits.
b23
b16 b15
b8 b7
b0
Transfer counter register 0 (Addresses 1FCA16 to 1FC816)
Transfer counter register 1 (Addresses 1FDA16 to 1FD816)
Transfer counter register 2 (Addresses 1FEA16 to 1FE816)
Transfer counter register 3 (Addresses 1FFA16 to 1FF816)
Bit
Functions
23 to 0 [Write]
Set the byte number of the transfer data.
These bits can be set to “00000116” to “FFFFFF16.”
[Read]
The read value indicates remaining byte number of
the transfer data.
Note: When writing to this register, write to all 24 bits.
Do not set this register to “00000016.”
17–34
7721 Group User’s Manual
At reset
RW
Undefined
RW
APPENDIX
Appendix 3. Control registers
Repeat transfer mode
b23
b16 b15
b8 b7
b0
Source address register 0 (Addresses 1FC216 to 1FC016)
Source address register 1 (Addresses 1FD216 to 1FD016)
Source address register 2 (Addresses 1FE216 to 1FE016)
Source address register 3 (Addresses 1FF216 to 1FF016)
Bit
Functions
23 to 0 [Write]
Set the transfer start address of the source.
These bits can be set to “00000016” to “FFFFFF16.”
[Read]
The read value indicates the source address of data
which is next transferred.
At reset
RW
Undefined
RW
Note: When writing to this register, write to all 24 bits.
b23
b16 b15
b8 b7
b0
Destination address register 0 (Addresses 1FC616 to 1FC416)
Destination address register 1 (Addresses 1FD616 to 1FD416)
Destination address register 2 (Addresses 1FE616 to 1FE416)
Destination address register 3 (Addresses 1FF616 to 1FF416)
Bit
Functions
23 to 0 [Write]
Set the transfer start address of the destination.
These bits can be set to “00000016” to “FFFFFF16.”
[Read]
The read value indicates the destination address of
data which is next transferred.
At reset
RW
Undefined
RW
Note: When writing to this register, write to all 24 bits.
b23
b16 b15
b8 b7
b0
Transfer counter register 0 (Addresses 1FCA16 to 1FC816)
Transfer counter register 1 (Addresses 1FDA16 to 1FD816)
Transfer counter register 2 (Addresses 1FEA16 to 1FE816)
Transfer counter register 3 (Addresses 1FFA16 to 1FF816)
Bit
Functions
23 to 0 [Write]
Set the byte number of the transfer data.
These bits can be set to “00000116” to “FFFFFF16.”
[Read]
The read value indicates the remaining byte number
of the block which is being transferred.
At reset
RW
Undefined
RW
Note: When writing to this register, write to all 24 bits.
Do not write “00000016” to this register.
7721 Group User’s Manual
17–35
APPENDIX
Appendix 3. Control registers
Array chain transfer mode
b23
b16 b15
b8 b7
b0
Source address register 0 (Addresses 1FC216 to 1FC016)
Source address register 1 (Addresses 1FD216 to 1FD016)
Source address register 2 (Addresses 1FE216 to 1FE016)
Source address register 3 (Addresses 1FF216 to 1FF016)
Bit
Functions
23 to 0 [Write]
Set the start address of transfer parameter memory.
These bits can be set to “00000016” to “FFFFFF16.”
[Read]
•After a value is written to this register and until
transfer starts, the read value indicates the written
value (the start address of the transfer parameter
memory).
•After tranfer starts, the read value indicates the
source address of data which is next transferred.
At reset
RW
Undefined
RW
Note: When writing to this register, write to all 24 bits.
b23
b16 b15
b8 b7
b0
Destination address register 0 (Addresses 1FC616 to 1FC416)
Destination address register 1 (Addresses 1FD616 to 1FD416)
Destination address register 2 (Addresses 1FE616 to 1FE416)
Destination address register 3 (Addresses 1FF616 to 1FF416)
Bit
Functions
23 to 0 Need not to set.
[Read]
After transfer starts, the read value indicates the
destination address of data which is next transferred.
b23
b16 b15
b8 b7
At reset
RW
Undefined
RW
b0
Transfer counter register 0 (Addresses 1FCA16 to 1FC816)
Transfer counter register 1 (Addresses 1FDA16 to 1FD816)
Transfer counter register 2 (Addresses 1FEA16 to 1FE816)
Transfer counter register 3 (Addresses 1FFA16 to 1FF816)
Bit
Functions
23 to 0 [Write]
Set the number of transfer blocks.
These bits can be set to “00000116” to “FFFFFF16.”
[Read]
•After a value is written to this register and until
transfer starts, the read value indicates the written
value (the transfer block number) .
•After transfer starts, the read value indicates the
remaining byte number of the block which is being
transferred.
Note: When writing to this register, write to all 24 bits.
Do not write “00000016” to this register.
17–36
7721 Group User’s Manual
At reset
RW
Undefined
RW
APPENDIX
Appendix 3. Control registers
Link array chain transfer mode
b23
b16 b15
b8 b7
b0
Source address register 0 (Addresses 1FC216 to 1FC016)
Source address register 1 (Addresses 1FD216 to 1FD016)
Source address register 2 (Addresses 1FE216 to 1FE016)
Source address register 3 (Addresses 1FF216 to 1FF016)
Bit
Functions
23 to 0 [Write]
Set the start address of transfer parameter memory
of block which is first transferred.
These bits can be set to “00000016” to “FFFFFF16.”
[Read]
•After a value is written to this register and until
transfer starts, the read value indicates the written
value (the start address of the transfer parameter
memory of block which is first transferred).
•After transfer starts, the read value indicates the
source address of data which is next transferred.
At reset
RW
Undefined
RW
Note: When writing to this register, write to all 24 bits.
b23
b16 b15
b8 b7
b0
Destination address register 0 (Addresses 1FC616 to 1FC416)
Destination address register 1 (Addresses 1FD616 to 1FD416)
Destination address register 2 (Addresses 1FE616 to 1FE416)
Destination address register 3 (Addresses 1FF616 to 1FF416)
Bit
Functions
23 to 0 Need not to set.
[Read]
After transfer starts, the read value indicates the
destination address of data which is next transferred.
b23
b16 b15
b8 b7
At reset
RW
Undefined
RW
b0
Transfer counter register 0 (Addresses 1FCA16 to 1FC816)
Transfer counter register 1 (Addresses 1FDA16 to 1FD816)
Transfer counter register 2 (Addresses 1FEA16 to 1FE816)
Transfer counter register 3 (Addresses 1FFA16 to 1FF816)
Bit
Functions
23 to 0 [Write]
Set the dummy data.
These bits can be set to “00000116” to “FFFFFF16.”
[Read]
•After a value is written to this register and until
transfer starts, the read value indicates the written
value (dummy data).
•After transfer starts, the read value indicates the
remaining byte number of the block which is being
transferred.
At reset
RW
Undefined
RW
Note: When writing to this register, write to all 24 bits.
Do not write “00000016” to this register.
7721 Group User’s Manual
17–37
APPENDIX
Appendix 3. Control registers
DMAi mode register L
b7
b6
b5
b4
b3
b2
b1
0
b0
DMA0 mode register L (Address 1FCC16)
DMA1 mode register L (Address 1FDC16)
DMA2 mode register L (Address 1FEC16)
DMA3 mode register L (Address 1FFC16)
Bit
Functions
Bit name
At reset
RW
0
Number-of-unit-transfer-bits
select bit (Note)
0 : 16 bits
1 : 8 bits
0
RW
1
Transfer method select bit
0 : 2-bus cycle transfer
1 : 1-bus cycle transfer
0
RW
2
Transfer mode select bit
0 : Burst transfer mode
1 : Cycle-steal transfer mode
0
RW
3
Fix this bit to “0.”
0
RW
4
Transfer source address
direction select bits
0
RW
0
RW
0
RW
0
RW
b5b4
0 0 : Fixed
0 1 : Forward
1 0 : Backward
1 1 : Do not select.
5
6
b7b6
Transfer destination address
direction select bits
0 0 : Fixed
0 1 : Forward
1 0 : Backward
1 1 : Do not select.
7
Note: When the external data bus has a width of 8 bits and 1-bus cycle transfer is selected, set
bit 0 to “1.”
DMAi mode register H
b7
b6
b5
b4
b3
b2
0 0
b1
b0
DMA0 mode register H (Address 1FCD16)
DMA1 mode register H (Address 1FDD16)
DMA2 mode register H (Address 1FED16)
DMA3 mode register H (Address 1FFD16)
At reset
RW
0 : From memory to I/O
1 : From I/O to memory
0
RW
Refer to “Fig.13.2.7.”
0
RW
0
RW
0
RW
Transfer source wait bit (Note 2) 0 : Wait
1 : No Wait
Transfer destination wait bit (Note 2)
0
RW
0
RW
Continuous transfer mode select b7b6
0 0 : Single transfer
bits
0 1 : Repeat transfer
1 0 : Array chain transfer
1 1 : Link array chain transfer
0
RW
0
RW
Bit
Bit name
0
Transfer direction select bit
(Used in 1-bus cycle transfer) (Note 1)
1
I/O connection select bit
(Valid in 1-bus cycle transfer)
2
Fix these bits to “0.”
Functions
3
4
5
6
7
Notes 1: Set bit 0 to “0” in 2-bus cycle transfer.
2: Bits 4 and 5 are valid to the external and internal areas. However, DRAM area is
always handled with “Wait” regardless of the contents of these bits.
The wait bit (bit 2 at address 5E16) is invalid in DMA transfer.
17–38
7721 Group User’s Manual
APPENDIX
Appendix 3. Control registers
DMAi control register
b7
b6
b5
b4
b3
b2
b1
b0
DMA0 control register (Address 1FCE16)
DMA1 control register (Address 1FDE16)
DMA2 control register (Address 1FEE16)
DMA3 control register (Address 1FFE16)
Bit
Bit name
0
DMA request source select bits
(Note)
1
2
3
Functions
b3b2b1b0
0 0 0 0 : Do not select.
0 0 0 1 : External source (DMAREQi)
0 0 1 0 : Software DMA source
0 0 1 1 : Timer A0
0 1 0 0 : Timer A1
0 1 0 1 : Timer A2
0 1 1 0 : Timer A3
0 1 1 1 : Timer A4
1 0 0 0 : Timer B0
1 0 0 1 : Timer B1
1 0 1 0 : Timer B2
1 0 1 1 : UART0 receive
1 1 0 0 : UART0 transmit
1 1 0 1 : UART1 receive
1 1 1 0 : UART1 transmit
1 1 1 1 : A-D conversion
At reset
RW
0
RW
0
RW
0
RW
0
RW
4
Edge sense/Level sense select
bit (Used when external source
and burst transfer mode are
selected) (Note)
0 : Edge sense (Falling edge)
1 : Level sense (“L” level)
0
RW
5
DMAACKi validity bit
0 : Invalid (The pin functions as a
programmable I/O port.)
1 : Valid
(The pin functions as DMAACKi.)
0
RW
7, 6
Nothing is assigned.
Undefined
–
Note: When a certain source other than an external source is selected by bits 0 to 3 or when
the cycle-steal transfer mode is selected, set bit 4 to “0.”
Level sense can be selected only when both of the external source and the burst
transfer mode are selected.
7721 Group User’s Manual
17–39
APPENDIX
Appendix 4. Package outline
Appendix 4. Package outline
17–40
7721 Group User’s Manual
APPENDIX
Appendix 5. Examples of handling unused pins
Appendix 5. Examples of handling unused pins
Examples of handling unused pins are described below. These descriptions are just examples. The user
shall modify them according to the actual application and test them.
Table 1 Examples of handling unused pins
Pins
Handling example
P4 3 to P4 7, P5 to P10
____
Connect these pins to the Vcc or Vss pin via resistors
after these pins are set to the input mode, or leave
these pins open after they are set to the output mode
(Notes 1, 2).
____
BLE, BHE, ALE, φ 1, ST0, ST1
Leave this pin open.
Leave this pin open.
XOUT (Note 3)
_____
____
HOLD, RDY
Connect these pins to the Vcc pin via resistors (These
pins are pulled high.) (Note 2)
CNVss
Connect this pin to the Vcc pin or Vss pin.
AVcc
Connect this pin to the Vcc pin.
Connect these pins to the Vss pin.
AVss, VREF
Notes 1: When leaving these pins open after they are set to the output mode, note the following: these pins
function as input ports from reset until they are switched to the output mode by software. Therefore,
voltage levels of these pins are undefined and the power source current may increase while these
pins function as input ports. Accordingly, set these ports to the output mode immediately after
reset. Software reliability can be enhanced when the contents of the above ports’ direction registers
are set periodically. This is because these contents may be changed by noise, a program runaway
which occurs to noise, etc.
2: For unused pins, use the shortest possible wiring (within 20 mm from the microcomputer’s pins).
3: This applies when a clock externally generated is input to the XIN pin.
● When setting ports to input mode
● When setting ports to output mode
P43–P47, P5–P10
P43–P47, P5–P10
Left open
ST0
ST1
BLE
BHE
ALE
ST0
ST1
BLE
BHE
ALE
Left open
Left open
XOUT
M37721
M37721
1
Left open
VCC
HOLD
RDY
AVCC
CNVSS✽
AVSS
VREF
1
XOUT
Left open
VCC
HOLD
RDY
AVCC
CNVSS✽
AVSS
VREF
VSS
VSS
✽ CNVss pin can be connected to Vcc pin.
Fig. 2 Examples of handling unused pins
7721 Group User’s Manual
17–41
APPENDIX
Appendix 6. Machine instructions
Appendix 6. Machine instructions
Addressing modes
Symbol
Functions
Details
IMP
op
ADC
A CC,C←A CC+M+C
(Notes 1,2)
A CC←A CC∧M
AND
(Notes 1,2)
ASL
(Note 1)
m=0
C ← b 15 ··· b 0 ←0
m=1
C ← b 7 ··· b0 ←0
DIR
DIR,b
DIR,X
DIR,Y
(DIR)
(DIR,X) (DIR),Y
69 2 2
65 4 2
75 5 2
72 6 2 61 7 2 71 8 2
42 4 3
69
42 6 3
65
42 7 3
75
42 8 3 42 9 3 42 10 3
72
61
71
Obtains the logical product of the contents of the accumulator and the contents of the memory . The result is entered into the accumulator.
29 2 2
25 4 2
35 5 2
32 6 2 21 7 2 31 8 2
42 4 3
29
42 6 3
25
42 7 3
35
42 8 3 42 9 3 42 10 3
32
21
31
0A 2 1 06 7 2
16 7 2
Shifts the accumulator or the memory contents one bit to
the left. “0” is entered into bit 0 of the accumulator or the
memory. The contents of bit 15 ( bit 7 when the m flag is
“1”) of the accumulator or memory before shift is entered
into the C flag.
Tests the specified bit of the memory. Branches when all
the contents of the specified bit is “0.”
Mb=1?
BBS
(Notes 3,5)
Tests the specified bit of the memory. Branches when all
the contents of the specified bit is “1.”
42 4 2
0A
BCC
(Note 3)
C=0?
Branches when the contents of the C flag is “0.”
BCS
(Note 3)
C=1?
Branches when the contents of the C flag is “1.”
BEQ
(Note 3)
Z=1?
Branches when the contents of the Z flag is “1.”
BMI
(Note 3)
N=1?
Branches when the contents of the N flag is “1.”
BNE
(Note 3)
Z=0?
Branches when the contents of the Z flag is “0.”
BPL
(Note 3)
N=0?
Branches when the contents of the N flag is “0.”
BRA
(Note 4)
PC←PC±offset
PG←PG+1
(when carry occurs)
PG←PG–1
(when borrow occurs)
Jumps to the address indicated by the program counter
plus the offset value.
BRK
PC←PC+2
M(S)←PG
S←S–1
M(S)←PCH
S←S–1
M(S)←PCL
S←S–1
M(S)←PSH
S←S–1
M(S)←PSL
S←S–1
I←1
PCL←AD L
PCH←ADH
PG←00 16
Executes software interruption.
BVC
(Note 3)
V=0?
Branches when the contents of the V flag is “0.”
BVS
(Note 3)
V=1?
Branches when the contents of the V flag is “1.”
CLB
(Note 5)
Mb←0
Makes the contents of the specified bit in the memory “0.”
CLC
C←0
Makes the contents of the C flag “0.”
18 2 1
CLI
I←0
Makes the contents of the I flag “0.”
58 2 1
CLM
m←0
Makes the contents of the m flag “0.”
D8 2 1
CLP
PSb←0
Specifies the bit position in the processor status register
by the bit pattern of the second byte in the instruction, and
sets “0” in that bit.
CLV
V←0
Makes the contents of the V flag “0.”
17–42
A
Adds the carry, the accumulator and the memory
contents.The result is entered into the accumulator. When
the D flag is “0,” binary additions is done, and when the
D flag is “1,” decimal addition is done.
Mb=0?
BBC
(Notes 3,5)
CMP
A CC–M
(Notes 1,2)
IMM
n # op n # op n # op n # op n # op n # op n # op n # op n # op n #
00 15 2
Compares the contents of the accumulator with the contents of the memory.
14 8 3
C2 4 2
B8 2 1
C9 2 2
C5 4 2
D5 5 2
D2 6 2 C1 7 2 D1 8 2
42 4 3
C9
42 6 3
C5
42 7 3
D5
42 8 3 42 9 3 42 10 3
C1
D2
D1
7721 Group User’s Manual
APPENDIX
Appendix 6. Machine instructions
Addressing modes
L(DIR) L(DIR),Y
op
ABS
ABS,b
ABS,X ABS,Y
ABL
ABL,X (ABS) L(ABS) (ABS,X)
Processor status register
STK
REL
DIR,b,R ABS,b,R
SR
(SR),Y
BLK
10 9 8 7 6 5 4 3 2 1 0
n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n #
67 10 2 77 11 2 6D 4 3
7D 6 3 79 6 3 6F 6 4 7F 7 4
63 5 2 73 8 2
42 12 3 42 13 3 42 6 4
77
6D
67
42 8 4 42 8 4 42 8 5 42 9 5
7D
79
6F
7F
42 7 3 42 10 3
63
73
27 10 2 37 11 2 2D 4 3
3D 6 3 39 6 3 2F 6 4 3F 7 4
23 5 2 33 8 2
42 12 3 42 13 3 42 6 4
37
2D
27
42 8 4 42 8 4 42 8 5 42 9 5
3D
39
2F
3F
42 7 3 42 10 3
23
33
0E 7 3
1E 8 3
N V m x D I Z C
IPL
• • • N V • • • • Z C
• • • N •
•
• • • Z •
• • • N • •
• • • Z C
34 7 4 3C 8 5
•
24 7 4 2C 8 5
• • •
• • • • • • • •
90 4 2
• • •
• • • •
B0 4 2
• • • •
F0 4 2
•
30 4 2
• • • • •
D0 4 2
• •
10 4 2
80 4 2
• • •
• • •
• • • •
• • • •
• • • • • • •
• • • •
• •
• • • •
• • • • • •
•
• • • • •
• • • •
• •
• • • • •
• • • •
• •
• • • •
•
• • • • • •
• • • •
•
50 4 2
• • • •
• •
• • • • •
70 4 2
• • • •
• • • • • • •
• • •
82 4 3
• • • • •
IC 9 4
• • •
• • • • • •
• •
• • • • • 0
• • • • •
• • • 0 • •
• • • •
• 0 • • • • •
• • • Specified flag becomes “0.”
• • •
C7 10 2 D7 11 2 CD 4 3
DD 6 3 D9 6 3 CF 6 4 DF 7 4
C3 5 2 D3 8 2
42 12 3 42 13 3 42 6 4
C7
D7
CD
42 8 4 42 8 4 42 8 5 42 9 5
DD
D9
CF
DF
42 7 3 42 10 3
C3
D3
7721 Group User’s Manual
•
• 0 •
• • N •
• • • • •
• • • • Z C
17–43
APPENDIX
Appendix 6. Machine instructions
Addressing modes
Symbol
Functions
Details
IMP
op
IMM
A
DIR
DIR,b
DIR,X
DIR,Y
(DIR)
(DIR,X) (DIR),Y
n # op n # op n # op n # op n # op n # op n # op n # op n # op n #
CPX
(Note 2)
X–M
Compares the contents of the index register X with the
contents of the memory.
E0 2 2
E4 4 2
CPY
(Note 2)
Y–M
Compares the contents of the index register Y with the
contents of the memory.
C0 2 2
C4 4 2
DEC
(Note 1)
A CC←A CC–1 or
M←M–1
Decrements the contents of the accumlator or memory by
1.
1A 2 1 C6 7 2
D6 7 2
42 4 2
1A
DEX
X←X–1
Decrements the contents of the index register X by 1.
CA 2 1
DEY
Y←Y–1
Decrements the contents of the index register Y by 1.
88 2 1
DIV
(Notes 2,10)
A(quotient)←B,A/M
B(remainder)
The numeral that places the contents of accumlator B to the higher
order and the contents of accumulator A to the lower order is divided
by the contents of the memory. The quotient is entered into accumulator A and the remainder into accumulator B.
89 27 3
29
89 29 3
25
89 30 3
35
89 31 3 89 32 3 89 33 3
32
21
31
EOR
(Notes 1,2)
A CC←A CC∨M
Logical exclusive sum is obtained of the contents of the
accumulator and the contents of the memory. The result is
placed into the accumulator.
49 2 2
45 4 2
55 5 2
52 6 2 41 7 2 51 8 2
42 4 3
49
42 6 3
45
42 7 3
55
42 8 3 42 9 3 42 10 3
51
52
41
3A 2 1 E6 7 2
F6 7 2
INC
(Note 1)
A CC←A CC+1 or
M←M+1
Increments the contents of the accumulator or memory by
1.
42 4 2
3A
INX
X←X+1
Increments the contents of the index register X by 1.
E8 2 1
INY
Y←Y+1
Increments the contents of the index register Y by 1.
C8 2 1
JMP
ABS
PC L←ADL
PCH←ADH
Places a new address into the program counter and jumps
to that new address.
ABL
PC L←ADL
PCH←ADH
PG←ADG
(ABS)
PC L←(ADH, AD L)
PCH←(ADH,AD L+1)
L(ABS)
PC L←(ADH, AD L)
PC H←(AD H, ADL+1)
PG←(AD H, ADL+2)
(ABS, X)
PC L←(ADH, ADL+X)
PC H←(AD H, AD L+X
+1)
JSR
ABS
M(S)←PCH
S←S–1
M(S)←PCL
S←S–1
PC L←ADL
PCH←ADH
Saves the contents of the program counter (also the contents of the program bank register for ABL) into the stack,
and jumps to the new address.
ABL
M(S)←PG
S←S–1
M(S)←PCH
S←S–1
M(S)←PCL
S←S–1
PC L←ADL
PCH←ADH
PG←ADG
(ABS, X)
M(S)←PCH
S←S–1
M(S)←PCL
S←S–1
PC L←(ADH, ADL+X)
PC H←(AD H, AD L+X
+1)
17–44
7721 Group User’s Manual
APPENDIX
Appendix 6. Machine instructions
Addressing modes
L(DIR) L(DIR),Y
op
ABS
ABS,b
ABS,X ABS,Y
ABL
ABL,X (ABS) L(ABS) (ABS,X)
Processor status register
STK
REL
DIR,b,R ABS,b,R
SR
(SR),Y
BLK
n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n #
10 9 8 7 6 5 4 3 2 1 0
IPL
N V m x D I Z C
EC 4 3
• • • N •
•
• • • Z C
CC 4 3
• • • N •
•
• • • Z C
• • • N •
•
• • • Z •
CE 7 3
DE 8 3
• • • N • • •
• • • N •
•
• • Z •
• • • Z •
89 35 3 89 36 3 89 29 4
27
2D
37
89 31 4 89 31 4 89 31 5 89 32 5
39
3D
2F
3F
89 30 3 89 33 3
23
33
• • • N V • • • • Z C
47 10 2 57 11 2 4D 4 3
5D 6 3 59 6 3 4F 6 4 5F 7 4
43 5 2 53 8 2
• • • N •
42 12 3 42 13 3 42 6 4
57
47
4D
42 8 4 42 8 4 42 8 5 42 9 5
59
5D
4F
5F
42 7 3 42 10 3
43
53
EE 7 3
FE 8 3
•
• • • Z •
• • • N • •
• • • Z •
• • • N •
• • • • Z •
• • • N •
• •
•
• • • • •
• •
• • • • •
4C 2 3
5C 4 4
6C 4 3 DC 8 3 7C 6 3
• •
• • •
20 6 3
22 8 4
FC 8 3
• •
• •
7721 Group User’s Manual
• • Z •
17–45
APPENDIX
Appendix 6. Machine instructions
Addressing modes
Symbol
Functions
Details
IMP
op
LDA
(Notes 1,2)
A CC←M
IMM
A
DIR
DIR,b
DIR,X
Enters the contents of the memory into the accummulator.
B5 5 2
B2 6 2 A1 7 2 B1 8 2
42 4 3
A9
42 6 3
A5
42 7 3
B5
42 8 3 42 9 3 42 10 3
A1
B1
B2
64 4 3
74 5 3
Enters the immediate vaiue into the memory.
LDT
DT←IMM
Enters the immediate value into the data bank regiater.
89 5 3
C2
LDX
(Note 2)
X←M
Enters the contents of the memory into index register X.
A2 2 2
A6 4 2
LDY
(Note 2)
Y←M
Enters the contents of the memory into index register Y.
A0 2 2
A4 4 2
B4 5 2
LSR
(Note 1)
m=0
0 → b 15 ··· b0 →C
m=1
0 → b 7 ··· b 0 →C
Shifts the contents of the accumulator or the contents of
the memory one bit to the right. The bit 0 of the accumulator or the memory is entered into the C flag. “0” is entered into bit 15 (bit 7 when the m flag is “1.”)
4A 2 1 46 7 2
56 7 2
MPY
(Notes 2,11)
B, A←A✽M
Multiplies the contents of accumulator A and the contents of the memory.
The higher order of the result of operation are entered into accumulator
B, and the lower order into accumulator A.
MVN
(Note 8)
Mn+i←Mm+i
Transmits the data block. The transmission is done from
the lower order address of the block.
MVP
(Note 9)
Mn–i←Mm–i
Transmits the data block. Transmission is done form the
higher order address of the data block.
NOP
PC←PC+1
Advances the program counter, but pertorms nothing else. EA 2 1
ORA
(Notes 1,2)
A CC←A CCVM
Logical sum per bit of the contents of the accumulator and
the contents of the memory is obtained. The result is entered into the accumulator.
The 3rd and the 2nd bytes of the instruction are saved into
the stack, in this order.
PEI
M(S)←M((DPR)+IMM
+1)
S←S–1
M(S)←M((DPR)+IMM)
S←S–1
Specifies 2 sequential bytes in the direct page in the 2nd
byte of the instruction, and saves the contents into the
stack.
PER
EAR←PC+IMM 2,IMM1
M(S)←EARH
S←S–1
M(S)←EARL
S←S–1
Regards the 2nd and 3rd bytes of the instruction as 16-bit
numerals, adds them to the program counter, and saves
the result into the stack.
PHA
m=0
M(S)←AH
S←S–1
M(S)←A L
S←S–1
Saves the contents of accumulator A into the stack.
m=0
M(S)←BH
S←S–1
M(S)←B L
S←S–1
89 16 3
09
89 18 3
05
89 19 3
15
89 20 3 89 21 3 89 22 3
01
11
12
09 2 2
05 4 2
15 5 2
12 6 2 01 7 2 11 8 2
42 4 3
09
42 6 3
05
42 7 3
15
42 8 3 42 9 3 42 10 3
12
01
11
Saves the contents of accumuator B into the stack.
m=1
M(S)←B L
S←S–1
17–46
B6 5 2
42 4 2
4A
m=1
M(S)←A L
S←S–1
PHB
(DIR,X) (DIR),Y
A5 4 2
M←IMM
M(S)←IMM2
S←S–1
M(S)←IMM1
S←S–1
(DIR)
A9 2 2
LDM
(Note 5)
PEA
DIR,Y
n # op n # op n # op n # op n # op n # op n # op n # op n # op n #
7721 Group User’s Manual
APPENDIX
Appendix 6. Machine instructions
Addressing modes
L(DIR) L(DIR),Y
op
ABS
ABS,b
ABS,X ABS,Y
ABL
ABL,X (ABS) L(ABS) (ABS,X)
Processor status register
STK
REL
DIR,b,R ABS,b,R
SR
(SR),Y
BLK
10 9 8 7 6 5 4 3 2 1 0
n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n #
A7 10 2 B7 11 2 AD 4 3
BD 6 3 B9 6 3 AF 6 4 BF 7 4
A3 5 2 B3 8 2
42 12 3 42 13 3 42 6 4
A7
B7
AD
42 8 4 42 8 4 42 8 5 42 9 5
BD
B9
AF
BF
42 7 3 42 10 3
A3
B3
9C 5 4
IPL
• • • N • •
9E 6 4
• • • • • •
• • •
• • • • • •
• • • N • •
BE 6 3
• • • Z •
• • • • •
• •
AE 4 3
N V m x D I Z C
• • • Z •
AC 4 3
BC 6 3
• • • N • • • • • Z •
4E 7 3
5E 8 3
• • • 0 •
•
• • • Z C
• •
•
• • • Z 0
• • • • • •
• • • • •
89 24 3 89 25 3 89 18 4
17
07
0D
89 20 4 89 20 4 89 20 5 89 21 5
1F
1D
19
0F
89 19 3 89 22 3
03
13
54 7 3
+
• N •
i
✕7
2
44 9 3 • • • • •
+
• • • • • •
i
✕7
2
• •
• •
•
• • • • •
• •
• N • •
• • • Z •
F4 5 3
• •
• • •
•
• • • • •
D4 6 2
• •
• • • •
• • • • •
62 5 3
•
48 4 1
• •
42 6 2
48
• • • • •
07 10 2 17 11 2 0D 4 3
1D 6 3 19 6 3 0F 6 4 1F 7 4
03 5 2 13 8 2
42 12 3 42 13 3 42 6 4
07
17
0D
42 8 4 42 8 4 42 8 5 42 9 5
1D
19
0F
1F
42 7 3 42 10 3
03
13
7721 Group User’s Manual
• • •
•
• • •
• • •
• • • •
• • • • • •
•
• • • • •
17–47
APPENDIX
Appendix 6. Machine instructions
Addressing modes
Symbol
Functions
Details
IMP
op
PHD
M(S)←DPRH
S←S–1
M(S)←DPR L
S←S–1
Saves the contents of the direct page register into the
stack.
PHG
M(S)←PG
S←S–1
Saves the contents of the program bank register into the
stack.
PHP
M(S)←PSH
S←S–1
M(S)←PSL
S←S–1
Saves the contents of the program status register into the
stack.
PHT
M(S)←DT
S←S–1
Saves the contents of the data bank register into the stack.
PHX
x=0
M(S)←XH
S←S–1
M(S)←X L
S←S–1
Saves the contents of the index register X into the stack.
x=1
M(S)←X L
S←S–1
PHY
x=0
M(S)←YH
S←S–1
M(S)←Y L
S←S–1
Saves the contents of the index register Y into the stack.
x=1
M(S)←Y L
S←S–1
PLA
m=0
S←S+1
A L←M(S)
S←S+1
A H←M(S)
Restores the contents of the stack on the accumulator A.
m=1
S←S+1
A L←M(S)
PLB
m=0
S←S+1
B L←M(S)
S←S+1
B H←M(S)
Restores the contents of the stack on the accumulator B.
m=1
S←S+1
B L←M(S)
PLD
S←S+1
DPR L←M(S)
S←S+1
DPR H←M(S)
Restores the contents of the stack on the direct page register.
PLP
S←S+1
PS L←M(S)
S←S+1
PS H←M(S)
Restores the contents of the stack on the processor status
register.
PLT
S←S+1
DT←M(S)
Restores the contents of the stack on the data bank register.
PLX
x=0
S←S+1
X L←M(S)
S←S+1
X H←M(S)
Restores the contents of the stack on the index register X.
x=1
S←S+1
X L←M(S)
17–48
IMM
A
DIR
n # op n # op n # op n #
7721 Group User’s Manual
DIR,b
op
DIR,X
DIR,Y
(DIR)
(DIR,X) (DIR),Y
n # op n # op n # op n # op n # op n #
APPENDIX
Appendix 6. Machine instructions
Addressing modes
L(DIR) L(DIR),Y
op
ABS
ABS,b
ABS,X ABS,Y
ABL
ABL,X (ABS) L(ABS) (ABS,X)
Processor status register
STK
REL
DIR,b,R ABS,b,R
SR
(SR),Y
BLK
n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n #
10 9 8 7 6 5 4 3 2 1 0
IPL
N V m x D I Z C
0B 4 1
• • • • • •
•
• • • •
4B 3 1
• • • • • •
•
• • • •
08 4 1
• • • • • •
•
• • • •
8B 3 1
• • • • • •
•
• • • •
DA 4 1
• • • • • •
•
• • • •
5A 4 1
• • • • • •
•
• • • •
68 5 1
• • • N • • • • • Z •
42 7 2
68
• • • N • • • • • Z •
2B 5 1
• • • • • •
28 6 1
Value saved in stack.
AB 6 1
• • • N • • • • • Z •
FA 5 1
• • • N • • • • • Z •
7721 Group User’s Manual
•
• • • •
17–49
APPENDIX
Appendix 6. Machine instructions
Addressing modes
Symbol
Functions
Details
IMP
op
PLY
x=0
S←S+1
Y L←M(S)
S←S+1
Y H←M(S)
IMM
A
DIR
n # op n # op n # op n #
DIR,b
op
DIR,X
DIR,Y
(DIR)
(DIR,X) (DIR),Y
n # op n # op n # op n # op n # op n #
Restores the contents of the stack on the index register Y.
x=1
S←S+1
Y L←M(S)
PSH
(Note 6)
M(S)←A, B, X···
Saves the registers among accumulator, index register, direct
page register, data bank register, program bank register,
or processor status register, specified by the bit pattern of
the second byte of the instruction into the stack.
PUL
(Note 7)
A, B, X···←M(S)
Restores the contents of the stack to the registers among
accumulator, index register, direct page register, data bank
register, or processor status register, specified by the bit
pattern of the second byte of the instruction.
RLA
(Note 13)
m=0
n bit rotate left
Rotates the contents of the accumulator A, n bits to the
left.
89 6 3
49 +
i
← b 15 ··· b0 ←
m=1
n bit rotate left
← b7 ··· b0 ←
ROL
(Note 1)
m=0
← b 15 ··· b0 ← C ←
Links the accumulator or the memory to C flag, and rotates
result to the left by 1 bit.
2A 2 1 26 7 2
36 7 2
42 4 2
2A
m=1
← b 7 ··· b 0 ← C ←
ROR
(Note 1)
m=0
→ C → b 15 ··· b0 →
Links the accumulator or the memory to C flag, and rotates
result to the right by 1 bit.
6A 2 1 66 7 2
76 7 2
42 4 2
6A
m=1
→ C → b7 ··· b 0 →
40 11 1
RTI
S←S+1
PS L←M(S)
S←S+1
PS H←M(S)
S←S+1
PC L←M(S)
S←S+1
PCH←M(S)
S←S+1
PG←M(S)
Returns from the interruption routine.
RTL
S←S+1
PC L←M(S)
S←S+1
PCH←M(S)
S←S+1
PG←M(S)
Returns from the subroutine. The contents of the program 6B 8 1
bank register are also restored.
RTS
S←S+1
PC L←M(S)
S←S+1
PCH←M(S)
Returns from the subroutine. The contents of the program 60 5 1
bank register are not restored.
SBC
(Notes 1,2)
A CC, C←A CC–M–C
Subtracts the contents of the memory and the borrow from
the contents of the accumulator.
17–50
E9 2 2
E5 4 2
F5 5 2
F2 6 2 E1 7 2 F1 8 2
42 4 3
E9
42 6 3
E5
42 7 3
F5
42 8 3 42 9 3 42 10 3
F2
E1
F1
7721 Group User’s Manual
APPENDIX
Appendix 6. Machine instructions
Addressing modes
L(DIR) L(DIR),Y
op
ABS
ABS,b
ABS,X ABS,Y
ABL
ABL,X (ABS) L(ABS) (ABS,X)
Processor status register
STK
REL
DIR,b,R ABS,b,R
SR
(SR),Y
BLK
n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n #
10 9 8 7 6 5 4 3 2 1 0
IPL
N V m x D I Z C
7A 5 1
• • • N • • • • • Z •
EB 12 2
• • • • • •
+
•
• • • •
2i1+i 2
FB 14 2
If restored the contents of
PS, it becomes its value.
And the other cases are no
change.
+
3i 1+4i 2
• • • • • •
•
• • • •
2E 7 3
3E 8 3
• • • N • • • • • Z C
6E 7 3
7E 8 3
• • • N • • • • • Z C
Value saved in stack.
E7 10 2 F7 11 2 ED 4 3
FD 6 3 F9 6 3 EF 6 4 FF 7 4
E3 5 2 F3 8 2
42 12 3 42 13 3 42 6 4
E7
F7
ED
42 8 4 42 8 4 42 8 5 42 9 5
FD
F9
EF
FF
42 7 3 42 10 3
F3
E3
7721 Group User’s Manual
• • • • • •
•
• •
• •
• • • • • •
•
• •
• •
• • • N V • • • • Z C
17–51
APPENDIX
Appendix 6. Machine instructions
Addressing modes
Symbol
Functions
Details
IMP
op
SEB
(Note 5)
Mb←1
Makes the contents of the specified bit in the memory “1.”
SEC
C←1
Makes the contents of the C flag “1.”
38 2 1
SEI
I←1
Makes the contents of the I flag “1.”
78 2 1
SEM
m←1
Makes the contents of the m flag “1.”
F8 2 1
SEP
PSb←1
Set the specified bit of the processor status register's lower
byte (PSL) to “1.”
STA
(Note 1)
M←ACC
Stores the contents of the accumulator into the memory.
Stops the oscillation of the oscillator.
STP
IMM
A
DIR
n # op n # op n # op n #
92 7 2 81 7 2 91 7 2
42 6 3
85
42 7 3
95
42 9 3 42 9 3 42 9 3
92
81
91
DB 3 1
STY
M←Y
Stores the contents of the index register Y into the memory.
84 4 2
TAD
DPR←A
Transmits the contents of the accumulator A to the direct 5B 2 1
page register.
TAS
S←A
Transmits the contents of the accumulator A to the stack pointer.
TAX
X←A
Transmits the contents of the accumulator A to the index AA 2 1
register X.
TAY
Y←A
Transmits the contents of the accumulator A to the index A8 2 1
register Y.
TBD
DPR←B
Transmits the contents of the accumulator B to the direct 42 4 2
page register.
5B
TBS
S←B
Transmits the contents of the accumulator B to the stack 42 4 2
pointer.
1B
TBX
X←B
Transmits the contents of the accumulator B to the index 42 4 2
register X.
AA
TBY
Y←B
Transmits the contents of the accumulator B to the index 42 4 2
register Y.
A8
TDA
A←DPR
Transmits the contents of the direct page register to the 7B 2 1
accumulator A.
TDB
B←DPR
Transmits the contents of the direct page register to the 42 4 2
accumulator B.
7B
TSA
A←S
Transmits the contents of the stack pointer to the accumulator A.
3B 2 1
TSB
B←S
Transmits the contents of the stack pointer to the accumulator B.
42 4 2
TSX
X←S
Transmits the contents of the stack pointer to the index BA 2 1
register X.
TXA
A←X
Transmits the contents of the index register X to the accumulator A.
8A 2 1
TXB
B←X
Transmits the contents of the index register X to the accumulator B.
42 4 2
8A
TXS
S←X
Transmits the contents of the index register X to the stack
pointer.
9A 2 1
TXY
Y←X
Transmits the contents of the index register X to the index 9B 2 1
register Y.
TYA
A←Y
Transmits the contents of the index register Y to the ac- 98 2 1
cumulator A.
TYB
B←Y
Transmits the contents of the index register Y to the accumulator B.
TYX
X←Y
Transmits the contents of the index register Y to the index BB 2 1
register X.
17–52
(DIR,X) (DIR),Y
95 5 2
86 4 2
Stops the internal clock.
(DIR)
85 4 2
Stores the contents of the index register X into the memory.
A←
→B
DIR,Y
E2 3 2
M←X
XAB
DIR,X
n # op n # op n # op n # op n # op n #
04 8 3
STX
WIT
DIR,b
op
1B 2 1
3B
42 4 2
98
CB 3 1
Exchanges the contents of the accumulator A and the con- 89 6 2
tents of the accumulator B.
28
7721 Group User’s Manual
96 5 2
94 5 2
APPENDIX
Appendix 6. Machine instructions
Addressing modes
L(DIR) L(DIR),Y
op
ABS
ABS,b
ABS,X ABS,Y
ABL
ABL,X (ABS) L(ABS) (ABS,X)
Processor status register
STK
REL
DIR,b,R ABS,b,R
SR
(SR),Y
BLK
n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n #
0C 9 4
10 9 8 7 6 5 4 3 2 1 0
IPL
N V m x D I Z C
• • • • • •
•
• • • •
• • • • • •
•
• • • 1
• • • • • •
•
• 1 • •
• • • • • 1
•
• • • •
• • • Specified
• • • flag
• •becomes
• • •
“1.”
87 10 2 97 11 2 8D 5 3
9D 5 3 99 5 3 8F 6 4 9F 7 4
83 5 2 93 8 2
42 12 3 42 13 3 42 7 4
97
87
8D
42 7 4 42 7 4 42 8 5 42 9 5
9D
99
9F
8F
42 7 3 42 10 3
83
93
• • • • • •
•
• • • •
• • • • • •
•
• • • •
8E 5 3
• • • • • •
•
• • • •
8C 5 3
• • • • • •
•
• • • •
• • • • • •
•
• • • •
• • • • • •
•
• • • •
• • • N • • • • • Z •
• • • N • • • • • Z •
• • • • • •
•
• • • •
• • • • • •
•
• • • •
• • • N • • • • • Z •
• • • N • • • • • Z •
• • • N • • • • • Z •
• • • N • • • • • Z •
• • • N • • • • • Z •
• • • N • • • • • Z •
• • • N • • • • • Z •
• • • N • • • • • Z •
• • • N • • • • • Z •
• • • • • •
•
• • • •
• • • N • • • • • Z •
• • • N • • • • • Z •
• • • N • • • • • Z •
• • • N • • • • • Z •
• • • • • •
•
• • • •
• • • N • • • • • Z •
7721 Group User’s Manual
17–53
APPENDIX
Appendix 6. Machine instructions
The number of cycles shown in the table is described in the case of the fastest mode for each instruction. The number of cycles shown
in the table is calculated for DPR L =0. The number of cycles in the addressing mode concerning the DPR when DPR L 0 must be
incremented by 1.
The number of cycles shown in the table differs according to the bytes fetched into the instruction queue buffer, or according to whether
the memory read/write address is odd or even. It also differs when the external region memory is accessed by BYTE=“H.”
Notes 1. The operation code at the upper row is used for accumulator A, and the operation at the lower row is used for accumulator
B.
2. When setting flag m=0 to handle the data as 16-bit data in the immediate addressing mode, the number of bytes increments
by 1.
3. The number of cycles increments by 2 when branching.
4. The operation code on the upper row is used for branching in the range of –128 to +127, and the operation code on the
lower row is used for branching in the range of –32768 to +32767.
5. When handling 16-bit data with flag m=0, the byte in the table is incremented by 1.
6.
Type of register
Number of cycles
A
2
B
2
X
2
Y
2
DPR
2
DT
1
PG
1
PS
2
The number of cycles corresponding to the register to be pushed are added. The number of cycles when no pushing is done
is 12. i 1 indicates the number of registers among A, B, X, Y, DPR, and PS to be saved, while i2 indicates the number of
registers among DT and PG to be saved.
7.
Type of register
Number of cycles
A
3
B
3
X
3
Y
3
DPR
4
DT
3
PS
3
The number of cycles corresponding to the register to be pulled are added. The number of cycles when no pulling is done
is 14. i 1 indicates the number of registers among A, B, X, Y, DT, and PS to be restored, while i 2 =1 when DPR is to be
restored.
8. The number of cycles is the case when the number of bytes to be transferred is even.
When the number of bytes to be transferred is odd, the number is calculated as;
7 + (i/2) ✕ 7 + 4
Note that, (i/2) shows the integer part when i is divided by 2.
9. The number of cycles is the case when the number of bytes to be transferred is even.
When the number of bytes to be transferred is odd, the number is calculated as;
9 + (i/2) ✕ 7 + 5
Note that, (i/2) shows the integer part when i is divided by 2.
10. The number of cycles is the case in the 16-bit ÷ 8-bit operation. The number of cycles is incremented by 16 for 32-bit ÷ 16bit operation.
11. The number of cycles is the case in the 8-bit ✕ 8-bit operation. The number of cycles is incremented by 8 for 16-bit ✕ 16bit operation.
12. When setting flag x=0 to handle the data as 16-bit data in the immediate addressing mode, the number of bytes increments
by 1.
13. When flag m is 0, the byte in the table is incremented by 1.
17–54
7721 Group User’s Manual
APPENDIX
Appendix 6. Machine instructions
Symbols in machine instructions table
Symbol
IMP
IMM
A
DIR
DIR, b
DIR, X
DIR, Y
(DIR)
(DIR,X)
(DIR), Y
L (DIR)
L (DIR),Y
ABS
ABS, b
ABS, X
ABS, Y
ABL
ABL, X
(ABS)
L (ABS)
(ABS, X)
STK
REL
DIR, b, REL
ABS, b, REL
SR
(SR), Y
BLK
C
Z
I
D
x
m
V
N
IPL
+
–
✽
/
∧
∨
Description
Implied addressing mode
Immediate addressing mode
Accumulator addressing mode
Direct addressing mode
Direct bit addressing mode
Direct indexed X addressing mode
Direct indexed Y addressing mode
Direct indirect addressing mode
Direct indexed X indirect addressing mode
Direct indirect indexed Y addressing mode
Direct indirect long addressing mode
Direct indirect long indexed Y addressing mode
Absolute addressing mode
Absolute bit addressing mode
Absolute indexed X addressing mode
Absolute indexed Y addressing mode
Absolute long addressing mode
Absolute long indexed X addressing mode
Absolute indirect addressing mode
Absolute indirect long addressing mode
Absolute indexed X indirect addressing mode
Stack addressing mode
Relative addressing mode
Direct bit relative addressing mode
Absolute bit relative addressing mode
Stack pointer relative addressing mode
Stack pointer relative indirect indexed Y
addressing mode
Block transfer addressing mode
Carry flag
Zero flag
Interrupt disable flag
Decimal operation mode flag
Index register length selection flag
Data length selection flag
Overflow flag
Negative flag
Processor interrupt priority level
Addition
Subtraction
Multiplication
Division
Logical AND
Logical OR
∨
Symbol
–
←
ACC
ACCH
ACCL
A
AH
AL
B
BH
BL
X
XH
XL
Y
YH
YL
S
PC
PCH
PCL
PG
DT
DPR
DPRH
DPRL
PS
PSH
PSL
PSb
M(S)
Mb
ADG
ADH
ADL
op
n
#
i
i1, i2
7721 Group User’s Manual
Description
Exclusive OR
Negation
Movement to the arrow direction
Accumulator
Accumulator’s upper 8 bits
Accumulator’s lower 8 bits
Accumulator A
Accumulator A’s upper 8 bits
Accumulator A’s lower 8 bits
Accumulator B
Accumulator B’s upper 8 bits
Accumulator B’s lower 8 bits
Index register X
Index register X’s upper 8 bits
Index register X’s lower 8 bits
Index register Y
Index register Y’s upper 8 bits
Index register Y’s lower 8 bits
Stack pointer
Program counter
Program counter’s upper 8 bits
Program counter’s lower 8 bits
Program bank register
Data bank register
Direct page register
Direct page register’s upper 8 bits
Direct page register’s lower 8 bits
Processor status register
Processor status register’s upper 8 bits
Processor status register’s lower 8 bits
Processor status register’s b-th bit
Contents of memory at address indicated by
stack pointer
b-th memory location
Value of 24-bit address’s upper 8-bit (A23–A16)
Value of 24-bit address’s middle 8-bit (A15–A8)
Value of 24-bit address’s lower 8-bit (A7–A0)
Operation code
Number of cycle
Number of byte
Number of transfer byte or rotation
Number of registers pushed or pulled
17–55
APPENDIX
Appendix 7. Hexadecimal instruction code table
Appendix 7. Hexadecimal instruction code table
INSTRUCTION CODE TABLE-1
D3–D0
D7–D4
0000
Hexadecimal
notation
0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
SEB
ORA
ORA
ORA
SEB
ORA
ASL
ORA
A,(DIR,X)
A,SR
DIR,b
A,DIR
DIR
A,L(DIR)
ORA
CLB
ORA
ASL
ORA
A,(DIR),Y A,(DIR) A,(SR),Y DIR,b
A,DIR,X
ORA
0001
1
3
AND
JSR
AND
BBS
AND
5
1001
A,DIR
DIR
A,L(DIR)
A,IMM
A
AND
ROL
AND
AND
INC
RTI
A,(DIR,X)
EOR
Note 1
EOR
EOR
1011
1101
EOR
DIR
A,L(DIR)
A,IMM
EOR
LSR
EOR
EOR
CLI
A,DIR,X
ADC
LDM
ADC
A,SR
DIR
A,DIR
ADC
LDM
ADC
DIR,X A,L(DIR),Y
ROR
ADC
PER
A,L(DIR)
ROR
ADC
BVS
STA
BRA
STA
STY
STA
REL
A,(DIR,X)
REL
A,SR
DIR
A,DIR
STA
STA
STA
STY
STA
A,L(DIR)
STX
STA
LDY
LDA
LDX
LDA
LDY
LDA
IMM
A,(DIR,X)
IMM
A,SR
DIR
A,DIR
LDA
LDA
LDA
LDY
LDA
A,L(DIR)
LDX
LDA
CPY
CMP
CLP
CMP
CPY
CMP
IMM
A,(DIR,X)
IMM
A,SR
DIR
A,DIR
E
1111
F
ROR
A
CMP
CMP
CMP
CMP
DIR
A,L(DIR)
DEC
CMP
PEI
BNE
CPX
SBC
SEP
SBC
CPX
SBC
INC
SBC
IMM
A,(DIR,X)
IMM
A,SR
DIR
A,DIR
DIR
A,L(DIR)
SBC
SBC
SBC
INC
SBC
BEQ
A,(DIR),Y A,(DIR) A,(SR),Y
SBC
PEA
A,DIR,X
DIR,X A,L(DIR),Y
EOR
ABS
A,ABS
ABS
A,ABL
JMP
EOR
LSR
EOR
A,ABS,X ABS,X A,ABL,X
ADC
Note 2
TXA
ADC
ABS
A,ABL
ROR
ADC
STA
STX
STA
A,ABS
ABS
A,ABL
STA
LDM
STA
TXY
ABS
TAX
TSX
A,ABS,X ABS,X A,ABL,X
LDY
LDA
LDX
LDA
ABS
A,ABS
ABS
A,ABL
LDY
LDA
LDX
LDA
PLT
LDA
TYX
ABS,X A,ABS,X ABS,Y A,ABL,X
CMP
DEX
CMP
PHX
CPY
CMP
DEC
CMP
ABS
A,ABS
ABS
A,ABL
JMP
CMP
DEC
CMP
WIT
A,IMM
STP
A,ABS,Y
L(ABS) A,ABS,X ABS,X A,ABL,X
SBC
NOP
PSH
PLX
PUL
SBC
A,ABS,Y
STY
ABS
PHT
LDM
TXS
A,IMM
ADC
CPX
SBC
INC
SBC
ABS
A,ABS
ABS
A,ABL
JSR
SBC
INC
SBC
(ABS,X) A,ABS,X ABS,X A,ABL,X
Notes 1: 4216 specifies the contents of the INSTRUCTION CODE TABLE-2.
About the second word’s codes, refer to the INSTRUCTION CODE TABLE-2.
2: 8916 specifies the contents of the INSTRUCTION CODE TABLE-3.
About the second word’s codes, refer to the INSTRUCTION CODE TABLE-2.
17–56
ROR
(ABS,X) A,ABS,X ABS,X A,ABL,X
A,ABS,Y
SEM
AND
TDA
LDA
INX
A,ABL
LSR
JMP
A,IMM
DIR,X A,L(DIR),Y
ABS
ROL
EOR
JMP
PLY
CLM
A,DIR,X
AND
(ABS) A,ABS
A,ABS,Y
DIR,Y A,L(DIR),Y
DEC
CMP
AND
RTL
INY
A,(DIR),Y A,(DIR) A,(SR),Y
1110
ADC
CLV
BCS
ROL
JMP
ABL
A,IMM
TAY
DIR
ORA
TAD
STA
DIR,Y A,L(DIR),Y
LDX
LDA
C
D
PHY
TYA
BCC
ASL
ABS,b,R A,ABS,X ABS,X A,ABL,X
A,ABS,Y
DEY
DIR
BBC
ADC
DIR,X A,L(DIR),Y
STX
STA
AND
ABS,b,R A,ABS
A,ABS,Y
SEI
BRA
BBS
A
PLA
DIR
ORA
PHG
A,DIR
A
B
LSR
EOR
MVN
ADC
A
EOR
A,SR
BVC
RTS
A,ABS,Y
PHA
A,(DIR),Y A,(DIR) A,(SR),Y DIR,X A,DIR,X
1100
LSR
MVP
A,(DIR),Y A,(DIR) A,(SR),Y DIR,X A,DIR,X
1010
DIR,X A,L(DIR),Y
CLB
ABS,b A,ABS,X ABS,X A,ABL,X
TSA
SEC
BMI
ORA
A,ABL
PLD
BBC
8
9
ROL
DIR,b,R
ADC
7
AND
A,SR
A,(DIR),Y A,(DIR) A,(SR),Y DIR,X A,DIR,X
1000
AND
ABS,b A,ABS
TAS
AND
A,(DIR,X)
0111
A
ABL
ADC
6
DEC
AND
A,(DIR),Y A,(DIR) A,(SR),Y
0110
ORA
A,ABS,Y
AND
EOR
0101
ROL
ASL
ABS
PHD
A,(DIR,X)
EOR
4
A
PLP
A,(DIR),Y A,(DIR) A,(SR),Y DIR,b,R A,DIR,X
0100
ASL
CLC
DIR,X A,L(DIR),Y
2
ABS
0011
ORA
BPL
JSR
0010
ORA
A,IMM
PHP
BRK
7721 Group User’s Manual
APPENDIX
Appendix 7. Hexadecimal instruction code table
INSTRUCTION CODE TABLE-2 (The first word’s code of each instruction is 4216)
D3–D0
D7–D4
0000
Hexadecimal
notation
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
ORA
ORA
ORA
ORA
ORA
ASL
ORA
ORA
B,(DIR,X)
B,SR
B,DIR
B,L(DIR)
B,IMM
B
B,ABS
B,ABL
0
ORA
0001
ORA
ORA
AND
AND
AND
ROL
AND
AND
B,DIR
B,L(DIR)
B,IMM
B
B,ABS
B,ABL
AND
AND
AND
AND
B,ABS,X
B,ABL,X
EOR
EOR
EOR
EOR
LSR
EOR
EOR
B,SR
B,DIR
B,L(DIR)
B,IMM
B
B,ABS
B,ABL
EOR
EOR
EOR
EOR
EOR
EOR
PHB
EOR
TBD
5
ADC
B,DIR,X
B,L(DIR),Y
B,ABS,Y
B,ABS,X
B,ABL,X
ADC
ADC
ADC
ROR
ADC
ADC
B
B,ABS
B,ABL
ADC
ADC
B,ABS,X
B,ABL,X
STA
STA
PLB
6
ADC
B,SR
B,DIR
B,L(DIR)
B,IMM
ADC
ADC
ADC
ADC
TDB
7
STA
B,DIR,X
B,L(DIR),Y
STA
STA
B,ABS,Y
TXB
8
STA
STA
B,SR
B,DIR
B,L(DIR)
STA
STA
STA
9
B,(DIR),Y B,(DIR) B,(SR),Y
LDA
LDA
TYB
LDA
LDA
B,ABS
B,ABL
STA
STA
STA
B,DIR,X
B,L(DIR),Y
B,ABS,Y
B,ABS,X
B,ABL,X
LDA
LDA
LDA
LDA
LDA
B,ABS
B,ABL
A
B,(DIR,X)
TBY
B,IMM
TBX
B,SR
B,DIR
B,L(DIR)
LDA
LDA
LDA
LDA
LDA
LDA
B,L(DIR),Y
B,ABS,Y
B,ABS,X
B,ABL,X
B
B,(DIR),Y B,(DIR) B,(SR),Y
B,DIR,X
CMP
CMP
CMP
CMP
CMP
CMP
CMP
B,(DIR,X)
B,SR
B,DIR
B,L(DIR)
B,IMM
B,ABS
B,ABL
C
CMP
1101
B
EOR
B,(DIR,X)
1100
INC
B,(DIR,X)
STA
1011
AND
B,ABS,Y
4
B,(DIR),Y B,(DIR) B,(SR),Y
1010
AND
B,L(DIR),Y
TSB
ADC
1001
AND
B,DIR,X
3
B,(DIR,X)
1000
ORA
B,ABL,X
AND
ADC
0111
ORA
B,ABS,X
B,SR
B,(DIR),Y B,(DIR) B,(SR),Y
0110
B
AND
EOR
0101
DEC
B,(DIR,X)
B,(DIR),Y B,(DIR) B,(SR),Y
0100
ORA
B,ABS,Y
2
AND
0011
ORA
B,L(DIR),Y
TBS
B,(DIR),Y B,(DIR) B,(SR),Y
0010
ORA
B,DIR,X
1
CMP
CMP
CMP
CMP
CMP
CMP
CMP
B,DIR,X
B,L(DIR),Y
B,ABS,Y
B,ABS,X
B,ABL,X
D
B,(DIR),Y B,(DIR) B,(SR),Y
1110
E
1111
F
SBC
SBC
SBC
SBC
SBC
SBC
SBC
B,(DIR,X)
B,SR
B,DIR
B,L(DIR)
B,IMM
B,ABS
B,ABL
SBC
SBC
SBC
B,(DIR),Y B,(DIR) B,(SR),Y
SBC
SBC
SBC
SBC
SBC
B,DIR,X
B,L(DIR),Y
B,ABS,Y
B,ABS,X
B,ABL,X
7721 Group User’s Manual
17–57
APPENDIX
Appendix 7. Hexadecimal instruction code table
INSTRUCTION CODE TABLE-3 (The first word’s code of each instruction is 8916 )
D3–D0
D7–D4
0000
Hexadecimal
notation
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
MPY
MPY
MPY
MPY
MPY
SR
DIR
L(DIR)
IMM
ABS
ABL
MPY
MPY
MPY
MPY
MPY
MPY
(SR),Y
DIR,X
L(DIR),Y
ABS,Y
ABS,X
ABL,X
DIV
DIV
DIV
DIV
DIV
DIV
MPY
0001
MPY
1
(DIR),Y (DIR)
DIV
0010
XAB
2
(DIR,X)
DIV
0011
DIV
SR
DIR
L(DIR)
IMM
ABS
ABL
DIV
DIV
DIV
DIV
DIV
DIV
(SR),Y
DIR,X
L(DIR),Y
ABS,Y
ABS,X
ABL,X
3
(DIR),Y (DIR)
RLA
0100
4
IMM
0101
5
0110
6
0111
7
1000
8
1001
9
1010
A
1011
B
1100
C
LDT
IMM
1101
D
1110
E
1111
F
17–58
MPY
MPY
(DIR,X)
0
7721 Group User’s Manual
APPENDIX
Appendix 8. Countermeasure against noise
Appendix 8. Countermeasure against noise
General countermeasure examples against noise are described below. Although the effect of these
countermeasure depends on each system, refer to the following when an noise-related problem occurs.
1. Short wiring length
The wiring on a printed circuit board may function as an antenna which feeds noise into the microcomputer.
The shorter the total wiring length (by mm unit), the less possibility of noise insertion into the microcomputer.
______
(1) Wiring for RESET pin
______
Make the length of wiring connected to the RESET
pin as short as possible.
______
In particular, connect a capacitor between the RESET pin and the Vss pin with the shortest possible
wiring (within 20 mm).
______
Reason: If noise is input to the RESET pin, the microcomputer restarts operation before the internal
state of the microcomputer is completely initialized. This may cause a program runaway.
Noise
Reset
circuit
M37721
M37721
Reset
circuit
RESET
Vss
RESET
Vss
Vss
Vss
Not
acceptable
Acceptable
______
Fig. 3 Wiring for RESET pin
(2) Wiring for clock input/output pins
● Make the length of wiring connected to the clock input/output pins as short as possible.
● Make the length of wiring between the grounding lead of the capacitor, which is connected to
the oscillator, and the Vss pin of the microcomputer, as short as possible (within 20 mm).
● Separate the Vss pattern for oscillation from all other Vss patterns. (Refer to “Figure 11.”)
Reason: The microcomputer’s operation
synchronizes with a clock generated
by the oscillation circuit.
If noise enters clock I/O pins, clock
waveforms may be deformed. This
may cause a malfunction or a
program runaway.
Also, if the noise causes a potential
difference between the Vss level of
the microcomputer and the Vss level
of an oscillator, the correct clock
will not be input in the
microcomputer.
Noise
M37721
M37721
XIN
XOUT
Vss
XIN
XOUT
Vss
Not acceptable
Acceptable
Fig. 4 Wiring for clock input/output pins
7721 Group User’s Manual
17–59
APPENDIX
Appendix 8. Countermeasure against noise
(3) Wiring for CNVss pin
Connect CNVss pin to the Vss pin with the shortest possible wiring.
Reason:
The processor mode of the
microcomputer is influenced by a
potential at the CNVss pin when
the CNVss pin and the Vcc or Vss
pin are connected.
If the noise causes a potential
difference between the CNVss pin
and the Vss or Vcc pin, the
processor mode may become
unstable. This may cause a
microcomputer malfunction or a
program runaway.
M37721
Noise
M37721
CNVss
CNVss
Vss
Vss
Not Acceptable
Acceptable
When connecting th e C NVss and Vcc pins, connect
them in the shortest possible distance, also.
Fig. 5 Wiring for CNVss pin
2. Connection of bypass capacitor between Vss and Vcc lines
Connect an approximate 0.1 µ F bypass capacitor as follows:
● Connect a bypass capacitor between the Vss and Vcc pins, at equal lengths.
● The wiring connecting the bypass capacitor between the Vss and Vcc pins should be as short as
possible.
● Use thicker wiring for the Vss and Vcc lines than that for the other signal lines.
Bypass capacitor
Wiring pattern
Wiring pattern
Vcc
Vss
M37721
Fig. 6 Bypass capacitor between Vss and Vcc lines
17–60
7721 Group User’s Manual
APPENDIX
Appendix 8. Countermeasure against noise
3. Wiring for analog input pins, analog power source pins, etc.
(1) Processing for analog input pins
● Connect a resistor to the analog signal line, which is connected to an analog input pin, in series.
Additionally, connect the resistor to the microcomputer as close as possible.
● Connect a capacitor between the analog input pin and the AVss pin, as close to the AVss pin as
possible.
Reason: A signal which is input to the analog input pin is usually an output signal from a sensor.
The sensor, which detects changes in status, is installed far from the microcomputer’s
printed circuit board. Therefore, this long wiring between them becomes an antenna which
picks up noise and feeds it into the microcomputer’s analog input pin.
If a capacitor between an analog input pin and the AVss pin is grounded far away from the
AVss pin, noise on the GND line may enter the microcomputer through the capacitor.
Noise
(Note 2)
Acceptable
M37721
RI
ANi
Thermistor
Not
CI
acceptable
Acceptable
AVss
Reference values
RI : Approximate 100 Ω to 1000 Ω
CI : Approximate 100 pF to 1000 pF
Notes 1 : Design an external circuit for the ANi pin so that charge/discharge is available within
1 cycle of AD.
2 : This resistor and thermistor are used to divide resistance.
Fig. 7 Countermeasure example against noise for analog input pin using thermistor
7721 Group User’s Manual
17–61
APPENDIX
Appendix 8. Countermeasure against noise
(2) Processing for analog power source pins, etc.
● Use independent power sources for the Vcc, AVcc and V REF pins.
● Insert capacitors between the AVcc and AVss pins, and between the V REF and AVss pins.
Reasons: Prevents the A-D converter from noise on the Vcc line.
M37721
Reference values
C1 0.47 µF
C2 0.47 µF
AVcc
VREF
C1
C2
Note : Connect capacitors using the
thickest, shortest wiring possible.
AVss
ANi
(sensor, etc.)
Fig. 8 Processing for analog power source pins, etc.
17–62
7721 Group User’s Manual
APPENDIX
Appendix 8. Countermeasure against noise
4. Oscillator protection
The oscillator, which generates the basic clock for the microcomputer operations, must be protected from
the affect of other signals.
(1) Distance oscillator from signal lines with large current flows
Install the microcomputer, especially the oscillator, as far as possible from signal lines which handle
currents larger than the microcomputer current value tolerance.
Reason: The microcomputer is used in
systems which contain signal lines
for controlling motors, LEDs,
thermal heads, etc. Noise occurs
due to mutual inductance when a
large current flows through the signal
lines.
M37721
Mutual inductance
M
XIN
XOUT
Vss
Large
current
Fig. 9 Wiring for signal lines where large current
flows
(2) Distance oscillator from signal lines with frequent potential level changes
● Install an oscillator and its wiring pattern away from signal lines where potential levels change
frequently.
● Do not cross these signal lines over the clock-related or noise-sensitive signal lines.
Reason: Signal lines with frequently changing
potential levels may affect other
signal lines at a rising or falling edge.
In particular, if the lines cross over
a clock-related signal line, clock
waveforms may be deformed, which
causes a microcomputer malfunction
or a program runaway.
M37721
Do not cross.
✽
XIN
XOUT
Vss
✽ I/O pin for signal with frequently
changing potential levels
Fig. 10 Wiring for signal lines where potential levels
frequently change
(3) Oscillator protection using Vss pattern
Print a Vss pattern on the bottom (soldering
side) of a double-sided printed circuit board,
under the oscillator mount position.
Connect the Vss pattern to the Vss pin of the
microcomputer with the shortest possible wiring,
separating it from other Vss patterns.
An example of Vss pattern on the
underside of an oscillator.
M37721
Mounted pattern
example of
oscillator unit.
XIN
XOUT
Vss
Separate Vss lines for oscillation and supply.
Fig. 11 Vss pattern underneath mounted oscillator
7721 Group User’s Manual
17–63
APPENDIX
Appendix 8. Countermeasure against noise
5. Setup for I/O ports
Setup I/O ports by hardware and software as follows:
<Hardware protection>
● Connect a resistor of 100 Ω or more to an I/O port in series.
<Software protection>
● Read the data of an input port several times to confirm that input levels are equal.
● Since the output data may reverse because of noise, rewrite data to the output port’s Pi register
periodically.
● Rewrite data to port Pi direction registers periodically.
Data bus
Noise
Direction register
Port latch
Port
Fig. 12 Setup for I/O ports
6. Reinforcement of the power source line
● For the Vss and Vcc lines, use thicker wiring than that of other signal lines.
● When using a multilayer printed circuit board, the Vss and Vcc patterns must each be one of the middle
layers.
● The following is necessary for double-sided printed circuit boards:
•On one side, the microcomputer is installed at the center, and the Vss line is looped or meshed around
it. The vacant area is filled with the Vss line.
•On the opposite side, the Vcc line is wired the same as the Vss line.
•The power source lines of external devices which are connected by bus to the microcomputer must be
connected to the microcomputer's power source lines with the shortest possible wiring.
Reasons: With external devices connected to the microcomputer, the levels of many of the signal lines
(total external address buses: 24 bits) may change simultaneously, causing noise on the power
source line.
17–64
7721 Group User’s Manual
APPENDIX
Appendix 9. 7721 Group Q & A
Appendix 9. 7721 Group Q & A
Information which may be helpful in fully utilizing the 7721 Group is provided in Q & A format.
In Q & A, as a rule, one question and its answer are summarized within one page. The upper box on each
page is a question, and a box below the question is its answer. (If a question or an answer extends to two
or more pages, there is a page number at the lower right corner.)
At the upper right corner of each page, the main function related to the contents of description in that page
is listed.
7721 Group User’s Manual
17–65
APPENDIX
Appendix 9. 7721 Group Q & A
SFR
Q
Is there any SFR to which a certain instruction cannot be used for writing ?
A
(1) Use the LDM or STA instruction to write to the registers or the bits listed below.
Do not use read-modify-write instructions (i.e., CLB, SEB, ASL, ASR, DEC, INC, LSR,
ROL, and ROR).
Pulse output data register 0, 1 (addresses 1A 16, 1C16)
UART0, 1 baud rate register (addresses 3116, 39 16)
UART0, 1 transmit buffer register (addresses 3316, 32 16, 3B16, 3A 16)
Timer A2–A4 two-phase pulse signal processing select bit (bits 5–7 at address 44 16)
Timer A2–A4 register (addresses 4A 16–4F 16 ; one-shot pulse mode or pulse width
modulation mode)
Refresh timer (address 6616)
(2) Use the SEB or CLB instruction to write to the following register.
DMAC control register H (address 69 16 ; when any of bits 4 to 7 = “1”)
17–66
7721 Group User’s Manual
APPENDIX
Appendix 9. 7721 Group Q & A
Reset, STP instruction, WIT instruction
Q
Is it possible to distinguish power-on reset from hardware reset for terminating the stop or wait mode
?
A
The contents of the internal RAM is undefined after power-on reset. On the other hand, the contents
of the internal RAM are retained when performing hardware reset in the stop or wait mode with Vcc
≥ 2 V.
Accordingly, write a certain data to the internal RAM before executing STP or WIT instruction, and
judge by checking the contents of the internal RAM after hardware reset.
7721 Group User’s Manual
17–67
APPENDIX
Appendix 9. 7721 Group Q & A
Interrupt
Q
If an interrupt request (b) occurs while executing an interrupt routine (a), is it true that the main routine
is not executed at all from when the execution of the interrupt routine (a) is completed until the
execution of the INTACK sequence for the next interrupt (b) starts?
Sequence of
execution
?
RTI instruction
Interrupt routine (a)
INTACK sequence
for interrupt (b)
Main routine
Conditions:
● I is cleared to “0” by executing the RTI instruction.
● Iinterrupt priority level of interrupt (b) is higher than IPL of main routine.
● Interrupt priority detection time is 2 cycles of φ.
A
Sampling for interrupt requests is performed by sampling pulses generated synchronously with the
CPU’s op-code fetch cycles.
for the RTI instruction is gener(1) If the next interrupt request (b) occurs before sampling pulse
ated, the microcomputer executes the INTACK sequence for (b) without executing the main routine (not even one instruction). It is because that sampling is completed while executing the RTI
instruction.
Interrupt request (b)
➀
Sampling pulse
RTI instruction
Interrupt routine (a)
INTACK sequence for interrupt (b)
(2) If the next interrupt request (b) occurs immediately after sampling pulse ➀ is generated, the
microcomputer executes one instruction of the main routine before executing the INTACK
sequence for (b). It is because that the interrupt request is sampled by the next sampling
pulse ➁.
Interrupt request (b)
➁
➀
Sampling pulse
RTI instruction One instruction executed
Interrupt routine (a)
17–68
Main routine
7721 Group User’s Manual
INTACK sequence
for interrupt (b)
APPENDIX
Appendix 9. 7721 Group Q & A
Interrupt
Q
Suppose that there is a routine which should not accept one certain interrupt request. (The other
interrupt request are acceptable).
Although when the interrupt priority level select bits for the above interrupt are set to “0002,” in other
words, when this interrupt is set to be disabled, this interrupt request is actually accepted immediately
after change of the priority level. Why did this occur and what should I do about it?
Interrupt request is
accepted in this
interval
:
LDM #00H, XXXIC ; Writes “0002” to interrupt priority level select bits.
; Clears interrupt request bit to “0.”
LDA A,DATA
; Instruction at the beginning of the routine which
should not accept one certain interrupt request.
:
;
A
As for the change of the interrupt priority level, when the following are met, the microcomputer may
pretend to accept an interrupt request immediately after this interrupt is set to be disabled:
•The next instruction (in the above example, it is the LDA instruction) is already stored into a instruction queue buffer for the BIU.
•Conditions for accepting the instruction which should not be accepted are satisfied immediately
before the next instruction in the instruction queue buffer is executed.
When writing to a memory or an I/O, the CPU passes the address and data to the BIU. Then, the
CPU executes the next instruction in the instruction queue buffer while the BIU is writing data into
the actual address. Detection of interrupt priority level is performed at the beginning of each instruction.
In the above case, the CPU executes the next instruction before the BIU completes the change of
the interrupt priority level. Therefore, when the interrupt priority level is detected synchronously with
the execution of the next instruction, the interrupt priority level before the change is detected and its
interrupt request is accepted.
Interrupt request generated
Interrupt request accepted
Sequence of execution
Interrupt priority detection time
CPU operation
Previous instruction
executed
BIU operation
(Instruction prefetched)
LDM instruction
executed
LDA instruction
executed
Interrupt priority level select bits set
Change of interrupt priority levels
completed
(1/2)
7721 Group User’s Manual
17–69
APPENDIX
Appendix 9. 7721 Group Q & A
Interrupt
A
To prevent this problem, after change of the interrupt priority level is completed, use software to
execute the routine that should not accept a certain interrupt request. The following shows a sample
program.
[ Sample program ]
After an instruction which writes “0002” to the interrupt priority level select bits, fill the instruction
queue buffer with the NOP instruction to make the next instruction not to be executed before the
writing is completed.
:
LDM #00H, XXXIC
NOP
NOP
NOP
LDA A,DATA
:
; Sets the interrupt priority level select bits to “000 2.”
;
;
;
; Instruction at the beginning of the routine that should not accept a certain
interrupt request
(2/2)
17–70
7721 Group User’s Manual
APPENDIX
Appendix 9. 7721 Group Q & A
Interrupt
Q
____
(1) Which timing of clock φ 1 is the external interrupts (input
signals to the INTi pin) detected?
____
(2) How can four or more external interrupt input pins (INT i) be used?
A
(1) In both the edge
sense and level sense, external interrupt requests occur when the input
____
signal to the INT i pin changes its level. This is independent of clock φ 1.
In the edge sense, the interrupt request bit is set to “1” at this time.
(2) There are two methods: one uses external interrupt’s level sense, and the other uses the
timer’s event counter mode.
➀ Method using external interrupt’s level sense
As for hardware, input a logical sum of multiple interrupt signals (e.g., ‘a’, ‘b’, and ‘c’) to the
____
INTi pin, and input each signal to each corresponding
port.
___
As for software, check the ports’ input levels in the INTi interrupt routine in order to detect
which signal (‘a’, ‘b’, or ‘c’) was input.
M37721
Port
Port
Port
a
b
c
INTi
➁ Method using timer’s event counter mode
As for hardware, input interrupt signals to the TAi IN pins or TBi IN pins.
As for software, set the timer’s operating mode to the event counter mode. Then, set a value
“0000 16” into the timer register and select the valid edge.
The timer’s interrupt request occurs when an interrupt signal (selected valid edge) is input.
7721 Group User’s Manual
17–71
APPENDIX
Appendix 9. 7721 Group Q & A
Stack, DRAM
Q
What are there the stack bank select bit (bit 7 at address 5E16) for?
A
It is supposed that DRAM is used as the stack area.
When connecting DRAM, the stack pointer addressing mode or stack operation instruction etc.
can be used. It is because all of 64 Kbytes can be used as the stack area when bank FF16 which
is assigned to DRAM is set as the stack area.
(The internal RAM also functions as the temporary area or the register file which is accessed
frequently because the internal RAM can be accessed with no Wait. Accordingly, it is expected
that the capacity will lack to be used as the stack area. As for the M37721, DRAM area can be
set as the stack area because cheap DRAM can be connected.)
Use bank 0 which is assigned to the internal RAM area as the stack area when DRAM is not
connected or the internal RAM is sufficient to be used as the stack area.
17–72
7721 Group User’s Manual
APPENDIX
Appendix 9. 7721 Group Q & A
DRAM, WIT instruction
Q
Are there methods to refresh DRAM in the wait mode?
7721 Group User’s Manual
17–73
APPENDIX
Appendix 9. 7721 Group Q & A
A
In the wait mode, DRAM refresh function does not operate, but the watchdog timer, timer A, and
timer B operate. Accordingly, DRAM can be refreshed by using these timers and ports.
(1) Method using watchdog timer
Return from the wait mode by the watchdog
5 by
timer interrupt. Control ports
P104, P10
____
____
software and perform the CAS-before-RASrefresh.
Interval of watchdog timer interrupt
f(X IN)
f 32 selected
f512 selected
25 MHz
2.621 ms
41.943 ms
16 MHz
4.096 ms
65.536 ms
Example 1: A case in 1024 refresh cycles, every 16.4 ms, f(XIN) = 16 MHz, watchdog timer
count source = f 32
•DRAM refresh is performed 256 times. This refresh is performed by every
watchdog timer interrupt. (See flow chart ➀.)
Flow chart ➀
Watchdog timer
interrupt routine
Main routine
Watchdog timer frequency ← “1”
select bit (bit 0 at address 6116)
Watchdog timer count
source: f32 selected
Bits 4, 5 of port P10 register ← “1”
(address 16 16)
Bit 4 of port P10 register ← “0”
(address 1616)
Port P104 (CAS):
“L” level output
Bit 5 of port P10 register ← “0”
(address 1616)
Port P105 (RAS):
“L” level output
Bit 4 of port P10 register ← “1”
(address 1616)
Port P104 (CAS):
“H” level output
Bit 5 of port P10 register ← “1”
(address 1616)
(RAS)
Port P105 (RAS):
“H” level output
Ports P104, P105:
“H” level output
Bits 4, 5 of port P10 direction← “1”
register (address 1816)
DRAM validity bit
← “0”
(bit 7 at address 6416)
DRAMC stopped
WIT instruction
Wait mode
256 times ?
N
Y
Wait mode completed ?
N
RTI
Y
Return to main routine
Note: By using 1 bit of RAM, judge
whether this interrupt is for return
from the wait mode or for refresh.
(1/2)
17–74
7721 Group User’s Manual
APPENDIX
Appendix 9. 7721 Group Q & A
DRAM, WIT instruction
A
(2) Method using timer A or timer B
Return from the wait mode by a timer A ( or timer
B) interrupt
every definite time. Control
____
____
ports P104, P105 by software and perform the CAS-before-RAS-refresh.
Example 2: A case in 512 refresh cycles, every 64 ms, f(XIN) = 25 MHz, timer A0 used
•DRAM refresh is performed 512 times by timer A0 interrupts. This interrupt
occurs every 64 ms. (See flow chart ➁.)
Flow chart ➁
Main routine
Timer A0
interrupt routine
Bits 4, 5 of port P10 register ← “1”
(address 1616)
Bit 4 of port P10 register ← “0”
(address 1616)
Port P104 (CAS):
“L” level output
Bit 5 of port P10 register ← “0”
(address 1616)
Port P105 (RAS):
“L” level output
Ports P104, P105:
“H” level output
Bits 4, 5 of port P10 direction ← “1”
register (address 1816)
DRAM validity bit
← “0”
(bit 7 at address 6416)
DRAMC stopped
Bit 4 of port P10 register ← “1”
(address 1616)
Port P104 (CAS):
“H” level output
Timer A0 mode ← “110000002”
register (address 5616)
f512 counted
Bit 5 of port P10 register ← “1”
(address 1616)
Port P105 (RAS):
“H” level output
Timer A0 register ← 3124
(addresses 4716, 4616)
Timer value set:
One cycle = 64 ms
512 times ?
Interrupt priority level set:
Timer A0 interrupt ← “XXXX00012” Level 1 or more (Interrupt
control register (address 7516)
enabled)
N
Y
RTI
Return to main routine
Timer A0 count start ← “1” Timer A0 count started
bit (bit 0 at address 4016)
Interrupt enable flag I ← “0”
Interrupt enabled
WIT instruction
Wait mode
Wait mode completed ?
Y
N
Note: By using 1 bit of RAM, judge
whether this interrupt is for return
from the wait mode or for refresh.
(2/2)
7721 Group User’s Manual
17–75
APPENDIX
Appendix 9. 7721 Group Q & A
DRAM
Q
How is the program execution time affected when using DRAM ?
A
When the M37721 uses DRAM, the execution time is affected as follows:
•CPU stops and DRAM refresh cycle is inserted.
•1-bus cycle becomes 3φ when accessing DRAM.
(1) Refresh method of the M37721’s DRAMC is the dispersion refresh and 5 cycles of φ are
necessary for one refresh. The rate occupied by the DRAM refresh cycle during the program
execution time is described below.
Rate occupied by DRAM refresh cycle during program execution time
Rate occupied by DRAM refresh cycle
Refresh interval
f(X IN) = 25 MHz
f(X IN) = 16 MHz
15.625 µ s
(Case of 512 refresh cycles, every 8 ms)
125 µ s
2.6 %
4.2 %
0.3 %
0.5 %
(Case of 512 refresh cycles, every 64 ms)
(2) The comparison results of two sample programs’ execution times are listed below; one is for
the case where SRAM is used and the other is for the case where DRAM is used.
Use conditions : Execution program
f(X IN)
External data bus width
Refresh interval
Memory used as work area
SRAM
SRAM
DRAM (bank FF 16)
DRAM (bank FF 16)
Sample program B (See (2/2))
16 MHz
16 bits
13 µ s
Software wait valid area
Nothing
ROM and RAM
Nothing
ROM
Execution time
3.4 ms
5.0 ms
3.9 ms
5.2 ms
Speed comparison
1.00
1.47
1.15
1.53
(1/2)
17–76
7721 Group User’s Manual
APPENDIX
Appendix 9. 7721 Group Q & A
DRAM
A
●Sample program B
LOOP0:
LOOP1:
SEP
CLM
.DATA
.INDEX
LDY
LDX
ASL
SEM
.DATA
ROL
ROL
CLM
.DATA
ROR
DEX
DEX
DEX
BNE
STA
SEM
.DATA
STA
CLM
.DATA
DEY
DEY
DEY
BNE
X
16
8
#69
#69
SOUR, X
8
SOUR+2, X
B
16
A
LOOP1
A, DEST, Y
8
B, DEST+2, Y
16
LOOP0
✽ SOUR, DEST : Work areas
(2/2)
7721 Group User’s Manual
17–77
APPENDIX
Appendix 9. 7721 Group Q & A
Watchdog timer
Q
When detecting the software runaway by the watchdog timer, if the same value as the contents
of the reset vector address is set to the watchdog timer interrupt vector address, not performing
software reset, how does it result in?
When branching to the reset branch address within the watchdog timer interrupt routine, how
does it result in?
A
The CPU registers and the SFR are not initialized in the above-mentioned way. Accordingly,
the user must initialize all of them by software.
Note that the processor interrupt priority level (IPL) retains “7” of the watchdog timer interrupt
priority level and is not initialized. Consequently, all interrupt requests cannot be accepted.
When rewriting the IPL by software, save once the 16-bit immediate value to the stack area
and then restore that 16-bit immediate value to all bits of the processor status register (PS).
When a software runaway occurs, we recommend to use software reset in order to initialize
the microcomputer.
17–78
7721 Group User’s Manual
APPENDIX
Appendix 10. Differences between 7721 Group and 7720 Group
Appendix 10. Differences between 7721 Group and 7720 Group
Table 2 Differences between M37721S2BFP and M37720S1AFP
M37721S2BFP
Item
1024 bytes (Note)
Internal RAM size
M37720S1AFP
512 bytes
16 MHz (maximum)
Instruction execution time (minimum)
160 ns
250 ns
Bit configuration of
4 bits ✕ 2 channels, or
4 bits ✕ 2 channels
real–time output channel
Port latch state after
6 bits ✕ 1channel and 2 bits ✕ 1channel
Retains the value before using Undefined
real-time output
output
25 MHz (maximum)
Real-time
External clock input frequency
using real-time output
Serial I/O
Limitation for instruction used when writing Nothing (LDM, STA instructions Exists (LDM, STA instructions
can be used.)
cannot be used.)
to interrupt control register
Timing when overrun error flag
One of the following:
becomes “0”
•When setting the receive enable •When setting the receive
bit to “0”
enable bit to “0”
One of the following:
•When setting the serial I/O mode •When setting the serial I/O
select bits to “000 2”
mode select bits to “0002”
•When reading the receive
buffer register
____
Conditions for outputting “L” of RTS When all of the following are When all of the following are
satisfied:
signal in clock synchronous serial I/O satisfied:
•Receive enable bit = “1”
•Receive enable bit = “1”
mode
•Reception is stopped.
•Reception is stopped.
DMA shortest transfer rate
•Dummy data is present in the
transmit buffer register
12.5 Mbytes/sec
8 Mbytes/sec
(At 1-bus cycle transfer)
Note: 512 bytes can be selected by software. For the M37721S1BFP, its internal RAM size is 512 bytes.
7721 Group User’s Manual
17–79
APPENDIX
Appendix 11. Electrical characteristics
Appendix 11. Electrical characteristics
The electrical characteristics of the M37721S2BFP are described below.
For the latest data, inquire of addresses described last (☞“CONTACT ADDRESSES FOR FURTHER
INFORMATION”).
Absolute maximum ratings
Parameter
Symbol
Conditions
VCC
Power source voltage
AVCC
Analog power source voltage
______
Input voltage
RESET , CNV SS, BYTE
Input voltage
A 8/D 8–A 15 /D 15 , A 16 /D 0–A 23 /D 7 ,
VI
VI
P4 3–P4 7, P50–P5 7, P60–P67,
P7 0–P77, P8 0–P87, P9 0–P97,
____
Ratings
–0.3 to 7
Unit
–0.3 to 7
V
–0.3 to 12
V
–0.3 to V CC+0.3
V
–0.3 to V CC+0.3
V
300
mW
–20 to 85
–40 to 150
°C
°C
V
_____
P100–P107, RDY, HOLD, X IN, VREF
VO
Output voltage
A0/MA0–A7/MA7, A8/D 8–A15/D15,
A16/D0–A23/D7, P4 3–P4 7,
P5 0 –P5 7 , P6 0 –P6 7 , P7 0–P7 7 ,
P80–P8
7, P90–P9 7, P100–P107,
________
__
φ 1, RESET____
OUT , X OUT , E, ST0,
____
__
ST1, ALE, BLE, BHE, R/W
Topr
Power dissipation
Operating temperature
Tstg
Storage temperature
Pd
17–80
Ta = 25 °C
7721 Group User’s Manual
APPENDIX
Appendix 11. Electrical characteristics
Recommended operating conditions (V CC = 5 V ± 10 %, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
Typ.
Max.
5.0
4.5
5.5
Power source voltage
Vcc
V
Vcc
Analog power source voltage
AVcc
V
0
Power source voltage
Vss
V
0
Analog power source voltage
AVss
V
High-level input voltage P43–P47, P50–P57, P60–P67, P70____
VIH
–P77,
0.8 Vcc
Vcc
V
P8
0
–P8
7
,
P9
0
–P9
7
,
P10
0
–P10
7
,
RDY,
_____
______
HOLD, BYTE, CNVss, RESET, XIN, VREF
0.5 Vcc
Vcc
VIH
High-level input voltage A8/D8–A 15/D15, A16/D0–A 23/D7
V
VIL
Low-level input voltage
P43–P47, P50–P57, P60–P67, P70____
–P77,
P8
0
–P8
7
,
P9
0
–P9
7
,
P10
0
–P10
7
,
RDY,
_____
______
0
0.2 Vcc
V
HOLD, BYTE, CNVSS, RESET, X IN,
VREF
0
0.16 Vcc
VIL
Low-level input voltage
V
A8/D8–A 15/D15, A16/D0–A 23/D7
I OH (peak) High-level peak output current A0/MA0–A 7/MA 7, A8/D8–A15/D15,
A16/D 0–A 23/D 7, P43–P4 7, P50–P5 7,
–10
mA
7,
P6 0–P6 7, P70–P77, P8 0–P8
________
P90–P9 7, P100–P10
7
,
φ
1
,
RESET
OUT
,
____ ____
__
ST0, ST1, ALE, BLE, BHE, R/W
I OH (avg) High-level average output A0/MA0–A 7/MA 7, A8/D8–A15/D15,
current
A16/D 0–A 23/D 7, P43–P47, P50–P5 7,
–5
mA
7,
P6 0–P67, P7 0–P7 7, P8 0–P8
_________
P90–P9 7, P100–P10
7
,
φ
1
,
RESET
OUT
,
____ ____
__
ST0, ST1, ALE, BLE, BHE, R/W
I OL (peak) Low-level peak output current A0/MA0–A 7/MA 7, A8/D8–A15/D15,
A16/D 0–A 23/D 7, P43–P47, P50–P5 7,
10
7,
P6 0–P67, P7 0–P7 7, P8 0–P8
mA
_________
P90–P9 7, P100–P10
7 , φ 1 , RESET
OUT,
____ ____
__
ST0, ST1, ALE, BLE, BHE, R/W
I OL (avg) Low-level average
A0/MA0–A 7/MA 7, A8/D8–A15/D15,
output current
A16/D 0–A 23/D 7, P43–P47, P50–P5 7,
5
7,
P6 0–P67, P7 0–P7 7, P8 0–P8
mA
_________
P90–P9 7, P100–P10
7
,
φ
1
,
RESET
OUT
,
____ ____
__
ST0, ST1, ALE, BLE, BHE, R/W
25
f(X IN)
External clock input frequency
MHz
Notes 1: Average output current is the average value of a 100 ms interval.
____
2: ____
The sum of IOL(peak)
for P8, P9, A 0/MA 0–A 7/MA7, A8/D8–A 15/D 15, A 16/D0–A 23/D7, ST0, ST1, ALE, BLE,
__
BHE, and R/W must be 80 mA or less;
the sum of IOH(peak)
for P8, P9, A 0/MA 0–A 7/MA 7 , A 8/D 8–
____ ____
__
A15/D 15, A 16/D 0–A 23/D 7, ST0, ST1, ALE, BLE, BHE, and R/W must be 80 mA or less; the sum of
IOL(peak) for P4, P5, P6, P7, P10, and φ1 must be 80 mA or less; the sum of IOH(peak) for P4, P5, P6,
P7, P10, and φ 1 must be 80 mA or less.
7721 Group User’s Manual
17–81
APPENDIX
Appendix 11. Electrical characteristics
Electrical characteristics (VCC = 5 V, V SS = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz, unless otherwise noted)
Limits
Parameter
Symbol
Test conditions Min. Typ. Max. Unit
VOH
High-level output A0/MA0–A7/MA7, A8/D8–A15/D15, A16/D0–A23/D7, P43–
voltage
P47, P50–P57, P60–P67, P70–P77,_________
V
3
I OH = –10 mA
P80–P87, P9____
0–P97,____
P100–P10
7, φ1, RESETOUT, ST0,
__
ST1, ALE, BLE, BHE, R/W
VOH
High-level output A0/MA____
0–A 7/MA
7, A8/D8–A15/D15, A16____
/D0–A____
23/D7, MA
8,
____
__
V
4.7
I OH = –400 µ A
voltage
MA9, RAS, CAS, φ 1, ST0, ST1, BLE, BHE, R/W
VOH
High-level output ALE
3.1
I OH = –10 mA
V
voltage
4.8
I OH = –400 µ A
__
VOH
3.4
I OH = –10 mA
High-level output E
V
voltage
I OH = –400 µ A
4.8
VOL
Low-level output A0/MA 0–A7/MA7, A8/D8–A 15/D15,
voltage
A16/D0–A23/D 7, P43–P47, P50–P57, P60–P67,
V
2
I OL = 10 mA
P7
0 –P7 7 , P8 0 –P8 7 , P9 0 –P9____
7 , P10
0 –P10 __
7, φ 1,
________
____
RESETOUT, ST0, ST1, ALE, BLE, BHE, R/W
VOL
Low-level output A0/MA 0–A7/MA7, A8/D8–A____
15/D 15,____
V
0.45
voltage
A
16
/D
0
–A
23
/D
7
,
MA
8
,
MA
9
,
RAS,
CAS, φ1, ST0, ST1, I OL = 2 mA
____ ____
__
BLE, BHE, R/W
VOL
1.9
Low-level output ALE
I OL = 10 mA
V
0.43
voltage
I OL = 2 mA
__
VOL
1.6
I OL = 10 mA
Low-level output E
V
0.4
voltage
I OL = 2 mA
_____ ____
____ ____
VT+–VT– Hysteresis
HOLD, RDY,
IN–TA4IN, TB0IN, TB1IN, INT0–INT2,
_____
____ TA2
____
V
1
AD
TRG , CTS0, CTS 1 , CLK 0, CLK 1,
0.4
________
________
___
DMAREQ0–DMAREQ3,
TC
______
VT+–VT– Hysteresis
V
0.5
RESET
0.2
V
VT+–VT– Hysteresis
0.3
XIN
0.1
I IH
High-level input
A8/D8–A15/D15, A 16/D0–A 23/D7, P43–P47, P5 0–P5 7,
0–P8 7,
P60–P67, P70–P77, P8____
current
_____
5 µA
VI = 5 V
P90–P9
7
,
P10
0
–P10
7
,
RDY,
HOLD, BYTE, CNVss,
______
XIN, RESET
I IL
A8/D8–A15/D15, A 16/D0–A 23/D7, P43–P47, P5 0–P5 7,
Low-level input
–5 µA
0–P67, P70–P77, P80–P87, P90–P9
7, P100–P107, V I = 0 V
P6
current
____ _____
______
RDY, HOLD, BYTE, CNVss, XIN, RESET
VRAM
V
RAM hold voltage
2
When clock is stopped.
Icc
Power source current
f(XIN) = 25 MHz (Square
54 mA
27
waveform)
Ta = 25 °C (when clock
is stopped)
Ta = 85 °C (when clock
is stopped)
1
µA
20
µA
A-D CONVERTER CHARACTERISTICS (V CC = 5 V, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz, unless otherwise noted)
Limits
Unit
Symbol
Test conditions
Parameter
Min. Typ. Max.
Resolution
—
V REF = V CC
8 Bits
V REF = V CC
—
Absolute accuracy
±3 LSB
2
V REF = V CC
R LADDER Ladder resistance
10 kΩ
9.12
t CONV
Conversion time
µs
2
VREF
Reference voltage
VCC V
0
VIA
Analog input voltage
VREF V
17–82
7721 Group User’s Manual
APPENDIX
Appendix 11. Electrical characteristics
Internal peripheral devices’ timing requirements (V CC = 5 V ± 10 %, V SS = 0 V, Ta = –20 to 85 °C,
f(X IN) = 25 MHz, unless otherwise noted)
Note: The limits depend on f(XIN). Table 3 lists calculation formulas for the limits.
Timer A input (Count input in event counter mode)
Symbol
t c(TA)
t w(TAH)
t w(TAL)
Parameter
TAj IN input cycle time
TAj IN input high-level pulse width
TAj IN input low-level pulse width
Limits
Min. Max.
80
40
40
Unit
ns
ns
ns
Timer A input (Gating input in timer mode)
Symbol
t c(TA)
t w(TAH)
t w(TAL)
Parameter
TAj IN input cycle time
TAj IN input high-level pulse width
TAj IN input low-level pulse width
Limits
Min. Max.
(Note)
320
(Note)
160
(Note)
160
Unit
ns
ns
ns
Timer A input (External trigger input in one-shot pulse mode)
Symbol
t c(TA)
t w(TAH)
t w(TAL)
Parameter
TAj IN input cycle time
TAj IN input high-level pulse width
TAj IN input low-level pulse width
Limits
Min. Max.
(Note)
160
80
80
Unit
ns
ns
ns
Timer A input (External trigger input in pulse width modulation mode)
Symbol
t w(TAH)
t w(TAL)
Parameter
TAj IN input high-level pulse width
TAj IN input low-level pulse width
Limits
Min. Max.
80
80
Unit
ns
ns
Timer A input (Up-down input in event counter mode)
Symbol
tc(UP)
tw(UPH)
tw(UPL)
tsu(UP-TIN)
th(TIN-UP)
Parameter
TAj OUT
TAj OUT
TAj OUT
TAj OUT
TAj OUT
input
input
input
input
input
cycle time
high-level pulse width
low-level pulse width
setup time
hold time
Limits
Min. Max.
2000
1000
1000
400
400
Unit
ns
ns
ns
ns
ns
Timer A input (Two-phase pulse input in event counter mode)
Symbol
Parameter
t c(TA)
TAj IN input cycle time
tsu(TAjIN–TAjOUT) TAj IN input setup time
tsu(TAjOUT–TAjIN) TAj OUT input setup time
7721 Group User’s Manual
Limits
Min. Max.
800
200
200
Unit
ns
ns
ns
17–83
APPENDIX
Appendix 11. Electrical characteristics
Internal peripheral devices
•Count input in event counter mode
•Gating input in timer mode
•External trigger input in one-shot pulse mode
•External trigger input in pulse width modulation mode
tc(TA)
tw(TAH)
TAjIN input
tw(TAL)
•Up-down input and count input in event counter mode
tc(UP)
tw(UPH)
TAjOUT input
(Up-down input)
tw(UPL)
TAjOUT input
(Up-down input)
TAjIN input
(When counted at falling edge)
th(TIN-UP)
tsu(UP-TIN)
TAjIN input
(When counted at rising edge)
•Two-phase pulse input in event counter mode
tc(TA)
TAjIN input
tsu(TAjIN-TAjOUT)
tsu(TAjIN-TAjOUT)
tsu(TAjOUT-TAjIN)
TAjOUT input
tsu(TAjOUT-TAjIN)
Test conditions
•Vcc = 5 V ± 10 %
•Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
17–84
7721 Group User’s Manual
APPENDIX
Appendix 11. Electrical characteristics
Timer B input (Count input in event counter mode)
Symbol
tc(TB)
tw(TBH)
tw(TBL)
tc(TB)
tw(TBH)
tw(TBL)
Parameter
TBj IN
TBj IN
TBj IN
TBj IN
TBjIN
TBj IN
input
input
input
input
input
input
cycle time (one edge count)
high-level pulse width (one edge count)
low-level pulse width (one edge count)
cycle time (both edges count)
high-level pulse width (both edges count)
low-level pulse width (both edges count)
Limits
Min. Max.
80
40
40
160
80
80
Unit
ns
ns
ns
ns
ns
ns
Timer B input (Pulse period measurement mode)
Symbol
t c(TB)
t w(TBH)
t w(TBL)
Parameter
TBj IN input cycle time
TBj IN input high-level pulse width
TBj IN input low-level pulse width
Limits
Min. Max.
(Note)
320
(Note)
160
(Note)
160
Unit
Limits
Min. Max.
(Note)
320
(Note)
160
(Note)
160
Unit
ns
ns
ns
Timer B input (Pulse width measurement mode)
Symbol
t c(TB)
t w(TBH)
t w(TBL)
Parameter
TBj IN input cycle time
TBj IN input high-level pulse width
TBj IN input low-level pulse width
ns
ns
ns
A-D trigger input
Symbol
tc(AD)
tw(ADL)
Parameter
AD TRG input cycle time (trigger enabled minimum)
AD TRG input low-level pulse width
Limits
Min. Max.
1000
125
Unit
ns
ns
Serial I/O
Symbol
tc(CK)
tw(CKH)
tw(CKL)
td(C–Q)
th(C–Q)
tsu(D–C)
th(C–D)
Parameter
CLKi
CLKi
CLKi
TxDi
TxDi
RxDi
RxDi
input cycle time
input high-level pulse width
input low-level pulse width
output delay time
hold time
input setup time
input hold time
Limits
Min. Max.
200
100
100
80
0
20
90
Unit
ns
ns
ns
ns
ns
ns
ns
____
External interrupt INTi input
Symbol
Parameter
____
tw(INH)
tw(INL)
INTi input high-level pulse width
INTi input low-level pulse width
____
7721 Group User’s Manual
Limits
Min. Max.
250
250
Unit
ns
ns
17–85
APPENDIX
Appendix 11. Electrical characteristics
Internal peripheral devices
tc(TB)
tw(TBH)
TBjIN input
tw(TBL)
tc(AD)
tw(ADL)
ADTRG input
tc(CK)
tw(CKH)
CLKi input
tw(CKL)
th(C-Q)
TxDi output
td(C-Q)
tsu(D-C)
RxDi input
tw(INL)
INTi input
tw(INH)
Test conditions
•Vcc = 5 V ± 10 %
•Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
•Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
17–86
7721 Group User’s Manual
th(C-D)
APPENDIX
Appendix 11. Electrical characteristics
Ready and Hold
Timing requirements (Vcc = 5 V ± 10 %, Vss = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz, unless otherwise noted)
Limits
Parameter
Symbol
Min.
Max.
____
tsu(RDY–φ1) RDY
input setup time
55
_____
tsu(HOLD–φ1) ____
HOLD input setup time
55
th(φ1–RDY)
RDY
input
hold
time
0
_____
th(φ1–HOLD) HOLD input hold time
0
Unit
ns
ns
ns
ns
Switching characteristics (Vcc = 5 V ± 10 %, Vss = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz, unless otherwise noted)
Limits
Parameter
Unit
Symbol
Min. Max.
ns
td(φ1–STi)
ST0, ST1 output delay time
40
Note: Figure 13 shows the test circuit.
7721 Group User’s Manual
17–87
APPENDIX
Appendix 11. Electrical characteristics
•Ready function
With no Wait
1
E output
RDY input
tsu(RDY-
1)
th(
1-RDY)
With Wait
1
E output
RDY input
tsu(RDY-
1)
th(
1-RDY)
th(
1-HOLD)
Test conditions
•Vcc = 5 V ± 10 %
•Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
•Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
•Hold function
1
tsu(HOLD-
1)
HOLD input
td(
1-STi)
STi output
Test conditions
•Vcc = 5 V ± 10 %
•Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
•Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
17–88
7721 Group User’s Manual
td(
1-STi)
APPENDIX
Appendix 11. Electrical characteristics
Microprocessor mode : with no Wait
Note: The limits depend on f(X IN). Table 4 lists calculation formulas for the limits.
Timing requirements (V CC = 5 V ± 10 %, V SS = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz, unless otherwise noted)
Limits
Symbol
Unit
Parameter
Min. Max.
ns
tc
External clock input cycle time
40
ns
t w(H)
External clock input high-level pulse width
15
ns
t w(L)
External clock input low-level pulse width
15
tr
External clock input rising time
8 ns
tf
External clock input falling time
8 ns
ns
t su(PiD–E)
Port Pi input setup time (i = 4–10)
60
ns
t h(E–PiD)
Port Pi input hold time (i = 4–10)
0
Switching characteristics (V CC = 5 V ± 10 %, V SS = 0 V, Ta = –20 to 85 °C, f(X IN) = 25 MHz, unless otherwise noted)
Limits
Symbol
Parameter
Min. Max.
t d(E-PiQ)
Port Pi data output delay time (i = 4–10)
80
t d(AL–E)
(Note)
Address low-order output delay time
15
t d(E–DHQ)
Data high-order output delay time (BYTE = “L”)
35
t pxz(E–DHZ) Data high-order floating start delay time (BYTE = “L”)
0
t d(AM–E)
(Note)
Address middle-order output delay time
15
t d(AM–ALE) Address middle-order output delay time
(Note)
5
t d(E–DLQ)
Data low-order output delay time
35
t pxz(E–DLZ) Data low-order floating start delay time
0
t d(AH–E)
Address high-order output delay time
(Note)
15
t d(AH–ALE) Address high-order output delay time
(Note)
5
t d(ALE–E)
ALE output delay time
4
t w(ALE)
ALE
pulse
width
(Note)
22
____
t d(BHE–E)
(Note)
BHE
output
delay
time
20
____
t d(BLE–E)
(Note)
BLE
output
delay
time
20
__
t d(R/W–E)
(Note)
R/W output delay time
20
t d(E–φ1)
φ 1 output delay time
18
0
t h(E–AL)
(Note)
Address low-order hold time
18
t h(ALE–AM) Address middle-order hold time (BYTE = “L”)
9
t h(E–DHQ)
Data high-order hold time (BYTE = “L”)
(Note)
18
t pzx(E–DHZ) Data high-order floating release delay time (BYTE = “L”)
(Note)
20
t h(E–AM)
Address middle-order hold time (BYTE = “H”)
(Note)
18
t h(ALE–AH) Address high-order hold time
9
t h(E–DLQ)
(Note)
Data low-order hold time
18
t pzx(E–DLZ) Data low-order floating release delay time
(Note)
20
____
t h(E–BHE)
(Note)
BHE
hold
time
18
____
t h(E–BLE)
(Note)
BLE
hold
time
18
__
t h(E–R/W)
(Note)
R/W hold time
18
t w(EL)
(Note)
E pulse width
55
t su(A–DL)
Data low-order setup time after address stabilization
(Note)
50
t su(ALE–DL) Data low-order setup time after rising of ALE
(Note)
55
t su(A–DH)
Data high-order setup time after address stabilization
(Note)
50
t su(ALE–DH) Data high-order setup time after rising of ALE
(Note)
55
Note: Figure 13 shows the test circuit.
7721 Group User’s Manual
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
17–89
APPENDIX
Appendix 11. Electrical characteristics
Microprocessor mode : with no Wait
<Write>
tw(L) tw(H)
tr
tf
tc
f(XIN)
1
td(E-
td(E- 1)
tw(EL)
1)
E
Address output
A0–A7
Address output
A8–A15
(BYTE = “H”)
Address/Data output
A8/D8–A15/D15
(BYTE = “L”)
Data input
D0–D15
(BYTE = “L”)
td(AL-E)
Address
td(AM-E)
th(E-AM)
Address
td(E-DHQ)
td(AM-E)
Address
td(AM-ALE)
th(E-DHQ)
Data
th(ALE-AM)
td(E-DLQ)
td(AH-E)
Address/Data output
A16/D0–A23/D7
Data input
D0–D7
th(E-AL)
td(AH-ALE)
tw(ALE)
th(E-DLQ)
Data
Address
th(ALE-AH)
td(ALE-E)
ALE output
td(BHE-E)
th(E-BHE)
td(BLE-E)
th(E-BLE)
BHE output
BLE output
td(R/W-E)
th(E-R/W)
R/W output
td(E-PiQ)
Port Pi output
(i = 4–10)
Test conditions (port Pi)
•Vcc = 5 V ± 10 %
•Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
•Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
17–90
Test conditions (except port Pi)
•Vcc = 5 V ± 10 %
•Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
•Data input : VIL = 0.8 V, VIH = 2.5 V
7721 Group User’s Manual
APPENDIX
Appendix 11. Electrical characteristics
Microprocessor mode : with no Wait
<Read>
tw(L) tw(H)
tr
tf
tc
f(XIN)
1
td(E-
td(E- 1)
tw(EL)
1)
E
td(AL-E)
Address output
A0–A7
Address output
A8–A15
(BYTE = “H”)
Address/Data output
A8/D8–A15/D15
(BYTE = “L”)
Data input
D8–D15
(BYTE = “L”)
Address/Data output
A16/D0–A23/D7
th(E-AL)
Address
td(AM-E)
th(E-AM)
Address
tpxz(E-DHZ)
td(AM-E)
tpzx(E-DHZ)
Address
td(AM-ALE)
th(ALE-AM)
tsu(A-DH)
tsu(DH-E)
tsu(ALE- DH)
td(AH-E)
th(E-DH)
Data
tpzx(E-DLZ)
tpxz(E-DLZ)
Address
td(AH-ALE)
tsu(A-DL)
Data input
D0–D7
th(ALE-AH)
tsu(DL-E)
tw(ALE)
th(E-DL)
Data
tsu(ALE-DL)
td(ALE-E)
ALE output
td(BHE-E)
th(E-BHE)
td(BLE-E)
th(E-BLE)
td(R/W-E)
th(E-R/W)
BHE output
BLE output
R/W output
tsu(PiD-E)
td(E-PiQ)
Port Pi input
(i = 4–10)
Test conditions (port Pi)
•Vcc = 5 V ± 10 %
•Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
•Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
Test conditions (except port Pi)
•Vcc = 5 V ± 10 %
•Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
•Data input : VIL = 0.8 V, VIH = 2.5 V
7721 Group User’s Manual
17–91
APPENDIX
Appendix 11. Electrical characteristics
Microprocessor mode : with Wait
Note: The limits depend on f(X IN). Table 4 lists calculation formulas for the limits.
Timing requirements (VCC = 5 V ± 10 %, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz, unless otherwise noted)
Limits
Symbol
Unit
Parameter
Min. Max.
ns
tc
External clock input cycle time
40
ns
tw(H)
External clock input high-level pulse width
15
ns
tw(L)
External clock input low-level pulse width
15
tr
External clock input rising time
8 ns
tf
External clock input falling time
8 ns
ns
tsu(PiD–E)
Port Pi input setup time (i = 4–10)
60
ns
th(E–PiD)
Port Pi input hold time (i = 4–10)
0
Switching characteristics (V CC = 5 V ± 10 %, V SS = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz, unless otherwise noted)
Limits
Symbol
Parameter
Min. Max.
td(E-PiQ)
Port Pi data output delay time
80
td(AL–E)
(Note)
Address low-order output delay time
15
td(E–DHQ)
Data high-order output delay time (BYTE = “L”)
35
tpxz(E–DHZ) Data high-order floating start delay time (BYTE = “L”)
0
td(AM–E)
(Note)
Address middle-order output delay time
15
td(AM–ALE) Address middle-order output delay time
(Note)
5
td(E–DLQ)
Data low-order output delay time
35
tpxz(E–DLZ) Data low-order floating start delay time
0
td(AH–E)
(Note)
Address high-order output delay time
15
td(AH–ALE) Address high-order output delay time
(Note)
5
td(ALE–E)
ALE output delay time
4
tw(ALE)
(Note)
ALE
pulse
width
22
____
td(BHE–E)
(Note)
BHE output delay time
20
____
td(BLE–E)
(Note)
BLE
output
delay
time
20
__
td(R/W–E)
(Note)
R/W output delay time
20
td(E–φ1)
φ 1 output delay time
18
0
th(E–AL)
(Note)
Address low-order hold time
18
th(ALE–AM) Address middle-order hold time (BYTE = “L”)
9
th(E–DHQ)
(Note)
Data high-order hold time (BYTE = “L”)
18
tpzx(E–DHZ) Data high-order floating release delay time (BYTE = “L”)
(Note)
20
th(E–AM)
(Note)
Address middle-order hold time (BYTE = “H”)
18
th(ALE–AH) Address high-order hold time
9
th(E–DLQ)
(Note)
Data low-order hold time
18
tpzx(E–DLZ) Data low-order floating release delay time
(Note)
20
____
th(E–BHE)
(Note)
BHE
hold
time
18
____
th(E–BLE)
(Note)
BLE
hold
time
18
__
th(E–R/W)
(Note)
R/W
hold
time
18
__
tw(EL)
(Note) 135
E pulse width
tsu(A–DL)
(Note)
Data low-order setup time after address stabilization
130
tsu(ALE–DL) Data low-order setup time after rising of ALE
(Note)
135
tsu(A–DH)
(Note)
Data high-order setup time after address stabilization
130
tsu(ALE–DH) Data high-order setup time after rising of ALE
(Note)
135
Note: Figure 13 shows the test circuit.
17–92
7721 Group User’s Manual
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
APPENDIX
Appendix 11. Electrical characteristics
Microprocessor mode : with Wait
<Write>
tw(L) tw(H)
tr
tf
tc
f(XIN)
1
td(E-
td(E-
1)
1)
tw(EL)
E
td(AL-E)
Address output
A0–A7
Address output
A8–A15
(BYTE = “H”)
Address/Data output
A8/D8–A15/D15
(BYTE = “L”)
Data input
D0–D15
(BYTE = “L”)
th(E-AL)
Address
td(AM-E)
th(E-AM)
Address
td(AM-E)
td(E-DHQ)
Address
td(AM-ALE)
th(ALE-AM)
td(E-DLQ)
td(AH-E)
Address/Data output
A16/D0–A23/D7
Data input
D0–D7
th(E-DHQ)
Data
td(AH-ALE)
tw(ALE)
th(E-DLQ)
Data
Address
th(ALE-AH)
td(ALE-E)
ALE output
td(BHE-E)
th(E-BHE)
td(BLE-E)
th(E-BLE)
BHE output
BLE output
td(R/W-E)
th(E-R/W)
R/W output
td(E-PiQ)
Port Pi output
(i = 4–10)
Test conditions (port Pi)
•Vcc = 5 V ± 10 %
•Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
•Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
Test conditions (except port Pi)
•Vcc = 5 V ± 10 %
•Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
•Data input : VIL = 0.8 V, VIH = 2.5 V
7721 Group User’s Manual
17–93
APPENDIX
Appendix 11. Electrical characteristics
Microprocessor mode : with Wait
<Read>
tw(L) tw(H)
tr
tf
tc
f(XIN)
1
td(E-
td(E-
1)
1)
tw(EL)
E
td(AL-E)
Address output
A0–A7
Address output
A8–A15
(BYTE = “H”)
Address/Data output
A8/D8–A15/D15
(BYTE = “L”)
Data input
D8–D15
(BYTE = “L”)
Address/Data output
A16/D0–A23/D7
th(E-AL)
Address
td(AM-E)
th(E-AM)
Address
td(AM-E)
tpxz(E-DHZ)
tpzx(E-DHZ)
Address
td(AM-ALE)
th(ALE-AM)
tsu(A-DH)
tsu(ALE-DH)
tpxz(E-DLZ)
td(AH-E)
tsu(DH-E)
th(E-DH)
Data
tpzx(E-DLZ)
Address
td(AH-ALE)
th(ALE-AH)
tsu(A-DL)
Data input
D0–D7
tsu(ALE-DL)
tw(ALE)
tsu(DL-E)
th(E-DL)
Data
td(ALE-E)
ALE output
td(BHE-E)
th(E-BHE)
td(BLE-E)
th(E-BLE)
td(R/W-E)
th(E-R/W)
BHE output
BLE output
R/W output
tsu(PiD-E)
td(E-PiQ)
Port Pi input
(i = 4–10)
Test conditions (port Pi)
•Vcc = 5 V ± 10 %
•Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
•Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
17–94
Test conditions (except port Pi)
•Vcc = 5 V ± 10 %
•Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
•Data input : VIL = 0.8 V, VIH = 2.5 V
7721 Group User’s Manual
APPENDIX
Appendix 11. Electrical characteristics
DRAM control switching characteristics (V CC = 5 V ± 10 %, V SS = 0 V, Ta = –20 to 85 °C,
f(X IN) = 25 MHz, unless otherwise noted)
Note: The limits depend on f(X IN). Table 5 lists calculation formulas for the limits.
Read
Symbol
Parameter
____
t w(RASL)
RAS low–level pulse width
____
t w(CASL)
CAS low–level pulse width
____
t w(RASH)
CAS high–level pulse width
____ ____
t d(RAS–CAS) RAS–CAS delay time
____
t d(RA–RAS) Row address delay time before
RAS
____
t h(RAS–RA) Row address hold time after RAS ____
t d(CA–CAS) Column address delay time before
CAS
____
t h(CAS–CA) Column
address
hold
time
after
CAS
__
____
t d(R/W–RAS) R/W
delay
time
before
RAS
__
____
t h(CAS–R/W) R/W hold time after CAS
__
t d(E–CA)
Column address delay__time after E’s low level
____
t d(E–RASL) ____
RAS delay time after __
E’s low level
t d(E–CASL) ____
CAS delay time after __
E’s low level
t d(E–RASH) ____
RAS delay time after __
E’s high level
t d(E–CASH) CAS delay time after E’s high level
Note: Figure 13 shows the test circuit.
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
Limits
Min. Max. Unit
ns
120
ns
92.5
ns
60
ns
28
ns
5
ns
18
ns
5
ns
100
ns
18
ns
18
65 ns
30 ns
77.5 ns
0
20 ns
20 ns
0
Write
Symbol
Parameter
____
t w(RASL)
RAS low–level pulse width
____
t w(CASL)
CAS low–level pulse width
____
t w(RASH)
CAS high–level pulse width
____ ____
t d(RAS–CAS) RAS–CAS delay time
____
t d(RA–RAS) Row address delay time before RAS
____
t h(RAS–RA) Row address hold time after RAS ____
t d(CA–CAS) Column address delay time before
CAS
____
t h(CAS–CA) Column
address
hold
time
afrer
CAS
__
____
t d(R/W–RAS) R/W delay time before RAS
__
____
t h(CAS–R/W) R/W hold time after CAS
____
__
t d(E–RASL) RAS delay time after E’s low level
____
__
t d(E–CASL) ____
CAS delay time after __
E’s low level
t d(E–RASH) ____
RAS delay time after __
E’s high level
t d(E–CASH) CAS delay time after E’s high level
Note: Figure 13 shows the test circuit.
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
Limits
Unit
Min. Max.
ns
120
ns
55
ns
60
ns
60
ns
5
ns
18
ns
10
ns
60
ns
18
ns
18
30 ns
115 ns
80
20 ns
0
20 ns
0
Refresh state
Symbol
Parameter
____
t w(RASL)
RAS low–level pulse width
____
t w(CASL)
CAS low–level
pulse width
____
___
t d(CAS–RAS) CAS–RAS delay time
____
____
t h(RAS–CAS) CAS hold time after RAS
Note: Figure 13 shows the test circuit.
(Note)
(Note)
(Note)
(Note)
7721 Group User’s Manual
Limits
Min. Max.
120
55
17.5
17.5
Unit
ns
ns
ns
ns
17–95
APPENDIX
Appendix 11. Electrical characteristics
At DRAM control
1
E
td(RAS-CAS)
tw(RASH)
tw(RASL)
td(E-RASH)
th(RAS-RA)
RAS output
td(RA-RAS)
td(E-CASH)
tw(CASL)
td(E-RASL)
td(R/W-RAS)
CAS output
td(E-CASL)
td(CA-CAS)
At read
MA0–MA9
output
th(CAS-R/W)
th(CAS-CA)
Row address
Column address
td(E-CA)
R/W output
td(RAS-CAS)
tw(RASH)
tw(RASL)
td(E-RASH)
th(RAS-RA)
RAS output
td(RA-RAS)
CAS output
At write
MA0–MA9
output
td(E-CASH)
td(E-RASL)
td(E-CASL)
td(CA-CAS)
td(R/W-RAS)
Row address
tw(CASL)
th(CAS-CA)
Column address
R/W output
tw(RASL)
RAS output
At refreshing
td(CAS-RAS) th(RAS-CAS)
CAS output
tw(CASL)
Test conditions
•Vcc = 5 V ± 10 %
•Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
•D0–D15 input : VIL = 0.8 V, VIH = 2.5 V
17–96
7721 Group User’s Manual
th(CAS-R/W)
APPENDIX
Appendix 11. Electrical characteristics
DMAC switching characteristics (V CC = 5 V ±10 %, V SS = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz,
unless otherwise noted)
Note: The limits depend on f(X IN). Table 6 lists calculation formulas for the limits.
Symbol
t su(DRQ-φ1)
t w(DRQ)
t d(φ1–STi)
t d(φ1–DAK)
t d(AL–E)
t d(E–DHQ)
t pxz(E–DHZ)
t d(AM–E)
t d(E–DLQ)
t pxz(E–DLZ)
t d(AH–E)
t d(ALE–E)
t w(ALE)
t d(BHE–E)
t d(BLE–E)
t d(R/W–E)
t h(E–AL)
t h(ALE–AM)
t h(E–DHQ)
t pzx(E–DHZ)
t h(E–AM)
t h(ALE–AH)
t h(E–DLQ)
t pzx(E–DLZ)
t h(E–BHE)
t h(E–BLE)
t h(E–R/W)
t w(EL)
t d(data)
t d(φ1–TC)
t w(TC)
t su(TCIN)
t w(TCIN)
Parameter
________
DMAREQi
input setup time
________
DMAREQi input pulse width
ST0,
ST1 output delay time
________
DMAACKi output delay time
Address low-order output delay time
Data high-order output delay time (BYTE = “L”)
Data high-order floating start delay time (BYTE = “L”)
Address middle-order output delay time
Data low-order output delay time
Data low-order floating start delay time
Address high-order output delay time
ALE output delay time
ALE pulse width
____
BHE output delay time
____
BLE
output delay time
__
R/W output delay time
Address low-order hold time
Address middle-order hold time (BYTE = “L”)
Data high-order hold time (BYTE = “L”)
Data high-order floating release delay time (BYTE = “L”)
Address middle-order hold time (BYTE = “H”)
Address high-order hold time
Data low-order hold time
Data low-order floating release delay time
____
BHE hold time
____
BLE
hold time
__
R/W
hold time
__
E pulse width
Copy delay time
___
TC output delay time
___
TC output pulse width
___
TC input setup time
___
TC input pulse width
Note: Figures 13 and 14 show the test circuits.
7721 Group User’s Manual
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
Limits
Unit
Min. Max.
ns
60
ns
80
40 ns
60 ns
ns
15
35 ns
0 ns
ns
35 ns
0 ns
ns
15
ns
4
ns
22
ns
20
ns
20
ns
20
ns
18
ns
9
ns
18
ns
20
ns
18
ns
9
ns
18
ns
20
ns
18
ns
18
ns
18
ns
55
ns
50
ns
50
ns
50
ns
60
ns
80
17–97
APPENDIX
Appendix 11. Electrical characteristics
At DMA transfer
•Burst transfer timing (External source DMAREQi)
1
E
tsu(DRQ-
1)
tw(EL)
DMAREQi
tw(DRQ)
ST0
td(
td(
1-STi)
1-DAK)
DMAACKi
td(AL-E)
A0–A7 output
Address
th(E-AL)
Address
Address
Address
Address
td(E-DHQ)
A8/D8–A15/D15 output
(BYTE = “L”)
Address
Data
Address
Address
td(AM-E)
A8/D8–A15/D15 output
(BYTE = “H”)
Address
Address
th(E-AM)
Address
Data
th(ALE-AM)
Address
Address
td(AH-E)
A16/D0–A23/D7 output
Address
Data
Address
tw(ALE)
Address
td(E-DLQ)
Address
Address
td(ALE-E)
Data
th(ALE-AH)
ALE output
td(BHE-E)
th(E-BHE)
td(BLE-E)
th(E-BLE)
td(R/W-E)
th(E-R/W)
BHE output
BLE output
R/W output
Test conditions
•Vcc = 5 V ± 10 %
•Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
•D0–D15 input : VIL = 0.8 V, VIH = 2.5 V
•DMAREQi input : VIL = 0.8 V, VIH = 2.5 V
17–98
Address
7721 Group User’s Manual
Address
APPENDIX
Appendix 11. Electrical characteristics
At DMA transfer
•Cycle-steal transfer timing (External source DMAREQi)
1
E
tsu(DRQ-
1)
tw(EL)
DMAREQi
tw(DRQ)
td(
1-STi)
td(
1-DAK)
ST0
td(
td(
1-STi)
1-DAK)
DMAACKi
td(AL-E)
A0–A7 output
A8/D8–A15/D15 output
(BYTE = “L”)
Address
th(E-AL)
Address
Address
Data
Address
Address
Address
Address
td(AM-E)
A8/D8–A15/D15 output
(BYTE = “H”)
Address
Address
th(E-AM)
Address
Address
Address
Address
Address
Address
td(AH-E)
A16/D0–A23/D7 output
Address
Data
Address
tw(ALE)
Address
Address
Address
td(ALE-E)
ALE output
td(BHE-E)
th(E-BHE)
td(BLE-E)
th(E-BLE)
BHE output
BLE output
td(R/W-E)
R/W output
Test conditions
•Vcc = 5 V ± 10 %
•Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
•D0–D15 input : VIL = 0.8 V, VIH = 2.5 V
•DMAREQi input : VIL = 0.8 V, VIH = 2.5 V
7721 Group User’s Manual
17–99
APPENDIX
Appendix 11. Electrical characteristics
At DMA transfer
•1-bus transfer timing
1
E
td(
td(
1-DAK)
td(
1-DAK)
td(
1-DAK)
1-DAK)
DMAACKi
td(AL-E)
th(E-AL)
td(AL-E)
Address
A0–A7 output
tpxz(E-DHZ)
A8/D8–A15/D15 output
(BYTE = “L”)
Address
th(E-AL)
Address
tpzx(E-DHZ)
Address
tsu(DH-E) th(E-DH)
Data
td(data)
D0–D15 input
td(data)
Address
A16/D0–A23/D7 output
tpxz(E-DLZ)
Address
Data
tpzx(E-DLZ)
tsu(DL-E) th(E-DL)
D0–D7 output
tw(ALE)
td(ALE-E)
tw(ALE)
td(ALE-E)
ALE output
td(BHE-E)
th(E-BHE)
td(BHE-E)
th(E-BHE)
td(BLE-E)
th(E-BLE)
td(BLE-E)
th(E-BLE)
td(R/W-E)
th(E-R/W)
td(R/W-E)
th(E-R/W)
BHE output
BLE output
R/W output
Test conditions
•Vcc = 5 V ± 10 %
•Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
•D0–D15 input : VIL = 0.8 V, VIH = 2.5 V
17–100
7721 Group User’s Manual
APPENDIX
Appendix 11. Electrical characteristics
At DMA transfer
•Transfer complete timing
1
E
td(
1-TC)
TC
tw(TC)
td(
1-STi)
ST0
td(
1-DAK)
DMAACKi
th(E-AL)
A0–A7 output
Address
td(AL-E)
Address
Address
Address
Address
Address
th(E-DHQ)
A8/D8–A15/D15 output
(BYTE = “L”)
Address
Data
Address
th(E-AM)
A8/D8–A15/D15 output
(BYTE = “H”)
td(AM-E)
Address
Address
Address
Address
th(E-DLQ)
A16/D0–A23/D7 output
Address
td(AH-E)
Address
Data
Data
Address
Address
Data
ALE output
th(E-BHE)
td(BHE-E)
th(E-BLE)
td(BLE-E)
th(E-R/W)
td(R/W-E)
BHE output
BLE output
R/W output
Test conditions
•Vcc = 5 V ± 10 %
•Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
•D0–D15 input : VIL = 0.8 V, VIH = 2.5 V
7721 Group User’s Manual
17–101
APPENDIX
Appendix 11. Electrical characteristics
When DMA transfer is forcedly completed by TC input
•TC input timing
1
E
tsu(TCIN)
TC input
tw(TCIN)
td(
1-STi)
td(
1-DAK)
ST0
DMAACKi
td(AL-E)
A0–A7 output
A8/D8–A15/D15 output
(BYTE = “L”)
Destination
address
Data
Destination
address
td(AH-E)
A16/D0–A23/D7 output
Source address
Destination address
Source Destination
address
address
td(AM-E)
A8/D8–A15/D15 output
(BYTE = “H”)
th(E-AL)
th(E-AM)
Source address
Data
Destination address
Address
td(E-DLQ)
Source Destination
address address
Data
td(ALE-E)
Address
th(ALE-AM)
Data
tw(ALE)
Address
td(E-DHQ)
Address
th(ALE-AH)
ALE output
td(R/W-E)
th(E-R/W)
R/W output
Test conditions
•Vcc = 5 V ± 10 %
•Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
•D0–D15 input : VIL = 0.8 V, VIH = 2.5 V
•TC input : VIL = 0.8 V, VIH = 2.5 V
17–102
7721 Group User’s Manual
APPENDIX
Appendix 11. Electrical characteristics
Table 3 Calculation formulas for internal peripheral devices’ input/output timing depending on f(X IN)
(Vcc = 5 V ± 10 %, Vss = 0 V, Ta = –20 to 85 °C)
Timer A input (Gating input in timer mode)
Symbol
Calculation formula
Unit
9
tc(TA)
ns
8 ✕ 10
f(X IN)
tw(TAH)
4 ✕ 10 9
f(X IN)
ns
tw(TAL)
4 ✕ 10 9
f(X IN)
ns
Timer A input (External trigger input in one-shot pulse mode)
Symbol
tc(TA)
Calculation formula
4 ✕ 10 9
f(X IN)
Unit
ns
Timer B input (Pulse period measurement mode)
Calculation formula
Symbol
Unit
9
tc(TB)
ns
8 ✕ 10
f(X IN)
tw(TBH)
4 ✕ 10 9
f(X IN)
ns
tw(TBL)
4 ✕ 10 9
f(X IN)
ns
Timer B input (Pulse width measurement mode)
Symbol
Unit
Calculation formula
9
tc(TB)
ns
8 ✕ 10
f(X IN)
tw(TBH)
ns
4 ✕ 10 9
f(X IN)
tw(TBL)
4 ✕ 10 9
f(X IN)
ns
7721 Group User’s Manual
17–103
APPENDIX
Appendix 11. Electrical characteristics
Table 4 Calculation formulas for bus timing depending on f(XIN )
(Vcc = 5 V ± 10 %, Vss = 0 V, Ta = –20 to 85 °C)
Symbol
td(AL–E)
td(AM–E)
td(AH–E)
td(AM–ALE)
td(AH–ALE)
tw(ALE)
td(BLE–E)
td(BHE–E)
td(R/W–E)
th(E–AL)
th(E–AM)
th(E–DLQ)
th(E–DHQ)
tpzx(E–DLZ)
tpzx(E–DHZ)
th(E–BLE)
th(E–BHE)
th(E–R/W)
tw(EL)
Wait bit = “1”
Wait bit = “0”
tsu(A–DL)
tsu(A–DH)
Wait bit = “1”
Wait bit = “0”
tsu(ALE–DL) Wait bit = “1”
tsu(ALE–DH)
Wait bit = “0”
17–104
Calculation formula Unit
1 ✕ 10 9
– 25
f(X IN)
1 ✕ 10 9
– 35
f(X IN)
1 ✕ 10 9
– 18
f(X IN)
1 ✕ 10 9 – 20
f(XIN)
1 ✕ 10 9
– 22
f(X IN)
1 ✕ 10 9
– 22
f(X IN)
1 ✕ 10 9
– 20
f(XIN)
1 ✕ 10 9 – 22
f(XIN)
2 ✕ 10 9
– 25
f(X IN)
4 ✕ 10 9
– 25
f(XIN)
3 ✕ 10 9
– 70
f(X IN)
5 ✕ 10 9
– 70
f(X IN)
3 ✕ 10 9 – 65
f(X IN)
5 ✕ 10 9 – 65
f(X IN)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7721 Group User’s Manual
APPENDIX
Appendix 11. Electrical characteristics
Table 5 Calculation formulas for DRAM control bus timing depending of f(XIN)
(Vcc = 5 V ± 10 %, Vss = 0 V, Ta = –20 to 85 °C)
Read
Symbol
Calculation formula
Unit
tw(RASL)
4 ✕ 10
f(X IN)
tw(CASL)
3 ✕ 10 9
– 27.5
f(X IN)
ns
tw(RASH)
2 ✕ 10 9
– 20
f(X IN)
ns
td(RAS–CAS)
1 ✕ 10 9
– 12
f(X IN)
ns
td(RA–RAS)
1 ✕ 10 9
– 35
f(XIN)
ns
th(RAS–RA)
1 ✕ 10 9
– 22
f(X IN)
ns
Calculation formula
Unit
Write
Symbol
9
– 40
tw(RASL)
4 ✕ 10
f(X IN)
tw(CASL)
2 ✕ 10 9
f(X IN)
ns
9
– 40
– 25
ns
ns
tw(RASH)
2 ✕ 10 9
– 20
f(X IN)
ns
td(RAS–CAS)
2 ✕ 10 9
– 20
f(X IN)
ns
td(RA–RAS)
1 ✕ 10 9
– 35
f(XIN)
ns
th(RAS–RA)
1 ✕ 10 9
– 22
f(X IN)
ns
Symbol
Calculation formula
th(CAS–CA)
4 ✕ 10
f(X IN)
td(R/W–RAS)
1 ✕ 10 9
f(XIN)
Unit
9
– 60
– 22
ns
ns
th(CAS–R/W)
1 ✕ 10 9
– 22
f(XIN)
ns
td(E–CA)
1 ✕ 10 9
+ 25
f(XIN)
ns
td(E–CASL)
1 ✕ 10 9
+ 37.5
f(XIN)
ns
Calculation formula
Unit
Symbol
td(CA–CAS)
1 ✕ 10
f(X IN)
th(CAS–CA)
3 ✕ 10 9
f(XIN)
9
– 30
– 60
ns
ns
td(R/W–RAS)
1 ✕ 10 9
– 22
f(XIN)
ns
th(CAS–R/W)
1 ✕ 10 9
– 22
f(XIN)
ns
td(E–CASL)
2 ✕ 10 9
f(XIN)
ns
+ 35(0) ✽
✽ The value within ( ) is for the minimum value.
Refresh
Symbol
Calculation formula
Unit
tw(RASL)
4 ✕ 10
f(X IN)
– 40
ns
tw(CASL)
2 ✕ 10 9
– 25
f(X IN)
ns
9
Symbol
Calculation formula
Unit
td(CAS–RAS)
1 ✕ 10 9
– 22.5
f(X IN)
ns
th(RAS–CAS)
1 ✕ 10 9
– 22.5
f(XIN)
ns
7721 Group User’s Manual
17–105
APPENDIX
Appendix 11. Electrical characteristics
Table 6 Calculation formulas for DMA transfer bus timing
depending on f(X IN) (Vcc = 5 V ± 10 %, Vss = 0 V,
Ta = –20 to 85 °C)
Symbol
Calculation formula Unit
t d(AL–E)
t d(AM–E)
t d(AH–E)
t w(ALE)
1 ✕ 10 9
f(XIN)
1 ✕ 10 9
f(XIN)
1 ✕ 10 9
f(X IN)
1 ✕ 10 9
f(X IN)
1 ✕ 10 9
f(X IN)
1 ✕ 10 9
f(XIN)
1 ✕ 10 9
f(X IN)
2 ✕ 10 9
f(X IN)
4 ✕ 10 9
f(X IN)
2 ✕ 10 9
f(X IN)
t d(BLE–E)
t d(BHE–E)
t d(R/W–E)
t h(E–AL)
t h(E–AM)
t h(E–DLQ)
t h(E–DHQ)
t pzx(E–DLZ)
t pzx(E–DHZ)
t h(E–BLE)
t h(E–BHE)
t h(E–R/W)
t w(EL) Transfer source/Transfer
destination wait bit = “1”
Transfer source/Transfer
destination wait bit = “0”
t w(TC)
A0/MA0–A7/MA7
A8/D8–A15/D15
A16/D0–A23/D7
P4
P5
P6
P7
P8
P9
P10
E
– 25
ns
– 18
ns
– 20
ns
– 22
ns
– 22
ns
– 20
ns
– 22
ns
– 25
ns
– 25
ns
– 30
ns
100 pF
3 kΩ
TC
100 pF
1
Fig. 13 Test circuit for each pin
17–106
___
Fig. 14 ___
Test circuit for TC output delay time and
TC output pulse width
7721 Group User’s Manual
APPENDIX
Appendix 12. Standard characteristics
Appendix 12. Standard characteristics
Standard characteristics described below are just examples of the M37721S2BFP’s characteristics and are
not guaranteed. For each parameter’s limits, refer to section “Appendix 11. Electrical characteristics.”
1. Programmable I/O port (CMOS output) standard characteristics
(1) P-channel I OH–V OH characteristics
30.0
IOH [mA]
24.0
18.0
Ta = 25 °C
Ta = 85 °C
12.0
6.0
0
1.0
2.0
3.0
4.0
5.0
VOH [V]
(2) N-channel I OL–V OL characteristics
30.0
Ta = 25 °C
IOL [mA]
24.0
Ta = 85 °C
18.0
12.0
6.0
0
1.0
2.0
3.0
4.0
5.0
VOL [V]
7721 Group User’s Manual
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APPENDIX
Appendix 12. Standard characteristics
2. Icc–f(XIN) standard characteristics
(1) Icc–f(XIN) characteristics on operating and at reset
Measurement condition (Vcc = 5.0 V, Ta = 25 °C, f(XIN) : square waveform, microprocessor mode)
30
Icc [mA]
20
On operating
At reset
10
0
0
5
10
15
20
25
30
f(XIN) [MHz]
(2) Wait mode
Measurement condition (Vcc = 5.0 V, Ta = 25 °C, f(XIN) : square waveform, microprocessor mode)
10
Icc [mA]
8
6
4
2
0
0
5
10
15
20
f(XIN) [MHz]
17–108
7721 Group User’s Manual
25
30
APPENDIX
Appendix 12. Standard characteristics
3. A-D converter standard characteristics
The lower lines of the graph indicate the absolute precision errors. These are expressed as the deviation
from the ideal value when the output code changes. For example, the change in output code from 0 to 1
should occur at 10 mV, but the measured value is +2 mV. Accordingly, the measured point of change is
10 + 2 = 12 mV.
The upper lines of the graph indicate the input voltage width for which the output code is constant. For
example, the measured input voltage width for which the output code is 15 is 24 mV, so that the differential
non-linear error is 24 – 20 = 4 mV (0.2 LSB).
30
30
20
20
10
10
0
0
–10
1LSB WIDTH [mV]
ERROR [mV]
[Measurement conditions]
•Vcc = 5 V, V REF = 5.12 V, f(X IN) = 25 MHz, Ta = 25 °C, φ AD = f 2 divided by 2
–20
0
8
16
24
32
40
48
56
ERROR
[mV]
30
64
STEP No.
72
80
88
96
104
112
120
128
30
20
20
10
10
0
0
–10
1LSB WIDTH [mV]
–30
–20
–30
128
136
144
152
160
168
176
184
192
200
STEP No.
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7721 Group User’s Manual
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240
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256
17–109
APPENDIX
Appendix 12. Standard characteristics
MEMORANDUM
17–110
7721 Group User’s Manual
GLOSSARY
GLOSSARY
This section briefly explains the terms used in this user’s manual. The terms defined here apply to this
manual only.
Term
Access
Meaning
Relevant term
Means performing read, write, or read and write.
In DRAMC, also means performing DRAM refresh.
Access space
An accessible memory space of up to 16 Mbytes.
Access
Access characteristics
Means whether accessible or not.
Access
Branch
Bus control signal
Means moving the program’s execution point (= address) to another location.
_____
__
__ ____ ____ ____
_____
A generic name for ALE, E , R/ W, BLE, BHE , RDY, HOLD, HLDA,
BYTE, ST0, and ST1 signals.
Countdown
Means decreasing by 1 and counting.
Count source
A signal that is counted by timers A and B, the UARTi baud rate
register (BRGi) and the watchdog timer. That is f 2 , f16, f 64, f 512
selected by the count source select bits and others.
Countup
Means increasing by 1 and counting.
External area
An accessible area for external devices connected. It is up to 16- Internal area
Mbyte external area.
External bus
A generic name for the external address bus and the external
data bus.
Devices connected externally to the microcomputer. A generic
name for a memory, an I/O device and a peripheral IC.
External device
Countup
Countdown
Internal area
An accessible internal area. A generic name for areas of the External area
internal RAM and the SFR.
Interrupt routine
A routine that is automatically executed when an interrupt request
is accepted. Set the start address of this routine into the interrupt
vector table.
A state where the countup resultant is greater than the counter Underflow
resolution.
Countup
R e a d - m o d i f y - w r i t e An instruction that reads the memory contents, modifies them
and writes back to the same address. Relevant instructions are
instruction
the ASL, ASR, CLB, DEC, INC, LSR, ROL, ROR, SEB instructions.
Overflow
Signal required for access A generic name for bus control, address bus, and data bus signals. B u s c o n t r o l
to external device
signal
A state where the oscillation circuit halts and the program execution Wait mode
Stop mode
is stopped. By executing the STP instruction, the microcomputer
enters the stop mode.
UART
Underflow
Wait mode
2
Clock asynchronous serial I/O. When used to designate the name Clock
of a functional block, this term also means the serial I/O which synchronous
can be switched to the cock synchronous serial I/O.
serial I/O
A state where the countdown resultant is greater than the counter Overflow
resolution.
Countdown
A state where the oscillation circuit is operating, however, the Stop mode
program execution is stopped. By executing the WIT instruction,
the microcomputer enters the wait mode.
7721 Group User’s Manual
MITSUBISHI SEMICONDUCTORS
USER’S MANUAL
7721 Group
Sep. First Edition 1997
Editioned by
Committee of editing of Mitsubishi Semiconductor USER’S MANUAL
Published by
Mitsubishi Electric Corp., Semiconductor Marketing Division
This book, or parts thereof, may not be reproduced in any form without permission
of Mitsubishi Electric Corporation.
©1997 MITSUBISHI ELECTRIC CORPORATION
User’s Manual
7721 Group
© 1997 MITSUBISHI ELECTRIC CORPORATION.
New publication, effective Sep. 1997.
Specifications subject to change without notice.