RENESAS M37733MHBXXXFP

To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DESCRIPTION
●Serial I/O (UART or clock synchronous) ..................................... 3
●10-bit A-D converter ............................................ 8-channel inputs
●12-bit watchdog timer
●Programmable input/output
(ports P0, P1, P2, P3, P4, P5, P6, P7, P8) ............................... 68
●Clock generating circuit ........................................ 2 circuits built-in
The M37733MHBXXXFP is a single-chip microcomputer using the
7700 Family core. This single-chip microcomputer has a CPU and a
bus interface unit. The CPU is a 16-bit parallel processor that can be
an 8-bit parallel processor, and the bus interface unit enhances the
memory access efficiency to execute instructions fast. This
microcomputer also includes a 32 kHz oscillation circuit, in addition
to the ROM, RAM, multiple-function timers, serial I/O, A-D converter,
and so on.
APPLICATION
Control devices for general commercial equipment such as office
automation, office equipment, and so on.
Control devices for general industrial equipment such as
communication equipment, and so on.
FEATURES
●Number of basic instructions .................................................. 103
●Memory size
ROM ............................................... 124 Kbytes
RAM ................................................ 3968 bytes
●Instruction execution time
The fastest instruction at 25 MHz frequency ...................... 160 ns
●Single power supply ...................................................... 5 V ± 10%
●Low power dissipation (at 25 MHz frequency)
............................................47.5 mW (Typ.)
●Interrupts ............................................................ 19 types, 7 levels
●Multiple-function 16-bit timer ................................................. 5 + 3
42
41
43
44
46
45
48
47
49
51
50
52
54
53
56
55
57
59
58
61
60
62
64
32
P24/A20/D4
P25/A21/D5
P26/A22/D6
P27/A23/D7
P30/R/W
P31/BHE
P32/ALE
P33/HLDA
Vss
74
31
E
75
30
76
29
XOUT
XIN
77
28
RESET
78
27
79
26
80
25
CNVSS
BYTE
P40/HOLD
65
40
66
39
67
38
68
37
69
36
70
35
34
71
72
33
24
P41/RDY
23
21
22
20
19
18
17
16
15
14
13
12
11
10
9
6
7
5
4
3
2
1
73
8
M37733MHBXXXFP
P70/AN0
P67/TB2IN/ φ SUB
P66/TB1IN
P65/TB0IN
P64/INT2
P63/INT1
P62/INT0
P61/TA4IN
P60/TA4OUT
P57/TA3IN/KI3
P56/TA3OUT/KI2
P55/TA2IN/KI1
P54/TA2OUT/KI0
P53/TA1IN
P52/TA1OUT
P51/TA0IN
P50/TA0OUT
P47
P46
P45
P44
P43
P42/ φ 1
P83/TXD0
P82/RXD0/CLKS0
P81/CLK0
P80/CTS0/RTS0/CLKS1
VCC
AVCC
VREF
AVSS
VSS
P77/AN7/XcIN
P76/AN6/XcOUT
P75/AN5/ADTRG/TxD2
P74/AN4/RxD2
P73/AN3/CLK2
P72/AN2/CTS2
P71/AN1
63
P84/CTS1/RTS1
P85/CLK1
P86/RXD1
P87/TXD1
P00/A0
P01/A1
P02/A2
P03/A3
P04/A4
P05/A5
P06/A6
P07/A7
P10/A8/D8
P11/A9/D9
P12/A10/D10
P13/A11/D11
P14/A12/D12
P15/A13/D13
P16/A14/D14
P17/A15/D15
P20/A16/D0
P21/A17/D1
P22/A18/D2
P23/A19/D3
PIN CONFIGURATION (TOP VIEW)
Outline 80P6N-A
0
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reference
External data bus width
voltage input
selection input
VREF
BYTE
Data Bus(Even)
Data Bus(Odd)
P0(8)
Instruction Queue Buffer Q0(8)
P1(8)
Instruction Queue Buffer Q2(8)
Address Bus
Input/Output
port P1
Instruction Queue Buffer Q1(8)
AVCC
Instruction Register(8)
Data Buffer DBL(8)
Input/Output
port P0
Data Buffer DBH(8)
Incrementer/Decrementer(24)
(0V)
VSS
Program Counter PC(16)
Program Bank Register PG(8)
Input/Output
port P3
P2(8)
A-D Converter(10)
CNVss
Data Address Register DA(24)
P3(4)
(0V)
AVSS
Program Address Register PA(24)
Input/Output
port P2
Incrementer(24)
2
P4(8)
Input/Output
port P4
Input/Output
port P5
Input/Output
port P6
Timer TB0(16)
Timer TA0(16)
P5(8)
Timer TB1(16)
P6(8)
Timer TB2(16)
Timer TA1(16)
UART0(9)
UART2(9)
Watchdog Timer
XCOUT
XCIN
Accumulatcr B(16)
E
Input/Output
port P7
P7(8)
3968 bytes
RAM
Accumulator A(16)
Input/Output
port P8
124 Kbytes
P8(8)
XCOUT
XCIN
Arithmetic Logic
Unit(16)
ROM
Clock Generating Circuit
Enable output
Index Register X(16)
Timer TA4(16)
Stack Pointer S(16)
Timer TA2(16)
RESET
Direct Page Register DPR(16)
Index Register Y(16)
Clock input Clock output
XIN
XOUT
M37733MHBXXXFP BLOCK DIAGRAM
Reset input
Processor Status Register PS(11)
Timer TA3(16)
Input Butter Register IB(16)
UART1(9)
VCC
Data Bank Register DT(8)
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MITSUBISHI MICROCOMPUTERS
M37733MHBXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
FUNCTIONS OF M37733MHBXXXFP
Parameter
Number of basic instructions
Instruction execution time
Memory size
Input/Output ports
Multi-function timers
ROM
RAM
P0 – P2, P4 – P8
P3
TA0, TA1, TA2, TA3, TA4
TB0, TB1, TB2
Serial I/O
A-D converter
Watchdog timer
Interrupts
Clock generating circuit
Supply voltage
Power dissipation
Input/Output characteristic
Memory expansion
Operating temperature range
Device structure
Package
Input/Output voltage
Output current
Functions
103
160 ns (the fastest instruction at external clock 25 MHz frequency)
124 Kbytes
3968 bytes
8-bit ✕ 8
4-bit ✕ 1
16-bit ✕ 5
16-bit ✕ 3
(UART or clock synchronous serial I/O) ✕ 3
10-bit ✕ 1 (8 channels)
12-bit ✕ 1
3 external types, 16 internal types
Each interrupt can be set to the priority level (0 – 7.)
2 circuits built-in (externally connected to a ceramic resonator or a
quartz-crystal oscillator)
5 V ± 10%
47.5 mW (at external clock 25 MHz frequency)
5V
5 mA
Maximum 16 Mbytes
–20 to 85 °C
CMOS high-performance silicon gate process
80-pin plastic molded QFP (80P6N-A)
3
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Pin
Vcc,
Vss
CNVss
CNVss input
Input
RESET
Reset input
Input
XIN
Clock input
Input
XOUT
Clock output
Enable output
Output
Output
External data
bus width
selection input
Analog power
source input
Reference
voltage input
I/O port P0
Input
E
BYTE
AVcc,
AVss
VREF
P00 – P07
Name
Input/Output
Power source
Apply 5 V ± 10% to Vcc and 0 V to Vss.
This pin controls the processor mode. Connect to Vss for the single-chip mode and the memory
expansion mode, and to Vcc for the microprocessor mode.
When “L” level is applied to this pin, the microcomputer enters the reset state.
These are pins of main-clock generating circuit. Connect a ceramic resonator or a quartzcrystal oscillator between XIN and XOUT . When an external clock is used, the clock source should
be connected to the XIN pin, and the XOUT pin should be left open.
This pin functions as the enable signal output pin which indicates the access status in the internal
bus. When output level of E signal is “L”, data/instruction read or data write is performed.
In the memory expansion mode or the microprocessor mode, this pin determines whether the
external data bus has an 8-bit width or a 16-bit width. The data bus has a 16-bit width when “L”
signal is input and an 8-bit width when “H” signal is input.
Power source input pin for the A-D converter. Externally connect AVcc to Vcc and AVss to Vss.
Input
This is reference voltage input pin for the A-D converter.
I/O
In the single-chip mode, port P0 becomes an 8-bit I/O port. An I/O direction register is available so
that each pin can be programmed for input or output. These ports are in the input mode when
reset.
In the memory expansion mode or the microprocessor mode, these pins output address (A0 – A 7).
In the single-chip mode, these pins have the same functions as port P0. When the BYTE pin is set
to “L” in the memory expansion mode or the microprocessor mode and external data bus has a
16-bit width, high-order data (D8 – D 15) is input/output or an address (A8 – A15 ) is output. When
the BYTE pin is “H” and an external data bus has an 8-bit width, only address (A8 – A 15) is output.
In the single-chip mode, these pins have the same functions as port P0. In the memory expansion
mode or the microprocessor mode, low-order data (D0 – D7) is input/output or an address
(A0 – A7) is output .
In the single-chip mode, these pins have the same function as port P0. In the memory expansion
mode or the microprocessor mode, R/W, BHE, ALE, and HLDA signals are output.
In the single-chip mode, these pins have the same functions as port P0. In the memory expansion
mode or the microprocessor mode, P40, P41 and P42 become HOLD and RDY input pins, and a
clock φ 1 output pin, respectively. Functions of the other pins are the same as in the single-chip
mode. However, in the memory expansion mode, P42 can be selected as an I/O port.
In addition to having the same functions as port P0 in the single-chip mode, these pins also
function as I/O pins for timers A0 to A3 and input pins for key input interrupt input (KI0 – KI3 ).
In addition to having the same functions as port P0 in the single-chip mode, these pins also
function as I/O pins for timer A4, input pins for external interrupt input (INT0 – INT2) and input pins
for timers B0 to B2. P67 also functions as sub-clock φ SUB output pin.
In addition to having the same functions as port P0 in the single-chip mode, these pins function as
input pins for A-D converter. P72 to P75 also function as I/O pins for UART2. Additionally, P7 6 and
P77 have the function as the output pin (X COUT) and the input pin (XCIN) of the sub-clock (32 kHz)
oscillation circuit, respectively. When P76 and P77 are used as the XCOUT and XCIN pins, connect
a resonator or an oscillator between the both.
In addition to having the same functions as port P0 in the single-chip mode, these pins also
function as I/O pins for UART 0 and UART 1.
P10 – P17 I/O port P1
I/O
P20 – P27 I/O port P2
I/O
P30 – P33 I/O port P3
I/O
P40 – P47 I/O port P4
I/O
P50 – P57 I/O port P5
I/O
P60 – P67 I/O port P6
I/O
P70 – P77 I/O port P7
I/O
P80 – P87 I/O port P8
I/O
4
Functions
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
BASIC FUNCTION BLOCKS
The M37733MHBXXXFP contains the following peripheral devices
on a single chip: ROM, RAM, CPU, bus interface unit, timers, serial
I/O, A-D converter, I/O ports, clock generating circuit and others. Each
of these devices is described below.
MEMORY
The memory map is shown in Figure 1. The address space has a
capacity of 16 Mbytes and is allocated to addresses from 016 to
FFFFFF16. The address space is divided by 64-Kbyte unit called bank.
The banks are numbered from 016 to FF16.
Built-in ROM, RAM and control registers for internal peripheral devices
are assigned to banks 016 and 1 16.
The 124-Kbyte area from addresses 100016 to 1FFFF16 is the built-in
ROM. Addresses FFD616 to FFFF16 are the RESET and interrupt
vector addresses and contain the interrupt vectors. Refer to the section
on interrupts for details.
The 3968-byte area allocated to addresses from 8016 to FFF16 is the
built-in RAM. In addition to storing data, the RAM is used as stack
during a subroutine call or interrupts.
00000016
Peripheral devices such as I/O ports, A-D converter, serial I/O, timer,
and interrupt control registers are allocated to addresses from 016 to
7F16 .
Additionally, the internal ROM and RAM area can be modified by
software. Refer to the section on ROM area modification function for
details.
A 256-byte direct page area can be allocated anywhere in bank 016
by using the direct page register (DPR). In the direct page addressing
mode, the memory in the direct page area can be accessed with two
words. Hence program steps can be reduced.
00000016
00007F16
00008016
00000016
Internal peripheral
devices
control registers
Bank 016
refer to Fig. 2 for
detail information
Internal RAM
3968 bytes
00FFFF16
01000016
00007F16
000FFF16
00100016
Bank 116
Interrupt vector table
00FFD616
A-D/UART2 trans./rece.
UART1 transmission
01FFFF16
UART1 receive
•••••••••••••••••••
UART0 transmission
UART0 receive
Timer B2
Timer B1
Internal ROM
124 Kbytes
Timer B0
Timer A4
00FFD616
Timer A3
Timer A2
00FFFF16
FE000016
Timer A1
Timer A0
Bank FE16
INT2/Key input
INT 1
INT 0
FEFFFF16
FF000016
Watchdog timer
DBC
Bank FF16
BRK instruction
Zero divide
FFFFFF16
01FFFF16
00FFFE16
RESET
Note. Internal ROM and RAM area can be modified. (Refer to the section on ROM area modification function.)
Fig. 1 Memory map
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Address (Hexadecimal notation)
000000
000001
000002 Port P0 register
000003 Port P1 register
000004 Port P0 direction register
000005 Port P1 direction register
000006 Port P2 register
000007 Port P3 register
000008 Port P2 direction register
000009 Port P3 direction register
00000A Port P4 register
00000B Port P5 register
00000C Port P4 direction register
00000D Port P5 direction register
00000E Port P6 register
00000F Port P7 register
000010 Port P6 direction register
000011 Port P7 direction register
000012 Port P8 register
000013
000014 Port P8 direction register
000015
000016
000017
000018
000019
00001A
00001B
00001C Reserved area (Note)
00001D Reserved area (Note)
00001E A-D control register 0
00001F A-D control register 1
000020
A-D register 0
000021
000022
A-D register 1
000023
000024
A-D register 2
000025
000026
A-D register 3
000027
000028
A-D register 4
000029
00002A
A-D register 5
00002B
00002C
A-D register 6
00002D
00002E
A-D register 7
00002F
UART
0 transmit/receive mode register
000030
000031 UART 0 baud rate register (BRG0)
000032 UART 0 transmission buffer register
000033
000034 UART 0 transmit/receive control register 0
000035 UART 0 transmit/receive control register 1
000036
UART 0 receive buffer register
000037
000038 UART 1 transmit/receive mode register
000039 UART 1 baud rate register (BRG1)
00003A
UART 1 transmission buffer register
00003B
00003C UART 1 transmit/receive control register 0
00003D UART 1 transmit/receive control register 1
00003E
UART 1 receive buffer register
00003F
Address (Hexadecimal notation)
000040
000041
000042
000043
000044
000045
000046
000047
000048
000049
00004A
00004B
00004C
00004D
00004E
00004F
000050
000051
000052
000053
000054
000055
000056
000057
000058
000059
00005A
00005B
00005C
00005D
00005E
00005F
000060
000061
000062
000063
000064
000065
000066
000067
000068
000069
00006A
00006B
00006C
00006D
00006E
00006F
000070
000071
000072
000073
000074
000075
000076
000077
000078
000079
00007A
00007B
00007C
00007D
00007E
00007F
Count start flag
One-shot start flag
Up-down flag
Timer A0 register
Timer A1 register
Timer A2 register
Timer A3 register
Timer A4 register
Timer B0 register
Timer B1 register
Timer B2 register
Timer A0 mode register
Timer A1 mode register
Timer A2 mode register
Timer A3 mode register
Timer A4 mode register
Timer B0 mode register
Timer B1 mode register
Timer B2 mode register
Processor mode register 0
Processor mode register 1
Watchdog timer register
Watchdog timer frequency selection flag
Reserved area (Note)
Memory allocation control register
UART 2 transmit/receive mode register
UART 2 baud rate register (BRG2)
UART 2 transmission buffer register
UART 2 transmit/receive control register 0
UART 2 transmit/receive control register 1
UART 2 receive buffer register
Oscillation circuit control register 0
Port function control register
Serial transmit control register
Oscillation circuit control register 1
A-D/UART 2 trans./rece. interrupt control register
UART 0 transmission interrupt control register
UART 0 receive interrupt control register
UART 1 transmission interrupt control register
UART 1 receive interrupt control register
Timer A0 interrupt control register
Timer A1 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
Timer B2 interrupt control register
INT0 interrupt control register
INT1 interrupt control register
INT2/Key input interrupt control register
Note. Do not write to this address.
Fig. 2 Location of internal peripheral devices and interrupt control registers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CENTRAL PROCESSING UNIT (CPU)
The CPU has ten registers and is shown in Figure 3. Each of these
registers is described below.
Also, when executing a block transfer instruction (MVP, MVN), the
contents of index register X indicates the low-order 16 bits of the
source data address. The third byte of the MVP or MVN is the highorder 8 bits of the source data address.
ACCUMULATOR A (A)
Accumulator A is the main register of the microcomputer. It consists
of 16 bits and the low-order 8 bits can be used separately. The data
length flag (m) determines whether the register is used as a 16-bit
register or as an 8-bit register. It is used as a 16-bit register when flag
m is “0” and as an 8-bit register when flag m is “1”. Flag m is a part of
the processor status register (PS) which is described later.
Data operations such as arithmetic operation, data transfer, input/
output, etc., are executed mainly through the accumulator A.
ACCUMULATOR B (B)
Accumulator B has the same functions as accumulator A, but the
use of accumulator B requires more instruction bytes and execution
cycles than accumulator A.
INDEX REGISTER Y (Y)
Index register Y consists of 16 bits and the low-order 8 bits can be
used separately. The index register length flag (x) determines whether
the register is used as a 16-bit register or as an 8-bit register. It is
used as a 16-bit register when flag x is “0” and as an 8-bit register
when flag x is “1”. Flag x is a part of the processor status register
(PS) which is described later.
In an index addressing mode where register Y is used as the index
register, the contents of this address is added to obtain the real
address.
Also, when executing a block transfer instruction (MVP, MVN), the
contents of index register Y indicates the low-order 16 bits of the
destination data address. The second byte of the MVP or MVN is the
high-order 8 bits of the destination data address.
INDEX REGISTER X (X)
Index register X consists of 16 bits and the low-order 8 bits can be
used separately. The index register length flag (x) determines whether
the register is used as a 16-bit register or as an 8-bit register. It is
used as a 16-bit register when flag x is “0” and as an 8-bit register
when flag x is “1”. Flag x is a part of the processor status register
(PS) which is described later.
In an index addressing mode where register X is used as the index
register, the contents of this address is added to obtain the real
address.
15
7
AH
0
Accumulator A (A)
AL
15
7
BH
0
Accumulator B (B)
BL
15
7
XH
0
Index register X (X)
XL
15
7
YH
0
YL
15
Index register Y (Y)
0
S
7
15
0
15
0
DT
PC
Program bank register (PG)
PG
7
Stack pointer (S)
0
Program counter (PC)
0
DPR
Data bank register (DT)
15
0 0 0 0 0
7
IPL2 IPL1 IPL0
Direct page register (DPR)
0
N V m x D I Z C
Processor status register (PS)
Carry flag
Zero frag
Interrupt disable flag
Decimal mode flag
Index register length flag
Data length flag
Overflow flag
Negative flag
Processor interrupt priority level (IPL)
Fig. 3 Register structure
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
STACK POINTER (S)
1. Carry flag (C)
Stack pointer (S) is a 16-bit register. It is used during a subroutine
call or interrupts. It is also used during stack, stack pointer relative,
or stack pointer relative indirect indexed Y addressing modes.
The carry flag contains the carry or borrow generated by the ALU
after an arithmetic operation. This flag is also affected by shift or
rotate instruction. This flag can be set or reset directly with the SEC,
CLC instructions or with the SEP, CLP instructions.
PROGRAM COUNTER (PC)
Program counter (PC) is a 16-bit counter that indicates the low-order
16 bits of the next program memory address to be executed. There
is a bus interface unit between the program memory and the CPU,
so that the program memory is accessed through the bus interface
unit. This is described later.
2. Zero flag (Z)
This zero flag is set when the result of an arithmetic operation or data
transfer is zero and reset when it is not. This flag can be set or reset
directly with the SEP or CLP instruction.
3. Interrupt disable flag ( I )
PROGRAM BANK REGISTER (PG)
Program bank register (PG) is an 8-bit register that indicates the highorder 8 bits of the next program memory address to be executed.
When a carry occurs by incrementing the contents of the program
counter, the contents of the program bank register (PG) is incremented
by 1. Also, when a carry or borrow occurs after adding or subtracting
the offset value to or from the contents of the program counter (PC)
by using a branch instruction, the contents of the program bank
register (PG) is incremented or decremented by 1 so that programs
can be written without worrying about bank boundaries.
DATA BANK REGISTER (DT)
Data bank register (DT) is an 8-bit register. With some addressing
modes, a part of the data bank register (DT) is used to specify a
memory address. The contents of data bank register (DT) is used as
the high-order 8 bits of a 24-bit address. Addressing modes that use
the data bank register (DT) to specify the address are direct indirect,
direct indexed X indirect, direct indirect indexed Y, absolute, absolute
bit, absolute indexed X, absolute indexed Y, absolute bit relative,
and stack pointer relative indirect indexed Y.
DIRECT PAGE REGISTER (DPR)
Direct page register (DPR) is a 16-bit register. Its contents is used as
the base address of a 256-byte direct page area. The direct page
area is allocated in bank 016, but when the contents of DPR is FF0116
or more, the direct page area spans across bank 016 and bank 116 .
All direct addressing modes use the contents of the direct page register
(DPR) to generate the data address. If the low-order 8 bits’ contents
of the direct page register (DPR) is “0016 ”, the number of cycles
required to generate an address is minimized. Hence the low-order 8
bits’ contents of the direct page register (DPR) is usually set to “0016 ”.
PROCESSOR STATUS REGISTER (PS)
Processor status register (PS) is an 11-bit register. It consists of flags
which indicate the result of operation and the processor interrupt
priority level (IPL).
Branch operations can be performed by testing flags C, Z , V, and N.
The details of each processor status register bit are described below.
8
When the interrupt disable flag is “1”, all interrupts except watchdog
timer, DBC , and software interrupt are disabled. This flag is
automatically set to “1” when an interrupt is accepted. It can be set or
reset directly with the SEI, CLI instructions or SEP and CLP
instructions.
4. Decimal mode flag (D)
The decimal mode flag determines whether addition and subtraction
are performed in the binary or the decimal system. Binary arithmetic
is performed when this flag is “0”. If it is “1”, decimal arithmetic is
performed with each word treated as the 2- or 4-digit number.
Arithmetic operation is performed with 4-digit number when the data
length flag (m) is “0” and with 2-digit number when it is “1”. Decimal
correction is automatically performed. (Decimal operation is possible
only with the ADC and SBC instructions.) This flag can be set or
reset with the SEP or CLP instruction.
5. Index register length flag (x)
The index register length flag determines whether index register X
and index register Y are used as 16-bit registers or as 8-bit registers.
The registers are used as 16-bit registers when flag x is “0” and as 8bit registers when it is “1”. This flag can be set or reset with the SEP
or CLP instruction.
6. Data length flag (m)
The data length flag determines whether the data has a length of 16
bits or that of 8 bits. The 16-bit length is selected when flag m is “0”
and the 8-bit length is selected when it is “1”. This flag can be set or
reset with the SEM, CLM instructions or with the SEP, CLP
instructions.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
7. Overflow flag (V)
9. Processor interrupt priority level (IPL)
The overflow flag is effective only when addition or subtraction is
performed with treating a word as a signed binary number. When the
data length flag (m) is “0”, the overflow flag is set if the result of
addition or subtraction is outside the range between – 32768 and
+32767. When the data length flag (m) is “1”, the overflow flag is set
if the result of addition or subtraction is outside the range between
–128 and +127. It is reset in the other cases. The overflow flag can
also be set or reset directly with the SEP or CLV, CLP instructions.
The processor interrupt priority level (IPL) consists of 3 bits and
determines the processor interrupt priority level (0 to 7). Interrupt is
enabled when the interrupt priority level of the device requesting
interrupt (the priority can be set using the interrupt control register) is
higher than the processor interrupt priority level. When interrupt is
enabled, the current processor interrupt priority level is saved in a
stack and the processor interrupt priority level is replaced by the
interrupt priority level of the device requesting the interrupt. Refer to
the section on interrupts for more details.
8. Negative flag (N)
The negative flag is set when the result of arithmetic operation or
data transfer is negative (If data length flag (m) is “0”, data bit 15 is
“1”. If data length flag (m) is “1”, data bit 7 is “1”.) It is reset in the
other cases. It can also be set or reset with the SEP or CLP
instructions.
BUS INTERFACE UNIT
The CPU operates on an internal clock ’s frequency. Internal clock
’s frequency is twice the bus cycle frequency. In order to speed up
processing, a bus interface unit is used to pre-fetch instructions when
the data bus is idle. The bus interface unit synchronizes the CPU
and the bus and pre-fetches instructions. Figure 4 shows the
relationship between the CPU and the bus interface unit. The bus
interface unit has a program address register, a 3-byte instruction
queue buffer, a data address register, and a 2-byte data buffer.
The bus interface unit obtains an instruction code from the memory
and stores it in the instruction queue buffer, obtains data from the
memory and stores it in the data buffer, or writes the data from the
data buffer to the memory.
D'15 – D'8
D15 – D8
D'7 – D'0
D7 – D0
A'23 – A'0
A23 – A0
Bus interface
unit
CPU
BHE
R/W
E
Control signal
ALE
BYTE
HOLD
Fig. 4 Relationship between the CPU and the bus interface unit
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
microprocessor mode, set the bus width selection input pin (BYTE)
to “L” (external data bus has a width of 16 bits). The data bus in the
internal memory area is always treated as the 16-bit bus independent
of BYTE.
The bus interface unit operates using one of the waveforms (1) to
(10) shown in Figure 5. The standard waveforms are (1) and (2).
The ALE signal is used to latch only the address signal from the
multiplexed signal containing data and address.
The E signal becomes “L” when the bus interface unit reads an
instruction code or data from the memory or when it writes data to
the memory. Whether to perform read or write is controlled by the
R/ W signal. When the R/W signal is “H”, read is performed; when “L”,
write is performed.
Waveform (1) in Figure 5 is used to access a single byte or two bytes
simultaneously. To read or write two bytes simultaneously, the first
address accessed must be even. Furthermore, when accessing an
external memory area in the memory expansion mode or the
Internal clock φ
Internal clock φ
Port P2
(1)
A
Port P2
D
E
(7)
ALE
E
ALE
Access time
Port P2
(2)
D
A
A
D
Access time
A
Port P2
D
A+1
E
D
E
(8)
ALE
ALE
Access time
A
Port P2
(3)
Access time
D
A
Port P2
(9)
E
ALE
A
D
Access time
D
A +1
Port P2
(10)
E
ALE
Port P2
A
A+1
D
Access time
A
D
A+1
E
ALE
Access time
10
A+1
Access time
D
A : Address
D : Data
ALE
Fig. 5 Bus access timing
D
ALE
E
Port P2
A
E
Access time
(6)
A+1
ALE
Port P2
(5)
D
E
Access time
(4)
A+1
D
D
D
D
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MITSUBISHI MICROCOMPUTERS
M37733MHBXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
When performing 16-bit data read or write, waveform (2) is used to
access each byte one by one if the conditions for simultaneously
accessing two bytes are not satisfied. However, when prefetching
the instruction code, if the address of the instruction code is odd,
waveform (1) is used, and only one byte is read in the instruction
queue buffer.
Access to the even/odd address is controlled by signals BHE and A0.
Bit 2 of processor mode register 0 (address 5E16) is the wait bit.
When the external memory area is accessed in the memory expansion
mode or the microprocessor mode with this bit set to “0”, the width of
the E signal is extended and access time can be extended.
There are two ways to extend the access time and they are selected
with bit 0 of the processor mode register 1 (address 5F16).
When this bit is set to “1”, the “L” width of the E signal in (1) becomes
twice as long as in (3) and the access time becomes 1.5 times (wait
1). When this bit is set to “0”, the ALE signal and E signal in (1) are
extended as in (7) and the access time is doubled (wait 0).
However, these signals are not extended when accessing the internal
memory area.
When the wait bit is set to “1”, these signals are not extended when
accessing any memory area regardless of the bit 0 of the processor
mode register 1.
Waveforms (4), (5), and (6) show the entire waveform, first half, and
last half respectively of waveform (2) for wait 1.
Waveforms (8), (9), and (10) show the entire waveform, first half,
and last half respectively of waveform (2) for wait 0.
Instruction code read, data read, and data write are described below.
Instruction code read will be described first.
The CPU obtains instruction codes from the instruction queue buffer
and executes them. The CPU notifies the bus interface unit that it is
requesting an instruction code during an instruction code request
cycle. If the requested instruction code is not yet stored in the
instruction queue buffer, the bus interface unit halts the CPU until
more instructions than requested is stored in the instruction queue
buffer. Even if there is no instruction code request from the CPU, the
bus interface unit reads instruction codes from the memory and stores
them in the instruction queue buffer when the instruction queue buffer
is empty or when only one instruction code is stored and the bus is
idle on the next cycle. This is referred to as instruction pre-fetching.
Normally , when reading an instruction code from the memory, if the
accessed address is even, the next odd address is read together
with the instruction code and stored in the instruction queue buffer.
However, in the memory expansion mode or the microprocessor
mode, only one byte is read and stored in the instruction queue buffer
if the following conditions are satisfied.
• The address to be read is in the external memory area when the
external data bus has an 8-bit width (BYTE = “H”).
• The address to be read is odd.
Therefore, waveform (1), (3) or (7) in Figure 5 is used for instruction
code read. Data read and write are described below.
The CPU notifies the bus interface unit when performing data read or
write. At this time, the bus interface unit halts the CPU if the bus
interface unit is already using the bus or if there is a request with
higher priority. When data read or write is enabled, the bus interface
unit uses one of the waveforms from (1) to (10) in Figure 5 to perform
the operation.
During data read, the CPU waits until the entire data is stored in the
data buffer. The bus interface unit sends the address received from
the CPU to the address bus. Then it reads the memory when the E
signal is “L” and stores the result in the data buffer.
During data write, the CPU writes the data in the data buffer and the
bus interface unit writes it to the memory . Therefore, the CPU can
proceed to the next step without waiting for write completed. The bus
interface unit sends the address received from the CPU to the address
bus. Then when the E signal is “L”, the bus interface unit sends the
data in the data buffer to the data bus and writes it to the memory.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
INTERRUPTS
Table 1. Interrupt sources and the interrupt vector addresses
Table 1 shows the interrupt sources and the corresponding interrupt
vector addresses. Reset is also treated as a source of interrupt and
is described in this section.
DBC is an interrupt used only for debugging.
Interrupts other than reset, DBC, watchdog timer, zero divide, and
BRK instruction all have their respective interrupt control registers.
Table 2 shows the addresses of the interrupt control registers and
Figure 6 shows the bit configuration of the interrupt control register.
The interrupt request bit is automatically cleared by hardware during
reset or when processing an interrupt. Also, interrupt request bits
other than DBC and watchdog timer can be cleared by software.
INT0 to INT2 are external interrupts, and whether to cause an interrupt
at the input level (level sense) or at the edge (edge sense) can be
selected with the level sense/edge sense selection bit. Furthermore,
the polarity of the interrupt input can be selected with a polarity
selection bit.
In the INT2 /Key input interrupt, whether to input an interrupt request
from the INT2 pin or the KI0 – KI3 pins can be selected by bit 7 of the
port function control register (refer to Figure 11).
Timer and UART interrupts are described in the respective section.
The priority of interrupts when multiple interrupts are caused
simultaneously is partially fixed by hardware, but it can also be
adjusted by software as shown in Figure 7. The hardware priority is
fixed as follows:
reset > DBC > watchdog timer > other interrupts
Interrupts
A-D/UART2 trans./rece.
UART1 transmit
UART1 receive
UART0 transmit
UART0 receive
Timer B2
Timer B1
Timer B0
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
INT2 /Key input
INT1
INT0
Watchdog timer
DBC (unusable)
BRK instruction
Zero divide
Reset
Vector addresses
00FFD616 00FFD716
00FFD816 00FFD916
00FFDA16 00FFDB16
00FFDC16 00FFDD16
00FFDE16 00FFDF16
00FFE016 00FFE116
00FFE216 00FFE316
00FFE416 00FFE516
00FFE616 00FFE716
00FFE816 00FFE916
00FFEA16 00FFEB16
00FFEC16 00FFED16
00FFEE16 00FFEF16
00FFF016
00FFF116
00FFF216
00FFF316
00FFF416
00FFF516
00FFF616
00FFF716
00FFF816
00FFF916
00FFFA16 00FFFB16
00FFFC16 00FFFD16
00FFFE16 00FFFF16
7 6 5 4 3 2 1 0
Interrupt priority level selection bits
Interrupt request bit
0 : No interrupt
1 : Interrupt
Interrupt control register configuration for timers A0 to A4, timers B0 to B2, UART0, UART1 and
A-D/UART2 trans./rece.
7 6 5 4 3 2 1 0
Interrupt priority level selection bits
Interrupt request bit
0 : No interrupt
1 : Interrupt
Polarity selection bit
0 : Interrupt request bit is set at “H” level for level sense or at the falling
edge for edge sence.
1 : Interrupt request bit is set at “L” level for level sense or at the rising
edge for edge sense.
Level sense/edge sense selection bit
0 : Edge sense
1 : Level sense
Interrupt control register configuration for INT0 to INT2/Key input
Fig. 6 Interrupt control register bit configuration
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 2. Addresses of interrupt control registers
Interrupt control registers
A-D/UART2 trans./rece. interrput control register
UART0 transmit interrput control register
UART0 receive interrput control register
UART1 transmit interrput control register
UART1 receive interrupt control register
Timer A0 interrupt control register
Timer A1 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
Timer B2 interrupt control register
INT0 interrupt control register
INT1 interrupt control register
INT2 /Key input interrupt control register
addresses
00007016
00007116
00007216
00007316
00007416
00007516
00007616
00007716
00007816
00007916
00007A16
00007B16
00007C16
00007D16
00007E16
00007F16
Because priority detection takes some time, no sampling pulse is
generated for a certain interval even if it is the next operation code
fetch cycle.
Priority is determined by hardware
➃
4
3
➂
2
1
Watchdog
timer
DBC
Reset
A-D converter, UART, Timer, INT interrupts
Priority can be changed by software inside 4
Fig. 7 Interrupt priority
Level 0
Interrupts caused by a BRK instruction and when dividing by zero
are software interrupts and are not included in this list.
Other interrupts previously mentioned are A-D converter, UART,
Timer, INT interrupts. The priority of these interrupts can be changed
by changing the interrupt priority level selection bits of the
corresponding interrupt control register with software.
Figure 8 shows a diagram of the interrupt priority detection circuit.
When an interrupt is caused, the each interrupt device compares its
own priority with the priority from above and if its own priority is higher,
then it sends the priority below and requests the interrupt. If the
priorities are the same, the one above has priority.
This comparison is repeated to select the interrupt with the highest
priority among the interrupts that are being requested. Finally the
selected interrupt is compared with the processor interrupt priority
level (IPL) contained in the processor status register (PS), and the
request is accepted if it is higher than IPL and the interrupt disable
flag (I) is “0”. The request is not accepted if flag I is “1”. The reset,
DBC, and watchdog timer interrupts are not affected by the interrupt
disable flag (I).
When an interrupt is accepted, the contents of the processor status
register (PS) is saved to the stack and the interrupt disable flag (I) is
set to “1”.
Furthermore, the interrupt request bit of the accepted interrupt is
cleared to “0” and the processor interrupt priority level (IPL) in the
processor status register (PS) is replaced by the priority level of the
accepted interrupt.
Therefore, multiple interrupts are possible by resetting the interrupt
disable flag (I) to “0” and enable further interrupts.
For reset, DBC, watchdog timer, zero divide, and BRK instruction
interrupts, which do not have an interrupt control register, the
processor interrupt level (IPL) is set as shown in Table 3.
Priority detection is performed by latching the interrupt request bit
and interrupt priority level selection bits so that they do not change.
They are sampled at the first half and latched at the last half of the
operation code fetch cycle.
A-D/UART2
trans./rece.
Interrupt request
UART1 transmit
UART1 receive
UART0 transmit
Reset
UART0 receive
Timer B2
Timer B1
DBC
Timer B0
Timer A4
Timer A3
Watchdog
timer
Timer A2
Timer A1
Interrupt disable flag(I)
Timer A0
INT2/Key input
IPL
INT1
INT0
Fig. 8 Interrupt priority detection circuit
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
As shown in Figure 9, there are three different interrupt priority
detection time from which one is selected by software. After the
selected time has elapsed, the interrupt which has the highest priority
is determined and is processed after the current instruction execution
has been completed.
The time is selected with bits 4 and 5 of the processor mode register
0 (address 5E16) shown in Figure 10. Table 4 shows the relationship
between these bits and the number of cycles. After a reset, the
processor mode register 0 is initialized to “0016”. Therefore, the longest
time is selected. However, the shortest time should be selected by
software.
Table 3. Value set in processor interrupt level (IPL) during an interrupt
Interrupt types
Setting value
Reset
0
DBC
7
Watchdog timer
7
Zero divide
Not change value of IPL.
BRK instruction
Not change value of IPL.
Table 4. Relationship between interrupt priority detection time selection bits and number of cycles
Interrupt priority detection time selection bits
Number of cycles
Bit 5
Bit 4
0
0
7 cycles of φ
0
1
4 cycles of φ
1
0
2 cycles of φ
φ : internal clock
Internal clock φ
Operation code fetch cycle
Sampling pulse
Priority detection time
0
Select one from 0 to 2 with
bits 4 and 5 of the
processor mode register 0
1
2
Fig. 9 Interrupt priority detection time
7
6
5
4
0
3
2
1
0
Address
Processor mode register 0 (5E 16)
Processor mode bits
0 0 : Single-chip mode
0 1 : Memory expansion mode
1 0 : Microprocessor mode
Wait bit
0 : Wait
1 : No wait
Software reset bit
The processor is reset when this bit is set to “1” .
Interrupt priority detection time selection bits
0 0 : Select 0 in Figure 9
0 1 : Select 1 in Figure 9
1 0 : Select 2 in Figure 9
Always “0”
Clock φ 1 output selection bit
0 : No φ 1 output
1 : φ 1 output
Fig. 10 Processor mode register 0 configuration
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pull-up resistors (transistors) can be added to the KI0 to KI3 pins by
setting “1” to the port P5 pull-up selection bit and “0” to the contents
of the port P5i (i = 4 to 7) direction register. Similarly, a pull-up resistor
can be added to the INT2 pin by setting “1” to the port P6 pull-up
selection bit 1 and “0” to the content of the port P64 direction register.
With the key input interrupt and the pull-up function, the key input
circuit is easily composed.
By setting the port function control register, the INT2 /Key input interrupt
function can be switched to the key input interrupt function which
uses the KI0 to KI3 inputs. Figure 11 shows the bit configuration of the
port function control register, and Figure 12 shows the INT2 /Key input
interrupt input circuit block diagram.
When the key input interrupt selection bit of the port function control
register is “0”, a signal is input from the INT2 pin to the INT2 /Key input
interrupt control circuit and the INT2 interrupt is normally performed.
When the key input interrupt selection bit is “1”, signals input from
the KI0 to KI3 pins are inverted, and then the logical sum of these
signals is input to the INT2 interrupt control circuit. In this case, the
external interrupt which uses the KI0 to KI3 pins is performed. (Pins
KI0 to KI3 correspond to ports P54 to P57, respectively.) Additionally,
by setting the port P6 pull-up selection bit 1 to “1”, the INT2 input is
added to that logical sum, so that the external interrupt which uses
the inputs KI0 to KI3 and INT2 is performed. When using the key input
interrupt, it is necessary to select the edge sense which uses the
falling edge by setting the INT2 /Key input interrupt control register.
Because of this selection, a key input interrupt request occurs when
“L” is input to one of the KI0 to KI3 and INT2 pins. The interrupt vector
and the interrupt control register are common to the INT2 and key
input interrupts.
Port P6 pull-up
selection bit 1
Port P64 direction register
P64/INT2
INT2/Key input interrupt control register
Port P6 pull-up
selection bit 1
Port P5 pull-up
selection bit
Pull–up
transistor
(Address 7F16)
When the key input interrupt is
selected, it is necessary to
select the edge sense which
uses falling edge.
0
Port P57 direction
register
P57/KI3
Pull–up
transistor
1
0
Interrupt control register
P56/KI2
INT2/Key input
interrupt request
1
Pull–up
transistor
Key input interrupt selection bit
P55/KI1
Pull–up
transistor
P54/KI0
Fig. 12 INT2 /Key input interrupt input circuit block diagram
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
7
6
5
4
0
3
2
1
0
Port function control register
Address
6D16
Standby state selection bit
0: Pins P0 – P3 as external bus output
1: Pins P0 – P3 as port output
Sub-clock output selection bit/Timer B2 clock source selection bit
• Port-Xc selection bit = “0” (sub-clock not used)
Timer B2 (event counter mode) clock source selection
0: TB2IN input
1: Main clock divided by 32
• Port-Xc selection bit = “1” (sub-clock used)
Sub-clock output selection
0: Function as port P67 pin
1: Output sub-clock φ SUB from P67/TB2IN/ φ SUB pin
Timer B1 internal connect selection bit
0: No internal connect
1: Internal connect to timer B2
Port P6 pull-up selection bit 0
0: With no pull-up transistor for pins P62/INT0, P63/INT1
1: With pull-up transistor for pins P62/INT0, P63/INT1
0: Always “0”
Port P6 pull-up selection bit 1
• Key input interrupt selection bit = “0”
0: With no pull-up transistor for P64/INT2 pin
1: With pull-up transistor for P64/INT2 pin
• Key input interrupt selection bit = “1”
0: With port function, no pull-up transistor for P64/INT2 pin
1: With key input interrupt, pull-up transistor for P64/INT2 pin
Port P5 pull-up selection bit
0: With no pull-up transistor for pins P54 – P57
1: With pull-up transistor for pins P54 – P57
Key input interrupt selection bit
0: INT2 interrupt
1: Key input interrupt
Fig. 11 Bit configuration of port function control register
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
TIMER
(1) Timer mode [00]
There are eight 16-bit timers. They are divided by type into timer A(5)
and timer B(3).
The timer I/O pins are also used as I/O pins for ports P5 and P6. To
use these pins as timer input pins, the port direction register bit
corresponding to the pin must be cleared to “0” to specify the input
mode.
Figure 14 shows the bit configuration of the timer Ai mode register
during timer mode. Bits 0, 1, and 5 of timer Ai mode register must
always be “0” in the timer mode.
Bit 3 is ignored if bit 4 is “0”.
Bits 6 and 7 are used to select the timer counter source. The counting
of the selected clock starts when the count start flag is “1” and stops
when it is “0”.
Figure 15 shows the bit configuration of the count start flag. The
counter is decremented. An interrupt is caused and the interrupt
request bit of the timer Ai interrupt control register is set when the
contents becomes 000016. At the same time, the contents of the reload
register are transferred to the counter, and count is continued.
TIMER A
Figure 13 shows a block diagram of timer A.
Timer A has four modes; timer mode, event counter mode, one-shot
pulse mode, and pulse width modulation mode. The mode is selected
with bits 0 and 1 of the timer Ai mode register (i = 0 to 4). Each of
these modes is described below.
Data bus (odd)
Data bus (even)
(Low-order
8 bits)
Clock source selection
f2
f16
f64
f512
• Timer
• One-shot
• Pulse width modulation
(High-order 8 bits)
Reload register(16)
Timer (gate function)
Counter(16)
Up/Down
TAi IN
Polarity
selection
Event counter
Count start flag
(Address 4016)
(i = 0 – 4)
External trigger
Down count
Always decremented
except in event count mode
Address
Timer A0 4716 4616
Timer A1 4916 4816
Timer A2 4B16 4A16
Timer A3 4D16 4C16
Timer A4 4F16 4E16
Up-down flag
(Address 4416)
Pulse output
Toggle flip-flop
TAi OUT
(i = 0 – 4)
Fig. 13 Block diagram of timer A
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
When bit 2 of the timer Ai mode register is “1”, the output is generated
from TAiOUT pin. The output is toggled each time the contents of the
counter reaches to 000016. When the contents of the count start flag
is “0”, “L” is output from TAiOUT pin.
When bit 2 is “0”, TAiOUT can be used as a normal port pin.
When bit 4 is “0”, TAiIN can be used as a normal port pin.
When bit 4 is “1”, counting is performed only while the input signal
from the TAiIN pin is “H” or “L” as shown in Figure 16. Therefore, this
can be used to measure the pulse width of the TAiIN input signal.
Whether to count while the input signal is “H” or while it is “L” is
determined by bit 3. If bit 3 is “1”, counting is performed while the
TAiIN pin input signal is “H” and if bit 3 is “0”, counting is performed
while it is “L”.
Note that the duration of “H” or “L” on the TAiIN pin must be two or
more cycles of the timer count sourse.
When data is written to the timer Ai register with timer Ai halted, the
same data is also written to the reload register and the counter. When
data is written to timer Ai which is busy, the data is written to the
reload register, but not to the counter. The counter is reloaded with
new data from the reload register at the next reload time. The contents
of the counter can be read at any time.
When the value set in the timer Ai register is n, the timer frequency
dividing ratio is 1/(n + 1).
Addresses
7 6 5 4 3 2 1 0
0
Timer A0 mode register
5616
Timer A1 mode register
5716
Timer A2 mode register
5816
Timer A3 mode register
5916
Timer A4 mode register
5A16
0 0
0 0 : Always “00” in timer mode
0 : No pulse output (TAiOUT is normal port pin)
1 : Pulse output
0 ✕ : No gate function (TAiIN is normal port pin)
1 0 : Count only while TAiIN input is “L”
1 1 : Count only while TAiIN input is “H”
0 : Always “0” in timer mode
Clock source selection bit
0 0 : Select f2
0 1 : Select f16
1 0 : Select f64
1 1 : Select f512
Fig. 14 Timer Ai mode register bit configuration during timer mode
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
7 6 5 4 3 2 1 0
Count start flag
(Stop at “0”, Start at “1”)
Address
4016
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
Timer B0 count start flag
Timer B1 count start flag
Timer B2 count start flag
Fig. 15 Count start flag bit configuration
Selected clock source fi
TAiN
Timer mode register
Bit 4
Bit 3
1
0
Timer mode register
Bit 4
Bit 3
1
1
Fig. 16 Count waveform when gate function is available
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) Event counter mode [01]
Figure 17 shows the bit configuration of the timer Ai mode register
during the event counter mode. In the event counter mode, the bit 0
of the timer Ai mode register must be “1” and bits 1 and 5 must be
“0”.
The input signal from the TAiIN pin is counted when the count start
flag shown in Figure 15 is “1” and counting is stopped when it is “0”.
Count is performed at the fall of the input signal when bit 3 is “0” and
at the rise of the signal when it is “1”.
In the event counter mode, whether to increment or decrement the
count can be selected with the up-down flag or the input signal from
the TAiOUT pin.
When bit 4 of the timer Ai mode register is “0”, the up-down flag is
used to determine whether to increment or decrement the count
(decrement when the flag is “0” and increment when it is “1”). Figure
18 shows the bit configuration of the up-down flag.
When bit 4 of the timer Ai mode register is “1”, the input signal from
the TAiOUT pin is used to determine whether to increment or decrement
the count. However, note that bit 2 must be “0” if bit 4 is “1”. Because
TAiOUT pin becomes an output pin with pulse output if bit 2 is “1”.
The count is decremented when the input signal from the TAiOUT pin
is “L” and incremented when it is “H”. Determine the level of the input
signal from the TAiOUT pin before an effective edge is input to the
TAiIN pin.
An interrupt request signal is generated and the interrupt request bit
of the timer Ai interrupt control register is set when the counter reaches
000016 (decrement count) or FFFF16 (increment count). At the same
time, timers A0 and A1 transfer the contents of the reload register to
the counter and continue counting.
Timers A2, A3, and A4 transfer the contents of the reload register to
the counter and continue count when bit 6 of the corresponding timer
Ai mode register is “0”, but when bit 6 is “1”, they continue counting
without transferring the contents of the reload register to the counter.
When bit 2 is “1”, the waveform of which polarity is reversed each
time the counter reaches 000016 (decrement count) or FFFF16
(increment count) is output from TAiOUT pin. If bit 2 is “0”, the TAiOUT
pin can be used as a normal port pin. However, if bit 4 is “1” and the
TAiOUT pin is used as an output pin, the output from the TAiOUT pin
changes the count direction. Therefore, bit 4 must be “0” unless the
output from the TAiOUT pin is used to select the count direction.
Data write and data read are performed in the same way as for the
timer mode. That is, when data is written to timer Ai which is halted,
it is also written to the reload register and the counter.
When data is written to timer Ai which is busy, the data is written to
the reload register, but not the counter. The counter is reloaded with
new data from the reload register at the next reload time and continues
counting. For timers A2, A3, and A4, the contents of the reload register
is not reloaded in the counter when bit 6 of the corresponding timer
Ai mode register is “1”. The contents of the counter can be read at
any time.
Addresses
7 6 5 4 3 2 1 0
0
Timer A0 mode register
5616
Timer A1 mode register
5716
Timer A2 mode register
5816
Timer A3 mode register
5916
Timer A4 mode register
5A16
0 1
0 1 : Always “01” in event counter
mode
0 : No pulse output
1 : Pulse output
0 : Count at the falling edge of input
signal
1 : Count at the rising edge of input
signal
0 : Increment or decrement according
to up-down flag
1 : Increment or decrement according
to TAiOUT pin input signal level
0 : Always “0” in event counter mode
This bit is available for times A2, A3,
and A4.
0 : Reload
1 : No reload
This bit is available for timer A3.
0 : Two-phase pulse signal processing
in the same manner as timer A2
1 : Two-phase pulse signal processing
in the same manner as timer A4
Fig. 17 Timer Ai mode register bit configuration during event counter
mode
Addresses
7 6 5 4 3 2 1 0
Up-down flag
4416
Timer A0 up-down flag
Timer A1 up-down flag
Timer A2 up-down flag
Timer A3 up-down flag
Timer A4 up-down flag
Timer A2 two-phase pulse signal processing
selection bit
0 : Two-phase pulse signal processing disabled
1 : Two-phase pulse signal processing mode
Timer A3 two-phase pulse signal processing
selection bit
0 : Two-phase pulse signal processing disabled
1 : Two-phase pulse signal processing mode
Timer A4 two-phase pulse signal processing
selection bit
0 : Two-phase pulse signal processing disabled
1 : Two-phase pulse signal processing mode
Fig. 18 Up-down flag bit configuration
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Furthermore, in the event counter mode, whether to increment or
decrement the counter can also be determined by supplying two kinds
of pulses of which phases differ by 90° to timer A2, A3, or A4. There
are two types of two-phase pulse signal processing operations. One
uses timer A2 and the other uses timer A4. Timer A3 can select one
of these two operations with bit 7 of the timer A3 mode register. In
both processing operations, two kinds of pulses of which phases differ
by 90° are input to the TAjOUT (j = 2 to 4) pin and TAjIN pin respectively.
After the level of the TA2OUT pin changes from “L” to “H” with timer
A2 used, as shown in Figure 19, the count is incremented when a
rising edge is input to the TA2IN pin and the count is decremented
when the falling edge is input.
For timer A4, as shown in Figure 20, when a phase related pulse
with a rising edge input to the TA4IN pin is input after the level of
TA4OUT pin changes from “L” to “H”, the count is incremented at the
respective rising edge and falling edge of the TA4OUT pin and TA4IN
pin. When a phase related pulse with a falling edge input to the TA4OUT
pin is input after the level of TA4IN pin changes from “H” to “L”, the
count is decremented at the respective rising edge and falling edge
of the TA4IN pin and TA4OUT pin.
When performing this two-phase pulse signal processing, bits 0 and
4 of the timer Aj mode register must be set to “1” and bits 1, 2, 3, and
5 must be set to “0” as shown in Figure 21.
Bit 7 is used to select whether to perform two-phase pulse signal
processing for timer A3 in the same manner as timer A2 or as timer
A4. When this bit is “0”, two-phase pulse signal processing for timer
A3 is performed in the same manner as timer A2 and when it is “1”, it
is performed in the same manner as timer A4. This bit is ignored for
timers A2 and A4.
Note that bits 5, 6, and 7 of the up-down flag (address 4416) are the
two-phase pulse signal processing selection bits for timers A2, A3,
and A4, respectively.
Each timer operates in the normal event counter mode when the
corresponding bit is “0” and performs two-phase pulse signal
processing when it is “1”.
Count is started by setting the count start flag to “1”. Data write and
read are performed in the same way as for the normal event counter
mode. Note that the port direction register of the input port must be
set to the input mode because two-phase pulse signal is input. Also,
there can be no pulse output in this mode.
TA2OUT
TA2IN
Increment Increment Increment Decrement Decrement Decrement
count
count
count
count
count
count
Fig. 19 Two-phase pulse signal processing operation of timer A2
TA4OUT
Increment count at each edge
Decrement count at each edge
TA4IN
Increment count at each edge
Decrement count at each edge
Fig. 20 Two-phase pulse signal processing operation of timer A4
Addresses
Timer A2 mode register
5816
7 6 5 4 3 2 1 0
Timer A3 mode register
5916
0 1 0 0 0 1
Timer A4 mode register
5A16
0 1 : Always “01” in event counter
mode
0 1 0 0 : Always “0100” when processing
two-phase pulse signal
0 : Reload
1 : No reload
This bit is avilable for timer A3
0 : Two-phase pulse signal processing
in the same manner as timer A2
1 : Two-phase pulse signal processing
in the same manner as timer A4
Fig. 21 Timer Aj mode register bit configuration when performing
two-phase pulse signal processing in event counter mode
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) One-shot pulse mode [10]
Figure 22 shows the bit configuration of the timer Ai mode resister
during the one-shot pulse mode. In the one-shot pulse mode, bit 0
and bit 5 must be “0” and bit 1 and bit 2 must be “1”.
The trigger is enabled when the count start flag is “1”. The trigger
can be generated by software, or it can be input from the TAiIN pin.
Software trigger is selected when bit 4 is “0”, and the input signal
from the TAiIN pin is used as the trigger when bit 4 is “1”.
Bit 3 is used to determine whether to trigger at the fall of the trigger
signal or at the rise. The trigger is at the fall of the trigger signal when
bit 3 is “0” and at the rise of the trigger signal when bit 3 is “1”.
Software trigger is generated by setting the bit of the one-shot start
flag corresponding to each timer.
Figure 23 shows the bit configuration of the one-shot start flag.
As shown in Figure 24, when a trigger signal is received, the counter
counts the clock selected by bits 6 and 7.
If the contents of the counter is not 000016, the TAiOUT pin goes “H”
when a trigger signal is received. The count direction is decrement.
When the counter reaches 000116, the TAiOUT pin goes “L” and count
is stopped. The contents of the reload register is transferred to the
counter. At the same time, an interrupt request signal is generated,
and the interrupt request bit of the timer Ai interrupt control register is
set. This is repeated each time a trigger signal is received. The output
pulse width is
1
pulse frequency of the selected clock
✕ (counter’s value at the time of trigger).
If the count start flag is “0”, the level of the TAiOUT pin goes “L”.
Therefore, the counter’s value corresponding to the desired pulse
width must be written to timer Ai before setting “1” to the timer Ai
count start flag.
As shown in Figure 25, a trigger signal can be received before the
operation for the previous trigger signal is completed. In this case,
the contents of the reload register is transferred to the counter by the
trigger, and then that value is decremented.
Except when retriggering while operating, the contents of the reload
register is not transferred to the counter by triggering.
When retriggering, there must be at least two timer count source
cycles before a new trigger can be issued.
22
Addresses
7 6 5 4 3 2 1 0
0
1 1 0
Timer A0 mode register
5616
Timer A1 mode register
5716
Timer A2 mode register
5816
Timer A3 mode register
5916
Timer A4 mode register
5A16
1 0 : Always “10” in one-shot
pulse mode
1 : Always “1” in one-shot pulse
mode
0 ✕ : Software trigger
1 0 : Trigger at the falling edge of
TAiIN input
1 1 : Trigger at the rising edge of
TAiIN input
0 : Always “0” in one-shot pulse
mode
Clock source selection
0 0 : Select f2
0 1 : Select f16
1 0 : Select f64
1 1 : Select f512
Fig. 22 Timer Ai mode register bit configuration during one-shot
pulse mode
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Data write is performed in the same way as for the timer mode. When
data is written in timer Ai halted, it is also written to the reload register
and the counter.
When data is written to timer Ai which is busy, the data is written to
the reload register, but not to the counter. The counter is reloaded
with new data from the reload register at the next reload time and
continues counting.
Undefined data is read when timer Ai is read.
7 6 5 4 3 2 1 0
One-shot start flag
Address
4216
Timer A0 one-shot start flag
Timer A1 one-shot start flag
Timer A2 one-shot start flag
Timer A3 one-shot start flag
Timer A4 one-shot start flag
Fig. 23 One-shot start flag bit configuration
Selected
clock source fi
TAiIN
(rising edge is
selected)
TAiOUT
In this case, the contents of the reload register is 000316.
Fig. 24 Pulse output example when external rising edge is selected
Selected
clock source fi
TAiIN
(rising edge is
selected)
TAiOUT
In this case, the contents of the reload register is 000416.
Fig. 25 Example when trigger is re-issued during pulse output
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MITSUBISHI MICROCOMPUTERS
M37733MHBXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(4) Pulse width modulation mode [11]
Figure 26 shows the bit configuration of the timer Ai mode register
during the pulse width modulation mode. In the pulse width modulation
mode, bits 0, 1, and 2 must be set to “1”.
Bit 5 is used to determine whether to perform as the 16-bit length
pulse width modulator or the 8-bit length pulse width modulator. 16bit length pulse width modulator is selected when bit 5 is “0” and 8-bit
length pulse width modulator is selected when bit 5 is “1”. The 16-bit
length pulse width modulator is described first.
The pulse width modulator can be started with a software trigger or
with an input signal from a TAiIN pin (external trigger).
The software trigger mode is selected when bit 4 is “0”. Pulse width
modulator is started and pulse is output from the TAiOUT pin when
the timer Ai start flag is set to “1”.
The external trigger mode is selected when bit 4 is “1”. Pulse width
modulator starts when a trigger signal is input from the TAiIN pin when
the timer Ai start flag is “1”. Whether to trigger at the fall or rise of the
trigger signal is determined by bit 3. The trigger is at the fall of the
trigger signal when bit 3 is “0” and at the rise when it is “1”.
When data is written to timer Ai with the pulse width modulator halted,
it is written to the reload register and the counter.
Then when the timer Ai start flag is set to “1” and a software trigger or
an external trigger is issued to start modulation, the waveform shown
in Figure 27 is output continuously. Once modulation is started,
triggers are not accepted. If the value in the reload register is m, the
duration “H” of pulse is
1
✕m
selected clock frequency
and the output pulse period is
1
✕ (2 16 – 1).
selected clock frequency
An interrupt request signal is generated and the interrupt request bit
of the timer Ai interrupt control register is set at each fall of the output
pulse.
The width of the output pulse is changed by updating timer data. The
update can be performed at any time. The output pulse width is
changed at the rise of the pulse after data is written to the timer.
The contents of the reload register is transferred to the counter just
before the rise of the next output pulse so that the pulse width is
changed from the next output pulse.
Undefined data is read when timer Ai is read.
The 8-bit length pulse width modulator is described next.
The 8-bit length pulse width modulator is selected when bit 5 of the
timer Ai mode register is “1”.
24
The reload register and the counter are both divided into 8-bit halves.
The low-order 8 bits function as a prescaler and the high-order 8 bits
function as the 8-bit length pulse width modulator. The prescaler
counts the clock selected by bits 6 and 7. A pulse is generated when
the counter reaches 000016 as shown in Figure 28. At the same time,
the contents of the reload register is transferred to the counter, and
count is continued.
Addresses
Timer A0 mode register
5616
Timer A1 mode register
5716
Timer A2 mode register
5816
7 6 5 4 3 2 1 0
Timer A3 mode register
5916
1 1 1
Timer A4 mode register
5A16
1 1 : Always “11” in pulse width
modulation mode
1 : Always “1” in pulse width
modulation mode
0 ✕ : Software trigger
1 0 : Trigger at the falling of TAiIN input
1 1 : Trigger at the rising of TAiIN input
0 : 16 bit pulse width modulator
1 : 8 bit pulse width modulator
Clock source selection bit
0 0 : Select f2
0 1 : Select f16
1 0 : Select f64
1 1 : Select f512
Fig. 26 Timer Ai mode register bit configuration during pulse width
modulation mode
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Therefore, if the low-order 8 bits of the reload register is n, the period
of the generated pulse is
1
✕ (n + 1) ✕ m.
selected clock frequency
1
✕ (n + 1).
selected clock frequency
And the output pulse period is
1
✕ (n + 1) ✕ (28 – 1).
selected clock frequency
The high-order 8 bits function as an 8-bit length pulse width modulator
using this pulse as input. Its operation is the same as for 16-bit length
pulse width modulator except it has a length of 8 bits. If the highorder 8 bits’ contents of the reload register is m, the duration “H” of
pulse is
1 / fi ✕ (216 – 1)
Selected clock
source fi
TAiIN
(rising edge is
selected)
This trigger is not accepted
1 / fi ✕ (m)
TAiOUT
In this case, the contents of the reload register is 000316.
Fig. 27 16-bit length pulse width modulator output pulse example
1 / fi ✕ (n + 1) ✕ (28 – 1)
Selected clock
source fi
TAiIN
(falling edge is
selected)
1 / fi ✕ (n + 1)
Prescaler output
(when n = 2)
1 / fi ✕ (n + 1) ✕ (m)
8-bit length pulse
width modulator
output
(when m = 2)
Fig. 28 8-bit length pulse width modulator output pulse example
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
TIMER B
Figure 29 shows a block diagram of timer B.
Timer B has three modes; timer mode, event counter mode, and
pulse period measurement/pulse width measurement mode. The
mode is selected with bits 0 and 1 of the timer Bi mode register (i = 0
to 2). Timer B2 can also be used as the clock timer of which clock
source is the main clock or the sub-clock divided by 32. Additionally,
timer B2 can be internally connected to timer B1 (cascade connection).
Each of these modes is described below.
(1) Timer mode [00]
Figure 30 shows the bit configuration of the timer Bi mode register
during the timer mode. Bits 0 and 1 of the timer Bi mode register
must always be “0” in the timer mode.
Bits 6 and 7 are used to select the clock source. The counting of the
selected clock starts when the count start flag is “1” and stops when
it is “0”.
As shown in Figure 15, the timer Bi count start flag is at the same
address as the timer Ai count start flag. The count is decremented.
When the contents of the counter becomes 000016 , an interrupt
request occurs and the interrupt request bit of the timer Bi interrupt
control register is set. At the same time, the contents of the reload
register is stored in the counter, and count is continued.
Timer Bi does not have a pulse output function or a gate function like
timer A.
When data is written to timer Bi halted, it is written to the reload register
and the counter. When data is written to timer Bi which is busy, the
data is written to the reload register, but not to the counter. The counter
is reloaded with new data from the reload register at the next reload
time and continues counting. The contents of the counter can be
read at any time.
Data bus (odd)
Clock source selection
Data bus (even)
f2
(Low-order 8 bits)
f16
f64
• Timer
• Pulse period measurement/pulse
width measurement
f512
TBi IN
(i = 0 – 2)
Polarity selection
and edge pulse
generator
Reload register (16)
Event counter
Counter (16)
fC32 (Note 1)
TB2 overflow
signal (Note 2)
Count start flag
(Address 4016)
Counter reset
circuit
Notes 1. Clock source of clock timer; Only timer B2 can select it (refer to Fig. 65)
2. Only timer B1 can select it (internal connect mode)
Fig. 29 Timer B block diagram
26
(High-order 8 bits)
Addresses
Timer B0 5116 5016
Timer B1 5316 5216
Timer B2 5516 5416
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) Event counter mode [01]
Figure 31 shows the bit configuration of the timer Bi mode register
during the event counter mode. In the event counter mode, the bit 0
of the timer Bi mode register must be “1” and bit 1 must be “0”.
The input signal from the TBiIN pin is counted when the count start
flag is “1”, and counting is stopped when it is “0”. Counting is performed
at the fall of the input signal when bits 2 and 3 are “0” and at the rise
of the input signal when bit 3 is “0” and bit 2 is “1”.
When bit 3 is “1” and bit 2 is “0”, counting is performed at the rise and
fall of the input signal.
When the sub-clock (32 kHz) oscillation circuit is used and others,
and the event counter mode is selected, timer B2 functions as the
clock timer and the original functions as timer B2 in the event counter
mode are lost. For details, refer to “(4) Clock timer”.
When the internal connect mode which connects timer B1 to timer
B2 is selected, the original function as timer B1 in the event counter
mode is lost. For details, refer to “(5) Internal connect mode”.
Data write, data read, and interrupt generation are performed in the
same way as for the timer mode.
When bit 3 is “1”, the pulse width measurement mode is selected.
The pulse width measurement mode is similar to the pulse period
measurement mode except that the clock is counted from the fall of
the TBiIN pin input signal to the next rise or from the rise of the input
signal to the next fall as shown in Figure 34.
Addresses
Timer B0 mode register
5B16
7 6 5 4 3 2 1 0
Timer B1 mode register
5C16
✕ 0 ✕ ✕ 0 0
Timer B2 mode register
5D16
0 0 : Always “00” in timer mode
✕ ✕ : Not used in timer mode and
may be any
0 : Always “0” in timer mode
(timer B0)
✕ :Not used in timer mode
(timers B1, B2)
✕ :Not used in timer mode
Clock source selection bit
0 0 : Select f2
0 1 : Select f16
1 0 : Select f64
1 1 : Select f512
(3) Pulse period measurement/pulse width
measurement mode [10]
Figure 32 shows the bit configuration of the timer Bi mode register
during the pulse period measurement/pulse width measurement
mode.
In the pulse period measurement/pulse width measurement mode,
bit 0 must be “0” and bit 1 must be “1”. Bits 6 and 7 are used to select
the clock source. The selected clock is counted when the count start
flag is “1”, and counting stops when it is “0”.
The pulse period measurement mode is selected when bit 3 is “0”. In
the pulse period measurement mode, the selected clock is counted
during the interval starting at the fall of the input signal from the TBiIN
pin to the next fall or at the rise of the input signal to the next rise.
And then, the result is stored in the reload register. In this case, the
reload register acts as a buffer register.
When bit 2 is “0”, the clock is counted from the fall of the input signal
to the next fall. When bit 2 is “1”, the clock is counted from the rise of
the input signal to the next rise.
In the case of counting from the fall of the input signal to the next fall,
counting is performed as follows. As shown in Figure 33, when the
fall of the input signal from TBiIN pin is detected, the contents of the
counter is transferred to the reload register. Next the counter is cleared
and count is started from the next clock. When the fall of the next
input signal is detected, the contents of the counter is transferred to
the reload register once more, the counter is cleared, and counting is
started. The period from the fall of the input signal to the next fall is
measured in this way.
After the contents of the counter is transferred to the reload register,
an interrupt request signal is generated and the interrupt request bit
of the timer Bi interrupt control register is set. However, no interrupt
request signal is generated when the contents of the counter is
transferred first time to the reload register after the count start flag is
set to “1”.
Fig. 30 Timer Bi mode register bit configuration during timer mode
Addresses
Timer B0 mode register
5B16
7 6 5 4 3 2 1 0
Timer B1 mode register
5C16
✕ ✕ ✕ 0
Timer B2 mode register
5D16
0 1
0 1 : Always “01” in event counter
mode
0 0 : Count at the falling edge of input
signal
0 1 : Count at the rising edge of input
signal
1 0 : Count at the both falling edge and
rising edge of input signal
0 : Always “0” in event counter mode
(timer B0)
✕ : Not used in event counter mode
(timers B1, B2)
✕ ✕ ✕ : Not used in event counter mode
Fig. 31 Timer Bi mode register bit configuration during event counter
mode
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
When timer Bi is read, the contents of the reload register is read.
Note that, in this mode, the interval from the fall of the TBiIN pin input
signal to the next rise or from the rise to the next fall must be at least
two cycles of the timer count source.
Timer Bi overflow flag which is bit 5 of the timer Bi mode register is
set to “1” when the timer Bi counter reaches 000016. This flag is cleared
by writing to the corresponding timer Bi mode register. By reading
this flag, the reason why the interrupt request signal is generated,
which is the completion of measurement or the counter overflow, can
be detected. An interrupt request signal may occur because the
counter value is particularly undefined just after counting starts.
Accordingly, make sure to detect the occurrence reason of an interrupt
request signal with the timer Bi overflow flag. This flag is “1” at reset.
When using timer B2 as the clock timer and using timer B1 in the
internal connect mode, functions in this mode are lost.
7
6 5
4 3
0
2 1
0
1
0
Addresses
Timer B0 mode register 5B16
Timer B1 mode register 5C16
Timer B2 mode register 5D16
1 0 : Always “10” in pulse period
measurement/pulse width
measurement mode
0 0 : Count from the falling edge of
input signal to the next falling one
0 1 : Count from the rising edge of
input signal to the next rising one
1 0 : Count from the falling edge of input
signal to the next rising one
and from the rising edge to the
next falling one
0 : Always “0” in pulse period
measurement/pulse width
measurement mode (timer B0)
✕ : Not used in pulse period
measurement/pulse width
measurement mode
(timers B1, B2)
Timer Bi overflow flag
Clock source selection bit
0 0 : Select f2
0 1 : Select f16
1 0 : Select f64
1 1 : Select f512
Fig. 32 Timer Bi mode register bit configuration during pulse period
measurement/pulse width measurement mode
Selected clock
source fi
TBiIN
Reload register←Counter
Counter←0
Count start flag
Interrupt request signal
Fig. 33 Pulse period measurement mode operation (example of measuring the interval from the falling edge to next falling one)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Selected
clock source fi
TBiIN
Reload register←Counter
Counter←0
Count start
flag
Interrupt
request signal
Fig. 34 Pulse width measurement mode operation
(4) Clock timer
When the port-XC selection bit of the oscillation circuit control register
0 (refer to Figure 63) is set to “1” to make the sub-clock oscillation
circuit active, timer B2 can function as the clock timer, which uses
clock fC32 as the clock source. Clock fC32 is the sub clock (32 kHz)
divided by 32.
Additionally, when the port-Xc selection bit is set to “0” not to use the
sub-clock and the timer B2 clock source selection bit of the port
function control register (refer to Figure 11) is set to “1”, timer B2 can
functions as the clock timer, which uses clock fc32 as the clock source.
Clock fc32 is the main clock divided by 32.
Figure 35 shows the timer B2 mode register bit configuration when
timer B2 is used as the clock timer. As shown in Figure 35, the event
counter mode must be selected for timer B2.
For how to use the clock timer, refer to the section on clock generating
circuit.
0 1 2 3 4 5 6 7
✕ ✕ ✕ ✕ 0 1 0 1
Address
Timer B1 mode register 5C16
Timer B2 mode register 5D16
0 1 : Always “01” in event
counter mode
0 1 : Count at the rising
edge of input signal
✕✕✕✕: Not used in event
counter mode
Fig. 35 Timer B1 mode register bit configuration when timer B1 is
used in the internal connect mode and timer B2 mode register
bit configuration when timer B2 is used as clock timer
(5) Internal connect mode
When the timer B1 internal connect selection bit of the port function
control register (refer to Figure 11) is set to “1”, timer B1 uses the
timer B2’s overflow signal as the clock source and timer B1 is internally
connected to timer B2 (cascade connection).
The internal connect mode makes timers B1 and B2 function as 16 +
16 bit-timer with the timer B2’s clock source.
Figure 35 shows the timer B1 mode register bit configuration when
using timer B1 in the internal connect mode. Set timer B1 in the event
counter mode as shown in Figure 35.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SERIAL I/O PORTS
Three independent serial I/O ports are provided.
Figure 36 shows a block diagram of the serial I/O ports.
Table 5 shows the functional differences of three serial I/O ports
(UART 0, 1, 2).
Bits 0, 1, and 2 of the UARTi (i = 0, 1, 2) transmit/receive mode
register shown in Figure 37 are used to determine whether to use
port P8 or port P7 as a parallel port, a clock synchronous serial I/O
port, or an asynchronous serial I/O port (UART) using start and stop
bits.
Data bus (odd)
Data bus (even)
Bit converter
0
0 0
0
0 0
(Note)
Receive
0 D8 D7 D6 D5 D4 D3 D2 D1 D0 buffer register
UART0 (Addresses 3716, 3616)
UART1 (Addresses 3F16, 3E16)
UART2 (Addresses 6B16, 6A16)
RxDi
Receive register
Bit rate
generator
UART0
(Address 3116)
UART1
(Address 3916)
UART2
(Address 6516)
Internal
1/(n + 1)
Divider
Clock source selection
f2
f 16
f 64
f 512
1/16 Divider
UART receive
Clock synchronous
1/16 Divider
Transmission
control circuit
Transmission clock
Clock synchronous
(Internal clock)
External
Clock synchronous
(Internal clock)
CLKi
Receive clock
UART transmission
Clock synchronous
1/2 Divider
Receive control
circuit
Clock synchronous
(External clock)
TxDi
Transmisson register
Transmission
D8 D7 D6 D5 D4 D3 D2 D1 D0 buffer register
UART0 (Addresses 3316, 3216)
UART1 (Addresses 3B16, 3A16)
UART2 (Addresses 6716, 6616)
Polarity
reversing circuit
CTSi/RTSi (Note)
(Note)
Bit converter
(Note)
Data bus (odd)
Note. UART2 does not include the bit converter, the polarity
reversing circuit and the RTSi output.
Data bus (even)
Fig. 36 Serial I/O port block diagram
7 6 5 4 3 2 1 0
Addresses
UART 0 transmit/receive mode register 3016
UART 1 transmit/receive mode register 3816
Serial I/O mode selection bits
0 0 0 : Parallel port
0 0 1 : Clock synchronous
1 0 0 : 7-bit UART
1 0 1 : 8-bit UART
1 1 0 : 9-bit UART
Internal clock/External clock selection bit
0 : Internal clock
1 : External clock
Stop bit length selection bit
0 : 1 stop bit
1 : 2 stop bits
Odd/even parity selection bit
0 : Odd parity
1 : Even parity
Parity enable bit
0 : No parity
1 : With parity
Sleep function selection bit
0 : No sleep
1 : Sleep
Fig. 37 UARTi transmit/receive mode register bit configuration
30
7 6 5 4 3 2 1 0
Address
UART 2 transmit/receive mode register 6416
Serial I/O mode selection bits
0 0 0 : Parallel port
0 0 1 : Clock synchronous
1 0 0 : 7-bit UART
1 0 1 : 8-bit UART
1 1 0 : 9-bit UART
Internal clock/External clock selection bit
0 : Internal clock
1 : External clock
Stop bit length selection bit
0 : 1 stop bit
1 : 2 stop bits
Odd/even parity selection bit
0 : Odd parity
1 : Even parity
Parity enable bit
0 : No parity
1 : With parity
Note. The switch of A-D conversion interrupt and UART2 transmit/receive
interrupt is performed by bits 0 to 2. When selecting a parallel port, A-D
conversion interrupt is valid. When selecting a clock synchronous serial
I/O port or a UART, UART2 transmit/receive interrupt is valid.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Figures 39 and 40 show the bit configuration of the UARTi transmit/
receive control register.
Each communication method is described below.
The interrupt vector and the interrupt control register are common to
the A-D conversion interrupt and UART2 transmit/receive interrupt.
It is switched by a selection of UART2 function as shown in Figure 37
and Table 5.
Figure 38 shows the connections of receiver/transmitter.
Receiver block diagram
Data bus (odd)
Data bus (even)
Bit converter
0
0
0
0
0
0
2 stop bit
RxDi
Stop
bit
0
Parity
bit
1 stop bit
D7
D6
D5
D4
D3
D2
D1
D0
Receive buffer
register
8 bit
9 bit
Synchronous
9 bit
7 bit
8 bit
9 bit
Parity
Stop
bit
D8
(Note)
Receive
register
No
Parity
7 bit
8 bit
7 bit
Synchronous
Synchronous
Transmitter block diagram
Data bus (odd)
Data bus (even)
Bit converter
D8
2 stop bit
“0”
Stop
bit
Stop
bit
D7
D6
D5
D4
D1
D0
8 bit
Transmission
buffer register
TxDi
Parity
“0”
D2
7 bit
8 bit
9 bit
9 bit
Synchro- Synchronous
nous
Parity 7 bit
8 bit
9 bit
Parity
bit
No
1 stop bit
D3
(Note)
Transmission register
7 bit
Synchronous
Note. U AR T2 does not include the bit converter.
Fig. 38 Receiver and transmitter block diagram
Table 5. Differences between UART0, UART1 and UART2
Communication
method
UART0
UART1
UART2
Selection of clock
synchronous or
asynchronous (UART)
Selection of clock
synchronous or
asynchronous (UART)
Selection of clock
synchronous or
asynchronous (UART)
CTS input/
RTS output
Interrupt
Selection of data
output, CLK polarity, Multiple clocks Sleep function
output
transfer format
Available
Available
Available
Both CTS input
and RTS output
Transmit and receive
(2 systems)
Both CTS input
and RTS output
Transmit and receive
(2 systems)
Available
Nothing
Available
Only CTS input
Transmit/receive
(1 system)
(Note)
Nothing
Nothing
Nothing
Note. The interrupt vector and the interrupt control register are common to the A-D conversion interrupt and UART2 transmit/receive interrupt.
It is switched by a selection of UART2 function.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
7
6
TFM CPL
5
4
3
2
Tx
R/C
EPTY
TxS
1
0
Addresses
UART0 transmit/receive control register 0 3416
UART1 transmit/receive control register 0 3C16
CS1 CS0
BRG count source selection bits
00 : Select f2
01 : Select f16
10 : Select f64
11 : Select f512
CTS/RTS selection bit
0 : Select CTS
1 : Select RTS
Transmission register empty bit
CTS, RTS enable bit
0 : Enble CTS and RTS
1 : Disable CTS and RTS (I/O port)
Data output selection bit
0 : CMOS output
1 : N-channel open-drain output
CLK polarity selection bit
0 : In transferring, transmit data is output at
the CLKi's falling edge or received data is
input at the CLKi's rising edge.
Not in transferring, CLKi level is "H".
1 : In transferring, transmit data is output at the
CLKi's rising edge or received data is input
at the CLKi's falling edge.
Not in transferring, CLKi level is "L".
Transfer format selection bit
0 : LSB first
1 : MSB first
7
6
5
4
SUM PER FER OER
3
2
1
0
RI
RE
TI
TE
Addresses
UART0 transmit/receive control register 1 3516
UART1 transmit/receive control register 1 3D16
Transmit enable flag
Transmit buffer empty flag
Receive enable bit
Receive completing flag
Overrun error flag
Framing error flag
Parity error flag
Error sum flag
Fig. 39 UART0, UART1 transmit/receive control registers bit configuration
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
7
6
5
4
3
2
Tx
R/C
EPTY
1
0
CS1 CS0
Addresses
UART2 transmit/receive control register 0 6816
BRG count source selection bits
00 : Select f2
01 : Select f16
10 : Select f64
11 : Select f512
CTS enable bit
0 : Enable CTS
1 : Disable CTS (I/O port)
Transmission register empty bit
7
6
5
4
SUM PER FER OER
3
2
1
0
RI
RE
TI
TE
Addresses
UART2 transmit/receive control register 1 6916
Transmit enable flag
Transmit buffer empty flag
Receive enable bit
Receive completing flag
Overrun error flag
Framing error flag
Parity error flag
Error sum flag
Fig. 40 UART2 transmit/receive control register bit configuration
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CLOCK SYNCHRONOUS SERIAL
COMMUNICATION
A case where communication is performed between two clock
synchronous serial I/O ports as shown in Figure 41 will be described.
(The transmission side will be denoted by subscript j and the receiving
side will be denoted by subscript k.)
Bit 0 of the UARTj transmit/receive mode register and UARTk transmit/
receive mode register must be set to “1”, and bits 1 and 2 must be
“0”. The length of the transmission data is 8 bits.
Bit 3 of the UARTj transmit/receive mode register of the clock sending
side is cleared to “0” to select the internal clock. Bit 3 of the UARTk
transmit/receive mode register of the clock receiving side is set to “1”
to select the external clock. Bits 4, 5 and 6 are ignored in the clock
synchronous mode. Bit 7 must always be “0”.
The clock source is selected by bit 0 (CS0) and bit 1 (CS1) of the
clock sending side UARTj transmit/receive control register 0. If the
contents of the bit rate genarator is n, as shown in Figure 36, the
selected clock is divided by (n + 1), then by 2, passed through a
transmission control circuit, and output as transmission clock CLKj.
Therefore, when the selected clock is fi,
The bit 2 of the clock sending side UARTj transmit/receive control
register 0 is cleared to “0” to select CTSj input. The bit 2 of the clock
receiving side is set to “1” to select RTSk output.
Whether to use the CTS and RTS signals is determined by bit 4 of the
UART transmit/receive control register 0. Set bit 4 to “0” when CTS
and RTS signals are used, and to “1” when they are not used.
UART2 has the CTS input function, but that does not have the RTS
output function (refer to Figure 40.)
When CTS and RTS signals are not used, the CTS/ RTS pin can be
used as a normal port. The following describes the case when the
CTS and RTS signals are used. If CTS and RTS signals are not used,
the CTSj input condition is unnecessary and there is no RTSk output.
Output driver format of the transmit data output pin (TXDj), which is
the CMOS output or the N-channel open-drain output, is selected
with bit 5 (TXS) of the UARTj transmit/receive control register 0. When
bit 5 is “0”, the CMOS output format is selected. When bit 5 is “1”, the
N-channel open-drain output format is selected. When the N-channel
open-drain output format is selected, make sure to pull-up the data
line using a pull-up resistor.
Bit Rate = fi / {(n + 1) ✕ 2}
On the clock receiving side, the CS0 and CS1 bits are ignored because
an external clock is selected.
TxDj
TxDk
UARTj transmission register
UARTk transmission register
UARTj transmission buffer register
UARTk transmission buffer register
UARTj receive buffer register
UARTk receive buffer register
RxDj
UARTj receive register
RxDk
UARTj transmit/receive mode register
0
✕
✕
✕
0
0
0
UARTk transmit/receive mode register
1
0
CLKj
TFM CPL TxS
0
0
TFM CPL TxS
CTSj
SUM PER FER OER RI
RE
TI
TE
✕
✕
1
0
0
1
UARTk transmit/receive control register 0
CS1 CS0
UARTj transmit/receive control register 1
✕
CLKk
UARTj transmit/receive control register 0
Tx
EPTY
UARTk receive register
0
Tx
EPTY
1
✕
✕
RTSk
UARTk transmit/receive control register 1
SUM PER FER OER RI
RE
TI
TE
Note. UART2 does not include RTS output. The UART2 transmit/receive control register 0’s bit configuration is partialy different.
Fig. 41 Clock synchronous serial communication
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Transmission
The internal/external clock polarity is selected with bit 6 (CPL) of the
UARTj transmit/receive control register 0. When bit 6 is “0”, transmit
data is output at the CLKj’s falling edge in transmitting, received data
is input at the CLKk’s rising edge in receiving, and the CLKi level is
“H” not in transferring (transmitting/receiving). When bit 6 is “1”,
reversely, transmit data is output at the CLK j’s rising edge in
transmitting, received data is input at the CLKk’s falling edge in
receiving, and the CLKi level is “L” not in transferring. Bit transfer
order of transmit/received data, which is LSB first or MSB first (Note),
is selected with bit 7 (TFM) of the UARTj transmit/receive control
register 0. LSB first is selected when bit 7 is “0”, and MSB first is
selected when bit 7 is “1”. However, UART2’s function is fixed to the
function specified by TxS=CPL=TFM=“0”, and it cannot be changed.
Note that, only in the UART0 transmission mode, the transmission
clock can be output not only from the CLK0 pin but also from the
other output pins (CLKS0, CLKS1). Transmission clock output multipleselection mode is set with the serial transmit control register and
others. For details, refer to the section on transmission.
Note. When LSB first is selected, data is transmitted/received
beginning at the least significant bit (LSB). When MSB first is
selected, data is transmitted/received beginning at the most
significant bit (MSB).
Transmission is started when the bit 0 (TEj flag) of the UARTj transmit/
receive control register 1 is “1”, bit 1 (TIj flag) of one is “0”, and the
CTSj input is “L”.
Transmit data is output each time when the transmission clock (CLKj)
level changes from “H” to “L” with bit 6 (CPL) of the UARTj transmit/
receive control register 0 “0” or is output each time when the CLKj
level changes from “L” to “H” with CPL “1”. For details, refer to Figure
42. In addition, transmit data is output beginning at the least significant
bit (LSB) with bit 7 (TFM) of the UARTj transmit/receive control register
“0” or is output beginning at the most significant bit (MSB) with TFM
“1”.
The TIj flag indicates whether the transmission buffer register is empty
or not. It is cleared to “0” when date is written in the transmission
buffer register and set to “1” when the contents of the transmission
buffer register is transferred to the transmission register.
1 / fi ✕ ( n + 1 ) ✕ 2
Transmission
clock
TEj
TIj
Write in transmission buffer register
Transmission register
Transmission buffer register
CTSj
1 / fi ✕ ( n + 1 ) ✕ 2
CLKj
Stopped because TEj = “0”
(CPL =
“0” )
(CPL =
“1” )
TENDj
TXDj
(TFM =
“0” )
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
(TFM =
“1” )
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
TXEPTYj
Fig. 42 Clock synchronous serial I/O timing
35
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
When the transmission register becomes empty after its contents
has been transmitted, data is automatically transferred from the
transmission buffer register to the transmission register if the next
transmission start condition is satisfied. If bit 2 of the UARTj transmit/
receive control register 0 is “1”, CTSj input is ignored and transmission
start is controlled only by the TEj flag and TIj flag. Once transmission
has started, the TEj flag, TIj flag, and CTSj signals are ignored until
data transmission completes. Therefore, transmission is not interrupt
even when CTSj input is changed to “H” during transmission.
As shown in Figure 42, CTSj and flags TEj and TIj, which indicate the
transmission start condition, are checked while the TENDj signal is
“H”. Therefore, data can be transmitted continuously if the next
transmission data is written in the transmission buffer register and
the TIj flag is cleared to “0” before the TENDj signal level becomes H”.
The bit 3 (TXEPTYj flag) of the UARTj transmit/receive control register
0 changes to “1” at the next cycle after the TENDj signal level becomes
“H”. Furthermore, the TxEPTYj flag changes to “0” when transmission
starts. Therefore, this flag can be used to determine whether data
transmission has been completed.
When the TIj flag changes from “0” to “1”, the interrupt request bit in
the UARTj transmission (transmit/receive in UART2) interrupt control
register is set to “1”.
Since UART0 has three output pins (CLK0, CLKS0, and CLKS1) for
the transmission clock, the user can select one from these pins when
using the internal clock. Accordingly, data can be transmitted to three
external receive devices which will not receive data at the same time.
Figure 43 shows the extrnal connection diagram example.
To select the transmission clock output multiple-selection mode, it is
necessary to set bits 5 and 4 of the serial transmit control register. In
addition, it is necessary to select the internal clock, to disable CTS
and RTS, and disable reception, with the UART0 transmit/receive
mode register and the UART0 transmit/receive control register 0/1.
Figure 44 shows the bit configuration of the serial transmit control
register and Figure 45 shows the bit configuration of the UART0
transmit/receive mode register and the UART0 transmit/receive
control register 0/1 in the transmission clock output multiple-selection
mode. Furthermore, Table 6 shows the function of bits 5 and 4
(Transmission clock output pin selection bits, TC1 and TC 0) of the
serial transmit control register. As shown in Table 5, the transmission
clock is output from the CLK0, CLKS0, or CLKS1 pin depending on
TC1, TC0. Do not change the value of TC1 and TC0 during transferring.
The transmission clock polarity also depends on bit 6 (CPL) of the
UART0 transmit/receive control register 0.
7
6
5
4
3
2
1
0
Serial transmit
control register
TC1 TC0
0 0 : Normal mode
(Clock is output only from CLK0)
0 1 : Multiple clocks are specified
(Clock is output from CLK0)
1 0 : Multiple clocks are specified
(Clock is output from CLKS0)
1 1 : Multiple clocks are specified
(Clock is output from CLKS1)
Fig. 44 Bit configuration of serial transmit control register
Table 6. Relationship between transmission clock output pin selection
bits and pin functions
Transmission clock
P81
P82
P80
output pin selection bits
RXD0
CTS0 /RTS0
CLK0
CLKS0
CLKS1
TC 1
TC0
0
0
CLK0
RXD0
P8/CTS0/RTS0
0
1
CLK0 “H” (Note2)
P80
1
0
“H”
CLKS0
P80
1
1
“H”
“H” (Note2)
CLKS1
Notes 1. In this table, the CLK polarity selection bit (CPL) is “0”.
When CPL is “1”, “H” in this table becomes “L”. The polarity
of CLK0, CLKS0, or CLKS 1 also depends on CPL.
2. When bit 2 of the port P8 direction register is “1”, “H” is
output. When this bit is “0”, floating is entered.
CLKS1
CLKS0
CLK0
DIN
CLK
DIN
CLK
DIN
CLK
Note. Clock synchronous serial I/O communication and internal clock are used.
This connection is applied only in transmission mode.
Fig. 43 External connection diagram example in the transmission clock output multiple-selection mode
36
6E16
Transmission clock output pin selection bits
TXD0
UART 0
Adress
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
7
0
6
5
4
✕ ✕ ✕
3
0
2
0
1
0
0
1 UART0 transmit/receive
mode register
Address
3016
001 : Clock synchronous
0
: Internal clock
✕✕✕ : Not used
0
7
TPM
6
5
CPL TxS
4
3
2
✕
1
1
: always “0”
0
CS1 CS2
UART0 transmit/receive
control register 0
Address
3416
Clock source selection bits
0 0 : Select f2
0 1 : Select f16
1 0 : Select f64
1 1 : Select f512
Receive
Receive starts when the bit 2 (REk flag) of the UARTk transmit/receive
control register 1 is set to “1”.
The RTSk output level is “H” when the REk flag is “0”, but it is “L” when
the REk flag is “1” and the TIk flag is “0”. Furthermore, the RTSk output
level is “H” again when receiving restarts. The TIk flag is cleared to
“0” by writing dummy data into the transmission buffer register. When
the RTSk output level is “L”, receiving for the receive register is enabled.
UART2 does not have the RTS output function.
When bit 6 (CPL) of the UARTk transmit/receive control register 0 is
“0”, the contents of the receive register is shifted by 1 bit each time
when the receive clock (CLKk) changes from “L” to “H”. When CPL is
“1”, the contents is shifted by 1 bit each time when CLKk changes
from “H” to “L”. These shifts are performed simultaneously with the
data reception from the RXDk pin. When an 8-bit data is received, the
contents of the receive register is transferred to the receive buffer
register and the bit 3 (RIk flag) of the UARTk transmit/receive control
register 1 is set to “1”. In other words, the setting of the RIk flag to “1”
indicates that the receive buffer register contains the received data.
When the TIk flag goes “0”, RTSk output level goes “L” to indicate that
the next data can be received. When the RIk flag changes from “0” to
“1”, the interrupt request bit of the UARTk receive (transmit/receive in
UART2) interrupt control register is set to “1”. Bit 4 (OERk flag) of the
UARTk transmit/receive control register is set to “1” when the next
data is transferred from the receive register to the receive buffer
register while RIk flag is “1”, and the OERk flag indicates that the next
data was transferred to the receive buffer register before the contents
of the receive buffer register was read.
The RIk flag is cleared to “0” when reading the low-order byte to the
receive buffer, when writing “0” to the REk flag, or when setting to be
a parallel port. The OERk flag is cleared to “0” when writing “0” to the
REk flag or when setting to be a parallel port. The FERk, PERk, and
SUMk flags are ineffective in the clock synchronous communication.
The received data in the receive buffer register is read into the data
bus according to the LSB first (beginning at the least significant bit)
when bit 7 (TEM) of the UARTk transmit/receive control register 0 is
“0” or according to the MSB first (beginning at the most significant
bit) when bit 7 is “1”.
As shown in Figure 36, with clock synchronous serial communication,
data cannot be received unless the transmitter is operating because
the receive clock is created from the transmission clock. Therefore,
the transmitter must be operating even when there is no data to be
sent from UARTk to UARTj.
AAAAAA
✕ : Not used
1 : Disable CTS and RTS
(I/O port)
Data output selection bit
0 : CMOS output
1 : N-channel open-drain output
CLK polarity selection bit
0 : In transmitting, transmit data
is output at the CLK's falling
edge. Not in transmitting,
CLK0 level is “H”.
1 : In transmitting, transmit data
is output at the CLK0's rising
edge. Not in transmitting,
CLK0 level is “L”.
Transfer format selection bit
0 : LSB first
1 : MSB first
7
6
5
4
3
2
0
1 0
UART0 transmit/receive
TE
control register 1
Address
3516
Trasmit enable flag
0 : Receiving is disabled
Fig. 45 Bit configuration of UART0 transmit/receive mode register
and UART0 transmit/receive control register 0/1 in the
transmission clock output multiple-selection mode
37
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
ASYNCHRONOUS SERIAL COMMUNICATION
(UART)
If the selected clock is an internal clock fi or an external clock fEXT,
Bit Rate = (fi or fEXT) / {(n + 1) ✕ 16}
Asynchronous serial communication can be performed using 7-, 8-,
or 9-bit length data. The operation is the same for all data lengths.
The following is the description for 8-bit asynchronous communication.
With 8-bit asynchronous communication, the bits 2 to 0 of the UARTi
transmit/receive mode register must be “101”.
Bit 3 is used to select an internal clock or an external clock. If bit 3 is
“0”, an internal clock is selected and if bit 3 is “1”, then external clock
is selected. If an internal clock is selected, the bit 0 (CS0) and bit 1
(CS1) of UART i transmit/receive control register 0 are used to select
the clock source. When an internal clock is selected for asynchronous
serial communication, the CLKi pin can be used as a normal port.
If the content of the bit rate generator is n, the selected internal or
external clock is divided by (n + 1), then by 16, and passed through a
control circuit to create the UART transmission clock or the UART
receive clock.
Bit 4 selects 1 stop bit or 2 stop bits.
The bit 5 is a selection bit of odd parity or even parity.
In the odd parity mode, the parity bit is adjusted so that the sum of
the 1’s in the data and parity bit is always odd.
In the even parity mode, the parity bit is adjusted so that the sum of
the 1’s in the data and parity bit is always even.
(1 / f1 , or 1 / fEXT) ✕ (n + 1) ✕ 16
Transmission clock
TEi
TI i
CTSi
TEN D i
TXD i
Transmission register ← Transmission
buffer register
Write in transmission buffer register
Parity bit Stop bit
Start bit
ST D0 D1 D2 D3
D4 D5
D6 D7
Stopped because TEi = “0”
P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1
TXEPTYi
Fig. 46 Transmit timing example when 8-bit asynchronous communication with parity and 1 stop bit is selected
(1 / f1 , or 1 / fEXT) ✕ (n + 1) ✕ 16
Transmission clock
TEi
TIi
Write in transmission buffer register
Transmission register ← Transmission
buffer register
TEN D i
Start bit
TXDi
Stop Bit Stop Bit
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP
TXEPTYi
Fig. 47 Transmit timing example when 9-bit asynchronous communication with no parity and 2 stop bits is selected
38
Stopped because
TEi = “0”
ST D0 D1 D2
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bit 6 is the parity enable bit which indicates whether to add parity bit
or not.
Bits 4 to 6 should be set or reset according to the data format of the
communicating devices.
Bit 7 is the sleep selection bit (refer to the next page).
Bit 2 of the UARTi transmit/receive control register 0 is used to
determine whether to use CTSi input or RTSi output. CTSi input is used
if bit 2 is “0” and RTSi output is used if bit 2 is “1”.
If CTSi input is selected, the user can control whether to stop or start
transmission with external CTSi input.
Whether to use CTS and RTS signals is determined by bit 4 of the
UART transmit/receive control register 0. Set bit 4 to “0” when CTS
and RTS signals are used, and to “1” when they are not used.
UART2 has the CTS input function, but that does not have the RTS
output function (refer to Figure 40.)
When CTS and RTS signals are not used, the CTS/ RTS pin can be
used as a normal port. The following describes the case when the
CTS and RTS signals are used. If CTS and RTS signals are not used,
the CTSi input condition is unnecessary and there is no RTSi output.
In addition, output driver format of the transmission data output pin
(TXDj), which is CMOS output or N-channel open-drain output, is
selected with bit 5 (TXS) of the UARTj transmit/receive control register
0. CMOS output format is selected when bit 5 is “0”, and N-channel
open-drain output format is selected when bit 5 is “1”. When N-channel
open-drain output format is selected, make sure to pull-up the data
line using a pull-up resistor.
However, UART2 does not have bit 5 (TxS) and the format is always
CMOS output.
In asynchronous serial communication, bits 6 and 7 of the UARTj
transmit/receive control register 0 must be “0”.
Transmission
Transmission is started when the bit 0 (TEi flag) of UARTi transmit/
receive control register 1 is “1”, the bit 1 (TIi flag) is “0”, and CTSi input
is “L” if CTSi input is selected. As shown in Figures 46 and 47, data is
output from the TXDi pin with the start bit and the stop bit or parity bit
specified by the bits 4 to 6 of UARTi transmit/receive mode register.
The data is output beginning at the least significant bit.
The TIi flag indicates whether the transmission butter is empty or not.
It is cleared to “0” when data is written in the transmission buffer and
set to “1” when the contents of the transmission buffer register is
transferred to the transmission register.
When the transmission register becomes empty after the contents
has been transmitted, data is transferred automatically from the
transmission buffer register to the transmission register if the next
transmission start condition is satisfied.
Once transmission has started, the TEi flag, TIi flag, and CTSi signal
(if CTSi input is selected) are ignored until data transmission is
completed.
Therefore, transmission does not stop until it completes even if the
TEi flag is cleared during transmission.
As shown in Figure 46, CTSi input and flags TEi and TIi, which indicate
the transmission start condition, are checked while the TENDi signal
is “H”. Therefore, data can be transmitted continuously if the next
transmission data is written in the transmission buffer register and TIi
flag is cleared to 0 before the TENDi signal goes “H”.
The bit 3 (TXEPTYi flag) of the UART i transmit/receive control register
0 changes to “1” at the next cycle after the TENDi signal goes “H” and
changes to “0” when transmission starts. Therefore, this flag can be
used to determine whether data transmission is completed.
When the TIi flag changes from “0” to “1”, the interrupt request bit of
the UARTi transmission (transmit/receive in UART2) interrupt control
register is set to “1”.
39
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Receive
Receive is enabled when bit 2 (REi flag) of the UARTi transmit/receive
control register 1 is set to “1”. As shown in Figure 48, the frequency
divider circuit at the receiving end begin to work when a start bit is
arrived and the data is received.
If RTSi output is selected by setting bit 2 of the UARTi transmit/receive
control register 0 to “1”, the RTSi output is “H” when the REi flag is “0”.
When the REi flag changes to “1”, the RTSi output goes “L” to indicate
receive ready and returns to “H” once receive has started. In other
words, RTSi output can be used to determine externally whether the
receive register is ready to receive. (UART2 does not have the RTS
output function.)
The entire transmission data bits are received when the start bit
passes the final bit of the receive register of the receive block shown
in Figure 38. At this point, the contents of the receive register is
transferred to the receive buffer register and the bit 3 of the UARTi
transmit/receive control register 1 (RIi flag) is set. In other words, the
RIi flag indicates that the receive buffer register contains data when it
is set. If RTSi output is selected, RTSi output goes “L” to indicate that
the register is ready to receive the next data.
The interrupt request bit of the UARTi receive (transmit/receive in
UART2) interrupt control register is set when the RIi flag changes
from “0” to “1”.
The bit 4 (OERi flag) of the UARTi transmission control register 1 is
set when the next data is transferred from the receive register to the
receive buffer register while the RIi flag is “1”. In other words when
an overrun error occurs. If the OERi flag is “1”, it indicates that the
next data has been transferred to the receive buffer register before
the contents of the receive butter register has been read.
Bit 5 (FERi flag) is set when the number of stop bits is less than
required (framing error).
Bit 6 (PERi flag) is set when a parity error occurs.
Bit 7 (SUMi flag) is set when either the OERi flag, FER i flag, or the
PERi flag is set. Therefore, the SUMi flag can be used to determine
whether there is an error.
The setting of the RIi flag, OERi flag, FER i flag, and the PERi flag is
performed while transferring the contents of the receive register to
the receive buffer register. The RIi, FERi, and PERi flags are cleared
when reading the low-order byte of the receive buffer register or when
writing “0” to the REi flag or when setting to be a parallel port. The
OERi and SUM i flags are cleared when writing “0” to the REi flag or
when the setting to be a parallel port.
Sleep mode
The sleep mode is used to communicate only between certain
microcomputers when multiple microcomputers are connected
through serial I/O.
The sleep mode is entered when bit 7 of the UARTi transmit/receive
mode register is set.
UART2 does not have the sleep mode.
The operation of the sleep mode for an 8-bit asynchronous
communication is described below.
When sleep mode is selected, the contents of the receive register is
not transferred to the receive buffer register if bit 7 (bit 6 if 7-bit
asynchronous communication and bit 8 if 9-bit asychronous
communication) of the received data is “0”. Also the RIi, OERi, FER i,
PERi, and the SUM i flag are unchanged. Therefore, the interrupt
request bit of the UARTi receive interrupt control register is also
unchanged.
Normal receive operation takes place when bit 7 of the received data
is “1”.
The following is an example of how the sleep mode can be used.
The main microcomputer first sends data with bit 7 set to “1” and bits
0 to 6 set to the address of the subordinate microcomputer which
wants to communicate with. Then all subordinate microcomputers
receive the same data. Each subordinate microcomputer checks the
received data, clears the sleep function selection bit if bits 0 to 6 are
its own address and sets the sleep bit if not. Next the main
microcomputer sends data with bit 7 cleared. Then the microcomputer
with the sleep bit cleared will receive the data, but the microcomputer
with the sleep bit set will not. In this way, the main microcomputer is
able to communicate only with the designated microcomputer.
fi or fEXT
REi
RxDi
Stop bit
Start bit
D0
Check to be “L” level
Receive
Clock
D1
D7
Get data
Starting at the falling
edge of start bit
RIi
RTSi
Fig. 48 Receive timing example when 8-bit asynchronous communication with no parity and 1 stop bit is selected
40
Start bit
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D CONVERTER
The A-D converter is an 10-bit successive approximation converter.
Figure 49 shows a block diagram of the A-D converter and Figure 50
shows the configuration of the A-D control register 0 (address 1E16)
and A-D control register 1 (address 1F16).
The frequency of the A-D converter operating clock φ AD is selected
by bit 7 of the A-D control register 0. When bit 7 is “0”, φ AD is the
clock frequency divided by 4. That is, φ AD = f2/4. When bit 7 is “1”,
φ AD is the clock frequency divided by 2 and φ AD = f2/2.
The φ AD during A-D conversion must be 250 kHz or more because
the comparator uses a capacity coupling amplifier.
Bit 3 of A-D control register 1 is used to select whether to use the
conversion result as 10 bits or as 8 bits. The conversion result is
used as 10 bits when bit 3 is “1” and as 8 bits when bit 3 is “0”.
When the conversion result is used as 10 bits, the low-order 8 bits of
the conversion result is stored in the even address of the
corresponding A-D register and the high-order two bits are stored in
bits 0 and 1 of the odd address of the corresponding A-D register.
Bits 2 to 7 of the A-D register odd address return “0000002” when
read.
When the conversion result is used as 8 bits, the high-order 8 bits of
the 10-bit A-D conversion are stored in even address of the
corresponding A-D register. In this case, the A-D register odd address
returns “0016” when read.
The operating mode is selected by bits 3 and 4 of A-D control register
0. The available operating modes are one-shot, repeat, single sweep,
repeat sweep.
Whether to connect the reference voltage input pin (VREF) with the
ladder network or not depends on bit 5 of the A-D control register 1.
The VREF pin is connected when bit 5 is “0” and is disconnected
when bit 5 is “1” (High impedance state). When A-D conversion is
not performed, current from the VREF pin to the ladder network can
be cut off by disconnecting ladder network from the VREF pin.
Before starting A-D conversion, wait for 1 µs or more after clearing
bit 5 to “0”.
The bit of the port direction register corresponding to the analog input
pin to be used must be “0” (input mode) because the analog input pin
is also used as port P7.
Note that when using the sub-clock (XCIN - XCOUT) or UART2, the
analog pins shared with those functions cannot be used.
The operation of each mode is described below.
The interrupt vector and the interrupt control register are common to
the A-D conversion interrupt and UART2 transmit/receive interrupt.
It is switched by a selection of UART2 function as shown in Figure
37’s note.
φ AD selection
f2
VREF connect selection
φ AD
1/2
1/2
VREF
Vref
Ladder network
AVSS
Successive approximation register
A-D control register 1 (1F16)
A-D control register 0 (1E16)
Address
Address
A-D register 0 (2116) A-D register 0 (2016)
A-D register 1 (2316) A-D register 1 (2216)
A-D register 2 (2516) A-D register 2 (2416)
A-D register 3 (2716) A-D register 3 (2616)
Decoder
A-D register 4 (2916) A-D register 4 (2816)
Comparator
A-D register 5 (2B16) A-D register 5 (2A16)
A-D register 6 (2D16) A-D register 6 (2C16)
A-D register 7 (2F16) A-D register 7 (2E16)
Data bus (odd)
Data bus (even)
AN0
AN1
AN2
AN3
AN4
AN5/ADTRG
AN6
AN7
Selector
Fig. 49 A-D converter block diagram
41
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) One-shot mode
One-shot mode is selected when bits 3 and 4 of A-D control register
0 are “0”. The analog input pin (AN0 – AN7) is selected with bits 0 to
2 of A-D control register 0. A-D conversion can be started by a software
trigger or by an external trigger.
A software trigger is selected when bit 5 of A-D control register 0 is
“0” and an external trigger is selected when it is “1”. When a software
trigger is selected, A-D conversion is started when bit 6 (A-D
conversion start flag) is set to “1”. A-D conversion ends after 59 φ AD
cycles and an interrupt request bit of the A-D conversion interrupt
control register is set to “1”. At the same time, the A-D conversion
start flag (bit 6 of the A-D control register 0) is cleared and A-D
conversion stops. The result of A-D conversion is stored in the A-D
register corresponding to the selected pin.
If an external trigger is selected, A-D conversion starts when the A-D
conversion start flag is “1” and the ADTRG input changes from “H” to
“L”. In this case, the pins that can be used for A-D conversion are
AN0 to AN4, AN6 and AN7 (a total of 7) because the ADTRG pin is also
used as the analog voltage input pin (AN5). The operation is the same
as with software trigger except that the A-D conversion start flag is
not cleared after A-D conversion and a retrigger can be available
during A-D conversion.
7
6
5
4
3
2
1
0
Address
A-D control register 0
(2) Repeat mode
Repeat mode is selected when bit 3 of A-D control register 0 is “1”
and bit 4 is “0”. The operation of this mode is the same as the operation
of one-shot mode except that when A-D conversion of the selected
pin is complete and the result is stored in the A-D register, conversion
does not stop, but is repeated.
No interrupt request is issued in this mode. Furthermore, if software
trigger is selected, the A-D conversion start flag is not cleared.
The contents of the A-D register can be read at any time.
7
6
5
1E16
0
3
2
1
0
Address
A-D control register 1
1F16
Analog input selection bits
0 0 0 : Select AN 0
0 0 1 : Select AN 1
0 1 0 : Select AN 2
0 1 1 : Select AN 3
1 0 0 : Select AN 4
1 0 1 : Select AN 5
1 1 0 : Select AN 6
1 1 1 : Select AN 7
A-D sweep pin selection bits
0 0 : AN 0, AN1 (2 pins)
0 1 : AN 0 – AN3 (4 pins)
1 0 : AN 0 – AN5 (6 pins)
1 1 : AN 0 – AN7 (8 pins)
A-D operation mode selection bits
0 0 : One-shot mode
0 1 : Repeat mode
1 0 : Single sweep mode
1 1 : Repeat sweep mode
0 : Always “0”
Trigger selection bit
0 : Software trigger
1 : ADTRG input trigger
A-D conversion start flag
0 : Stop A-D conversion
1 : Start A-D conversion
A-D conversion frequency ( φ AD) selection flag
0 : Select f 2/4
1 : Select f 2/2
Fig. 50 A-D control register bit configuration
42
4
8/10-bit mode selection bit
0 : 8-bit mode
1 : 10-bit mode
VREF connection selection bit
0 : V REF is connected
1 : V REF is not connected
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MITSUBISHI MICROCOMPUTERS
M37733MHBXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) Single sweep mode
Single sweep mode is selected when bit 3 of A-D control register 0 is
“0” and bit 4 is “1”.
In the single sweep mode, the number of analog input pins to be
swept can be selected. Analog input pins are selected by bits 1 and
0 of the A-D control register 1 (address 1F16). Two pins, four pins, six
pins or eight pins can be selected as analog input pins, depending
on the contents of these bits.
A-D conversion is performed only for selected input pins. After A-D
conversion is performed for input of AN0 pin, the conversion result is
stored in A-D register 0, and in the same way, A-D conversion is
performed for selected pins one after another. After A-D conversion
is performed for all selected pins, the sweep is stopped.
A-D conversion can be started with a software trigger or with an
external trigger input. A software trigger is selected when bit 5 is “0”
and an external trigger is selected when it is “1”.
When a software trigger is selected, A-D conversion is started when
A-D control register 0 bit 6 (A-D conversion start flag) is set to “1”.
When A-D conversion of all selected pins ends, an interrupt request
bit of the A-D conversion interrupt control register is set to “1”. At the
same time, A-D conversion start flag is cleared and A-D conversion
stops.
If an external trigger is selected, A-D conversion starts when the A-D
conversion start flag is “1” and the ADTRG input changes from “H” to
“L”. In this case, the A-D conversion result which is stored in the A-D
register 5 becomes invalid because the ADTRG pin is also used as the
AN5 pin.
The operation by external trigger is the same as that done by software
trigger except that the A-D conversion start flag is not cleared after
A-D conversion and a retrigger can be available during A-D
conversion.
(4) Repeat sweep mode
Repeat sweep mode 0 is selected when bit 3 of A-D control register
0 is “1” and bit 4 is “1”.
The difference from the single sweep mode is that A-D conversion
does not stop after converting from the AN0 pin to the selected pins,
but repeats again from the AN0 pin. The repeat is performed among
the selected pins. Also, no interrupt request is generated. Furthermore,
if software trigger is selected, the A-D conversion start flag is not
cleared. The A-D register can be read at any time.
43
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
WATCHDOG TIMER
The watchdog timer is used to detect unexpected execution sequence
caused by software runaway.
Figure 51 shows a block diagram of the watchdog timer. The watchdog
timer includes a 12-bit binary counter.
The watchdog timer counts divided clock f32 or f512. Whether to count
f32 or f512 is determined by the watchdog timer frequency selection
flag shown in Figure 52. For divided clocks f32 and f512, refer to the
section on clock generating circuit. f512 is selected when the flag is
“0” and f32 is selected when it is “1”. The flag is cleared after reset.
“FFF16” is set in the watchdog timer when “L” or 2 Vcc is applied to
the RESET pin, STP instruction is executed, data is written to the
watchdog timer register, or the most significant bit of the watchdog
timer becomes “0”.
After “FFF16” is set in the watchdog timer, the contents of the watchdog
timer is decremented by one at every cycle of f32 or f512. After 2048
counts, the most significant bit of the watchdog timer becomes “0”,
and a watchdog timer interrupt request bit is set, and “FFF16” is set in
the watchdog timer.
Normally, a program is written so that data is written in the watchdog
timer register before the most significant bit of the watchdog timer
becomes “0”. If this routine is not executed due to unexpected program
runaway, the most significant bit of the watchdog timer becomes
eventually “0” and an interrupt is generated.
The processor can be reset by setting “1” to the software reset bit (bit
3 of the processor mode register 0) described in Figure 10 on the
interrupt section and generating a reset pulse.
The watchdog timer stops its function when the RESET pin voltage is
raised to double the Vcc voltage.
The watchdog timer can also be used to recover from when the clock
is stopped by the STP instruction. Refer to the section on stand-by
function for more details.
The watchdog timer hold the contents during a hold state and the
input of the divided clock is stopped.
Select with the watchdog timer frequency selection flag.
(If STP instruction is executed, f32 is forced to be selected when
the system clock selection bit is “0”, or f8 is forced to be selected
when the system clock selection bit is “1”.)
f32
f512
Watchog timer
Hold
(Address 6016)
Write to watchdog
timer register
RESET
2 • Vcc
detection
circuit
STP instruction
S
Set “FFF16”
Q
R
(Note)
Note. When the main clock external input selection bit is “1”
and the main clock or the main clock divided by 8 is
selected as a system clock, or the sub-clock external
input selection bit is “1” and the sub-clock is selected;
the divided clock f16 is input.
Fig. 51 Watchdog timer block diagram
7
6
5
4
3
2
1
0
Addresses
Watchdog timer
frequency
selection flag
0 : Select f512
1 : Select f32
Fig. 52 Watchdog timer frequency selection flag
44
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
RESET CIRCUIT
The microcomputer is released from the reset state when the RESET
pin is returned to “H” level after holding it at “L” level with the power
source voltage at 5 V ± 10%. Program execution starts at the address
formed by setting address A23 – A16 to 0016, A15 – A8 to the contents
of address FFFF16, and A7 – A0 to the contents of address FFFE16.
Figure 53 shows the status of the internal registers during reset.
Address
Address
Port P0 direction register
(0416)•••
0016
Watchdog timer frequency selection flag
(6116)•••
Port P1 direction register
(0516)•••
0016
Memory allocation control
1
(6316)••• 0 0 0 0 0 0 0 0
Port P2 direction register
(0816)•••
0016
UART2 transmit/receive mode register
(6416)•••
0 0 0 0 0 0 0
Port P3 direction register
(0916)•••
UART2 transmit/receive control register 0
(6816)•••
1 0 0 0
Port P4 direction register
(0C16)•••
0016
UART2 transmit/receive control register 1
(6916)••• 0 0 0 0 0 0 1 0
Port P5 direction register
(0D16)•••
0016
Oscillation circuit control register 0
(6C16)••• 0 0 0 0 0 0 0 1
Port P6 direction register
(1016)•••
0016
Port function control register
(6D16)••• 0
Port P7 direction register
(1116)•••
0016
Serial transmit control register
(6E16)•••
Port P8 direction register
(1416)•••
0016
A-D control register 0
(1E16)••• 0 0 0 0 0 ? ? ?
A-D control register 1
(1F16)•••
0 0 0
UART 0 Transmit/Receive mode register (3016)•••
0016
UART 0 receive interrupt control register
UART 1 Transmit/Receive mode register (3816)•••
0016
0 0 0 0
1 1
0
0016
0 0
0
0 0 0 0 0
Oscillation circuit control register 1
(6F16)•••
A-D/UART2 trans./rece. interrupt control register
(7016)•••
0 0 0 0
UART 0 transmission interrupt control register (7116)•••
0 0 0 0
(7216)•••
0 0 0 0
UART 1 transmission interrupt control register (7316)•••
0 0 0 0
(3416)••• 0 0 0 0 1 0 0 0
UART 1 receive interrupt control register
(7416)•••
0 0 0 0
(3C16)••• 0 0 0 0 1 0 0 0
Timer A0 interrupt control register
(7516)•••
0 0 0 0
0 0 0 0 0 0 1 0
Timer A1 interrupt control register
(7616)•••
0 0 0 0
(3D16)••• 0 0 0 0 0 0 1 0
Timer A2 interrupt control register
(7716)•••
0 0 0 0
(4016)•••
0016
Timer A3 interrupt control register
(7816)•••
0 0 0 0
One- shot start flag
(4216)•••
0 0 0 0 0
Timer A4 interrupt control register
(7916)•••
0 0 0 0
Up-down flag
(4416)•••
0016
Timer B0 interrupt control register
(7A16)•••
0 0 0 0
Timer A0 mode register
(5616)•••
0016
Timer B1 interrupt control register
(7B16)•••
0 0 0 0
Timer A1 mode register
(5716)•••
0016
Timer B2 interrupt control register
(7C16)•••
0 0 0 0
Timer A2 mode register
(5816)•••
0016
INT0 interrupt control register
(7D16)•••
0 0 0 0 0 0
Timer A3 mode register
(5916)•••
0016
INT1 interrupt control register
(7E16)•••
0 0 0 0 0 0
Timer A4 mode register
(5A16)•••
0016
INT2/Key input interrupt control register
(7F16)•••
0 0 0 0 0 0
Timer B0 mode register
(5B16)••• 0 0 1 0 0 0 0 0
Processor status register (PS)
Timer B1 mode register
(5C16)••• 0 0 1
0 0 0 0
Program bank register (PG)
Timer B2 mode register
(5D16)••• 0 0 1
0 0 0 0
Program counter (PCH)
Content of FFFF16
Processor mode register 0
(5E16)•••
Program counter (PCL)
Content of FFFE16
Processor mode register 1
(5F16)•••
UART 0 transmit/receive
control register 0
UART 1 transmit/receive
control register 0
UART 0 transmit/receive
control register 1
UART 1 transmit/receive
control register 1
Count start flag
Watchdog timer register
(3516)•••
(6016)•••
0016
0
FFF16
Direct page register (DPR)
Data bank register (DT)
0 0 0 ? ? 0 0 0 1 ? ?
0016
000016
0016
Contents of other registers and RAM are undefined during reset. Initialize them by software.
Fig. 53 Microcomputer internal status during reset
45
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Figure 54 shows an example of a reset circuit. If the stabilized clock
is input from the external to the main-clock oscillation circuit, the reset
input voltage must be 0.9 V or less when the power source voltage
reaches 4.5 V. If a resonator/oscillator is connected to the main-clock
oscillation circuit, change the reset input voltage from “L” to “H” after
the main-clock oscillation is fully stabilized.
Power on
4.5V
VCC
RESET
VCC
0V
RESET
0V
0.9V
Note. In this case, stabilized clock is input from the
external to the main-clock oscillation circuit.
Perform careful evaluation at the system design
level before using.
Fig. 54 Example of a reset circuit
46
INPUT / OUTPUT PINS
Ports P0 to P8 all have a port direction register and each bit can be
programmed for input or output. A pin becomes an output pin when
the corresponding bit of the port direction register is set to “1” and an
input pin when the bit is cleared to “0”.
When a pin is programmed for output, the data is written to the port
latch and is output, and the contents of the port latch is read instead
of the value of the pin. Therefore, a previously output value can be
read correctly even when the output “L” voltage is raised by directly
driving an LED or others.
A pin programmed for input is floating and the value input to the pin
can be read. When a pin is programmed for input, the data is written
only in the port latch and the pin retains floating.
Ports P54 to P57, and P62 – P64, however, have pull-up transistors
and the port’s pull-up function can be selected by setting “1” to bits 6,
5, 3 of the port function control register (reffer to Figure 11.) A port
which corresponds to a port direction register’s bit set to “0” is pulled
up. A port which corresponds to a bit set to “1” is an output pin and it
is not pulled up.
Figures 55 and 56 show the block diagram of ports P0 to P8 and the
E pin output format.
In the memory expansion mode and the microprocessor mode, ports
P0 to P4 are also used as address, data, and control signal pins.
Refer to the section on the processor modes for more details.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
• Ports P00 – P07, P10 – P17, P20 – P27, P30 – P33, P43 – P46 (Inside dotted-line not included)
Ports P40, P41, P47, P51, P53, P61, P65 – P67, P86 (Inside dotted-line included)
Port direction register
Data bus
Port latch
• Ports P83, P87 (Inside dotted-line not included. Shaded area included.)
Ports P50, P52, P60, P75, P82 (Inside dotted-line included. Shaded area not included.)
Port P42 (Inside dotted-line not included.
Shaded area not included.)
N-channel open-drain
selection (Note 1)
Port direction register
“1”
Output
Data bus
Port latch
AA
A
Analog input
AAA
AAA
AAA
Notes 1. Valid only when pins are used as
TxDj pins for serial I/O communication
2. Only P75 as analog input
(Note 2)
• Ports P54, P56
Pull-up selection
Port direction register
“1”
Output
Data bus
Port latch
AA
A
Pull-up
transistor
• Ports P55, P57, P62 – P64
Pull-up selection
Port direction register
Pull-up
transistor
Data bus
Port latch
Fig. 55 Block diagram for ports P0 to P8 and the E pin output format (1)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
• Ports P70, P71, P76, P77 (Inside dotted-line not included.)
Ports P72, P74 (Inside dotted-line included.)
Port direction register
Data bus
Port latch
Sub-clock oscillation circuit
(Note 1)
Analog input
Note 1. Only P76, P77 as sub-clock oscillation circuit
• Ports P55, P73, P80, P81, P84
Port direction register
“1”
“0”
Output
Data bus
Port latch
Analog input
(Note 2)
Note 2. Only P73 as analog input
•E
Fig. 56 Block diagram for ports P0 to P8 and the E pin output format (2)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PROCESSOR MODE
• BYTE pin
Bits 0 and 1 of processor mode register 0 shown in Figure 57 are
used to select any mode of the single-chip mode, the memory
expansion mode, the microprocessor mode and the evaluation mode.
Ports P0 to P3 and a part of port P4 are used as I/O pins of address,
data, and control signals except for in the single-chip mode.
Figure 58 shows the functions of ports P0 to P4 in each mode.
The external memory area changes when the mode changes.
Figure 59 shows the memory map for each mode. Refer to Figure 1
for the addresses of RAM and ROM. The external memory area can
be accessed except in the single-chip mode. The accessing of the
external memory is affected by the BYTE pin, the wait bit (bit 2 of the
processor mode register 0), and the wait selection bit (bit 0 of the
processor mode register 1). These will be described next.
When accessing the external memory, the level of the BYTE pin is
used to determine whether to use the data bus as 8-bit width or 16bit width.
The data bus has a width of 8 bits when level of the BYTE pin is “H”,
and port P2 becomes the data I/O pin.
The data bus has a width of 16 bits when the level of the BYTE pin is
“L”, and ports P1 and P2 become the data I/O pins.
When accessing the internal memory, the data bus always has a
width of 16 bits regardless of the BYTE pin level.
7 6 5 4 3 2 1 0
0
Address
Processor mode register 0 5E16
Processor mode bit
0 0 : Single-chip mode
0 1 : Memory expansion mode
1 0 : Microprocessor mode
1 1 : Evaluation mode
7 6 5 4 3 2 1 0
Processor mode register 1
Address
5F16
Wait selection bit
0 : Wait 0
1 : Wait 1
Wait bit
0 : Wait
1 : No Wait
Software reset bit
Reset occurs when this bit is set to “1”
Interrupt priority detection time selection bit
0 0 : Internal clock φ ✕ 7 (cycle)
0 1 : Internal clock φ ✕ 4 (cycle)
1 0 : Internal clock φ ✕ 2 (cycle)
Test mode bit
This bit must be "0"
Clock φ 1 output selection bit
0 : No φ 1 output
1 : φ 1 output
Fig. 57 Processor mode register bit configuration
49
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PM1
0
0
1
1
PM0
0
1
0
1
Single-chip Mode
Memory Expantion Mode
Microprocessor
Mode
Evaluation Chip Mode
Same as left
Same as left
Same as left
Same as left
Mode
Port
E
Port P0
(Note)
P07
E
(Note)
P07
E
~
~
I/O Port
P00
Address A7~A0
P00
E
BYTE =“L”
P17
A15~A8
~
Address
Port P1
P10
P17
~
I/O Port
P10
Data(odd)
E
E
P17
P17
Same as left
P10
BYTE =“H”
~
~
Address A15~A8
P10
A15~A8
Address Data(odd)
Ports P4, P5 and their direction
registers are treated as 16-bit wide
bus.
E
E
BYTE =“L”
P27
~
Data
(even)
Address
P20
P27
Same as left
Same as left
I/O Port
~
Port P2
A23~A16
P20
E
E
P27
Address
P20
E
P27
Data
(even, odd)
Same as left
A23~A16
Address
Data
(even, odd)
Ports P4, P5 and their direction
registers are treated as 16-bit wide
bus.
~
~
BYTE =“H”
A23~A16
P20
E
P33
HLDA
P33
I/O Port
~
Port P3
P30
E
ALE
P32
P31
BHE
P30
R/W
Same as left
E
P47
P40
E
I/O Port
P42
In this case, bit 7 of the processor
mode register 0 is “0”
Port P4
P41
RDY
P40
HOLD
In this case, bit 7 of the processor
mode register 0 is “0”
P42
φ1
P42
DBC
P47
P47
~
~
I/O Port
Same as left
φ1
Same as above except P42
Same as above except P42
In this case, bit 7 of the processor
mode register 0 is “1”
In this case, bit 7 of the processor
mode register 0 is “1”
Same as left
except for port
P42 which outputs φ 1 independent of bit
7 of the processor mode
register 0 (Note)
P46
VPA
P45
VDA
P44
QCL
P43
MX
P42
φ1
P41
RDY
P40
HOLD
Fig. 58 Relationship between ports P0 to P4 and processor modes
Note.
50
The signal output disable selection bit (bit 6 of the oscillation circuit control register 0) can stop the E signal output in the single-chip
mode and the φ 1 output in the microprocessor mode. In the memory expansion mode or the microprocessor mode, signal E can also
be fixed to “H” when the internal memory area is accessed.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
• Wait bit
As shown in Figure 60, when the external memory area is accessed
with the wait bit (bit 2 of the processor mode register 0 at address
5E16) cleared to “0”, the access time can be extended compared with
no wait (the wait bit is “1”).
The access time is extended in two ways and this is selected with the
wait selection bit (bit 0 of the processor mode register 1 at address
5F16).
When this bit is “1”, the access time is 1.5 times compared to that for
no wait. When this bit is “0”, the access time is twice compared to
that for no wait.
At reset, the wait bit and the wait selection bit are “0”.
The accessing of internal memory area is always performed in the
no wait mode regardless of the wait bit.
The processor modes are described below.
Internal clock
Port P2
Wait bit “1”
(No wait)
Microprocessor
mode
0016
SFR
SFR
Evaluation
chip mode
216
A16
C16
Data Address Data
E
ALE
Access time
Port P2
Wait bit “0”
(Wait 1)
Address
Data
Address
Data
E
ALE
Access time
Port P2
Memory expansion
mode
Address
Wait bit “0”
(Wait 0)
Address
Data
Address
E
ALE
Access time
SFR
Fig. 60 Relationship between wait bit, wait selection bit, and access time
8016
RAM
RAM
RAM
FFF16
100016
ROM
1FFFF16
FFFFFF16
The shaded area is the external memory area.
Fig. 59 External memory area for each processor mode
51
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MITSUBISHI MICROCOMPUTERS
M37733MHBXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) Single-chip mode [00]
HOLD is a hold request signal. It is an input signal used to put the
Single-chip mode is entered by connecting the CNVss pin to Vss and
starting from reset. Ports P0 to P4 all function as normal I/O ports.
Port P42 can output clock φ 1 by setting bit 7 of the processor mode
register 0 to “1”. For clock φ 1, refer to Figure 65.
In this mode, signal E is output from pin E. Signal E output, however,
can be stopped by setting the signal output disable selection bit (bit 6
of the oscillation circuit control register 0) to “1”, and it is possible to
switch the E pin function to “L” output. Table 7 shows the function of
the signal output disable selection bit.
microcomputer in hold state. HOLD input is accepted when the internal
clock φ falls from “H” level to “L” level while the bus is not used. Ports
P0, P1, P2, P30 and P31 are floating while the microcomputer stays
in hold state. These ports become floating after one cycle of internal
clock φ later than HLDA signal changes to “L” level. At releasing hold
state, these ports are released from floating state after one cycle of
internal clock φ later than HLDA signal changes to “H” level.
RDY is a ready signal. When this signal goes “L”, the internal clock φ
stops at “L”. RDY is used when a slow external memory is attached.
Port P42 becomes a normal I/O port when bit 7 of the processor
mode register 0 is “0” and becomes an output pin for clock φ 1 when
bit 7 is “1”. The φ 1 output is independent of RDY and does not stop
even when internal clock φ stops because of “L” input to the RDY pin.
(2) Memory expansion mode [01]
Memory expansion mode is entered by setting the processor mode
bits to “01” after connecting the CNVss pin to Vss and starting from
reset.
Pin E becomes the output pin for signal E.
E is an enable signal and is “L” during the data/instruction code read
or data write term. When the internal memory area is read or written,
E can be fixed to “H” by setting the signal output disabe selection bit
(bit 6 of the oscillation circuit control register 0) to “1”.
Port P0 becomes an address output pin and loses its I/O port function.
Port P1 has two functions depending on the level of the BYTE pin. In
both cases, the I/O port function is lost.
When the BYTE pin level is “L”, port P1 functions as an address
output pin while E is “H” and as an odd address data I/O pin while E
is “L”. However, if an internal memory is read, external data is ignored
while E is “L”.
When the BYTE pin level “H”, port P1 functions as an address output
pin.
Port P2 has two functions depending on the level of the BYTE pin. In
both cases, the I/O port function is lost.
When the BYTE pin level is “L”, port P2 functions as an address
output pin while E is “H” and as an even address data I/O pin while E
is “L”. However, if an internal memory is read, external data is ignored
while E is “L”.
When the BYTE pin level is “H”, port P2 functions as an address
output pin while E is “H” and as an even and odd address data I/O pin
while E is “L”. However, if an internal memory is read, external data is
ignored while E is “L”.
Ports P30, P31, P32, and P33 become R/W, BHE, ALE, and HLDA
output pin respectively and lose their I/O port functions.
R/W is a read/write signal which indicates a read when it is “H” and a
write when it is “L”.
BHE is a byte high enable signal which indicates that an odd address
is accessed when it is “L”.
Therefore, two bytes at even and odd addresses are accessed
simultaneously when address A0 is “L” and BHE is “L”.
ALE is an address latch enable signal used to latch the address signal
from a multiplexed signal of address and data. The latch is transparent
while ALE is “H” to let the address signal pass through and held
while ALE is “L”.
HLDA is a hold acknowledge signal and is used to notify externally
when the microcomputer receives HOLD input and enters hold state.
Ports P40 and P41 become HOLD and RDY input pin, respectively,
and lose their output pin function.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) Microprocessor mode [10]
Microprocessor mode is entered by connecting the CNVss pin to Vcc
and starting from reset. It can also be entered by programming the
processor mode bits to “10” after connecting the CNVss pin to Vss
and starting from reset. This mode is similar to the memory expansion
mode except that internal ROM is disabled and an external memory
is required, and clock φ 1 from port P42 is always output independently
of bit 7 of the processor mode register 0.
As shown in Table 7, φ 1 output can also be stopped with the signal
output disable selection bit “1”. In this case, write “1” to the port P42
direction register.
(4) Evaluation chip mode [11]
Evaluation chip mode is entered by applying voltage twice the VCC
voltage to the CNVSS pin. This mode is normally used for evaluation
tools.
The functions of E, ports P0 and P3 are the same as those in memory
expansion mode.
Port P1 functions as an address output pin while E is “H” and as data
I/O pin of odd addresses while E is “L” regardless of the BYTE pin
level.
Port P2 function as an address output pin while E is “H” and as data
I/O pin of even addresses while E is “L” when the BYTE pin level is
“L”.
When the BYTE pin level is “H” or 2·VCC , port P2 functions as an
address output pin while E is “H” and as data I/O pin of even and odd
addresses while E is “L”.
Port P4 and its data direction register which are located at address
0A16 and 0C16 are treated differently in evaluation chip mode. When
these addresses are accessed, the data bus width is treated as 16
bits regardless of the BYTE pin level, and the access cycle is treated
as internal memory regardless of the wait bit.
When a voltage twice the VCC voltage is applied to the BYTE pin, the
addresses corresponding to the internal ROM area are also treated
as 16-bit data bus.
The functions of ports P40 and P4 1 are the same as in memory
expansion mode.
Ports P42 to P46 become φ 1, MX, QCL, VDA, and VPA output pins
respectively. Port P47 becomes the DBC input pin.
φ 1 from port P42 is always output regardless of bit 7 of processor
mode register 0.
The MX signal normally contains the contents of flag m, however,
the contents of flag x is output when the CPU is using flag x.
QCL is the queue buffer clear signal. It becomes “H” when the
instruction queue buffer is cleared, for example, when a jump
instruction is executed.
VDA is the valid data address signal. It becomes “H” while the CPU
is reading data from data buffer or writing data to data buffer. It also
becomes “H” when the first byte of the instruction (operation code) is
read from the instruction queue buffer.
VPA is the valid program address signal. It becomes “H” while the
CPU is reading an instruction code from the instruction queue buffer.
DBC is the debug control signal and is used for debugging.
Table 8 shows the relationship between the CNVss pin input level
and the processor modes.
Table 8. Relationship between CNVss pin input levels and processor
modes
CNVss
Mode
Description
Single-chip mode upon
• Single-chip
• Memory expansion starting after reset. Each
mode can be selected by
Vss
• Microprocessor
(• Evaluation chip) changing the processor
mode bits by software.
Microprocessor mode upon
• Microprocessor
Vcc
(• Evaluation chip) starting after reset.
Evaluation chip mode only.
2·Vcc
• Evaluation chip
Table 7. Function of signal output disable selection bit CM6 (bit 6 of oscillation circuit control register 0)
Processor mode
Pin
Function
CM6 = “1”
“L” is output.
E is output only when the external
memory area is accessed.
“L” is output after WIT/STP instruction is
Memory expansion mode,
executed.
After WIT/STP instruction is executed,
Microprocessor mode
∗ Standby state selection bit (bit 0 of port
E
“H” is output.
function control register) must be set to
“1”.
“H”or “L” is output. (Output the content of
P42 latch.)
Clock
φ
1 is output independent of φ 1
Microprocessor mode
φ1
output selection bit.
∗ Port P42 direction register must be set to
“1”.
Note. Functions shown in Table 7 cannot be emulated in a debugger. For the oscillation circuit control register 0, refer to Figure 63.
For the port function control register, refer to Figure 11.
Single-chip mode
E
E
CM6 = “0”
Enable signal E is output.
E is output when the internal/external
memory area is accessed.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
OSCILLATION CIRCUIT
In the oscillation circuit, two kinds of clock circuits are built-in. One is
the main-clock oscillation circuit which uses the XIN and XOUT pins,
and the other is the sub-clock (32 kHz) oscillation circuit which uses
the XCIN and the XCOUT pins.
Either of these two oscillation circuits can output the system clock,
and it can be selected.
Figure 61 shows the oscillation circuit example with a ceramic
resonator or a quartz-crystal oscillator connected. The circuit
constants such as capacitance depend on a resonator/oscillator, and
these constants shall be set to the resonator/oscillator manufacture’s
recommended value.
Figure 62 shows the example of the external clock input circuit.
When inputting the main clock externally, the main-clock oscillation
circuit stops operating and power dissipation could be conserved by
setting the main clock external input selection bit (bit 1 of the oscillation
circuit control register 1, refer to Figure 63) to “1”. Note that this bit
also has the function to select a return factor from STP state (refer to
the section on the STANDBY FUNCTION.) Additionally, write to the
oscillation circuit control register 1 as the flow shown in Figure 64.
Pins XCIN and XCOUT of the sub-clock oscillation circuit are also used
as I/O ports P77 and P76, and these functions are selected with the
port-XC selection bit described below.
From the time during reset to the time after releasing reset, only the
main-clock oscillation circuit operates and the main clock is selected
as the system clock. Furthermore, at this time, the sub-clock oscillation
circuit stops and pins XCIN and X COUT become I/O ports (P77, P76).
When the port-XC selection bit (bit 4 of the oscillation circuit control
register 0) is set to “1” in this condition, I/O ports P77 and P76 are
switched to pins XCIN and XCOUT, and then, oscillation starts in the
sub-clock oscillation circuit.
XIN
XOUT
XCOUT
Rd
COUT
(32 kHz)
CCIN
External oscillation circuit
Vcc
Vss
P76
(P76 as I/O port)
External oscillation circuit
• When inputting the main clock externally, set the main clock
external input selection bit to “1”. Then, leave the XOUT pin
open.
• When inputting the sub clock externally, set the sub-clock
external input selection bit to “1”. Then, port P76 becomes an
I/O port.
Fig. 62 External clock input circuit
When inputting the sub clock externally, set the sub-clock external
input selection bit (bit 2 of the oscillation circuit control register 1) to
“1” before selecting pins XCIN and XCOUT with the port-Xc selection
bit. When the sub-clock external input selection bit is set to “1”, port
P76 becomes an I/O port (or an analog input AN6). Note that this bit
also has the function to select a return factor from STP state (refer to
the section on the STANDBY FUNCTION.)
When the sub-clock output selection bit (bit 1 of the port function
control register, refer to Figure 11) is set to “1” under the condition of
the port-Xc selection bit = “1”, the sub-clock φ SUB is output from port
P67. Accordingly, the sub-clock 32 kHz can be supplied for external
devices.
XIN
XOUT
Rcd
CCOUT
XCIN
Vcc
Vss
Rf
In this case, sub-clock oscillation circuit is used.
(Port-Xc selection bit is “1”)
P77
P76
(P77, P76 as I/O port)
Rd
CIN
COUT
In this case, sub-clock oscillation circuit is not used.
( Port-Xc selection bit is “0”)
Fig. 61 Oscillation circuit example with external resonator or quartz-crystal oscillator
54
XOUT
Left open
Rcf
Rf
CIN
XCIN
XIN
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CLOCK GENERATING CIRCUIT
Figures 63 and 65 show the bit configuration of the oscillation circuit
control registers 0, 1 and the clock generating circuit diagram. The
clock generating circuit consists of main- and sub-clock oscillation
circuits, system clock switch circuit, clock dividing circuit, standby
control circuit, and others. The oscillation circuit control registers are
some of the control registers for the clock generating circuit.
Clocks φ , f2 to f512 , fC32, and φ 1 are used in CPU and internal
peripheral devices or are output from pins, and they are made of the
main or sub clock, as shown in Figure 65.
The system clock and the clock f2 can be switched to high-speed
clocks or low-speed clocks shown in Table 9. When using the sub
clock, it is possible to select one of 3 types: the main clock divided by
2, the direct main clock (not divided) and the sub clock divided by 2
as the clock f2.
When not using the sub clock, it is possible to select one of 4 types:
the main clock divided by 2, divided by 8, divided by 16 and the direct
main clock (not divided) as the clock f2.
This function of clocks switch make it possible to adapt power control
to the system operation.
Bits 0 to 4 of the oscillation circuit control register 0 and bit 0 of the
oscillation circuit control register 1 control sub-clock oscillation start,
system clock selection, stop/restart of main-clock oscillation, subclock drivability selection and the main clock division selection.
The method of clocks switch is described bellow.
When selecting the main clock as the system clock, the main clock
division selection bit (bit 0 of the oscillation circuit control register 1)
selects either the main clock divided by 2 or the direct main clock as
the clock f2. When this bit is “1”, the clock f2 is the direct main clock
which is not divided, so that a half external input frequency is enough
to perform the same operation speed. Consequently, power
dissipation could be conserved (refer to Figure 69.) The main clock
division selection bit is valid regardless of either using the sub clock
or not.
Figure 66 shows the system clock state transition when using the
sub clock.
From the time during reset to the time reset is released, only the
main clock, which is selected as the system clock, oscillates.
If the port-XC selection bit is set to “1” in this term, the sub-clock
oscillation circuit starts oscillation. When the sub clock is not used,
fix the port-XC selection bit to “0” (“0” at reset) and use the P77/AN7
XCIN and P76/AN6/XCOUT pins as I/O ports P77 and P76 or analog
inputs AN7 and AN6, respectively.
Table 9. Selection of system clock and clock f2
Sub clock
Not used
Used
Port-Xc
selection bit
(CM4)
System clock
selection bit
(CM3)
Main clock
division selection
bit (CC0)
System clock
Clock f2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Main clock
Main clock
Main clock divided by 8
Main clock divided by 8
Main clock
Main clock
Sub clock
Sub clock
Main clock divided by 2
Main clock
Main clock divided by 16
Main clock divided by 8
Main clock divided by 2
Main clock
Sub clock divided by 2
Sub clock divided by 2
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
7
6
5
4
3
2
1
CM6 CM5 CM4 CM3 CM2
0
CM0
Oscillation circuit control register 0
Address
6C16
XCOUT drivability selection bit
0 : LOW
1 : HIGH
Main clock stop bit
0 : Main-clock oscillation is available.
1 : Main-clock oscillation is stopped.
System clock selection bit
• Port-XC selection bit = “0” (Sub clock is not used.)
0 : Main clock is selected.
1 : Main clock divided by 8 is selected.
• Port-XC selection bit = “1” (Sub clock is used.)
0 : Main clock is selected.
1 : Sub clock is selected.
Port-Xc selection bit
0 : Ports P77 and P76 are selected. (Sub clock is not used.)
1 : Pins XCIN and XCOUT are selected. (Sub clock is used.)
System clock stop bit at wait state
0 : Clocks f2 to f512 are operating at WIT state
1 : Clocks f2 to f512 stop at WIT state
Signal output disable selection bit (Refer to Table 7.)
7
6
5
4
0
3
2
1
0
CC2 CC1 CC0
Oscillation circuit control register 1
Main clock division selection bit
0 : Main clock is divided by 2.
1 : Main clock is not divided by 2.
Address
6F16
Note. Write to the oscillation circuit control
register 1 as the flow shown in Figure 64.
Main clock external input selection bit
0 : Main-clock oscillation circuit is operating by itself.
Watchdog timer is used at returning from STP state.
1 : Main-clock is input externally.
Watchdog timer is not used at returning from STP state.
Sub clock external input selection bit
0 : Sub-clock oscillation circuit is operating by itself.
Port P76 functions as XCOUT pin.
Watchdog timer is used at returning from STP state.
1 : Sub-clock is input externally.
Port P76 functions as I/O port.
Watchdog timer is not used ar returning from STP state.
X : Not used
0 : Always “0” (However, writing data “5516” shown in Figure 64 is possible.)
Clock prescaler reset bit
Fig. 63 Bit configuration of oscillation circuit control registers 0, 1
Writing data “5516” (LDM instruction)
Next instruction
Writing data “8016” (LDM instruction)
Reset clock prescaler
• How to reset clock prescaler
Writing data “0Y16” (LDM instruction)
CC2 to CC0 selection bits
• How to write in CC2 to CC0 selection bits
Note. “Y” is the sum of bits to be set. For example, when
setting bits 2 and 1 to “1”, “Y” becomes “6”.
Fig. 64 How to write data in oscillation circuit control register 1
56
CM4
CC2
XIN
1
0
Sub clock
0
1
Q
CC1
CM4
P77/XCIN
R
S
CM2
CM3
0
1
1/32
CM4
1
0
CM5
0
1
fC32
CM3
Clock
prescaler
0
STP instruction
Main clock
1/8
0
1
PC1
CM4
(Port latch)
1
P67/TB2IN/ φ SUB
WIT instruction
CM3
CM4
CC0
System clock
1/2
0
1
R
S
Timer B2
(clock timer)
(In event counter mode)
CM4
PC1
Q
f2
P42/ φ 1
Q
1/2
R
S
f16
f32
0
WDC
f64
1/2
Reset
0
1
0
f512
1
12-bit
Watchdog
timer
1/8
Watchdog timer frequency
selection flag
1/2
1
Interrupt disable flag
Interrupt request
STP
instruction
Internal clock
φ
1/4
f8
CM3
CC2
CC1
CM3
CM4
P
IN
XOUT
P76/XCOUT
(Oscillation circuit control register 0 : Address 6C16)
CM2 : Main clock stop bit
CM3 : System clock selection bit
CM4 : Port-Xc selection bit
CM5 : System clock stop bit at wait state
(Oscillation circuit control register 1:Address 6F16)
CC0 : Main clock division selection bit
CC1 : Main clock external input selection bit
CC2 : Sub clock external input selection bit
(Port function control register : Address 6D16)
PC1 : Sub-clock output selection bit/Timer B2 clock
source selection bit
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Fig. 65 Block diagram of clock generating circuit
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
Main clock : Oscillating
Sub clock : Stopped
I/O ports P7 7 and P7 6
f2 : Main-clock side
(Note 2)
φ : Stopped
WIT instruction
Interrupt
Main clock : Oscillating
Sub clock : Stopped
I/O ports P7 7 and P7 6
f2 : Main-clock side
φ : Main-clock side
STP instruction
Interrupt
Main clock : Stopped
Sub clock : Stopped
I/O ports P7 7 and P7 6
f2 : Stopped
φ : Stopped
XC is selected
(CM4 = “1”)
Main clock : Oscillating
Sub clock : Oscillating
f2 : Main-clock side
(Note 2)
φ : Stopped
WIT instruction
Interrupt
Main clock : Oscillating
Sub clock : Oscillating
f2 : Main-clock side
φ : Main-clock side
Main clock is selected as
system clock (Note 1)
(CM3 = “0”)
WIT instruction
Main clock : Oscillating
Sub clock : Oscillating
f2 : Sub-clock side (Note 2)
Interrupt
φ : Stopped
WIT instruction
Main clock :Stopped
Sub clock :Oscillating
f2 : Sub-clock side (Note 2)
φ : Stopped
Interrupt
Interrupt
Main clock : Stopped
Sub clock : Stopped
f2 : Stopped
φ : Stopped
Sub clock is selected as
system clock (Note 1)
(CM3 = “1”)
Main clock : Oscillating
Sub clock : Oscillating
f2 : Sub-clock side
φ : Sub-clock side
Main clock
oscillation starts
(CM2 = “0”)
STP intrunction
STP intrunction
Interrupt
Main clock : Stopped
Sub clock : Stopped
f2 : Stopped
φ : Stopped
Main clock
oscillation stops
(CM2 = “1”)
Main clock : Stopped
Sub clock : Oscillating
f2 : Sub-clock side
φ : Sub-clock side
STP instruction
Interrupt
Main clock : Stopped
Sub clock : Stopped
f2 : Stopped
φ : Stopped
Notes 1. Before selecting the main/sub clock of which oscillation already starts as the system clock, use software
to fully stabilize the oscillation.
2. When the system clock stop bit at wait state (CM 5) is “1”, f 2 stops at wait state.
Fig. 66 System clock state transition
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Note that the port-XC selection bit cannot be cleared by software
when it is once set to “1”. The bit can be cleared only by reset. It is
impossible to write “1” to the port-XC selection bit and the system
clock selection bit at the same time. In addition, the contents of the
main clock stop bit and the XCOUT drivability selection bit cannot be
changed when the port-XC selection bit is “0”.
Figure 67 shows the system clock selection change example when
using the sub clock. When the system clock selection bit is “1” after
sub-clock oscillation starts, the sub clock is selected as the system
clock. Make sure to select the sub clock after the sub-clock oscillation
is fully stabilized.
When the main clock stop bit is set to “1” after the sub clock is selected,
the main-clock oscillation/input stops. By stopping the main-clock
oscillation, current consumption can be further restricted.
When the main clock stop bit is cleared to “0” after the main-clock
oscillation stops, the main-clock oscillation/input restarts.
When the system clock selection bit is “0” after the main-clock
oscillation restarts, the main clock is selected as the system clock
again. Make sure to select the main clock after the main-clock
oscillation restarts and is fully stabilized.
The X COUT drivability selection bit is a bit to select the drivability of
the sub-clock oscillation circuit and is set to “1” (HIGH) after reset is
released. Make sure to clear the XCOUT drivability selection bit to “0”
(LOW) after the sub-clock oscillation is fully stabilized.
Port-Xc selection bit (CM4)
System colck selection bit (CM3)
Main clock stop bit (CM2)
Main clock
Sub clock
Main clock
System clock
Oscillation stabilizing time
Stopped
Main-clock oscillation
Operating
Operating
Oscillation stabilizing time
Sub-clock oscillation
Stop
Operating
Fig. 67 System clock selection change example
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
When the port-XC selection bit is set to “1” to use sub-clock oscillation
and timer B2 is set to be in the event count mode, clock fC32 which is
the sub clock (32 kHz) divided by 32 is selected as the count source
of timer B2. By this selection, timer B2 can be used as the clock
timer. For setting of timer B2 related registers, refer to the section on
clock timer mode of timer B2.
The clock prescaler in which the sub clock is divided by 32 is reset by
writing “1”, in dummy, into bit 7 (clock prescaler reset bit) of the
oscillation circuit control register 1.
When the main clock is selected, by this function, clock fC32 of clock
timer B2 can be synchronized with software. Figure 68 shows the
operation timing for clock prescaler and clock timer B2.
Figure 69 shows the clock f2 state transition when the port-Xc selection
bit is “0” and the sub clock is not used.
From the time during reset to the time reset is released, the main
clock divided by 2 is being selected as the clock f2. When the system
clock selection bit is set “1” in that condition, the main clock divided
by 16 is selected as the clock f2 and the clock frequency supplied for
the CPU and internal peripheral devices is divided by 8 more. It makes
current consumption restrict, although the operation speed slows.
When the timer B2 clock source selection bit (bit 1 of the port function
control register) is set to “1” and event counter mode is selected in
timer B2 under the condition which the port-Xc selection bit is “0”;
fc32 , which is the main clock divided by 32, is connected as a timer
B’s count source. Accordingly, timer B2 can be used as a clock timer
which always operates with a regular clock source shown in Figure
69. For details relating to register setting of timer B2, refer to the
section “Clock timer” on timer B.
Timer B2 count start flag
Writing pulse of clock
prescaler reset bit
XCIN
(Note)
XCIN × 31(cycle)
XCIN × 32 (cycle)
Clock source of clock timer(fc32)
n–1
n (Set value)
Timer B2 count value
This applies when the main clock is selected as the system clock (System clock selection bit (CM3) = “0”).
Note. Period of fc32 = XCIN × 31 (cycle) (only in this term)
Period of fc32 = XCIN × 32 (cycle) (after this term)
Fig. 68 Operation timing for clock prescaler and clock timer B2
Notes 1. f2 = f(XIN) / 2 expresses that the clock f2 is
the main clock divided by 2.
2. f2 = f(XIN) expresses that the clock f2 is the
direct main clock, which is not divided.
Reset
(Note 1)
f2 = f(XIN) / 2
CM3 = “0”
CC0 = “1”
CM3 = “1”
CC0 = “0”
(Note 2)
1)
f(X
ININ
) /) 2
f2f2= =f(X
f2 = f(XIN) / 16
CM3 = “0”
CC0 = “1”
CC0 = “0”
CM3 = “1”
f2 = f(XIN) / 8
• In the case of not using sub clock (CM4 = “0”)
Fig. 69 Clock f2 state transition (when the sub clock is not used.)
60
CC0 = Main clock division selection bit
CM3 = System clock selection bit
CM4 = Port-Xc selection bit
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
STANDBY FUNCTION
The WIT and the STP instructions make the microcomputer standby
state.
Table 10 shows the relationship between standby state and each
block’s operation.
When the WIT instruction is executed with the system clock stop bit
at wait state (bit 5 of the oscillation circuit control register 0) = “0”,
internal clock φ is stopped being at “L”, but the oscillation circuit,
system clock, and divided clocks f2 to f512 are not stopped.
Because divided clocks f2 to f512 are not stopped, a part of internal
peripheral devices which use these divided clocks can operate even
at wait state.
Otherwise, when the WIT instruction is executed with the system
clock stop bit at wait state = “1”, the oscillation circuit is not stopped,
but the system clock, divided clocks, and internal clock φ are stopped.
Accordingly, in this case, all of the internal peripheral devices which
use divided clocks f2 to f512, including the watchdog timer, are stopped.
When port-XC selection bit is “1” to operate the sub-clock oscillation
circuit, however, clock timer B2 can operate because clock fC32 for
the clock timer is not stopped.
When internal peripheral devices are not used, later wait state (System
clock stop bit at wait state = “1”) is more effective to restrict the current
consumption.
Make sure to set the system clock stop bit at wait state to “1”
immediately before the WIT instruction execution and clear the bit to
“0” immediately after the wait state is terminated.
The wait state is terminated when an interrupt request is accepted,
and the internal clock φ operation is restarted. At this time, interrupt
processing can immediately be executed because oscillation circuit’s
operation is not stopped during the wait state.
When the STP instruction is executed, the oscillation circuit is stopped
with internal clock φ stopped at “L”. Furthermore, “FFF 16” is
automatically set into the watchdog timer, and the clock source of
the watchdog timer is forced to connect with f32 when the main clock
is selected or f8 when the sub clock is selected. This connection is
cut off when the most significant bit of the watchdog timer is cleared
to “0” or the microcomputer is reset, and the clock source is connected
with the input depending on the content of the watchdog timer
frequency selection flag. In the stop state, internal peripheral devices
using divided clocks f2 to f512 are stopped.
The stop state is terminated by system reset or interrupt request
acceptance, and then oscillation is restarted. At this time, supply of
system clock and divided clocks f2 to f512 is restarted.
In that condition, when the main clock external input selection bit is
“0” and the main clock is being selected as a system clock, or when
the sub clock external input selection bit is “0” and the sub clock is
being selected as a system clock, internal clock φ is stopped at “L” till
the most significant bit of the watchdog timer decremented with divided
clock f32 or f8 becomes “0”. However, supply of internal clock φ is
restarted immediately after the oscillation restarts by reset.
Accordingly, in this case, it is necessary to wait for the oscillation
stabilized before making the reset input “H”.
Otherwise in that condition, when the main clock external input
selection bit is “1” and the main clock is being selected as a system
clock, or when the sub clock external input selection bit is “1” and the
sub clock is being selected as a system clock, supply of internal clock
φ is restarted from the seventh clock of clock f2 after the oscillation
restarts. By this function, the microcomputer can immediately return
from the stop state when the clock supply input from the external is
stabilized.
Even though the main clock or the sub clock is input externally, make
sure to clear the main clock external input selection bit or the sub
clock external input selection bit to “0” before executing the STP
instruction if this external clock is unstable for a short time at a return
from the stop state.
Table 10. Relationship between standby state and each block’s operation
Instruction
System clock
stop bit at wait
Oscillation circuit
state
System clock
f2 – f 512
Clock output φ 1
Internal clock φ
“0”
Operating
(Note)
Operating
Operating
Operating
Stopped
(“L”)
“1”
Operating
(Note)
Stopped
Stopped
Stopped
(“L”)
Stopped
(“L”)
Stopped
Stopped
Stopped
(“L”)
Stopped
(“L”)
WIT
STP
Operation at WIT/STP state
—
Stopped
Internal peripheral devices
using f2 – f512
Operation enabled
(Watchdog timer is operating)
Operation disabled
(Watchdog timer is stopped)
(Clock timer’s operation is enabled)
Operation disabled
(Watchdog timer is stopped)
Note. When the main clock external input selection bit is “1”, the main clock oscillation circuit stops. When the sub clock external input selection
bit is “1”, the sub-clock oscillation circuit stops. (In both cases, the external clock can be input.)
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MITSUBISHI MICROCOMPUTERS
M37733MHBXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The wait/stop state is terminated by interrupt acceptance or reset.
Accordingly, it is necessary to prepare the state in which any interrupt
can be accepted before the WIT/STP instruction is executed.
Additionally, it is necessary to set the system clock stop bit at wait
state before the WIT instruction is executed.
When the WIT/STP instruction is executed in a bus access cycle, the
bus enters the non-access state (E is at “H”) because internal clock
φ (or oscillation) is stopped after the read/write in this cycle is finished.
Pins P00/A0 to P33/HLDA normally retain the state at which internal
clock φ is stopped in the wait/stop state.
However, only in the memory expansion mode and the microprocessor
mode, arbitrary data which is set in the port P0 to P3 latches can be
output from pins P00/A0 to P3 3/ HLDA even at the wait/stop state when
the following conditions are satisfied before the WIT/STP instruction
execution.
• The standby state selection bit (bit 0 of the port function control
register) is set to “1”.
• “FF16 ” is set into the port P0 to P3 direction registers.
Furthermore, when the standby state selection bit is set to “1” and bit
6 of the oscillation circuit control register 0 (signal output disable
selection bit) is set to “1”, “L” level can be output from the E pin at the
wait/stop state. For the signal output disable selection bit, refer to
Table 7 on the processor mode section.
Note that the function of arbitrary data output cannot be emulated
using a debugger.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
ROM AREA MODIFICATION FUNCTION
The internal ROM size and RAM size of the M37733MHBXXXFP can
be modified by the memory allocation control register’s bits 0,1 and 2
shown in Figure 70.
Figure 72 shows the memory allocation in which the internal ROM
size and RAM size are modified.
Make sure to write data in the memory allocation control register as
the flow shown in Figure 71.
This ROM area modification function is valid in memory expansion
mode and single-chip mode.
7
6
5
4
3
2
1
0
0
0
ML2
ML1
ML0
When ordering a mask ROM, Mitsubishi Electric corp. produces the
mask ROM using the data within 128 Kbytes (addresses 00000016 –
01FFFF16 ). It is regardless of the selected ROM size (refer to MASK
ROM ORDER CONFIRMATION FORM.) Therefore, program “FF16 ”
to the addresses out of the selected ROM area in the EPROM which
you tender when ordering a mask ROM.
Address 01FFFF16 of this microcomputer corresponds to the lowest
address of the EPROM which you tender.
Memory allocation control register
Address
6316
Memory allocation selection bits
ROM size
RAM size
0 0 0 : 124 Kbytes 3968 bytes
0 0 1 : 120 Kbytes 3968 bytes
0 1 0 : 60 Kbytes 2048 bytes
1 0 0 : 32 Kbytes 2048 bytes
1 0 1 : 16 Kbytes 2048 bytes
1 1 0 : 96 Kbytes 3968 bytes
0 0 : Always “00” (However, writing data “5516”
shown in Figure 71 is possible.)
Note. Write to the memory allocation control register as the flow shown in Figure 71.
Fig. 70 Bit configuration of memory allocation control register
Writing data “5516” (LDM instruction)
Next instruction
Writing data “0Y16” (LDM instruction)
ML2, ML1, ML0 selection bits
• How to write in memory allocation control register
Note. “Y” is the sum of bits to be set. For example, when setting bit 1 to “1”, “Y” becomes “2”.
Fig. 71 How to write data in memory allocation control register
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(ML2, ML1, ML0) = (0, 0, 0)
00000016
00007F16
00008016
000FFF16
00100016
SFR
Internal RAM
3968 bytes
(ML2, ML1, ML0) = (0, 0, 1)
00000016
00007F16
00008016
000FFF16
SFR
Internal RAM
3968 bytes
Internal ROM
124 Kbytes
00FFFF16
01000016
01FFFF16
01FFFF16
FFFFFF16
FFFFFF16
(ML2, ML1, ML0) = (1, 0, 0)
00000016
00007F16
00008016
00087F16
00087F16
SFR
Internal RAM
2048 bytes
00000016
00007F16
00008016
00087F16
SFR
Internal RAM
2048 bytes
(1.9 Kbytes)
00100016
Internal ROM
120 Kbytes
Internal ROM
60 Kbytes
00FFFF16
01000016
FFFFFF16
(ML2, ML1, ML0) = (1, 0, 1)
(29.9 Kbytes)
SFR
Internal RAM
2048 bytes
(ML2, ML1, ML0) = (1, 1, 0)
00000016
00007F16
00008016
000FFF16
SFR
Internal RAM
3968 bytes
(28 Kbytes)
(45.9 Kbytes)
00800016
00800016
Internal ROM
32 Kbytes
00FFFF16
01000016
00000016
00007F16
00008016
(4 Kbytes)
00200016
00FFFF16
01000016
(ML2, ML1, ML0) = (0, 1, 0)
00C00016
00FFFF16
01000016
Internal ROM
16 Kbytes
00FFFF16
01000016
Internal ROM
96 Kbytes
01FFFF16
FFFFFF16
FFFFFF16
FFFFFF16
: External memory area
Fig. 72 Memory allocation (modification of internal ROM and RAM area by memory allocation selection bits)
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MITSUBISHI MICROCOMPUTERS
M37733MHBXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
ADDRESSING MODES
The M37733MHBXXXFP has 28 powerful addressing modes. Refer
to the “7700 Family Software Manual” for the details.
MACHINE INSTRUCTION LIST
The M37733MHBXXXFP has 103 machine instructions. Refer to the
“7700 Family Software Manual” for the details.
DATA REQUIRED FOR MASK ROM ORDERING
Please send the following data for mask orders.
(1) M37733MHBXXXFP mask ROM order confirmation form
(2) 80P6N mark specification form
(3) ROM data (EPROM 3 sets)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
ABSOLUTE MAXIMUM RATINGS
Symbol
Vcc
AVcc
VI
VI
VO
Pd
Topr
Tstg
Parameter
Conditions
Power source voltage
Analog power source voltage
Input voltage RESET, CNVss, BYTE
Input voltage P00 – P07, P1 0 – P1 7, P2 0 – P2 7,
P30 – P33, P40 – P47, P5 0 – P5 7,
P60 – P67, P7 0 – P7 7, P8 0 – P8 7,
VREF, XIN
Output voltage P00 – P07, P1 0 – P1 7, P2 0 – P2 7,
P30 – P33, P40 – P47, P5 0 – P5 7,
P60 – P67, P7 0 – P7 7, P8 0 – P8 7,
XOUT , E
Power dissipation
Ta = 25 °C
Operating temperature
Storage temperature
Ratings
–0.3 to +7
–0.3 to +7
–0.3 to +12
Unit
V
V
V
–0.3 to Vcc + 0.3
V
–0.3 to Vcc + 0.3
V
300
–20 to +85
–40 to +150
mW
°C
°C
RECOMMENDED OPERATING CONDITIONS (Vcc = 5 V ± 10%, Ta = –20 to +85 °C, unless otherwise noted)
Symbol
Vcc
VIH
VIH
VIH
VIL
VIL
VIL
I OH(peak)
I OH(avg)
I OL(peak)
I OL(peak)
I OL(avg)
IOL(peak)
f(XIN)
f(XCIN)
Notes 1.
2.
3.
4.
Min.
4.5
2.7
f(X IN) : Operating
f(X IN) : Stopped, f(XCIN) = 32.768 kHz
Analog power source voltage
Power source voltage
Analog power source voltage
High-level input voltage P00 – P07, P30 – P3 3, P4 0 – P4 7, P50 – P57, P60 – P6 7,
0.8 Vcc
P70 – P77, P8 0 – P8 7, XIN, RESET, CNVss, BYTE, XCIN (Note 3)
High-level input voltage P10 – P17, P20 – P27 (in single-chip mode)
0.8 Vcc
High-level input voltage P10 – P17, P20 – P27
0.5 Vcc
(in memory expansion mode and microprocessor mode)
Low-level input voltage P00 – P0 7, P3 0 – P3 3, P40 – P47, P50 – P57, P6 0 – P6 7,
0
P70 – P77, P8 0 – P8 7, XIN, RESET, CNVss, BYTE, XCIN (Note 3)
Low-level input voltage P10 – P1 7, P2 0 – P2 7 (in single-chip mode)
0
Low-level input voltage P10 – P1 7, P2 0 – P2 7
0
(in memory expansion mode and microprocessor mode)
High-level peak output current P00 – P07, P10 – P1 7, P2 0 – P2 7, P30 – P33,
P40 – P4 7, P5 0 – P5 7, P60 – P67, P70 – P7 7,
P80 – P87
High-level average output current P00 – P07, P1 0 – P1 7, P2 0 – P27, P30 – P33,
P40 – P4 7, P5 0 – P57, P60 – P67, P70 – P77,
P80 – P8 7
Low-level peak output current P00 – P0 7, P1 0 – P17, P20 – P27, P30 – P3 3,
P40 – P4 3, P54 – P57, P60 – P6 7, P7 0 – P7 7,
P80 – P87
Low-level peak output current P44 – P4 7, P5 0 – P5 3
Low-level average output current P00 – P0 7, P1 0 – P17, P20 – P27, P3 0 – P3 3,
P40 – P43, P5 4 – P5 7, P6 0 – P67, P70 – P77,
P80 – P87
Low-level average output current P44 – P4 7, P5 0 – P53
Main-clock oscillation frequency (Note 4)
Sub-clock oscillation frequency
Average output current is the average value of a 100 ms interval.
The sum of IOL(peak) for ports P0, P1, P2, P3, and P8 must be 80 mA or less,
the sum of IOH(peak) for ports P0, P1, P2, P3, and P8 must be 80 mA or less,
the sum of IOL(peak) for ports P4, P5, P6, and P7 must be 100 mA or less, and
the sum of IOH(peak) for ports P4, P5, P6, and P7 must be 80 mA or less.
Limits VIH and VIL for XCIN are applied when the sub clock external input selection bit = “1”.
The maximum value of f(XIN) = 12.5 MHz when the main clock division selection bit = “1”.
Power source voltage
AVcc
Vss
AVss
66
Parameter
Limits
Typ.
5.0
Max.
5.5
5.5
Vcc
0
0
32.768
Unit
V
V
V
V
Vcc
V
Vcc
V
Vcc
V
0.2Vcc
V
0.2Vcc
V
0.16Vcc
V
–10
mA
–5
mA
10
mA
20
mA
5
mA
15
25
50
mA
MHz
kHz
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz, unless otherwise noted)
Symbol
VOH
VOH
VOH
VOH
VOL
VOL
VOL
VOL
VOL
VT+ – VT–
VT+ – VT–
VT+ – VT–
VT+ – VT–
IIH
IIL
IIL
VRAM
Parameter
Test conditions
High-level output voltage P00 – P07, P10 – P17, P20 – P27,
P33, P40 – P47, P50 – P57,
IOH = –10 mA
P60 – P67, P70 – P77, P80 – P87
High-level output voltage P00 – P07, P10 – P17, P20 – P27,
IOH = –400 µA
P33
IOH = –10 mA
High-level output voltage P30 – P32
ICH = –400 µA
IOH = –10 mA
High-level output voltage E
IOH = –400 µA
Low-level output voltage P00 – P07, P10 – P17, P20 – P27,
P33, P40 – P43, P54 – P57,
IOL = 10 mA
P60 – P67, P70 – P75, P80 – P87
Low-level output voltage P44 – P47, P50 – P53
IOL = 20 mA
Low-level output voltage P00 – P07, P10 – P17, P20 – P27,
IOL = 2 mA
P33
IOL = 10 mA
Low-level output voltage P30 – P32
IOL = 2 mA
IOL = 10 mA
Low-level output voltage E
IOL = 2 mA
Hysteresis HOLD, RDY, TA0IN – TA4IN, TB0IN – TB2IN,
INT0 – INT2, ADTRG, CTS0, CTS1, CTS2, CLK0,
CLK1, CLK2, KI0 – KI3
Hysteresis RESET
Hysteresis XIN
Hysteresis XCIN (When external clock is input)
High-level input current
P00 – P07, P10 – P17, P20 – P27, P30 – P33,
VI = 5 V
P40 – P47, P50 – P57, P60 – P67, P70 – P77,
P80 – P87, XIN, RESET, CNVss, BYTE
Low-level input current
P00 – P07, P10 – P17, P20 – P27, P30 – P33,
VI = 0 V
P40 – P47, P50 – P53, P60, P61, P65 – P67,
P70 – P77, P80 – P87, XIN, RESET, CNVss, BYTE
VI = 0 V,
Low-level input current P54 – P57, P62 – P64
RAM hold voltage
Min.
Limits
Typ.
Unit
3
V
4.7
V
3.1
4.8
3.4
4.8
V
V
2
V
2
V
0.45
V
1.9
0.43
1.6
0.4
V
V
0.4
1
V
0.2
0.1
0.1
0.5
0.4
0.4
V
V
V
without a pull-up transistor
VI = 0 V,
with a pull-up transistor
When clock is stopped.
Max.
–0.25
2
–0.5
5
µA
–5
µA
–5
µA
–1.0
mA
V
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Limits
Typ.
Max.
9.5
19
mA
1.3
2.6
mA
VCC = 5V,
f(XIN) = 25 MHz (square waveform),
f(XCIN) = 32.768 kHz,
when a WIT instruction is executed (Note 2)
10
20
µA
VCC = 5 V,
f(XIN) : Stopped,
f(XCIN) : 32.768 kHz,
in operating (Note 3)
50
100
µA
Test conditions
Min.
VCC = 5 V,
f(XIN) = 25 MHz (square waveform),
f(f2) = 12.5 MHz,
f(XCIN) = 32.768 kHz,
in operating (Note 1)
VCC = 5 V,
f(XIN) = 25 MHz (square waveform),
(f(f2) = 1.5625 MHz),
f(XCIN) = Stopped,
in operating (Note 1)
Power source
current
ICC
Notes 1.
2.
3.
4.
In single-chip
mode, output pins
are open, and
other pins are VSS.
Unit
VCC = 5 V,
f(XIN) : Stopped,
µA
5
10
f(XCIN) : 32.768 kHz,
when a WIT instruction is executed (Note 4)
Ta = 25 °C,
µA
1
when clock is stopped
Ta = 85 °C,
µA
20
when clock is stopped
This applies when the main clock external input selection bit = “1”, the main clock division selection bit = “0”, and the signal output stop
bit = “1”.
This applies when the main clock external input selection bit = “1” and the system clock stop bit at wait state = “1”.
This applies when CPU and the clock timer are operating with the sub clock (32.768 kHz) selected as the system clock.
This applies when the XCOUT drivability selection bit = “0” and the system clock stop bit at wait state = “1”.
A–D CONVERTER CHARACTERISTICS
(VCC = AVCC = 5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz (Note), unless otherwise noted)
Symbol
Parameter
Test conditions
Resolution
VREF = VCC
Absolute accuracy
VREF = VCC
RLADDER
Ladder resistance
VREF = VCC
tCONV
Conversion time
VREF
Reference voltage
VIA
Analog input voltage
Note. This applies when the main clock division selection bit = “0” and f(f2) = 12.5 MHz.
Min.
—
—
68
10
9.44
2
0
Limits
Typ.
Max.
10
±3
25
VCC
VREF
Unit
Bits
LSB
kΩ
µs
V
V
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
TIMING REQUIREMENTS (VCC = 5 V ± 10%, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz, unless otherwise noted (Note))
Notes 1. This applies when the main clock division selection bit = “0” and f(f2) = 12.5 MHz.
2. Input signal’s rise/fall time must be 100 ns or less, unless otherwise noted.
External clock input
Symbol
Parameter
Limits
Min.
40
15
15
Max.
Unit
tc
External clock input cycle time (Note 3)
ns
tw(H)
External clock input high-level pulse width (Note 4)
ns
tw(L)
External clock input low-level pulse width (Note 4)
ns
tr
External clock rise time
8
ns
tf
External clock fall time
8
ns
Notes 3. When the main clock division selection bit = “1”, the minimum value of tc = 80 ns.
4. When the main clock division selection bit = “1”, values of tw(H) / tc and tw(L) / tc must be set to values from 0.45 through 0.55.
Single-chip mode
Symbol
tsu(P0D–E)
tsu(P1D–E)
tsu(P2D-E)
tsu(P3D–E)
tsu(P4D–E)
tsu(P5D–E)
tsu(P6D–E)
tsu(P7D–E)
tsu(P8D–E)
th(E–P0D)
th(E–P1D)
th(E–P2D)
th(E–P3D)
th(E–P4D)
th(E–P5D)
th(E–P6D)
th(E–P7D)
th(E–P8D)
Parameter
Port P0 input setup time
Port P1 input setup time
Port P2 input setup time
Port P3 input setup time
Port P4 input setup time
Port P5 input setup time
Port P6 input setup time
Port P7 input setup time
Port P8 input setup time
Port P0 input hold time
Port P1 input hold time
Port P2 input hold time
Port P3 input hold time
Port P4 input hold time
Port P5 input hold time
Port P6 input hold time
Port P7 input hold time
Port P8 input hold time
Limits
Min.
60
60
60
60
60
60
60
60
60
0
0
0
0
0
0
0
0
0
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Memory expansion mode and microprocessor mode
Symbol
tsu(D–E)
tsu(RDY– φ 1)
tsu(HOLD– φ 1)
th(E–D)
th( φ 1–RDY)
th( φ 1–HOLD)
Parameter
Data input setup time
RDY input setup time
HOLD input setup time
Data input hold time
RDY input hold time
HOLD input hold time
Limits
Min.
32
55
55
0
0
0
Max.
Unit
ns
ns
ns
ns
ns
ns
69
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MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A input
(Count input in event counter mode)
Symbol
tc(TA)
tw(TAH)
tw(TAL)
parameter
TAiIN input cycle time
TAiIN input high-level pulse width
TAiIN input low-level pulse width
Limits
Min.
80
40
40
Max.
Unit
ns
ns
ns
Timer A input (Gating input in timer mode)
Symbol
tc(TA)
tw(TAH)
tw(TAL)
parameter
TAiIN input cycle time (Note)
TAiIN input high-level pulse width (Note)
TAiIN input low-level pulse width (Note)
Limits
Min.
320
160
160
Max.
Unit
ns
ns
ns
Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS” on page 72.
Timer A input (External trigger input in one-shot pulse mode)
Symbol
t c(TA)
tw(TAH)
tw(TAL)
parameter
TAiIN input cycle time (Note)
TAiIN input high-level pulse width
TAiIN input low-level pulse width
Limits
Min.
320
80
80
Max.
Unit
ns
ns
ns
Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS” on page 72.
Timer A input (External trigger input in pulse width modulation mode)
Symbol
tw(TAH)
tw(TAL)
parameter
TAiIN input high-level pulse width
TAiIN input low-level pulse width
Limits
Min.
80
80
Max.
Unit
ns
ns
Timer A input (Up-down input in event counter mode)
Symbol
tc(UP)
tw(UPH)
tw(UPL)
tsu(UP–TIN)
th(TIN–UP)
parameter
TAiOUT input cycle time
TAiOUT input high-level pulse width
TAiOUT input low-level pulse width
TAiOUT input setup time
TAiOUT input hold time
Limits
Min.
2000
1000
1000
400
400
Max.
Unit
ns
ns
ns
ns
ns
Timer A input (Two-phase pulse input in event counter mode)
Symbol
t c(TA)
TAj input cycle time
tsu(TAjIN–TAjOUT) TAjIN input setup time
tsu(TAjOUT–TAjIN) TAjOUT input setup time
70
parameter
Limits
Min.
800
200
200
Max.
Unit
ns
ns
ns
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B input (Count input in event counter mode)
Symbol
tc(TB)
tw(TBH)
tw(TBL)
tc(TB)
tw(TBH)
tw(TBL)
Parameter
TBiIN input cycle time (one edge count)
TBiIN input high-level pulse width (one edge count)
TBiIN input low-level pulse width (one edge count)
TBiIN input cycle time (both edges count)
TBiIN input high-level pulse width (both edges count)
TBiIN input low-level pulse width (both edges count)
Limits
Min.
80
40
40
160
80
80
Max.
Unit
ns
ns
ns
ns
ns
ns
Timer B input (Pulse period measurement mode)
Symbol
tc(TB)
tw(TBH)
tw(TBL)
Parameter
TBiIN input cycle time (Note)
TBiIN input high-level pulse width (Note)
TBiIN input low-level pulse width (Note)
Limits
Min.
320
160
160
Max.
Unit
ns
ns
ns
Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS” on page 72.
Timer B input (Pulse width measurement mode)
Symbol
tc(TB)
tw(TBH)
tw(TBL)
Parameter
TBiIN input cycle time (Note)
TBiIN input high-level pulse width (Note)
TBiIN input low-level pulse width (Note)
Limits
Min.
320
160
160
Max.
Unit
ns
ns
ns
Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS” on page 72.
A-D trigger input
Symbol
tc(AD)
tw(ADL)
Parameter
ADTRG input cycle time (minimum allowable trigger)
ADTRG input low-level pulse width
Limits
Min.
1000
125
Max.
Unit
ns
ns
Serial I/O
Symbol
tc(CK)
tw(CKH)
tw(CKL)
td(C–Q)
th(C–Q)
tsu(D–C)
th(C–D)
Parameter
CLKi input cycle time
CLKi input high-level pulse width
CLKi input low-level pulse width
TXDi output delay time
TXDi hold time
RXDi input setup time
RXDi input hold time
Limits
Min.
200
100
100
Max.
80
0
30
90
Unit
ns
ns
ns
ns
ns
ns
ns
External interrupt INTi input, key input interrupt KIi input
Symbol
tw(INH)
tw(INL)
tw(KIL)
Parameter
INTi input high-level pulse width
INTi input low-level pulse width
KIi input low-level pulse width
Limits
Min.
250
250
250
Max.
Unit
ns
ns
ns
71
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MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DATA FORMULAS
Timer A input (Gating input in timer mode)
Symbol
Parameter
tc(TA)
TAiIN input cycle time
tw(TAH)
TAiIN input high-level pulse width
tw(TAL)
TAiIN input low-level pulse width
Limits
Min.
8 ✕ 109
2 · f(f2)
4 ✕ 109
2 · f(f2)
4 ✕ 109
2 · f(f2)
Max.
Unit
ns
ns
ns
Timer A input (External trigger input in one-shot pulse mode)
Symbol
tc(TA)
Parameter
TAiIN input cycle time
Limits
Min.
8 ✕ 109
2 · f(f2)
Max.
Unit
ns
Timer B input (In pulse period measurement mode or pulse width measurement mode)
Symbol
Parameter
tc(TB)
TBiIN input cycle time
tw(TBH)
TBiIN input high-level pulse width
tw(TBL)
TBiIN input low-level pulse width
Note. f(f2) represents the clock f2 frequency.
For the relation to the main clock and sub clock, refer to Table 9.
72
Limits
Min.
8 ✕ 109
2 · f(f2)
4 ✕ 109
2 · f(f2)
4 ✕ 109
2 · f(f2)
Max.
Unit
ns
ns
ns
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SWITCHING CHARACTERISTICS (VCC = 5 V ± 10%, VSS = 0 V, Ta = –20 to 85°C, f(XIN) = 25 MHz (Note), unless otherwise noted)
Symbol
Parameter
Test conditions
td(E–P0Q)
Port P0 data output delay time
td(E–P1Q)
Port P1 data output delay time
td(E–P2Q)
Port P2 data output delay time
td(E–P3Q)
Port P3 data output delay time
Fig. 73
td(E–P4Q)
Port P4 data output delay time
td(E–P5Q)
Port P5 data output delay time
td(E–P6Q)
Port P6 data output delay time
td(E–P7Q)
Port P7 data output delay time
td(E–P8Q)
Port P8 data output delay time
Note. This applies when the main clock division selection bit = “0” and f(f2) = 12.5 MHz.
Limits
Min.
Max.
80
80
80
80
80
80
80
80
80
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
P0
P1
P2
P3
50 pF
P4
P5
P6
P7
P8
φ1
E
Fig. 73 Measuring circuit for ports P0 – P8 and φ 1
73
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory expansion mode and microprocessor mode
(VCC = 5 V ± 10%, VSS = 0 V, Ta = 25 °C, f(XIN) = 25 MHz (Note 1), unless otherwise noted)
Symbol
td(An–E)
td(A–E)
Parameter
Address output delay time
Address output delay time
th(E–An)
Address hold time
tw(ALE)
ALE pulse width
tsu(A–ALE)
th(ALE–A)
Address output set up time
Address hold time
td(ALE–E)
ALE output delay time
td(E–DQ)
th(E–DQ)
Data output delay time
Data hold delay time
tw(EL)
E pulse width
tpxz(E–DZ)
tpzx(E–DZ)
Floating start delay time
Floating release delay time
td(BHE–E)
BHE output delay time
td(R/W–E)
R/ W output delay time
th(E–BHE)
th(E–R/W)
td(E– φ 1)
td( φ 1–HLDA)
BHE hold time
R/ W hold time
Test
(Note 2)
Wait mode conditions
No wait
Wait 1
Wait 0
No wait
Wait 1
Wait 0
No wait
Wait 1
Wait 0
No wait
Wait 1
Wait 0
No wait
Wait 1
Wait 0
No wait
Wait 1
Wait 0
Fig. 73
Max.
No wait
Wait 1
Wait 0
ns
87
ns
12
ns
75
ns
18
ns
22
ns
57
ns
5
ns
45
ns
9
ns
15
ns
4
ns
18
50
ns
ns
ns
ns
130
ns
10
20
ns
ns
12
ns
87
ns
12
ns
87
18
18
0
ns
ns
ns
ns
ns
5
No wait
Wait 1
Wait 0
No wait
Wait 1
Wait 0
φ 1 output delay time
HLDA output delay time
Unit
12
45
Notes 1. This applies when the main clock division selection bit = “0” and f(f2) = 12.5 MHz.
2. No wait : Wait bit = “1”.
Wait 1 : The external memory area is accessed with wait bit = “0” and wait selection bit = “1”.
Wait 0 : The external memory area is accessed with wait bit = “0” and wait selection bit = “0”.
74
Limits
Min.
18
50
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory expansion mode and microprocessor mode
Bus timing data formulas (VCC = 5 V ± 10%, VSS = 0 V, Ta = –20 to 85 °C,
Symbol
td(An–E)
Parameter
Address output delay time
f(XIN) = 25 MHz (Max., Note), unless otherwise noted)
Wait mode
No wait
Wait 1
Wait 0
td(A–E)
Address output delay time
No wait
Wait 1
Wait 0
th(E–An)
tw(ALE)
Address hold time
ALE pulse width
No wait
Wait 1
Wait 0
tsu(A–ALE)
Address output set up time
No wait
Wait 1
Wait 0
th(ALE–A)
Address hold time
No wait
Wait 1
Wait 0
td(ALE–E)
td(E–DQ)
ALE output delay time
Data hold time
tw(EL)
E pulse width
tpxz(E–DZ)
Floating start delay time
tpzx(E–DZ)
Floating release delay time
BHE output delay time
1 ✕ 109
2 · f(f2)
R/W output delay time
1 ✕ 10
2 · f(f2)
No wait
1 ✕ 109
2 · f(f2)
2 ✕ 109
2 · f(f2)
4 ✕ 109
2 · f(f2)
BHE hold time
th(E–R/W)
R/W hold time
td(E– φ 1)
φ 1 output delay time
ns
ns
ns
ns
ns
ns
ns
ns
ns
– 25
ns
ns
– 30
ns
45
Wait 1
Wait 0
No wait
Wait 1
No wait
Wait 1
1 ✕ 109
2 · f(f2)
1 ✕ 109
2 · f(f2)
3 ✕ 109
2 · f(f2)
1 ✕ 109
2 · f(f2)
3 ✕ 109
2 · f(f2)
1 ✕ 109
2 · f(XIN)
1 ✕ 109
2 · f(XIN)
0
ns
– 22
ns
– 30
ns
– 30
ns
5
Wait 0
th(E–BHE)
ns
4
Wait 0
Unit
9
Wait 0
td(R/W–E)
Max.
9
Data output delay time
th(E–DQ)
td(BHE–E)
No wait
Wait 1
Limits
Min.
1 ✕ 109
– 28
2 · f(f2)
3 ✕ 109
– 33
2 · f(f2)
9
1 ✕ 10
– 28
2 · f(f2)
9
3 ✕ 10
– 45
2 · f(f2)
9
1 ✕ 10
– 22
2 · f(f2)
1 ✕ 109
– 18
2 · f(f2)
2 ✕ 109
– 23
2 · f(f2)
9
1 ✕ 10
– 35
2 · f(f2)
9
2 ✕ 10
– 35
2 · f(f2)
ns
– 20
ns
– 28
ns
– 33
ns
– 28
ns
– 33
ns
– 22
ns
– 22
ns
18
ns
Notes 1. This applies when the main-clock division selection bit = “0”.
2. f(f2) represents the clock f2 frequency.
For the relation to the main clock and sub clock, refer to Table 9.
75
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MITSUBISHI MICROCOMPUTERS
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T
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PR
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
TIMING DIAGRAM
tr
tf
tc
tw(H)
Single-chip mode
XIN
E
td(E–P0Q)
Port P0 output
tsu(P0D–E)
th(E–P0D)
Port P0 input
td(E–P1Q)
Port P1 output
tsu(P1D–E)
th(E–P1D)
Port P1 input
td(E–P2Q)
Port P2 output
tsu(P2D–E)
th(E–P2D)
Port P2 input
td(E–P3Q)
Port P3 output
tsu(P3D–E)
th(E–P3D)
Port P3 input
td(E–P4Q)
Port P4 output
tsu(P4D–E)
th(E–P4D)
Port P4 input
td(E–P5Q)
Port P5 output
tsu(P5D–E)
th(E–P5D)
Port P5 input
td(E–P6Q)
Port P6 output
tsu(P6D–E)
th(E–P6D)
Port P6 input
td(E–P7Q)
Port P7 output
tsu(P7D–E)
th(E–P7D)
Port P7 input
td(E–P8Q)
Port P8 output
tsu(P8D–E)
Port P8 input
76
th(E–P8D)
tw(L)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
In event count mode
TAiOUT input
(Up-down input)
TAiIN input
(when count by falling)
TAiIN input
(when count by rising)
th(TIN–UP)
tsu(UP–TIN)
In event counter mode
(When two-phase pulse input is selected)
tc(TA)
TAjIN input
tsu(TAjIN–TAjOUT)
tsu(TAjIN–TAjOUT)
tsu(TAjOUT–TAjIN)
TAjOUT input
tsu(TAjOUT–TAjIN)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
77
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
tc(AD)
tw(ADL)
ADTRG input
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C–Q)
TxDi
td(C–Q)
tSU(D–C)
RxDi
tw(INL)
INTi input
Kli input
78
tw(INH)
tw(KNL)
th(C–D)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory expansion mode and microprocessor mode
(When wait bit = “1”)
φ1
E
RDY input
tsu(RDY– φ 1) th( φ 1–RDY)
( When wait bit = “0”)
φ1
E
RDY input
tsu(RDY– φ 1) th( φ 1–RDY)
(When wait bit = “1” or “0” in common)
φ1
tsu(HOLD– φ 1)
th( φ 1–HOLD)
HOLD input
td( φ 1–HLDA)
td( φ 1–HLDA)
HLDA output
Test conditions
• VCC = 5 V ± 10%
• Input timing voltage : V IL = 1.0 V, VIH = 4.0 V
• Output timing voltage : V OL = 0.8 V, VOH = 2.0 V
79
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory expansion mode and microprocessor mode
(No wait : When wait bit = “1”)
tw(L)
tw(H)
tf
tr
tc
XIN
φ1
td(E- φ1)
td(E- φ1)
tw(EL)
E
td(An-E)
An
th(E-An)
Address
Address
tw(ALE)
Address
td(ALE-E)
ALE
th(ALE-A)
th(E-DQ)
tsu(A-ALE)
Am/Dm
Address
Data
tpxz(E-DZ)
tpzx(E-DZ)
Address
Address
th(E-D)
td(E-DQ)
td(A-E)
tsu(D-E)
DmIN
Data
td(BHE-E)
th(E-BHE)
BHE
td(R/W-E)
R/W
Test condition
• VCC = 5 V ± 10%
• Output timing voltage : VIL = 0.8 V, VIH = 2.0 V
• Data input DmIN : VIL = 0.8 V, VIH = 2.5 V
80
th(E-R/W)
IM
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory expansion mode and microprocessor mode
(Wait 1 : The external area is accessed when wait bit = “0” and wait selection bit = “1”.)
tw(L)
tw(H)
tf tr
tc
XIN
φ1
td(E– φ 1)
td(E– φ 1)
tw(EL)
E
td(An–E)
th(E–An)
Address
An
tw(ALE)
Address
td(ALE–E)
ALE
th(ALE–A)
tsu(A–ALE)
Am/Dm
th(E–DQ)
Address
td(A–E)
Data
tpzx(E–DZ)
tpxz(E–DZ)
Address
Address
td(E–DQ)
th(E–D)
tsu(D–E)
DmIN
Data
td(BHE–E)
th(E–BHE)
td(R/W–E)
th(E–R/W)
BHE
R/W
Test condition
• Vcc = 5 V ± 10%
• Output timing voltage : V OL = 0.8 V, V OH = 2.0 V
• Data input Dm IN : VIL = 0.8 V, VIH = 2.5 V
81
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory expansion mode and microprocessor mode
(Wait 0 : The external memory area is accessed when wait bit = “0” and wait selection bit = “0”.)
tw(L)
tw(H)
tf tr
tc
XIN
φ1
td(E– φ1)
td(E– φ1)
tw(EL)
E
td(An–E)
th(E–An)
Address
An
tw(ALE)
td(ALE–E)
tsu(A–ALE)
th(ALE–A)
Address
Address
ALE
th(E–DQ)
Am/Dm
Address
Data
tpzx(E–DZ)
tpxz(E–DZ)
Address
Address
td(E–DQ)
td(A–E)
tsu(D–E)
Data
DmIN
td(BHE–E)
th(E–BHE)
BHE
td(R/W–E)
R/W
Test conditions
• Vcc = 5 V ± 10%
• Output timing voltage : V OL = 0.8 V, V OH = 2.0 V
• Data input Dm IN : VIL = 0.8 V, VIH = 2.5 V
82
th(E–R/W)
th(E–D)
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MITSUBISHI MICROCOMPUTERS
M37733MHBXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PACKAGE OUTLINE
83
GZZ–SH00–77B<84A0>
Mask ROM number
7700 FAMILY MASK ROM ORDER CONFIRMATION FORM
SINGLE-CHIP 16-BIT MICROCOMPUTER
M37733MHBXXXFP
MITSUBISHI ELECTRIC
Receipt
Date:
Section head Supervisor
signature
signature
TEL
(
Company
name
Customer
Date
issued
)
Date:
Issuance
signatures
Note : Please fill in all items marked
Responsible
officer
Supervisor
1. Confirmation
Specify the name of the product being ordered.
Three sets of EPROMs are required for each pattern (Check @ in the appropriate box).
If at least two of the three sets of EPROMs submitted contain the identical data, we will produce masks based on this data.
We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data.
Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted.
(hexadecimal notation)
Checksum code for entire EPROM areas
EPROM Type :
(1) Set “FF16 ” in the shaded area.
27C201
(2) Address 016 to 1016 are the area for storing the data on
model designation and options.This area must be written
with the data shown below.
00000
00010
Details for option data are given next in the section
describing the STP instruction option.
Address and data are written in hexadecimal notation.
20000
128K
DATA
3FFFF
Note : Make sure that address 01FFFF16
of the microcomputer’s internal
ROM corresponds to address
3FFFF 16 of EPROM.
4D
33
37
37
33
33
4D
48
Address
0
1
2
3
4
5
6
7
42
FF
FF
FF
FF
FF
FF
FF
Address
Address
Option data 10
8
9
A
B
C
D
E
F
2. STP instruction option
One of the following sets of data should be written to the option data address (1016) of the EPROM you have ordered.
Check @ in the appropriate box.
STP instruction enable
STP instruction disable
0116
Address 1016
Address 1016
3. Mark specification
Mark specification must be submitted using the correct form for the type of package being ordered fill out the appropriate
80P6N Mark Specification Form (for M37733MHBXXXFP) and attach to the Mask ROM Order Confirmation Form.
4. Comments
0016
80P6N (80-PIN QFP) MARK SPECIFICATION FORM
Mitsubishi IC catalog name
Please choose one of the marking types below (A, B, C), and enter the Mitsubishi IC catalog name and the special mark (if needed).
A. Standard Mitsubishi Mark
64
41
40
65
Mitsubishi IC catalog name
Mitsubishi product number
(6-digit, or 7-digit)
25
80
1
24
B. Customer’s Parts Number + Mitsubishi IC Catalog Name
64
41
40
65
25
80
1
24
Customer’s Parts Number
Note : The fonts and size of characters are standard Mitsubishi type.
Mitsubishi IC catalog name
Notes 1 : The mark field should be written right aligned.
2 : The fonts and size of characters are standard Mitsubishi type.
3 : Customer’s parts number can be up to 14 alphanumeric characters for capital letters, hyphens, commas, periods and so on.
C. Special Mark Required
64
41
65
40
80
25
1
24
Notes1 : If special mark is to be printed, indicate the desired layout of the mark in the left figure. The layout will be
duplicated technically as close as possible.
Mitsubishi product number (6-digit, or 7-digit) and Mask
ROM number (3-digit) are always marked for sorting the
products.
2 : If special character fonts (e,g., customer’s trade mark
logo) must be used in Special Mark, check the box below.
For the new special character fonts, a clean font original
(ideally logo drawing) must be submitted.
Special character fonts required
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MITSUBISHI MICROCOMPUTERS
M37733MHBXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Keep safety first in your circuit designs!
¡ Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of
substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
¡ These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any
intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
¡ Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples
contained in these materials.
¡ All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi
Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor for the latest product information before purchasing a product listed herein.
¡ Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact
Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for
transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
¡ The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.
¡ If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the
approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
¡ Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
© 1996 MITSUBISHI ELECTRIC CORP.
H-LF422-A KI-9605 Printed in Japan (ROD) 2
New publication, effective May. 1996.
Specifications subject to change without notice.
REVISION DESCRIPTION LIST
Rev.
No.
M37733MHBXXXFP Datasheet
Rev.
date
Revision Description
1.00
First Edition
970604
1.01
The following are added:
980526
• MASK ROM ORDER CONFIRMATION FORM
• MARK SPECIFICATION FORM
2.00
The following are revised:
980731
Page
Previous Version
Revised Version
P5
Right column
Line 4
Additionally, the internal ROM area can be modified by software.
Additionally, the internal ROM and RAM area can
be modified by software.
P5
Fig. 1
Note. Internal ROM area can be modified. (Refer
to the section on ROM area modification
function.)
Note. Internal ROM and RAM area can be modified. (Refer to the section on ROM area
modification function.)
P9
Right column
Line 12
The CPU operates on an internal clock φ ’s frequency which is obtained by dividing the external
clock frequency f(X IN) by two.
The CPU operates on an internal clock φ ’s frequency.
P63
Left column
Line 2
The internal ROM size and its address area of the
M37733MHBXXXFP can be modified by the
memory allocation control register’s bits 0,1 and 2
shown in Figure 70.
Figure 72 shows the memory allocation in which
the internal ROM size and its address area are
modified.
The internal ROM size and RAM size of the
M37733MHBXXXFP can be modified by the
memory allocation control register’s bits 0,1 and 2
shown in Figure 70.
Figure 72 shows the memory allocation in which
the internal ROM size and RAM size are modified.
P63
Fig. 70
Memory allocation selection bits
ROM size
(ROM area)
0 0 0 : 124 Kbytes (addresses 00100016 – 01FFFF16)
0 0 1 : 120 Kbytes (addresses 00200016 – 01FFFF16)
1 1 0 : 96 Kbytes (addresses 00800016 – 01FFFF16)
1 1 1 : 32 Kbytes (addresses 00800016 – 00FFFF16)
Memory allocation selection bits
ROM size
RAM size
0 0 0 : 124 Kbytes 3968 bytes
0 0 1 : 120 Kbytes 3968 bytes
0 1 0 : 60 Kbytes 2048 bytes
1 0 0 : 32 Kbytes 2048 bytes
1 0 1 : 16 Kbytes 2048 bytes
1 1 0 : 96 Kbytes 3968 bytes
P64
Fig. 72
Refer to page (2).
Refer to page (3).
The M37733MHBXXXFP has 28 powerful
addressing modes. Refer to the SINGLE-CHIP 16BIT MICROCOMPUTERS DATA BOOK for the
details of each addressing mode.
The M37733MHBXXXFP has 28 powerful
addressing modes. Refer to the “7700 Family
Software Manual” for the details.
P65
Right column
Line 2
MACHINE INSTRUCTION LIST
MACHINE INSTRUCTION LIST
The M37733MHBXXXFP has 103 machine
instructions. Refer to the SINGLE-CHIP 16-BIT
MICROCOMPUTERS DATA BOOK for details.
(1)
The M37733MHBXXXFP has 103 machine
instructions. Refer to the “7700 Family Software
Manual” for the details.
REVISION DESCRIPTION LIST
M37733MHBXXXFP Datasheet
Previous version
(ML2, ML1, ML0) = (0, 0, 0)
(ML2, ML1, ML0) = (0, 0, 1)
(ML2, ML1, ML0) = (1, 1, 0)
(ML2, ML1, ML0) = (1, 1, 1)
ROM size : 124 Kbytes
ROM size :120 Kbytes
ROM size : 96 Kbytes
ROM size : 32 Kbytes
00000016
00007F16
00008016
000FFF16
00100016
SFR
Internal RAM
3968 bytes
00000016
00007F16
00008016
000FFF16
SFR
Internal RAM
3968 bytes
00000016
00007F16
00008016
000FFF16
SFR
Internal RAM
3968 bytes
00000016
00007F16
00008016
000FFF16
SFR
Internal RAM
3968 bytes
(4 Kbytes)
00200016
Internal ROM
60 Kbytes
(28 Kbytes)
Internal ROM
56 Kbytes
00800016
(28 Kbytes)
00800016
Internal ROM
32 Kbytes
Internal ROM
32 Kbytes
00FFFF16
01000016
00FFFF16
01000016
Internal ROM
64 Kbytes
00FFFF16
01000016
Internal ROM
64 Kbytes
00FFFF16
01000016
Internal ROM
64 Kbytes
01FFFF16
01FFFF16
01FFFF16
FFFFFF16
FFFFFF16
FFFFFF16
: External memory area
Fig. 72 Memory allocation (modification of internal ROM area by memory allocation selection bit)
(2)
FFFFFF16
REVISION DESCRIPTION LIST
M37733MHBXXXFP Datasheet
Revised version
(ML2, ML1, ML0) = (0, 0, 0)
00000016
00007F16
00008016
000FFF16
00100016
SFR
Internal RAM
3968 bytes
(ML2, ML1, ML0) = (0, 0, 1)
00000016
00007F16
00008016
000FFF16
SFR
Internal RAM
3968 bytes
Internal ROM
124 Kbytes
00FFFF16
01000016
01FFFF16
01FFFF16
FFFFFF16
FFFFFF16
(ML2, ML1, ML0) = (1, 0, 0)
00000016
00007F16
00008016
00087F16
00087F16
SFR
Internal RAM
2048 bytes
00000016
00007F16
00008016
00087F16
SFR
Internal RAM
2048 bytes
(1.9 Kbytes)
00100016
Internal ROM
120 Kbytes
Internal ROM
60 Kbytes
00FFFF16
01000016
FFFFFF16
(ML2, ML1, ML0) = (1, 0, 1)
(29.9 Kbytes)
SFR
Internal RAM
2048 bytes
(ML2, ML1, ML0) = (1, 1, 0)
00000016
00007F16
00008016
000FFF16
SFR
Internal RAM
3968 bytes
(28 Kbytes)
(45.9 Kbytes)
00800016
00800016
Internal ROM
32 Kbytes
00FFFF16
01000016
00000016
00007F16
00008016
(4 Kbytes)
00200016
00FFFF16
01000016
(ML2, ML1, ML0) = (0, 1, 0)
00C00016
00FFFF16
01000016
Internal ROM
16 Kbytes
00FFFF16
01000016
Internal ROM
96 Kbytes
01FFFF16
FFFFFF16
FFFFFF16
FFFFFF16
: External memory area
Fig. 72 Memory allocation (modification of internal ROM and RAM area by memory allocation selection bits)
(3)