i5141-TG

i5141-TG
i5141-TG
SD/MMC Memory Card Controller
Datasheet
Version 1.1
iCreate Technologies Corporation
2006/9/28
© 2006 iCreate Technologies Corporation
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iCreate Technologies Corporation reserves the right to change the specification in any manner without notice.
i5141-TG
© Copyright 2006 iCreate Technologies Corporation
Information contained in this publication is intended through suggestion only and may be superseded by updates.
No liability is assumed by iCreate Technologies Corporation with respect to the use of such information or
otherwise and no representation or warranty is given. Use of iCreate’s products as critical components in life
support systems is not authorized.
No part of this document may be reproduced or transmitted in any form or by any means for any purpose without
the permission of iCreate. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.
The iCreate logo and name are registered trademarks of iCreate Technologies Corporation. All rights reserved.
All other trademarks mentioned herein are the property of their respective companies.
Data sheet marking
iCreate uses various markings in the data sheet to designate each document phase as it relates to the product
development stage.
Marking
Description
Objective Specification The objective specification contains data for new product development.
Advance Information
The information is on products in the design phase. Your designs should not be finalized
with this information.
Preliminary
This is preliminary information on new products but not yet fully characterized. The
specifications in these data sheets are subject to change in any manner without notice.
No Marking
Information contained in the data sheet is on products in full production.
For more information please contact:
iCreate Technologies Corporation
nd
2F, No. 26, R&D 2 Road, Science-Based Industrial Park,
Hsinchu, Taiwan 30077, R.O.C.
Phone:
+886-3-579-0000
Fax:
+886-3-579-0077
E-mail:
[email protected]
© 2006 iCreate Technologies Corporation
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i5141-TG
Revision History
Date
Revision
Description
2006/9/25
1.0
Initial release version
2006/9/28
1.1
Update new package outline
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i5141-TG
1. Introduction
1.1. General description
i5141-TG is a high performance flash memory controller for SD/MMC interface flash memory cards. This chip
is based on iCreate 3rd-generation flash engine to achieve high data transfer rate. The enhanced designs
include high performance CPU, multi-bank flash access, 8/16-bit flash interface, and Reed-Solomon based ECC
capability. Voltage-Regulator, Power-on-reset and RC oscillator are integrated to reduce BOM cost and PCB
area. Typical applications of i5141-TG are SD, miniSD, MMC and RS-MMC memory card.
1.2. Features
Compliant to SD1.1, MMC4.1 standards
1/4/8-bit host data transfer
SD/MMC Clock frequency 0 ~ 52 MHz
Integrated power-on-reset and RC oscillator
On-the-fly ECC (4 Byte per 528 Byte)
Wear-leveling mechanism
Support large block NAND type flash
Support small block NAND type flash
Support AG-AND type flash
4 flash chips enable
Auto-suspend to conserve energy
1.3. Block diagram
Figure 1. Block diagram
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i5141-TG
2. Pin Diagram and Description
2.1. Pin Diagram
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Figure 2. Pin Diagram
© 2006 iCreate Technologies Corporation
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i5141-TG
2.2. Pin Description
Pin Name
Type*1
Description
VDD33
Power
Internal regulator 3.3V input pin.
VDD18
Power
Internal regulator 1.8V output pin.
VDDC
Power
1.8V power supply for core.
VDDP
Power
3.3V power supply for I/O.
GND
Power
Power supply ground.
VDDA33
Power
3.3V power supply for analog block.
GNDA
Power
Power supply ground for analog block.
ROSC
Analog
Connect 3.9K Ohm resister to VDD18 for internal 50MHz clock generator.
DAT0~3
IO/ST/PUC
SD/MMC Data Bus
CMD
IO/ST/PUC
SD/MMC Command/Response signal
CLK
I/ST
SD/MMC Clock input.
FCE0~1
IO/ST/PUC
Flash chip enable signal.
FRBn
IO/ST/PUC
Flash Ready/Busy signal
FCLE
IO/ST/PUC
Flash command latch enable
FALE
IO/ST/PUC
Flash address latch enable.
FREn
IO/ST/PUC
Flash read enable.
FWEn
IO/ST/PUC
Flash write enable.
FWPn
IO/ST/PUC
Flash write protect.
FD0~FD7
IO/ST/PUC
Flash data bus.
SDMMC
I
SD/MMC Selection. MMC Mode when Tie-High and SD Mode when Tie-Low.
TEST
I/PD
Test mode enable. This pin must floating or tie-low when normal operation.
TCLK
I/ST
Clock for test mode.
TRSTn
I/PD
Reset for test mode.
GPIO0
IO/ST/PUC
General purpose I/O pin.
*1: I/O Type I: Input pin.
IO: Bidirectional pin. ST: pin with S Trigger.
PD: pin with pull-down resister.
Analog: Analog pin
PUC: pin with controllable pull-up resister.
Power: Power Pin
Table 1. Pin Description
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i5141-TG
3. Internal Regulator, Power-ON Reset and RC oscillator
3.1. Regulator
The internal voltage regulator input 3.3V and output 1.8V used for core power supply as shown in Figure 3.
3.2. Power-on-reset and brown-out-reset
The internal reset control unit has power-on-reset (POR). To use internal POR, only provide 3.3V to VDDA33
and GNDA connected to ground as shown in Figure 3.
3.3. RC oscillator
An integrated RC oscillator can be used to reduce BOM cost. ROSC must be connected to 1.8V through a
resistor, as shown in Figure 3.
.
Figure 3. Pin connection to use internal Regulator, Power-ON Reset and Oscillator
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i5141-TG
4. Electrical specifications
4.1. Absolute maximum ratings
Symbol
Description
Value
Unit
VDD
I/O Power Supply Voltage
- 0.3 to +3.6
V
VDDP, VDD33, VDD33A
VDDC
Core Power Supply Voltage
- 0.3 to +1.98
V
VDDC
- 0.3 to VDD + 0.3
V
- 45 to +85
°C
VIN, VOUT
Tstg
All input/output voltages
Storage temperature range
Notes
Table 2. Absolute maximum ratings
4.2. Recommended operating conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
I/O Power Supply Voltage
2.7
3.3
3.6
V
VDDC
Core Power Supply Voltage
1.62
1.8
1.98
V
TOPR
Operating temperature
0
70
o
C
Table 3. Recommended operation conditions
4.3. Power-on-reset characteristics
Symbol
VT(POR)
Parameter
Threshold voltage of power-on-reset
Typ.
Unit
2.6
V
Table 4. Power-on-reset characteristics
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i5141-TG
4.4. Bus Operating Conditions
4.4.1. General
Parameter
Symbol
Peak voltage on all lines
Min.
Max.
Unit Remark
-0.5
3.6
V
-10
10
A
-10
10
A
All inputs
Input Leakages Current
All outputs
Output Leakages Current
Table 5. Bus Operating Conditions – General
4.4.2. Bus Signal Level
Figure 4. Bus Signal Level
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i5141-TG
4.5. SD Mode Bus Operating Conditions
4.5.1. Deault
Figure 5. SD Mode: Timing Diagram Data Input/Output Referenced to Clock (Default)
Parameter
Symbol
Min.
Max.
Unit
Remark
Clock CLK (All values are referred to min(VIH) and max (VIL),
Clock frequency Data Transfer Mode
fPP
0
25
MHz
Clock frequency Identification Mode
fOD
0(1)/100
400
KHz
Clock low time
tWL
10
ns
Clock high time
tWH
10
ns
Clock rise time
tTLH
10
ns
Clock fall time
tTHL
10
ns
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CCARD 10pF
(1 card)
CCARD 10pF
(1 card)
CCARD 10pF
(1 card)
CCARD 10pF
(1 card)
CCARD 10pF
(1 card)
CCARD 10pF
(1 card)
i5141-TG
Parameter
Symbol
Min.
Max.
Unit
Remark
Input CMD, DAT (referenced to CLK)
Input set-up time
tISU
5
ns
Input hold time
tIH
5
ns
Output Delay time during Data Transfer Mode
tODLY
0
14
ns
Output Delay time during Identification Mode
tODLY
0
50
ns
CCARD 10pF
(1 card)
CCARD 10pF
(1 card)
Outputs CMD, DAT (referenced to CLK)
CL 40pF
(1 card)
CL 40pF
(1 card)
(1) 0 Hz means to stop the clock. The given minimum frequency range is for cases were continues clock is
required.
Table 6. SD Mode: Bus Timing – Parameters Value (Default)
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i5141-TG
4.5.2. High Speed
Figure 6. SD Mode: Timing Diagram Data Input/Output Referenced to Clock (High-Speed)
Parameter
Symbol
Min.
Max.
Unit
50
MHz
Remark
Clock CLK (All values are referred to min(VIH) and max (VIL),
Clock frequency Data Transfer Mode
fPP
0
Clock low time
tWL
7
ns
Clock high time
tWH
7
ns
Clock rise time
tTLH
3
ns
Clock fall time
tTHL
3
ns
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CCARD 10pF
(1 card)
CCARD 10pF
(1 card)
CCARD 10pF
(1 card)
CCARD 10pF
(1 card)
CCARD 10pF
(1 card)
i5141-TG
Parameter
Symbol
Min.
Max.
Unit
Remark
Input CMD, DAT (referenced to CLK)
Input set-up time
tISU
6
ns
Input hold time
tIH
2
ns
CCARD 10pF
(1 card)
CCARD 10pF
(1 card)
Outputs CMD, DAT (referenced to CLK)
Output Delay time during Data Transfer Mode
tODLY
Output Hold time
tOH
Total System capacitance for each line
CL
14
2.5
ns
40
(1) In order to satisfy severe timing, host shall drive only one card.
Table 7. SD Mode: Bus Timing – Parameters Values (High-Speed)
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ns
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pF
CL 40pF
(1 card)
CL
15pF
(1 card)
1 card
i5141-TG
4.6. MMC Mode Bus Operating Conditions
Figure 7. MMC Mode: Timing Diagram - Data Input/Output
4.6.1. Card Interface Timing
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i5141-TG
Table 8. MMC Mode: High-Speed Card Interface Timing
Table 9. MMC Mode: Backwards Compatible Card Interface Timing
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i5141-TG
4.7. Flash Interface Command Write AC characteristics
Symbol
Parameter
Min.
Max.
Unit
tCLS
FCLE setup time
0
ns
tCLH
FCLE hold time
10
ns
tCS
FCE# setup time
0
ns
tCH
FCE# hold time
10
ns
tWP
FWE# pulse width
25
ns
tALS
FALE setup time
0
ns
tALH
FALE hold time
10
ns
tDS
Data Setup time
20
ns
tDH
Data hold time
10
ns
Table 10. Timing Parameters: Flash Interface Command Write
FCLE
tCLS
tCLH
tCS
tCH
FCE#
tWP
FWE#
tALS
tALH
FALE
tDS
tDH
Command
FD
Figure 8. Timing Diagram: Flash Interface Command Write
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i5141-TG
4.8. Flash Interface Address Write AC characteristics
Symbol
Parameter
Min.
Max.
Unit
tCLS
FCLE setup time
0
ns
tCS
FCE# setup time
0
ns
tCH
FCE# hold time
10
ns
tWP
FWE# pulse width
25
ns
tWH
FWE# high hold time
15
ns
tALS
FALE setup time
0
ns
tALH
FALE hold time
10
ns
tDS
Data Setup time
20
ns
tDH
Data hold time
10
ns
tWC
Flash write cycle time
50
Table 11. Timing Parameters: Flash Interface Address Write
FCLE
FCE#
FWE#
tCLS
tCS
tWC
tWC
tWP
tWP
tWP
tWH
tALS
tWC
tALH
tWP
tWH
tALS
tALH
tWH
tALS
tALH
tALS
tALH
FALE
tDS
FD
tDH
Col. Add1
tDS
tDH
Col. Add2
tDS
tDH
Row Add1
Figure 9. Timing Diagram: Flash Interface Address Write
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tDS
tDH
Row Add2
i5141-TG
4.9. Flash Interface Data Write AC characteristics
Symbol
Parameter
Min.
Max.
tCLH
FCLE hold time
10
ns
tCH
FCE# hold time
10
ns
tWP
FWE# pulse width
25
ns
tWH
FWE# high hold time
15
ns
tALS
FALE setup time
0
ns
tDS
Data setup time
20
ns
tDH
Data hold time
10
ns
tWC
Flash write cycle time
50
ns
Table 12. Timing Parameters: Flash Interface Data Write
tCLH
FCLE
tCH
FCE#
FALE
FWE#
tALS
tWC
tWP
tWP
tWP
tWH
tDS
FD
Unit
tDH
DIN 0
tWH
tDS
tDH
DIN 1
tDS
tDH
DIN Final
Figure 10. Timing Diagram: Flash Interface Data Write
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i5141-TG
4.10.
Flash Interface Data Read AC characteristics
Symbol
Parameter
Min.
Max.
Unit
tCLR
FCLE to FRE# delay
10
ns
tAR
ALE to FRE# delay
10
ns
tRR
Ready to FRE# low
20
ns
tRC
Read cycle time
30
ns
Table 13. Timing Parameters: Flash Interface Data Read
tCLR
FCLE
FCE#
tWC
FWE#
tWB
tAR
FALE
tR
tRHZ
tRC
FRE#
tRR
FD
00h
Col.Add1
Col.Add2
Row Add1
Row Add2
30h
Dout N
Dout
N+1
Busy
FREADY/
BUSY#
Figure 11. Timing Diagram: Flash Interface Data Read
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tOH
Dout M
i5141-TG
5. Package Dimensions
Figure 12. i5141-TG Package Diagram
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