Create i510x CompactFlash Memory Card Controller Datasheet Version 1.3 iCreate Technologies Corporation Release date: 12/9/2004 © 2004 iCreate Technologies Corporation iCreate Technologies Corporation reserves the right to change the specification in any manner without notice. Page 1 Create i510x © Copyright 2004 iCreate Technologies Corporation Information contained in this publication is intended through suggestion only and may be superseded by updates. No liability is assumed by iCreate Technologies Corporation with respect to the use of such information or otherwise and no representation or warranty is given. Use of iCreate’s products as critical components in life support systems is not authorized. No part of this document may be reproduced or transmitted in any form or by any means for any purpose without the permission of iCreate. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The iCreate logo and name are registered trademarks of iCreate Technologies Corporation. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. Data sheet marking iCreate uses various markings in the data sheet to designate each document phase as it relates to the product development stage. Marking Description Objective Specification The objective specification contains data for new product development. Advance Information The information is on products in the design phase. Your designs should not be finalized with this information. Preliminary This is preliminary information on new products but not yet fully characterized. The specifications in these data sheets are subject to change in any manner without notice. No Marking Information contained in the data sheet is on products in full production. For more information please contact: iCreate Technologies Corporation 2F, No. 26, R&D 2nd Road, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C. Phone +886-3-579-0000 Fax +886-3-579-0077 e-mail [email protected] Page 2 Release date: 12/9/2004 © 2004 iCreate Technologies Corporation iCreate Technologies Corporation reserves the right to change the specification in any manner without notice. Create i510x 1. Introduction General description i510X is a high performance flash memory controller for CompactFlash/ATA interface memory devices. This chip is based on iCreate 2nd-generation flash engine to achieve high data transfer rate. The enhanced designs include high-speed RISC CPU, multi-bank flash access, 8/16-bit flash interface, and ECC capability. Power-on-reset, RC oscillator and LDO regulator are integrated to reduce BOM cost and PCB area. Typical applications of i510X are CompactFlash memory card, IDE flash disk module/chip and PCMCIA flash card. Features Compliant to CompactFlash, PCMCIA, and ATA standards 8-bit/16-bit host data transfer Support PIO mode 4 5V and 3.3V host interface Integrated power-on-reset, RC oscillator and LDO regulator On-the-fly ECC Wear-leveling mechanism Support Samsung 2KB/page BLC NAND flash Number of flash chips: i5100: 8 chips i5101: 16 chips Package: i5100: TQFP 100 pin i5101: TQFP 128 pin Block diagram POR RC-OSC Program memory (Mask ROM ) MCU Core Data memory (SRAM) Attribute Memory Data Mux Flash Interface ECC CF Interface Buffer Interface Buffer Banks Figure 1. Block diagram Release date: 12/9/2004 © 2004 iCreate Technologies Corporation iCreate Technologies Corporation reserves the right to change the specification in any manner without notice. Page 1 Create i510x 2. Pin configuration and definition GNDA ROSC VDDA RESET# VDDCLK NC CLKI GNDCLK FWP# FWE# FALE FCLE FRE# FRDY SEL_CLK VDDQ GNDQ FCE7# FCE5# FCE3# FCE1# TEST GNDC SEL_RST FCE6# 2.1. Pin diagrams FCE4# FCE2# FCE0# FD0 FD1 FD2 FD3 FD4 FD5 FD6 VDDC VDDQ FD7 GNDQ FD8 FD9 FD10 FD11 FD12 FD13 FD14 FD15 VDD3 VDD5 GNDR HRDY HA6 HCSEL# HA5 HA4 HRST GNDC HA3 HWAIT# HA2 HINPACK# HA1 HREG# HA0 HBVD2 VDDPQ HD0 HBVD1 HD1 HD8 GNDPQ HD2 HD9 HWP HD10 HD3 HD11 HD4 HD12 HD5 GNDC HD13 GNDPQ HD6 VDDPQ HD14 HD7 HD15 HCE1# VDDC HCE2# HA10 HOE# HIORD# HA9 HIOWR# HA8 GNDPQ HWE# HA7 Figure 2. 100-pin configuration Page 2 Release date: 12/9/2004 © 2004 iCreate Technologies Corporation iCreate Technologies Corporation reserves the right to change the specification in any manner without notice. Create i510x Figure 3. 128-pin configuration 2.2. Pin function Host interface Pin Name HA0 ~ HA10 HBVD1 HBVD2 Pin No. (100pin) Pin No. (128pin) 17, 20, 22, 25, 27, 20, 25, 29, 33, 35, 29, 30, 33, 35, 37, 37, 38, 41, 43, 45, 39 47 43 52 40 48 Type 5V/3.3V In, Schmitt Trigger Function (Refer to CF Specification) HA0 ~ HA10 (PC Card Memory Mode) HA0 ~ HA10 (PC Card I/O Mode) HA0 ~ HA2 (True IDE Mode) 5V/3.3V In/Out, BVD1 (PC Card Memory Mode) Schmitt Trigger, STSCHG# (PC Card I/O Mode) 4mA PDIAG# (True IDE Mode) 5V/3.3V In/Out, BVD2 (PC Card Memory Mode) Schmitt Trigger, SPKR# (PC Card I/O Mode) 4mA DASP# (True IDE Mode) Release date: 12/9/2004 © 2004 iCreate Technologies Corporation iCreate Technologies Corporation reserves the right to change the specification in any manner without notice. Page 3 Create i510x HCE1#, HCE2# 5V/3.3V In, 14, 16 Schmitt Trigger, Pull up HCSEL# HD0 ~ HD15 15, 18 28 36, 1, 2, 3, 4, 5, 7, 9, 1, 2, 3, 4, 5, 7, 9, 11, 11, 12, 13, 42, 44, 12, 13, 50, 54, 56, 45, 47, 48, 50 59, 61, 65 36 44 HINPACK# HIORD# 19 HIOWR# 21 HOE# 18 HRDY 26 HREG# 38 HRST 31 23 27 22 34 46 39 34 HWE# 24 HWP 49 42 32 63 CE1#, CE2# (PC Card I/O Mode) Card Enable CS0#, CS1# (True IDE Mode) 5V/3.3V In, CSEL# (PC Card Memory Mode) Schmitt Trigger, CSEL# (PC Card I/O Mode) Pull up CSEL# (True IDE Mode) 5V/3.3V In/Out, HD0 ~ HD15 (PC Card Memory Mode) Schmitt Trigger, HD0 ~ HD15 (PC Card I/O Mode) 8mA HD0 ~ HD15 (True IDE Mode) 5V/3.3V Output, 4mA INPACK# (PC Card Memory Mode) INPACK# (PC Card I/O Mode) INPACK# (True IDE Mode) 5V/3.3V In, IORD# (PC Card Memory Mode) Schmitt Trigger, IORD# (PC Card I/O Mode) Pull up IORD# (True IDE Mode) 5V/3.3V In, IOWR# (PC Card Memory Mode) Schmitt Trigger, IOWR# (PC Card I/O Mode) Pull up IOWR# (True IDE Mode) 5V/3.3V In, OE# (PC Card Memory Mode) Schmitt Trigger, OE# (PC Card I/O Mode) Pull up ATASEL# (True IDE Mode) 5V/3.3V Output, 4mA RDY/BSY# (PC Card Memory Mode) IREQ# (PC Card I/O Mode) INTRQ (True IDE Mode) 5V/3.3V In, REG# (PC Card Memory Mode) Schmitt Trigger, REG# (PC Card I/O Mode) Pull up REG# (True IDE Mode) 5V/3.3V In, RESET (PC Card Memory Mode) Schmitt Trigger, RESET (PC Card I/O Mode) Pull up HWAIT# CE1#, CE2# (PC Card Memory Mode) RESET# (True IDE Mode) 5V/3.3V Output, 4mA WAIT# (PC Card Memory Mode) WAIT# (PC Card I/O Mode) IORDY (True IDE Mode) 5V/3.3V In, WE# (PC Card Memory Mode) Schmitt Trigger, WE# (PC Card I/O Mode) Pull up WE# (True IDE Mode) 5V/3.3V In, Schmitt Trigger WP (PC Card Memory Mode) IOIS16# (PC Card I/O Mode) IOIS16# (True IDE Mode) Flash interface Pin Name Pin No. (100) Pin No. (128) Type Function Page 4 Release date: 12/9/2004 © 2004 iCreate Technologies Corporation iCreate Technologies Corporation reserves the right to change the specification in any manner without notice. Create i510x 54, 55, 56, 57, 58, FD0 ~ FD15 59, 60, 61, 63, 66, 67, 68, 69, 70, 71, 72 Flash Data Bus 0 ~ 7. Connect to flash memory 70, 71, 72, 73, 74, 75, 76, 77, 80, 83, 84, 85, In/Out, 3mA 86, 87, 88, 89 FALE 90 118 Out, 3mA FCLE 89 117 Out, 3mA FRE#, FWE# 88 , 91 116, 119 Out, 3mA FCE0# ~ 73, 74, 75, 76, 80, 93, 94, 96, 97, 104, FCE7# 81, 82, 83 105, 106, 108 FCE8# ~ FCE15# - pins FD0 ~ FD7. 91, 92, 99, 100, 103, 110, 111, 112, Out, 2mA Out, 2mA FWP# 92 120 Out, 3mA FRDY 87 115 In Flash Address Latch Enable. Connect to flash memory pin ALE Flash Command Latch Enable. Connect to flash memory pin CLE Flash Read/Write Enable. Connect to flash memory pin RE/WE. Flash Chip Enable. Connect to flash memory pin CE. Flash Chip Enable. Connect to flash memory pin CE. Flash Write-Protect. Connect to flash memory pin WP. Flash Ready/BSY signal. Connect to flash memory pin Ready/Busy#. System interface & power pins Pin Name Pin No. (100) Pin No. (128) Type Function SEL_CLK 86 114 In SEL_RST 77 98 In TEST 79 102 In Test mode enable pin. Connected to GND. RX - 95 In Test pin. Connected to 3.3V or GND. TX - 107 Out, 3mA CLKI 94 122 In Connected to 3.3V to select internal oscillator, or GND for external clock. Connected to 3.3V to select internal power-onreset or GND for external reset Test pin. Not connected. Clock input Reset input if reset is provided externally. If RESET# 97 125 In SEL_RST is high, this pin is connected to GND through a capacitor. Connected to the same power source as VDDA ROSC 99 127 Analog In REG_EN - 67 In Regulator enable IROM_SEL - 90 In Test pin. Connected to 3.3V or NC. through a resistor to configure oscillator frequency Release date: 12/9/2004 © 2004 iCreate Technologies Corporation iCreate Technologies Corporation reserves the right to change the specification in any manner without notice. Page 5 Create i510x VDDPQ 10, 41 10, 49, Power for CF interface (3.3V or 5V) GNDPQ 8, 23, 46 8, 30, 57 Ground for CF interface VDDQ 64, 85 81, 113 3.3V power for flash interface GNDQ 62, 84 78, 101, 109 VDDC 15, 65, 17, 82 GNDC 6, 32, 78 6, 40, 79 VDD5 52 68 VDD3 53 69 GNDR 51 66 Ground for LDO regulator VDDA 98 126 3.3V power for reset circuit GNDA 100 128 Ground for analog circuit VDDCLK 96 124 3.3V power for oscillator GNDCLK 93 121 Ground for oscillator Ground for flash interface 3.3V power for core Ground for core Power input for LDO regulator (3.3V or 5V) O 3.3V LDO regulator output Page 6 Release date: 12/9/2004 © 2004 iCreate Technologies Corporation iCreate Technologies Corporation reserves the right to change the specification in any manner without notice. Create i510x 3. Reset voltage detector and RC oscillator Power-on-reset and brown-out-reset The internal reset control unit has power-on-reset (POR) and brown-out-reset (BOR) functions. To use internal POR, set SEL_RST to 1 and RESET# must be connected to an external capacitor as shown in Fig. 3. To use external reset signal, set SEL_RST to 0 and RESET# becomes the reset signal input. 3.3V Vdd SEL_RST RESET# Cext Figure 3. Pin connection to use internal power-on-reset/brown-out-reset Internal RC oscillator An integrated RC oscillator can be used to reduce BOM cost. When the internal oscillator is enabled, ROSC must be connected to 3.3V through a resistor, as shown in Figure 4, while CLKI is not connected. The value of Rext determines the oscillator frequency. The relationship of Rext and typical oscillator frequency is as follows. Rext 15KΩ 22KΩ 30KΩ 58KΩ Fosc 50MHz 40MHz 33MHz 20MHz 3.3V Vdd Rext CLKI ROSC 3.3V Vdd SEL_CLK Figure 4. Pin connection to use internal Oscillator Release date: 12/9/2004 © 2004 iCreate Technologies Corporation iCreate Technologies Corporation reserves the right to change the specification in any manner without notice. Page 7 Create i510x 4. Electrical specifications Absolute maximum ratings Symbol Description Value Unit Notes VCC VCC Voltage - 0.3 to +6.5 V VDDPQ VDD VDD Voltage - 0.3 to +4.6 V VDDC, VDDQ - 0.3 to VCC + 0.3 V CF interface - 0.3 to VDD + 0.3 V Other I/O except CF interface - 25 to +125 °C VIN, VOUT All input/output voltages VIN, VOUT Tstg Storage temperature range Recommended operating conditions Symbol Parameter VCC VCC voltage VDD VDD voltage TOPR Operating temperature Min. Typ. Max. Unit 4.5 5 5.5 V 3.15 3.3 3.45 V 3.15 3.3 3.45 0 70 V o C DC characteristics Symbol Parameter Min. VIH3 High level input voltage for 3.3V domain 2.4 VIL3 Low level input voltage for 3.3V domain VOH3 High level output voltage for 3.3V domain VOL3 Low level output voltage for 3.3V domain VIH53 High level input voltage for 5V domain under 3.3V VIL53 Low level input voltage for 5V domain under 3.3V VOH53 High level output voltage for 5V domain under 3.3V VOL53 Low level output voltage for 5V domain under 3.3V Typ. Max. Unit V 0.6 2.4 V V 0.4 2.4 V V 0.6 Vcc-0.8 V V 0.4 V Page 8 Release date: 12/9/2004 © 2004 iCreate Technologies Corporation iCreate Technologies Corporation reserves the right to change the specification in any manner without notice. Create i510x VIH55 High level input voltage for 5V domain under 5V VIL55 Low level input voltage for 5V domain under 5V VOH55 High level output voltage for 5V domain under 5V VOL55 Low level output voltage for 5V domain under 5V 4.0 V 0.8 Vcc-0.8 V V 0.4 V Typ. Unit Power-on-reset characteristics Symbol Parameter VT(POR) Threshold voltage of power-on-reset 2.8 V VT(BOR) Threshold voltage for brown-out-reset 2.6 V CF attribute memory read and write AC characteristics For the definitions of parameters, please refer to CompactFlash Specification Rev. 2.1. Symbol Parameter Min. Max. 300 Unit tcR Read cycle time Ns ta(A) Address access time 300 Ns ta(CE) Card Enable access time 300 ns ta(OE) Output Enable access time 150 ns tdis(CE) Output disable time from CE 100 ns tdis(OE) Output disable time from OE 100 ns tsu(A) Address setup time 30 ns ten(CE) Output enable time from CE 5 ns ten(OE) Output enable time from OE 5 ns tv(A) Data valid time from address change 0 ns tcW Write cycle time 250 ns tw(WE) Write pulse width 150 ns trec(WE) Write recovery time 30 ns tsu(D-WEH) Data setup time for WE 80 ns th(D) Data hold time 30 ns Release date: 12/9/2004 © 2004 iCreate Technologies Corporation iCreate Technologies Corporation reserves the right to change the specification in any manner without notice. Page 9 Create i510x Common memory read and write AC characteristics For the definitions of parameters, please refer to CompactFlash Specification Rev. 2.1. Symbol Parameter Min. Max. Unit ta(OE) Output Enable access time 125 ns tdis(OE) Output disable time from OE 100 ns tsu(A) Address setup time 30 ns th(A) Address hold time 20 ns tsu(CE) Card Enable setup time 0 ns th(CE) Card Enable hold time 20 ns tw(WT) Wait width time tw(WE) Write pulse time 150 ns tsu(D-WEH) Data setup time for WE 80 ns th(D) Data hold time 30 ns trec(WE) Write recover time 30 ns tv(WT-OE) Wait delay falling from OE 35 ns tv(D-WT) Data setup for wait release 0 Ns tv(WT-WE1) Wait delay falling from WE 35 ns tv(WT-WE2) WE high from wait release 3000 0 ns ns I/O access read and write AC characteristics For the definitions of parameters, please refer to CompactFlash Specification Rev. 2.1. Symbol Parameter td(IORD) Data delay after IORD th(IORD) Data hold time following IORD tw(IORD) Min. Max. Unit 100 ns 0 ns IORD pulse width 165 ns tsuA(IORD) Address setup time for IORD 70 ns thA(IORD) Address hold time from IORD 20 ns tsuCE(IORD) Card Enable setup time for IORD 5 ns thCE(IORD) Card Enable hold time from IORD 20 ns tsuREG(IORD) REG setup time for IORD 5 ns thREG(IORD) REG hold time from IORD 0 ns tdfINP(IORD) INPACK delay falling from IORD 0 tdrINP(IORD) 45 ns INPACK delay rising from IORD 45 ns tdfIO16(IORD) IOIS16 delay falling from address 35 ns tdrIO16(IORD) IOIS16 delay rising from address 35 ns tdWT(IORD) Wait delay falling from IORD 35 ns Page 10 Release date: 12/9/2004 © 2004 iCreate Technologies Corporation iCreate Technologies Corporation reserves the right to change the specification in any manner without notice. Create i510x td(WT) Data delay from wait rising 0 tsu(IOWR) Data setup time for IOWR 60 ns th(IOWR) Data hold time from IOWR 30 ns tw(IOWR) IOWR pulse width 165 ns tsuA(IOWR) Address setup time for IOWR 70 ns thA(IOWR) Address hold time from IOWR 20 ns tsuCE(IOWR) Card Enable setup time for IOWR 5 ns thCE(IOWR) Card Enable hold time from IOWR 20 ns tsuREG(IOWR) REG setup time for IOWR 5 ns thREG(IOWR) REG hold time from IOWR 0 ns tdWT(IOWR) Wait delay falling from IOWR tdrIOWR(WT) IOWR high from wait high tw(WT) Wait width time 35 0 ns ns ns 3000 ns True-IDE mode I/O access read and write AC characteristics For the definitions of parameters, please refer to CompactFlash Specification Rev. 2.1. Symbol Parameter Min. Max. Unit t0 Cycle time 120 ns t1 Address valid to IORD/IOWR setup 25 ns t2 IORD/IOWR 70 ns t2 IORD/IOWR register (8bit) 70 ns t3 IOWR data setup 20 ns t4 IOWR data hold 10 ns t5 IORD data setup 20 ns t6 IORD data hold 5 ns t6Z t9 IORD data tri-state 30 ns IORD/IOWR to address valid hold 10 ns Read data valid to IORDY active, if IORDY initially low after tA 0 ns tA IORDY setup time 35 ns tB IORDY pulse width tC IORDY assertion to release tRD 1250 ns 5 ns Read/write timing for NAND type flash For the definition of parameters, please refer to Toshiba flash datasheet. Release date: 12/9/2004 © 2004 iCreate Technologies Corporation iCreate Technologies Corporation reserves the right to change the specification in any manner without notice. Page 11 Create i510x Symbol Parameter Min. Max. Unit tCLS FCLE setup time 0 ns tCLH FCLE hold time 10 ns tCS FCE# setup time 0 ns tCH FCE# hold time 10 ns tCEH FCE# high hold time 100 ns tWP FWE# pulse width 25 ns tALS FALE setup time 0 ns tALH FALE hold time 10 ns tDS Data Setup time 20 ns tDH Data hold time 10 ns tWH FWE# high hold time 15 ns tWW FWP high to FWE# low 100 ns tRR Ready-to-FRE# Falling edge 20 ns tRP FRE# pulse width 25 ns tREH FRE# high hold time 15 ns tRHW FRE# high to FWE# low 0 ns tWHC FWE# high to FCE# low 30 ns tWHR FWE# high to FRE# low 60 ns tAR FALE low to FRE# low 10 ns tCLR FCLE low to FRE# low 10 ns Page 12 Release date: 12/9/2004 © 2004 iCreate Technologies Corporation iCreate Technologies Corporation reserves the right to change the specification in any manner without notice. Create i510x 5. Package dimensions 100 Pin package Release date: 12/9/2004 © 2004 iCreate Technologies Corporation iCreate Technologies Corporation reserves the right to change the specification in any manner without notice. Page 13 i510x Create 128 Pin package Page 14 Release date: 12/9/2004 © 2004 iCreate Technologies Corporation iCreate Technologies Corporation reserves the right to change the specification in any manner without notice.