PL611-31-A-D Datasheet 12-1-2009

(Preliminary)
PL611-31-A/B/C/D
Application Specific Standard Clock (ASSC) for HD Video
FEATURES
PIN CONFIGURATION
XIN/FIN
1
GND
2
CLK0
3
CLK1
4
PL611-31-X
• Advanced low noise PLL design
• Very low Jitter and Phase Noise (< 50ps Pk-Pk typical)
• Complementary LVCMOS outputs to drive LVPECL and
LVDS inputs.
• Output Frequency (Selectable using FSEL):
o PL611-31-A/B 148.50MHz/148.35164MHz
o PL611-31-C/D 74.25MHz/74.17582MHz
• Input Frequency:
o PL611-31-A/C 27MHz Reference Clock
o PL611-31-B/D 27MHz Fundamental Crystal
• Accepts <1.0V reference signal input voltage
• Single 2.5V ~ 3.3V ± 10% power supply
• Operating temperature range from -40°C to 85°C
• Available in 8-pin MSOP/SOP and 6-pin SOT23
GREEN/RoHS compliant packages.
8
XOUT
7
FSEL
6
DNC
5
VDD
6
CLK0
5
VDD
4
FSEL
(M)SOP-8L
1
GND
2
FIN
3
PL611-31-A/C
CLK1
SOT23-6L
DESCRIPTION
The PL611-31A/B/C/D are Application Specific Standard Clocks (ASSC) and members of PhaseLink’s PicoPLL
Programmable product family. Designed to fit in a small 8-pin MSOP, 8-pin SOP or 6-pin SOT23 (-31-A&C only)
package for high performance applications, the PL611-31-A/B/C/D provide very low jitter and power consumption
while offering 2 selectable clock outputs using the Frequency Switching (FSEL) feature. The complementary
LVCMOS outputs can be used to drive LVCMOS, LVPECL or LVDS inputs. The PL611-31-A/B/C/D are excellent
choices for HD Video designs that need to support both US and European standards. For applications requiring
alternate configurations to the ones shown, please refer to the PL611 programmable products on our website.
PRODUCT SELECTOR TABLE
Part Number
Input
FSEL State
CLK0/CLK1
Output Frequency (MHz)
PL611-31-A
27MHz
Reference Clock
1
148.50
0
148.35164
PL611-31-B
27MHz Crystal
1
148.50
0
148.35164
PL611-31-C
27MHz
Reference Clock
1
74.25
0
74.17582
PL611-31-D
27MHz Crystal
1
74.25
0
74.17582
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/01/09 Page 1
(Preliminary)
PL611-31-A/B/C/D
Application Specific Standard Clock (ASSC) for HD Video
BLOCK DIAGRAM
XIN / FIN
XOUT
CLK0
Xtal
Osc
PLL
CLK1
FSEL
PIN DESCRIPTION
Name
Package Pin #
Type
Description
(M)SOP-8L
SOT23-6L
XIN/FIN
1
3
I
GND
2
2
P
27MHz fundamental crystal or reference clock input.
FIN only for SOT23-6L package.
GND connection.
CLK0
3
6
O
LVCMOS clock output.
CLK1
4
1
O
Complementary LVCMOS clock output.
VDD
5
5
P
VDD connection (2.25~3.63V).
DNC
6
-
-
FSEL
7
4
B
XOUT
8
-
O
Do no connect.
Frequency Selection (FSEL) input pin. This pin has an
internal 60KΩ pull up resistor. See the PRODUCT
SELECTOR TABLE on page 1 for available options.
Crystal output pin. Do Not Connect when using
reference clock input on pin 1.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/01/09 Page 2
(Preliminary)
PL611-31-A/B/C/D
Application Specific Standard Clock (ASSC) for HD Video
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
V DD
-0.5
4.6
V
Input Voltage Range
VI
-0.5
V DD +0.5
V
Output Voltage Range
VO
-0.5
V DD +0.5
V
Supply Voltage Range
Data Retention @ 85º C
10
Years
260
°C
-65
150
°C
-40
+85
°C
Soldering Temperature (Green Package)
Storage Temperature
TS
Ambient Operating Temperature*
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device
and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above
the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only.
AC SPECIFICATIONS
PARAMETERS
Crystal Input Frequency
CONDITIONS
MIN.
Fundamental Crystal
Input (FIN) Frequency
Input (FIN) Signal Amplitude
TYP.
MAX.
UNITS
27
MHz
27
MHz
0.9
VDD
Vpp
10
ms
2
ppm
Settling Time
At power-up (V DD < 2.25V)
VDD Sensitivity
Frequency vs. V DD +/-10%
Output Rise Time
15pF Load, 10/90%V DD , 3.3V
1.0
1.5
ns
Output Fall Time
15pF Load, 90/10%V DD , 3.3V
1.0
1.5
ns
Duty Cycle
At V DD /2
50
55
%
Max. output skew between clocks
Equal loading (15 pF)
200
ps
Period Jitter, peak-to-peak
(10,000 samples measured)
With capacitive decoupling between V DD
and GND.
-2
45
45
ps
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/01/09 Page 3
(Preliminary)
PL611-31-A/B/C/D
Application Specific Standard Clock (ASSC) for HD Video
DC SPECIFICATIONS
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
20
mA
3.63
V
0.4
V
PL611-31-A, 3.3V, No Load
Supply Current,
Dynamic
I DD
PL611-31-B, 3.3V, No Load
PL611-31-C, 3.3V, No Load
PL611-31-D, 3.3V, No Load
Operating Voltage
V DD
2.25
Output Low Voltage
V OL
I OL = +4mA
Output High Voltage
V OH
I OH = -4mA
Output Current
I OHD
V OL = 0.4V, V OH = 2.4V
V DD – 0.4
V
24
mA
CRYSTAL SPECIFICATIONS (PL611-31-B/D Only)
PARAMETERS
Fundamental Crystal Resonator Frequency
Crystal Loading Rating
SYMBOL
MIN.
TYP.
MAX.
UNITS
F XIN
27
MHz
C L (xtal)
18
pF
Maximum Sustainable Drive Level
500
Operating Drive Level
µW
µW
100
Crystal Shunt Capacitance
C0
6
pF
Effective Series Resistance
RS
30
Ω
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/01/09 Page 4
(Preliminary)
PL611-31-A/B/C/D
Application Specific Standard Clock (ASSC) for HD Video
TERMINATION FOR LVPECL AND LVDS INPUTS
Figure 1 below describes how to terminate the complementary LVCMOS outputs of PhaseLink’s PL611-31A/B/C/D ASSC clock for use with LVPECL or LVDS inputs.
+3.3V
LVCMOS Output
R1
50? line
R2
Input
R3
Complementary
LVCMOS Output
R1
50? line
3.3V
0V
R3
R2
+3.3V
Complementary
Input
LVPECL LVDS
2.35V 1.40V
1.59V 1.10V
Component selection
For LVPECL input For LVDS input
Notes:
Place R1 as close to the LVCMOS outputs as
possible.
R1 = 130?
R2 = 82?
R3 = 130?
Place R2 and R3 as close to the LVPECL/LVDS
inputs as possible.
R1 = 360?
R2 = 82?
R3 = 130?
Figure 1
The above layout allows the PL611-31 to drive either LVPECL or LVDS inputs by simply changing the value of R1.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/01/09 Page 5
(Preliminary)
PL611-31-A/B/C/D
Application Specific Standard Clock (ASSC) for HD Video
PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT)
MSOP-8L
Symbol
A
A1
A2
B
C
D
E
H
L
e
Dimension in MM
Min.
Max.
--1.10
0.05
0.15
0.81
0.91
0.25
0.40
0.13
0.23
2.90
3.10
2.90
3.10
4.90 BSC
0.445
0.648
0.65 BSC
E
H
D
A2 A
A1
C
L
b
e
SOP-8L
Symbol
A
A1
A2
B
C
D
E
H
L
e
Dimension in MM
Min.
Max.
1.35
1.75
0.10
0.25
1.25
1.50
0.33
0.53
0.19
0.27
4.80
5.00
3.80
4.00
5.80
6.20
0.40
0.89
1.27 BSC
E
H
D
A2 A
A1
C
L
b
e
SOT23-6L
Symbol
A
A1
A2
b
c
D
E
H
L
e
Dimension in MM
Min.
Max.
1.05
1.35
0.05
0.15
1.00
1.20
0.30
0.50
0.08
0.20
2.80
3.00
1.50
1.70
2.60
3.0
0.35
0.55
0.95 BSC
Pin1 Dot
E
H
D
A2 A
A1
C
e
b
L
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/01/09 Page 6
(Preliminary)
PL611-31-A/B/C/D
Application Specific Standard Clock (ASSC) for HD Video
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Part number, Package type and Operating temperature range
PL611-31-X
X X-R
PART NUMBER
NONE= TUBE
R=TAPE and REEL
DEVICE CONFIGURATION
See Product Selector Table on page 1
PACKAGE TYPE
M=MSOP-8L
S=SOP-8L
T=SOT23-6L
Part / Order Number
TEMPERATURE
C=COMMERCIAL (0°C TO 70°C)
I = INDUSTRIAL (-40°C TO 85°C)
Marking
PL611-31-XMC
C4X
LLL
PL611-31-XMC-R
PL611-31-XSC
PL611-31-XSC-R
PL611-31-XTC-R
(A & C versions only)
P611-31
X
LLLLL
C4X
LLL
Package Option
8-Pin MSOP (Tube)
8-Pin MSOP (Tape and Reel)
8-Pin SOP (Tube)
8-Pin SOP (Tape and Reel)
6-Pin SOT23 (Tape and Reel)
Note: LLL / LLLLL designate Production Lot.
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information
furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the
express written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/01/09 Page 7