RD30LDT595 8–bit Serial–in Parallel–out LED Driver IC REJ03D0906-0200 Rev.2.00 Jun 16, 2008 Description The RD30LDT595 has eight edge trigger D–type Flip–Flops with eight latches in 16–pin package. Data is input to the serial data input and the clock pulse is input to the clock input. When the clock is changed from ”L” to ”H”, the signal of the data input enters an internal shift register. The data of the shift register is shifted one by one. In addition, output load circuit is added so that power supply prevents a wrong action in on/off. When Vcc is less than a fixed level, the output (Q1 to Q8) compulsorily is off state. Low–voltage and high–speed operation is suitable for battery–powered product (e.g., notebook computers), and the low–power consumption extends the battery life. Features • • • • • • Supply voltage range : 4.5 to 5.5 V, VO = 30V Output current : IO = 100 mA (@VCC = 5 V) All the logical input has hysteresis voltage for the slow transition. Input with pull-up resistance. (Enable, Latch terminal) Input with pull-down resistance. (CLK, S-in terminal) Ordering Information Part Name Package Type RD30LDT595PT0 DILP-16 pin RD30LDT595FPH0 SOP-16 pin Note: Package Code (Previous Code) PRDP0016AE-B (DP-16FV) PRSP0016DH-B (FP-16DAV) Package Abbreviation Taping Abbreviation (Quantity) P T (1,000 pcs/reel) 0 (Ni/Pd/Au) FP H (2,000 pcs/reel) 0 (Ni/Pd/Au) Please consult the sales office for the above package availability. Pin Arrangement CLK 1 16 Q1 S-in 2 15 Q2 GND 3 14 Q3 VCC 4 13 Q4 S-out 5 12 Q5 Latch 6 11 Q6 Enable 7 10 Q7 GND 8 9 Q8 (Top view) REJ03D0906-0200 Rev.2.00, Jun 16, 2008 Page 1 of 7 Surface Treatment RD30LDT595 Logic Diagram VCC S-in CLK D L Q D D L Q D Output wrong action protection circuit Q1 CK Q VCC Latch Q8 VCC CK Q Enable S-out Function Table Inputs CLK *1 IN IN IN IN IN S-in L L H H H *1 Outputs Latch L H L H H Enable L L L L H IN : Input the following signal in CLK 1 2 7 8 H : High level L : Low level Z : High impedance t - 1 : Output level before the indicated steady state input conditions were established. REJ03D0906-0200 Rev.2.00, Jun 16, 2008 Page 2 of 7 Q1 to Q8 t-1 Z t-1 L Z S-out L L H H H RD30LDT595 Absolute Maximum Ratings Item Supply voltage range Input voltage range Symbol VCC VI Output voltage range *1, VO Continuous output current IO Maximum power dissipation *2 at Ta = 25°C (in still air) Pd Storage temperature Ratings –0.5 to 7 –0.5 to VCC + 0.5 –0.5 to 30 –0.5 to VCC + 0.5 100 1.19 0.79 –65 to 150 Tstg Unit V V V V mA W Test Conditions Output : Z (OFF) S-out VO = 0 to VCC DILP SOP °C Notes: The absolute maximum ratings are values which must not individually be exceeded, and furthermore no two of which may be realized at the same time. 1. This value is limited to 30 V maximum. 2. The maximum package power dissipation was calculated using a junction temperature of 150°C. Recommended Operating Conditions Item Supply voltage range Output voltage range Symbol VCC VO Output current (per pin) IO Operating free-air temperature Ta Note: Min 4.5 — 0 Max 5.5 30 100 Unit V V mA 0 –40 100 85 mA °C Conditions Q1 to Q8 : Z (OFF) DILP Duty cycle ≤ 100% SOP Duty cycle ≤ 60% Q1 to Q8 : ON Unused or floating inputs must be held high or low. Electrical Characteristic Item Symbol VCC (V) * Ta = 25°C Ta = –40 to 85°C Min Typ Max Min Typ Max 2.0 — VCC 2.0 — VCC Unit Test condition VIH 4.5 to 5.5 VIL 4.5 to 5.5 0 — 0.8 0 — 0.8 V IIH 5.5 — — 25 — — 30 µA VIH = 5.5 V IIL 5.5 — — –25 — — –30 µA VIL = 0 V VOH 5.0 4.9 — — 4.9 — — V IOH = –1 µA VOL 5.0 — — 0.1 — — 0.1 V IOL = 1 µA Output voltage (Q1 to Q8) VOL 5.0 — — 0.55 — — 0.77 V IOL = 100 mA Output leakage current IOLK 5.5 — — 50 — — 100 µA VO = 30 V (Output : Z (OFF)) ICC1 5.5 — — 300 — — 500 µA Input : Open All driver output : OFF ICC2 5.5 — — 300 — — 500 µA Driver output one circuit : ON VT+ — 2.9 3.4 3.9 2.6 3.4 4.2 V VT- — 2.6 3.1 3.6 2.3 3.1 3.9 V Input voltage Input current Output voltage (S-out) Quiescent supply current Driver output wrong action protection voltage Note: V For conditions shown as Min or Max, use the appropriate values under recommended operating conditions. REJ03D0906-0200 Rev.2.00, Jun 16, 2008 Page 3 of 7 RD30LDT595 Timing Characteristics (VCC = 5 V, CL = 15 pF, RL (S-out) = ∞, RL (Qn) = 100 Ω, tr = tf = 20 ns) Ta = 25°C Typ Max Ta = –40 to 85°C Min Typ Max Item Symbol Maximum clock frequency fmax — — 12.5 — — 12.5 MHz Pulse width Pulse width Setup time Hold time Setup time Clock pulse rise time Clock pulse fall time tW tW tsu th tsu tr tf 30 30 30 20 60 — — — — — — — — — — — — — — 500 500 30 30 30 20 60 — — — — — — — — — — — — — — 500 500 ns ns ns ns ns ns ns Min Unit Test condition Duty cycle = 45 % to 55 % CLK Latch S-in to CLK S-in to CLK Latch to CLK Switching Characteristics (VCC = 5 V, CL = 15 pF, RL (S-out) = ∞, RL (Qn) = 100 Ω , tr = tf = 20 ns) Item Symbol Propagation delay time Ta = 25°C Ta = –40 to 85°C Min Typ Max Min Typ Max tPLH — — 60 — — 60 tPHL — — 60 — — 60 tPLH — — 70 — — 70 tPHL — — 70 — — 70 tPLH — — 70 — — 70 tPHL — — 70 — — 70 Unit FROM (Input) TO (Output) ns CLK S-out ns CLK Qn ns Enable Qn Test Circuit VCC Pulse Generator Zout = 50 Ω Input Pulse Generator Zout = 50 Ω See Function Table Input RL VCC Output Qn CLK CL S-in Latch Enable RL S-out GND Output CL Notes 1. Input waveform : PRR ≤ 1MHz, Duty Cycle = 50%, tr ≤ 20ns, tf ≤ 20ns 2. CL includes probe and jig capacitance. REJ03D0906-0200 Rev.2.00, Jun 16, 2008 Page 4 of 7 RD30LDT595 Waveforms • Waveform – 1 tf tr 3V 90 % 1.5 V Input CLK 1.5 V 10 % 10 % 0V t PLH t PHL VOH Output S-out 50 % 50 % VOL tf tr 3V 90 % 1.5 V 90 % 1.5 V Input Enable 10 % 10 % t PLH t PLH t PHL t PHL 0V VOH Output Qn 50 % 50 % 50 % 50 % VOL • Waveform – 2 tr , tf 90 % Input S-in 10 % tr , tf 90 % 1.5 V 10 % 90 % 3V 90 % 1.5 V 10 % t su 0V tf tr th 3V 90 % Input CLK 1.5 V 1.5 V 10 % 10 % tw Input Latch t su tf tr 3V 90 % 1.5 V 90 % 1.5 V 10 % 10 % tw Notes 1. Input waveform : PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 20 ns, tf ≤ 20 ns 2. The output are measured one at a time with one transition per measurement. REJ03D0906-0200 Rev.2.00, Jun 16, 2008 Page 5 of 7 0V 0V RD30LDT595 Application Data Duty Cycle − Output Current Characteristics Duty Cycle − Output Current Characteristics • RD30LDT595P • RD30LDT595P Ta=25°C 100 Output Current IOL (mA) Output Current IOL (mA) 80 70 60 50 40 30 • Output current values represent the current per circuit. • Repeated frequency ≥ 10Hz • The value the circle represents the value of the simultaneously - operated circuit. 20 10 0 80 70 60 50 40 30 • Output current values represent the current per circuit. • Repeated frequency ≥ 10Hz • The value the circle represents the value of the simultaneously - operated circuit. 20 10 0 10 20 30 40 50 60 70 80 90 100 0 Duty Cycle (%) Duty Cycle − Output Current Characteristics Duty Cycle − Output Current Characteristics • RD30LDT595FP Ta=25°C 100 Ta=85°C 100 1~8 90 80 70 60 50 40 30 • Output current values represent the current per circuit. • Repeated frequency ≥ 10Hz • The value the circle represents the value of the simultaneously - operated circuit. 20 10 0 10 20 30 40 50 60 70 80 90 100 Duty Cycle (%) REJ03D0906-0200 Rev.2.00, Jun 16, 2008 Page 6 of 7 80 70 60 50 40 30 • Output current values represent the current per circuit. • Repeated frequency ≥ 10Hz • The value the circle represents the value of the simultaneously - operated circuit. 20 10 0 1~5 6 7 8 90 Output Current IOL (mA) Output Current IOL (mA) 10 20 30 40 50 60 70 80 90 100 Duty Cycle (%) • RD30LDT595FP 0 1~8 90 90 0 Ta=85°C 100 1~8 0 10 20 30 40 50 60 70 80 90 100 Duty Cycle (%) RD30LDT595 Package Dimensions JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B Previous Code DP-16FV MASS[Typ.] 1.05g D 9 E 16 1 8 b3 0.89 A1 A Z L Reference Symbol θ bp e e1 D E A A1 bp b3 c θ e Z L c e1 ( Ni/Pd/Au plating ) JEITA Package Code P-SOP16-5.5x10.06-1.27 RENESAS Code PRSP0016DH-B *1 Previous Code FP-16DAV Dimension in Millimeters Min Nom Max 7.62 19.2 20.32 6.3 7.4 5.06 0.51 0.40 0.48 0.56 1.30 0.19 0.25 0.31 0° 15° 2.29 2.54 2.79 1.12 2.54 MASS[Typ.] 0.24g D F 16 NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 9 c HE *2 E bp Index mark Terminal cross section ( Ni/Pd/Au plating ) 1 Z 8 e *3 bp x Reference Dimension in Millimeters Symbol M A L1 A1 θ y L Detail F REJ03D0906-0200 Rev.2.00, Jun 16, 2008 Page 7 of 7 D E A2 A1 A bp b1 c c1 θ HE e x y Z L L1 Min Nom Max 10.06 10.5 5.50 0.00 0.10 0.20 2.20 0.34 0.40 0.46 0.15 0.20 0.25 0° 8° 7.50 7.80 8.00 1.27 0.12 0.15 0.80 0.50 0.70 0.90 1.15 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. 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